drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include "i915_reg.h"
  34 #include "intel_bios.h"
  35 #include <linux/io-mapping.h>
  36
  37 /* General customization:
  38  */
  39
  40 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  41
  42 #define DRIVER_NAME             "i915"
  43 #define DRIVER_DESC             "Intel Graphics"
  44 #define DRIVER_DATE             "20080730"
  45
  46 enum pipe {
  47         PIPE_A = 0,
  48         PIPE_B,
  49 };
  50
  51 enum plane {
  52         PLANE_A = 0,
  53         PLANE_B,
  54 };
  55
  56 #define I915_NUM_PIPE   2
  57
  58 /* Interface history:
  59  *
  60  * 1.1: Original.
  61  * 1.2: Add Power Management
  62  * 1.3: Add vblank support
  63  * 1.4: Fix cmdbuffer path, add heap destroy
  64  * 1.5: Add vblank pipe configuration
  65  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  66  *      - Support vertical blank on secondary display pipe
  67  */
  68 #define DRIVER_MAJOR            1
  69 #define DRIVER_MINOR            6
  70 #define DRIVER_PATCHLEVEL       0
  71
  72 #define WATCH_COHERENCY 0
  73 #define WATCH_BUF       0
  74 #define WATCH_EXEC      0
  75 #define WATCH_LRU       0
  76 #define WATCH_RELOC     0
  77 #define WATCH_INACTIVE  0
  78 #define WATCH_PWRITE    0
  79
  80 #define I915_GEM_PHYS_CURSOR_0 1
  81 #define I915_GEM_PHYS_CURSOR_1 2
  82 #define I915_GEM_PHYS_OVERLAY_REGS 3
  83 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
  84
  85 struct drm_i915_gem_phys_object {
  86         int id;
  87         struct page **page_list;
  88         drm_dma_handle_t *handle;
  89         struct drm_gem_object *cur_obj;
  90 };
  91
  92 typedef struct _drm_i915_ring_buffer {
  93         unsigned long Size;
  94         u8 *virtual_start;
  95         int head;
  96         int tail;
  97         int space;
  98         drm_local_map_t map;
  99         struct drm_gem_object *ring_obj;
 100 } drm_i915_ring_buffer_t;
 101
 102 struct mem_block {
 103         struct mem_block *next;
 104         struct mem_block *prev;
 105         int start;
 106         int size;
 107         struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
 108 };
 109
 110 struct opregion_header;
 111 struct opregion_acpi;
 112 struct opregion_swsci;
 113 struct opregion_asle;
 114
 115 struct intel_opregion {
 116         struct opregion_header *header;
 117         struct opregion_acpi *acpi;
 118         struct opregion_swsci *swsci;
 119         struct opregion_asle *asle;
 120         int enabled;
 121 };
 122
 123 struct drm_i915_master_private {
 124         drm_local_map_t *sarea;
 125         struct _drm_i915_sarea *sarea_priv;
 126 };
 127 #define I915_FENCE_REG_NONE -1
 128
 129 struct drm_i915_fence_reg {
 130         struct drm_gem_object *obj;
 131 };
 132
 133 struct sdvo_device_mapping {
 134         u8 dvo_port;
 135         u8 slave_addr;
 136         u8 dvo_wiring;
 137         u8 initialized;
 138 };
 139
 140 struct drm_i915_error_state {
 141         u32 eir;
 142         u32 pgtbl_er;
 143         u32 pipeastat;
 144         u32 pipebstat;
 145         u32 ipeir;
 146         u32 ipehr;
 147         u32 instdone;
 148         u32 acthd;
 149         u32 instpm;
 150         u32 instps;
 151         u32 instdone1;
 152         u32 seqno;
 153         struct timeval time;
 154 };
 155
 156 struct drm_i915_display_funcs {
 157         void (*dpms)(struct drm_crtc *crtc, int mode);
 158         bool (*fbc_enabled)(struct drm_crtc *crtc);
 159         void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
 160         void (*disable_fbc)(struct drm_device *dev);
 161         int (*get_display_clock_speed)(struct drm_device *dev);
 162         int (*get_fifo_size)(struct drm_device *dev, int plane);
 163         void (*update_wm)(struct drm_device *dev, int planea_clock,
 164                           int planeb_clock, int sr_hdisplay, int pixel_size);
 165         /* clock updates for mode set */
 166         /* cursor updates */
 167         /* render clock increase/decrease */
 168         /* display clock increase/decrease */
 169         /* pll clock increase/decrease */
 170         /* clock gating init */
 171 };
 172
 173 typedef struct drm_i915_private {
 174         struct drm_device *dev;
 175
 176         int has_gem;
 177
 178         void __iomem *regs;
 179
 180         struct pci_dev *bridge_dev;
 181         drm_i915_ring_buffer_t ring;
 182
 183         drm_dma_handle_t *status_page_dmah;
 184         void *hw_status_page;
 185         dma_addr_t dma_status_page;
 186         uint32_t counter;
 187         unsigned int status_gfx_addr;
 188         drm_local_map_t hws_map;
 189         struct drm_gem_object *hws_obj;
 190
 191         struct resource mch_res;
 192
 193         unsigned int cpp;
 194         int back_offset;
 195         int front_offset;
 196         int current_page;
 197         int page_flipping;
 198
 199         wait_queue_head_t irq_queue;
 200         atomic_t irq_received;
 201         /** Protects user_irq_refcount and irq_mask_reg */
 202         spinlock_t user_irq_lock;
 203         /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
 204         int user_irq_refcount;
 205         u32 trace_irq_seqno;
 206         /** Cached value of IMR to avoid reads in updating the bitfield */
 207         u32 irq_mask_reg;
 208         u32 pipestat[2];
 209         /** splitted irq regs for graphics and display engine on IGDNG,
 210             irq_mask_reg is still used for display irq. */
 211         u32 gt_irq_mask_reg;
 212         u32 gt_irq_enable_reg;
 213         u32 de_irq_enable_reg;
 214
 215         u32 hotplug_supported_mask;
 216         struct work_struct hotplug_work;
 217
 218         int tex_lru_log_granularity;
 219         int allow_batchbuffer;
 220         struct mem_block *agp_heap;
 221         unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
 222         int vblank_pipe;
 223
 224         /* For hangcheck timer */
 225 #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */
 226         struct timer_list hangcheck_timer;
 227         int hangcheck_count;
 228         uint32_t last_acthd;
 229
 230         bool cursor_needs_physical;
 231
 232         struct drm_mm vram;
 233
 234         unsigned long cfb_size;
 235         unsigned long cfb_pitch;
 236         int cfb_fence;
 237         int cfb_plane;
 238
 239         int irq_enabled;
 240
 241         struct intel_opregion opregion;
 242
 243         /* LVDS info */
 244         int backlight_duty_cycle;  /* restore backlight to this value */
 245         bool panel_wants_dither;
 246         struct drm_display_mode *panel_fixed_mode;
 247         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 248         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
 249
 250         /* Feature bits from the VBIOS */
 251         unsigned int int_tv_support:1;
 252         unsigned int lvds_dither:1;
 253         unsigned int lvds_vbt:1;
 254         unsigned int int_crt_support:1;
 255         unsigned int lvds_use_ssc:1;
 256         unsigned int edp_support:1;
 257         int lvds_ssc_freq;
 258
 259         struct notifier_block lid_notifier;
 260
 261         int crt_ddc_bus; /* -1 = unknown, else GPIO to use for CRT DDC */
 262         struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
 263         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
 264         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 265
 266         unsigned int fsb_freq, mem_freq;
 267
 268         spinlock_t error_lock;
 269         struct drm_i915_error_state *first_error;
 270         struct work_struct error_work;
 271         struct workqueue_struct *wq;
 272
 273         /* Display functions */
 274         struct drm_i915_display_funcs display;
 275
 276         /* Register state */
 277         bool suspended;
 278         u8 saveLBB;
 279         u32 saveDSPACNTR;
 280         u32 saveDSPBCNTR;
 281         u32 saveDSPARB;
 282         u32 saveRENDERSTANDBY;
 283         u32 saveHWS;
 284         u32 savePIPEACONF;
 285         u32 savePIPEBCONF;
 286         u32 savePIPEASRC;
 287         u32 savePIPEBSRC;
 288         u32 saveFPA0;
 289         u32 saveFPA1;
 290         u32 saveDPLL_A;
 291         u32 saveDPLL_A_MD;
 292         u32 saveHTOTAL_A;
 293         u32 saveHBLANK_A;
 294         u32 saveHSYNC_A;
 295         u32 saveVTOTAL_A;
 296         u32 saveVBLANK_A;
 297         u32 saveVSYNC_A;
 298         u32 saveBCLRPAT_A;
 299         u32 savePIPEASTAT;
 300         u32 saveDSPASTRIDE;
 301         u32 saveDSPASIZE;
 302         u32 saveDSPAPOS;
 303         u32 saveDSPAADDR;
 304         u32 saveDSPASURF;
 305         u32 saveDSPATILEOFF;
 306         u32 savePFIT_PGM_RATIOS;
 307         u32 saveBLC_HIST_CTL;
 308         u32 saveBLC_PWM_CTL;
 309         u32 saveBLC_PWM_CTL2;
 310         u32 saveFPB0;
 311         u32 saveFPB1;
 312         u32 saveDPLL_B;
 313         u32 saveDPLL_B_MD;
 314         u32 saveHTOTAL_B;
 315         u32 saveHBLANK_B;
 316         u32 saveHSYNC_B;
 317         u32 saveVTOTAL_B;
 318         u32 saveVBLANK_B;
 319         u32 saveVSYNC_B;
 320         u32 saveBCLRPAT_B;
 321         u32 savePIPEBSTAT;
 322         u32 saveDSPBSTRIDE;
 323         u32 saveDSPBSIZE;
 324         u32 saveDSPBPOS;
 325         u32 saveDSPBADDR;
 326         u32 saveDSPBSURF;
 327         u32 saveDSPBTILEOFF;
 328         u32 saveVGA0;
 329         u32 saveVGA1;
 330         u32 saveVGA_PD;
 331         u32 saveVGACNTRL;
 332         u32 saveADPA;
 333         u32 saveLVDS;
 334         u32 savePP_ON_DELAYS;
 335         u32 savePP_OFF_DELAYS;
 336         u32 saveDVOA;
 337         u32 saveDVOB;
 338         u32 saveDVOC;
 339         u32 savePP_ON;
 340         u32 savePP_OFF;
 341         u32 savePP_CONTROL;
 342         u32 savePP_DIVISOR;
 343         u32 savePFIT_CONTROL;
 344         u32 save_palette_a[256];
 345         u32 save_palette_b[256];
 346         u32 saveDPFC_CB_BASE;
 347         u32 saveFBC_CFB_BASE;
 348         u32 saveFBC_LL_BASE;
 349         u32 saveFBC_CONTROL;
 350         u32 saveFBC_CONTROL2;
 351         u32 saveIER;
 352         u32 saveIIR;
 353         u32 saveIMR;
 354         u32 saveCACHE_MODE_0;
 355         u32 saveD_STATE;
 356         u32 saveDSPCLK_GATE_D;
 357         u32 saveMI_ARB_STATE;
 358         u32 saveSWF0[16];
 359         u32 saveSWF1[16];
 360         u32 saveSWF2[3];
 361         u8 saveMSR;
 362         u8 saveSR[8];
 363         u8 saveGR[25];
 364         u8 saveAR_INDEX;
 365         u8 saveAR[21];
 366         u8 saveDACMASK;
 367         u8 saveCR[37];
 368         uint64_t saveFENCE[16];
 369         u32 saveCURACNTR;
 370         u32 saveCURAPOS;
 371         u32 saveCURABASE;
 372         u32 saveCURBCNTR;
 373         u32 saveCURBPOS;
 374         u32 saveCURBBASE;
 375         u32 saveCURSIZE;
 376         u32 saveDP_B;
 377         u32 saveDP_C;
 378         u32 saveDP_D;
 379         u32 savePIPEA_GMCH_DATA_M;
 380         u32 savePIPEB_GMCH_DATA_M;
 381         u32 savePIPEA_GMCH_DATA_N;
 382         u32 savePIPEB_GMCH_DATA_N;
 383         u32 savePIPEA_DP_LINK_M;
 384         u32 savePIPEB_DP_LINK_M;
 385         u32 savePIPEA_DP_LINK_N;
 386         u32 savePIPEB_DP_LINK_N;
 387
 388         struct {
 389                 struct drm_mm gtt_space;
 390
 391                 struct io_mapping *gtt_mapping;
 392                 int gtt_mtrr;
 393
 394                 /**
 395                  * Membership on list of all loaded devices, used to evict
 396                  * inactive buffers under memory pressure.
 397                  *
 398                  * Modifications should only be done whilst holding the
 399                  * shrink_list_lock spinlock.
 400                  */
 401                 struct list_head shrink_list;
 402
 403                 /**
 404                  * List of objects currently involved in rendering from the
 405                  * ringbuffer.
 406                  *
 407                  * Includes buffers having the contents of their GPU caches
 408                  * flushed, not necessarily primitives.  last_rendering_seqno
 409                  * represents when the rendering involved will be completed.
 410                  *
 411                  * A reference is held on the buffer while on this list.
 412                  */
 413                 spinlock_t active_list_lock;
 414                 struct list_head active_list;
 415
 416                 /**
 417                  * List of objects which are not in the ringbuffer but which
 418                  * still have a write_domain which needs to be flushed before
 419                  * unbinding.
 420                  *
 421                  * last_rendering_seqno is 0 while an object is in this list.
 422                  *
 423                  * A reference is held on the buffer while on this list.
 424                  */
 425                 struct list_head flushing_list;
 426
 427                 /**
 428                  * LRU list of objects which are not in the ringbuffer and
 429                  * are ready to unbind, but are still in the GTT.
 430                  *
 431                  * last_rendering_seqno is 0 while an object is in this list.
 432                  *
 433                  * A reference is not held on the buffer while on this list,
 434                  * as merely being GTT-bound shouldn't prevent its being
 435                  * freed, and we'll pull it off the list in the free path.
 436                  */
 437                 struct list_head inactive_list;
 438
 439                 /** LRU list of objects with fence regs on them. */
 440                 struct list_head fence_list;
 441
 442                 /**
 443                  * List of breadcrumbs associated with GPU requests currently
 444                  * outstanding.
 445                  */
 446                 struct list_head request_list;
 447
 448                 /**
 449                  * We leave the user IRQ off as much as possible,
 450                  * but this means that requests will finish and never
 451                  * be retired once the system goes idle. Set a timer to
 452                  * fire periodically while the ring is running. When it
 453                  * fires, go retire requests.
 454                  */
 455                 struct delayed_work retire_work;
 456
 457                 uint32_t next_gem_seqno;
 458
 459                 /**
 460                  * Waiting sequence number, if any
 461                  */
 462                 uint32_t waiting_gem_seqno;
 463
 464                 /**
 465                  * Last seq seen at irq time
 466                  */
 467                 uint32_t irq_gem_seqno;
 468
 469                 /**
 470                  * Flag if the X Server, and thus DRM, is not currently in
 471                  * control of the device.
 472                  *
 473                  * This is set between LeaveVT and EnterVT.  It needs to be
 474                  * replaced with a semaphore.  It also needs to be
 475                  * transitioned away from for kernel modesetting.
 476                  */
 477                 int suspended;
 478
 479                 /**
 480                  * Flag if the hardware appears to be wedged.
 481                  *
 482                  * This is set when attempts to idle the device timeout.
 483                  * It prevents command submission from occuring and makes
 484                  * every pending request fail
 485                  */
 486                 atomic_t wedged;
 487
 488                 /** Bit 6 swizzling required for X tiling */
 489                 uint32_t bit_6_swizzle_x;
 490                 /** Bit 6 swizzling required for Y tiling */
 491                 uint32_t bit_6_swizzle_y;
 492
 493                 /* storage for physical objects */
 494                 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
 495         } mm;
 496         struct sdvo_device_mapping sdvo_mappings[2];
 497         /* indicate whether the LVDS_BORDER should be enabled or not */
 498         unsigned int lvds_border_bits;
 499
 500         /* Reclocking support */
 501         bool render_reclock_avail;
 502         bool lvds_downclock_avail;
 503         struct work_struct idle_work;
 504         struct timer_list idle_timer;
 505         bool busy;
 506         u16 orig_clock;
 507 } drm_i915_private_t;
 508
 509 /** driver private structure attached to each drm_gem_object */
 510 struct drm_i915_gem_object {
 511         struct drm_gem_object *obj;
 512
 513         /** Current space allocated to this object in the GTT, if any. */
 514         struct drm_mm_node *gtt_space;
 515
 516         /** This object's place on the active/flushing/inactive lists */
 517         struct list_head list;
 518
 519         /** This object's place on the fenced object LRU */
 520         struct list_head fence_list;
 521
 522         /**
 523          * This is set if the object is on the active or flushing lists
 524          * (has pending rendering), and is not set if it's on inactive (ready
 525          * to be unbound).
 526          */
 527         int active;
 528
 529         /**
 530          * This is set if the object has been written to since last bound
 531          * to the GTT
 532          */
 533         int dirty;
 534
 535         /** AGP memory structure for our GTT binding. */
 536         DRM_AGP_MEM *agp_mem;
 537
 538         struct page **pages;
 539         int pages_refcount;
 540
 541         /**
 542          * Current offset of the object in GTT space.
 543          *
 544          * This is the same as gtt_space->start
 545          */
 546         uint32_t gtt_offset;
 547
 548         /**
 549          * Fake offset for use by mmap(2)
 550          */
 551         uint64_t mmap_offset;
 552
 553         /**
 554          * Fence register bits (if any) for this object.  Will be set
 555          * as needed when mapped into the GTT.
 556          * Protected by dev->struct_mutex.
 557          */
 558         int fence_reg;
 559
 560         /** How many users have pinned this object in GTT space */
 561         int pin_count;
 562
 563         /** Breadcrumb of last rendering to the buffer. */
 564         uint32_t last_rendering_seqno;
 565
 566         /** Current tiling mode for the object. */
 567         uint32_t tiling_mode;
 568         uint32_t stride;
 569
 570         /** Record of address bit 17 of each page at last unbind. */
 571         long *bit_17;
 572
 573         /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
 574         uint32_t agp_type;
 575
 576         /**
 577          * If present, while GEM_DOMAIN_CPU is in the read domain this array
 578          * flags which individual pages are valid.
 579          */
 580         uint8_t *page_cpu_valid;
 581
 582         /** User space pin count and filp owning the pin */
 583         uint32_t user_pin_count;
 584         struct drm_file *pin_filp;
 585
 586         /** for phy allocated objects */
 587         struct drm_i915_gem_phys_object *phys_obj;
 588
 589         /**
 590          * Used for checking the object doesn't appear more than once
 591          * in an execbuffer object list.
 592          */
 593         int in_execbuffer;
 594
 595         /**
 596          * Advice: are the backing pages purgeable?
 597          */
 598         int madv;
 599 };
 600
 601 /**
 602  * Request queue structure.
 603  *
 604  * The request queue allows us to note sequence numbers that have been emitted
 605  * and may be associated with active buffers to be retired.
 606  *
 607  * By keeping this list, we can avoid having to do questionable
 608  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
 609  * an emission time with seqnos for tracking how far ahead of the GPU we are.
 610  */
 611 struct drm_i915_gem_request {
 612         /** GEM sequence number associated with this request. */
 613         uint32_t seqno;
 614
 615         /** Time at which this request was emitted, in jiffies. */
 616         unsigned long emitted_jiffies;
 617
 618         /** global list entry for this request */
 619         struct list_head list;
 620
 621         /** file_priv list entry for this request */
 622         struct list_head client_list;
 623 };
 624
 625 struct drm_i915_file_private {
 626         struct {
 627                 struct list_head request_list;
 628         } mm;
 629 };
 630
 631 enum intel_chip_family {
 632         CHIP_I8XX = 0x01,
 633         CHIP_I9XX = 0x02,
 634         CHIP_I915 = 0x04,
 635         CHIP_I965 = 0x08,
 636 };
 637
 638 extern struct drm_ioctl_desc i915_ioctls[];
 639 extern int i915_max_ioctl;
 640 extern unsigned int i915_fbpercrtc;
 641 extern unsigned int i915_powersave;
 642
 643 extern void i915_save_display(struct drm_device *dev);
 644 extern void i915_restore_display(struct drm_device *dev);
 645 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
 646 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
 647
 648                                 /* i915_dma.c */
 649 extern void i915_kernel_lost_context(struct drm_device * dev);
 650 extern int i915_driver_load(struct drm_device *, unsigned long flags);
 651 extern int i915_driver_unload(struct drm_device *);
 652 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
 653 extern void i915_driver_lastclose(struct drm_device * dev);
 654 extern void i915_driver_preclose(struct drm_device *dev,
 655                                  struct drm_file *file_priv);
 656 extern void i915_driver_postclose(struct drm_device *dev,
 657                                   struct drm_file *file_priv);
 658 extern int i915_driver_device_is_agp(struct drm_device * dev);
 659 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
 660                               unsigned long arg);
 661 extern int i915_emit_box(struct drm_device *dev,
 662                          struct drm_clip_rect *boxes,
 663                          int i, int DR1, int DR4);
 664 extern int i965_reset(struct drm_device *dev, u8 flags);
 665
 666 /* i915_irq.c */
 667 void i915_hangcheck_elapsed(unsigned long data);
 668 extern int i915_irq_emit(struct drm_device *dev, void *data,
 669                          struct drm_file *file_priv);
 670 extern int i915_irq_wait(struct drm_device *dev, void *data,
 671                          struct drm_file *file_priv);
 672 void i915_user_irq_get(struct drm_device *dev);
 673 void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
 674 void i915_user_irq_put(struct drm_device *dev);
 675 extern void i915_enable_interrupt (struct drm_device *dev);
 676
 677 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
 678 extern void i915_driver_irq_preinstall(struct drm_device * dev);
 679 extern int i915_driver_irq_postinstall(struct drm_device *dev);
 680 extern void i915_driver_irq_uninstall(struct drm_device * dev);
 681 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 682                                 struct drm_file *file_priv);
 683 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 684                                 struct drm_file *file_priv);
 685 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
 686 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
 687 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
 688 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
 689 extern int i915_vblank_swap(struct drm_device *dev, void *data,
 690                             struct drm_file *file_priv);
 691 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
 692
 693 void
 694 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
 695
 696 void
 697 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
 698
 699
 700 /* i915_mem.c */
 701 extern int i915_mem_alloc(struct drm_device *dev, void *data,
 702                           struct drm_file *file_priv);
 703 extern int i915_mem_free(struct drm_device *dev, void *data,
 704                          struct drm_file *file_priv);
 705 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
 706                               struct drm_file *file_priv);
 707 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
 708                                  struct drm_file *file_priv);
 709 extern void i915_mem_takedown(struct mem_block **heap);
 710 extern void i915_mem_release(struct drm_device * dev,
 711                              struct drm_file *file_priv, struct mem_block *heap);
 712 /* i915_gem.c */
 713 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
 714                         struct drm_file *file_priv);
 715 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
 716                           struct drm_file *file_priv);
 717 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 718                          struct drm_file *file_priv);
 719 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 720                           struct drm_file *file_priv);
 721 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
 722                         struct drm_file *file_priv);
 723 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
 724                         struct drm_file *file_priv);
 725 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 726                               struct drm_file *file_priv);
 727 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
 728                              struct drm_file *file_priv);
 729 int i915_gem_execbuffer(struct drm_device *dev, void *data,
 730                         struct drm_file *file_priv);
 731 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
 732                        struct drm_file *file_priv);
 733 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
 734                          struct drm_file *file_priv);
 735 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
 736                         struct drm_file *file_priv);
 737 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
 738                             struct drm_file *file_priv);
 739 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
 740                            struct drm_file *file_priv);
 741 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
 742                            struct drm_file *file_priv);
 743 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
 744                            struct drm_file *file_priv);
 745 int i915_gem_set_tiling(struct drm_device *dev, void *data,
 746                         struct drm_file *file_priv);
 747 int i915_gem_get_tiling(struct drm_device *dev, void *data,
 748                         struct drm_file *file_priv);
 749 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 750                                 struct drm_file *file_priv);
 751 void i915_gem_load(struct drm_device *dev);
 752 int i915_gem_init_object(struct drm_gem_object *obj);
 753 void i915_gem_free_object(struct drm_gem_object *obj);
 754 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
 755 void i915_gem_object_unpin(struct drm_gem_object *obj);
 756 int i915_gem_object_unbind(struct drm_gem_object *obj);
 757 void i915_gem_release_mmap(struct drm_gem_object *obj);
 758 void i915_gem_lastclose(struct drm_device *dev);
 759 uint32_t i915_get_gem_seqno(struct drm_device *dev);
 760 bool i915_seqno_passed(uint32_t seq1, uint32_t seq2);
 761 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
 762 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
 763 void i915_gem_retire_requests(struct drm_device *dev);
 764 void i915_gem_retire_work_handler(struct work_struct *work);
 765 void i915_gem_clflush_object(struct drm_gem_object *obj);
 766 int i915_gem_object_set_domain(struct drm_gem_object *obj,
 767                                uint32_t read_domains,
 768                                uint32_t write_domain);
 769 int i915_gem_init_ringbuffer(struct drm_device *dev);
 770 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
 771 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
 772                      unsigned long end);
 773 int i915_gem_idle(struct drm_device *dev);
 774 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
 775 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
 776                                       int write);
 777 int i915_gem_attach_phys_object(struct drm_device *dev,
 778                                 struct drm_gem_object *obj, int id);
 779 void i915_gem_detach_phys_object(struct drm_device *dev,
 780                                  struct drm_gem_object *obj);
 781 void i915_gem_free_all_phys_object(struct drm_device *dev);
 782 int i915_gem_object_get_pages(struct drm_gem_object *obj);
 783 void i915_gem_object_put_pages(struct drm_gem_object *obj);
 784 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
 785
 786 void i915_gem_shrinker_init(void);
 787 void i915_gem_shrinker_exit(void);
 788
 789 /* i915_gem_tiling.c */
 790 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
 791 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
 792 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
 793
 794 /* i915_gem_debug.c */
 795 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
 796                           const char *where, uint32_t mark);
 797 #if WATCH_INACTIVE
 798 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
 799 #else
 800 #define i915_verify_inactive(dev, file, line)
 801 #endif
 802 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
 803 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
 804                           const char *where, uint32_t mark);
 805 void i915_dump_lru(struct drm_device *dev, const char *where);
 806
 807 /* i915_debugfs.c */
 808 int i915_debugfs_init(struct drm_minor *minor);
 809 void i915_debugfs_cleanup(struct drm_minor *minor);
 810
 811 /* i915_suspend.c */
 812 extern int i915_save_state(struct drm_device *dev);
 813 extern int i915_restore_state(struct drm_device *dev);
 814
 815 /* i915_suspend.c */
 816 extern int i915_save_state(struct drm_device *dev);
 817 extern int i915_restore_state(struct drm_device *dev);
 818
 819 #ifdef CONFIG_ACPI
 820 /* i915_opregion.c */
 821 extern int intel_opregion_init(struct drm_device *dev, int resume);
 822 extern void intel_opregion_free(struct drm_device *dev, int suspend);
 823 extern void opregion_asle_intr(struct drm_device *dev);
 824 extern void opregion_enable_asle(struct drm_device *dev);
 825 #else
 826 static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
 827 static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
 828 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
 829 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
 830 #endif
 831
 832 /* modesetting */
 833 extern void intel_modeset_init(struct drm_device *dev);
 834 extern void intel_modeset_cleanup(struct drm_device *dev);
 835 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
 836 extern void i8xx_disable_fbc(struct drm_device *dev);
 837 extern void g4x_disable_fbc(struct drm_device *dev);
 838
 839 /**
 840  * Lock test for when it's just for synchronization of ring access.
 841  *
 842  * In that case, we don't need to do it when GEM is initialized as nobody else
 843  * has access to the ring.
 844  */
 845 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do {                 \
 846         if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
 847                 LOCK_TEST_WITH_RETURN(dev, file_priv);                  \
 848 } while (0)
 849
 850 #define I915_READ(reg)          readl(dev_priv->regs + (reg))
 851 #define I915_WRITE(reg, val)     writel(val, dev_priv->regs + (reg))
 852 #define I915_READ16(reg)        readw(dev_priv->regs + (reg))
 853 #define I915_WRITE16(reg, val)  writel(val, dev_priv->regs + (reg))
 854 #define I915_READ8(reg)         readb(dev_priv->regs + (reg))
 855 #define I915_WRITE8(reg, val)   writeb(val, dev_priv->regs + (reg))
 856 #define I915_WRITE64(reg, val)  writeq(val, dev_priv->regs + (reg))
 857 #define I915_READ64(reg)        readq(dev_priv->regs + (reg))
 858 #define POSTING_READ(reg)       (void)I915_READ(reg)
 859
 860 #define I915_VERBOSE 0
 861
 862 #define RING_LOCALS     volatile unsigned int *ring_virt__;
 863
 864 #define BEGIN_LP_RING(n) do {                                           \
 865         int bytes__ = 4*(n);                                            \
 866         if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n));        \
 867         /* a wrap must occur between instructions so pad beforehand */  \
 868         if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \
 869                 i915_wrap_ring(dev);                                    \
 870         if (unlikely (dev_priv->ring.space < bytes__))                  \
 871                 i915_wait_ring(dev, bytes__, __func__);                 \
 872         ring_virt__ = (unsigned int *)                                  \
 873                 (dev_priv->ring.virtual_start + dev_priv->ring.tail);   \
 874         dev_priv->ring.tail += bytes__;                                 \
 875         dev_priv->ring.tail &= dev_priv->ring.Size - 1;                 \
 876         dev_priv->ring.space -= bytes__;                                \
 877 } while (0)
 878
 879 #define OUT_RING(n) do {                                                \
 880         if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));      \
 881         *ring_virt__++ = (n);                                           \
 882 } while (0)
 883
 884 #define ADVANCE_LP_RING() do {                                          \
 885         if (I915_VERBOSE)                                               \
 886                 DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \
 887         I915_WRITE(PRB0_TAIL, dev_priv->ring.tail);                     \
 888 } while(0)
 889
 890 /**
 891  * Reads a dword out of the status page, which is written to from the command
 892  * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 893  * MI_STORE_DATA_IMM.
 894  *
 895  * The following dwords have a reserved meaning:
 896  * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 897  * 0x04: ring 0 head pointer
 898  * 0x05: ring 1 head pointer (915-class)
 899  * 0x06: ring 2 head pointer (915-class)
 900  * 0x10-0x1b: Context status DWords (GM45)
 901  * 0x1f: Last written status offset. (GM45)
 902  *
 903  * The area from dword 0x20 to 0x3ff is available for driver usage.
 904  */
 905 #define READ_HWSP(dev_priv, reg)  (((volatile u32*)(dev_priv->hw_status_page))[reg])
 906 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
 907 #define I915_GEM_HWS_INDEX              0x20
 908 #define I915_BREADCRUMB_INDEX           0x21
 909
 910 extern int i915_wrap_ring(struct drm_device * dev);
 911 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 912
 913 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
 914 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
 915 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
 916 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
 917 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
 918
 919 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
 920 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
 921 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
 922 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
 923                         (dev)->pci_device == 0x27AE)
 924 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
 925                        (dev)->pci_device == 0x2982 || \
 926                        (dev)->pci_device == 0x2992 || \
 927                        (dev)->pci_device == 0x29A2 || \
 928                        (dev)->pci_device == 0x2A02 || \
 929                        (dev)->pci_device == 0x2A12 || \
 930                        (dev)->pci_device == 0x2A42 || \
 931                        (dev)->pci_device == 0x2E02 || \
 932                        (dev)->pci_device == 0x2E12 || \
 933                        (dev)->pci_device == 0x2E22 || \
 934                        (dev)->pci_device == 0x2E32 || \
 935                        (dev)->pci_device == 0x2E42 || \
 936                        (dev)->pci_device == 0x0042 || \
 937                        (dev)->pci_device == 0x0046)
 938
 939 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
 940                         (dev)->pci_device == 0x2A12)
 941
 942 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
 943
 944 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
 945                      (dev)->pci_device == 0x2E12 || \
 946                      (dev)->pci_device == 0x2E22 || \
 947                      (dev)->pci_device == 0x2E32 || \
 948                      (dev)->pci_device == 0x2E42 || \
 949                      IS_GM45(dev))
 950
 951 #define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
 952 #define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
 953 #define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
 954
 955 #define IS_G33(dev)    ((dev)->pci_device == 0x29C2 ||  \
 956                         (dev)->pci_device == 0x29B2 ||  \
 957                         (dev)->pci_device == 0x29D2 ||  \
 958                         (IS_IGD(dev)))
 959
 960 #define IS_IGDNG_D(dev) ((dev)->pci_device == 0x0042)
 961 #define IS_IGDNG_M(dev) ((dev)->pci_device == 0x0046)
 962 #define IS_IGDNG(dev)   (IS_IGDNG_D(dev) || IS_IGDNG_M(dev))
 963
 964 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
 965                       IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
 966                       IS_IGDNG(dev))
 967
 968 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
 969                         IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
 970                         IS_IGD(dev) || IS_IGDNG_M(dev))
 971
 972 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
 973                                 IS_IGDNG(dev))
 974 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 975  * rows, which changed the alignment requirements and fence programming.
 976  */
 977 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
 978                                                       IS_I915GM(dev)))
 979 #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_IGDNG(dev))
 980 #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_IGDNG(dev))
 981 #define SUPPORTS_EDP(dev)               (IS_IGDNG_M(dev))
 982 #define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev) || IS_I965G(dev))
 983 /* dsparb controlled by hw only */
 984 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev))
 985
 986 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev))
 987 #define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev))
 988 #define I915_HAS_FBC(dev) (IS_MOBILE(dev) && \
 989                            (IS_I9XX(dev) || IS_GM45(dev)) && \
 990                            !IS_IGD(dev) && \
 991                            !IS_IGDNG(dev))
 992
 993 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)
 994
 995 #endif