1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <drm/intel-gtt.h>
40 /* General customization:
43 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
45 #define DRIVER_NAME "i915"
46 #define DRIVER_DESC "Intel Graphics"
47 #define DRIVER_DATE "20080730"
59 #define I915_NUM_PIPE 2
61 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
66 * 1.2: Add Power Management
67 * 1.3: Add vblank support
68 * 1.4: Fix cmdbuffer path, add heap destroy
69 * 1.5: Add vblank pipe configuration
70 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
71 * - Support vertical blank on secondary display pipe
73 #define DRIVER_MAJOR 1
74 #define DRIVER_MINOR 6
75 #define DRIVER_PATCHLEVEL 0
77 #define WATCH_COHERENCY 0
81 #define WATCH_PWRITE 0
83 #define I915_GEM_PHYS_CURSOR_0 1
84 #define I915_GEM_PHYS_CURSOR_1 2
85 #define I915_GEM_PHYS_OVERLAY_REGS 3
86 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
88 struct drm_i915_gem_phys_object
{
90 struct page
**page_list
;
91 drm_dma_handle_t
*handle
;
92 struct drm_i915_gem_object
*cur_obj
;
96 struct mem_block
*next
;
97 struct mem_block
*prev
;
100 struct drm_file
*file_priv
; /* NULL: free, -1: heap, other: real files */
103 struct opregion_header
;
104 struct opregion_acpi
;
105 struct opregion_swsci
;
106 struct opregion_asle
;
108 struct intel_opregion
{
109 struct opregion_header
*header
;
110 struct opregion_acpi
*acpi
;
111 struct opregion_swsci
*swsci
;
112 struct opregion_asle
*asle
;
115 #define OPREGION_SIZE (8*1024)
117 struct intel_overlay
;
118 struct intel_overlay_error_state
;
120 struct drm_i915_master_private
{
121 drm_local_map_t
*sarea
;
122 struct _drm_i915_sarea
*sarea_priv
;
124 #define I915_FENCE_REG_NONE -1
126 struct drm_i915_fence_reg
{
127 struct list_head lru_list
;
128 struct drm_i915_gem_object
*obj
;
131 struct sdvo_device_mapping
{
141 struct intel_display_error_state
;
143 struct drm_i915_error_state
{
152 u32 error
; /* gen6+ */
153 u32 bcs_acthd
; /* gen6+ blt engine */
158 u32 vcs_acthd
; /* gen6+ bsd engine */
170 struct drm_i915_error_object
{
174 } *ringbuffer
, *batchbuffer
[2];
175 struct drm_i915_error_buffer
{
188 } *active_bo
, *pinned_bo
;
189 u32 active_bo_count
, pinned_bo_count
;
190 struct intel_overlay_error_state
*overlay
;
191 struct intel_display_error_state
*display
;
194 struct drm_i915_display_funcs
{
195 void (*dpms
)(struct drm_crtc
*crtc
, int mode
);
196 bool (*fbc_enabled
)(struct drm_device
*dev
);
197 void (*enable_fbc
)(struct drm_crtc
*crtc
, unsigned long interval
);
198 void (*disable_fbc
)(struct drm_device
*dev
);
199 int (*get_display_clock_speed
)(struct drm_device
*dev
);
200 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
201 void (*update_wm
)(struct drm_device
*dev
, int planea_clock
,
202 int planeb_clock
, int sr_hdisplay
, int sr_htotal
,
204 /* clock updates for mode set */
206 /* render clock increase/decrease */
207 /* display clock increase/decrease */
208 /* pll clock increase/decrease */
209 /* clock gating init */
212 struct intel_device_info
{
222 u8 is_broadwater
: 1;
226 u8 has_pipe_cxsr
: 1;
228 u8 cursor_needs_physical
: 1;
230 u8 overlay_needs_physical
: 1;
237 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
238 FBC_STOLEN_TOO_SMALL
, /* not enough space to hold compressed buffers */
239 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
240 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
241 FBC_BAD_PLANE
, /* fbc not supported on plane */
242 FBC_NOT_TILED
, /* buffer not tiled */
243 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
247 PCH_IBX
, /* Ibexpeak PCH */
248 PCH_CPT
, /* Cougarpoint PCH */
251 #define QUIRK_PIPEA_FORCE (1<<0)
255 typedef struct drm_i915_private
{
256 struct drm_device
*dev
;
258 const struct intel_device_info
*info
;
265 struct i2c_adapter adapter
;
266 struct i2c_adapter
*force_bit
;
270 struct pci_dev
*bridge_dev
;
271 struct intel_ring_buffer render_ring
;
272 struct intel_ring_buffer bsd_ring
;
273 struct intel_ring_buffer blt_ring
;
276 drm_dma_handle_t
*status_page_dmah
;
277 dma_addr_t dma_status_page
;
279 drm_local_map_t hws_map
;
280 struct drm_i915_gem_object
*pwrctx
;
281 struct drm_i915_gem_object
*renderctx
;
283 struct resource mch_res
;
291 atomic_t irq_received
;
292 /** Protects user_irq_refcount and irq_mask_reg */
293 spinlock_t user_irq_lock
;
295 /** Cached value of IMR to avoid reads in updating the bitfield */
298 /** splitted irq regs for graphics and display engine on Ironlake,
299 irq_mask_reg is still used for display irq. */
301 u32 gt_irq_enable_reg
;
302 u32 de_irq_enable_reg
;
303 u32 pch_irq_mask_reg
;
304 u32 pch_irq_enable_reg
;
306 u32 hotplug_supported_mask
;
307 struct work_struct hotplug_work
;
309 int tex_lru_log_granularity
;
310 int allow_batchbuffer
;
311 struct mem_block
*agp_heap
;
312 unsigned int sr01
, adpa
, ppcr
, dvob
, dvoc
, lvds
;
316 /* For hangcheck timer */
317 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
318 struct timer_list hangcheck_timer
;
321 uint32_t last_instdone
;
322 uint32_t last_instdone1
;
324 unsigned long cfb_size
;
325 unsigned long cfb_pitch
;
326 unsigned long cfb_offset
;
333 struct intel_opregion opregion
;
336 struct intel_overlay
*overlay
;
339 int backlight_level
; /* restore backlight to this value */
340 struct drm_display_mode
*panel_fixed_mode
;
341 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
342 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
344 /* Feature bits from the VBIOS */
345 unsigned int int_tv_support
:1;
346 unsigned int lvds_dither
:1;
347 unsigned int lvds_vbt
:1;
348 unsigned int int_crt_support
:1;
349 unsigned int lvds_use_ssc
:1;
360 struct edp_power_seq pps
;
362 bool no_aux_handshake
;
364 struct notifier_block lid_notifier
;
367 struct drm_i915_fence_reg fence_regs
[16]; /* assume 965 */
368 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
369 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
371 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
373 spinlock_t error_lock
;
374 struct drm_i915_error_state
*first_error
;
375 struct work_struct error_work
;
376 struct completion error_completion
;
377 struct workqueue_struct
*wq
;
379 /* Display functions */
380 struct drm_i915_display_funcs display
;
382 /* PCH chipset type */
383 enum intel_pch pch_type
;
385 unsigned long quirks
;
410 u32 saveTRANS_HTOTAL_A
;
411 u32 saveTRANS_HBLANK_A
;
412 u32 saveTRANS_HSYNC_A
;
413 u32 saveTRANS_VTOTAL_A
;
414 u32 saveTRANS_VBLANK_A
;
415 u32 saveTRANS_VSYNC_A
;
423 u32 savePFIT_PGM_RATIOS
;
424 u32 saveBLC_HIST_CTL
;
426 u32 saveBLC_PWM_CTL2
;
427 u32 saveBLC_CPU_PWM_CTL
;
428 u32 saveBLC_CPU_PWM_CTL2
;
441 u32 saveTRANS_HTOTAL_B
;
442 u32 saveTRANS_HBLANK_B
;
443 u32 saveTRANS_HSYNC_B
;
444 u32 saveTRANS_VTOTAL_B
;
445 u32 saveTRANS_VBLANK_B
;
446 u32 saveTRANS_VSYNC_B
;
460 u32 savePP_ON_DELAYS
;
461 u32 savePP_OFF_DELAYS
;
469 u32 savePFIT_CONTROL
;
470 u32 save_palette_a
[256];
471 u32 save_palette_b
[256];
472 u32 saveDPFC_CB_BASE
;
473 u32 saveFBC_CFB_BASE
;
476 u32 saveFBC_CONTROL2
;
486 u32 saveCACHE_MODE_0
;
487 u32 saveMI_ARB_STATE
;
498 uint64_t saveFENCE
[16];
509 u32 savePIPEA_GMCH_DATA_M
;
510 u32 savePIPEB_GMCH_DATA_M
;
511 u32 savePIPEA_GMCH_DATA_N
;
512 u32 savePIPEB_GMCH_DATA_N
;
513 u32 savePIPEA_DP_LINK_M
;
514 u32 savePIPEB_DP_LINK_M
;
515 u32 savePIPEA_DP_LINK_N
;
516 u32 savePIPEB_DP_LINK_N
;
527 u32 savePCH_DREF_CONTROL
;
528 u32 saveDISP_ARB_CTL
;
529 u32 savePIPEA_DATA_M1
;
530 u32 savePIPEA_DATA_N1
;
531 u32 savePIPEA_LINK_M1
;
532 u32 savePIPEA_LINK_N1
;
533 u32 savePIPEB_DATA_M1
;
534 u32 savePIPEB_DATA_N1
;
535 u32 savePIPEB_LINK_M1
;
536 u32 savePIPEB_LINK_N1
;
537 u32 saveMCHBAR_RENDER_STANDBY
;
540 /** Bridge to intel-gtt-ko */
541 const struct intel_gtt
*gtt
;
542 /** Memory allocator for GTT stolen memory */
543 struct drm_mm stolen
;
544 /** Memory allocator for GTT */
545 struct drm_mm gtt_space
;
546 /** List of all objects in gtt_space. Used to restore gtt
547 * mappings on resume */
548 struct list_head gtt_list
;
549 /** End of mappable part of GTT */
550 unsigned long gtt_mappable_end
;
552 struct io_mapping
*gtt_mapping
;
555 struct shrinker inactive_shrinker
;
558 * List of objects currently involved in rendering.
560 * Includes buffers having the contents of their GPU caches
561 * flushed, not necessarily primitives. last_rendering_seqno
562 * represents when the rendering involved will be completed.
564 * A reference is held on the buffer while on this list.
566 struct list_head active_list
;
569 * List of objects which are not in the ringbuffer but which
570 * still have a write_domain which needs to be flushed before
573 * last_rendering_seqno is 0 while an object is in this list.
575 * A reference is held on the buffer while on this list.
577 struct list_head flushing_list
;
580 * LRU list of objects which are not in the ringbuffer and
581 * are ready to unbind, but are still in the GTT.
583 * last_rendering_seqno is 0 while an object is in this list.
585 * A reference is not held on the buffer while on this list,
586 * as merely being GTT-bound shouldn't prevent its being
587 * freed, and we'll pull it off the list in the free path.
589 struct list_head inactive_list
;
592 * LRU list of objects which are not in the ringbuffer but
593 * are still pinned in the GTT.
595 struct list_head pinned_list
;
597 /** LRU list of objects with fence regs on them. */
598 struct list_head fence_list
;
601 * List of objects currently pending being freed.
603 * These objects are no longer in use, but due to a signal
604 * we were prevented from freeing them at the appointed time.
606 struct list_head deferred_free_list
;
609 * We leave the user IRQ off as much as possible,
610 * but this means that requests will finish and never
611 * be retired once the system goes idle. Set a timer to
612 * fire periodically while the ring is running. When it
613 * fires, go retire requests.
615 struct delayed_work retire_work
;
618 * Flag if the X Server, and thus DRM, is not currently in
619 * control of the device.
621 * This is set between LeaveVT and EnterVT. It needs to be
622 * replaced with a semaphore. It also needs to be
623 * transitioned away from for kernel modesetting.
628 * Flag if the hardware appears to be wedged.
630 * This is set when attempts to idle the device timeout.
631 * It prevents command submission from occuring and makes
632 * every pending request fail
636 /** Bit 6 swizzling required for X tiling */
637 uint32_t bit_6_swizzle_x
;
638 /** Bit 6 swizzling required for Y tiling */
639 uint32_t bit_6_swizzle_y
;
641 /* storage for physical objects */
642 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
644 /* accounting, useful for userland debugging */
645 size_t object_memory
;
648 size_t gtt_mappable_memory
;
649 size_t mappable_gtt_used
;
650 size_t mappable_gtt_total
;
654 u32 gtt_mappable_count
;
657 struct sdvo_device_mapping sdvo_mappings
[2];
658 /* indicate whether the LVDS_BORDER should be enabled or not */
659 unsigned int lvds_border_bits
;
660 /* Panel fitter placement and size for Ironlake+ */
661 u32 pch_pf_pos
, pch_pf_size
;
663 struct drm_crtc
*plane_to_crtc_mapping
[2];
664 struct drm_crtc
*pipe_to_crtc_mapping
[2];
665 wait_queue_head_t pending_flip_queue
;
666 bool flip_pending_is_done
;
668 /* Reclocking support */
669 bool render_reclock_avail
;
670 bool lvds_downclock_avail
;
671 /* indicates the reduced downclock for LVDS*/
673 struct work_struct idle_work
;
674 struct timer_list idle_timer
;
678 struct child_device_config
*child_dev
;
679 struct drm_connector
*int_lvds_connector
;
681 bool mchbar_need_disable
;
690 unsigned long last_time1
;
692 struct timespec last_time2
;
693 unsigned long gfx_power
;
697 spinlock_t
*mchdev_lock
;
699 enum no_fbc_reason no_fbc_reason
;
701 struct drm_mm_node
*compressed_fb
;
702 struct drm_mm_node
*compressed_llb
;
704 unsigned long last_gpu_reset
;
706 /* list of fbdev register on this device */
707 struct intel_fbdev
*fbdev
;
708 } drm_i915_private_t
;
710 struct drm_i915_gem_object
{
711 struct drm_gem_object base
;
713 /** Current space allocated to this object in the GTT, if any. */
714 struct drm_mm_node
*gtt_space
;
715 struct list_head gtt_list
;
717 /** This object's place on the active/flushing/inactive lists */
718 struct list_head ring_list
;
719 struct list_head mm_list
;
720 /** This object's place on GPU write list */
721 struct list_head gpu_write_list
;
722 /** This object's place on eviction list */
723 struct list_head evict_list
;
726 * This is set if the object is on the active or flushing lists
727 * (has pending rendering), and is not set if it's on inactive (ready
730 unsigned int active
: 1;
733 * This is set if the object has been written to since last bound
736 unsigned int dirty
: 1;
739 * Fence register bits (if any) for this object. Will be set
740 * as needed when mapped into the GTT.
741 * Protected by dev->struct_mutex.
743 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
745 signed int fence_reg
: 5;
748 * Used for checking the object doesn't appear more than once
749 * in an execbuffer object list.
751 unsigned int in_execbuffer
: 1;
754 * Advice: are the backing pages purgeable?
756 unsigned int madv
: 2;
759 * Current tiling mode for the object.
761 unsigned int tiling_mode
: 2;
763 /** How many users have pinned this object in GTT space. The following
764 * users can each hold at most one reference: pwrite/pread, pin_ioctl
765 * (via user_pin_count), execbuffer (objects are not allowed multiple
766 * times for the same batchbuffer), and the framebuffer code. When
767 * switching/pageflipping, the framebuffer code has at most two buffers
770 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
771 * bits with absolutely no headroom. So use 4 bits. */
772 unsigned int pin_count
: 4;
773 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
776 * Is the object at the current location in the gtt mappable and
777 * fenceable? Used to avoid costly recalculations.
779 unsigned int map_and_fenceable
: 1;
782 * Whether the current gtt mapping needs to be mappable (and isn't just
783 * mappable by accident). Track pin and fault separate for a more
784 * accurate mappable working set.
786 unsigned int fault_mappable
: 1;
787 unsigned int pin_mappable
: 1;
790 * Is the GPU currently using a fence to access this buffer,
792 unsigned int pending_fenced_gpu_access
:1;
793 unsigned int fenced_gpu_access
:1;
800 struct scatterlist
*sg_list
;
804 * Current offset of the object in GTT space.
806 * This is the same as gtt_space->start
810 /** Breadcrumb of last rendering to the buffer. */
811 uint32_t last_rendering_seqno
;
812 struct intel_ring_buffer
*ring
;
814 /** Breadcrumb of last fenced GPU access to the buffer. */
815 uint32_t last_fenced_seqno
;
816 struct intel_ring_buffer
*last_fenced_ring
;
818 /** Current tiling stride for the object, if it's tiled. */
821 /** Record of address bit 17 of each page at last unbind. */
822 unsigned long *bit_17
;
824 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
828 * If present, while GEM_DOMAIN_CPU is in the read domain this array
829 * flags which individual pages are valid.
831 uint8_t *page_cpu_valid
;
833 /** User space pin count and filp owning the pin */
834 uint32_t user_pin_count
;
835 struct drm_file
*pin_filp
;
837 /** for phy allocated objects */
838 struct drm_i915_gem_phys_object
*phys_obj
;
841 * Number of crtcs where this object is currently the fb, but
842 * will be page flipped away on the next vblank. When it
843 * reaches 0, dev_priv->pending_flip_queue will be woken up.
845 atomic_t pending_flip
;
848 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
851 * Request queue structure.
853 * The request queue allows us to note sequence numbers that have been emitted
854 * and may be associated with active buffers to be retired.
856 * By keeping this list, we can avoid having to do questionable
857 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
858 * an emission time with seqnos for tracking how far ahead of the GPU we are.
860 struct drm_i915_gem_request
{
861 /** On Which ring this request was generated */
862 struct intel_ring_buffer
*ring
;
864 /** GEM sequence number associated with this request. */
867 /** Time at which this request was emitted, in jiffies. */
868 unsigned long emitted_jiffies
;
870 /** global list entry for this request */
871 struct list_head list
;
873 struct drm_i915_file_private
*file_priv
;
874 /** file_priv list entry for this request */
875 struct list_head client_list
;
878 struct drm_i915_file_private
{
880 struct spinlock lock
;
881 struct list_head request_list
;
885 enum intel_chip_family
{
892 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
894 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
895 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
896 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
897 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
898 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
899 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
900 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
901 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
902 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
903 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
904 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
905 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
906 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
907 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
908 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
909 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
910 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
911 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
912 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
914 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
915 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
916 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
917 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
918 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
920 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
921 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
922 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
924 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
925 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
927 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
928 * rows, which changed the alignment requirements and fence programming.
930 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
932 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
933 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
934 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
935 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
936 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
937 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
938 /* dsparb controlled by hw only */
939 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
941 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
942 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
943 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
944 #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
946 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
947 #define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))
949 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
950 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
951 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
953 #include "i915_trace.h"
955 extern struct drm_ioctl_desc i915_ioctls
[];
956 extern int i915_max_ioctl
;
957 extern unsigned int i915_fbpercrtc
;
958 extern unsigned int i915_powersave
;
959 extern unsigned int i915_lvds_downclock
;
961 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
962 extern int i915_resume(struct drm_device
*dev
);
963 extern void i915_save_display(struct drm_device
*dev
);
964 extern void i915_restore_display(struct drm_device
*dev
);
965 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
966 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
969 extern void i915_kernel_lost_context(struct drm_device
* dev
);
970 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
971 extern int i915_driver_unload(struct drm_device
*);
972 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
973 extern void i915_driver_lastclose(struct drm_device
* dev
);
974 extern void i915_driver_preclose(struct drm_device
*dev
,
975 struct drm_file
*file_priv
);
976 extern void i915_driver_postclose(struct drm_device
*dev
,
977 struct drm_file
*file_priv
);
978 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
979 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
981 extern int i915_emit_box(struct drm_device
*dev
,
982 struct drm_clip_rect
*boxes
,
983 int i
, int DR1
, int DR4
);
984 extern int i915_reset(struct drm_device
*dev
, u8 flags
);
985 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
986 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
987 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
988 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
992 void i915_hangcheck_elapsed(unsigned long data
);
993 void i915_handle_error(struct drm_device
*dev
, bool wedged
);
994 extern int i915_irq_emit(struct drm_device
*dev
, void *data
,
995 struct drm_file
*file_priv
);
996 extern int i915_irq_wait(struct drm_device
*dev
, void *data
,
997 struct drm_file
*file_priv
);
998 void i915_trace_irq_get(struct drm_device
*dev
, u32 seqno
);
999 extern void i915_enable_interrupt (struct drm_device
*dev
);
1001 extern irqreturn_t
i915_driver_irq_handler(DRM_IRQ_ARGS
);
1002 extern void i915_driver_irq_preinstall(struct drm_device
* dev
);
1003 extern int i915_driver_irq_postinstall(struct drm_device
*dev
);
1004 extern void i915_driver_irq_uninstall(struct drm_device
* dev
);
1005 extern int i915_vblank_pipe_set(struct drm_device
*dev
, void *data
,
1006 struct drm_file
*file_priv
);
1007 extern int i915_vblank_pipe_get(struct drm_device
*dev
, void *data
,
1008 struct drm_file
*file_priv
);
1009 extern int i915_enable_vblank(struct drm_device
*dev
, int crtc
);
1010 extern void i915_disable_vblank(struct drm_device
*dev
, int crtc
);
1011 extern u32
i915_get_vblank_counter(struct drm_device
*dev
, int crtc
);
1012 extern u32
gm45_get_vblank_counter(struct drm_device
*dev
, int crtc
);
1013 extern int i915_vblank_swap(struct drm_device
*dev
, void *data
,
1014 struct drm_file
*file_priv
);
1015 extern void i915_enable_irq(drm_i915_private_t
*dev_priv
, u32 mask
);
1016 extern void i915_disable_irq(drm_i915_private_t
*dev_priv
, u32 mask
);
1017 extern void ironlake_enable_graphics_irq(drm_i915_private_t
*dev_priv
,
1019 extern void ironlake_disable_graphics_irq(drm_i915_private_t
*dev_priv
,
1023 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1026 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1028 void intel_enable_asle (struct drm_device
*dev
);
1030 #ifdef CONFIG_DEBUG_FS
1031 extern void i915_destroy_error_state(struct drm_device
*dev
);
1033 #define i915_destroy_error_state(x)
1038 extern int i915_mem_alloc(struct drm_device
*dev
, void *data
,
1039 struct drm_file
*file_priv
);
1040 extern int i915_mem_free(struct drm_device
*dev
, void *data
,
1041 struct drm_file
*file_priv
);
1042 extern int i915_mem_init_heap(struct drm_device
*dev
, void *data
,
1043 struct drm_file
*file_priv
);
1044 extern int i915_mem_destroy_heap(struct drm_device
*dev
, void *data
,
1045 struct drm_file
*file_priv
);
1046 extern void i915_mem_takedown(struct mem_block
**heap
);
1047 extern void i915_mem_release(struct drm_device
* dev
,
1048 struct drm_file
*file_priv
, struct mem_block
*heap
);
1050 int i915_gem_check_is_wedged(struct drm_device
*dev
);
1051 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
1052 struct drm_file
*file_priv
);
1053 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1054 struct drm_file
*file_priv
);
1055 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
1056 struct drm_file
*file_priv
);
1057 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1058 struct drm_file
*file_priv
);
1059 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1060 struct drm_file
*file_priv
);
1061 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1062 struct drm_file
*file_priv
);
1063 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1064 struct drm_file
*file_priv
);
1065 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1066 struct drm_file
*file_priv
);
1067 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1068 struct drm_file
*file_priv
);
1069 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1070 struct drm_file
*file_priv
);
1071 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
1072 struct drm_file
*file_priv
);
1073 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
1074 struct drm_file
*file_priv
);
1075 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
1076 struct drm_file
*file_priv
);
1077 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
1078 struct drm_file
*file_priv
);
1079 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
1080 struct drm_file
*file_priv
);
1081 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
1082 struct drm_file
*file_priv
);
1083 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
1084 struct drm_file
*file_priv
);
1085 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
1086 struct drm_file
*file_priv
);
1087 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
1088 struct drm_file
*file_priv
);
1089 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
1090 struct drm_file
*file_priv
);
1091 void i915_gem_load(struct drm_device
*dev
);
1092 int i915_gem_init_object(struct drm_gem_object
*obj
);
1093 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
1095 void i915_gem_free_object(struct drm_gem_object
*obj
);
1096 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
1098 bool map_and_fenceable
);
1099 void i915_gem_object_unpin(struct drm_i915_gem_object
*obj
);
1100 int __must_check
i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
1101 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
1102 void i915_gem_lastclose(struct drm_device
*dev
);
1105 * Returns true if seq1 is later than seq2.
1108 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1110 return (int32_t)(seq1
- seq2
) >= 0;
1113 int __must_check
i915_gem_object_get_fence_reg(struct drm_i915_gem_object
*obj
,
1114 bool interruptible
);
1115 int __must_check
i915_gem_object_put_fence_reg(struct drm_i915_gem_object
*obj
,
1116 bool interruptible
);
1118 void i915_gem_retire_requests(struct drm_device
*dev
);
1119 void i915_gem_reset(struct drm_device
*dev
);
1120 void i915_gem_clflush_object(struct drm_i915_gem_object
*obj
);
1121 int __must_check
i915_gem_object_set_domain(struct drm_i915_gem_object
*obj
,
1122 uint32_t read_domains
,
1123 uint32_t write_domain
);
1124 int __must_check
i915_gem_object_flush_gpu(struct drm_i915_gem_object
*obj
,
1125 bool interruptible
);
1126 int __must_check
i915_gem_init_ringbuffer(struct drm_device
*dev
);
1127 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
1128 void i915_gem_do_init(struct drm_device
*dev
,
1129 unsigned long start
,
1130 unsigned long mappable_end
,
1132 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
1133 int __must_check
i915_gem_idle(struct drm_device
*dev
);
1134 int __must_check
i915_add_request(struct drm_device
*dev
,
1135 struct drm_file
*file_priv
,
1136 struct drm_i915_gem_request
*request
,
1137 struct intel_ring_buffer
*ring
);
1138 int __must_check
i915_do_wait_request(struct drm_device
*dev
,
1141 struct intel_ring_buffer
*ring
);
1142 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
1144 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
1147 i915_gem_object_set_to_display_plane(struct drm_i915_gem_object
*obj
,
1148 struct intel_ring_buffer
*pipelined
);
1149 int i915_gem_attach_phys_object(struct drm_device
*dev
,
1150 struct drm_i915_gem_object
*obj
,
1153 void i915_gem_detach_phys_object(struct drm_device
*dev
,
1154 struct drm_i915_gem_object
*obj
);
1155 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
1156 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
1158 /* i915_gem_gtt.c */
1159 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
);
1160 int __must_check
i915_gem_gtt_bind_object(struct drm_i915_gem_object
*obj
);
1161 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object
*obj
);
1163 /* i915_gem_evict.c */
1164 int __must_check
i915_gem_evict_something(struct drm_device
*dev
, int min_size
,
1165 unsigned alignment
, bool mappable
);
1166 int __must_check
i915_gem_evict_everything(struct drm_device
*dev
,
1167 bool purgeable_only
);
1168 int __must_check
i915_gem_evict_inactive(struct drm_device
*dev
,
1169 bool purgeable_only
);
1171 /* i915_gem_tiling.c */
1172 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
1173 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1174 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1176 /* i915_gem_debug.c */
1177 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1178 const char *where
, uint32_t mark
);
1180 int i915_verify_lists(struct drm_device
*dev
);
1182 #define i915_verify_lists(dev) 0
1184 void i915_gem_object_check_coherency(struct drm_i915_gem_object
*obj
,
1186 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1187 const char *where
, uint32_t mark
);
1189 /* i915_debugfs.c */
1190 int i915_debugfs_init(struct drm_minor
*minor
);
1191 void i915_debugfs_cleanup(struct drm_minor
*minor
);
1193 /* i915_suspend.c */
1194 extern int i915_save_state(struct drm_device
*dev
);
1195 extern int i915_restore_state(struct drm_device
*dev
);
1197 /* i915_suspend.c */
1198 extern int i915_save_state(struct drm_device
*dev
);
1199 extern int i915_restore_state(struct drm_device
*dev
);
1202 extern int intel_setup_gmbus(struct drm_device
*dev
);
1203 extern void intel_teardown_gmbus(struct drm_device
*dev
);
1204 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
1205 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
1206 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
1208 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
1210 extern void intel_i2c_reset(struct drm_device
*dev
);
1212 /* intel_opregion.c */
1213 extern int intel_opregion_setup(struct drm_device
*dev
);
1215 extern void intel_opregion_init(struct drm_device
*dev
);
1216 extern void intel_opregion_fini(struct drm_device
*dev
);
1217 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
1218 extern void intel_opregion_gse_intr(struct drm_device
*dev
);
1219 extern void intel_opregion_enable_asle(struct drm_device
*dev
);
1221 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
1222 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
1223 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
1224 static inline void intel_opregion_gse_intr(struct drm_device
*dev
) { return; }
1225 static inline void intel_opregion_enable_asle(struct drm_device
*dev
) { return; }
1230 extern void intel_register_dsm_handler(void);
1231 extern void intel_unregister_dsm_handler(void);
1233 static inline void intel_register_dsm_handler(void) { return; }
1234 static inline void intel_unregister_dsm_handler(void) { return; }
1235 #endif /* CONFIG_ACPI */
1238 extern void intel_modeset_init(struct drm_device
*dev
);
1239 extern void intel_modeset_cleanup(struct drm_device
*dev
);
1240 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
1241 extern void i8xx_disable_fbc(struct drm_device
*dev
);
1242 extern void g4x_disable_fbc(struct drm_device
*dev
);
1243 extern void ironlake_disable_fbc(struct drm_device
*dev
);
1244 extern void intel_disable_fbc(struct drm_device
*dev
);
1245 extern void intel_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
);
1246 extern bool intel_fbc_enabled(struct drm_device
*dev
);
1247 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
1248 extern void intel_detect_pch (struct drm_device
*dev
);
1249 extern int intel_trans_dp_port_sel (struct drm_crtc
*crtc
);
1252 #ifdef CONFIG_DEBUG_FS
1253 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
1254 extern void intel_overlay_print_error_state(struct seq_file
*m
, struct intel_overlay_error_state
*error
);
1256 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
1257 extern void intel_display_print_error_state(struct seq_file
*m
,
1258 struct drm_device
*dev
,
1259 struct intel_display_error_state
*error
);
1263 * Lock test for when it's just for synchronization of ring access.
1265 * In that case, we don't need to do it when GEM is initialized as nobody else
1266 * has access to the ring.
1268 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
1269 if (((drm_i915_private_t *)dev->dev_private)->render_ring.obj \
1271 LOCK_TEST_WITH_RETURN(dev, file); \
1275 #define __i915_read(x, y) \
1276 static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1277 u##x val = read##y(dev_priv->regs + reg); \
1278 trace_i915_reg_rw('R', reg, val, sizeof(val)); \
1287 #define __i915_write(x, y) \
1288 static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1289 trace_i915_reg_rw('W', reg, val, sizeof(val)); \
1290 write##y(val, dev_priv->regs + reg); \
1298 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1299 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1301 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1302 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1303 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1304 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1306 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1307 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1308 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1309 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1311 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1312 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1314 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1315 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1318 /* On SNB platform, before reading ring registers forcewake bit
1319 * must be set to prevent GT core from power down and stale values being
1322 static inline u32
i915_safe_read(struct drm_i915_private
*dev_priv
, u32 reg
)
1324 if (IS_GEN6(dev_priv
->dev
)) {
1325 I915_WRITE_NOTRACE(FORCEWAKE
, 1);
1326 POSTING_READ(FORCEWAKE
);
1327 /* XXX How long do we really need to wait here?
1328 * Will different registers/engines require different periods?
1332 return I915_READ(reg
);
1336 i915_write(struct drm_i915_private
*dev_priv
, u32 reg
, u64 val
, int len
)
1338 /* Trace down the write operation before the real write */
1339 trace_i915_reg_rw('W', reg
, val
, len
);
1342 writeq(val
, dev_priv
->regs
+ reg
);
1345 writel(val
, dev_priv
->regs
+ reg
);
1348 writew(val
, dev_priv
->regs
+ reg
);
1351 writeb(val
, dev_priv
->regs
+ reg
);
1356 #define BEGIN_LP_RING(n) \
1357 intel_ring_begin(&dev_priv->render_ring, (n))
1359 #define OUT_RING(x) \
1360 intel_ring_emit(&dev_priv->render_ring, x)
1362 #define ADVANCE_LP_RING() \
1363 intel_ring_advance(&dev_priv->render_ring)
1366 * Reads a dword out of the status page, which is written to from the command
1367 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
1368 * MI_STORE_DATA_IMM.
1370 * The following dwords have a reserved meaning:
1371 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
1372 * 0x04: ring 0 head pointer
1373 * 0x05: ring 1 head pointer (915-class)
1374 * 0x06: ring 2 head pointer (915-class)
1375 * 0x10-0x1b: Context status DWords (GM45)
1376 * 0x1f: Last written status offset. (GM45)
1378 * The area from dword 0x20 to 0x3ff is available for driver usage.
1380 #define READ_HWSP(dev_priv, reg) (((volatile u32 *)\
1381 (dev_priv->render_ring.status_page.page_addr))[reg])
1382 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1383 #define I915_GEM_HWS_INDEX 0x20
1384 #define I915_BREADCRUMB_INDEX 0x21