1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
38 #include "intel_bios.h"
39 #include "intel_ringbuffer.h"
40 #include "intel_lrc.h"
41 #include "i915_gem_gtt.h"
42 #include "i915_gem_render_state.h"
43 #include <linux/io-mapping.h>
44 #include <linux/i2c.h>
45 #include <linux/i2c-algo-bit.h>
46 #include <drm/intel-gtt.h>
47 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
48 #include <drm/drm_gem.h>
49 #include <linux/backlight.h>
50 #include <linux/hashtable.h>
51 #include <linux/intel-iommu.h>
52 #include <linux/kref.h>
53 #include <linux/pm_qos.h>
54 #include "intel_guc.h"
56 /* General customization:
59 #define DRIVER_NAME "i915"
60 #define DRIVER_DESC "Intel Graphics"
61 #define DRIVER_DATE "20151204"
64 /* Many gcc seem to no see through this and fall over :( */
66 #define WARN_ON(x) ({ \
67 bool __i915_warn_cond = (x); \
68 if (__builtin_constant_p(__i915_warn_cond)) \
69 BUILD_BUG_ON(__i915_warn_cond); \
70 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
72 #define WARN_ON(x) WARN((x), "WARN_ON(%s)", #x )
76 #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(%s)", #x )
78 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
79 (long) (x), __func__);
81 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
82 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
83 * which may not necessarily be a user visible problem. This will either
84 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
85 * enable distros and users to tailor their preferred amount of i915 abrt
88 #define I915_STATE_WARN(condition, format...) ({ \
89 int __ret_warn_on = !!(condition); \
90 if (unlikely(__ret_warn_on)) { \
91 if (i915.verbose_state_checks) \
96 unlikely(__ret_warn_on); \
99 #define I915_STATE_WARN_ON(condition) ({ \
100 int __ret_warn_on = !!(condition); \
101 if (unlikely(__ret_warn_on)) { \
102 if (i915.verbose_state_checks) \
103 WARN(1, "WARN_ON(" #condition ")\n"); \
105 DRM_ERROR("WARN_ON(" #condition ")\n"); \
107 unlikely(__ret_warn_on); \
110 static inline const char *yesno(bool v
)
112 return v
? "yes" : "no";
121 I915_MAX_PIPES
= _PIPE_EDP
123 #define pipe_name(p) ((p) + 'A')
132 #define transcoder_name(t) ((t) + 'A')
135 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
136 * number of planes per CRTC. Not all platforms really have this many planes,
137 * which means some arrays of size I915_MAX_PLANES may have unused entries
138 * between the topmost sprite plane and the cursor plane.
147 #define plane_name(p) ((p) + 'A')
149 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
159 #define port_name(p) ((p) + 'A')
161 #define I915_NUM_PHYS_VLV 2
173 enum intel_display_power_domain
{
177 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
178 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
179 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
180 POWER_DOMAIN_TRANSCODER_A
,
181 POWER_DOMAIN_TRANSCODER_B
,
182 POWER_DOMAIN_TRANSCODER_C
,
183 POWER_DOMAIN_TRANSCODER_EDP
,
184 POWER_DOMAIN_PORT_DDI_A_LANES
,
185 POWER_DOMAIN_PORT_DDI_B_LANES
,
186 POWER_DOMAIN_PORT_DDI_C_LANES
,
187 POWER_DOMAIN_PORT_DDI_D_LANES
,
188 POWER_DOMAIN_PORT_DDI_E_LANES
,
189 POWER_DOMAIN_PORT_DSI
,
190 POWER_DOMAIN_PORT_CRT
,
191 POWER_DOMAIN_PORT_OTHER
,
200 POWER_DOMAIN_MODESET
,
206 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
207 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
208 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
209 #define POWER_DOMAIN_TRANSCODER(tran) \
210 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
211 (tran) + POWER_DOMAIN_TRANSCODER_A)
215 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
227 #define for_each_hpd_pin(__pin) \
228 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
230 struct i915_hotplug
{
231 struct work_struct hotplug_work
;
234 unsigned long last_jiffies
;
239 HPD_MARK_DISABLED
= 2
241 } stats
[HPD_NUM_PINS
];
243 struct delayed_work reenable_work
;
245 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
248 struct work_struct dig_port_work
;
251 * if we get a HPD irq from DP and a HPD irq from non-DP
252 * the non-DP HPD could block the workqueue on a mode config
253 * mutex getting, that userspace may have taken. However
254 * userspace is waiting on the DP workqueue to run which is
255 * blocked behind the non-DP one.
257 struct workqueue_struct
*dp_wq
;
260 #define I915_GEM_GPU_DOMAINS \
261 (I915_GEM_DOMAIN_RENDER | \
262 I915_GEM_DOMAIN_SAMPLER | \
263 I915_GEM_DOMAIN_COMMAND | \
264 I915_GEM_DOMAIN_INSTRUCTION | \
265 I915_GEM_DOMAIN_VERTEX)
267 #define for_each_pipe(__dev_priv, __p) \
268 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
269 #define for_each_plane(__dev_priv, __pipe, __p) \
271 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
273 #define for_each_sprite(__dev_priv, __p, __s) \
275 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
278 #define for_each_crtc(dev, crtc) \
279 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
281 #define for_each_intel_plane(dev, intel_plane) \
282 list_for_each_entry(intel_plane, \
283 &dev->mode_config.plane_list, \
286 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
287 list_for_each_entry(intel_plane, \
288 &(dev)->mode_config.plane_list, \
290 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
292 #define for_each_intel_crtc(dev, intel_crtc) \
293 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
295 #define for_each_intel_encoder(dev, intel_encoder) \
296 list_for_each_entry(intel_encoder, \
297 &(dev)->mode_config.encoder_list, \
300 #define for_each_intel_connector(dev, intel_connector) \
301 list_for_each_entry(intel_connector, \
302 &dev->mode_config.connector_list, \
305 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
306 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
307 for_each_if ((intel_encoder)->base.crtc == (__crtc))
309 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
310 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
311 for_each_if ((intel_connector)->base.encoder == (__encoder))
313 #define for_each_power_domain(domain, mask) \
314 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
315 for_each_if ((1 << (domain)) & (mask))
317 struct drm_i915_private
;
318 struct i915_mm_struct
;
319 struct i915_mmu_object
;
321 struct drm_i915_file_private
{
322 struct drm_i915_private
*dev_priv
;
323 struct drm_file
*file
;
327 struct list_head request_list
;
328 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
329 * chosen to prevent the CPU getting more than a frame ahead of the GPU
330 * (when using lax throttling for the frontbuffer). We also use it to
331 * offer free GPU waitboosts for severely congested workloads.
333 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
335 struct idr context_idr
;
337 struct intel_rps_client
{
338 struct list_head link
;
342 struct intel_engine_cs
*bsd_ring
;
346 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
347 /* real shared dpll ids must be >= 0 */
348 DPLL_ID_PCH_PLL_A
= 0,
349 DPLL_ID_PCH_PLL_B
= 1,
356 DPLL_ID_SKL_DPLL1
= 0,
357 DPLL_ID_SKL_DPLL2
= 1,
358 DPLL_ID_SKL_DPLL3
= 2,
360 #define I915_NUM_PLLS 3
362 struct intel_dpll_hw_state
{
375 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
376 * lower part of ctrl1 and they get shifted into position when writing
377 * the register. This allows us to easily compare the state to share
381 /* HDMI only, 0 when used for DP */
382 uint32_t cfgcr1
, cfgcr2
;
385 uint32_t ebb0
, ebb4
, pll0
, pll1
, pll2
, pll3
, pll6
, pll8
, pll9
, pll10
,
389 struct intel_shared_dpll_config
{
390 unsigned crtc_mask
; /* mask of CRTCs sharing this PLL */
391 struct intel_dpll_hw_state hw_state
;
394 struct intel_shared_dpll
{
395 struct intel_shared_dpll_config config
;
397 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
398 bool on
; /* is the PLL actually active? Disabled during modeset */
400 /* should match the index in the dev_priv->shared_dplls array */
401 enum intel_dpll_id id
;
402 /* The mode_set hook is optional and should be used together with the
403 * intel_prepare_shared_dpll function. */
404 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
405 struct intel_shared_dpll
*pll
);
406 void (*enable
)(struct drm_i915_private
*dev_priv
,
407 struct intel_shared_dpll
*pll
);
408 void (*disable
)(struct drm_i915_private
*dev_priv
,
409 struct intel_shared_dpll
*pll
);
410 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
411 struct intel_shared_dpll
*pll
,
412 struct intel_dpll_hw_state
*hw_state
);
420 /* Used by dp and fdi links */
421 struct intel_link_m_n
{
429 void intel_link_compute_m_n(int bpp
, int nlanes
,
430 int pixel_clock
, int link_clock
,
431 struct intel_link_m_n
*m_n
);
433 /* Interface history:
436 * 1.2: Add Power Management
437 * 1.3: Add vblank support
438 * 1.4: Fix cmdbuffer path, add heap destroy
439 * 1.5: Add vblank pipe configuration
440 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
441 * - Support vertical blank on secondary display pipe
443 #define DRIVER_MAJOR 1
444 #define DRIVER_MINOR 6
445 #define DRIVER_PATCHLEVEL 0
447 #define WATCH_LISTS 0
449 struct opregion_header
;
450 struct opregion_acpi
;
451 struct opregion_swsci
;
452 struct opregion_asle
;
454 struct intel_opregion
{
455 struct opregion_header
*header
;
456 struct opregion_acpi
*acpi
;
457 struct opregion_swsci
*swsci
;
458 u32 swsci_gbda_sub_functions
;
459 u32 swsci_sbcb_sub_functions
;
460 struct opregion_asle
*asle
;
465 struct work_struct asle_work
;
467 #define OPREGION_SIZE (8*1024)
469 struct intel_overlay
;
470 struct intel_overlay_error_state
;
472 #define I915_FENCE_REG_NONE -1
473 #define I915_MAX_NUM_FENCES 32
474 /* 32 fences + sign bit for FENCE_REG_NONE */
475 #define I915_MAX_NUM_FENCE_BITS 6
477 struct drm_i915_fence_reg
{
478 struct list_head lru_list
;
479 struct drm_i915_gem_object
*obj
;
483 struct sdvo_device_mapping
{
492 struct intel_display_error_state
;
494 struct drm_i915_error_state
{
503 /* Generic register state */
511 u32 error
; /* gen6+ */
512 u32 err_int
; /* gen7 */
513 u32 fault_data0
; /* gen8, gen9 */
514 u32 fault_data1
; /* gen8, gen9 */
520 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
521 u64 fence
[I915_MAX_NUM_FENCES
];
522 struct intel_overlay_error_state
*overlay
;
523 struct intel_display_error_state
*display
;
524 struct drm_i915_error_object
*semaphore_obj
;
526 struct drm_i915_error_ring
{
528 /* Software tracked state */
531 enum intel_ring_hangcheck_action hangcheck_action
;
534 /* our own tracking of ring head and tail */
538 u32 semaphore_seqno
[I915_NUM_RINGS
- 1];
557 u32 rc_psmi
; /* sleep state */
558 u32 semaphore_mboxes
[I915_NUM_RINGS
- 1];
560 struct drm_i915_error_object
{
564 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
566 struct drm_i915_error_request
{
581 char comm
[TASK_COMM_LEN
];
582 } ring
[I915_NUM_RINGS
];
584 struct drm_i915_error_buffer
{
587 u32 rseqno
[I915_NUM_RINGS
], wseqno
;
591 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
599 } **active_bo
, **pinned_bo
;
601 u32
*active_bo_count
, *pinned_bo_count
;
605 struct intel_connector
;
606 struct intel_encoder
;
607 struct intel_crtc_state
;
608 struct intel_initial_plane_config
;
613 struct drm_i915_display_funcs
{
614 int (*get_display_clock_speed
)(struct drm_device
*dev
);
615 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
617 * find_dpll() - Find the best values for the PLL
618 * @limit: limits for the PLL
619 * @crtc: current CRTC
620 * @target: target frequency in kHz
621 * @refclk: reference clock frequency in kHz
622 * @match_clock: if provided, @best_clock P divider must
623 * match the P divider from @match_clock
624 * used for LVDS downclocking
625 * @best_clock: best PLL values found
627 * Returns true on success, false on failure.
629 bool (*find_dpll
)(const struct intel_limit
*limit
,
630 struct intel_crtc_state
*crtc_state
,
631 int target
, int refclk
,
632 struct dpll
*match_clock
,
633 struct dpll
*best_clock
);
634 int (*compute_pipe_wm
)(struct intel_crtc
*crtc
,
635 struct drm_atomic_state
*state
);
636 void (*update_wm
)(struct drm_crtc
*crtc
);
637 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
638 void (*modeset_commit_cdclk
)(struct drm_atomic_state
*state
);
639 /* Returns the active state of the crtc, and if the crtc is active,
640 * fills out the pipe-config with the hw state. */
641 bool (*get_pipe_config
)(struct intel_crtc
*,
642 struct intel_crtc_state
*);
643 void (*get_initial_plane_config
)(struct intel_crtc
*,
644 struct intel_initial_plane_config
*);
645 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
646 struct intel_crtc_state
*crtc_state
);
647 void (*crtc_enable
)(struct drm_crtc
*crtc
);
648 void (*crtc_disable
)(struct drm_crtc
*crtc
);
649 void (*audio_codec_enable
)(struct drm_connector
*connector
,
650 struct intel_encoder
*encoder
,
651 const struct drm_display_mode
*adjusted_mode
);
652 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
653 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
654 void (*init_clock_gating
)(struct drm_device
*dev
);
655 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
656 struct drm_framebuffer
*fb
,
657 struct drm_i915_gem_object
*obj
,
658 struct drm_i915_gem_request
*req
,
660 void (*update_primary_plane
)(struct drm_crtc
*crtc
,
661 struct drm_framebuffer
*fb
,
663 void (*hpd_irq_setup
)(struct drm_device
*dev
);
664 /* clock updates for mode set */
666 /* render clock increase/decrease */
667 /* display clock increase/decrease */
668 /* pll clock increase/decrease */
671 enum forcewake_domain_id
{
672 FW_DOMAIN_ID_RENDER
= 0,
673 FW_DOMAIN_ID_BLITTER
,
679 enum forcewake_domains
{
680 FORCEWAKE_RENDER
= (1 << FW_DOMAIN_ID_RENDER
),
681 FORCEWAKE_BLITTER
= (1 << FW_DOMAIN_ID_BLITTER
),
682 FORCEWAKE_MEDIA
= (1 << FW_DOMAIN_ID_MEDIA
),
683 FORCEWAKE_ALL
= (FORCEWAKE_RENDER
|
688 struct intel_uncore_funcs
{
689 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
690 enum forcewake_domains domains
);
691 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
692 enum forcewake_domains domains
);
694 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
695 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
696 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
697 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
699 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
700 uint8_t val
, bool trace
);
701 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
702 uint16_t val
, bool trace
);
703 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
704 uint32_t val
, bool trace
);
705 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
706 uint64_t val
, bool trace
);
709 struct intel_uncore
{
710 spinlock_t lock
; /** lock is also taken in irq contexts. */
712 struct intel_uncore_funcs funcs
;
715 enum forcewake_domains fw_domains
;
717 struct intel_uncore_forcewake_domain
{
718 struct drm_i915_private
*i915
;
719 enum forcewake_domain_id id
;
721 struct timer_list timer
;
728 } fw_domain
[FW_DOMAIN_ID_COUNT
];
731 /* Iterate over initialised fw domains */
732 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
733 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
734 (i__) < FW_DOMAIN_ID_COUNT; \
735 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
736 for_each_if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
738 #define for_each_fw_domain(domain__, dev_priv__, i__) \
739 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
741 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
742 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
743 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
746 struct work_struct work
;
748 uint32_t *dmc_payload
;
749 uint32_t dmc_fw_size
;
752 i915_reg_t mmioaddr
[8];
753 uint32_t mmiodata
[8];
756 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
757 func(is_mobile) sep \
760 func(is_i945gm) sep \
762 func(need_gfx_hws) sep \
764 func(is_pineview) sep \
765 func(is_broadwater) sep \
766 func(is_crestline) sep \
767 func(is_ivybridge) sep \
768 func(is_valleyview) sep \
769 func(is_cherryview) sep \
770 func(is_haswell) sep \
771 func(is_skylake) sep \
772 func(is_broxton) sep \
773 func(is_kabylake) sep \
774 func(is_preliminary) sep \
776 func(has_pipe_cxsr) sep \
777 func(has_hotplug) sep \
778 func(cursor_needs_physical) sep \
779 func(has_overlay) sep \
780 func(overlay_needs_physical) sep \
781 func(supports_tv) sep \
786 #define DEFINE_FLAG(name) u8 name:1
787 #define SEP_SEMICOLON ;
789 struct intel_device_info
{
790 u32 display_mmio_offset
;
793 u8 num_sprites
[I915_MAX_PIPES
];
795 u8 ring_mask
; /* Rings supported by the HW */
796 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
797 /* Register offsets for the various display pipes and transcoders */
798 int pipe_offsets
[I915_MAX_TRANSCODERS
];
799 int trans_offsets
[I915_MAX_TRANSCODERS
];
800 int palette_offsets
[I915_MAX_PIPES
];
801 int cursor_offsets
[I915_MAX_PIPES
];
803 /* Slice/subslice/EU info */
806 u8 subslice_per_slice
;
809 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
812 u8 has_subslice_pg
:1;
819 enum i915_cache_level
{
821 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
822 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
823 caches, eg sampler/render caches, and the
824 large Last-Level-Cache. LLC is coherent with
825 the CPU, but L3 is only visible to the GPU. */
826 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
829 struct i915_ctx_hang_stats
{
830 /* This context had batch pending when hang was declared */
831 unsigned batch_pending
;
833 /* This context had batch active when hang was declared */
834 unsigned batch_active
;
836 /* Time when this context was last blamed for a GPU reset */
837 unsigned long guilty_ts
;
839 /* If the contexts causes a second GPU hang within this time,
840 * it is permanently banned from submitting any more work.
842 unsigned long ban_period_seconds
;
844 /* This context is banned to submit more work */
848 /* This must match up with the value previously used for execbuf2.rsvd1. */
849 #define DEFAULT_CONTEXT_HANDLE 0
851 #define CONTEXT_NO_ZEROMAP (1<<0)
853 * struct intel_context - as the name implies, represents a context.
854 * @ref: reference count.
855 * @user_handle: userspace tracking identity for this context.
856 * @remap_slice: l3 row remapping information.
857 * @flags: context specific flags:
858 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
859 * @file_priv: filp associated with this context (NULL for global default
861 * @hang_stats: information about the role of this context in possible GPU
863 * @ppgtt: virtual memory space used by this context.
864 * @legacy_hw_ctx: render context backing object and whether it is correctly
865 * initialized (legacy ring submission mechanism only).
866 * @link: link in the global list of contexts.
868 * Contexts are memory images used by the hardware to store copies of their
871 struct intel_context
{
875 struct drm_i915_private
*i915
;
877 struct drm_i915_file_private
*file_priv
;
878 struct i915_ctx_hang_stats hang_stats
;
879 struct i915_hw_ppgtt
*ppgtt
;
881 /* Legacy ring buffer submission */
883 struct drm_i915_gem_object
*rcs_state
;
889 struct drm_i915_gem_object
*state
;
890 struct intel_ringbuffer
*ringbuf
;
892 } engine
[I915_NUM_RINGS
];
894 struct list_head link
;
906 /* This is always the inner lock when overlapping with struct_mutex and
907 * it's the outer lock when overlapping with stolen_lock. */
911 unsigned int possible_framebuffer_bits
;
912 unsigned int busy_bits
;
913 struct intel_crtc
*crtc
;
916 struct drm_mm_node compressed_fb
;
917 struct drm_mm_node
*compressed_llb
;
924 struct intel_fbc_work
{
926 struct work_struct work
;
927 struct drm_framebuffer
*fb
;
928 unsigned long enable_jiffies
;
931 const char *no_fbc_reason
;
933 bool (*is_active
)(struct drm_i915_private
*dev_priv
);
934 void (*activate
)(struct intel_crtc
*crtc
);
935 void (*deactivate
)(struct drm_i915_private
*dev_priv
);
939 * HIGH_RR is the highest eDP panel refresh rate read from EDID
940 * LOW_RR is the lowest eDP panel refresh rate found from EDID
941 * parsing for same resolution.
943 enum drrs_refresh_rate_type
{
946 DRRS_MAX_RR
, /* RR count */
949 enum drrs_support_type
{
950 DRRS_NOT_SUPPORTED
= 0,
951 STATIC_DRRS_SUPPORT
= 1,
952 SEAMLESS_DRRS_SUPPORT
= 2
958 struct delayed_work work
;
960 unsigned busy_frontbuffer_bits
;
961 enum drrs_refresh_rate_type refresh_rate_type
;
962 enum drrs_support_type type
;
969 struct intel_dp
*enabled
;
971 struct delayed_work work
;
972 unsigned busy_frontbuffer_bits
;
978 PCH_NONE
= 0, /* No PCH present */
979 PCH_IBX
, /* Ibexpeak PCH */
980 PCH_CPT
, /* Cougarpoint PCH */
981 PCH_LPT
, /* Lynxpoint PCH */
982 PCH_SPT
, /* Sunrisepoint PCH */
986 enum intel_sbi_destination
{
991 #define QUIRK_PIPEA_FORCE (1<<0)
992 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
993 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
994 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
995 #define QUIRK_PIPEB_FORCE (1<<4)
996 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
999 struct intel_fbc_work
;
1001 struct intel_gmbus
{
1002 struct i2c_adapter adapter
;
1005 i915_reg_t gpio_reg
;
1006 struct i2c_algo_bit_data bit_algo
;
1007 struct drm_i915_private
*dev_priv
;
1010 struct i915_suspend_saved_registers
{
1013 u32 savePP_ON_DELAYS
;
1014 u32 savePP_OFF_DELAYS
;
1019 u32 saveFBC_CONTROL
;
1020 u32 saveCACHE_MODE_0
;
1021 u32 saveMI_ARB_STATE
;
1025 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1026 u32 savePCH_PORT_HOTPLUG
;
1030 struct vlv_s0ix_state
{
1037 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1038 u32 media_max_req_count
;
1039 u32 gfx_max_req_count
;
1065 u32 rp_down_timeout
;
1071 /* Display 1 CZ domain */
1076 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1078 /* GT SA CZ domain */
1085 /* Display 2 CZ domain */
1089 u32 clock_gate_dis2
;
1092 struct intel_rps_ei
{
1098 struct intel_gen6_power_mgmt
{
1100 * work, interrupts_enabled and pm_iir are protected by
1101 * dev_priv->irq_lock
1103 struct work_struct work
;
1104 bool interrupts_enabled
;
1107 /* Frequencies are stored in potentially platform dependent multiples.
1108 * In other words, *_freq needs to be multiplied by X to be interesting.
1109 * Soft limits are those which are used for the dynamic reclocking done
1110 * by the driver (raise frequencies under heavy loads, and lower for
1111 * lighter loads). Hard limits are those imposed by the hardware.
1113 * A distinction is made for overclocking, which is never enabled by
1114 * default, and is considered to be above the hard limit if it's
1117 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1118 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1119 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1120 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1121 u8 min_freq
; /* AKA RPn. Minimum frequency */
1122 u8 idle_freq
; /* Frequency to request when we are idle */
1123 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1124 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1125 u8 rp0_freq
; /* Non-overclocked max frequency. */
1127 u8 up_threshold
; /* Current %busy required to uplock */
1128 u8 down_threshold
; /* Current %busy required to downclock */
1131 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1133 spinlock_t client_lock
;
1134 struct list_head clients
;
1138 struct delayed_work delayed_resume_work
;
1141 struct intel_rps_client semaphores
, mmioflips
;
1143 /* manual wa residency calculations */
1144 struct intel_rps_ei up_ei
, down_ei
;
1147 * Protects RPS/RC6 register access and PCU communication.
1148 * Must be taken after struct_mutex if nested. Note that
1149 * this lock may be held for long periods of time when
1150 * talking to hw - so only take it when talking to hw!
1152 struct mutex hw_lock
;
1155 /* defined intel_pm.c */
1156 extern spinlock_t mchdev_lock
;
1158 struct intel_ilk_power_mgmt
{
1166 unsigned long last_time1
;
1167 unsigned long chipset_power
;
1170 unsigned long gfx_power
;
1177 struct drm_i915_private
;
1178 struct i915_power_well
;
1180 struct i915_power_well_ops
{
1182 * Synchronize the well's hw state to match the current sw state, for
1183 * example enable/disable it based on the current refcount. Called
1184 * during driver init and resume time, possibly after first calling
1185 * the enable/disable handlers.
1187 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1188 struct i915_power_well
*power_well
);
1190 * Enable the well and resources that depend on it (for example
1191 * interrupts located on the well). Called after the 0->1 refcount
1194 void (*enable
)(struct drm_i915_private
*dev_priv
,
1195 struct i915_power_well
*power_well
);
1197 * Disable the well and resources that depend on it. Called after
1198 * the 1->0 refcount transition.
1200 void (*disable
)(struct drm_i915_private
*dev_priv
,
1201 struct i915_power_well
*power_well
);
1202 /* Returns the hw enabled state. */
1203 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1204 struct i915_power_well
*power_well
);
1207 /* Power well structure for haswell */
1208 struct i915_power_well
{
1211 /* power well enable/disable usage count */
1213 /* cached hw enabled state */
1215 unsigned long domains
;
1217 const struct i915_power_well_ops
*ops
;
1220 struct i915_power_domains
{
1222 * Power wells needed for initialization at driver init and suspend
1223 * time are on. They are kept on until after the first modeset.
1227 int power_well_count
;
1230 int domain_use_count
[POWER_DOMAIN_NUM
];
1231 struct i915_power_well
*power_wells
;
1234 #define MAX_L3_SLICES 2
1235 struct intel_l3_parity
{
1236 u32
*remap_info
[MAX_L3_SLICES
];
1237 struct work_struct error_work
;
1241 struct i915_gem_mm
{
1242 /** Memory allocator for GTT stolen memory */
1243 struct drm_mm stolen
;
1244 /** Protects the usage of the GTT stolen memory allocator. This is
1245 * always the inner lock when overlapping with struct_mutex. */
1246 struct mutex stolen_lock
;
1248 /** List of all objects in gtt_space. Used to restore gtt
1249 * mappings on resume */
1250 struct list_head bound_list
;
1252 * List of objects which are not bound to the GTT (thus
1253 * are idle and not used by the GPU) but still have
1254 * (presumably uncached) pages still attached.
1256 struct list_head unbound_list
;
1258 /** Usable portion of the GTT for GEM */
1259 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1261 /** PPGTT used for aliasing the PPGTT with the GTT */
1262 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1264 struct notifier_block oom_notifier
;
1265 struct shrinker shrinker
;
1266 bool shrinker_no_lock_stealing
;
1268 /** LRU list of objects with fence regs on them. */
1269 struct list_head fence_list
;
1272 * We leave the user IRQ off as much as possible,
1273 * but this means that requests will finish and never
1274 * be retired once the system goes idle. Set a timer to
1275 * fire periodically while the ring is running. When it
1276 * fires, go retire requests.
1278 struct delayed_work retire_work
;
1281 * When we detect an idle GPU, we want to turn on
1282 * powersaving features. So once we see that there
1283 * are no more requests outstanding and no more
1284 * arrive within a small period of time, we fire
1285 * off the idle_work.
1287 struct delayed_work idle_work
;
1290 * Are we in a non-interruptible section of code like
1296 * Is the GPU currently considered idle, or busy executing userspace
1297 * requests? Whilst idle, we attempt to power down the hardware and
1298 * display clocks. In order to reduce the effect on performance, there
1299 * is a slight delay before we do so.
1303 /* the indicator for dispatch video commands on two BSD rings */
1304 int bsd_ring_dispatch_index
;
1306 /** Bit 6 swizzling required for X tiling */
1307 uint32_t bit_6_swizzle_x
;
1308 /** Bit 6 swizzling required for Y tiling */
1309 uint32_t bit_6_swizzle_y
;
1311 /* accounting, useful for userland debugging */
1312 spinlock_t object_stat_lock
;
1313 size_t object_memory
;
1317 struct drm_i915_error_state_buf
{
1318 struct drm_i915_private
*i915
;
1327 struct i915_error_state_file_priv
{
1328 struct drm_device
*dev
;
1329 struct drm_i915_error_state
*error
;
1332 struct i915_gpu_error
{
1333 /* For hangcheck timer */
1334 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1335 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1336 /* Hang gpu twice in this window and your context gets banned */
1337 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1339 struct workqueue_struct
*hangcheck_wq
;
1340 struct delayed_work hangcheck_work
;
1342 /* For reset and error_state handling. */
1344 /* Protected by the above dev->gpu_error.lock. */
1345 struct drm_i915_error_state
*first_error
;
1347 unsigned long missed_irq_rings
;
1350 * State variable controlling the reset flow and count
1352 * This is a counter which gets incremented when reset is triggered,
1353 * and again when reset has been handled. So odd values (lowest bit set)
1354 * means that reset is in progress and even values that
1355 * (reset_counter >> 1):th reset was successfully completed.
1357 * If reset is not completed succesfully, the I915_WEDGE bit is
1358 * set meaning that hardware is terminally sour and there is no
1359 * recovery. All waiters on the reset_queue will be woken when
1362 * This counter is used by the wait_seqno code to notice that reset
1363 * event happened and it needs to restart the entire ioctl (since most
1364 * likely the seqno it waited for won't ever signal anytime soon).
1366 * This is important for lock-free wait paths, where no contended lock
1367 * naturally enforces the correct ordering between the bail-out of the
1368 * waiter and the gpu reset work code.
1370 atomic_t reset_counter
;
1372 #define I915_RESET_IN_PROGRESS_FLAG 1
1373 #define I915_WEDGED (1 << 31)
1376 * Waitqueue to signal when the reset has completed. Used by clients
1377 * that wait for dev_priv->mm.wedged to settle.
1379 wait_queue_head_t reset_queue
;
1381 /* Userspace knobs for gpu hang simulation;
1382 * combines both a ring mask, and extra flags
1385 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1386 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1388 /* For missed irq/seqno simulation. */
1389 unsigned int test_irq_rings
;
1391 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1392 bool reload_in_reset
;
1395 enum modeset_restore
{
1396 MODESET_ON_LID_OPEN
,
1401 #define DP_AUX_A 0x40
1402 #define DP_AUX_B 0x10
1403 #define DP_AUX_C 0x20
1404 #define DP_AUX_D 0x30
1406 #define DDC_PIN_B 0x05
1407 #define DDC_PIN_C 0x04
1408 #define DDC_PIN_D 0x06
1410 struct ddi_vbt_port_info
{
1412 * This is an index in the HDMI/DVI DDI buffer translation table.
1413 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1414 * populate this field.
1416 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1417 uint8_t hdmi_level_shift
;
1419 uint8_t supports_dvi
:1;
1420 uint8_t supports_hdmi
:1;
1421 uint8_t supports_dp
:1;
1423 uint8_t alternate_aux_channel
;
1424 uint8_t alternate_ddc_pin
;
1426 uint8_t dp_boost_level
;
1427 uint8_t hdmi_boost_level
;
1430 enum psr_lines_to_wait
{
1431 PSR_0_LINES_TO_WAIT
= 0,
1433 PSR_4_LINES_TO_WAIT
,
1437 struct intel_vbt_data
{
1438 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1439 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1442 unsigned int int_tv_support
:1;
1443 unsigned int lvds_dither
:1;
1444 unsigned int lvds_vbt
:1;
1445 unsigned int int_crt_support
:1;
1446 unsigned int lvds_use_ssc
:1;
1447 unsigned int display_clock_mode
:1;
1448 unsigned int fdi_rx_polarity_inverted
:1;
1449 unsigned int has_mipi
:1;
1451 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1453 enum drrs_support_type drrs_type
;
1458 int edp_preemphasis
;
1460 bool edp_initialized
;
1463 struct edp_power_seq edp_pps
;
1467 bool require_aux_wakeup
;
1469 enum psr_lines_to_wait lines_to_wait
;
1470 int tp1_wakeup_time
;
1471 int tp2_tp3_wakeup_time
;
1477 bool active_low_pwm
;
1478 u8 min_brightness
; /* min_brightness/255 of max */
1485 struct mipi_config
*config
;
1486 struct mipi_pps_data
*pps
;
1490 u8
*sequence
[MIPI_SEQ_MAX
];
1496 union child_device_config
*child_dev
;
1498 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1501 enum intel_ddb_partitioning
{
1503 INTEL_DDB_PART_5_6
, /* IVB+ */
1506 struct intel_wm_level
{
1514 struct ilk_wm_values
{
1515 uint32_t wm_pipe
[3];
1517 uint32_t wm_lp_spr
[3];
1518 uint32_t wm_linetime
[3];
1520 enum intel_ddb_partitioning partitioning
;
1523 struct vlv_pipe_wm
{
1534 struct vlv_wm_values
{
1535 struct vlv_pipe_wm pipe
[3];
1536 struct vlv_sr_wm sr
;
1546 struct skl_ddb_entry
{
1547 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1550 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1552 return entry
->end
- entry
->start
;
1555 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1556 const struct skl_ddb_entry
*e2
)
1558 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1564 struct skl_ddb_allocation
{
1565 struct skl_ddb_entry pipe
[I915_MAX_PIPES
];
1566 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1567 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1570 struct skl_wm_values
{
1571 bool dirty
[I915_MAX_PIPES
];
1572 struct skl_ddb_allocation ddb
;
1573 uint32_t wm_linetime
[I915_MAX_PIPES
];
1574 uint32_t plane
[I915_MAX_PIPES
][I915_MAX_PLANES
][8];
1575 uint32_t plane_trans
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1578 struct skl_wm_level
{
1579 bool plane_en
[I915_MAX_PLANES
];
1580 uint16_t plane_res_b
[I915_MAX_PLANES
];
1581 uint8_t plane_res_l
[I915_MAX_PLANES
];
1585 * This struct helps tracking the state needed for runtime PM, which puts the
1586 * device in PCI D3 state. Notice that when this happens, nothing on the
1587 * graphics device works, even register access, so we don't get interrupts nor
1590 * Every piece of our code that needs to actually touch the hardware needs to
1591 * either call intel_runtime_pm_get or call intel_display_power_get with the
1592 * appropriate power domain.
1594 * Our driver uses the autosuspend delay feature, which means we'll only really
1595 * suspend if we stay with zero refcount for a certain amount of time. The
1596 * default value is currently very conservative (see intel_runtime_pm_enable), but
1597 * it can be changed with the standard runtime PM files from sysfs.
1599 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1600 * goes back to false exactly before we reenable the IRQs. We use this variable
1601 * to check if someone is trying to enable/disable IRQs while they're supposed
1602 * to be disabled. This shouldn't happen and we'll print some error messages in
1605 * For more, read the Documentation/power/runtime_pm.txt.
1607 struct i915_runtime_pm
{
1608 atomic_t wakeref_count
;
1609 atomic_t atomic_seq
;
1614 enum intel_pipe_crc_source
{
1615 INTEL_PIPE_CRC_SOURCE_NONE
,
1616 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1617 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1618 INTEL_PIPE_CRC_SOURCE_PF
,
1619 INTEL_PIPE_CRC_SOURCE_PIPE
,
1620 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1621 INTEL_PIPE_CRC_SOURCE_TV
,
1622 INTEL_PIPE_CRC_SOURCE_DP_B
,
1623 INTEL_PIPE_CRC_SOURCE_DP_C
,
1624 INTEL_PIPE_CRC_SOURCE_DP_D
,
1625 INTEL_PIPE_CRC_SOURCE_AUTO
,
1626 INTEL_PIPE_CRC_SOURCE_MAX
,
1629 struct intel_pipe_crc_entry
{
1634 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1635 struct intel_pipe_crc
{
1637 bool opened
; /* exclusive access to the result file */
1638 struct intel_pipe_crc_entry
*entries
;
1639 enum intel_pipe_crc_source source
;
1641 wait_queue_head_t wq
;
1644 struct i915_frontbuffer_tracking
{
1648 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1655 struct i915_wa_reg
{
1658 /* bitmask representing WA bits */
1662 #define I915_MAX_WA_REGS 16
1664 struct i915_workarounds
{
1665 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1669 struct i915_virtual_gpu
{
1673 struct i915_execbuffer_params
{
1674 struct drm_device
*dev
;
1675 struct drm_file
*file
;
1676 uint32_t dispatch_flags
;
1677 uint32_t args_batch_start_offset
;
1678 uint64_t batch_obj_vm_offset
;
1679 struct intel_engine_cs
*ring
;
1680 struct drm_i915_gem_object
*batch_obj
;
1681 struct intel_context
*ctx
;
1682 struct drm_i915_gem_request
*request
;
1685 /* used in computing the new watermarks state */
1686 struct intel_wm_config
{
1687 unsigned int num_pipes_active
;
1688 bool sprites_enabled
;
1689 bool sprites_scaled
;
1692 struct drm_i915_private
{
1693 struct drm_device
*dev
;
1694 struct kmem_cache
*objects
;
1695 struct kmem_cache
*vmas
;
1696 struct kmem_cache
*requests
;
1698 const struct intel_device_info info
;
1700 int relative_constants_mode
;
1704 struct intel_uncore uncore
;
1706 struct i915_virtual_gpu vgpu
;
1708 struct intel_guc guc
;
1710 struct intel_csr csr
;
1712 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
1714 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1715 * controller on different i2c buses. */
1716 struct mutex gmbus_mutex
;
1719 * Base address of the gmbus and gpio block.
1721 uint32_t gpio_mmio_base
;
1723 /* MMIO base address for MIPI regs */
1724 uint32_t mipi_mmio_base
;
1726 uint32_t psr_mmio_base
;
1728 wait_queue_head_t gmbus_wait_queue
;
1730 struct pci_dev
*bridge_dev
;
1731 struct intel_engine_cs ring
[I915_NUM_RINGS
];
1732 struct drm_i915_gem_object
*semaphore_obj
;
1733 uint32_t last_seqno
, next_seqno
;
1735 struct drm_dma_handle
*status_page_dmah
;
1736 struct resource mch_res
;
1738 /* protects the irq masks */
1739 spinlock_t irq_lock
;
1741 /* protects the mmio flip data */
1742 spinlock_t mmio_flip_lock
;
1744 bool display_irqs_enabled
;
1746 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1747 struct pm_qos_request pm_qos
;
1749 /* Sideband mailbox protection */
1750 struct mutex sb_lock
;
1752 /** Cached value of IMR to avoid reads in updating the bitfield */
1755 u32 de_irq_mask
[I915_MAX_PIPES
];
1760 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1762 struct i915_hotplug hotplug
;
1763 struct i915_fbc fbc
;
1764 struct i915_drrs drrs
;
1765 struct intel_opregion opregion
;
1766 struct intel_vbt_data vbt
;
1768 bool preserve_bios_swizzle
;
1771 struct intel_overlay
*overlay
;
1773 /* backlight registers and fields in struct intel_panel */
1774 struct mutex backlight_lock
;
1777 bool no_aux_handshake
;
1779 /* protects panel power sequencer state */
1780 struct mutex pps_mutex
;
1782 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1783 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1785 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1786 unsigned int skl_boot_cdclk
;
1787 unsigned int cdclk_freq
, max_cdclk_freq
;
1788 unsigned int max_dotclk_freq
;
1789 unsigned int hpll_freq
;
1790 unsigned int czclk_freq
;
1793 * wq - Driver workqueue for GEM.
1795 * NOTE: Work items scheduled here are not allowed to grab any modeset
1796 * locks, for otherwise the flushing done in the pageflip code will
1797 * result in deadlocks.
1799 struct workqueue_struct
*wq
;
1801 /* Display functions */
1802 struct drm_i915_display_funcs display
;
1804 /* PCH chipset type */
1805 enum intel_pch pch_type
;
1806 unsigned short pch_id
;
1808 unsigned long quirks
;
1810 enum modeset_restore modeset_restore
;
1811 struct mutex modeset_restore_lock
;
1813 struct list_head vm_list
; /* Global list of all address spaces */
1814 struct i915_gtt gtt
; /* VM representing the global address space */
1816 struct i915_gem_mm mm
;
1817 DECLARE_HASHTABLE(mm_structs
, 7);
1818 struct mutex mm_lock
;
1820 /* Kernel Modesetting */
1822 struct sdvo_device_mapping sdvo_mappings
[2];
1824 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1825 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1826 wait_queue_head_t pending_flip_queue
;
1828 #ifdef CONFIG_DEBUG_FS
1829 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1832 int num_shared_dpll
;
1833 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1834 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1836 struct i915_workarounds workarounds
;
1838 /* Reclocking support */
1839 bool render_reclock_avail
;
1841 struct i915_frontbuffer_tracking fb_tracking
;
1845 bool mchbar_need_disable
;
1847 struct intel_l3_parity l3_parity
;
1849 /* Cannot be determined by PCIID. You must always read a register. */
1852 /* gen6+ rps state */
1853 struct intel_gen6_power_mgmt rps
;
1855 /* ilk-only ips/rps state. Everything in here is protected by the global
1856 * mchdev_lock in intel_pm.c */
1857 struct intel_ilk_power_mgmt ips
;
1859 struct i915_power_domains power_domains
;
1861 struct i915_psr psr
;
1863 struct i915_gpu_error gpu_error
;
1865 struct drm_i915_gem_object
*vlv_pctx
;
1867 #ifdef CONFIG_DRM_FBDEV_EMULATION
1868 /* list of fbdev register on this device */
1869 struct intel_fbdev
*fbdev
;
1870 struct work_struct fbdev_suspend_work
;
1873 struct drm_property
*broadcast_rgb_property
;
1874 struct drm_property
*force_audio_property
;
1876 /* hda/i915 audio component */
1877 struct i915_audio_component
*audio_component
;
1878 bool audio_component_registered
;
1880 * av_mutex - mutex for audio/video sync
1883 struct mutex av_mutex
;
1885 uint32_t hw_context_size
;
1886 struct list_head context_list
;
1890 u32 chv_phy_control
;
1893 bool suspended_to_idle
;
1894 struct i915_suspend_saved_registers regfile
;
1895 struct vlv_s0ix_state vlv_s0ix_state
;
1899 * Raw watermark latency values:
1900 * in 0.1us units for WM0,
1901 * in 0.5us units for WM1+.
1904 uint16_t pri_latency
[5];
1906 uint16_t spr_latency
[5];
1908 uint16_t cur_latency
[5];
1910 * Raw watermark memory latency values
1911 * for SKL for all 8 levels
1914 uint16_t skl_latency
[8];
1916 /* Committed wm config */
1917 struct intel_wm_config config
;
1920 * The skl_wm_values structure is a bit too big for stack
1921 * allocation, so we keep the staging struct where we store
1922 * intermediate results here instead.
1924 struct skl_wm_values skl_results
;
1926 /* current hardware state */
1928 struct ilk_wm_values hw
;
1929 struct skl_wm_values skl_hw
;
1930 struct vlv_wm_values vlv
;
1936 struct i915_runtime_pm pm
;
1938 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1940 int (*execbuf_submit
)(struct i915_execbuffer_params
*params
,
1941 struct drm_i915_gem_execbuffer2
*args
,
1942 struct list_head
*vmas
);
1943 int (*init_rings
)(struct drm_device
*dev
);
1944 void (*cleanup_ring
)(struct intel_engine_cs
*ring
);
1945 void (*stop_ring
)(struct intel_engine_cs
*ring
);
1948 bool edp_low_vswing
;
1950 /* perform PHY state sanity checks? */
1951 bool chv_phy_assert
[2];
1953 struct intel_encoder
*dig_port_map
[I915_MAX_PORTS
];
1956 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1957 * will be rejected. Instead look for a better place.
1961 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1963 return dev
->dev_private
;
1966 static inline struct drm_i915_private
*dev_to_i915(struct device
*dev
)
1968 return to_i915(dev_get_drvdata(dev
));
1971 static inline struct drm_i915_private
*guc_to_i915(struct intel_guc
*guc
)
1973 return container_of(guc
, struct drm_i915_private
, guc
);
1976 /* Iterate over initialised rings */
1977 #define for_each_ring(ring__, dev_priv__, i__) \
1978 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1979 for_each_if ((((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))))
1981 enum hdmi_force_audio
{
1982 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1983 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1984 HDMI_AUDIO_AUTO
, /* trust EDID */
1985 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1988 #define I915_GTT_OFFSET_NONE ((u32)-1)
1990 struct drm_i915_gem_object_ops
{
1991 /* Interface between the GEM object and its backing storage.
1992 * get_pages() is called once prior to the use of the associated set
1993 * of pages before to binding them into the GTT, and put_pages() is
1994 * called after we no longer need them. As we expect there to be
1995 * associated cost with migrating pages between the backing storage
1996 * and making them available for the GPU (e.g. clflush), we may hold
1997 * onto the pages after they are no longer referenced by the GPU
1998 * in case they may be used again shortly (for example migrating the
1999 * pages to a different memory domain within the GTT). put_pages()
2000 * will therefore most likely be called when the object itself is
2001 * being released or under memory pressure (where we attempt to
2002 * reap pages for the shrinker).
2004 int (*get_pages
)(struct drm_i915_gem_object
*);
2005 void (*put_pages
)(struct drm_i915_gem_object
*);
2006 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
2007 void (*release
)(struct drm_i915_gem_object
*);
2011 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2012 * considered to be the frontbuffer for the given plane interface-wise. This
2013 * doesn't mean that the hw necessarily already scans it out, but that any
2014 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2016 * We have one bit per pipe and per scanout plane type.
2018 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2019 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2020 #define INTEL_FRONTBUFFER_BITS \
2021 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2022 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2023 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2024 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2025 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2026 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2027 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2028 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2029 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2030 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2031 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2033 struct drm_i915_gem_object
{
2034 struct drm_gem_object base
;
2036 const struct drm_i915_gem_object_ops
*ops
;
2038 /** List of VMAs backed by this object */
2039 struct list_head vma_list
;
2041 /** Stolen memory for this object, instead of being backed by shmem. */
2042 struct drm_mm_node
*stolen
;
2043 struct list_head global_list
;
2045 struct list_head ring_list
[I915_NUM_RINGS
];
2046 /** Used in execbuf to temporarily hold a ref */
2047 struct list_head obj_exec_link
;
2049 struct list_head batch_pool_link
;
2052 * This is set if the object is on the active lists (has pending
2053 * rendering and so a non-zero seqno), and is not set if it i s on
2054 * inactive (ready to be unbound) list.
2056 unsigned int active
:I915_NUM_RINGS
;
2059 * This is set if the object has been written to since last bound
2062 unsigned int dirty
:1;
2065 * Fence register bits (if any) for this object. Will be set
2066 * as needed when mapped into the GTT.
2067 * Protected by dev->struct_mutex.
2069 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
2072 * Advice: are the backing pages purgeable?
2074 unsigned int madv
:2;
2077 * Current tiling mode for the object.
2079 unsigned int tiling_mode
:2;
2081 * Whether the tiling parameters for the currently associated fence
2082 * register have changed. Note that for the purposes of tracking
2083 * tiling changes we also treat the unfenced register, the register
2084 * slot that the object occupies whilst it executes a fenced
2085 * command (such as BLT on gen2/3), as a "fence".
2087 unsigned int fence_dirty
:1;
2090 * Is the object at the current location in the gtt mappable and
2091 * fenceable? Used to avoid costly recalculations.
2093 unsigned int map_and_fenceable
:1;
2096 * Whether the current gtt mapping needs to be mappable (and isn't just
2097 * mappable by accident). Track pin and fault separate for a more
2098 * accurate mappable working set.
2100 unsigned int fault_mappable
:1;
2103 * Is the object to be mapped as read-only to the GPU
2104 * Only honoured if hardware has relevant pte bit
2106 unsigned long gt_ro
:1;
2107 unsigned int cache_level
:3;
2108 unsigned int cache_dirty
:1;
2110 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
2112 unsigned int pin_display
;
2114 struct sg_table
*pages
;
2115 int pages_pin_count
;
2117 struct scatterlist
*sg
;
2121 /* prime dma-buf support */
2122 void *dma_buf_vmapping
;
2125 /** Breadcrumb of last rendering to the buffer.
2126 * There can only be one writer, but we allow for multiple readers.
2127 * If there is a writer that necessarily implies that all other
2128 * read requests are complete - but we may only be lazily clearing
2129 * the read requests. A read request is naturally the most recent
2130 * request on a ring, so we may have two different write and read
2131 * requests on one ring where the write request is older than the
2132 * read request. This allows for the CPU to read from an active
2133 * buffer by only waiting for the write to complete.
2135 struct drm_i915_gem_request
*last_read_req
[I915_NUM_RINGS
];
2136 struct drm_i915_gem_request
*last_write_req
;
2137 /** Breadcrumb of last fenced GPU access to the buffer. */
2138 struct drm_i915_gem_request
*last_fenced_req
;
2140 /** Current tiling stride for the object, if it's tiled. */
2143 /** References from framebuffers, locks out tiling changes. */
2144 unsigned long framebuffer_references
;
2146 /** Record of address bit 17 of each page at last unbind. */
2147 unsigned long *bit_17
;
2150 /** for phy allocated objects */
2151 struct drm_dma_handle
*phys_handle
;
2153 struct i915_gem_userptr
{
2155 unsigned read_only
:1;
2156 unsigned workers
:4;
2157 #define I915_GEM_USERPTR_MAX_WORKERS 15
2159 struct i915_mm_struct
*mm
;
2160 struct i915_mmu_object
*mmu_object
;
2161 struct work_struct
*work
;
2165 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2167 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
2168 struct drm_i915_gem_object
*new,
2169 unsigned frontbuffer_bits
);
2172 * Request queue structure.
2174 * The request queue allows us to note sequence numbers that have been emitted
2175 * and may be associated with active buffers to be retired.
2177 * By keeping this list, we can avoid having to do questionable sequence
2178 * number comparisons on buffer last_read|write_seqno. It also allows an
2179 * emission time to be associated with the request for tracking how far ahead
2180 * of the GPU the submission is.
2182 * The requests are reference counted, so upon creation they should have an
2183 * initial reference taken using kref_init
2185 struct drm_i915_gem_request
{
2188 /** On Which ring this request was generated */
2189 struct drm_i915_private
*i915
;
2190 struct intel_engine_cs
*ring
;
2192 /** GEM sequence number associated with the previous request,
2193 * when the HWS breadcrumb is equal to this the GPU is processing
2198 /** GEM sequence number associated with this request,
2199 * when the HWS breadcrumb is equal or greater than this the GPU
2200 * has finished processing this request.
2204 /** Position in the ringbuffer of the start of the request */
2208 * Position in the ringbuffer of the start of the postfix.
2209 * This is required to calculate the maximum available ringbuffer
2210 * space without overwriting the postfix.
2214 /** Position in the ringbuffer of the end of the whole request */
2218 * Context and ring buffer related to this request
2219 * Contexts are refcounted, so when this request is associated with a
2220 * context, we must increment the context's refcount, to guarantee that
2221 * it persists while any request is linked to it. Requests themselves
2222 * are also refcounted, so the request will only be freed when the last
2223 * reference to it is dismissed, and the code in
2224 * i915_gem_request_free() will then decrement the refcount on the
2227 struct intel_context
*ctx
;
2228 struct intel_ringbuffer
*ringbuf
;
2230 /** Batch buffer related to this request if any (used for
2231 error state dump only) */
2232 struct drm_i915_gem_object
*batch_obj
;
2234 /** Time at which this request was emitted, in jiffies. */
2235 unsigned long emitted_jiffies
;
2237 /** global list entry for this request */
2238 struct list_head list
;
2240 struct drm_i915_file_private
*file_priv
;
2241 /** file_priv list entry for this request */
2242 struct list_head client_list
;
2244 /** process identifier submitting this request */
2248 * The ELSP only accepts two elements at a time, so we queue
2249 * context/tail pairs on a given queue (ring->execlist_queue) until the
2250 * hardware is available. The queue serves a double purpose: we also use
2251 * it to keep track of the up to 2 contexts currently in the hardware
2252 * (usually one in execution and the other queued up by the GPU): We
2253 * only remove elements from the head of the queue when the hardware
2254 * informs us that an element has been completed.
2256 * All accesses to the queue are mediated by a spinlock
2257 * (ring->execlist_lock).
2260 /** Execlist link in the submission queue.*/
2261 struct list_head execlist_link
;
2263 /** Execlists no. of times this request has been sent to the ELSP */
2268 int i915_gem_request_alloc(struct intel_engine_cs
*ring
,
2269 struct intel_context
*ctx
,
2270 struct drm_i915_gem_request
**req_out
);
2271 void i915_gem_request_cancel(struct drm_i915_gem_request
*req
);
2272 void i915_gem_request_free(struct kref
*req_ref
);
2273 int i915_gem_request_add_to_client(struct drm_i915_gem_request
*req
,
2274 struct drm_file
*file
);
2276 static inline uint32_t
2277 i915_gem_request_get_seqno(struct drm_i915_gem_request
*req
)
2279 return req
? req
->seqno
: 0;
2282 static inline struct intel_engine_cs
*
2283 i915_gem_request_get_ring(struct drm_i915_gem_request
*req
)
2285 return req
? req
->ring
: NULL
;
2288 static inline struct drm_i915_gem_request
*
2289 i915_gem_request_reference(struct drm_i915_gem_request
*req
)
2292 kref_get(&req
->ref
);
2297 i915_gem_request_unreference(struct drm_i915_gem_request
*req
)
2299 WARN_ON(!mutex_is_locked(&req
->ring
->dev
->struct_mutex
));
2300 kref_put(&req
->ref
, i915_gem_request_free
);
2304 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request
*req
)
2306 struct drm_device
*dev
;
2311 dev
= req
->ring
->dev
;
2312 if (kref_put_mutex(&req
->ref
, i915_gem_request_free
, &dev
->struct_mutex
))
2313 mutex_unlock(&dev
->struct_mutex
);
2316 static inline void i915_gem_request_assign(struct drm_i915_gem_request
**pdst
,
2317 struct drm_i915_gem_request
*src
)
2320 i915_gem_request_reference(src
);
2323 i915_gem_request_unreference(*pdst
);
2329 * XXX: i915_gem_request_completed should be here but currently needs the
2330 * definition of i915_seqno_passed() which is below. It will be moved in
2331 * a later patch when the call to i915_seqno_passed() is obsoleted...
2335 * A command that requires special handling by the command parser.
2337 struct drm_i915_cmd_descriptor
{
2339 * Flags describing how the command parser processes the command.
2341 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2342 * a length mask if not set
2343 * CMD_DESC_SKIP: The command is allowed but does not follow the
2344 * standard length encoding for the opcode range in
2346 * CMD_DESC_REJECT: The command is never allowed
2347 * CMD_DESC_REGISTER: The command should be checked against the
2348 * register whitelist for the appropriate ring
2349 * CMD_DESC_MASTER: The command is allowed if the submitting process
2353 #define CMD_DESC_FIXED (1<<0)
2354 #define CMD_DESC_SKIP (1<<1)
2355 #define CMD_DESC_REJECT (1<<2)
2356 #define CMD_DESC_REGISTER (1<<3)
2357 #define CMD_DESC_BITMASK (1<<4)
2358 #define CMD_DESC_MASTER (1<<5)
2361 * The command's unique identification bits and the bitmask to get them.
2362 * This isn't strictly the opcode field as defined in the spec and may
2363 * also include type, subtype, and/or subop fields.
2371 * The command's length. The command is either fixed length (i.e. does
2372 * not include a length field) or has a length field mask. The flag
2373 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2374 * a length mask. All command entries in a command table must include
2375 * length information.
2383 * Describes where to find a register address in the command to check
2384 * against the ring's register whitelist. Only valid if flags has the
2385 * CMD_DESC_REGISTER bit set.
2387 * A non-zero step value implies that the command may access multiple
2388 * registers in sequence (e.g. LRI), in that case step gives the
2389 * distance in dwords between individual offset fields.
2397 #define MAX_CMD_DESC_BITMASKS 3
2399 * Describes command checks where a particular dword is masked and
2400 * compared against an expected value. If the command does not match
2401 * the expected value, the parser rejects it. Only valid if flags has
2402 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2405 * If the check specifies a non-zero condition_mask then the parser
2406 * only performs the check when the bits specified by condition_mask
2413 u32 condition_offset
;
2415 } bits
[MAX_CMD_DESC_BITMASKS
];
2419 * A table of commands requiring special handling by the command parser.
2421 * Each ring has an array of tables. Each table consists of an array of command
2422 * descriptors, which must be sorted with command opcodes in ascending order.
2424 struct drm_i915_cmd_table
{
2425 const struct drm_i915_cmd_descriptor
*table
;
2429 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2430 #define __I915__(p) ({ \
2431 struct drm_i915_private *__p; \
2432 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2433 __p = (struct drm_i915_private *)p; \
2434 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2435 __p = to_i915((struct drm_device *)p); \
2440 #define INTEL_INFO(p) (&__I915__(p)->info)
2441 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2442 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2444 #define REVID_FOREVER 0xff
2446 * Return true if revision is in range [since,until] inclusive.
2448 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2450 #define IS_REVID(p, since, until) \
2451 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2453 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2454 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2455 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2456 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2457 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2458 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2459 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2460 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2461 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2462 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2463 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2464 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2465 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2466 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2467 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2468 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2469 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2470 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2471 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2472 INTEL_DEVID(dev) == 0x0152 || \
2473 INTEL_DEVID(dev) == 0x015a)
2474 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2475 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2476 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2477 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
2478 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2479 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2480 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2481 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2482 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2483 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2484 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2485 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2486 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2487 (INTEL_DEVID(dev) & 0xf) == 0xe))
2488 /* ULX machines are also considered ULT. */
2489 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2490 (INTEL_DEVID(dev) & 0xf) == 0xe)
2491 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2492 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2493 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2494 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2495 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2496 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2497 /* ULX machines are also considered ULT. */
2498 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2499 INTEL_DEVID(dev) == 0x0A1E)
2500 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2501 INTEL_DEVID(dev) == 0x1913 || \
2502 INTEL_DEVID(dev) == 0x1916 || \
2503 INTEL_DEVID(dev) == 0x1921 || \
2504 INTEL_DEVID(dev) == 0x1926)
2505 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2506 INTEL_DEVID(dev) == 0x1915 || \
2507 INTEL_DEVID(dev) == 0x191E)
2508 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2509 INTEL_DEVID(dev) == 0x5913 || \
2510 INTEL_DEVID(dev) == 0x5916 || \
2511 INTEL_DEVID(dev) == 0x5921 || \
2512 INTEL_DEVID(dev) == 0x5926)
2513 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2514 INTEL_DEVID(dev) == 0x5915 || \
2515 INTEL_DEVID(dev) == 0x591E)
2516 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2517 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2518 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2519 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2521 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2523 #define SKL_REVID_A0 0x0
2524 #define SKL_REVID_B0 0x1
2525 #define SKL_REVID_C0 0x2
2526 #define SKL_REVID_D0 0x3
2527 #define SKL_REVID_E0 0x4
2528 #define SKL_REVID_F0 0x5
2530 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2532 #define BXT_REVID_A0 0x0
2533 #define BXT_REVID_A1 0x1
2534 #define BXT_REVID_B0 0x3
2535 #define BXT_REVID_C0 0x9
2537 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2540 * The genX designation typically refers to the render engine, so render
2541 * capability related checks should use IS_GEN, while display and other checks
2542 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2545 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2546 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2547 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2548 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2549 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2550 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2551 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2552 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2554 #define RENDER_RING (1<<RCS)
2555 #define BSD_RING (1<<VCS)
2556 #define BLT_RING (1<<BCS)
2557 #define VEBOX_RING (1<<VECS)
2558 #define BSD2_RING (1<<VCS2)
2559 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2560 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2561 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2562 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2563 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2564 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2565 __I915__(dev)->ellc_size)
2566 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2568 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2569 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2570 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2571 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2572 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2574 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2575 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2577 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2578 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2580 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2581 * even when in MSI mode. This results in spurious interrupt warnings if the
2582 * legacy irq no. is shared with another device. The kernel then disables that
2583 * interrupt source and so prevents the other device from working properly.
2585 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2586 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2588 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2589 * rows, which changed the alignment requirements and fence programming.
2591 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2593 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2594 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2596 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2597 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2598 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2600 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2602 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2603 INTEL_INFO(dev)->gen >= 9)
2605 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2606 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2607 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2608 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2609 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2610 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2611 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2612 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2614 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2615 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2617 #define HAS_CSR(dev) (IS_GEN9(dev))
2619 #define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2620 #define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2622 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2623 INTEL_INFO(dev)->gen >= 8)
2625 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2626 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2629 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2630 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2631 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2632 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2633 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2634 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2635 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2636 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2637 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2638 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2640 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2641 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2642 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2643 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2644 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2645 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2646 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2647 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2648 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2650 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2651 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2653 /* DPF == dynamic parity feature */
2654 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2655 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2657 #define GT_FREQUENCY_MULTIPLIER 50
2658 #define GEN9_FREQ_SCALER 3
2660 #include "i915_trace.h"
2662 extern const struct drm_ioctl_desc i915_ioctls
[];
2663 extern int i915_max_ioctl
;
2665 extern int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
);
2666 extern int i915_resume_switcheroo(struct drm_device
*dev
);
2669 struct i915_params
{
2671 int panel_ignore_lid
;
2673 int lvds_channel_mode
;
2675 int vbt_sdvo_panel_type
;
2680 int enable_execlists
;
2682 unsigned int preliminary_hw_support
;
2683 int disable_power_well
;
2685 int invert_brightness
;
2686 int enable_cmd_parser
;
2687 /* leave bools at the end to not create holes */
2688 bool enable_hangcheck
;
2690 bool prefault_disable
;
2691 bool load_detect_test
;
2693 bool disable_display
;
2694 bool disable_vtd_wa
;
2695 bool enable_guc_submission
;
2699 bool verbose_state_checks
;
2700 bool nuclear_pageflip
;
2703 extern struct i915_params i915 __read_mostly
;
2706 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
2707 extern int i915_driver_unload(struct drm_device
*);
2708 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
);
2709 extern void i915_driver_lastclose(struct drm_device
* dev
);
2710 extern void i915_driver_preclose(struct drm_device
*dev
,
2711 struct drm_file
*file
);
2712 extern void i915_driver_postclose(struct drm_device
*dev
,
2713 struct drm_file
*file
);
2714 #ifdef CONFIG_COMPAT
2715 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2718 extern int intel_gpu_reset(struct drm_device
*dev
);
2719 extern bool intel_has_gpu_reset(struct drm_device
*dev
);
2720 extern int i915_reset(struct drm_device
*dev
);
2721 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2722 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2723 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2724 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2725 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2727 /* intel_hotplug.c */
2728 void intel_hpd_irq_handler(struct drm_device
*dev
, u32 pin_mask
, u32 long_mask
);
2729 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2730 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
2731 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2732 bool intel_hpd_pin_to_port(enum hpd_pin pin
, enum port
*port
);
2735 void i915_queue_hangcheck(struct drm_device
*dev
);
2737 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2738 const char *fmt
, ...);
2740 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2741 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2742 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2744 extern void intel_uncore_sanitize(struct drm_device
*dev
);
2745 extern void intel_uncore_early_sanitize(struct drm_device
*dev
,
2746 bool restore_forcewake
);
2747 extern void intel_uncore_init(struct drm_device
*dev
);
2748 extern void intel_uncore_check_errors(struct drm_device
*dev
);
2749 extern void intel_uncore_fini(struct drm_device
*dev
);
2750 extern void intel_uncore_forcewake_reset(struct drm_device
*dev
, bool restore
);
2751 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
2752 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
2753 enum forcewake_domains domains
);
2754 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
2755 enum forcewake_domains domains
);
2756 /* Like above but the caller must manage the uncore.lock itself.
2757 * Must be used with I915_READ_FW and friends.
2759 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
2760 enum forcewake_domains domains
);
2761 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
2762 enum forcewake_domains domains
);
2763 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
2764 static inline bool intel_vgpu_active(struct drm_device
*dev
)
2766 return to_i915(dev
)->vgpu
.active
;
2770 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2774 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2777 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2778 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2779 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
2782 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
2783 uint32_t interrupt_mask
,
2784 uint32_t enabled_irq_mask
);
2786 ilk_enable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2788 ilk_update_display_irq(dev_priv
, bits
, bits
);
2791 ilk_disable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2793 ilk_update_display_irq(dev_priv
, bits
, 0);
2795 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
2797 uint32_t interrupt_mask
,
2798 uint32_t enabled_irq_mask
);
2799 static inline void bdw_enable_pipe_irq(struct drm_i915_private
*dev_priv
,
2800 enum pipe pipe
, uint32_t bits
)
2802 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, bits
);
2804 static inline void bdw_disable_pipe_irq(struct drm_i915_private
*dev_priv
,
2805 enum pipe pipe
, uint32_t bits
)
2807 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, 0);
2809 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
2810 uint32_t interrupt_mask
,
2811 uint32_t enabled_irq_mask
);
2813 ibx_enable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2815 ibx_display_interrupt_update(dev_priv
, bits
, bits
);
2818 ibx_disable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2820 ibx_display_interrupt_update(dev_priv
, bits
, 0);
2825 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2826 struct drm_file
*file_priv
);
2827 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2828 struct drm_file
*file_priv
);
2829 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2830 struct drm_file
*file_priv
);
2831 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2832 struct drm_file
*file_priv
);
2833 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2834 struct drm_file
*file_priv
);
2835 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2836 struct drm_file
*file_priv
);
2837 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2838 struct drm_file
*file_priv
);
2839 void i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
2840 struct drm_i915_gem_request
*req
);
2841 void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params
*params
);
2842 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params
*params
,
2843 struct drm_i915_gem_execbuffer2
*args
,
2844 struct list_head
*vmas
);
2845 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2846 struct drm_file
*file_priv
);
2847 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2848 struct drm_file
*file_priv
);
2849 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2850 struct drm_file
*file_priv
);
2851 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2852 struct drm_file
*file
);
2853 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2854 struct drm_file
*file
);
2855 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2856 struct drm_file
*file_priv
);
2857 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2858 struct drm_file
*file_priv
);
2859 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2860 struct drm_file
*file_priv
);
2861 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2862 struct drm_file
*file_priv
);
2863 int i915_gem_init_userptr(struct drm_device
*dev
);
2864 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2865 struct drm_file
*file
);
2866 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2867 struct drm_file
*file_priv
);
2868 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2869 struct drm_file
*file_priv
);
2870 void i915_gem_load(struct drm_device
*dev
);
2871 void *i915_gem_object_alloc(struct drm_device
*dev
);
2872 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2873 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2874 const struct drm_i915_gem_object_ops
*ops
);
2875 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
2877 struct drm_i915_gem_object
*i915_gem_object_create_from_data(
2878 struct drm_device
*dev
, const void *data
, size_t size
);
2879 void i915_gem_free_object(struct drm_gem_object
*obj
);
2880 void i915_gem_vma_destroy(struct i915_vma
*vma
);
2882 /* Flags used by pin/bind&friends. */
2883 #define PIN_MAPPABLE (1<<0)
2884 #define PIN_NONBLOCK (1<<1)
2885 #define PIN_GLOBAL (1<<2)
2886 #define PIN_OFFSET_BIAS (1<<3)
2887 #define PIN_USER (1<<4)
2888 #define PIN_UPDATE (1<<5)
2889 #define PIN_ZONE_4G (1<<6)
2890 #define PIN_HIGH (1<<7)
2891 #define PIN_OFFSET_FIXED (1<<8)
2892 #define PIN_OFFSET_MASK (~4095)
2894 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
2895 struct i915_address_space
*vm
,
2899 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
2900 const struct i915_ggtt_view
*view
,
2904 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
2906 void __i915_vma_set_map_and_fenceable(struct i915_vma
*vma
);
2907 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
2909 * BEWARE: Do not use the function below unless you can _absolutely_
2910 * _guarantee_ VMA in question is _not in use_ anywhere.
2912 int __must_check
__i915_vma_unbind_no_wait(struct i915_vma
*vma
);
2913 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
2914 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
2915 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2917 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
2918 int *needs_clflush
);
2920 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2922 static inline int __sg_page_count(struct scatterlist
*sg
)
2924 return sg
->length
>> PAGE_SHIFT
;
2928 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
, int n
);
2930 static inline struct page
*
2931 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
2933 if (WARN_ON(n
>= obj
->base
.size
>> PAGE_SHIFT
))
2936 if (n
< obj
->get_page
.last
) {
2937 obj
->get_page
.sg
= obj
->pages
->sgl
;
2938 obj
->get_page
.last
= 0;
2941 while (obj
->get_page
.last
+ __sg_page_count(obj
->get_page
.sg
) <= n
) {
2942 obj
->get_page
.last
+= __sg_page_count(obj
->get_page
.sg
++);
2943 if (unlikely(sg_is_chain(obj
->get_page
.sg
)))
2944 obj
->get_page
.sg
= sg_chain_ptr(obj
->get_page
.sg
);
2947 return nth_page(sg_page(obj
->get_page
.sg
), n
- obj
->get_page
.last
);
2950 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2952 BUG_ON(obj
->pages
== NULL
);
2953 obj
->pages_pin_count
++;
2955 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2957 BUG_ON(obj
->pages_pin_count
== 0);
2958 obj
->pages_pin_count
--;
2961 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
2962 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2963 struct intel_engine_cs
*to
,
2964 struct drm_i915_gem_request
**to_req
);
2965 void i915_vma_move_to_active(struct i915_vma
*vma
,
2966 struct drm_i915_gem_request
*req
);
2967 int i915_gem_dumb_create(struct drm_file
*file_priv
,
2968 struct drm_device
*dev
,
2969 struct drm_mode_create_dumb
*args
);
2970 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
2971 uint32_t handle
, uint64_t *offset
);
2973 * Returns true if seq1 is later than seq2.
2976 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
2978 return (int32_t)(seq1
- seq2
) >= 0;
2981 static inline bool i915_gem_request_started(struct drm_i915_gem_request
*req
,
2982 bool lazy_coherency
)
2984 u32 seqno
= req
->ring
->get_seqno(req
->ring
, lazy_coherency
);
2985 return i915_seqno_passed(seqno
, req
->previous_seqno
);
2988 static inline bool i915_gem_request_completed(struct drm_i915_gem_request
*req
,
2989 bool lazy_coherency
)
2991 u32 seqno
= req
->ring
->get_seqno(req
->ring
, lazy_coherency
);
2992 return i915_seqno_passed(seqno
, req
->seqno
);
2995 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
2996 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
2998 struct drm_i915_gem_request
*
2999 i915_gem_find_active_request(struct intel_engine_cs
*ring
);
3001 bool i915_gem_retire_requests(struct drm_device
*dev
);
3002 void i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
);
3003 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
3004 bool interruptible
);
3006 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
3008 return unlikely(atomic_read(&error
->reset_counter
)
3009 & (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
3012 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
3014 return atomic_read(&error
->reset_counter
) & I915_WEDGED
;
3017 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
3019 return ((atomic_read(&error
->reset_counter
) & ~I915_WEDGED
) + 1) / 2;
3022 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private
*dev_priv
)
3024 return dev_priv
->gpu_error
.stop_rings
== 0 ||
3025 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_BAN
;
3028 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private
*dev_priv
)
3030 return dev_priv
->gpu_error
.stop_rings
== 0 ||
3031 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_WARN
;
3034 void i915_gem_reset(struct drm_device
*dev
);
3035 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
3036 int __must_check
i915_gem_init(struct drm_device
*dev
);
3037 int i915_gem_init_rings(struct drm_device
*dev
);
3038 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
3039 int i915_gem_l3_remap(struct drm_i915_gem_request
*req
, int slice
);
3040 void i915_gem_init_swizzling(struct drm_device
*dev
);
3041 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
3042 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
3043 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
3044 void __i915_add_request(struct drm_i915_gem_request
*req
,
3045 struct drm_i915_gem_object
*batch_obj
,
3047 #define i915_add_request(req) \
3048 __i915_add_request(req, NULL, true)
3049 #define i915_add_request_no_flush(req) \
3050 __i915_add_request(req, NULL, false)
3051 int __i915_wait_request(struct drm_i915_gem_request
*req
,
3052 unsigned reset_counter
,
3055 struct intel_rps_client
*rps
);
3056 int __must_check
i915_wait_request(struct drm_i915_gem_request
*req
);
3057 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
3059 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
3062 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
3065 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
3067 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3069 const struct i915_ggtt_view
*view
);
3070 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
3071 const struct i915_ggtt_view
*view
);
3072 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
3074 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
3075 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3078 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
3080 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
3081 int tiling_mode
, bool fenced
);
3083 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3084 enum i915_cache_level cache_level
);
3086 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3087 struct dma_buf
*dma_buf
);
3089 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3090 struct drm_gem_object
*gem_obj
, int flags
);
3092 u64
i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
3093 const struct i915_ggtt_view
*view
);
3094 u64
i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
3095 struct i915_address_space
*vm
);
3097 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*o
)
3099 return i915_gem_obj_ggtt_offset_view(o
, &i915_ggtt_view_normal
);
3102 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
3103 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
3104 const struct i915_ggtt_view
*view
);
3105 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
3106 struct i915_address_space
*vm
);
3108 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
3109 struct i915_address_space
*vm
);
3111 i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
3112 struct i915_address_space
*vm
);
3114 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
3115 const struct i915_ggtt_view
*view
);
3118 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3119 struct i915_address_space
*vm
);
3121 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
3122 const struct i915_ggtt_view
*view
);
3124 static inline struct i915_vma
*
3125 i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
)
3127 return i915_gem_obj_to_ggtt_view(obj
, &i915_ggtt_view_normal
);
3129 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
);
3131 /* Some GGTT VM helpers */
3132 #define i915_obj_to_ggtt(obj) \
3133 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
3134 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
3136 struct i915_address_space
*ggtt
=
3137 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
3141 static inline struct i915_hw_ppgtt
*
3142 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3144 WARN_ON(i915_is_ggtt(vm
));
3146 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3150 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
3152 return i915_gem_obj_ggtt_bound_view(obj
, &i915_ggtt_view_normal
);
3155 static inline unsigned long
3156 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
3158 return i915_gem_obj_size(obj
, i915_obj_to_ggtt(obj
));
3161 static inline int __must_check
3162 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
3166 return i915_gem_object_pin(obj
, i915_obj_to_ggtt(obj
),
3167 alignment
, flags
| PIN_GLOBAL
);
3171 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
3173 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj
));
3176 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
3177 const struct i915_ggtt_view
*view
);
3179 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
)
3181 i915_gem_object_ggtt_unpin_view(obj
, &i915_ggtt_view_normal
);
3184 /* i915_gem_fence.c */
3185 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
3186 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
3188 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
3189 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
3191 void i915_gem_restore_fences(struct drm_device
*dev
);
3193 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
3194 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3195 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3197 /* i915_gem_context.c */
3198 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
3199 void i915_gem_context_fini(struct drm_device
*dev
);
3200 void i915_gem_context_reset(struct drm_device
*dev
);
3201 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
3202 int i915_gem_context_enable(struct drm_i915_gem_request
*req
);
3203 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
3204 int i915_switch_context(struct drm_i915_gem_request
*req
);
3205 struct intel_context
*
3206 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
);
3207 void i915_gem_context_free(struct kref
*ctx_ref
);
3208 struct drm_i915_gem_object
*
3209 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
3210 static inline void i915_gem_context_reference(struct intel_context
*ctx
)
3212 kref_get(&ctx
->ref
);
3215 static inline void i915_gem_context_unreference(struct intel_context
*ctx
)
3217 kref_put(&ctx
->ref
, i915_gem_context_free
);
3220 static inline bool i915_gem_context_is_default(const struct intel_context
*c
)
3222 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
3225 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
3226 struct drm_file
*file
);
3227 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
3228 struct drm_file
*file
);
3229 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
3230 struct drm_file
*file_priv
);
3231 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
3232 struct drm_file
*file_priv
);
3234 /* i915_gem_evict.c */
3235 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
3236 struct i915_address_space
*vm
,
3239 unsigned cache_level
,
3240 unsigned long start
,
3243 int __must_check
i915_gem_evict_for_vma(struct i915_vma
*target
);
3244 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
3246 /* belongs in i915_gem_gtt.h */
3247 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
3249 if (INTEL_INFO(dev
)->gen
< 6)
3250 intel_gtt_chipset_flush();
3253 /* i915_gem_stolen.c */
3254 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3255 struct drm_mm_node
*node
, u64 size
,
3256 unsigned alignment
);
3257 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private
*dev_priv
,
3258 struct drm_mm_node
*node
, u64 size
,
3259 unsigned alignment
, u64 start
,
3261 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3262 struct drm_mm_node
*node
);
3263 int i915_gem_init_stolen(struct drm_device
*dev
);
3264 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3265 struct drm_i915_gem_object
*
3266 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
3267 struct drm_i915_gem_object
*
3268 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
3273 /* i915_gem_shrinker.c */
3274 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3275 unsigned long target
,
3277 #define I915_SHRINK_PURGEABLE 0x1
3278 #define I915_SHRINK_UNBOUND 0x2
3279 #define I915_SHRINK_BOUND 0x4
3280 #define I915_SHRINK_ACTIVE 0x8
3281 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3282 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3285 /* i915_gem_tiling.c */
3286 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3288 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3290 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3291 obj
->tiling_mode
!= I915_TILING_NONE
;
3294 /* i915_gem_debug.c */
3296 int i915_verify_lists(struct drm_device
*dev
);
3298 #define i915_verify_lists(dev) 0
3301 /* i915_debugfs.c */
3302 int i915_debugfs_init(struct drm_minor
*minor
);
3303 void i915_debugfs_cleanup(struct drm_minor
*minor
);
3304 #ifdef CONFIG_DEBUG_FS
3305 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3306 void intel_display_crc_init(struct drm_device
*dev
);
3308 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3310 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
3313 /* i915_gpu_error.c */
3315 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3316 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3317 const struct i915_error_state_file_priv
*error
);
3318 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3319 struct drm_i915_private
*i915
,
3320 size_t count
, loff_t pos
);
3321 static inline void i915_error_state_buf_release(
3322 struct drm_i915_error_state_buf
*eb
)
3326 void i915_capture_error_state(struct drm_device
*dev
, bool wedge
,
3327 const char *error_msg
);
3328 void i915_error_state_get(struct drm_device
*dev
,
3329 struct i915_error_state_file_priv
*error_priv
);
3330 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
3331 void i915_destroy_error_state(struct drm_device
*dev
);
3333 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
3334 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3336 /* i915_cmd_parser.c */
3337 int i915_cmd_parser_get_version(void);
3338 int i915_cmd_parser_init_ring(struct intel_engine_cs
*ring
);
3339 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*ring
);
3340 bool i915_needs_cmd_parser(struct intel_engine_cs
*ring
);
3341 int i915_parse_cmds(struct intel_engine_cs
*ring
,
3342 struct drm_i915_gem_object
*batch_obj
,
3343 struct drm_i915_gem_object
*shadow_batch_obj
,
3344 u32 batch_start_offset
,
3348 /* i915_suspend.c */
3349 extern int i915_save_state(struct drm_device
*dev
);
3350 extern int i915_restore_state(struct drm_device
*dev
);
3353 void i915_setup_sysfs(struct drm_device
*dev_priv
);
3354 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
3357 extern int intel_setup_gmbus(struct drm_device
*dev
);
3358 extern void intel_teardown_gmbus(struct drm_device
*dev
);
3359 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3362 extern struct i2c_adapter
*
3363 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3364 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3365 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3366 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3368 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3370 extern void intel_i2c_reset(struct drm_device
*dev
);
3373 int intel_bios_init(struct drm_i915_private
*dev_priv
);
3374 bool intel_bios_is_valid_vbt(const void *buf
, size_t size
);
3376 /* intel_opregion.c */
3378 extern int intel_opregion_setup(struct drm_device
*dev
);
3379 extern void intel_opregion_init(struct drm_device
*dev
);
3380 extern void intel_opregion_fini(struct drm_device
*dev
);
3381 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
3382 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3384 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
3387 static inline int intel_opregion_setup(struct drm_device
*dev
) { return 0; }
3388 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
3389 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
3390 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
3392 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3397 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
3405 extern void intel_register_dsm_handler(void);
3406 extern void intel_unregister_dsm_handler(void);
3408 static inline void intel_register_dsm_handler(void) { return; }
3409 static inline void intel_unregister_dsm_handler(void) { return; }
3410 #endif /* CONFIG_ACPI */
3413 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3414 extern void intel_modeset_init(struct drm_device
*dev
);
3415 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3416 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3417 extern void intel_connector_unregister(struct intel_connector
*);
3418 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
3419 extern void intel_display_resume(struct drm_device
*dev
);
3420 extern void i915_redisable_vga(struct drm_device
*dev
);
3421 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
3422 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
3423 extern void intel_init_pch_refclk(struct drm_device
*dev
);
3424 extern void intel_set_rps(struct drm_device
*dev
, u8 val
);
3425 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3427 extern void intel_detect_pch(struct drm_device
*dev
);
3428 extern int intel_enable_rc6(const struct drm_device
*dev
);
3430 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
3431 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3432 struct drm_file
*file
);
3433 int i915_get_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
3434 struct drm_file
*file
);
3437 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
3438 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3439 struct intel_overlay_error_state
*error
);
3441 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
3442 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3443 struct drm_device
*dev
,
3444 struct intel_display_error_state
*error
);
3446 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3447 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3449 /* intel_sideband.c */
3450 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3451 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3452 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3453 u32
vlv_gpio_nc_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3454 void vlv_gpio_nc_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3455 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3456 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3457 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3458 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3459 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3460 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3461 u32
vlv_gps_core_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3462 void vlv_gps_core_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3463 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3464 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3465 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3466 enum intel_sbi_destination destination
);
3467 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3468 enum intel_sbi_destination destination
);
3469 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3470 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3472 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3473 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3475 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3476 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3478 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3479 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3480 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3481 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3483 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3484 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3485 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3486 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3488 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3489 * will be implemented using 2 32-bit writes in an arbitrary order with
3490 * an arbitrary delay between them. This can cause the hardware to
3491 * act upon the intermediate value, possibly leading to corruption and
3492 * machine death. You have been warned.
3494 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3495 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3497 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3498 u32 upper, lower, old_upper, loop = 0; \
3499 upper = I915_READ(upper_reg); \
3501 old_upper = upper; \
3502 lower = I915_READ(lower_reg); \
3503 upper = I915_READ(upper_reg); \
3504 } while (upper != old_upper && loop++ < 2); \
3505 (u64)upper << 32 | lower; })
3507 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3508 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3510 #define __raw_read(x, s) \
3511 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3514 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3517 #define __raw_write(x, s) \
3518 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3519 i915_reg_t reg, uint##x##_t val) \
3521 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3536 /* These are untraced mmio-accessors that are only valid to be used inside
3537 * criticial sections inside IRQ handlers where forcewake is explicitly
3539 * Think twice, and think again, before using these.
3540 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3541 * intel_uncore_forcewake_irqunlock().
3543 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3544 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3545 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3547 /* "Broadcast RGB" property */
3548 #define INTEL_BROADCAST_RGB_AUTO 0
3549 #define INTEL_BROADCAST_RGB_FULL 1
3550 #define INTEL_BROADCAST_RGB_LIMITED 2
3552 static inline i915_reg_t
i915_vgacntrl_reg(struct drm_device
*dev
)
3554 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
3555 return VLV_VGACNTRL
;
3556 else if (INTEL_INFO(dev
)->gen
>= 5)
3557 return CPU_VGACNTRL
;
3562 static inline void __user
*to_user_ptr(u64 address
)
3564 return (void __user
*)(uintptr_t)address
;
3567 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3569 unsigned long j
= msecs_to_jiffies(m
);
3571 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3574 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
3576 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
3579 static inline unsigned long
3580 timespec_to_jiffies_timeout(const struct timespec
*value
)
3582 unsigned long j
= timespec_to_jiffies(value
);
3584 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3588 * If you need to wait X milliseconds between events A and B, but event B
3589 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3590 * when event A happened, then just before event B you call this function and
3591 * pass the timestamp as the first argument, and X as the second argument.
3594 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3596 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3599 * Don't re-read the value of "jiffies" every time since it may change
3600 * behind our back and break the math.
3602 tmp_jiffies
= jiffies
;
3603 target_jiffies
= timestamp_jiffies
+
3604 msecs_to_jiffies_timeout(to_wait_ms
);
3606 if (time_after(target_jiffies
, tmp_jiffies
)) {
3607 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3608 while (remaining_jiffies
)
3610 schedule_timeout_uninterruptible(remaining_jiffies
);
3614 static inline void i915_trace_irq_get(struct intel_engine_cs
*ring
,
3615 struct drm_i915_gem_request
*req
)
3617 if (ring
->trace_irq_req
== NULL
&& ring
->irq_get(ring
))
3618 i915_gem_request_assign(&ring
->trace_irq_req
, req
);