1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/shmem_fs.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
50 #include <drm/drm_auth.h>
52 #include "i915_params.h"
55 #include "intel_bios.h"
56 #include "intel_dpll_mgr.h"
57 #include "intel_guc.h"
58 #include "intel_lrc.h"
59 #include "intel_ringbuffer.h"
62 #include "i915_gem_gtt.h"
63 #include "i915_gem_render_state.h"
65 #include "intel_gvt.h"
67 /* General customization:
70 #define DRIVER_NAME "i915"
71 #define DRIVER_DESC "Intel Graphics"
72 #define DRIVER_DATE "20160711"
75 /* Many gcc seem to no see through this and fall over :( */
77 #define WARN_ON(x) ({ \
78 bool __i915_warn_cond = (x); \
79 if (__builtin_constant_p(__i915_warn_cond)) \
80 BUILD_BUG_ON(__i915_warn_cond); \
81 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
83 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
87 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
89 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
90 (long) (x), __func__);
92 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
93 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
94 * which may not necessarily be a user visible problem. This will either
95 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
96 * enable distros and users to tailor their preferred amount of i915 abrt
99 #define I915_STATE_WARN(condition, format...) ({ \
100 int __ret_warn_on = !!(condition); \
101 if (unlikely(__ret_warn_on)) \
102 if (!WARN(i915.verbose_state_checks, format)) \
104 unlikely(__ret_warn_on); \
107 #define I915_STATE_WARN_ON(x) \
108 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
110 bool __i915_inject_load_failure(const char *func
, int line
);
111 #define i915_inject_load_failure() \
112 __i915_inject_load_failure(__func__, __LINE__)
114 static inline const char *yesno(bool v
)
116 return v
? "yes" : "no";
119 static inline const char *onoff(bool v
)
121 return v
? "on" : "off";
130 I915_MAX_PIPES
= _PIPE_EDP
132 #define pipe_name(p) ((p) + 'A')
144 static inline const char *transcoder_name(enum transcoder transcoder
)
146 switch (transcoder
) {
155 case TRANSCODER_DSI_A
:
157 case TRANSCODER_DSI_C
:
164 static inline bool transcoder_is_dsi(enum transcoder transcoder
)
166 return transcoder
== TRANSCODER_DSI_A
|| transcoder
== TRANSCODER_DSI_C
;
170 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
171 * number of planes per CRTC. Not all platforms really have this many planes,
172 * which means some arrays of size I915_MAX_PLANES may have unused entries
173 * between the topmost sprite plane and the cursor plane.
182 #define plane_name(p) ((p) + 'A')
184 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
194 #define port_name(p) ((p) + 'A')
196 #define I915_NUM_PHYS_VLV 2
208 enum intel_display_power_domain
{
212 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
213 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
214 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
215 POWER_DOMAIN_TRANSCODER_A
,
216 POWER_DOMAIN_TRANSCODER_B
,
217 POWER_DOMAIN_TRANSCODER_C
,
218 POWER_DOMAIN_TRANSCODER_EDP
,
219 POWER_DOMAIN_TRANSCODER_DSI_A
,
220 POWER_DOMAIN_TRANSCODER_DSI_C
,
221 POWER_DOMAIN_PORT_DDI_A_LANES
,
222 POWER_DOMAIN_PORT_DDI_B_LANES
,
223 POWER_DOMAIN_PORT_DDI_C_LANES
,
224 POWER_DOMAIN_PORT_DDI_D_LANES
,
225 POWER_DOMAIN_PORT_DDI_E_LANES
,
226 POWER_DOMAIN_PORT_DSI
,
227 POWER_DOMAIN_PORT_CRT
,
228 POWER_DOMAIN_PORT_OTHER
,
237 POWER_DOMAIN_MODESET
,
243 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
244 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
245 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
246 #define POWER_DOMAIN_TRANSCODER(tran) \
247 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
248 (tran) + POWER_DOMAIN_TRANSCODER_A)
252 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
264 #define for_each_hpd_pin(__pin) \
265 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
267 struct i915_hotplug
{
268 struct work_struct hotplug_work
;
271 unsigned long last_jiffies
;
276 HPD_MARK_DISABLED
= 2
278 } stats
[HPD_NUM_PINS
];
280 struct delayed_work reenable_work
;
282 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
285 struct work_struct dig_port_work
;
288 * if we get a HPD irq from DP and a HPD irq from non-DP
289 * the non-DP HPD could block the workqueue on a mode config
290 * mutex getting, that userspace may have taken. However
291 * userspace is waiting on the DP workqueue to run which is
292 * blocked behind the non-DP one.
294 struct workqueue_struct
*dp_wq
;
297 #define I915_GEM_GPU_DOMAINS \
298 (I915_GEM_DOMAIN_RENDER | \
299 I915_GEM_DOMAIN_SAMPLER | \
300 I915_GEM_DOMAIN_COMMAND | \
301 I915_GEM_DOMAIN_INSTRUCTION | \
302 I915_GEM_DOMAIN_VERTEX)
304 #define for_each_pipe(__dev_priv, __p) \
305 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
306 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
307 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
308 for_each_if ((__mask) & (1 << (__p)))
309 #define for_each_plane(__dev_priv, __pipe, __p) \
311 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
313 #define for_each_sprite(__dev_priv, __p, __s) \
315 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
318 #define for_each_port_masked(__port, __ports_mask) \
319 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
320 for_each_if ((__ports_mask) & (1 << (__port)))
322 #define for_each_crtc(dev, crtc) \
323 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
325 #define for_each_intel_plane(dev, intel_plane) \
326 list_for_each_entry(intel_plane, \
327 &(dev)->mode_config.plane_list, \
330 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
331 list_for_each_entry(intel_plane, \
332 &(dev)->mode_config.plane_list, \
334 for_each_if ((plane_mask) & \
335 (1 << drm_plane_index(&intel_plane->base)))
337 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
338 list_for_each_entry(intel_plane, \
339 &(dev)->mode_config.plane_list, \
341 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
343 #define for_each_intel_crtc(dev, intel_crtc) \
344 list_for_each_entry(intel_crtc, \
345 &(dev)->mode_config.crtc_list, \
348 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
349 list_for_each_entry(intel_crtc, \
350 &(dev)->mode_config.crtc_list, \
352 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
354 #define for_each_intel_encoder(dev, intel_encoder) \
355 list_for_each_entry(intel_encoder, \
356 &(dev)->mode_config.encoder_list, \
359 #define for_each_intel_connector(dev, intel_connector) \
360 list_for_each_entry(intel_connector, \
361 &(dev)->mode_config.connector_list, \
364 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
365 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
366 for_each_if ((intel_encoder)->base.crtc == (__crtc))
368 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
369 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
370 for_each_if ((intel_connector)->base.encoder == (__encoder))
372 #define for_each_power_domain(domain, mask) \
373 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
374 for_each_if ((1 << (domain)) & (mask))
376 struct drm_i915_private
;
377 struct i915_mm_struct
;
378 struct i915_mmu_object
;
380 struct drm_i915_file_private
{
381 struct drm_i915_private
*dev_priv
;
382 struct drm_file
*file
;
386 struct list_head request_list
;
387 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
388 * chosen to prevent the CPU getting more than a frame ahead of the GPU
389 * (when using lax throttling for the frontbuffer). We also use it to
390 * offer free GPU waitboosts for severely congested workloads.
392 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
394 struct idr context_idr
;
396 struct intel_rps_client
{
397 struct list_head link
;
401 unsigned int bsd_ring
;
404 /* Used by dp and fdi links */
405 struct intel_link_m_n
{
413 void intel_link_compute_m_n(int bpp
, int nlanes
,
414 int pixel_clock
, int link_clock
,
415 struct intel_link_m_n
*m_n
);
417 /* Interface history:
420 * 1.2: Add Power Management
421 * 1.3: Add vblank support
422 * 1.4: Fix cmdbuffer path, add heap destroy
423 * 1.5: Add vblank pipe configuration
424 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
425 * - Support vertical blank on secondary display pipe
427 #define DRIVER_MAJOR 1
428 #define DRIVER_MINOR 6
429 #define DRIVER_PATCHLEVEL 0
431 #define WATCH_LISTS 0
433 struct opregion_header
;
434 struct opregion_acpi
;
435 struct opregion_swsci
;
436 struct opregion_asle
;
438 struct intel_opregion
{
439 struct opregion_header
*header
;
440 struct opregion_acpi
*acpi
;
441 struct opregion_swsci
*swsci
;
442 u32 swsci_gbda_sub_functions
;
443 u32 swsci_sbcb_sub_functions
;
444 struct opregion_asle
*asle
;
449 struct work_struct asle_work
;
451 #define OPREGION_SIZE (8*1024)
453 struct intel_overlay
;
454 struct intel_overlay_error_state
;
456 #define I915_FENCE_REG_NONE -1
457 #define I915_MAX_NUM_FENCES 32
458 /* 32 fences + sign bit for FENCE_REG_NONE */
459 #define I915_MAX_NUM_FENCE_BITS 6
461 struct drm_i915_fence_reg
{
462 struct list_head lru_list
;
463 struct drm_i915_gem_object
*obj
;
467 struct sdvo_device_mapping
{
476 struct intel_display_error_state
;
478 struct drm_i915_error_state
{
488 /* Generic register state */
496 u32 error
; /* gen6+ */
497 u32 err_int
; /* gen7 */
498 u32 fault_data0
; /* gen8, gen9 */
499 u32 fault_data1
; /* gen8, gen9 */
505 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
506 u64 fence
[I915_MAX_NUM_FENCES
];
507 struct intel_overlay_error_state
*overlay
;
508 struct intel_display_error_state
*display
;
509 struct drm_i915_error_object
*semaphore_obj
;
511 struct drm_i915_error_ring
{
513 /* Software tracked state */
517 enum intel_ring_hangcheck_action hangcheck_action
;
520 /* our own tracking of ring head and tail */
525 u32 semaphore_seqno
[I915_NUM_ENGINES
- 1];
544 u32 rc_psmi
; /* sleep state */
545 u32 semaphore_mboxes
[I915_NUM_ENGINES
- 1];
547 struct drm_i915_error_object
{
551 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
553 struct drm_i915_error_object
*wa_ctx
;
555 struct drm_i915_error_request
{
561 struct drm_i915_error_waiter
{
562 char comm
[TASK_COMM_LEN
];
576 char comm
[TASK_COMM_LEN
];
577 } ring
[I915_NUM_ENGINES
];
579 struct drm_i915_error_buffer
{
582 u32 rseqno
[I915_NUM_ENGINES
], wseqno
;
586 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
594 } **active_bo
, **pinned_bo
;
596 u32
*active_bo_count
, *pinned_bo_count
;
600 struct intel_connector
;
601 struct intel_encoder
;
602 struct intel_crtc_state
;
603 struct intel_initial_plane_config
;
608 struct drm_i915_display_funcs
{
609 int (*get_display_clock_speed
)(struct drm_device
*dev
);
610 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
611 int (*compute_pipe_wm
)(struct intel_crtc_state
*cstate
);
612 int (*compute_intermediate_wm
)(struct drm_device
*dev
,
613 struct intel_crtc
*intel_crtc
,
614 struct intel_crtc_state
*newstate
);
615 void (*initial_watermarks
)(struct intel_crtc_state
*cstate
);
616 void (*optimize_watermarks
)(struct intel_crtc_state
*cstate
);
617 int (*compute_global_watermarks
)(struct drm_atomic_state
*state
);
618 void (*update_wm
)(struct drm_crtc
*crtc
);
619 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
620 void (*modeset_commit_cdclk
)(struct drm_atomic_state
*state
);
621 /* Returns the active state of the crtc, and if the crtc is active,
622 * fills out the pipe-config with the hw state. */
623 bool (*get_pipe_config
)(struct intel_crtc
*,
624 struct intel_crtc_state
*);
625 void (*get_initial_plane_config
)(struct intel_crtc
*,
626 struct intel_initial_plane_config
*);
627 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
628 struct intel_crtc_state
*crtc_state
);
629 void (*crtc_enable
)(struct drm_crtc
*crtc
);
630 void (*crtc_disable
)(struct drm_crtc
*crtc
);
631 void (*audio_codec_enable
)(struct drm_connector
*connector
,
632 struct intel_encoder
*encoder
,
633 const struct drm_display_mode
*adjusted_mode
);
634 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
635 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
636 void (*init_clock_gating
)(struct drm_device
*dev
);
637 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
638 struct drm_framebuffer
*fb
,
639 struct drm_i915_gem_object
*obj
,
640 struct drm_i915_gem_request
*req
,
642 void (*hpd_irq_setup
)(struct drm_i915_private
*dev_priv
);
643 /* clock updates for mode set */
645 /* render clock increase/decrease */
646 /* display clock increase/decrease */
647 /* pll clock increase/decrease */
649 void (*load_csc_matrix
)(struct drm_crtc_state
*crtc_state
);
650 void (*load_luts
)(struct drm_crtc_state
*crtc_state
);
653 enum forcewake_domain_id
{
654 FW_DOMAIN_ID_RENDER
= 0,
655 FW_DOMAIN_ID_BLITTER
,
661 enum forcewake_domains
{
662 FORCEWAKE_RENDER
= (1 << FW_DOMAIN_ID_RENDER
),
663 FORCEWAKE_BLITTER
= (1 << FW_DOMAIN_ID_BLITTER
),
664 FORCEWAKE_MEDIA
= (1 << FW_DOMAIN_ID_MEDIA
),
665 FORCEWAKE_ALL
= (FORCEWAKE_RENDER
|
670 #define FW_REG_READ (1)
671 #define FW_REG_WRITE (2)
673 enum forcewake_domains
674 intel_uncore_forcewake_for_reg(struct drm_i915_private
*dev_priv
,
675 i915_reg_t reg
, unsigned int op
);
677 struct intel_uncore_funcs
{
678 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
679 enum forcewake_domains domains
);
680 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
681 enum forcewake_domains domains
);
683 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
684 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
685 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
686 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
688 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
689 uint8_t val
, bool trace
);
690 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
691 uint16_t val
, bool trace
);
692 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
693 uint32_t val
, bool trace
);
694 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
695 uint64_t val
, bool trace
);
698 struct intel_uncore
{
699 spinlock_t lock
; /** lock is also taken in irq contexts. */
701 struct intel_uncore_funcs funcs
;
704 enum forcewake_domains fw_domains
;
706 struct intel_uncore_forcewake_domain
{
707 struct drm_i915_private
*i915
;
708 enum forcewake_domain_id id
;
709 enum forcewake_domains mask
;
711 struct hrtimer timer
;
718 } fw_domain
[FW_DOMAIN_ID_COUNT
];
720 int unclaimed_mmio_check
;
723 /* Iterate over initialised fw domains */
724 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
725 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
726 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
728 for_each_if ((mask__) & (domain__)->mask)
730 #define for_each_fw_domain(domain__, dev_priv__) \
731 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
733 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
734 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
735 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
738 struct work_struct work
;
740 uint32_t *dmc_payload
;
741 uint32_t dmc_fw_size
;
744 i915_reg_t mmioaddr
[8];
745 uint32_t mmiodata
[8];
747 uint32_t allowed_dc_mask
;
750 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
751 func(is_mobile) sep \
754 func(is_i945gm) sep \
756 func(need_gfx_hws) sep \
758 func(is_pineview) sep \
759 func(is_broadwater) sep \
760 func(is_crestline) sep \
761 func(is_ivybridge) sep \
762 func(is_valleyview) sep \
763 func(is_cherryview) sep \
764 func(is_haswell) sep \
765 func(is_broadwell) sep \
766 func(is_skylake) sep \
767 func(is_broxton) sep \
768 func(is_kabylake) sep \
769 func(is_preliminary) sep \
771 func(has_pipe_cxsr) sep \
772 func(has_hotplug) sep \
773 func(cursor_needs_physical) sep \
774 func(has_overlay) sep \
775 func(overlay_needs_physical) sep \
776 func(supports_tv) sep \
778 func(has_snoop) sep \
780 func(has_fpga_dbg) sep \
783 #define DEFINE_FLAG(name) u8 name:1
784 #define SEP_SEMICOLON ;
786 struct intel_device_info
{
787 u32 display_mmio_offset
;
790 u8 num_sprites
[I915_MAX_PIPES
];
793 u8 ring_mask
; /* Rings supported by the HW */
794 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
795 /* Register offsets for the various display pipes and transcoders */
796 int pipe_offsets
[I915_MAX_TRANSCODERS
];
797 int trans_offsets
[I915_MAX_TRANSCODERS
];
798 int palette_offsets
[I915_MAX_PIPES
];
799 int cursor_offsets
[I915_MAX_PIPES
];
801 /* Slice/subslice/EU info */
804 u8 subslice_per_slice
;
808 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
811 u8 has_subslice_pg
:1;
815 u16 degamma_lut_size
;
823 enum i915_cache_level
{
825 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
826 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
827 caches, eg sampler/render caches, and the
828 large Last-Level-Cache. LLC is coherent with
829 the CPU, but L3 is only visible to the GPU. */
830 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
833 struct i915_ctx_hang_stats
{
834 /* This context had batch pending when hang was declared */
835 unsigned batch_pending
;
837 /* This context had batch active when hang was declared */
838 unsigned batch_active
;
840 /* Time when this context was last blamed for a GPU reset */
841 unsigned long guilty_ts
;
843 /* If the contexts causes a second GPU hang within this time,
844 * it is permanently banned from submitting any more work.
846 unsigned long ban_period_seconds
;
848 /* This context is banned to submit more work */
852 /* This must match up with the value previously used for execbuf2.rsvd1. */
853 #define DEFAULT_CONTEXT_HANDLE 0
856 * struct i915_gem_context - as the name implies, represents a context.
857 * @ref: reference count.
858 * @user_handle: userspace tracking identity for this context.
859 * @remap_slice: l3 row remapping information.
860 * @flags: context specific flags:
861 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
862 * @file_priv: filp associated with this context (NULL for global default
864 * @hang_stats: information about the role of this context in possible GPU
866 * @ppgtt: virtual memory space used by this context.
867 * @legacy_hw_ctx: render context backing object and whether it is correctly
868 * initialized (legacy ring submission mechanism only).
869 * @link: link in the global list of contexts.
871 * Contexts are memory images used by the hardware to store copies of their
874 struct i915_gem_context
{
876 struct drm_i915_private
*i915
;
877 struct drm_i915_file_private
*file_priv
;
878 struct i915_hw_ppgtt
*ppgtt
;
880 struct i915_ctx_hang_stats hang_stats
;
882 /* Unique identifier for this context, used by the hw for tracking */
884 #define CONTEXT_NO_ZEROMAP BIT(0)
885 #define CONTEXT_NO_ERROR_CAPTURE BIT(1)
891 struct intel_context
{
892 struct drm_i915_gem_object
*state
;
893 struct intel_ringbuffer
*ringbuf
;
894 struct i915_vma
*lrc_vma
;
895 uint32_t *lrc_reg_state
;
899 } engine
[I915_NUM_ENGINES
];
902 struct atomic_notifier_head status_notifier
;
903 bool execlists_force_single_submission
;
905 struct list_head link
;
919 /* This is always the inner lock when overlapping with struct_mutex and
920 * it's the outer lock when overlapping with stolen_lock. */
923 unsigned int possible_framebuffer_bits
;
924 unsigned int busy_bits
;
925 unsigned int visible_pipes_mask
;
926 struct intel_crtc
*crtc
;
928 struct drm_mm_node compressed_fb
;
929 struct drm_mm_node
*compressed_llb
;
936 struct intel_fbc_state_cache
{
938 unsigned int mode_flags
;
939 uint32_t hsw_bdw_pixel_rate
;
943 unsigned int rotation
;
951 uint32_t pixel_format
;
954 unsigned int tiling_mode
;
958 struct intel_fbc_reg_params
{
962 unsigned int fence_y_offset
;
967 uint32_t pixel_format
;
975 struct intel_fbc_work
{
977 u32 scheduled_vblank
;
978 struct work_struct work
;
981 const char *no_fbc_reason
;
985 * HIGH_RR is the highest eDP panel refresh rate read from EDID
986 * LOW_RR is the lowest eDP panel refresh rate found from EDID
987 * parsing for same resolution.
989 enum drrs_refresh_rate_type
{
992 DRRS_MAX_RR
, /* RR count */
995 enum drrs_support_type
{
996 DRRS_NOT_SUPPORTED
= 0,
997 STATIC_DRRS_SUPPORT
= 1,
998 SEAMLESS_DRRS_SUPPORT
= 2
1004 struct delayed_work work
;
1005 struct intel_dp
*dp
;
1006 unsigned busy_frontbuffer_bits
;
1007 enum drrs_refresh_rate_type refresh_rate_type
;
1008 enum drrs_support_type type
;
1015 struct intel_dp
*enabled
;
1017 struct delayed_work work
;
1018 unsigned busy_frontbuffer_bits
;
1020 bool aux_frame_sync
;
1025 PCH_NONE
= 0, /* No PCH present */
1026 PCH_IBX
, /* Ibexpeak PCH */
1027 PCH_CPT
, /* Cougarpoint PCH */
1028 PCH_LPT
, /* Lynxpoint PCH */
1029 PCH_SPT
, /* Sunrisepoint PCH */
1030 PCH_KBP
, /* Kabypoint PCH */
1034 enum intel_sbi_destination
{
1039 #define QUIRK_PIPEA_FORCE (1<<0)
1040 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1041 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1042 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1043 #define QUIRK_PIPEB_FORCE (1<<4)
1044 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1047 struct intel_fbc_work
;
1049 struct intel_gmbus
{
1050 struct i2c_adapter adapter
;
1051 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1054 i915_reg_t gpio_reg
;
1055 struct i2c_algo_bit_data bit_algo
;
1056 struct drm_i915_private
*dev_priv
;
1059 struct i915_suspend_saved_registers
{
1062 u32 savePP_ON_DELAYS
;
1063 u32 savePP_OFF_DELAYS
;
1068 u32 saveFBC_CONTROL
;
1069 u32 saveCACHE_MODE_0
;
1070 u32 saveMI_ARB_STATE
;
1074 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1075 u32 savePCH_PORT_HOTPLUG
;
1079 struct vlv_s0ix_state
{
1086 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1087 u32 media_max_req_count
;
1088 u32 gfx_max_req_count
;
1114 u32 rp_down_timeout
;
1120 /* Display 1 CZ domain */
1125 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1127 /* GT SA CZ domain */
1134 /* Display 2 CZ domain */
1138 u32 clock_gate_dis2
;
1141 struct intel_rps_ei
{
1147 struct intel_gen6_power_mgmt
{
1149 * work, interrupts_enabled and pm_iir are protected by
1150 * dev_priv->irq_lock
1152 struct work_struct work
;
1153 bool interrupts_enabled
;
1158 /* Frequencies are stored in potentially platform dependent multiples.
1159 * In other words, *_freq needs to be multiplied by X to be interesting.
1160 * Soft limits are those which are used for the dynamic reclocking done
1161 * by the driver (raise frequencies under heavy loads, and lower for
1162 * lighter loads). Hard limits are those imposed by the hardware.
1164 * A distinction is made for overclocking, which is never enabled by
1165 * default, and is considered to be above the hard limit if it's
1168 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1169 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1170 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1171 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1172 u8 min_freq
; /* AKA RPn. Minimum frequency */
1173 u8 idle_freq
; /* Frequency to request when we are idle */
1174 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1175 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1176 u8 rp0_freq
; /* Non-overclocked max frequency. */
1177 u16 gpll_ref_freq
; /* vlv/chv GPLL reference frequency */
1179 u8 up_threshold
; /* Current %busy required to uplock */
1180 u8 down_threshold
; /* Current %busy required to downclock */
1183 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1185 spinlock_t client_lock
;
1186 struct list_head clients
;
1190 struct delayed_work delayed_resume_work
;
1193 struct intel_rps_client semaphores
, mmioflips
;
1195 /* manual wa residency calculations */
1196 struct intel_rps_ei up_ei
, down_ei
;
1199 * Protects RPS/RC6 register access and PCU communication.
1200 * Must be taken after struct_mutex if nested. Note that
1201 * this lock may be held for long periods of time when
1202 * talking to hw - so only take it when talking to hw!
1204 struct mutex hw_lock
;
1207 /* defined intel_pm.c */
1208 extern spinlock_t mchdev_lock
;
1210 struct intel_ilk_power_mgmt
{
1218 unsigned long last_time1
;
1219 unsigned long chipset_power
;
1222 unsigned long gfx_power
;
1229 struct drm_i915_private
;
1230 struct i915_power_well
;
1232 struct i915_power_well_ops
{
1234 * Synchronize the well's hw state to match the current sw state, for
1235 * example enable/disable it based on the current refcount. Called
1236 * during driver init and resume time, possibly after first calling
1237 * the enable/disable handlers.
1239 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1240 struct i915_power_well
*power_well
);
1242 * Enable the well and resources that depend on it (for example
1243 * interrupts located on the well). Called after the 0->1 refcount
1246 void (*enable
)(struct drm_i915_private
*dev_priv
,
1247 struct i915_power_well
*power_well
);
1249 * Disable the well and resources that depend on it. Called after
1250 * the 1->0 refcount transition.
1252 void (*disable
)(struct drm_i915_private
*dev_priv
,
1253 struct i915_power_well
*power_well
);
1254 /* Returns the hw enabled state. */
1255 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1256 struct i915_power_well
*power_well
);
1259 /* Power well structure for haswell */
1260 struct i915_power_well
{
1263 /* power well enable/disable usage count */
1265 /* cached hw enabled state */
1267 unsigned long domains
;
1269 const struct i915_power_well_ops
*ops
;
1272 struct i915_power_domains
{
1274 * Power wells needed for initialization at driver init and suspend
1275 * time are on. They are kept on until after the first modeset.
1279 int power_well_count
;
1282 int domain_use_count
[POWER_DOMAIN_NUM
];
1283 struct i915_power_well
*power_wells
;
1286 #define MAX_L3_SLICES 2
1287 struct intel_l3_parity
{
1288 u32
*remap_info
[MAX_L3_SLICES
];
1289 struct work_struct error_work
;
1293 struct i915_gem_mm
{
1294 /** Memory allocator for GTT stolen memory */
1295 struct drm_mm stolen
;
1296 /** Protects the usage of the GTT stolen memory allocator. This is
1297 * always the inner lock when overlapping with struct_mutex. */
1298 struct mutex stolen_lock
;
1300 /** List of all objects in gtt_space. Used to restore gtt
1301 * mappings on resume */
1302 struct list_head bound_list
;
1304 * List of objects which are not bound to the GTT (thus
1305 * are idle and not used by the GPU) but still have
1306 * (presumably uncached) pages still attached.
1308 struct list_head unbound_list
;
1310 /** Usable portion of the GTT for GEM */
1311 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1313 /** PPGTT used for aliasing the PPGTT with the GTT */
1314 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1316 struct notifier_block oom_notifier
;
1317 struct notifier_block vmap_notifier
;
1318 struct shrinker shrinker
;
1319 bool shrinker_no_lock_stealing
;
1321 /** LRU list of objects with fence regs on them. */
1322 struct list_head fence_list
;
1325 * Are we in a non-interruptible section of code like
1330 /* the indicator for dispatch video commands on two BSD rings */
1331 unsigned int bsd_ring_dispatch_index
;
1333 /** Bit 6 swizzling required for X tiling */
1334 uint32_t bit_6_swizzle_x
;
1335 /** Bit 6 swizzling required for Y tiling */
1336 uint32_t bit_6_swizzle_y
;
1338 /* accounting, useful for userland debugging */
1339 spinlock_t object_stat_lock
;
1340 size_t object_memory
;
1344 struct drm_i915_error_state_buf
{
1345 struct drm_i915_private
*i915
;
1354 struct i915_error_state_file_priv
{
1355 struct drm_device
*dev
;
1356 struct drm_i915_error_state
*error
;
1359 struct i915_gpu_error
{
1360 /* For hangcheck timer */
1361 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1362 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1363 /* Hang gpu twice in this window and your context gets banned */
1364 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1366 struct delayed_work hangcheck_work
;
1368 /* For reset and error_state handling. */
1370 /* Protected by the above dev->gpu_error.lock. */
1371 struct drm_i915_error_state
*first_error
;
1373 unsigned long missed_irq_rings
;
1376 * State variable controlling the reset flow and count
1378 * This is a counter which gets incremented when reset is triggered,
1379 * and again when reset has been handled. So odd values (lowest bit set)
1380 * means that reset is in progress and even values that
1381 * (reset_counter >> 1):th reset was successfully completed.
1383 * If reset is not completed succesfully, the I915_WEDGE bit is
1384 * set meaning that hardware is terminally sour and there is no
1385 * recovery. All waiters on the reset_queue will be woken when
1388 * This counter is used by the wait_seqno code to notice that reset
1389 * event happened and it needs to restart the entire ioctl (since most
1390 * likely the seqno it waited for won't ever signal anytime soon).
1392 * This is important for lock-free wait paths, where no contended lock
1393 * naturally enforces the correct ordering between the bail-out of the
1394 * waiter and the gpu reset work code.
1396 atomic_t reset_counter
;
1398 #define I915_RESET_IN_PROGRESS_FLAG 1
1399 #define I915_WEDGED (1 << 31)
1402 * Waitqueue to signal when a hang is detected. Used to for waiters
1403 * to release the struct_mutex for the reset to procede.
1405 wait_queue_head_t wait_queue
;
1408 * Waitqueue to signal when the reset has completed. Used by clients
1409 * that wait for dev_priv->mm.wedged to settle.
1411 wait_queue_head_t reset_queue
;
1413 /* For missed irq/seqno simulation. */
1414 unsigned long test_irq_rings
;
1417 enum modeset_restore
{
1418 MODESET_ON_LID_OPEN
,
1423 #define DP_AUX_A 0x40
1424 #define DP_AUX_B 0x10
1425 #define DP_AUX_C 0x20
1426 #define DP_AUX_D 0x30
1428 #define DDC_PIN_B 0x05
1429 #define DDC_PIN_C 0x04
1430 #define DDC_PIN_D 0x06
1432 struct ddi_vbt_port_info
{
1434 * This is an index in the HDMI/DVI DDI buffer translation table.
1435 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1436 * populate this field.
1438 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1439 uint8_t hdmi_level_shift
;
1441 uint8_t supports_dvi
:1;
1442 uint8_t supports_hdmi
:1;
1443 uint8_t supports_dp
:1;
1445 uint8_t alternate_aux_channel
;
1446 uint8_t alternate_ddc_pin
;
1448 uint8_t dp_boost_level
;
1449 uint8_t hdmi_boost_level
;
1452 enum psr_lines_to_wait
{
1453 PSR_0_LINES_TO_WAIT
= 0,
1455 PSR_4_LINES_TO_WAIT
,
1459 struct intel_vbt_data
{
1460 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1461 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1464 unsigned int int_tv_support
:1;
1465 unsigned int lvds_dither
:1;
1466 unsigned int lvds_vbt
:1;
1467 unsigned int int_crt_support
:1;
1468 unsigned int lvds_use_ssc
:1;
1469 unsigned int display_clock_mode
:1;
1470 unsigned int fdi_rx_polarity_inverted
:1;
1471 unsigned int panel_type
:4;
1473 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1475 enum drrs_support_type drrs_type
;
1486 struct edp_power_seq pps
;
1491 bool require_aux_wakeup
;
1493 enum psr_lines_to_wait lines_to_wait
;
1494 int tp1_wakeup_time
;
1495 int tp2_tp3_wakeup_time
;
1501 bool active_low_pwm
;
1502 u8 min_brightness
; /* min_brightness/255 of max */
1503 enum intel_backlight_type type
;
1509 struct mipi_config
*config
;
1510 struct mipi_pps_data
*pps
;
1514 const u8
*sequence
[MIPI_SEQ_MAX
];
1520 union child_device_config
*child_dev
;
1522 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1523 struct sdvo_device_mapping sdvo_mappings
[2];
1526 enum intel_ddb_partitioning
{
1528 INTEL_DDB_PART_5_6
, /* IVB+ */
1531 struct intel_wm_level
{
1539 struct ilk_wm_values
{
1540 uint32_t wm_pipe
[3];
1542 uint32_t wm_lp_spr
[3];
1543 uint32_t wm_linetime
[3];
1545 enum intel_ddb_partitioning partitioning
;
1548 struct vlv_pipe_wm
{
1559 struct vlv_wm_values
{
1560 struct vlv_pipe_wm pipe
[3];
1561 struct vlv_sr_wm sr
;
1571 struct skl_ddb_entry
{
1572 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1575 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1577 return entry
->end
- entry
->start
;
1580 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1581 const struct skl_ddb_entry
*e2
)
1583 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1589 struct skl_ddb_allocation
{
1590 struct skl_ddb_entry pipe
[I915_MAX_PIPES
];
1591 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1592 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1595 struct skl_wm_values
{
1596 unsigned dirty_pipes
;
1597 struct skl_ddb_allocation ddb
;
1598 uint32_t wm_linetime
[I915_MAX_PIPES
];
1599 uint32_t plane
[I915_MAX_PIPES
][I915_MAX_PLANES
][8];
1600 uint32_t plane_trans
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1603 struct skl_wm_level
{
1604 bool plane_en
[I915_MAX_PLANES
];
1605 uint16_t plane_res_b
[I915_MAX_PLANES
];
1606 uint8_t plane_res_l
[I915_MAX_PLANES
];
1610 * This struct helps tracking the state needed for runtime PM, which puts the
1611 * device in PCI D3 state. Notice that when this happens, nothing on the
1612 * graphics device works, even register access, so we don't get interrupts nor
1615 * Every piece of our code that needs to actually touch the hardware needs to
1616 * either call intel_runtime_pm_get or call intel_display_power_get with the
1617 * appropriate power domain.
1619 * Our driver uses the autosuspend delay feature, which means we'll only really
1620 * suspend if we stay with zero refcount for a certain amount of time. The
1621 * default value is currently very conservative (see intel_runtime_pm_enable), but
1622 * it can be changed with the standard runtime PM files from sysfs.
1624 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1625 * goes back to false exactly before we reenable the IRQs. We use this variable
1626 * to check if someone is trying to enable/disable IRQs while they're supposed
1627 * to be disabled. This shouldn't happen and we'll print some error messages in
1630 * For more, read the Documentation/power/runtime_pm.txt.
1632 struct i915_runtime_pm
{
1633 atomic_t wakeref_count
;
1634 atomic_t atomic_seq
;
1639 enum intel_pipe_crc_source
{
1640 INTEL_PIPE_CRC_SOURCE_NONE
,
1641 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1642 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1643 INTEL_PIPE_CRC_SOURCE_PF
,
1644 INTEL_PIPE_CRC_SOURCE_PIPE
,
1645 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1646 INTEL_PIPE_CRC_SOURCE_TV
,
1647 INTEL_PIPE_CRC_SOURCE_DP_B
,
1648 INTEL_PIPE_CRC_SOURCE_DP_C
,
1649 INTEL_PIPE_CRC_SOURCE_DP_D
,
1650 INTEL_PIPE_CRC_SOURCE_AUTO
,
1651 INTEL_PIPE_CRC_SOURCE_MAX
,
1654 struct intel_pipe_crc_entry
{
1659 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1660 struct intel_pipe_crc
{
1662 bool opened
; /* exclusive access to the result file */
1663 struct intel_pipe_crc_entry
*entries
;
1664 enum intel_pipe_crc_source source
;
1666 wait_queue_head_t wq
;
1669 struct i915_frontbuffer_tracking
{
1673 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1680 struct i915_wa_reg
{
1683 /* bitmask representing WA bits */
1688 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1689 * allowing it for RCS as we don't foresee any requirement of having
1690 * a whitelist for other engines. When it is really required for
1691 * other engines then the limit need to be increased.
1693 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1695 struct i915_workarounds
{
1696 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1698 u32 hw_whitelist_count
[I915_NUM_ENGINES
];
1701 struct i915_virtual_gpu
{
1705 struct i915_execbuffer_params
{
1706 struct drm_device
*dev
;
1707 struct drm_file
*file
;
1708 uint32_t dispatch_flags
;
1709 uint32_t args_batch_start_offset
;
1710 uint64_t batch_obj_vm_offset
;
1711 struct intel_engine_cs
*engine
;
1712 struct drm_i915_gem_object
*batch_obj
;
1713 struct i915_gem_context
*ctx
;
1714 struct drm_i915_gem_request
*request
;
1717 /* used in computing the new watermarks state */
1718 struct intel_wm_config
{
1719 unsigned int num_pipes_active
;
1720 bool sprites_enabled
;
1721 bool sprites_scaled
;
1724 struct drm_i915_private
{
1725 struct drm_device drm
;
1727 struct kmem_cache
*objects
;
1728 struct kmem_cache
*vmas
;
1729 struct kmem_cache
*requests
;
1731 const struct intel_device_info info
;
1733 int relative_constants_mode
;
1737 struct intel_uncore uncore
;
1739 struct i915_virtual_gpu vgpu
;
1741 struct intel_gvt gvt
;
1743 struct intel_guc guc
;
1745 struct intel_csr csr
;
1747 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
1749 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1750 * controller on different i2c buses. */
1751 struct mutex gmbus_mutex
;
1754 * Base address of the gmbus and gpio block.
1756 uint32_t gpio_mmio_base
;
1758 /* MMIO base address for MIPI regs */
1759 uint32_t mipi_mmio_base
;
1761 uint32_t psr_mmio_base
;
1763 wait_queue_head_t gmbus_wait_queue
;
1765 struct pci_dev
*bridge_dev
;
1766 struct i915_gem_context
*kernel_context
;
1767 struct intel_engine_cs engine
[I915_NUM_ENGINES
];
1768 struct drm_i915_gem_object
*semaphore_obj
;
1769 uint32_t last_seqno
, next_seqno
;
1771 struct drm_dma_handle
*status_page_dmah
;
1772 struct resource mch_res
;
1774 /* protects the irq masks */
1775 spinlock_t irq_lock
;
1777 /* protects the mmio flip data */
1778 spinlock_t mmio_flip_lock
;
1780 bool display_irqs_enabled
;
1782 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1783 struct pm_qos_request pm_qos
;
1785 /* Sideband mailbox protection */
1786 struct mutex sb_lock
;
1788 /** Cached value of IMR to avoid reads in updating the bitfield */
1791 u32 de_irq_mask
[I915_MAX_PIPES
];
1796 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1798 struct i915_hotplug hotplug
;
1799 struct intel_fbc fbc
;
1800 struct i915_drrs drrs
;
1801 struct intel_opregion opregion
;
1802 struct intel_vbt_data vbt
;
1804 bool preserve_bios_swizzle
;
1807 struct intel_overlay
*overlay
;
1809 /* backlight registers and fields in struct intel_panel */
1810 struct mutex backlight_lock
;
1813 bool no_aux_handshake
;
1815 /* protects panel power sequencer state */
1816 struct mutex pps_mutex
;
1818 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1819 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1821 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1822 unsigned int skl_preferred_vco_freq
;
1823 unsigned int cdclk_freq
, max_cdclk_freq
, atomic_cdclk_freq
;
1824 unsigned int max_dotclk_freq
;
1825 unsigned int rawclk_freq
;
1826 unsigned int hpll_freq
;
1827 unsigned int czclk_freq
;
1830 unsigned int vco
, ref
;
1834 * wq - Driver workqueue for GEM.
1836 * NOTE: Work items scheduled here are not allowed to grab any modeset
1837 * locks, for otherwise the flushing done in the pageflip code will
1838 * result in deadlocks.
1840 struct workqueue_struct
*wq
;
1842 /* Display functions */
1843 struct drm_i915_display_funcs display
;
1845 /* PCH chipset type */
1846 enum intel_pch pch_type
;
1847 unsigned short pch_id
;
1849 unsigned long quirks
;
1851 enum modeset_restore modeset_restore
;
1852 struct mutex modeset_restore_lock
;
1853 struct drm_atomic_state
*modeset_restore_state
;
1855 struct list_head vm_list
; /* Global list of all address spaces */
1856 struct i915_ggtt ggtt
; /* VM representing the global address space */
1858 struct i915_gem_mm mm
;
1859 DECLARE_HASHTABLE(mm_structs
, 7);
1860 struct mutex mm_lock
;
1862 /* The hw wants to have a stable context identifier for the lifetime
1863 * of the context (for OA, PASID, faults, etc). This is limited
1864 * in execlists to 21 bits.
1866 struct ida context_hw_ida
;
1867 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1869 /* Kernel Modesetting */
1871 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1872 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1873 wait_queue_head_t pending_flip_queue
;
1875 #ifdef CONFIG_DEBUG_FS
1876 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1879 /* dpll and cdclk state is protected by connection_mutex */
1880 int num_shared_dpll
;
1881 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1882 const struct intel_dpll_mgr
*dpll_mgr
;
1885 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1886 * Must be global rather than per dpll, because on some platforms
1887 * plls share registers.
1889 struct mutex dpll_lock
;
1891 unsigned int active_crtcs
;
1892 unsigned int min_pixclk
[I915_MAX_PIPES
];
1894 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1896 struct i915_workarounds workarounds
;
1898 struct i915_frontbuffer_tracking fb_tracking
;
1902 bool mchbar_need_disable
;
1904 struct intel_l3_parity l3_parity
;
1906 /* Cannot be determined by PCIID. You must always read a register. */
1909 /* gen6+ rps state */
1910 struct intel_gen6_power_mgmt rps
;
1912 /* ilk-only ips/rps state. Everything in here is protected by the global
1913 * mchdev_lock in intel_pm.c */
1914 struct intel_ilk_power_mgmt ips
;
1916 struct i915_power_domains power_domains
;
1918 struct i915_psr psr
;
1920 struct i915_gpu_error gpu_error
;
1922 struct drm_i915_gem_object
*vlv_pctx
;
1924 #ifdef CONFIG_DRM_FBDEV_EMULATION
1925 /* list of fbdev register on this device */
1926 struct intel_fbdev
*fbdev
;
1927 struct work_struct fbdev_suspend_work
;
1930 struct drm_property
*broadcast_rgb_property
;
1931 struct drm_property
*force_audio_property
;
1933 /* hda/i915 audio component */
1934 struct i915_audio_component
*audio_component
;
1935 bool audio_component_registered
;
1937 * av_mutex - mutex for audio/video sync
1940 struct mutex av_mutex
;
1942 uint32_t hw_context_size
;
1943 struct list_head context_list
;
1947 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1948 u32 chv_phy_control
;
1950 * Shadows for CHV DPLL_MD regs to keep the state
1951 * checker somewhat working in the presence hardware
1952 * crappiness (can't read out DPLL_MD for pipes B & C).
1954 u32 chv_dpll_md
[I915_MAX_PIPES
];
1958 bool suspended_to_idle
;
1959 struct i915_suspend_saved_registers regfile
;
1960 struct vlv_s0ix_state vlv_s0ix_state
;
1964 * Raw watermark latency values:
1965 * in 0.1us units for WM0,
1966 * in 0.5us units for WM1+.
1969 uint16_t pri_latency
[5];
1971 uint16_t spr_latency
[5];
1973 uint16_t cur_latency
[5];
1975 * Raw watermark memory latency values
1976 * for SKL for all 8 levels
1979 uint16_t skl_latency
[8];
1982 * The skl_wm_values structure is a bit too big for stack
1983 * allocation, so we keep the staging struct where we store
1984 * intermediate results here instead.
1986 struct skl_wm_values skl_results
;
1988 /* current hardware state */
1990 struct ilk_wm_values hw
;
1991 struct skl_wm_values skl_hw
;
1992 struct vlv_wm_values vlv
;
1998 * Should be held around atomic WM register writing; also
1999 * protects * intel_crtc->wm.active and
2000 * cstate->wm.need_postvbl_update.
2002 struct mutex wm_mutex
;
2005 * Set during HW readout of watermarks/DDB. Some platforms
2006 * need to know when we're still using BIOS-provided values
2007 * (which we don't fully trust).
2009 bool distrust_bios_wm
;
2012 struct i915_runtime_pm pm
;
2014 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2016 int (*execbuf_submit
)(struct i915_execbuffer_params
*params
,
2017 struct drm_i915_gem_execbuffer2
*args
,
2018 struct list_head
*vmas
);
2019 int (*init_engines
)(struct drm_device
*dev
);
2020 void (*cleanup_engine
)(struct intel_engine_cs
*engine
);
2021 void (*stop_engine
)(struct intel_engine_cs
*engine
);
2024 * Is the GPU currently considered idle, or busy executing
2025 * userspace requests? Whilst idle, we allow runtime power
2026 * management to power down the hardware and display clocks.
2027 * In order to reduce the effect on performance, there
2028 * is a slight delay before we do so.
2030 unsigned int active_engines
;
2034 * We leave the user IRQ off as much as possible,
2035 * but this means that requests will finish and never
2036 * be retired once the system goes idle. Set a timer to
2037 * fire periodically while the ring is running. When it
2038 * fires, go retire requests.
2040 struct delayed_work retire_work
;
2043 * When we detect an idle GPU, we want to turn on
2044 * powersaving features. So once we see that there
2045 * are no more requests outstanding and no more
2046 * arrive within a small period of time, we fire
2047 * off the idle_work.
2049 struct delayed_work idle_work
;
2052 /* perform PHY state sanity checks? */
2053 bool chv_phy_assert
[2];
2055 struct intel_encoder
*dig_port_map
[I915_MAX_PORTS
];
2058 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2059 * will be rejected. Instead look for a better place.
2063 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
2065 return container_of(dev
, struct drm_i915_private
, drm
);
2068 static inline struct drm_i915_private
*dev_to_i915(struct device
*dev
)
2070 return to_i915(dev_get_drvdata(dev
));
2073 static inline struct drm_i915_private
*guc_to_i915(struct intel_guc
*guc
)
2075 return container_of(guc
, struct drm_i915_private
, guc
);
2078 /* Simple iterator over all initialised engines */
2079 #define for_each_engine(engine__, dev_priv__) \
2080 for ((engine__) = &(dev_priv__)->engine[0]; \
2081 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2083 for_each_if (intel_engine_initialized(engine__))
2085 /* Iterator with engine_id */
2086 #define for_each_engine_id(engine__, dev_priv__, id__) \
2087 for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
2088 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2090 for_each_if (((id__) = (engine__)->id, \
2091 intel_engine_initialized(engine__)))
2093 /* Iterator over subset of engines selected by mask */
2094 #define for_each_engine_masked(engine__, dev_priv__, mask__) \
2095 for ((engine__) = &(dev_priv__)->engine[0]; \
2096 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2098 for_each_if (((mask__) & intel_engine_flag(engine__)) && \
2099 intel_engine_initialized(engine__))
2101 enum hdmi_force_audio
{
2102 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
2103 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
2104 HDMI_AUDIO_AUTO
, /* trust EDID */
2105 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
2108 #define I915_GTT_OFFSET_NONE ((u32)-1)
2110 struct drm_i915_gem_object_ops
{
2112 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2114 /* Interface between the GEM object and its backing storage.
2115 * get_pages() is called once prior to the use of the associated set
2116 * of pages before to binding them into the GTT, and put_pages() is
2117 * called after we no longer need them. As we expect there to be
2118 * associated cost with migrating pages between the backing storage
2119 * and making them available for the GPU (e.g. clflush), we may hold
2120 * onto the pages after they are no longer referenced by the GPU
2121 * in case they may be used again shortly (for example migrating the
2122 * pages to a different memory domain within the GTT). put_pages()
2123 * will therefore most likely be called when the object itself is
2124 * being released or under memory pressure (where we attempt to
2125 * reap pages for the shrinker).
2127 int (*get_pages
)(struct drm_i915_gem_object
*);
2128 void (*put_pages
)(struct drm_i915_gem_object
*);
2130 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
2131 void (*release
)(struct drm_i915_gem_object
*);
2135 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2136 * considered to be the frontbuffer for the given plane interface-wise. This
2137 * doesn't mean that the hw necessarily already scans it out, but that any
2138 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2140 * We have one bit per pipe and per scanout plane type.
2142 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2143 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2144 #define INTEL_FRONTBUFFER_BITS \
2145 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2146 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2147 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2148 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2149 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2150 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2151 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2152 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2153 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2154 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2155 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2157 struct drm_i915_gem_object
{
2158 struct drm_gem_object base
;
2160 const struct drm_i915_gem_object_ops
*ops
;
2162 /** List of VMAs backed by this object */
2163 struct list_head vma_list
;
2165 /** Stolen memory for this object, instead of being backed by shmem. */
2166 struct drm_mm_node
*stolen
;
2167 struct list_head global_list
;
2169 struct list_head engine_list
[I915_NUM_ENGINES
];
2170 /** Used in execbuf to temporarily hold a ref */
2171 struct list_head obj_exec_link
;
2173 struct list_head batch_pool_link
;
2176 * This is set if the object is on the active lists (has pending
2177 * rendering and so a non-zero seqno), and is not set if it i s on
2178 * inactive (ready to be unbound) list.
2180 unsigned int active
:I915_NUM_ENGINES
;
2183 * This is set if the object has been written to since last bound
2186 unsigned int dirty
:1;
2189 * Fence register bits (if any) for this object. Will be set
2190 * as needed when mapped into the GTT.
2191 * Protected by dev->struct_mutex.
2193 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
2196 * Advice: are the backing pages purgeable?
2198 unsigned int madv
:2;
2201 * Current tiling mode for the object.
2203 unsigned int tiling_mode
:2;
2205 * Whether the tiling parameters for the currently associated fence
2206 * register have changed. Note that for the purposes of tracking
2207 * tiling changes we also treat the unfenced register, the register
2208 * slot that the object occupies whilst it executes a fenced
2209 * command (such as BLT on gen2/3), as a "fence".
2211 unsigned int fence_dirty
:1;
2214 * Is the object at the current location in the gtt mappable and
2215 * fenceable? Used to avoid costly recalculations.
2217 unsigned int map_and_fenceable
:1;
2220 * Whether the current gtt mapping needs to be mappable (and isn't just
2221 * mappable by accident). Track pin and fault separate for a more
2222 * accurate mappable working set.
2224 unsigned int fault_mappable
:1;
2227 * Is the object to be mapped as read-only to the GPU
2228 * Only honoured if hardware has relevant pte bit
2230 unsigned long gt_ro
:1;
2231 unsigned int cache_level
:3;
2232 unsigned int cache_dirty
:1;
2234 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
2236 unsigned int has_wc_mmap
;
2237 unsigned int pin_display
;
2239 struct sg_table
*pages
;
2240 int pages_pin_count
;
2242 struct scatterlist
*sg
;
2247 /** Breadcrumb of last rendering to the buffer.
2248 * There can only be one writer, but we allow for multiple readers.
2249 * If there is a writer that necessarily implies that all other
2250 * read requests are complete - but we may only be lazily clearing
2251 * the read requests. A read request is naturally the most recent
2252 * request on a ring, so we may have two different write and read
2253 * requests on one ring where the write request is older than the
2254 * read request. This allows for the CPU to read from an active
2255 * buffer by only waiting for the write to complete.
2257 struct drm_i915_gem_request
*last_read_req
[I915_NUM_ENGINES
];
2258 struct drm_i915_gem_request
*last_write_req
;
2259 /** Breadcrumb of last fenced GPU access to the buffer. */
2260 struct drm_i915_gem_request
*last_fenced_req
;
2262 /** Current tiling stride for the object, if it's tiled. */
2265 /** References from framebuffers, locks out tiling changes. */
2266 unsigned long framebuffer_references
;
2268 /** Record of address bit 17 of each page at last unbind. */
2269 unsigned long *bit_17
;
2272 /** for phy allocated objects */
2273 struct drm_dma_handle
*phys_handle
;
2275 struct i915_gem_userptr
{
2277 unsigned read_only
:1;
2278 unsigned workers
:4;
2279 #define I915_GEM_USERPTR_MAX_WORKERS 15
2281 struct i915_mm_struct
*mm
;
2282 struct i915_mmu_object
*mmu_object
;
2283 struct work_struct
*work
;
2287 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2290 i915_gem_object_has_struct_page(const struct drm_i915_gem_object
*obj
)
2292 return obj
->ops
->flags
& I915_GEM_OBJECT_HAS_STRUCT_PAGE
;
2296 * Optimised SGL iterator for GEM objects
2298 static __always_inline
struct sgt_iter
{
2299 struct scatterlist
*sgp
;
2306 } __sgt_iter(struct scatterlist
*sgl
, bool dma
) {
2307 struct sgt_iter s
= { .sgp
= sgl
};
2310 s
.max
= s
.curr
= s
.sgp
->offset
;
2311 s
.max
+= s
.sgp
->length
;
2313 s
.dma
= sg_dma_address(s
.sgp
);
2315 s
.pfn
= page_to_pfn(sg_page(s
.sgp
));
2322 * __sg_next - return the next scatterlist entry in a list
2323 * @sg: The current sg entry
2326 * If the entry is the last, return NULL; otherwise, step to the next
2327 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2328 * otherwise just return the pointer to the current element.
2330 static inline struct scatterlist
*__sg_next(struct scatterlist
*sg
)
2332 #ifdef CONFIG_DEBUG_SG
2333 BUG_ON(sg
->sg_magic
!= SG_MAGIC
);
2335 return sg_is_last(sg
) ? NULL
:
2336 likely(!sg_is_chain(++sg
)) ? sg
:
2341 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2342 * @__dmap: DMA address (output)
2343 * @__iter: 'struct sgt_iter' (iterator state, internal)
2344 * @__sgt: sg_table to iterate over (input)
2346 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2347 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2348 ((__dmap) = (__iter).dma + (__iter).curr); \
2349 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2350 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2353 * for_each_sgt_page - iterate over the pages of the given sg_table
2354 * @__pp: page pointer (output)
2355 * @__iter: 'struct sgt_iter' (iterator state, internal)
2356 * @__sgt: sg_table to iterate over (input)
2358 #define for_each_sgt_page(__pp, __iter, __sgt) \
2359 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2360 ((__pp) = (__iter).pfn == 0 ? NULL : \
2361 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2362 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2363 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2366 * Request queue structure.
2368 * The request queue allows us to note sequence numbers that have been emitted
2369 * and may be associated with active buffers to be retired.
2371 * By keeping this list, we can avoid having to do questionable sequence
2372 * number comparisons on buffer last_read|write_seqno. It also allows an
2373 * emission time to be associated with the request for tracking how far ahead
2374 * of the GPU the submission is.
2376 * The requests are reference counted, so upon creation they should have an
2377 * initial reference taken using kref_init
2379 struct drm_i915_gem_request
{
2382 /** On Which ring this request was generated */
2383 struct drm_i915_private
*i915
;
2384 struct intel_engine_cs
*engine
;
2385 struct intel_signal_node signaling
;
2387 /** GEM sequence number associated with the previous request,
2388 * when the HWS breadcrumb is equal to this the GPU is processing
2393 /** GEM sequence number associated with this request,
2394 * when the HWS breadcrumb is equal or greater than this the GPU
2395 * has finished processing this request.
2399 /** Position in the ringbuffer of the start of the request */
2403 * Position in the ringbuffer of the start of the postfix.
2404 * This is required to calculate the maximum available ringbuffer
2405 * space without overwriting the postfix.
2409 /** Position in the ringbuffer of the end of the whole request */
2412 /** Preallocate space in the ringbuffer for the emitting the request */
2416 * Context and ring buffer related to this request
2417 * Contexts are refcounted, so when this request is associated with a
2418 * context, we must increment the context's refcount, to guarantee that
2419 * it persists while any request is linked to it. Requests themselves
2420 * are also refcounted, so the request will only be freed when the last
2421 * reference to it is dismissed, and the code in
2422 * i915_gem_request_free() will then decrement the refcount on the
2425 struct i915_gem_context
*ctx
;
2426 struct intel_ringbuffer
*ringbuf
;
2429 * Context related to the previous request.
2430 * As the contexts are accessed by the hardware until the switch is
2431 * completed to a new context, the hardware may still be writing
2432 * to the context object after the breadcrumb is visible. We must
2433 * not unpin/unbind/prune that object whilst still active and so
2434 * we keep the previous context pinned until the following (this)
2435 * request is retired.
2437 struct i915_gem_context
*previous_context
;
2439 /** Batch buffer related to this request if any (used for
2440 error state dump only) */
2441 struct drm_i915_gem_object
*batch_obj
;
2443 /** Time at which this request was emitted, in jiffies. */
2444 unsigned long emitted_jiffies
;
2446 /** global list entry for this request */
2447 struct list_head list
;
2449 struct drm_i915_file_private
*file_priv
;
2450 /** file_priv list entry for this request */
2451 struct list_head client_list
;
2453 /** process identifier submitting this request */
2457 * The ELSP only accepts two elements at a time, so we queue
2458 * context/tail pairs on a given queue (ring->execlist_queue) until the
2459 * hardware is available. The queue serves a double purpose: we also use
2460 * it to keep track of the up to 2 contexts currently in the hardware
2461 * (usually one in execution and the other queued up by the GPU): We
2462 * only remove elements from the head of the queue when the hardware
2463 * informs us that an element has been completed.
2465 * All accesses to the queue are mediated by a spinlock
2466 * (ring->execlist_lock).
2469 /** Execlist link in the submission queue.*/
2470 struct list_head execlist_link
;
2472 /** Execlists no. of times this request has been sent to the ELSP */
2475 /** Execlists context hardware id. */
2479 struct drm_i915_gem_request
* __must_check
2480 i915_gem_request_alloc(struct intel_engine_cs
*engine
,
2481 struct i915_gem_context
*ctx
);
2482 void i915_gem_request_free(struct kref
*req_ref
);
2483 int i915_gem_request_add_to_client(struct drm_i915_gem_request
*req
,
2484 struct drm_file
*file
);
2486 static inline uint32_t
2487 i915_gem_request_get_seqno(struct drm_i915_gem_request
*req
)
2489 return req
? req
->seqno
: 0;
2492 static inline struct intel_engine_cs
*
2493 i915_gem_request_get_engine(struct drm_i915_gem_request
*req
)
2495 return req
? req
->engine
: NULL
;
2498 static inline struct drm_i915_gem_request
*
2499 i915_gem_request_reference(struct drm_i915_gem_request
*req
)
2502 kref_get(&req
->ref
);
2507 i915_gem_request_unreference(struct drm_i915_gem_request
*req
)
2509 kref_put(&req
->ref
, i915_gem_request_free
);
2512 static inline void i915_gem_request_assign(struct drm_i915_gem_request
**pdst
,
2513 struct drm_i915_gem_request
*src
)
2516 i915_gem_request_reference(src
);
2519 i915_gem_request_unreference(*pdst
);
2525 * XXX: i915_gem_request_completed should be here but currently needs the
2526 * definition of i915_seqno_passed() which is below. It will be moved in
2527 * a later patch when the call to i915_seqno_passed() is obsoleted...
2531 * A command that requires special handling by the command parser.
2533 struct drm_i915_cmd_descriptor
{
2535 * Flags describing how the command parser processes the command.
2537 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2538 * a length mask if not set
2539 * CMD_DESC_SKIP: The command is allowed but does not follow the
2540 * standard length encoding for the opcode range in
2542 * CMD_DESC_REJECT: The command is never allowed
2543 * CMD_DESC_REGISTER: The command should be checked against the
2544 * register whitelist for the appropriate ring
2545 * CMD_DESC_MASTER: The command is allowed if the submitting process
2549 #define CMD_DESC_FIXED (1<<0)
2550 #define CMD_DESC_SKIP (1<<1)
2551 #define CMD_DESC_REJECT (1<<2)
2552 #define CMD_DESC_REGISTER (1<<3)
2553 #define CMD_DESC_BITMASK (1<<4)
2554 #define CMD_DESC_MASTER (1<<5)
2557 * The command's unique identification bits and the bitmask to get them.
2558 * This isn't strictly the opcode field as defined in the spec and may
2559 * also include type, subtype, and/or subop fields.
2567 * The command's length. The command is either fixed length (i.e. does
2568 * not include a length field) or has a length field mask. The flag
2569 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2570 * a length mask. All command entries in a command table must include
2571 * length information.
2579 * Describes where to find a register address in the command to check
2580 * against the ring's register whitelist. Only valid if flags has the
2581 * CMD_DESC_REGISTER bit set.
2583 * A non-zero step value implies that the command may access multiple
2584 * registers in sequence (e.g. LRI), in that case step gives the
2585 * distance in dwords between individual offset fields.
2593 #define MAX_CMD_DESC_BITMASKS 3
2595 * Describes command checks where a particular dword is masked and
2596 * compared against an expected value. If the command does not match
2597 * the expected value, the parser rejects it. Only valid if flags has
2598 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2601 * If the check specifies a non-zero condition_mask then the parser
2602 * only performs the check when the bits specified by condition_mask
2609 u32 condition_offset
;
2611 } bits
[MAX_CMD_DESC_BITMASKS
];
2615 * A table of commands requiring special handling by the command parser.
2617 * Each ring has an array of tables. Each table consists of an array of command
2618 * descriptors, which must be sorted with command opcodes in ascending order.
2620 struct drm_i915_cmd_table
{
2621 const struct drm_i915_cmd_descriptor
*table
;
2625 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2626 #define __I915__(p) ({ \
2627 struct drm_i915_private *__p; \
2628 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2629 __p = (struct drm_i915_private *)p; \
2630 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2631 __p = to_i915((struct drm_device *)p); \
2636 #define INTEL_INFO(p) (&__I915__(p)->info)
2637 #define INTEL_GEN(p) (INTEL_INFO(p)->gen)
2638 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2640 #define REVID_FOREVER 0xff
2641 #define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision)
2643 #define GEN_FOREVER (0)
2645 * Returns true if Gen is in inclusive range [Start, End].
2647 * Use GEN_FOREVER for unbound start and or end.
2649 #define IS_GEN(p, s, e) ({ \
2650 unsigned int __s = (s), __e = (e); \
2651 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2652 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2653 if ((__s) != GEN_FOREVER) \
2655 if ((__e) == GEN_FOREVER) \
2656 __e = BITS_PER_LONG - 1; \
2659 !!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \
2663 * Return true if revision is in range [since,until] inclusive.
2665 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2667 #define IS_REVID(p, since, until) \
2668 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2670 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2671 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2672 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2673 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2674 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2675 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2676 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2677 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2678 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2679 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2680 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2681 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2682 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2683 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2684 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2685 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2686 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2687 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2688 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2689 INTEL_DEVID(dev) == 0x0152 || \
2690 INTEL_DEVID(dev) == 0x015a)
2691 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2692 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2693 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2694 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->is_broadwell)
2695 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2696 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2697 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2698 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2699 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2700 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2701 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2702 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2703 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2704 (INTEL_DEVID(dev) & 0xf) == 0xe))
2705 /* ULX machines are also considered ULT. */
2706 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2707 (INTEL_DEVID(dev) & 0xf) == 0xe)
2708 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2709 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2710 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2711 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2712 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2713 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2714 /* ULX machines are also considered ULT. */
2715 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2716 INTEL_DEVID(dev) == 0x0A1E)
2717 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2718 INTEL_DEVID(dev) == 0x1913 || \
2719 INTEL_DEVID(dev) == 0x1916 || \
2720 INTEL_DEVID(dev) == 0x1921 || \
2721 INTEL_DEVID(dev) == 0x1926)
2722 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2723 INTEL_DEVID(dev) == 0x1915 || \
2724 INTEL_DEVID(dev) == 0x191E)
2725 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2726 INTEL_DEVID(dev) == 0x5913 || \
2727 INTEL_DEVID(dev) == 0x5916 || \
2728 INTEL_DEVID(dev) == 0x5921 || \
2729 INTEL_DEVID(dev) == 0x5926)
2730 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2731 INTEL_DEVID(dev) == 0x5915 || \
2732 INTEL_DEVID(dev) == 0x591E)
2733 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2734 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2735 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2736 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2738 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2740 #define SKL_REVID_A0 0x0
2741 #define SKL_REVID_B0 0x1
2742 #define SKL_REVID_C0 0x2
2743 #define SKL_REVID_D0 0x3
2744 #define SKL_REVID_E0 0x4
2745 #define SKL_REVID_F0 0x5
2747 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2749 #define BXT_REVID_A0 0x0
2750 #define BXT_REVID_A1 0x1
2751 #define BXT_REVID_B0 0x3
2752 #define BXT_REVID_C0 0x9
2754 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2756 #define KBL_REVID_A0 0x0
2757 #define KBL_REVID_B0 0x1
2758 #define KBL_REVID_C0 0x2
2759 #define KBL_REVID_D0 0x3
2760 #define KBL_REVID_E0 0x4
2762 #define IS_KBL_REVID(p, since, until) \
2763 (IS_KABYLAKE(p) && IS_REVID(p, since, until))
2766 * The genX designation typically refers to the render engine, so render
2767 * capability related checks should use IS_GEN, while display and other checks
2768 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2771 #define IS_GEN2(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(1)))
2772 #define IS_GEN3(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(2)))
2773 #define IS_GEN4(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(3)))
2774 #define IS_GEN5(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(4)))
2775 #define IS_GEN6(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(5)))
2776 #define IS_GEN7(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(6)))
2777 #define IS_GEN8(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(7)))
2778 #define IS_GEN9(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(8)))
2780 #define ENGINE_MASK(id) BIT(id)
2781 #define RENDER_RING ENGINE_MASK(RCS)
2782 #define BSD_RING ENGINE_MASK(VCS)
2783 #define BLT_RING ENGINE_MASK(BCS)
2784 #define VEBOX_RING ENGINE_MASK(VECS)
2785 #define BSD2_RING ENGINE_MASK(VCS2)
2786 #define ALL_ENGINES (~0)
2788 #define HAS_ENGINE(dev_priv, id) \
2789 (!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id)))
2791 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2792 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2793 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2794 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2796 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2797 #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
2798 #define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
2799 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2801 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2803 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2804 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2805 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2806 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2807 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2809 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2810 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2812 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2813 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2815 /* WaRsDisableCoarsePowerGating:skl,bxt */
2816 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2817 (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
2818 IS_SKL_GT3(dev_priv) || \
2819 IS_SKL_GT4(dev_priv))
2822 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2823 * even when in MSI mode. This results in spurious interrupt warnings if the
2824 * legacy irq no. is shared with another device. The kernel then disables that
2825 * interrupt source and so prevents the other device from working properly.
2827 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2828 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2830 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2831 * rows, which changed the alignment requirements and fence programming.
2833 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2835 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2836 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2838 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2839 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2840 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2842 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2844 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2845 INTEL_INFO(dev)->gen >= 9)
2847 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2848 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2849 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2850 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2851 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2852 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2853 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2854 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2855 IS_KABYLAKE(dev) || IS_BROXTON(dev))
2856 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2857 #define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
2859 #define HAS_CSR(dev) (IS_GEN9(dev))
2862 * For now, anything with a GuC requires uCode loading, and then supports
2863 * command submission once loaded. But these are logically independent
2864 * properties, so we have separate macros to test them.
2866 #define HAS_GUC(dev) (IS_GEN9(dev))
2867 #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
2868 #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
2870 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2871 INTEL_INFO(dev)->gen >= 8)
2873 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2874 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2877 #define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu)
2879 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2880 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2881 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2882 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2883 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2884 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2885 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2886 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2887 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2888 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2889 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2890 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2892 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2893 #define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
2894 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2895 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2896 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2897 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2898 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2899 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2900 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2901 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2903 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2904 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2906 /* DPF == dynamic parity feature */
2907 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2908 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2910 #define GT_FREQUENCY_MULTIPLIER 50
2911 #define GEN9_FREQ_SCALER 3
2913 #include "i915_trace.h"
2915 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private
*dev_priv
)
2917 #ifdef CONFIG_INTEL_IOMMU
2918 if (INTEL_GEN(dev_priv
) >= 6 && intel_iommu_gfx_mapped
)
2924 extern int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
);
2925 extern int i915_resume_switcheroo(struct drm_device
*dev
);
2927 int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv
,
2932 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
2933 const char *fmt
, ...);
2935 #define i915_report_error(dev_priv, fmt, ...) \
2936 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2938 #ifdef CONFIG_COMPAT
2939 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2942 extern int intel_gpu_reset(struct drm_i915_private
*dev_priv
, u32 engine_mask
);
2943 extern bool intel_has_gpu_reset(struct drm_i915_private
*dev_priv
);
2944 extern int i915_reset(struct drm_i915_private
*dev_priv
);
2945 extern int intel_guc_reset(struct drm_i915_private
*dev_priv
);
2946 extern void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
);
2947 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2948 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2949 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2950 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2951 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2953 /* intel_hotplug.c */
2954 void intel_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
2955 u32 pin_mask
, u32 long_mask
);
2956 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2957 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
2958 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2959 bool intel_hpd_pin_to_port(enum hpd_pin pin
, enum port
*port
);
2962 static inline void i915_queue_hangcheck(struct drm_i915_private
*dev_priv
)
2964 unsigned long delay
;
2966 if (unlikely(!i915
.enable_hangcheck
))
2969 /* Don't continually defer the hangcheck so that it is always run at
2970 * least once after work has been scheduled on any ring. Otherwise,
2971 * we will ignore a hung ring if a second ring is kept busy.
2974 delay
= round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES
);
2975 queue_delayed_work(system_long_wq
,
2976 &dev_priv
->gpu_error
.hangcheck_work
, delay
);
2980 void i915_handle_error(struct drm_i915_private
*dev_priv
,
2982 const char *fmt
, ...);
2984 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2985 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2986 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2988 extern void intel_uncore_sanitize(struct drm_i915_private
*dev_priv
);
2989 extern void intel_uncore_early_sanitize(struct drm_i915_private
*dev_priv
,
2990 bool restore_forcewake
);
2991 extern void intel_uncore_init(struct drm_i915_private
*dev_priv
);
2992 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private
*dev_priv
);
2993 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private
*dev_priv
);
2994 extern void intel_uncore_fini(struct drm_i915_private
*dev_priv
);
2995 extern void intel_uncore_forcewake_reset(struct drm_i915_private
*dev_priv
,
2997 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
2998 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
2999 enum forcewake_domains domains
);
3000 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
3001 enum forcewake_domains domains
);
3002 /* Like above but the caller must manage the uncore.lock itself.
3003 * Must be used with I915_READ_FW and friends.
3005 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
3006 enum forcewake_domains domains
);
3007 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
3008 enum forcewake_domains domains
);
3009 u64
intel_uncore_edram_size(struct drm_i915_private
*dev_priv
);
3011 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
3013 int intel_wait_for_register(struct drm_i915_private
*dev_priv
,
3017 const unsigned long timeout_ms
);
3018 int intel_wait_for_register_fw(struct drm_i915_private
*dev_priv
,
3022 const unsigned long timeout_ms
);
3024 static inline bool intel_gvt_active(struct drm_i915_private
*dev_priv
)
3026 return dev_priv
->gvt
.initialized
;
3029 static inline bool intel_vgpu_active(struct drm_i915_private
*dev_priv
)
3031 return dev_priv
->vgpu
.active
;
3035 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
3039 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
3042 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
3043 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
3044 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
3047 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
3048 uint32_t interrupt_mask
,
3049 uint32_t enabled_irq_mask
);
3051 ilk_enable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3053 ilk_update_display_irq(dev_priv
, bits
, bits
);
3056 ilk_disable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3058 ilk_update_display_irq(dev_priv
, bits
, 0);
3060 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
3062 uint32_t interrupt_mask
,
3063 uint32_t enabled_irq_mask
);
3064 static inline void bdw_enable_pipe_irq(struct drm_i915_private
*dev_priv
,
3065 enum pipe pipe
, uint32_t bits
)
3067 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, bits
);
3069 static inline void bdw_disable_pipe_irq(struct drm_i915_private
*dev_priv
,
3070 enum pipe pipe
, uint32_t bits
)
3072 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, 0);
3074 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
3075 uint32_t interrupt_mask
,
3076 uint32_t enabled_irq_mask
);
3078 ibx_enable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3080 ibx_display_interrupt_update(dev_priv
, bits
, bits
);
3083 ibx_disable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3085 ibx_display_interrupt_update(dev_priv
, bits
, 0);
3089 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
3090 struct drm_file
*file_priv
);
3091 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
3092 struct drm_file
*file_priv
);
3093 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
3094 struct drm_file
*file_priv
);
3095 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
3096 struct drm_file
*file_priv
);
3097 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
3098 struct drm_file
*file_priv
);
3099 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
3100 struct drm_file
*file_priv
);
3101 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
3102 struct drm_file
*file_priv
);
3103 void i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
3104 struct drm_i915_gem_request
*req
);
3105 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params
*params
,
3106 struct drm_i915_gem_execbuffer2
*args
,
3107 struct list_head
*vmas
);
3108 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3109 struct drm_file
*file_priv
);
3110 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
3111 struct drm_file
*file_priv
);
3112 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3113 struct drm_file
*file_priv
);
3114 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3115 struct drm_file
*file
);
3116 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3117 struct drm_file
*file
);
3118 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3119 struct drm_file
*file_priv
);
3120 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3121 struct drm_file
*file_priv
);
3122 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
3123 struct drm_file
*file_priv
);
3124 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
3125 struct drm_file
*file_priv
);
3126 void i915_gem_init_userptr(struct drm_i915_private
*dev_priv
);
3127 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
3128 struct drm_file
*file
);
3129 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
3130 struct drm_file
*file_priv
);
3131 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
3132 struct drm_file
*file_priv
);
3133 void i915_gem_load_init(struct drm_device
*dev
);
3134 void i915_gem_load_cleanup(struct drm_device
*dev
);
3135 void i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
);
3136 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
);
3138 void *i915_gem_object_alloc(struct drm_device
*dev
);
3139 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
3140 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3141 const struct drm_i915_gem_object_ops
*ops
);
3142 struct drm_i915_gem_object
*i915_gem_object_create(struct drm_device
*dev
,
3144 struct drm_i915_gem_object
*i915_gem_object_create_from_data(
3145 struct drm_device
*dev
, const void *data
, size_t size
);
3146 void i915_gem_free_object(struct drm_gem_object
*obj
);
3147 void i915_gem_vma_destroy(struct i915_vma
*vma
);
3149 /* Flags used by pin/bind&friends. */
3150 #define PIN_MAPPABLE (1<<0)
3151 #define PIN_NONBLOCK (1<<1)
3152 #define PIN_GLOBAL (1<<2)
3153 #define PIN_OFFSET_BIAS (1<<3)
3154 #define PIN_USER (1<<4)
3155 #define PIN_UPDATE (1<<5)
3156 #define PIN_ZONE_4G (1<<6)
3157 #define PIN_HIGH (1<<7)
3158 #define PIN_OFFSET_FIXED (1<<8)
3159 #define PIN_OFFSET_MASK (~4095)
3161 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3162 struct i915_address_space
*vm
,
3166 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
3167 const struct i915_ggtt_view
*view
,
3171 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
3173 void __i915_vma_set_map_and_fenceable(struct i915_vma
*vma
);
3174 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
3176 * BEWARE: Do not use the function below unless you can _absolutely_
3177 * _guarantee_ VMA in question is _not in use_ anywhere.
3179 int __must_check
__i915_vma_unbind_no_wait(struct i915_vma
*vma
);
3180 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
3181 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
3182 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
3184 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
3185 int *needs_clflush
);
3187 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
3189 static inline int __sg_page_count(struct scatterlist
*sg
)
3191 return sg
->length
>> PAGE_SHIFT
;
3195 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
, int n
);
3197 static inline dma_addr_t
3198 i915_gem_object_get_dma_address(struct drm_i915_gem_object
*obj
, int n
)
3200 if (n
< obj
->get_page
.last
) {
3201 obj
->get_page
.sg
= obj
->pages
->sgl
;
3202 obj
->get_page
.last
= 0;
3205 while (obj
->get_page
.last
+ __sg_page_count(obj
->get_page
.sg
) <= n
) {
3206 obj
->get_page
.last
+= __sg_page_count(obj
->get_page
.sg
++);
3207 if (unlikely(sg_is_chain(obj
->get_page
.sg
)))
3208 obj
->get_page
.sg
= sg_chain_ptr(obj
->get_page
.sg
);
3211 return sg_dma_address(obj
->get_page
.sg
) + ((n
- obj
->get_page
.last
) << PAGE_SHIFT
);
3214 static inline struct page
*
3215 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
3217 if (WARN_ON(n
>= obj
->base
.size
>> PAGE_SHIFT
))
3220 if (n
< obj
->get_page
.last
) {
3221 obj
->get_page
.sg
= obj
->pages
->sgl
;
3222 obj
->get_page
.last
= 0;
3225 while (obj
->get_page
.last
+ __sg_page_count(obj
->get_page
.sg
) <= n
) {
3226 obj
->get_page
.last
+= __sg_page_count(obj
->get_page
.sg
++);
3227 if (unlikely(sg_is_chain(obj
->get_page
.sg
)))
3228 obj
->get_page
.sg
= sg_chain_ptr(obj
->get_page
.sg
);
3231 return nth_page(sg_page(obj
->get_page
.sg
), n
- obj
->get_page
.last
);
3234 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3236 BUG_ON(obj
->pages
== NULL
);
3237 obj
->pages_pin_count
++;
3240 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3242 BUG_ON(obj
->pages_pin_count
== 0);
3243 obj
->pages_pin_count
--;
3247 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3248 * @obj - the object to map into kernel address space
3250 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3251 * pages and then returns a contiguous mapping of the backing storage into
3252 * the kernel address space.
3254 * The caller must hold the struct_mutex, and is responsible for calling
3255 * i915_gem_object_unpin_map() when the mapping is no longer required.
3257 * Returns the pointer through which to access the mapped object, or an
3258 * ERR_PTR() on error.
3260 void *__must_check
i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
);
3263 * i915_gem_object_unpin_map - releases an earlier mapping
3264 * @obj - the object to unmap
3266 * After pinning the object and mapping its pages, once you are finished
3267 * with your access, call i915_gem_object_unpin_map() to release the pin
3268 * upon the mapping. Once the pin count reaches zero, that mapping may be
3271 * The caller must hold the struct_mutex.
3273 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object
*obj
)
3275 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3276 i915_gem_object_unpin_pages(obj
);
3279 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
3280 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3281 struct intel_engine_cs
*to
,
3282 struct drm_i915_gem_request
**to_req
);
3283 void i915_vma_move_to_active(struct i915_vma
*vma
,
3284 struct drm_i915_gem_request
*req
);
3285 int i915_gem_dumb_create(struct drm_file
*file_priv
,
3286 struct drm_device
*dev
,
3287 struct drm_mode_create_dumb
*args
);
3288 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
3289 uint32_t handle
, uint64_t *offset
);
3291 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
3292 struct drm_i915_gem_object
*new,
3293 unsigned frontbuffer_bits
);
3296 * Returns true if seq1 is later than seq2.
3299 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
3301 return (int32_t)(seq1
- seq2
) >= 0;
3304 static inline bool i915_gem_request_started(const struct drm_i915_gem_request
*req
)
3306 return i915_seqno_passed(intel_engine_get_seqno(req
->engine
),
3307 req
->previous_seqno
);
3310 static inline bool i915_gem_request_completed(const struct drm_i915_gem_request
*req
)
3312 return i915_seqno_passed(intel_engine_get_seqno(req
->engine
),
3316 bool __i915_spin_request(const struct drm_i915_gem_request
*request
,
3317 int state
, unsigned long timeout_us
);
3318 static inline bool i915_spin_request(const struct drm_i915_gem_request
*request
,
3319 int state
, unsigned long timeout_us
)
3321 return (i915_gem_request_started(request
) &&
3322 __i915_spin_request(request
, state
, timeout_us
));
3325 int __must_check
i915_gem_get_seqno(struct drm_i915_private
*dev_priv
, u32
*seqno
);
3326 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
3328 struct drm_i915_gem_request
*
3329 i915_gem_find_active_request(struct intel_engine_cs
*engine
);
3331 void i915_gem_retire_requests(struct drm_i915_private
*dev_priv
);
3332 void i915_gem_retire_requests_ring(struct intel_engine_cs
*engine
);
3334 static inline u32
i915_reset_counter(struct i915_gpu_error
*error
)
3336 return atomic_read(&error
->reset_counter
);
3339 static inline bool __i915_reset_in_progress(u32 reset
)
3341 return unlikely(reset
& I915_RESET_IN_PROGRESS_FLAG
);
3344 static inline bool __i915_reset_in_progress_or_wedged(u32 reset
)
3346 return unlikely(reset
& (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
3349 static inline bool __i915_terminally_wedged(u32 reset
)
3351 return unlikely(reset
& I915_WEDGED
);
3354 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
3356 return __i915_reset_in_progress(i915_reset_counter(error
));
3359 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error
*error
)
3361 return __i915_reset_in_progress_or_wedged(i915_reset_counter(error
));
3364 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
3366 return __i915_terminally_wedged(i915_reset_counter(error
));
3369 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
3371 return ((i915_reset_counter(error
) & ~I915_WEDGED
) + 1) / 2;
3374 void i915_gem_reset(struct drm_device
*dev
);
3375 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
3376 int __must_check
i915_gem_init(struct drm_device
*dev
);
3377 int i915_gem_init_engines(struct drm_device
*dev
);
3378 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
3379 void i915_gem_init_swizzling(struct drm_device
*dev
);
3380 void i915_gem_cleanup_engines(struct drm_device
*dev
);
3381 int __must_check
i915_gem_wait_for_idle(struct drm_i915_private
*dev_priv
);
3382 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
3383 void __i915_add_request(struct drm_i915_gem_request
*req
,
3384 struct drm_i915_gem_object
*batch_obj
,
3386 #define i915_add_request(req) \
3387 __i915_add_request(req, NULL, true)
3388 #define i915_add_request_no_flush(req) \
3389 __i915_add_request(req, NULL, false)
3390 int __i915_wait_request(struct drm_i915_gem_request
*req
,
3393 struct intel_rps_client
*rps
);
3394 int __must_check
i915_wait_request(struct drm_i915_gem_request
*req
);
3395 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
3397 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
3400 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
3403 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
3405 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3407 const struct i915_ggtt_view
*view
);
3408 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
3409 const struct i915_ggtt_view
*view
);
3410 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
3412 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
3413 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3416 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
3418 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
3419 int tiling_mode
, bool fenced
);
3421 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3422 enum i915_cache_level cache_level
);
3424 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3425 struct dma_buf
*dma_buf
);
3427 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3428 struct drm_gem_object
*gem_obj
, int flags
);
3430 u64
i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
3431 const struct i915_ggtt_view
*view
);
3432 u64
i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
3433 struct i915_address_space
*vm
);
3435 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*o
)
3437 return i915_gem_obj_ggtt_offset_view(o
, &i915_ggtt_view_normal
);
3440 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
3441 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
3442 const struct i915_ggtt_view
*view
);
3443 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
3444 struct i915_address_space
*vm
);
3447 i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
3448 struct i915_address_space
*vm
);
3450 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
3451 const struct i915_ggtt_view
*view
);
3454 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3455 struct i915_address_space
*vm
);
3457 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
3458 const struct i915_ggtt_view
*view
);
3460 static inline struct i915_vma
*
3461 i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
)
3463 return i915_gem_obj_to_ggtt_view(obj
, &i915_ggtt_view_normal
);
3465 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
);
3467 /* Some GGTT VM helpers */
3468 static inline struct i915_hw_ppgtt
*
3469 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3471 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3475 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
3477 return i915_gem_obj_ggtt_bound_view(obj
, &i915_ggtt_view_normal
);
3481 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
);
3483 static inline int __must_check
3484 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
3488 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3489 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3491 return i915_gem_object_pin(obj
, &ggtt
->base
,
3492 alignment
, flags
| PIN_GLOBAL
);
3495 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
3496 const struct i915_ggtt_view
*view
);
3498 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
)
3500 i915_gem_object_ggtt_unpin_view(obj
, &i915_ggtt_view_normal
);
3503 /* i915_gem_fence.c */
3504 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
3505 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
3507 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
3508 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
3510 void i915_gem_restore_fences(struct drm_device
*dev
);
3512 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
3513 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3514 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3516 /* i915_gem_context.c */
3517 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
3518 void i915_gem_context_lost(struct drm_i915_private
*dev_priv
);
3519 void i915_gem_context_fini(struct drm_device
*dev
);
3520 void i915_gem_context_reset(struct drm_device
*dev
);
3521 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
3522 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
3523 int i915_switch_context(struct drm_i915_gem_request
*req
);
3524 void i915_gem_context_free(struct kref
*ctx_ref
);
3525 struct drm_i915_gem_object
*
3526 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
3527 struct i915_gem_context
*
3528 i915_gem_context_create_gvt(struct drm_device
*dev
);
3530 static inline struct i915_gem_context
*
3531 i915_gem_context_lookup(struct drm_i915_file_private
*file_priv
, u32 id
)
3533 struct i915_gem_context
*ctx
;
3535 lockdep_assert_held(&file_priv
->dev_priv
->drm
.struct_mutex
);
3537 ctx
= idr_find(&file_priv
->context_idr
, id
);
3539 return ERR_PTR(-ENOENT
);
3544 static inline void i915_gem_context_reference(struct i915_gem_context
*ctx
)
3546 kref_get(&ctx
->ref
);
3549 static inline void i915_gem_context_unreference(struct i915_gem_context
*ctx
)
3551 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
3552 kref_put(&ctx
->ref
, i915_gem_context_free
);
3555 static inline bool i915_gem_context_is_default(const struct i915_gem_context
*c
)
3557 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
3560 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
3561 struct drm_file
*file
);
3562 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
3563 struct drm_file
*file
);
3564 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
3565 struct drm_file
*file_priv
);
3566 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
3567 struct drm_file
*file_priv
);
3568 int i915_gem_context_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
3569 struct drm_file
*file
);
3571 /* i915_gem_evict.c */
3572 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
3573 struct i915_address_space
*vm
,
3576 unsigned cache_level
,
3577 unsigned long start
,
3580 int __must_check
i915_gem_evict_for_vma(struct i915_vma
*target
);
3581 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
3583 /* belongs in i915_gem_gtt.h */
3584 static inline void i915_gem_chipset_flush(struct drm_i915_private
*dev_priv
)
3586 if (INTEL_GEN(dev_priv
) < 6)
3587 intel_gtt_chipset_flush();
3590 /* i915_gem_stolen.c */
3591 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3592 struct drm_mm_node
*node
, u64 size
,
3593 unsigned alignment
);
3594 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private
*dev_priv
,
3595 struct drm_mm_node
*node
, u64 size
,
3596 unsigned alignment
, u64 start
,
3598 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3599 struct drm_mm_node
*node
);
3600 int i915_gem_init_stolen(struct drm_device
*dev
);
3601 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3602 struct drm_i915_gem_object
*
3603 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
3604 struct drm_i915_gem_object
*
3605 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
3610 /* i915_gem_shrinker.c */
3611 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3612 unsigned long target
,
3614 #define I915_SHRINK_PURGEABLE 0x1
3615 #define I915_SHRINK_UNBOUND 0x2
3616 #define I915_SHRINK_BOUND 0x4
3617 #define I915_SHRINK_ACTIVE 0x8
3618 #define I915_SHRINK_VMAPS 0x10
3619 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3620 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3621 void i915_gem_shrinker_cleanup(struct drm_i915_private
*dev_priv
);
3624 /* i915_gem_tiling.c */
3625 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3627 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3629 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3630 obj
->tiling_mode
!= I915_TILING_NONE
;
3633 /* i915_gem_debug.c */
3635 int i915_verify_lists(struct drm_device
*dev
);
3637 #define i915_verify_lists(dev) 0
3640 /* i915_debugfs.c */
3641 #ifdef CONFIG_DEBUG_FS
3642 int i915_debugfs_register(struct drm_i915_private
*dev_priv
);
3643 void i915_debugfs_unregister(struct drm_i915_private
*dev_priv
);
3644 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3645 void intel_display_crc_init(struct drm_device
*dev
);
3647 static inline int i915_debugfs_register(struct drm_i915_private
*dev_priv
) {return 0;}
3648 static inline void i915_debugfs_unregister(struct drm_i915_private
*dev_priv
) {}
3649 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3651 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
3654 /* i915_gpu_error.c */
3656 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3657 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3658 const struct i915_error_state_file_priv
*error
);
3659 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3660 struct drm_i915_private
*i915
,
3661 size_t count
, loff_t pos
);
3662 static inline void i915_error_state_buf_release(
3663 struct drm_i915_error_state_buf
*eb
)
3667 void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3669 const char *error_msg
);
3670 void i915_error_state_get(struct drm_device
*dev
,
3671 struct i915_error_state_file_priv
*error_priv
);
3672 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
3673 void i915_destroy_error_state(struct drm_device
*dev
);
3675 void i915_get_extra_instdone(struct drm_i915_private
*dev_priv
, uint32_t *instdone
);
3676 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3678 /* i915_cmd_parser.c */
3679 int i915_cmd_parser_get_version(struct drm_i915_private
*dev_priv
);
3680 int i915_cmd_parser_init_ring(struct intel_engine_cs
*engine
);
3681 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*engine
);
3682 bool i915_needs_cmd_parser(struct intel_engine_cs
*engine
);
3683 int i915_parse_cmds(struct intel_engine_cs
*engine
,
3684 struct drm_i915_gem_object
*batch_obj
,
3685 struct drm_i915_gem_object
*shadow_batch_obj
,
3686 u32 batch_start_offset
,
3690 /* i915_suspend.c */
3691 extern int i915_save_state(struct drm_device
*dev
);
3692 extern int i915_restore_state(struct drm_device
*dev
);
3695 void i915_setup_sysfs(struct drm_device
*dev_priv
);
3696 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
3699 extern int intel_setup_gmbus(struct drm_device
*dev
);
3700 extern void intel_teardown_gmbus(struct drm_device
*dev
);
3701 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3704 extern struct i2c_adapter
*
3705 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3706 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3707 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3708 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3710 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3712 extern void intel_i2c_reset(struct drm_device
*dev
);
3715 int intel_bios_init(struct drm_i915_private
*dev_priv
);
3716 bool intel_bios_is_valid_vbt(const void *buf
, size_t size
);
3717 bool intel_bios_is_tv_present(struct drm_i915_private
*dev_priv
);
3718 bool intel_bios_is_lvds_present(struct drm_i915_private
*dev_priv
, u8
*i2c_pin
);
3719 bool intel_bios_is_port_present(struct drm_i915_private
*dev_priv
, enum port port
);
3720 bool intel_bios_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
3721 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private
*dev_priv
, enum port port
);
3722 bool intel_bios_is_dsi_present(struct drm_i915_private
*dev_priv
, enum port
*port
);
3723 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private
*dev_priv
,
3726 /* intel_opregion.c */
3728 extern int intel_opregion_setup(struct drm_i915_private
*dev_priv
);
3729 extern void intel_opregion_register(struct drm_i915_private
*dev_priv
);
3730 extern void intel_opregion_unregister(struct drm_i915_private
*dev_priv
);
3731 extern void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
);
3732 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3734 extern int intel_opregion_notify_adapter(struct drm_i915_private
*dev_priv
,
3736 extern int intel_opregion_get_panel_type(struct drm_i915_private
*dev_priv
);
3738 static inline int intel_opregion_setup(struct drm_i915_private
*dev
) { return 0; }
3739 static inline void intel_opregion_register(struct drm_i915_private
*dev_priv
) { }
3740 static inline void intel_opregion_unregister(struct drm_i915_private
*dev_priv
) { }
3741 static inline void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
)
3745 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3750 intel_opregion_notify_adapter(struct drm_i915_private
*dev
, pci_power_t state
)
3754 static inline int intel_opregion_get_panel_type(struct drm_i915_private
*dev
)
3762 extern void intel_register_dsm_handler(void);
3763 extern void intel_unregister_dsm_handler(void);
3765 static inline void intel_register_dsm_handler(void) { return; }
3766 static inline void intel_unregister_dsm_handler(void) { return; }
3767 #endif /* CONFIG_ACPI */
3769 /* intel_device_info.c */
3770 static inline struct intel_device_info
*
3771 mkwrite_device_info(struct drm_i915_private
*dev_priv
)
3773 return (struct intel_device_info
*)&dev_priv
->info
;
3776 void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv
);
3777 void intel_device_info_dump(struct drm_i915_private
*dev_priv
);
3780 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3781 extern void intel_modeset_init(struct drm_device
*dev
);
3782 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3783 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3784 extern int intel_connector_register(struct drm_connector
*);
3785 extern void intel_connector_unregister(struct drm_connector
*);
3786 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
3787 extern void intel_display_resume(struct drm_device
*dev
);
3788 extern void i915_redisable_vga(struct drm_device
*dev
);
3789 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
3790 extern bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
);
3791 extern void intel_init_pch_refclk(struct drm_device
*dev
);
3792 extern void intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
);
3793 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3796 extern bool i915_semaphore_is_enabled(struct drm_i915_private
*dev_priv
);
3797 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3798 struct drm_file
*file
);
3801 extern struct intel_overlay_error_state
*
3802 intel_overlay_capture_error_state(struct drm_i915_private
*dev_priv
);
3803 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3804 struct intel_overlay_error_state
*error
);
3806 extern struct intel_display_error_state
*
3807 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
);
3808 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3809 struct drm_device
*dev
,
3810 struct intel_display_error_state
*error
);
3812 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3813 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3815 /* intel_sideband.c */
3816 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3817 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3818 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3819 u32
vlv_iosf_sb_read(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
);
3820 void vlv_iosf_sb_write(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
, u32 val
);
3821 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3822 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3823 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3824 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3825 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3826 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3827 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3828 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3829 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3830 enum intel_sbi_destination destination
);
3831 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3832 enum intel_sbi_destination destination
);
3833 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3834 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3836 /* intel_dpio_phy.c */
3837 void chv_set_phy_signal_level(struct intel_encoder
*encoder
,
3838 u32 deemph_reg_value
, u32 margin_reg_value
,
3839 bool uniq_trans_scale
);
3840 void chv_data_lane_soft_reset(struct intel_encoder
*encoder
,
3842 void chv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3843 void chv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3844 void chv_phy_release_cl2_override(struct intel_encoder
*encoder
);
3845 void chv_phy_post_pll_disable(struct intel_encoder
*encoder
);
3847 void vlv_set_phy_signal_level(struct intel_encoder
*encoder
,
3848 u32 demph_reg_value
, u32 preemph_reg_value
,
3849 u32 uniqtranscale_reg_value
, u32 tx3_demph
);
3850 void vlv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3851 void vlv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3852 void vlv_phy_reset_lanes(struct intel_encoder
*encoder
);
3854 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3855 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3857 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3858 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3860 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3861 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3862 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3863 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3865 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3866 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3867 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3868 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3870 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3871 * will be implemented using 2 32-bit writes in an arbitrary order with
3872 * an arbitrary delay between them. This can cause the hardware to
3873 * act upon the intermediate value, possibly leading to corruption and
3874 * machine death. You have been warned.
3876 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3877 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3879 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3880 u32 upper, lower, old_upper, loop = 0; \
3881 upper = I915_READ(upper_reg); \
3883 old_upper = upper; \
3884 lower = I915_READ(lower_reg); \
3885 upper = I915_READ(upper_reg); \
3886 } while (upper != old_upper && loop++ < 2); \
3887 (u64)upper << 32 | lower; })
3889 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3890 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3892 #define __raw_read(x, s) \
3893 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3896 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3899 #define __raw_write(x, s) \
3900 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3901 i915_reg_t reg, uint##x##_t val) \
3903 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3918 /* These are untraced mmio-accessors that are only valid to be used inside
3919 * criticial sections inside IRQ handlers where forcewake is explicitly
3921 * Think twice, and think again, before using these.
3922 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3923 * intel_uncore_forcewake_irqunlock().
3925 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3926 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3927 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3928 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3930 /* "Broadcast RGB" property */
3931 #define INTEL_BROADCAST_RGB_AUTO 0
3932 #define INTEL_BROADCAST_RGB_FULL 1
3933 #define INTEL_BROADCAST_RGB_LIMITED 2
3935 static inline i915_reg_t
i915_vgacntrl_reg(struct drm_device
*dev
)
3937 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
3938 return VLV_VGACNTRL
;
3939 else if (INTEL_INFO(dev
)->gen
>= 5)
3940 return CPU_VGACNTRL
;
3945 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3947 unsigned long j
= msecs_to_jiffies(m
);
3949 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3952 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
3954 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
3957 static inline unsigned long
3958 timespec_to_jiffies_timeout(const struct timespec
*value
)
3960 unsigned long j
= timespec_to_jiffies(value
);
3962 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3966 * If you need to wait X milliseconds between events A and B, but event B
3967 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3968 * when event A happened, then just before event B you call this function and
3969 * pass the timestamp as the first argument, and X as the second argument.
3972 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3974 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3977 * Don't re-read the value of "jiffies" every time since it may change
3978 * behind our back and break the math.
3980 tmp_jiffies
= jiffies
;
3981 target_jiffies
= timestamp_jiffies
+
3982 msecs_to_jiffies_timeout(to_wait_ms
);
3984 if (time_after(target_jiffies
, tmp_jiffies
)) {
3985 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3986 while (remaining_jiffies
)
3988 schedule_timeout_uninterruptible(remaining_jiffies
);
3991 static inline bool __i915_request_irq_complete(struct drm_i915_gem_request
*req
)
3993 struct intel_engine_cs
*engine
= req
->engine
;
3995 /* Before we do the heavier coherent read of the seqno,
3996 * check the value (hopefully) in the CPU cacheline.
3998 if (i915_gem_request_completed(req
))
4001 /* Ensure our read of the seqno is coherent so that we
4002 * do not "miss an interrupt" (i.e. if this is the last
4003 * request and the seqno write from the GPU is not visible
4004 * by the time the interrupt fires, we will see that the
4005 * request is incomplete and go back to sleep awaiting
4006 * another interrupt that will never come.)
4008 * Strictly, we only need to do this once after an interrupt,
4009 * but it is easier and safer to do it every time the waiter
4012 if (engine
->irq_seqno_barrier
&&
4013 READ_ONCE(engine
->breadcrumbs
.irq_seqno_bh
) == current
&&
4014 cmpxchg_relaxed(&engine
->breadcrumbs
.irq_posted
, 1, 0)) {
4015 struct task_struct
*tsk
;
4017 /* The ordering of irq_posted versus applying the barrier
4018 * is crucial. The clearing of the current irq_posted must
4019 * be visible before we perform the barrier operation,
4020 * such that if a subsequent interrupt arrives, irq_posted
4021 * is reasserted and our task rewoken (which causes us to
4022 * do another __i915_request_irq_complete() immediately
4023 * and reapply the barrier). Conversely, if the clear
4024 * occurs after the barrier, then an interrupt that arrived
4025 * whilst we waited on the barrier would not trigger a
4026 * barrier on the next pass, and the read may not see the
4029 engine
->irq_seqno_barrier(engine
);
4031 /* If we consume the irq, but we are no longer the bottom-half,
4032 * the real bottom-half may not have serialised their own
4033 * seqno check with the irq-barrier (i.e. may have inspected
4034 * the seqno before we believe it coherent since they see
4035 * irq_posted == false but we are still running).
4038 tsk
= READ_ONCE(engine
->breadcrumbs
.irq_seqno_bh
);
4039 if (tsk
&& tsk
!= current
)
4040 /* Note that if the bottom-half is changed as we
4041 * are sending the wake-up, the new bottom-half will
4042 * be woken by whomever made the change. We only have
4043 * to worry about when we steal the irq-posted for
4046 wake_up_process(tsk
);
4049 if (i915_gem_request_completed(req
))
4053 /* We need to check whether any gpu reset happened in between
4054 * the request being submitted and now. If a reset has occurred,
4055 * the seqno will have been advance past ours and our request
4056 * is complete. If we are in the process of handling a reset,
4057 * the request is effectively complete as the rendering will
4058 * be discarded, but we need to return in order to drop the
4061 if (i915_reset_in_progress(&req
->i915
->gpu_error
))