1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/shmem_fs.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
50 #include <drm/drm_auth.h>
52 #include "i915_params.h"
55 #include "intel_bios.h"
56 #include "intel_dpll_mgr.h"
57 #include "intel_guc.h"
58 #include "intel_lrc.h"
59 #include "intel_ringbuffer.h"
62 #include "i915_gem_gtt.h"
63 #include "i915_gem_render_state.h"
65 #include "intel_gvt.h"
67 /* General customization:
70 #define DRIVER_NAME "i915"
71 #define DRIVER_DESC "Intel Graphics"
72 #define DRIVER_DATE "20160620"
75 /* Many gcc seem to no see through this and fall over :( */
77 #define WARN_ON(x) ({ \
78 bool __i915_warn_cond = (x); \
79 if (__builtin_constant_p(__i915_warn_cond)) \
80 BUILD_BUG_ON(__i915_warn_cond); \
81 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
83 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
87 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
89 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
90 (long) (x), __func__);
92 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
93 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
94 * which may not necessarily be a user visible problem. This will either
95 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
96 * enable distros and users to tailor their preferred amount of i915 abrt
99 #define I915_STATE_WARN(condition, format...) ({ \
100 int __ret_warn_on = !!(condition); \
101 if (unlikely(__ret_warn_on)) \
102 if (!WARN(i915.verbose_state_checks, format)) \
104 unlikely(__ret_warn_on); \
107 #define I915_STATE_WARN_ON(x) \
108 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
110 bool __i915_inject_load_failure(const char *func
, int line
);
111 #define i915_inject_load_failure() \
112 __i915_inject_load_failure(__func__, __LINE__)
114 static inline const char *yesno(bool v
)
116 return v
? "yes" : "no";
119 static inline const char *onoff(bool v
)
121 return v
? "on" : "off";
130 I915_MAX_PIPES
= _PIPE_EDP
132 #define pipe_name(p) ((p) + 'A')
144 static inline const char *transcoder_name(enum transcoder transcoder
)
146 switch (transcoder
) {
155 case TRANSCODER_DSI_A
:
157 case TRANSCODER_DSI_C
:
164 static inline bool transcoder_is_dsi(enum transcoder transcoder
)
166 return transcoder
== TRANSCODER_DSI_A
|| transcoder
== TRANSCODER_DSI_C
;
170 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
171 * number of planes per CRTC. Not all platforms really have this many planes,
172 * which means some arrays of size I915_MAX_PLANES may have unused entries
173 * between the topmost sprite plane and the cursor plane.
182 #define plane_name(p) ((p) + 'A')
184 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
194 #define port_name(p) ((p) + 'A')
196 #define I915_NUM_PHYS_VLV 2
208 enum intel_display_power_domain
{
212 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
213 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
214 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
215 POWER_DOMAIN_TRANSCODER_A
,
216 POWER_DOMAIN_TRANSCODER_B
,
217 POWER_DOMAIN_TRANSCODER_C
,
218 POWER_DOMAIN_TRANSCODER_EDP
,
219 POWER_DOMAIN_TRANSCODER_DSI_A
,
220 POWER_DOMAIN_TRANSCODER_DSI_C
,
221 POWER_DOMAIN_PORT_DDI_A_LANES
,
222 POWER_DOMAIN_PORT_DDI_B_LANES
,
223 POWER_DOMAIN_PORT_DDI_C_LANES
,
224 POWER_DOMAIN_PORT_DDI_D_LANES
,
225 POWER_DOMAIN_PORT_DDI_E_LANES
,
226 POWER_DOMAIN_PORT_DSI
,
227 POWER_DOMAIN_PORT_CRT
,
228 POWER_DOMAIN_PORT_OTHER
,
237 POWER_DOMAIN_MODESET
,
243 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
244 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
245 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
246 #define POWER_DOMAIN_TRANSCODER(tran) \
247 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
248 (tran) + POWER_DOMAIN_TRANSCODER_A)
252 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
264 #define for_each_hpd_pin(__pin) \
265 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
267 struct i915_hotplug
{
268 struct work_struct hotplug_work
;
271 unsigned long last_jiffies
;
276 HPD_MARK_DISABLED
= 2
278 } stats
[HPD_NUM_PINS
];
280 struct delayed_work reenable_work
;
282 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
285 struct work_struct dig_port_work
;
288 * if we get a HPD irq from DP and a HPD irq from non-DP
289 * the non-DP HPD could block the workqueue on a mode config
290 * mutex getting, that userspace may have taken. However
291 * userspace is waiting on the DP workqueue to run which is
292 * blocked behind the non-DP one.
294 struct workqueue_struct
*dp_wq
;
297 #define I915_GEM_GPU_DOMAINS \
298 (I915_GEM_DOMAIN_RENDER | \
299 I915_GEM_DOMAIN_SAMPLER | \
300 I915_GEM_DOMAIN_COMMAND | \
301 I915_GEM_DOMAIN_INSTRUCTION | \
302 I915_GEM_DOMAIN_VERTEX)
304 #define for_each_pipe(__dev_priv, __p) \
305 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
306 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
307 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
308 for_each_if ((__mask) & (1 << (__p)))
309 #define for_each_plane(__dev_priv, __pipe, __p) \
311 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
313 #define for_each_sprite(__dev_priv, __p, __s) \
315 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
318 #define for_each_port_masked(__port, __ports_mask) \
319 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
320 for_each_if ((__ports_mask) & (1 << (__port)))
322 #define for_each_crtc(dev, crtc) \
323 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
325 #define for_each_intel_plane(dev, intel_plane) \
326 list_for_each_entry(intel_plane, \
327 &dev->mode_config.plane_list, \
330 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
331 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, \
333 for_each_if ((plane_mask) & \
334 (1 << drm_plane_index(&intel_plane->base)))
336 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
337 list_for_each_entry(intel_plane, \
338 &(dev)->mode_config.plane_list, \
340 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
342 #define for_each_intel_crtc(dev, intel_crtc) \
343 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
345 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
346 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) \
347 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
349 #define for_each_intel_encoder(dev, intel_encoder) \
350 list_for_each_entry(intel_encoder, \
351 &(dev)->mode_config.encoder_list, \
354 #define for_each_intel_connector(dev, intel_connector) \
355 list_for_each_entry(intel_connector, \
356 &dev->mode_config.connector_list, \
359 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
360 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
361 for_each_if ((intel_encoder)->base.crtc == (__crtc))
363 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
364 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
365 for_each_if ((intel_connector)->base.encoder == (__encoder))
367 #define for_each_power_domain(domain, mask) \
368 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
369 for_each_if ((1 << (domain)) & (mask))
371 struct drm_i915_private
;
372 struct i915_mm_struct
;
373 struct i915_mmu_object
;
375 struct drm_i915_file_private
{
376 struct drm_i915_private
*dev_priv
;
377 struct drm_file
*file
;
381 struct list_head request_list
;
382 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
383 * chosen to prevent the CPU getting more than a frame ahead of the GPU
384 * (when using lax throttling for the frontbuffer). We also use it to
385 * offer free GPU waitboosts for severely congested workloads.
387 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
389 struct idr context_idr
;
391 struct intel_rps_client
{
392 struct list_head link
;
396 unsigned int bsd_ring
;
399 /* Used by dp and fdi links */
400 struct intel_link_m_n
{
408 void intel_link_compute_m_n(int bpp
, int nlanes
,
409 int pixel_clock
, int link_clock
,
410 struct intel_link_m_n
*m_n
);
412 /* Interface history:
415 * 1.2: Add Power Management
416 * 1.3: Add vblank support
417 * 1.4: Fix cmdbuffer path, add heap destroy
418 * 1.5: Add vblank pipe configuration
419 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
420 * - Support vertical blank on secondary display pipe
422 #define DRIVER_MAJOR 1
423 #define DRIVER_MINOR 6
424 #define DRIVER_PATCHLEVEL 0
426 #define WATCH_LISTS 0
428 struct opregion_header
;
429 struct opregion_acpi
;
430 struct opregion_swsci
;
431 struct opregion_asle
;
433 struct intel_opregion
{
434 struct opregion_header
*header
;
435 struct opregion_acpi
*acpi
;
436 struct opregion_swsci
*swsci
;
437 u32 swsci_gbda_sub_functions
;
438 u32 swsci_sbcb_sub_functions
;
439 struct opregion_asle
*asle
;
444 struct work_struct asle_work
;
446 #define OPREGION_SIZE (8*1024)
448 struct intel_overlay
;
449 struct intel_overlay_error_state
;
451 #define I915_FENCE_REG_NONE -1
452 #define I915_MAX_NUM_FENCES 32
453 /* 32 fences + sign bit for FENCE_REG_NONE */
454 #define I915_MAX_NUM_FENCE_BITS 6
456 struct drm_i915_fence_reg
{
457 struct list_head lru_list
;
458 struct drm_i915_gem_object
*obj
;
462 struct sdvo_device_mapping
{
471 struct intel_display_error_state
;
473 struct drm_i915_error_state
{
483 /* Generic register state */
491 u32 error
; /* gen6+ */
492 u32 err_int
; /* gen7 */
493 u32 fault_data0
; /* gen8, gen9 */
494 u32 fault_data1
; /* gen8, gen9 */
500 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
501 u64 fence
[I915_MAX_NUM_FENCES
];
502 struct intel_overlay_error_state
*overlay
;
503 struct intel_display_error_state
*display
;
504 struct drm_i915_error_object
*semaphore_obj
;
506 struct drm_i915_error_ring
{
508 /* Software tracked state */
512 enum intel_ring_hangcheck_action hangcheck_action
;
515 /* our own tracking of ring head and tail */
520 u32 semaphore_seqno
[I915_NUM_ENGINES
- 1];
539 u32 rc_psmi
; /* sleep state */
540 u32 semaphore_mboxes
[I915_NUM_ENGINES
- 1];
542 struct drm_i915_error_object
{
546 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
548 struct drm_i915_error_object
*wa_ctx
;
550 struct drm_i915_error_request
{
556 struct drm_i915_error_waiter
{
557 char comm
[TASK_COMM_LEN
];
571 char comm
[TASK_COMM_LEN
];
572 } ring
[I915_NUM_ENGINES
];
574 struct drm_i915_error_buffer
{
577 u32 rseqno
[I915_NUM_ENGINES
], wseqno
;
581 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
589 } **active_bo
, **pinned_bo
;
591 u32
*active_bo_count
, *pinned_bo_count
;
595 struct intel_connector
;
596 struct intel_encoder
;
597 struct intel_crtc_state
;
598 struct intel_initial_plane_config
;
603 struct drm_i915_display_funcs
{
604 int (*get_display_clock_speed
)(struct drm_device
*dev
);
605 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
606 int (*compute_pipe_wm
)(struct intel_crtc_state
*cstate
);
607 int (*compute_intermediate_wm
)(struct drm_device
*dev
,
608 struct intel_crtc
*intel_crtc
,
609 struct intel_crtc_state
*newstate
);
610 void (*initial_watermarks
)(struct intel_crtc_state
*cstate
);
611 void (*optimize_watermarks
)(struct intel_crtc_state
*cstate
);
612 int (*compute_global_watermarks
)(struct drm_atomic_state
*state
);
613 void (*update_wm
)(struct drm_crtc
*crtc
);
614 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
615 void (*modeset_commit_cdclk
)(struct drm_atomic_state
*state
);
616 /* Returns the active state of the crtc, and if the crtc is active,
617 * fills out the pipe-config with the hw state. */
618 bool (*get_pipe_config
)(struct intel_crtc
*,
619 struct intel_crtc_state
*);
620 void (*get_initial_plane_config
)(struct intel_crtc
*,
621 struct intel_initial_plane_config
*);
622 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
623 struct intel_crtc_state
*crtc_state
);
624 void (*crtc_enable
)(struct drm_crtc
*crtc
);
625 void (*crtc_disable
)(struct drm_crtc
*crtc
);
626 void (*audio_codec_enable
)(struct drm_connector
*connector
,
627 struct intel_encoder
*encoder
,
628 const struct drm_display_mode
*adjusted_mode
);
629 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
630 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
631 void (*init_clock_gating
)(struct drm_device
*dev
);
632 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
633 struct drm_framebuffer
*fb
,
634 struct drm_i915_gem_object
*obj
,
635 struct drm_i915_gem_request
*req
,
637 void (*hpd_irq_setup
)(struct drm_i915_private
*dev_priv
);
638 /* clock updates for mode set */
640 /* render clock increase/decrease */
641 /* display clock increase/decrease */
642 /* pll clock increase/decrease */
644 void (*load_csc_matrix
)(struct drm_crtc_state
*crtc_state
);
645 void (*load_luts
)(struct drm_crtc_state
*crtc_state
);
648 enum forcewake_domain_id
{
649 FW_DOMAIN_ID_RENDER
= 0,
650 FW_DOMAIN_ID_BLITTER
,
656 enum forcewake_domains
{
657 FORCEWAKE_RENDER
= (1 << FW_DOMAIN_ID_RENDER
),
658 FORCEWAKE_BLITTER
= (1 << FW_DOMAIN_ID_BLITTER
),
659 FORCEWAKE_MEDIA
= (1 << FW_DOMAIN_ID_MEDIA
),
660 FORCEWAKE_ALL
= (FORCEWAKE_RENDER
|
665 #define FW_REG_READ (1)
666 #define FW_REG_WRITE (2)
668 enum forcewake_domains
669 intel_uncore_forcewake_for_reg(struct drm_i915_private
*dev_priv
,
670 i915_reg_t reg
, unsigned int op
);
672 struct intel_uncore_funcs
{
673 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
674 enum forcewake_domains domains
);
675 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
676 enum forcewake_domains domains
);
678 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
679 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
680 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
681 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
683 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
684 uint8_t val
, bool trace
);
685 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
686 uint16_t val
, bool trace
);
687 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
688 uint32_t val
, bool trace
);
689 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
690 uint64_t val
, bool trace
);
693 struct intel_uncore
{
694 spinlock_t lock
; /** lock is also taken in irq contexts. */
696 struct intel_uncore_funcs funcs
;
699 enum forcewake_domains fw_domains
;
701 struct intel_uncore_forcewake_domain
{
702 struct drm_i915_private
*i915
;
703 enum forcewake_domain_id id
;
704 enum forcewake_domains mask
;
706 struct hrtimer timer
;
713 } fw_domain
[FW_DOMAIN_ID_COUNT
];
715 int unclaimed_mmio_check
;
718 /* Iterate over initialised fw domains */
719 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
720 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
721 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
723 for_each_if ((mask__) & (domain__)->mask)
725 #define for_each_fw_domain(domain__, dev_priv__) \
726 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
728 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
729 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
730 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
733 struct work_struct work
;
735 uint32_t *dmc_payload
;
736 uint32_t dmc_fw_size
;
739 i915_reg_t mmioaddr
[8];
740 uint32_t mmiodata
[8];
742 uint32_t allowed_dc_mask
;
745 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
746 func(is_mobile) sep \
749 func(is_i945gm) sep \
751 func(need_gfx_hws) sep \
753 func(is_pineview) sep \
754 func(is_broadwater) sep \
755 func(is_crestline) sep \
756 func(is_ivybridge) sep \
757 func(is_valleyview) sep \
758 func(is_cherryview) sep \
759 func(is_haswell) sep \
760 func(is_broadwell) sep \
761 func(is_skylake) sep \
762 func(is_broxton) sep \
763 func(is_kabylake) sep \
764 func(is_preliminary) sep \
766 func(has_pipe_cxsr) sep \
767 func(has_hotplug) sep \
768 func(cursor_needs_physical) sep \
769 func(has_overlay) sep \
770 func(overlay_needs_physical) sep \
771 func(supports_tv) sep \
773 func(has_snoop) sep \
775 func(has_fpga_dbg) sep \
778 #define DEFINE_FLAG(name) u8 name:1
779 #define SEP_SEMICOLON ;
781 struct intel_device_info
{
782 u32 display_mmio_offset
;
785 u8 num_sprites
[I915_MAX_PIPES
];
788 u8 ring_mask
; /* Rings supported by the HW */
789 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
790 /* Register offsets for the various display pipes and transcoders */
791 int pipe_offsets
[I915_MAX_TRANSCODERS
];
792 int trans_offsets
[I915_MAX_TRANSCODERS
];
793 int palette_offsets
[I915_MAX_PIPES
];
794 int cursor_offsets
[I915_MAX_PIPES
];
796 /* Slice/subslice/EU info */
799 u8 subslice_per_slice
;
803 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
806 u8 has_subslice_pg
:1;
810 u16 degamma_lut_size
;
818 enum i915_cache_level
{
820 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
821 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
822 caches, eg sampler/render caches, and the
823 large Last-Level-Cache. LLC is coherent with
824 the CPU, but L3 is only visible to the GPU. */
825 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
828 struct i915_ctx_hang_stats
{
829 /* This context had batch pending when hang was declared */
830 unsigned batch_pending
;
832 /* This context had batch active when hang was declared */
833 unsigned batch_active
;
835 /* Time when this context was last blamed for a GPU reset */
836 unsigned long guilty_ts
;
838 /* If the contexts causes a second GPU hang within this time,
839 * it is permanently banned from submitting any more work.
841 unsigned long ban_period_seconds
;
843 /* This context is banned to submit more work */
847 /* This must match up with the value previously used for execbuf2.rsvd1. */
848 #define DEFAULT_CONTEXT_HANDLE 0
851 * struct i915_gem_context - as the name implies, represents a context.
852 * @ref: reference count.
853 * @user_handle: userspace tracking identity for this context.
854 * @remap_slice: l3 row remapping information.
855 * @flags: context specific flags:
856 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
857 * @file_priv: filp associated with this context (NULL for global default
859 * @hang_stats: information about the role of this context in possible GPU
861 * @ppgtt: virtual memory space used by this context.
862 * @legacy_hw_ctx: render context backing object and whether it is correctly
863 * initialized (legacy ring submission mechanism only).
864 * @link: link in the global list of contexts.
866 * Contexts are memory images used by the hardware to store copies of their
869 struct i915_gem_context
{
871 struct drm_i915_private
*i915
;
872 struct drm_i915_file_private
*file_priv
;
873 struct i915_hw_ppgtt
*ppgtt
;
875 struct i915_ctx_hang_stats hang_stats
;
877 /* Unique identifier for this context, used by the hw for tracking */
879 #define CONTEXT_NO_ZEROMAP BIT(0)
880 #define CONTEXT_NO_ERROR_CAPTURE BIT(1)
886 struct intel_context
{
887 struct drm_i915_gem_object
*state
;
888 struct intel_ringbuffer
*ringbuf
;
889 struct i915_vma
*lrc_vma
;
890 uint32_t *lrc_reg_state
;
894 } engine
[I915_NUM_ENGINES
];
897 struct atomic_notifier_head status_notifier
;
898 bool execlists_force_single_submission
;
900 struct list_head link
;
914 /* This is always the inner lock when overlapping with struct_mutex and
915 * it's the outer lock when overlapping with stolen_lock. */
918 unsigned int possible_framebuffer_bits
;
919 unsigned int busy_bits
;
920 unsigned int visible_pipes_mask
;
921 struct intel_crtc
*crtc
;
923 struct drm_mm_node compressed_fb
;
924 struct drm_mm_node
*compressed_llb
;
931 struct intel_fbc_state_cache
{
933 unsigned int mode_flags
;
934 uint32_t hsw_bdw_pixel_rate
;
938 unsigned int rotation
;
946 uint32_t pixel_format
;
949 unsigned int tiling_mode
;
953 struct intel_fbc_reg_params
{
957 unsigned int fence_y_offset
;
962 uint32_t pixel_format
;
970 struct intel_fbc_work
{
972 u32 scheduled_vblank
;
973 struct work_struct work
;
976 const char *no_fbc_reason
;
980 * HIGH_RR is the highest eDP panel refresh rate read from EDID
981 * LOW_RR is the lowest eDP panel refresh rate found from EDID
982 * parsing for same resolution.
984 enum drrs_refresh_rate_type
{
987 DRRS_MAX_RR
, /* RR count */
990 enum drrs_support_type
{
991 DRRS_NOT_SUPPORTED
= 0,
992 STATIC_DRRS_SUPPORT
= 1,
993 SEAMLESS_DRRS_SUPPORT
= 2
999 struct delayed_work work
;
1000 struct intel_dp
*dp
;
1001 unsigned busy_frontbuffer_bits
;
1002 enum drrs_refresh_rate_type refresh_rate_type
;
1003 enum drrs_support_type type
;
1010 struct intel_dp
*enabled
;
1012 struct delayed_work work
;
1013 unsigned busy_frontbuffer_bits
;
1015 bool aux_frame_sync
;
1020 PCH_NONE
= 0, /* No PCH present */
1021 PCH_IBX
, /* Ibexpeak PCH */
1022 PCH_CPT
, /* Cougarpoint PCH */
1023 PCH_LPT
, /* Lynxpoint PCH */
1024 PCH_SPT
, /* Sunrisepoint PCH */
1028 enum intel_sbi_destination
{
1033 #define QUIRK_PIPEA_FORCE (1<<0)
1034 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1035 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1036 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1037 #define QUIRK_PIPEB_FORCE (1<<4)
1038 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1041 struct intel_fbc_work
;
1043 struct intel_gmbus
{
1044 struct i2c_adapter adapter
;
1045 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1048 i915_reg_t gpio_reg
;
1049 struct i2c_algo_bit_data bit_algo
;
1050 struct drm_i915_private
*dev_priv
;
1053 struct i915_suspend_saved_registers
{
1056 u32 savePP_ON_DELAYS
;
1057 u32 savePP_OFF_DELAYS
;
1062 u32 saveFBC_CONTROL
;
1063 u32 saveCACHE_MODE_0
;
1064 u32 saveMI_ARB_STATE
;
1068 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1069 u32 savePCH_PORT_HOTPLUG
;
1073 struct vlv_s0ix_state
{
1080 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1081 u32 media_max_req_count
;
1082 u32 gfx_max_req_count
;
1108 u32 rp_down_timeout
;
1114 /* Display 1 CZ domain */
1119 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1121 /* GT SA CZ domain */
1128 /* Display 2 CZ domain */
1132 u32 clock_gate_dis2
;
1135 struct intel_rps_ei
{
1141 struct intel_gen6_power_mgmt
{
1143 * work, interrupts_enabled and pm_iir are protected by
1144 * dev_priv->irq_lock
1146 struct work_struct work
;
1147 bool interrupts_enabled
;
1152 /* Frequencies are stored in potentially platform dependent multiples.
1153 * In other words, *_freq needs to be multiplied by X to be interesting.
1154 * Soft limits are those which are used for the dynamic reclocking done
1155 * by the driver (raise frequencies under heavy loads, and lower for
1156 * lighter loads). Hard limits are those imposed by the hardware.
1158 * A distinction is made for overclocking, which is never enabled by
1159 * default, and is considered to be above the hard limit if it's
1162 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1163 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1164 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1165 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1166 u8 min_freq
; /* AKA RPn. Minimum frequency */
1167 u8 idle_freq
; /* Frequency to request when we are idle */
1168 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1169 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1170 u8 rp0_freq
; /* Non-overclocked max frequency. */
1171 u16 gpll_ref_freq
; /* vlv/chv GPLL reference frequency */
1173 u8 up_threshold
; /* Current %busy required to uplock */
1174 u8 down_threshold
; /* Current %busy required to downclock */
1177 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1179 spinlock_t client_lock
;
1180 struct list_head clients
;
1184 struct delayed_work delayed_resume_work
;
1187 struct intel_rps_client semaphores
, mmioflips
;
1189 /* manual wa residency calculations */
1190 struct intel_rps_ei up_ei
, down_ei
;
1193 * Protects RPS/RC6 register access and PCU communication.
1194 * Must be taken after struct_mutex if nested. Note that
1195 * this lock may be held for long periods of time when
1196 * talking to hw - so only take it when talking to hw!
1198 struct mutex hw_lock
;
1201 /* defined intel_pm.c */
1202 extern spinlock_t mchdev_lock
;
1204 struct intel_ilk_power_mgmt
{
1212 unsigned long last_time1
;
1213 unsigned long chipset_power
;
1216 unsigned long gfx_power
;
1223 struct drm_i915_private
;
1224 struct i915_power_well
;
1226 struct i915_power_well_ops
{
1228 * Synchronize the well's hw state to match the current sw state, for
1229 * example enable/disable it based on the current refcount. Called
1230 * during driver init and resume time, possibly after first calling
1231 * the enable/disable handlers.
1233 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1234 struct i915_power_well
*power_well
);
1236 * Enable the well and resources that depend on it (for example
1237 * interrupts located on the well). Called after the 0->1 refcount
1240 void (*enable
)(struct drm_i915_private
*dev_priv
,
1241 struct i915_power_well
*power_well
);
1243 * Disable the well and resources that depend on it. Called after
1244 * the 1->0 refcount transition.
1246 void (*disable
)(struct drm_i915_private
*dev_priv
,
1247 struct i915_power_well
*power_well
);
1248 /* Returns the hw enabled state. */
1249 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1250 struct i915_power_well
*power_well
);
1253 /* Power well structure for haswell */
1254 struct i915_power_well
{
1257 /* power well enable/disable usage count */
1259 /* cached hw enabled state */
1261 unsigned long domains
;
1263 const struct i915_power_well_ops
*ops
;
1266 struct i915_power_domains
{
1268 * Power wells needed for initialization at driver init and suspend
1269 * time are on. They are kept on until after the first modeset.
1273 int power_well_count
;
1276 int domain_use_count
[POWER_DOMAIN_NUM
];
1277 struct i915_power_well
*power_wells
;
1280 #define MAX_L3_SLICES 2
1281 struct intel_l3_parity
{
1282 u32
*remap_info
[MAX_L3_SLICES
];
1283 struct work_struct error_work
;
1287 struct i915_gem_mm
{
1288 /** Memory allocator for GTT stolen memory */
1289 struct drm_mm stolen
;
1290 /** Protects the usage of the GTT stolen memory allocator. This is
1291 * always the inner lock when overlapping with struct_mutex. */
1292 struct mutex stolen_lock
;
1294 /** List of all objects in gtt_space. Used to restore gtt
1295 * mappings on resume */
1296 struct list_head bound_list
;
1298 * List of objects which are not bound to the GTT (thus
1299 * are idle and not used by the GPU) but still have
1300 * (presumably uncached) pages still attached.
1302 struct list_head unbound_list
;
1304 /** Usable portion of the GTT for GEM */
1305 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1307 /** PPGTT used for aliasing the PPGTT with the GTT */
1308 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1310 struct notifier_block oom_notifier
;
1311 struct notifier_block vmap_notifier
;
1312 struct shrinker shrinker
;
1313 bool shrinker_no_lock_stealing
;
1315 /** LRU list of objects with fence regs on them. */
1316 struct list_head fence_list
;
1319 * Are we in a non-interruptible section of code like
1324 /* the indicator for dispatch video commands on two BSD rings */
1325 unsigned int bsd_ring_dispatch_index
;
1327 /** Bit 6 swizzling required for X tiling */
1328 uint32_t bit_6_swizzle_x
;
1329 /** Bit 6 swizzling required for Y tiling */
1330 uint32_t bit_6_swizzle_y
;
1332 /* accounting, useful for userland debugging */
1333 spinlock_t object_stat_lock
;
1334 size_t object_memory
;
1338 struct drm_i915_error_state_buf
{
1339 struct drm_i915_private
*i915
;
1348 struct i915_error_state_file_priv
{
1349 struct drm_device
*dev
;
1350 struct drm_i915_error_state
*error
;
1353 struct i915_gpu_error
{
1354 /* For hangcheck timer */
1355 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1356 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1357 /* Hang gpu twice in this window and your context gets banned */
1358 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1360 struct delayed_work hangcheck_work
;
1362 /* For reset and error_state handling. */
1364 /* Protected by the above dev->gpu_error.lock. */
1365 struct drm_i915_error_state
*first_error
;
1367 unsigned long missed_irq_rings
;
1370 * State variable controlling the reset flow and count
1372 * This is a counter which gets incremented when reset is triggered,
1373 * and again when reset has been handled. So odd values (lowest bit set)
1374 * means that reset is in progress and even values that
1375 * (reset_counter >> 1):th reset was successfully completed.
1377 * If reset is not completed succesfully, the I915_WEDGE bit is
1378 * set meaning that hardware is terminally sour and there is no
1379 * recovery. All waiters on the reset_queue will be woken when
1382 * This counter is used by the wait_seqno code to notice that reset
1383 * event happened and it needs to restart the entire ioctl (since most
1384 * likely the seqno it waited for won't ever signal anytime soon).
1386 * This is important for lock-free wait paths, where no contended lock
1387 * naturally enforces the correct ordering between the bail-out of the
1388 * waiter and the gpu reset work code.
1390 atomic_t reset_counter
;
1392 #define I915_RESET_IN_PROGRESS_FLAG 1
1393 #define I915_WEDGED (1 << 31)
1396 * Waitqueue to signal when a hang is detected. Used to for waiters
1397 * to release the struct_mutex for the reset to procede.
1399 wait_queue_head_t wait_queue
;
1402 * Waitqueue to signal when the reset has completed. Used by clients
1403 * that wait for dev_priv->mm.wedged to settle.
1405 wait_queue_head_t reset_queue
;
1407 /* For missed irq/seqno simulation. */
1408 unsigned long test_irq_rings
;
1411 enum modeset_restore
{
1412 MODESET_ON_LID_OPEN
,
1417 #define DP_AUX_A 0x40
1418 #define DP_AUX_B 0x10
1419 #define DP_AUX_C 0x20
1420 #define DP_AUX_D 0x30
1422 #define DDC_PIN_B 0x05
1423 #define DDC_PIN_C 0x04
1424 #define DDC_PIN_D 0x06
1426 struct ddi_vbt_port_info
{
1428 * This is an index in the HDMI/DVI DDI buffer translation table.
1429 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1430 * populate this field.
1432 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1433 uint8_t hdmi_level_shift
;
1435 uint8_t supports_dvi
:1;
1436 uint8_t supports_hdmi
:1;
1437 uint8_t supports_dp
:1;
1439 uint8_t alternate_aux_channel
;
1440 uint8_t alternate_ddc_pin
;
1442 uint8_t dp_boost_level
;
1443 uint8_t hdmi_boost_level
;
1446 enum psr_lines_to_wait
{
1447 PSR_0_LINES_TO_WAIT
= 0,
1449 PSR_4_LINES_TO_WAIT
,
1453 struct intel_vbt_data
{
1454 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1455 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1458 unsigned int int_tv_support
:1;
1459 unsigned int lvds_dither
:1;
1460 unsigned int lvds_vbt
:1;
1461 unsigned int int_crt_support
:1;
1462 unsigned int lvds_use_ssc
:1;
1463 unsigned int display_clock_mode
:1;
1464 unsigned int fdi_rx_polarity_inverted
:1;
1465 unsigned int panel_type
:4;
1467 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1469 enum drrs_support_type drrs_type
;
1480 struct edp_power_seq pps
;
1485 bool require_aux_wakeup
;
1487 enum psr_lines_to_wait lines_to_wait
;
1488 int tp1_wakeup_time
;
1489 int tp2_tp3_wakeup_time
;
1495 bool active_low_pwm
;
1496 u8 min_brightness
; /* min_brightness/255 of max */
1497 enum intel_backlight_type type
;
1503 struct mipi_config
*config
;
1504 struct mipi_pps_data
*pps
;
1508 const u8
*sequence
[MIPI_SEQ_MAX
];
1514 union child_device_config
*child_dev
;
1516 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1517 struct sdvo_device_mapping sdvo_mappings
[2];
1520 enum intel_ddb_partitioning
{
1522 INTEL_DDB_PART_5_6
, /* IVB+ */
1525 struct intel_wm_level
{
1533 struct ilk_wm_values
{
1534 uint32_t wm_pipe
[3];
1536 uint32_t wm_lp_spr
[3];
1537 uint32_t wm_linetime
[3];
1539 enum intel_ddb_partitioning partitioning
;
1542 struct vlv_pipe_wm
{
1553 struct vlv_wm_values
{
1554 struct vlv_pipe_wm pipe
[3];
1555 struct vlv_sr_wm sr
;
1565 struct skl_ddb_entry
{
1566 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1569 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1571 return entry
->end
- entry
->start
;
1574 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1575 const struct skl_ddb_entry
*e2
)
1577 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1583 struct skl_ddb_allocation
{
1584 struct skl_ddb_entry pipe
[I915_MAX_PIPES
];
1585 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1586 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1589 struct skl_wm_values
{
1590 unsigned dirty_pipes
;
1591 struct skl_ddb_allocation ddb
;
1592 uint32_t wm_linetime
[I915_MAX_PIPES
];
1593 uint32_t plane
[I915_MAX_PIPES
][I915_MAX_PLANES
][8];
1594 uint32_t plane_trans
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1597 struct skl_wm_level
{
1598 bool plane_en
[I915_MAX_PLANES
];
1599 uint16_t plane_res_b
[I915_MAX_PLANES
];
1600 uint8_t plane_res_l
[I915_MAX_PLANES
];
1604 * This struct helps tracking the state needed for runtime PM, which puts the
1605 * device in PCI D3 state. Notice that when this happens, nothing on the
1606 * graphics device works, even register access, so we don't get interrupts nor
1609 * Every piece of our code that needs to actually touch the hardware needs to
1610 * either call intel_runtime_pm_get or call intel_display_power_get with the
1611 * appropriate power domain.
1613 * Our driver uses the autosuspend delay feature, which means we'll only really
1614 * suspend if we stay with zero refcount for a certain amount of time. The
1615 * default value is currently very conservative (see intel_runtime_pm_enable), but
1616 * it can be changed with the standard runtime PM files from sysfs.
1618 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1619 * goes back to false exactly before we reenable the IRQs. We use this variable
1620 * to check if someone is trying to enable/disable IRQs while they're supposed
1621 * to be disabled. This shouldn't happen and we'll print some error messages in
1624 * For more, read the Documentation/power/runtime_pm.txt.
1626 struct i915_runtime_pm
{
1627 atomic_t wakeref_count
;
1628 atomic_t atomic_seq
;
1633 enum intel_pipe_crc_source
{
1634 INTEL_PIPE_CRC_SOURCE_NONE
,
1635 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1636 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1637 INTEL_PIPE_CRC_SOURCE_PF
,
1638 INTEL_PIPE_CRC_SOURCE_PIPE
,
1639 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1640 INTEL_PIPE_CRC_SOURCE_TV
,
1641 INTEL_PIPE_CRC_SOURCE_DP_B
,
1642 INTEL_PIPE_CRC_SOURCE_DP_C
,
1643 INTEL_PIPE_CRC_SOURCE_DP_D
,
1644 INTEL_PIPE_CRC_SOURCE_AUTO
,
1645 INTEL_PIPE_CRC_SOURCE_MAX
,
1648 struct intel_pipe_crc_entry
{
1653 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1654 struct intel_pipe_crc
{
1656 bool opened
; /* exclusive access to the result file */
1657 struct intel_pipe_crc_entry
*entries
;
1658 enum intel_pipe_crc_source source
;
1660 wait_queue_head_t wq
;
1663 struct i915_frontbuffer_tracking
{
1667 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1674 struct i915_wa_reg
{
1677 /* bitmask representing WA bits */
1682 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1683 * allowing it for RCS as we don't foresee any requirement of having
1684 * a whitelist for other engines. When it is really required for
1685 * other engines then the limit need to be increased.
1687 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1689 struct i915_workarounds
{
1690 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1692 u32 hw_whitelist_count
[I915_NUM_ENGINES
];
1695 struct i915_virtual_gpu
{
1699 struct i915_execbuffer_params
{
1700 struct drm_device
*dev
;
1701 struct drm_file
*file
;
1702 uint32_t dispatch_flags
;
1703 uint32_t args_batch_start_offset
;
1704 uint64_t batch_obj_vm_offset
;
1705 struct intel_engine_cs
*engine
;
1706 struct drm_i915_gem_object
*batch_obj
;
1707 struct i915_gem_context
*ctx
;
1708 struct drm_i915_gem_request
*request
;
1711 /* used in computing the new watermarks state */
1712 struct intel_wm_config
{
1713 unsigned int num_pipes_active
;
1714 bool sprites_enabled
;
1715 bool sprites_scaled
;
1718 struct drm_i915_private
{
1719 struct drm_device drm
;
1721 struct drm_device
*dev
;
1722 struct kmem_cache
*objects
;
1723 struct kmem_cache
*vmas
;
1724 struct kmem_cache
*requests
;
1726 const struct intel_device_info info
;
1728 int relative_constants_mode
;
1732 struct intel_uncore uncore
;
1734 struct i915_virtual_gpu vgpu
;
1736 struct intel_gvt gvt
;
1738 struct intel_guc guc
;
1740 struct intel_csr csr
;
1742 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
1744 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1745 * controller on different i2c buses. */
1746 struct mutex gmbus_mutex
;
1749 * Base address of the gmbus and gpio block.
1751 uint32_t gpio_mmio_base
;
1753 /* MMIO base address for MIPI regs */
1754 uint32_t mipi_mmio_base
;
1756 uint32_t psr_mmio_base
;
1758 wait_queue_head_t gmbus_wait_queue
;
1760 struct pci_dev
*bridge_dev
;
1761 struct i915_gem_context
*kernel_context
;
1762 struct intel_engine_cs engine
[I915_NUM_ENGINES
];
1763 struct drm_i915_gem_object
*semaphore_obj
;
1764 uint32_t last_seqno
, next_seqno
;
1766 struct drm_dma_handle
*status_page_dmah
;
1767 struct resource mch_res
;
1769 /* protects the irq masks */
1770 spinlock_t irq_lock
;
1772 /* protects the mmio flip data */
1773 spinlock_t mmio_flip_lock
;
1775 bool display_irqs_enabled
;
1777 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1778 struct pm_qos_request pm_qos
;
1780 /* Sideband mailbox protection */
1781 struct mutex sb_lock
;
1783 /** Cached value of IMR to avoid reads in updating the bitfield */
1786 u32 de_irq_mask
[I915_MAX_PIPES
];
1791 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1793 struct i915_hotplug hotplug
;
1794 struct intel_fbc fbc
;
1795 struct i915_drrs drrs
;
1796 struct intel_opregion opregion
;
1797 struct intel_vbt_data vbt
;
1799 bool preserve_bios_swizzle
;
1802 struct intel_overlay
*overlay
;
1804 /* backlight registers and fields in struct intel_panel */
1805 struct mutex backlight_lock
;
1808 bool no_aux_handshake
;
1810 /* protects panel power sequencer state */
1811 struct mutex pps_mutex
;
1813 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1814 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1816 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1817 unsigned int skl_preferred_vco_freq
;
1818 unsigned int cdclk_freq
, max_cdclk_freq
, atomic_cdclk_freq
;
1819 unsigned int max_dotclk_freq
;
1820 unsigned int rawclk_freq
;
1821 unsigned int hpll_freq
;
1822 unsigned int czclk_freq
;
1825 unsigned int vco
, ref
;
1829 * wq - Driver workqueue for GEM.
1831 * NOTE: Work items scheduled here are not allowed to grab any modeset
1832 * locks, for otherwise the flushing done in the pageflip code will
1833 * result in deadlocks.
1835 struct workqueue_struct
*wq
;
1837 /* Display functions */
1838 struct drm_i915_display_funcs display
;
1840 /* PCH chipset type */
1841 enum intel_pch pch_type
;
1842 unsigned short pch_id
;
1844 unsigned long quirks
;
1846 enum modeset_restore modeset_restore
;
1847 struct mutex modeset_restore_lock
;
1848 struct drm_atomic_state
*modeset_restore_state
;
1850 struct list_head vm_list
; /* Global list of all address spaces */
1851 struct i915_ggtt ggtt
; /* VM representing the global address space */
1853 struct i915_gem_mm mm
;
1854 DECLARE_HASHTABLE(mm_structs
, 7);
1855 struct mutex mm_lock
;
1857 /* The hw wants to have a stable context identifier for the lifetime
1858 * of the context (for OA, PASID, faults, etc). This is limited
1859 * in execlists to 21 bits.
1861 struct ida context_hw_ida
;
1862 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1864 /* Kernel Modesetting */
1866 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1867 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1868 wait_queue_head_t pending_flip_queue
;
1870 #ifdef CONFIG_DEBUG_FS
1871 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1874 /* dpll and cdclk state is protected by connection_mutex */
1875 int num_shared_dpll
;
1876 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1877 const struct intel_dpll_mgr
*dpll_mgr
;
1880 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1881 * Must be global rather than per dpll, because on some platforms
1882 * plls share registers.
1884 struct mutex dpll_lock
;
1886 unsigned int active_crtcs
;
1887 unsigned int min_pixclk
[I915_MAX_PIPES
];
1889 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1891 struct i915_workarounds workarounds
;
1893 struct i915_frontbuffer_tracking fb_tracking
;
1897 bool mchbar_need_disable
;
1899 struct intel_l3_parity l3_parity
;
1901 /* Cannot be determined by PCIID. You must always read a register. */
1904 /* gen6+ rps state */
1905 struct intel_gen6_power_mgmt rps
;
1907 /* ilk-only ips/rps state. Everything in here is protected by the global
1908 * mchdev_lock in intel_pm.c */
1909 struct intel_ilk_power_mgmt ips
;
1911 struct i915_power_domains power_domains
;
1913 struct i915_psr psr
;
1915 struct i915_gpu_error gpu_error
;
1917 struct drm_i915_gem_object
*vlv_pctx
;
1919 #ifdef CONFIG_DRM_FBDEV_EMULATION
1920 /* list of fbdev register on this device */
1921 struct intel_fbdev
*fbdev
;
1922 struct work_struct fbdev_suspend_work
;
1925 struct drm_property
*broadcast_rgb_property
;
1926 struct drm_property
*force_audio_property
;
1928 /* hda/i915 audio component */
1929 struct i915_audio_component
*audio_component
;
1930 bool audio_component_registered
;
1932 * av_mutex - mutex for audio/video sync
1935 struct mutex av_mutex
;
1937 uint32_t hw_context_size
;
1938 struct list_head context_list
;
1942 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1943 u32 chv_phy_control
;
1945 * Shadows for CHV DPLL_MD regs to keep the state
1946 * checker somewhat working in the presence hardware
1947 * crappiness (can't read out DPLL_MD for pipes B & C).
1949 u32 chv_dpll_md
[I915_MAX_PIPES
];
1953 bool suspended_to_idle
;
1954 struct i915_suspend_saved_registers regfile
;
1955 struct vlv_s0ix_state vlv_s0ix_state
;
1959 * Raw watermark latency values:
1960 * in 0.1us units for WM0,
1961 * in 0.5us units for WM1+.
1964 uint16_t pri_latency
[5];
1966 uint16_t spr_latency
[5];
1968 uint16_t cur_latency
[5];
1970 * Raw watermark memory latency values
1971 * for SKL for all 8 levels
1974 uint16_t skl_latency
[8];
1977 * The skl_wm_values structure is a bit too big for stack
1978 * allocation, so we keep the staging struct where we store
1979 * intermediate results here instead.
1981 struct skl_wm_values skl_results
;
1983 /* current hardware state */
1985 struct ilk_wm_values hw
;
1986 struct skl_wm_values skl_hw
;
1987 struct vlv_wm_values vlv
;
1993 * Should be held around atomic WM register writing; also
1994 * protects * intel_crtc->wm.active and
1995 * cstate->wm.need_postvbl_update.
1997 struct mutex wm_mutex
;
2000 * Set during HW readout of watermarks/DDB. Some platforms
2001 * need to know when we're still using BIOS-provided values
2002 * (which we don't fully trust).
2004 bool distrust_bios_wm
;
2007 struct i915_runtime_pm pm
;
2009 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2011 int (*execbuf_submit
)(struct i915_execbuffer_params
*params
,
2012 struct drm_i915_gem_execbuffer2
*args
,
2013 struct list_head
*vmas
);
2014 int (*init_engines
)(struct drm_device
*dev
);
2015 void (*cleanup_engine
)(struct intel_engine_cs
*engine
);
2016 void (*stop_engine
)(struct intel_engine_cs
*engine
);
2019 * Is the GPU currently considered idle, or busy executing
2020 * userspace requests? Whilst idle, we allow runtime power
2021 * management to power down the hardware and display clocks.
2022 * In order to reduce the effect on performance, there
2023 * is a slight delay before we do so.
2025 unsigned int active_engines
;
2029 * We leave the user IRQ off as much as possible,
2030 * but this means that requests will finish and never
2031 * be retired once the system goes idle. Set a timer to
2032 * fire periodically while the ring is running. When it
2033 * fires, go retire requests.
2035 struct delayed_work retire_work
;
2038 * When we detect an idle GPU, we want to turn on
2039 * powersaving features. So once we see that there
2040 * are no more requests outstanding and no more
2041 * arrive within a small period of time, we fire
2042 * off the idle_work.
2044 struct delayed_work idle_work
;
2047 /* perform PHY state sanity checks? */
2048 bool chv_phy_assert
[2];
2050 struct intel_encoder
*dig_port_map
[I915_MAX_PORTS
];
2053 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2054 * will be rejected. Instead look for a better place.
2058 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
2060 return container_of(dev
, struct drm_i915_private
, drm
);
2063 static inline struct drm_i915_private
*dev_to_i915(struct device
*dev
)
2065 return to_i915(dev_get_drvdata(dev
));
2068 static inline struct drm_i915_private
*guc_to_i915(struct intel_guc
*guc
)
2070 return container_of(guc
, struct drm_i915_private
, guc
);
2073 /* Simple iterator over all initialised engines */
2074 #define for_each_engine(engine__, dev_priv__) \
2075 for ((engine__) = &(dev_priv__)->engine[0]; \
2076 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2078 for_each_if (intel_engine_initialized(engine__))
2080 /* Iterator with engine_id */
2081 #define for_each_engine_id(engine__, dev_priv__, id__) \
2082 for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
2083 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2085 for_each_if (((id__) = (engine__)->id, \
2086 intel_engine_initialized(engine__)))
2088 /* Iterator over subset of engines selected by mask */
2089 #define for_each_engine_masked(engine__, dev_priv__, mask__) \
2090 for ((engine__) = &(dev_priv__)->engine[0]; \
2091 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2093 for_each_if (((mask__) & intel_engine_flag(engine__)) && \
2094 intel_engine_initialized(engine__))
2096 enum hdmi_force_audio
{
2097 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
2098 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
2099 HDMI_AUDIO_AUTO
, /* trust EDID */
2100 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
2103 #define I915_GTT_OFFSET_NONE ((u32)-1)
2105 struct drm_i915_gem_object_ops
{
2107 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2109 /* Interface between the GEM object and its backing storage.
2110 * get_pages() is called once prior to the use of the associated set
2111 * of pages before to binding them into the GTT, and put_pages() is
2112 * called after we no longer need them. As we expect there to be
2113 * associated cost with migrating pages between the backing storage
2114 * and making them available for the GPU (e.g. clflush), we may hold
2115 * onto the pages after they are no longer referenced by the GPU
2116 * in case they may be used again shortly (for example migrating the
2117 * pages to a different memory domain within the GTT). put_pages()
2118 * will therefore most likely be called when the object itself is
2119 * being released or under memory pressure (where we attempt to
2120 * reap pages for the shrinker).
2122 int (*get_pages
)(struct drm_i915_gem_object
*);
2123 void (*put_pages
)(struct drm_i915_gem_object
*);
2125 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
2126 void (*release
)(struct drm_i915_gem_object
*);
2130 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2131 * considered to be the frontbuffer for the given plane interface-wise. This
2132 * doesn't mean that the hw necessarily already scans it out, but that any
2133 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2135 * We have one bit per pipe and per scanout plane type.
2137 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2138 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2139 #define INTEL_FRONTBUFFER_BITS \
2140 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2141 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2142 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2143 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2144 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2145 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2146 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2147 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2148 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2149 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2150 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2152 struct drm_i915_gem_object
{
2153 struct drm_gem_object base
;
2155 const struct drm_i915_gem_object_ops
*ops
;
2157 /** List of VMAs backed by this object */
2158 struct list_head vma_list
;
2160 /** Stolen memory for this object, instead of being backed by shmem. */
2161 struct drm_mm_node
*stolen
;
2162 struct list_head global_list
;
2164 struct list_head engine_list
[I915_NUM_ENGINES
];
2165 /** Used in execbuf to temporarily hold a ref */
2166 struct list_head obj_exec_link
;
2168 struct list_head batch_pool_link
;
2171 * This is set if the object is on the active lists (has pending
2172 * rendering and so a non-zero seqno), and is not set if it i s on
2173 * inactive (ready to be unbound) list.
2175 unsigned int active
:I915_NUM_ENGINES
;
2178 * This is set if the object has been written to since last bound
2181 unsigned int dirty
:1;
2184 * Fence register bits (if any) for this object. Will be set
2185 * as needed when mapped into the GTT.
2186 * Protected by dev->struct_mutex.
2188 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
2191 * Advice: are the backing pages purgeable?
2193 unsigned int madv
:2;
2196 * Current tiling mode for the object.
2198 unsigned int tiling_mode
:2;
2200 * Whether the tiling parameters for the currently associated fence
2201 * register have changed. Note that for the purposes of tracking
2202 * tiling changes we also treat the unfenced register, the register
2203 * slot that the object occupies whilst it executes a fenced
2204 * command (such as BLT on gen2/3), as a "fence".
2206 unsigned int fence_dirty
:1;
2209 * Is the object at the current location in the gtt mappable and
2210 * fenceable? Used to avoid costly recalculations.
2212 unsigned int map_and_fenceable
:1;
2215 * Whether the current gtt mapping needs to be mappable (and isn't just
2216 * mappable by accident). Track pin and fault separate for a more
2217 * accurate mappable working set.
2219 unsigned int fault_mappable
:1;
2222 * Is the object to be mapped as read-only to the GPU
2223 * Only honoured if hardware has relevant pte bit
2225 unsigned long gt_ro
:1;
2226 unsigned int cache_level
:3;
2227 unsigned int cache_dirty
:1;
2229 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
2231 unsigned int has_wc_mmap
;
2232 unsigned int pin_display
;
2234 struct sg_table
*pages
;
2235 int pages_pin_count
;
2237 struct scatterlist
*sg
;
2242 /** Breadcrumb of last rendering to the buffer.
2243 * There can only be one writer, but we allow for multiple readers.
2244 * If there is a writer that necessarily implies that all other
2245 * read requests are complete - but we may only be lazily clearing
2246 * the read requests. A read request is naturally the most recent
2247 * request on a ring, so we may have two different write and read
2248 * requests on one ring where the write request is older than the
2249 * read request. This allows for the CPU to read from an active
2250 * buffer by only waiting for the write to complete.
2252 struct drm_i915_gem_request
*last_read_req
[I915_NUM_ENGINES
];
2253 struct drm_i915_gem_request
*last_write_req
;
2254 /** Breadcrumb of last fenced GPU access to the buffer. */
2255 struct drm_i915_gem_request
*last_fenced_req
;
2257 /** Current tiling stride for the object, if it's tiled. */
2260 /** References from framebuffers, locks out tiling changes. */
2261 unsigned long framebuffer_references
;
2263 /** Record of address bit 17 of each page at last unbind. */
2264 unsigned long *bit_17
;
2267 /** for phy allocated objects */
2268 struct drm_dma_handle
*phys_handle
;
2270 struct i915_gem_userptr
{
2272 unsigned read_only
:1;
2273 unsigned workers
:4;
2274 #define I915_GEM_USERPTR_MAX_WORKERS 15
2276 struct i915_mm_struct
*mm
;
2277 struct i915_mmu_object
*mmu_object
;
2278 struct work_struct
*work
;
2282 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2285 i915_gem_object_has_struct_page(const struct drm_i915_gem_object
*obj
)
2287 return obj
->ops
->flags
& I915_GEM_OBJECT_HAS_STRUCT_PAGE
;
2291 * Optimised SGL iterator for GEM objects
2293 static __always_inline
struct sgt_iter
{
2294 struct scatterlist
*sgp
;
2301 } __sgt_iter(struct scatterlist
*sgl
, bool dma
) {
2302 struct sgt_iter s
= { .sgp
= sgl
};
2305 s
.max
= s
.curr
= s
.sgp
->offset
;
2306 s
.max
+= s
.sgp
->length
;
2308 s
.dma
= sg_dma_address(s
.sgp
);
2310 s
.pfn
= page_to_pfn(sg_page(s
.sgp
));
2317 * __sg_next - return the next scatterlist entry in a list
2318 * @sg: The current sg entry
2321 * If the entry is the last, return NULL; otherwise, step to the next
2322 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2323 * otherwise just return the pointer to the current element.
2325 static inline struct scatterlist
*__sg_next(struct scatterlist
*sg
)
2327 #ifdef CONFIG_DEBUG_SG
2328 BUG_ON(sg
->sg_magic
!= SG_MAGIC
);
2330 return sg_is_last(sg
) ? NULL
:
2331 likely(!sg_is_chain(++sg
)) ? sg
:
2336 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2337 * @__dmap: DMA address (output)
2338 * @__iter: 'struct sgt_iter' (iterator state, internal)
2339 * @__sgt: sg_table to iterate over (input)
2341 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2342 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2343 ((__dmap) = (__iter).dma + (__iter).curr); \
2344 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2345 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2348 * for_each_sgt_page - iterate over the pages of the given sg_table
2349 * @__pp: page pointer (output)
2350 * @__iter: 'struct sgt_iter' (iterator state, internal)
2351 * @__sgt: sg_table to iterate over (input)
2353 #define for_each_sgt_page(__pp, __iter, __sgt) \
2354 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2355 ((__pp) = (__iter).pfn == 0 ? NULL : \
2356 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2357 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2358 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2361 * Request queue structure.
2363 * The request queue allows us to note sequence numbers that have been emitted
2364 * and may be associated with active buffers to be retired.
2366 * By keeping this list, we can avoid having to do questionable sequence
2367 * number comparisons on buffer last_read|write_seqno. It also allows an
2368 * emission time to be associated with the request for tracking how far ahead
2369 * of the GPU the submission is.
2371 * The requests are reference counted, so upon creation they should have an
2372 * initial reference taken using kref_init
2374 struct drm_i915_gem_request
{
2377 /** On Which ring this request was generated */
2378 struct drm_i915_private
*i915
;
2379 struct intel_engine_cs
*engine
;
2380 struct intel_signal_node signaling
;
2382 /** GEM sequence number associated with the previous request,
2383 * when the HWS breadcrumb is equal to this the GPU is processing
2388 /** GEM sequence number associated with this request,
2389 * when the HWS breadcrumb is equal or greater than this the GPU
2390 * has finished processing this request.
2394 /** Position in the ringbuffer of the start of the request */
2398 * Position in the ringbuffer of the start of the postfix.
2399 * This is required to calculate the maximum available ringbuffer
2400 * space without overwriting the postfix.
2404 /** Position in the ringbuffer of the end of the whole request */
2407 /** Preallocate space in the ringbuffer for the emitting the request */
2411 * Context and ring buffer related to this request
2412 * Contexts are refcounted, so when this request is associated with a
2413 * context, we must increment the context's refcount, to guarantee that
2414 * it persists while any request is linked to it. Requests themselves
2415 * are also refcounted, so the request will only be freed when the last
2416 * reference to it is dismissed, and the code in
2417 * i915_gem_request_free() will then decrement the refcount on the
2420 struct i915_gem_context
*ctx
;
2421 struct intel_ringbuffer
*ringbuf
;
2424 * Context related to the previous request.
2425 * As the contexts are accessed by the hardware until the switch is
2426 * completed to a new context, the hardware may still be writing
2427 * to the context object after the breadcrumb is visible. We must
2428 * not unpin/unbind/prune that object whilst still active and so
2429 * we keep the previous context pinned until the following (this)
2430 * request is retired.
2432 struct i915_gem_context
*previous_context
;
2434 /** Batch buffer related to this request if any (used for
2435 error state dump only) */
2436 struct drm_i915_gem_object
*batch_obj
;
2438 /** Time at which this request was emitted, in jiffies. */
2439 unsigned long emitted_jiffies
;
2441 /** global list entry for this request */
2442 struct list_head list
;
2444 struct drm_i915_file_private
*file_priv
;
2445 /** file_priv list entry for this request */
2446 struct list_head client_list
;
2448 /** process identifier submitting this request */
2452 * The ELSP only accepts two elements at a time, so we queue
2453 * context/tail pairs on a given queue (ring->execlist_queue) until the
2454 * hardware is available. The queue serves a double purpose: we also use
2455 * it to keep track of the up to 2 contexts currently in the hardware
2456 * (usually one in execution and the other queued up by the GPU): We
2457 * only remove elements from the head of the queue when the hardware
2458 * informs us that an element has been completed.
2460 * All accesses to the queue are mediated by a spinlock
2461 * (ring->execlist_lock).
2464 /** Execlist link in the submission queue.*/
2465 struct list_head execlist_link
;
2467 /** Execlists no. of times this request has been sent to the ELSP */
2470 /** Execlists context hardware id. */
2474 struct drm_i915_gem_request
* __must_check
2475 i915_gem_request_alloc(struct intel_engine_cs
*engine
,
2476 struct i915_gem_context
*ctx
);
2477 void i915_gem_request_free(struct kref
*req_ref
);
2478 int i915_gem_request_add_to_client(struct drm_i915_gem_request
*req
,
2479 struct drm_file
*file
);
2481 static inline uint32_t
2482 i915_gem_request_get_seqno(struct drm_i915_gem_request
*req
)
2484 return req
? req
->seqno
: 0;
2487 static inline struct intel_engine_cs
*
2488 i915_gem_request_get_engine(struct drm_i915_gem_request
*req
)
2490 return req
? req
->engine
: NULL
;
2493 static inline struct drm_i915_gem_request
*
2494 i915_gem_request_reference(struct drm_i915_gem_request
*req
)
2497 kref_get(&req
->ref
);
2502 i915_gem_request_unreference(struct drm_i915_gem_request
*req
)
2504 kref_put(&req
->ref
, i915_gem_request_free
);
2507 static inline void i915_gem_request_assign(struct drm_i915_gem_request
**pdst
,
2508 struct drm_i915_gem_request
*src
)
2511 i915_gem_request_reference(src
);
2514 i915_gem_request_unreference(*pdst
);
2520 * XXX: i915_gem_request_completed should be here but currently needs the
2521 * definition of i915_seqno_passed() which is below. It will be moved in
2522 * a later patch when the call to i915_seqno_passed() is obsoleted...
2526 * A command that requires special handling by the command parser.
2528 struct drm_i915_cmd_descriptor
{
2530 * Flags describing how the command parser processes the command.
2532 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2533 * a length mask if not set
2534 * CMD_DESC_SKIP: The command is allowed but does not follow the
2535 * standard length encoding for the opcode range in
2537 * CMD_DESC_REJECT: The command is never allowed
2538 * CMD_DESC_REGISTER: The command should be checked against the
2539 * register whitelist for the appropriate ring
2540 * CMD_DESC_MASTER: The command is allowed if the submitting process
2544 #define CMD_DESC_FIXED (1<<0)
2545 #define CMD_DESC_SKIP (1<<1)
2546 #define CMD_DESC_REJECT (1<<2)
2547 #define CMD_DESC_REGISTER (1<<3)
2548 #define CMD_DESC_BITMASK (1<<4)
2549 #define CMD_DESC_MASTER (1<<5)
2552 * The command's unique identification bits and the bitmask to get them.
2553 * This isn't strictly the opcode field as defined in the spec and may
2554 * also include type, subtype, and/or subop fields.
2562 * The command's length. The command is either fixed length (i.e. does
2563 * not include a length field) or has a length field mask. The flag
2564 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2565 * a length mask. All command entries in a command table must include
2566 * length information.
2574 * Describes where to find a register address in the command to check
2575 * against the ring's register whitelist. Only valid if flags has the
2576 * CMD_DESC_REGISTER bit set.
2578 * A non-zero step value implies that the command may access multiple
2579 * registers in sequence (e.g. LRI), in that case step gives the
2580 * distance in dwords between individual offset fields.
2588 #define MAX_CMD_DESC_BITMASKS 3
2590 * Describes command checks where a particular dword is masked and
2591 * compared against an expected value. If the command does not match
2592 * the expected value, the parser rejects it. Only valid if flags has
2593 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2596 * If the check specifies a non-zero condition_mask then the parser
2597 * only performs the check when the bits specified by condition_mask
2604 u32 condition_offset
;
2606 } bits
[MAX_CMD_DESC_BITMASKS
];
2610 * A table of commands requiring special handling by the command parser.
2612 * Each ring has an array of tables. Each table consists of an array of command
2613 * descriptors, which must be sorted with command opcodes in ascending order.
2615 struct drm_i915_cmd_table
{
2616 const struct drm_i915_cmd_descriptor
*table
;
2620 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2621 #define __I915__(p) ({ \
2622 struct drm_i915_private *__p; \
2623 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2624 __p = (struct drm_i915_private *)p; \
2625 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2626 __p = to_i915((struct drm_device *)p); \
2631 #define INTEL_INFO(p) (&__I915__(p)->info)
2632 #define INTEL_GEN(p) (INTEL_INFO(p)->gen)
2633 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2635 #define REVID_FOREVER 0xff
2636 #define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision)
2638 #define GEN_FOREVER (0)
2640 * Returns true if Gen is in inclusive range [Start, End].
2642 * Use GEN_FOREVER for unbound start and or end.
2644 #define IS_GEN(p, s, e) ({ \
2645 unsigned int __s = (s), __e = (e); \
2646 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2647 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2648 if ((__s) != GEN_FOREVER) \
2650 if ((__e) == GEN_FOREVER) \
2651 __e = BITS_PER_LONG - 1; \
2654 !!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \
2658 * Return true if revision is in range [since,until] inclusive.
2660 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2662 #define IS_REVID(p, since, until) \
2663 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2665 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2666 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2667 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2668 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2669 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2670 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2671 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2672 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2673 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2674 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2675 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2676 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2677 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2678 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2679 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2680 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2681 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2682 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2683 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2684 INTEL_DEVID(dev) == 0x0152 || \
2685 INTEL_DEVID(dev) == 0x015a)
2686 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2687 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2688 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2689 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->is_broadwell)
2690 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2691 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2692 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2693 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2694 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2695 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2696 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2697 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2698 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2699 (INTEL_DEVID(dev) & 0xf) == 0xe))
2700 /* ULX machines are also considered ULT. */
2701 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2702 (INTEL_DEVID(dev) & 0xf) == 0xe)
2703 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2704 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2705 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2706 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2707 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2708 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2709 /* ULX machines are also considered ULT. */
2710 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2711 INTEL_DEVID(dev) == 0x0A1E)
2712 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2713 INTEL_DEVID(dev) == 0x1913 || \
2714 INTEL_DEVID(dev) == 0x1916 || \
2715 INTEL_DEVID(dev) == 0x1921 || \
2716 INTEL_DEVID(dev) == 0x1926)
2717 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2718 INTEL_DEVID(dev) == 0x1915 || \
2719 INTEL_DEVID(dev) == 0x191E)
2720 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2721 INTEL_DEVID(dev) == 0x5913 || \
2722 INTEL_DEVID(dev) == 0x5916 || \
2723 INTEL_DEVID(dev) == 0x5921 || \
2724 INTEL_DEVID(dev) == 0x5926)
2725 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2726 INTEL_DEVID(dev) == 0x5915 || \
2727 INTEL_DEVID(dev) == 0x591E)
2728 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2729 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2730 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2731 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2733 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2735 #define SKL_REVID_A0 0x0
2736 #define SKL_REVID_B0 0x1
2737 #define SKL_REVID_C0 0x2
2738 #define SKL_REVID_D0 0x3
2739 #define SKL_REVID_E0 0x4
2740 #define SKL_REVID_F0 0x5
2742 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2744 #define BXT_REVID_A0 0x0
2745 #define BXT_REVID_A1 0x1
2746 #define BXT_REVID_B0 0x3
2747 #define BXT_REVID_C0 0x9
2749 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2751 #define KBL_REVID_A0 0x0
2752 #define KBL_REVID_B0 0x1
2753 #define KBL_REVID_C0 0x2
2754 #define KBL_REVID_D0 0x3
2755 #define KBL_REVID_E0 0x4
2757 #define IS_KBL_REVID(p, since, until) \
2758 (IS_KABYLAKE(p) && IS_REVID(p, since, until))
2761 * The genX designation typically refers to the render engine, so render
2762 * capability related checks should use IS_GEN, while display and other checks
2763 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2766 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen_mask & BIT(1))
2767 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen_mask & BIT(2))
2768 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen_mask & BIT(3))
2769 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen_mask & BIT(4))
2770 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen_mask & BIT(5))
2771 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen_mask & BIT(6))
2772 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen_mask & BIT(7))
2773 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen_mask & BIT(8))
2775 #define ENGINE_MASK(id) BIT(id)
2776 #define RENDER_RING ENGINE_MASK(RCS)
2777 #define BSD_RING ENGINE_MASK(VCS)
2778 #define BLT_RING ENGINE_MASK(BCS)
2779 #define VEBOX_RING ENGINE_MASK(VECS)
2780 #define BSD2_RING ENGINE_MASK(VCS2)
2781 #define ALL_ENGINES (~0)
2783 #define HAS_ENGINE(dev_priv, id) \
2784 (INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id))
2786 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2787 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2788 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2789 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2791 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2792 #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
2793 #define HAS_EDRAM(dev) (__I915__(dev)->edram_cap & EDRAM_ENABLED)
2794 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2796 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2798 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2799 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2800 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2801 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2802 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2804 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2805 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2807 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2808 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2810 /* WaRsDisableCoarsePowerGating:skl,bxt */
2811 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2812 (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
2813 IS_SKL_GT3(dev_priv) || \
2814 IS_SKL_GT4(dev_priv))
2817 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2818 * even when in MSI mode. This results in spurious interrupt warnings if the
2819 * legacy irq no. is shared with another device. The kernel then disables that
2820 * interrupt source and so prevents the other device from working properly.
2822 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2823 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2825 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2826 * rows, which changed the alignment requirements and fence programming.
2828 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2830 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2831 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2833 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2834 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2835 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2837 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2839 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2840 INTEL_INFO(dev)->gen >= 9)
2842 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2843 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2844 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2845 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2846 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2847 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2848 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2849 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2850 IS_KABYLAKE(dev) || IS_BROXTON(dev))
2851 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2852 #define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
2854 #define HAS_CSR(dev) (IS_GEN9(dev))
2857 * For now, anything with a GuC requires uCode loading, and then supports
2858 * command submission once loaded. But these are logically independent
2859 * properties, so we have separate macros to test them.
2861 #define HAS_GUC(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2862 #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
2863 #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
2865 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2866 INTEL_INFO(dev)->gen >= 8)
2868 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2869 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2872 #define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu)
2874 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2875 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2876 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2877 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2878 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2879 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2880 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2881 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2882 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2883 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2884 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2886 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2887 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2888 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2889 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2890 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2891 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2892 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2893 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2894 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2896 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2897 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2899 /* DPF == dynamic parity feature */
2900 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2901 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2903 #define GT_FREQUENCY_MULTIPLIER 50
2904 #define GEN9_FREQ_SCALER 3
2906 #include "i915_trace.h"
2908 extern int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
);
2909 extern int i915_resume_switcheroo(struct drm_device
*dev
);
2911 int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv
,
2916 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
2917 const char *fmt
, ...);
2919 #define i915_report_error(dev_priv, fmt, ...) \
2920 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2922 #ifdef CONFIG_COMPAT
2923 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2926 extern int intel_gpu_reset(struct drm_i915_private
*dev_priv
, u32 engine_mask
);
2927 extern bool intel_has_gpu_reset(struct drm_i915_private
*dev_priv
);
2928 extern int i915_reset(struct drm_i915_private
*dev_priv
);
2929 extern int intel_guc_reset(struct drm_i915_private
*dev_priv
);
2930 extern void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
);
2931 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2932 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2933 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2934 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2935 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2937 /* intel_hotplug.c */
2938 void intel_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
2939 u32 pin_mask
, u32 long_mask
);
2940 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2941 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
2942 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2943 bool intel_hpd_pin_to_port(enum hpd_pin pin
, enum port
*port
);
2946 static inline void i915_queue_hangcheck(struct drm_i915_private
*dev_priv
)
2948 unsigned long delay
;
2950 if (unlikely(!i915
.enable_hangcheck
))
2953 /* Don't continually defer the hangcheck so that it is always run at
2954 * least once after work has been scheduled on any ring. Otherwise,
2955 * we will ignore a hung ring if a second ring is kept busy.
2958 delay
= round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES
);
2959 queue_delayed_work(system_long_wq
,
2960 &dev_priv
->gpu_error
.hangcheck_work
, delay
);
2964 void i915_handle_error(struct drm_i915_private
*dev_priv
,
2966 const char *fmt
, ...);
2968 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2969 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2970 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2972 extern void intel_uncore_sanitize(struct drm_i915_private
*dev_priv
);
2973 extern void intel_uncore_early_sanitize(struct drm_i915_private
*dev_priv
,
2974 bool restore_forcewake
);
2975 extern void intel_uncore_init(struct drm_i915_private
*dev_priv
);
2976 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private
*dev_priv
);
2977 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private
*dev_priv
);
2978 extern void intel_uncore_fini(struct drm_i915_private
*dev_priv
);
2979 extern void intel_uncore_forcewake_reset(struct drm_i915_private
*dev_priv
,
2981 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
2982 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
2983 enum forcewake_domains domains
);
2984 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
2985 enum forcewake_domains domains
);
2986 /* Like above but the caller must manage the uncore.lock itself.
2987 * Must be used with I915_READ_FW and friends.
2989 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
2990 enum forcewake_domains domains
);
2991 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
2992 enum forcewake_domains domains
);
2993 u64
intel_uncore_edram_size(struct drm_i915_private
*dev_priv
);
2995 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
2997 int intel_wait_for_register(struct drm_i915_private
*dev_priv
,
3001 const unsigned long timeout_ms
);
3002 int intel_wait_for_register_fw(struct drm_i915_private
*dev_priv
,
3006 const unsigned long timeout_ms
);
3008 static inline bool intel_gvt_active(struct drm_i915_private
*dev_priv
)
3010 return dev_priv
->gvt
.initialized
;
3013 static inline bool intel_vgpu_active(struct drm_i915_private
*dev_priv
)
3015 return dev_priv
->vgpu
.active
;
3019 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
3023 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
3026 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
3027 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
3028 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
3031 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
3032 uint32_t interrupt_mask
,
3033 uint32_t enabled_irq_mask
);
3035 ilk_enable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3037 ilk_update_display_irq(dev_priv
, bits
, bits
);
3040 ilk_disable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3042 ilk_update_display_irq(dev_priv
, bits
, 0);
3044 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
3046 uint32_t interrupt_mask
,
3047 uint32_t enabled_irq_mask
);
3048 static inline void bdw_enable_pipe_irq(struct drm_i915_private
*dev_priv
,
3049 enum pipe pipe
, uint32_t bits
)
3051 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, bits
);
3053 static inline void bdw_disable_pipe_irq(struct drm_i915_private
*dev_priv
,
3054 enum pipe pipe
, uint32_t bits
)
3056 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, 0);
3058 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
3059 uint32_t interrupt_mask
,
3060 uint32_t enabled_irq_mask
);
3062 ibx_enable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3064 ibx_display_interrupt_update(dev_priv
, bits
, bits
);
3067 ibx_disable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3069 ibx_display_interrupt_update(dev_priv
, bits
, 0);
3073 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
3074 struct drm_file
*file_priv
);
3075 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
3076 struct drm_file
*file_priv
);
3077 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
3078 struct drm_file
*file_priv
);
3079 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
3080 struct drm_file
*file_priv
);
3081 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
3082 struct drm_file
*file_priv
);
3083 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
3084 struct drm_file
*file_priv
);
3085 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
3086 struct drm_file
*file_priv
);
3087 void i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
3088 struct drm_i915_gem_request
*req
);
3089 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params
*params
,
3090 struct drm_i915_gem_execbuffer2
*args
,
3091 struct list_head
*vmas
);
3092 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3093 struct drm_file
*file_priv
);
3094 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
3095 struct drm_file
*file_priv
);
3096 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3097 struct drm_file
*file_priv
);
3098 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3099 struct drm_file
*file
);
3100 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3101 struct drm_file
*file
);
3102 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3103 struct drm_file
*file_priv
);
3104 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3105 struct drm_file
*file_priv
);
3106 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
3107 struct drm_file
*file_priv
);
3108 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
3109 struct drm_file
*file_priv
);
3110 void i915_gem_init_userptr(struct drm_i915_private
*dev_priv
);
3111 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
3112 struct drm_file
*file
);
3113 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
3114 struct drm_file
*file_priv
);
3115 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
3116 struct drm_file
*file_priv
);
3117 void i915_gem_load_init(struct drm_device
*dev
);
3118 void i915_gem_load_cleanup(struct drm_device
*dev
);
3119 void i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
);
3120 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
);
3122 void *i915_gem_object_alloc(struct drm_device
*dev
);
3123 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
3124 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3125 const struct drm_i915_gem_object_ops
*ops
);
3126 struct drm_i915_gem_object
*i915_gem_object_create(struct drm_device
*dev
,
3128 struct drm_i915_gem_object
*i915_gem_object_create_from_data(
3129 struct drm_device
*dev
, const void *data
, size_t size
);
3130 void i915_gem_free_object(struct drm_gem_object
*obj
);
3131 void i915_gem_vma_destroy(struct i915_vma
*vma
);
3133 /* Flags used by pin/bind&friends. */
3134 #define PIN_MAPPABLE (1<<0)
3135 #define PIN_NONBLOCK (1<<1)
3136 #define PIN_GLOBAL (1<<2)
3137 #define PIN_OFFSET_BIAS (1<<3)
3138 #define PIN_USER (1<<4)
3139 #define PIN_UPDATE (1<<5)
3140 #define PIN_ZONE_4G (1<<6)
3141 #define PIN_HIGH (1<<7)
3142 #define PIN_OFFSET_FIXED (1<<8)
3143 #define PIN_OFFSET_MASK (~4095)
3145 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3146 struct i915_address_space
*vm
,
3150 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
3151 const struct i915_ggtt_view
*view
,
3155 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
3157 void __i915_vma_set_map_and_fenceable(struct i915_vma
*vma
);
3158 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
3160 * BEWARE: Do not use the function below unless you can _absolutely_
3161 * _guarantee_ VMA in question is _not in use_ anywhere.
3163 int __must_check
__i915_vma_unbind_no_wait(struct i915_vma
*vma
);
3164 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
3165 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
3166 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
3168 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
3169 int *needs_clflush
);
3171 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
3173 static inline int __sg_page_count(struct scatterlist
*sg
)
3175 return sg
->length
>> PAGE_SHIFT
;
3179 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
, int n
);
3181 static inline dma_addr_t
3182 i915_gem_object_get_dma_address(struct drm_i915_gem_object
*obj
, int n
)
3184 if (n
< obj
->get_page
.last
) {
3185 obj
->get_page
.sg
= obj
->pages
->sgl
;
3186 obj
->get_page
.last
= 0;
3189 while (obj
->get_page
.last
+ __sg_page_count(obj
->get_page
.sg
) <= n
) {
3190 obj
->get_page
.last
+= __sg_page_count(obj
->get_page
.sg
++);
3191 if (unlikely(sg_is_chain(obj
->get_page
.sg
)))
3192 obj
->get_page
.sg
= sg_chain_ptr(obj
->get_page
.sg
);
3195 return sg_dma_address(obj
->get_page
.sg
) + ((n
- obj
->get_page
.last
) << PAGE_SHIFT
);
3198 static inline struct page
*
3199 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
3201 if (WARN_ON(n
>= obj
->base
.size
>> PAGE_SHIFT
))
3204 if (n
< obj
->get_page
.last
) {
3205 obj
->get_page
.sg
= obj
->pages
->sgl
;
3206 obj
->get_page
.last
= 0;
3209 while (obj
->get_page
.last
+ __sg_page_count(obj
->get_page
.sg
) <= n
) {
3210 obj
->get_page
.last
+= __sg_page_count(obj
->get_page
.sg
++);
3211 if (unlikely(sg_is_chain(obj
->get_page
.sg
)))
3212 obj
->get_page
.sg
= sg_chain_ptr(obj
->get_page
.sg
);
3215 return nth_page(sg_page(obj
->get_page
.sg
), n
- obj
->get_page
.last
);
3218 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3220 BUG_ON(obj
->pages
== NULL
);
3221 obj
->pages_pin_count
++;
3224 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3226 BUG_ON(obj
->pages_pin_count
== 0);
3227 obj
->pages_pin_count
--;
3231 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3232 * @obj - the object to map into kernel address space
3234 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3235 * pages and then returns a contiguous mapping of the backing storage into
3236 * the kernel address space.
3238 * The caller must hold the struct_mutex, and is responsible for calling
3239 * i915_gem_object_unpin_map() when the mapping is no longer required.
3241 * Returns the pointer through which to access the mapped object, or an
3242 * ERR_PTR() on error.
3244 void *__must_check
i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
);
3247 * i915_gem_object_unpin_map - releases an earlier mapping
3248 * @obj - the object to unmap
3250 * After pinning the object and mapping its pages, once you are finished
3251 * with your access, call i915_gem_object_unpin_map() to release the pin
3252 * upon the mapping. Once the pin count reaches zero, that mapping may be
3255 * The caller must hold the struct_mutex.
3257 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object
*obj
)
3259 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3260 i915_gem_object_unpin_pages(obj
);
3263 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
3264 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3265 struct intel_engine_cs
*to
,
3266 struct drm_i915_gem_request
**to_req
);
3267 void i915_vma_move_to_active(struct i915_vma
*vma
,
3268 struct drm_i915_gem_request
*req
);
3269 int i915_gem_dumb_create(struct drm_file
*file_priv
,
3270 struct drm_device
*dev
,
3271 struct drm_mode_create_dumb
*args
);
3272 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
3273 uint32_t handle
, uint64_t *offset
);
3275 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
3276 struct drm_i915_gem_object
*new,
3277 unsigned frontbuffer_bits
);
3280 * Returns true if seq1 is later than seq2.
3283 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
3285 return (int32_t)(seq1
- seq2
) >= 0;
3288 static inline bool i915_gem_request_started(const struct drm_i915_gem_request
*req
)
3290 return i915_seqno_passed(intel_engine_get_seqno(req
->engine
),
3291 req
->previous_seqno
);
3294 static inline bool i915_gem_request_completed(const struct drm_i915_gem_request
*req
)
3296 return i915_seqno_passed(intel_engine_get_seqno(req
->engine
),
3300 bool __i915_spin_request(const struct drm_i915_gem_request
*request
,
3301 int state
, unsigned long timeout_us
);
3302 static inline bool i915_spin_request(const struct drm_i915_gem_request
*request
,
3303 int state
, unsigned long timeout_us
)
3305 return (i915_gem_request_started(request
) &&
3306 __i915_spin_request(request
, state
, timeout_us
));
3309 int __must_check
i915_gem_get_seqno(struct drm_i915_private
*dev_priv
, u32
*seqno
);
3310 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
3312 struct drm_i915_gem_request
*
3313 i915_gem_find_active_request(struct intel_engine_cs
*engine
);
3315 void i915_gem_retire_requests(struct drm_i915_private
*dev_priv
);
3316 void i915_gem_retire_requests_ring(struct intel_engine_cs
*engine
);
3318 static inline u32
i915_reset_counter(struct i915_gpu_error
*error
)
3320 return atomic_read(&error
->reset_counter
);
3323 static inline bool __i915_reset_in_progress(u32 reset
)
3325 return unlikely(reset
& I915_RESET_IN_PROGRESS_FLAG
);
3328 static inline bool __i915_reset_in_progress_or_wedged(u32 reset
)
3330 return unlikely(reset
& (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
3333 static inline bool __i915_terminally_wedged(u32 reset
)
3335 return unlikely(reset
& I915_WEDGED
);
3338 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
3340 return __i915_reset_in_progress(i915_reset_counter(error
));
3343 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error
*error
)
3345 return __i915_reset_in_progress_or_wedged(i915_reset_counter(error
));
3348 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
3350 return __i915_terminally_wedged(i915_reset_counter(error
));
3353 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
3355 return ((i915_reset_counter(error
) & ~I915_WEDGED
) + 1) / 2;
3358 void i915_gem_reset(struct drm_device
*dev
);
3359 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
3360 int __must_check
i915_gem_init(struct drm_device
*dev
);
3361 int i915_gem_init_engines(struct drm_device
*dev
);
3362 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
3363 void i915_gem_init_swizzling(struct drm_device
*dev
);
3364 void i915_gem_cleanup_engines(struct drm_device
*dev
);
3365 int __must_check
i915_gem_wait_for_idle(struct drm_i915_private
*dev_priv
);
3366 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
3367 void __i915_add_request(struct drm_i915_gem_request
*req
,
3368 struct drm_i915_gem_object
*batch_obj
,
3370 #define i915_add_request(req) \
3371 __i915_add_request(req, NULL, true)
3372 #define i915_add_request_no_flush(req) \
3373 __i915_add_request(req, NULL, false)
3374 int __i915_wait_request(struct drm_i915_gem_request
*req
,
3377 struct intel_rps_client
*rps
);
3378 int __must_check
i915_wait_request(struct drm_i915_gem_request
*req
);
3379 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
3381 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
3384 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
3387 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
3389 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3391 const struct i915_ggtt_view
*view
);
3392 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
3393 const struct i915_ggtt_view
*view
);
3394 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
3396 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
3397 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3400 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
3402 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
3403 int tiling_mode
, bool fenced
);
3405 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3406 enum i915_cache_level cache_level
);
3408 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3409 struct dma_buf
*dma_buf
);
3411 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3412 struct drm_gem_object
*gem_obj
, int flags
);
3414 u64
i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
3415 const struct i915_ggtt_view
*view
);
3416 u64
i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
3417 struct i915_address_space
*vm
);
3419 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*o
)
3421 return i915_gem_obj_ggtt_offset_view(o
, &i915_ggtt_view_normal
);
3424 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
3425 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
3426 const struct i915_ggtt_view
*view
);
3427 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
3428 struct i915_address_space
*vm
);
3431 i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
3432 struct i915_address_space
*vm
);
3434 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
3435 const struct i915_ggtt_view
*view
);
3438 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3439 struct i915_address_space
*vm
);
3441 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
3442 const struct i915_ggtt_view
*view
);
3444 static inline struct i915_vma
*
3445 i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
)
3447 return i915_gem_obj_to_ggtt_view(obj
, &i915_ggtt_view_normal
);
3449 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
);
3451 /* Some GGTT VM helpers */
3452 static inline struct i915_hw_ppgtt
*
3453 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3455 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3459 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
3461 return i915_gem_obj_ggtt_bound_view(obj
, &i915_ggtt_view_normal
);
3465 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
);
3467 static inline int __must_check
3468 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
3472 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3473 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3475 return i915_gem_object_pin(obj
, &ggtt
->base
,
3476 alignment
, flags
| PIN_GLOBAL
);
3479 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
3480 const struct i915_ggtt_view
*view
);
3482 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
)
3484 i915_gem_object_ggtt_unpin_view(obj
, &i915_ggtt_view_normal
);
3487 /* i915_gem_fence.c */
3488 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
3489 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
3491 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
3492 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
3494 void i915_gem_restore_fences(struct drm_device
*dev
);
3496 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
3497 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3498 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3500 /* i915_gem_context.c */
3501 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
3502 void i915_gem_context_lost(struct drm_i915_private
*dev_priv
);
3503 void i915_gem_context_fini(struct drm_device
*dev
);
3504 void i915_gem_context_reset(struct drm_device
*dev
);
3505 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
3506 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
3507 int i915_switch_context(struct drm_i915_gem_request
*req
);
3508 void i915_gem_context_free(struct kref
*ctx_ref
);
3509 struct drm_i915_gem_object
*
3510 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
3511 struct i915_gem_context
*
3512 i915_gem_context_create_gvt(struct drm_device
*dev
);
3514 static inline struct i915_gem_context
*
3515 i915_gem_context_lookup(struct drm_i915_file_private
*file_priv
, u32 id
)
3517 struct i915_gem_context
*ctx
;
3519 lockdep_assert_held(&file_priv
->dev_priv
->drm
.struct_mutex
);
3521 ctx
= idr_find(&file_priv
->context_idr
, id
);
3523 return ERR_PTR(-ENOENT
);
3528 static inline void i915_gem_context_reference(struct i915_gem_context
*ctx
)
3530 kref_get(&ctx
->ref
);
3533 static inline void i915_gem_context_unreference(struct i915_gem_context
*ctx
)
3535 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
3536 kref_put(&ctx
->ref
, i915_gem_context_free
);
3539 static inline bool i915_gem_context_is_default(const struct i915_gem_context
*c
)
3541 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
3544 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
3545 struct drm_file
*file
);
3546 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
3547 struct drm_file
*file
);
3548 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
3549 struct drm_file
*file_priv
);
3550 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
3551 struct drm_file
*file_priv
);
3552 int i915_gem_context_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
3553 struct drm_file
*file
);
3555 /* i915_gem_evict.c */
3556 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
3557 struct i915_address_space
*vm
,
3560 unsigned cache_level
,
3561 unsigned long start
,
3564 int __must_check
i915_gem_evict_for_vma(struct i915_vma
*target
);
3565 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
3567 /* belongs in i915_gem_gtt.h */
3568 static inline void i915_gem_chipset_flush(struct drm_i915_private
*dev_priv
)
3570 if (INTEL_GEN(dev_priv
) < 6)
3571 intel_gtt_chipset_flush();
3574 /* i915_gem_stolen.c */
3575 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3576 struct drm_mm_node
*node
, u64 size
,
3577 unsigned alignment
);
3578 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private
*dev_priv
,
3579 struct drm_mm_node
*node
, u64 size
,
3580 unsigned alignment
, u64 start
,
3582 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3583 struct drm_mm_node
*node
);
3584 int i915_gem_init_stolen(struct drm_device
*dev
);
3585 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3586 struct drm_i915_gem_object
*
3587 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
3588 struct drm_i915_gem_object
*
3589 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
3594 /* i915_gem_shrinker.c */
3595 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3596 unsigned long target
,
3598 #define I915_SHRINK_PURGEABLE 0x1
3599 #define I915_SHRINK_UNBOUND 0x2
3600 #define I915_SHRINK_BOUND 0x4
3601 #define I915_SHRINK_ACTIVE 0x8
3602 #define I915_SHRINK_VMAPS 0x10
3603 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3604 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3605 void i915_gem_shrinker_cleanup(struct drm_i915_private
*dev_priv
);
3608 /* i915_gem_tiling.c */
3609 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3611 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3613 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3614 obj
->tiling_mode
!= I915_TILING_NONE
;
3617 /* i915_gem_debug.c */
3619 int i915_verify_lists(struct drm_device
*dev
);
3621 #define i915_verify_lists(dev) 0
3624 /* i915_debugfs.c */
3625 #ifdef CONFIG_DEBUG_FS
3626 int i915_debugfs_register(struct drm_i915_private
*dev_priv
);
3627 void i915_debugfs_unregister(struct drm_i915_private
*dev_priv
);
3628 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3629 void intel_display_crc_init(struct drm_device
*dev
);
3631 static inline int i915_debugfs_register(struct drm_i915_private
*) {return 0;}
3632 static inline void i915_debugfs_unregister(struct drm_i915_private
*) {}
3633 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3635 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
3638 /* i915_gpu_error.c */
3640 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3641 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3642 const struct i915_error_state_file_priv
*error
);
3643 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3644 struct drm_i915_private
*i915
,
3645 size_t count
, loff_t pos
);
3646 static inline void i915_error_state_buf_release(
3647 struct drm_i915_error_state_buf
*eb
)
3651 void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3653 const char *error_msg
);
3654 void i915_error_state_get(struct drm_device
*dev
,
3655 struct i915_error_state_file_priv
*error_priv
);
3656 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
3657 void i915_destroy_error_state(struct drm_device
*dev
);
3659 void i915_get_extra_instdone(struct drm_i915_private
*dev_priv
, uint32_t *instdone
);
3660 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3662 /* i915_cmd_parser.c */
3663 int i915_cmd_parser_get_version(struct drm_i915_private
*dev_priv
);
3664 int i915_cmd_parser_init_ring(struct intel_engine_cs
*engine
);
3665 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*engine
);
3666 bool i915_needs_cmd_parser(struct intel_engine_cs
*engine
);
3667 int i915_parse_cmds(struct intel_engine_cs
*engine
,
3668 struct drm_i915_gem_object
*batch_obj
,
3669 struct drm_i915_gem_object
*shadow_batch_obj
,
3670 u32 batch_start_offset
,
3674 /* i915_suspend.c */
3675 extern int i915_save_state(struct drm_device
*dev
);
3676 extern int i915_restore_state(struct drm_device
*dev
);
3679 void i915_setup_sysfs(struct drm_device
*dev_priv
);
3680 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
3683 extern int intel_setup_gmbus(struct drm_device
*dev
);
3684 extern void intel_teardown_gmbus(struct drm_device
*dev
);
3685 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3688 extern struct i2c_adapter
*
3689 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3690 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3691 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3692 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3694 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3696 extern void intel_i2c_reset(struct drm_device
*dev
);
3699 int intel_bios_init(struct drm_i915_private
*dev_priv
);
3700 bool intel_bios_is_valid_vbt(const void *buf
, size_t size
);
3701 bool intel_bios_is_tv_present(struct drm_i915_private
*dev_priv
);
3702 bool intel_bios_is_lvds_present(struct drm_i915_private
*dev_priv
, u8
*i2c_pin
);
3703 bool intel_bios_is_port_present(struct drm_i915_private
*dev_priv
, enum port port
);
3704 bool intel_bios_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
3705 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private
*dev_priv
, enum port port
);
3706 bool intel_bios_is_dsi_present(struct drm_i915_private
*dev_priv
, enum port
*port
);
3707 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private
*dev_priv
,
3710 /* intel_opregion.c */
3712 extern int intel_opregion_setup(struct drm_i915_private
*dev_priv
);
3713 extern void intel_opregion_register(struct drm_i915_private
*dev_priv
);
3714 extern void intel_opregion_unregister(struct drm_i915_private
*dev_priv
);
3715 extern void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
);
3716 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3718 extern int intel_opregion_notify_adapter(struct drm_i915_private
*dev_priv
,
3720 extern int intel_opregion_get_panel_type(struct drm_i915_private
*dev_priv
);
3722 static inline int intel_opregion_setup(struct drm_i915_private
*dev
) { return 0; }
3723 static inline void intel_opregion_register(struct drm_i915_private
*dev_priv
) { }
3724 static inline void intel_opregion_unregister(struct drm_i915_private
*dev_priv
) { }
3725 static inline void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
)
3729 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3734 intel_opregion_notify_adapter(struct drm_i915_private
*dev
, pci_power_t state
)
3738 static inline int intel_opregion_get_panel_type(struct drm_i915_private
*dev
)
3746 extern void intel_register_dsm_handler(void);
3747 extern void intel_unregister_dsm_handler(void);
3749 static inline void intel_register_dsm_handler(void) { return; }
3750 static inline void intel_unregister_dsm_handler(void) { return; }
3751 #endif /* CONFIG_ACPI */
3754 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3755 extern void intel_modeset_init(struct drm_device
*dev
);
3756 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3757 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3758 extern int intel_connector_register(struct drm_connector
*);
3759 extern void intel_connector_unregister(struct drm_connector
*);
3760 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
3761 extern void intel_display_resume(struct drm_device
*dev
);
3762 extern void i915_redisable_vga(struct drm_device
*dev
);
3763 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
3764 extern bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
);
3765 extern void intel_init_pch_refclk(struct drm_device
*dev
);
3766 extern void intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
);
3767 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3770 extern bool i915_semaphore_is_enabled(struct drm_i915_private
*dev_priv
);
3771 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3772 struct drm_file
*file
);
3775 extern struct intel_overlay_error_state
*
3776 intel_overlay_capture_error_state(struct drm_i915_private
*dev_priv
);
3777 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3778 struct intel_overlay_error_state
*error
);
3780 extern struct intel_display_error_state
*
3781 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
);
3782 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3783 struct drm_device
*dev
,
3784 struct intel_display_error_state
*error
);
3786 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3787 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3789 /* intel_sideband.c */
3790 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3791 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3792 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3793 u32
vlv_iosf_sb_read(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
);
3794 void vlv_iosf_sb_write(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
, u32 val
);
3795 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3796 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3797 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3798 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3799 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3800 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3801 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3802 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3803 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3804 enum intel_sbi_destination destination
);
3805 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3806 enum intel_sbi_destination destination
);
3807 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3808 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3810 /* intel_dpio_phy.c */
3811 void chv_set_phy_signal_level(struct intel_encoder
*encoder
,
3812 u32 deemph_reg_value
, u32 margin_reg_value
,
3813 bool uniq_trans_scale
);
3814 void chv_data_lane_soft_reset(struct intel_encoder
*encoder
,
3816 void chv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3817 void chv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3818 void chv_phy_release_cl2_override(struct intel_encoder
*encoder
);
3819 void chv_phy_post_pll_disable(struct intel_encoder
*encoder
);
3821 void vlv_set_phy_signal_level(struct intel_encoder
*encoder
,
3822 u32 demph_reg_value
, u32 preemph_reg_value
,
3823 u32 uniqtranscale_reg_value
, u32 tx3_demph
);
3824 void vlv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3825 void vlv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3826 void vlv_phy_reset_lanes(struct intel_encoder
*encoder
);
3828 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3829 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3831 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3832 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3834 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3835 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3836 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3837 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3839 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3840 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3841 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3842 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3844 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3845 * will be implemented using 2 32-bit writes in an arbitrary order with
3846 * an arbitrary delay between them. This can cause the hardware to
3847 * act upon the intermediate value, possibly leading to corruption and
3848 * machine death. You have been warned.
3850 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3851 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3853 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3854 u32 upper, lower, old_upper, loop = 0; \
3855 upper = I915_READ(upper_reg); \
3857 old_upper = upper; \
3858 lower = I915_READ(lower_reg); \
3859 upper = I915_READ(upper_reg); \
3860 } while (upper != old_upper && loop++ < 2); \
3861 (u64)upper << 32 | lower; })
3863 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3864 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3866 #define __raw_read(x, s) \
3867 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3870 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3873 #define __raw_write(x, s) \
3874 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3875 i915_reg_t reg, uint##x##_t val) \
3877 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3892 /* These are untraced mmio-accessors that are only valid to be used inside
3893 * criticial sections inside IRQ handlers where forcewake is explicitly
3895 * Think twice, and think again, before using these.
3896 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3897 * intel_uncore_forcewake_irqunlock().
3899 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3900 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3901 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3902 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3904 /* "Broadcast RGB" property */
3905 #define INTEL_BROADCAST_RGB_AUTO 0
3906 #define INTEL_BROADCAST_RGB_FULL 1
3907 #define INTEL_BROADCAST_RGB_LIMITED 2
3909 static inline i915_reg_t
i915_vgacntrl_reg(struct drm_device
*dev
)
3911 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
3912 return VLV_VGACNTRL
;
3913 else if (INTEL_INFO(dev
)->gen
>= 5)
3914 return CPU_VGACNTRL
;
3919 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3921 unsigned long j
= msecs_to_jiffies(m
);
3923 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3926 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
3928 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
3931 static inline unsigned long
3932 timespec_to_jiffies_timeout(const struct timespec
*value
)
3934 unsigned long j
= timespec_to_jiffies(value
);
3936 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3940 * If you need to wait X milliseconds between events A and B, but event B
3941 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3942 * when event A happened, then just before event B you call this function and
3943 * pass the timestamp as the first argument, and X as the second argument.
3946 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3948 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3951 * Don't re-read the value of "jiffies" every time since it may change
3952 * behind our back and break the math.
3954 tmp_jiffies
= jiffies
;
3955 target_jiffies
= timestamp_jiffies
+
3956 msecs_to_jiffies_timeout(to_wait_ms
);
3958 if (time_after(target_jiffies
, tmp_jiffies
)) {
3959 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3960 while (remaining_jiffies
)
3962 schedule_timeout_uninterruptible(remaining_jiffies
);
3965 static inline bool __i915_request_irq_complete(struct drm_i915_gem_request
*req
)
3967 struct intel_engine_cs
*engine
= req
->engine
;
3969 /* Before we do the heavier coherent read of the seqno,
3970 * check the value (hopefully) in the CPU cacheline.
3972 if (i915_gem_request_completed(req
))
3975 /* Ensure our read of the seqno is coherent so that we
3976 * do not "miss an interrupt" (i.e. if this is the last
3977 * request and the seqno write from the GPU is not visible
3978 * by the time the interrupt fires, we will see that the
3979 * request is incomplete and go back to sleep awaiting
3980 * another interrupt that will never come.)
3982 * Strictly, we only need to do this once after an interrupt,
3983 * but it is easier and safer to do it every time the waiter
3986 if (engine
->irq_seqno_barrier
&&
3987 cmpxchg_relaxed(&engine
->irq_posted
, 1, 0)) {
3988 /* The ordering of irq_posted versus applying the barrier
3989 * is crucial. The clearing of the current irq_posted must
3990 * be visible before we perform the barrier operation,
3991 * such that if a subsequent interrupt arrives, irq_posted
3992 * is reasserted and our task rewoken (which causes us to
3993 * do another __i915_request_irq_complete() immediately
3994 * and reapply the barrier). Conversely, if the clear
3995 * occurs after the barrier, then an interrupt that arrived
3996 * whilst we waited on the barrier would not trigger a
3997 * barrier on the next pass, and the read may not see the
4000 engine
->irq_seqno_barrier(engine
);
4001 if (i915_gem_request_completed(req
))
4005 /* We need to check whether any gpu reset happened in between
4006 * the request being submitted and now. If a reset has occurred,
4007 * the seqno will have been advance past ours and our request
4008 * is complete. If we are in the process of handling a reset,
4009 * the request is effectively complete as the rendering will
4010 * be discarded, but we need to return in order to drop the
4013 if (i915_reset_in_progress(&req
->i915
->gpu_error
))