1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/shmem_fs.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
51 #include "i915_params.h"
54 #include "intel_bios.h"
55 #include "intel_dpll_mgr.h"
56 #include "intel_guc.h"
57 #include "intel_lrc.h"
58 #include "intel_ringbuffer.h"
61 #include "i915_gem_gtt.h"
62 #include "i915_gem_render_state.h"
64 #include "intel_gvt.h"
66 /* General customization:
69 #define DRIVER_NAME "i915"
70 #define DRIVER_DESC "Intel Graphics"
71 #define DRIVER_DATE "20160606"
74 /* Many gcc seem to no see through this and fall over :( */
76 #define WARN_ON(x) ({ \
77 bool __i915_warn_cond = (x); \
78 if (__builtin_constant_p(__i915_warn_cond)) \
79 BUILD_BUG_ON(__i915_warn_cond); \
80 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
82 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
86 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
88 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
89 (long) (x), __func__);
91 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
92 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
93 * which may not necessarily be a user visible problem. This will either
94 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
95 * enable distros and users to tailor their preferred amount of i915 abrt
98 #define I915_STATE_WARN(condition, format...) ({ \
99 int __ret_warn_on = !!(condition); \
100 if (unlikely(__ret_warn_on)) \
101 if (!WARN(i915.verbose_state_checks, format)) \
103 unlikely(__ret_warn_on); \
106 #define I915_STATE_WARN_ON(x) \
107 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
109 bool __i915_inject_load_failure(const char *func
, int line
);
110 #define i915_inject_load_failure() \
111 __i915_inject_load_failure(__func__, __LINE__)
113 static inline const char *yesno(bool v
)
115 return v
? "yes" : "no";
118 static inline const char *onoff(bool v
)
120 return v
? "on" : "off";
129 I915_MAX_PIPES
= _PIPE_EDP
131 #define pipe_name(p) ((p) + 'A')
143 static inline const char *transcoder_name(enum transcoder transcoder
)
145 switch (transcoder
) {
154 case TRANSCODER_DSI_A
:
156 case TRANSCODER_DSI_C
:
163 static inline bool transcoder_is_dsi(enum transcoder transcoder
)
165 return transcoder
== TRANSCODER_DSI_A
|| transcoder
== TRANSCODER_DSI_C
;
169 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
170 * number of planes per CRTC. Not all platforms really have this many planes,
171 * which means some arrays of size I915_MAX_PLANES may have unused entries
172 * between the topmost sprite plane and the cursor plane.
181 #define plane_name(p) ((p) + 'A')
183 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
193 #define port_name(p) ((p) + 'A')
195 #define I915_NUM_PHYS_VLV 2
207 enum intel_display_power_domain
{
211 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
212 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
213 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
214 POWER_DOMAIN_TRANSCODER_A
,
215 POWER_DOMAIN_TRANSCODER_B
,
216 POWER_DOMAIN_TRANSCODER_C
,
217 POWER_DOMAIN_TRANSCODER_EDP
,
218 POWER_DOMAIN_TRANSCODER_DSI_A
,
219 POWER_DOMAIN_TRANSCODER_DSI_C
,
220 POWER_DOMAIN_PORT_DDI_A_LANES
,
221 POWER_DOMAIN_PORT_DDI_B_LANES
,
222 POWER_DOMAIN_PORT_DDI_C_LANES
,
223 POWER_DOMAIN_PORT_DDI_D_LANES
,
224 POWER_DOMAIN_PORT_DDI_E_LANES
,
225 POWER_DOMAIN_PORT_DSI
,
226 POWER_DOMAIN_PORT_CRT
,
227 POWER_DOMAIN_PORT_OTHER
,
236 POWER_DOMAIN_MODESET
,
242 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
243 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
244 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
245 #define POWER_DOMAIN_TRANSCODER(tran) \
246 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
247 (tran) + POWER_DOMAIN_TRANSCODER_A)
251 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
263 #define for_each_hpd_pin(__pin) \
264 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
266 struct i915_hotplug
{
267 struct work_struct hotplug_work
;
270 unsigned long last_jiffies
;
275 HPD_MARK_DISABLED
= 2
277 } stats
[HPD_NUM_PINS
];
279 struct delayed_work reenable_work
;
281 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
284 struct work_struct dig_port_work
;
287 * if we get a HPD irq from DP and a HPD irq from non-DP
288 * the non-DP HPD could block the workqueue on a mode config
289 * mutex getting, that userspace may have taken. However
290 * userspace is waiting on the DP workqueue to run which is
291 * blocked behind the non-DP one.
293 struct workqueue_struct
*dp_wq
;
296 #define I915_GEM_GPU_DOMAINS \
297 (I915_GEM_DOMAIN_RENDER | \
298 I915_GEM_DOMAIN_SAMPLER | \
299 I915_GEM_DOMAIN_COMMAND | \
300 I915_GEM_DOMAIN_INSTRUCTION | \
301 I915_GEM_DOMAIN_VERTEX)
303 #define for_each_pipe(__dev_priv, __p) \
304 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
305 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
306 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
307 for_each_if ((__mask) & (1 << (__p)))
308 #define for_each_plane(__dev_priv, __pipe, __p) \
310 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
312 #define for_each_sprite(__dev_priv, __p, __s) \
314 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
317 #define for_each_port_masked(__port, __ports_mask) \
318 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
319 for_each_if ((__ports_mask) & (1 << (__port)))
321 #define for_each_crtc(dev, crtc) \
322 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
324 #define for_each_intel_plane(dev, intel_plane) \
325 list_for_each_entry(intel_plane, \
326 &dev->mode_config.plane_list, \
329 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
330 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, \
332 for_each_if ((plane_mask) & \
333 (1 << drm_plane_index(&intel_plane->base)))
335 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
336 list_for_each_entry(intel_plane, \
337 &(dev)->mode_config.plane_list, \
339 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
341 #define for_each_intel_crtc(dev, intel_crtc) \
342 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
344 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
345 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) \
346 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
348 #define for_each_intel_encoder(dev, intel_encoder) \
349 list_for_each_entry(intel_encoder, \
350 &(dev)->mode_config.encoder_list, \
353 #define for_each_intel_connector(dev, intel_connector) \
354 list_for_each_entry(intel_connector, \
355 &dev->mode_config.connector_list, \
358 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
359 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
360 for_each_if ((intel_encoder)->base.crtc == (__crtc))
362 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
363 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
364 for_each_if ((intel_connector)->base.encoder == (__encoder))
366 #define for_each_power_domain(domain, mask) \
367 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
368 for_each_if ((1 << (domain)) & (mask))
370 struct drm_i915_private
;
371 struct i915_mm_struct
;
372 struct i915_mmu_object
;
374 struct drm_i915_file_private
{
375 struct drm_i915_private
*dev_priv
;
376 struct drm_file
*file
;
380 struct list_head request_list
;
381 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
382 * chosen to prevent the CPU getting more than a frame ahead of the GPU
383 * (when using lax throttling for the frontbuffer). We also use it to
384 * offer free GPU waitboosts for severely congested workloads.
386 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
388 struct idr context_idr
;
390 struct intel_rps_client
{
391 struct list_head link
;
395 unsigned int bsd_ring
;
398 /* Used by dp and fdi links */
399 struct intel_link_m_n
{
407 void intel_link_compute_m_n(int bpp
, int nlanes
,
408 int pixel_clock
, int link_clock
,
409 struct intel_link_m_n
*m_n
);
411 /* Interface history:
414 * 1.2: Add Power Management
415 * 1.3: Add vblank support
416 * 1.4: Fix cmdbuffer path, add heap destroy
417 * 1.5: Add vblank pipe configuration
418 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
419 * - Support vertical blank on secondary display pipe
421 #define DRIVER_MAJOR 1
422 #define DRIVER_MINOR 6
423 #define DRIVER_PATCHLEVEL 0
425 #define WATCH_LISTS 0
427 struct opregion_header
;
428 struct opregion_acpi
;
429 struct opregion_swsci
;
430 struct opregion_asle
;
432 struct intel_opregion
{
433 struct opregion_header
*header
;
434 struct opregion_acpi
*acpi
;
435 struct opregion_swsci
*swsci
;
436 u32 swsci_gbda_sub_functions
;
437 u32 swsci_sbcb_sub_functions
;
438 struct opregion_asle
*asle
;
443 struct work_struct asle_work
;
445 #define OPREGION_SIZE (8*1024)
447 struct intel_overlay
;
448 struct intel_overlay_error_state
;
450 #define I915_FENCE_REG_NONE -1
451 #define I915_MAX_NUM_FENCES 32
452 /* 32 fences + sign bit for FENCE_REG_NONE */
453 #define I915_MAX_NUM_FENCE_BITS 6
455 struct drm_i915_fence_reg
{
456 struct list_head lru_list
;
457 struct drm_i915_gem_object
*obj
;
461 struct sdvo_device_mapping
{
470 struct intel_display_error_state
;
472 struct drm_i915_error_state
{
481 /* Generic register state */
489 u32 error
; /* gen6+ */
490 u32 err_int
; /* gen7 */
491 u32 fault_data0
; /* gen8, gen9 */
492 u32 fault_data1
; /* gen8, gen9 */
498 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
499 u64 fence
[I915_MAX_NUM_FENCES
];
500 struct intel_overlay_error_state
*overlay
;
501 struct intel_display_error_state
*display
;
502 struct drm_i915_error_object
*semaphore_obj
;
504 struct drm_i915_error_ring
{
506 /* Software tracked state */
509 enum intel_ring_hangcheck_action hangcheck_action
;
512 /* our own tracking of ring head and tail */
517 u32 semaphore_seqno
[I915_NUM_ENGINES
- 1];
536 u32 rc_psmi
; /* sleep state */
537 u32 semaphore_mboxes
[I915_NUM_ENGINES
- 1];
539 struct drm_i915_error_object
{
543 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
545 struct drm_i915_error_object
*wa_ctx
;
547 struct drm_i915_error_request
{
562 char comm
[TASK_COMM_LEN
];
563 } ring
[I915_NUM_ENGINES
];
565 struct drm_i915_error_buffer
{
568 u32 rseqno
[I915_NUM_ENGINES
], wseqno
;
572 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
580 } **active_bo
, **pinned_bo
;
582 u32
*active_bo_count
, *pinned_bo_count
;
586 struct intel_connector
;
587 struct intel_encoder
;
588 struct intel_crtc_state
;
589 struct intel_initial_plane_config
;
594 struct drm_i915_display_funcs
{
595 int (*get_display_clock_speed
)(struct drm_device
*dev
);
596 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
597 int (*compute_pipe_wm
)(struct intel_crtc_state
*cstate
);
598 int (*compute_intermediate_wm
)(struct drm_device
*dev
,
599 struct intel_crtc
*intel_crtc
,
600 struct intel_crtc_state
*newstate
);
601 void (*initial_watermarks
)(struct intel_crtc_state
*cstate
);
602 void (*optimize_watermarks
)(struct intel_crtc_state
*cstate
);
603 int (*compute_global_watermarks
)(struct drm_atomic_state
*state
);
604 void (*update_wm
)(struct drm_crtc
*crtc
);
605 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
606 void (*modeset_commit_cdclk
)(struct drm_atomic_state
*state
);
607 /* Returns the active state of the crtc, and if the crtc is active,
608 * fills out the pipe-config with the hw state. */
609 bool (*get_pipe_config
)(struct intel_crtc
*,
610 struct intel_crtc_state
*);
611 void (*get_initial_plane_config
)(struct intel_crtc
*,
612 struct intel_initial_plane_config
*);
613 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
614 struct intel_crtc_state
*crtc_state
);
615 void (*crtc_enable
)(struct drm_crtc
*crtc
);
616 void (*crtc_disable
)(struct drm_crtc
*crtc
);
617 void (*audio_codec_enable
)(struct drm_connector
*connector
,
618 struct intel_encoder
*encoder
,
619 const struct drm_display_mode
*adjusted_mode
);
620 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
621 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
622 void (*init_clock_gating
)(struct drm_device
*dev
);
623 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
624 struct drm_framebuffer
*fb
,
625 struct drm_i915_gem_object
*obj
,
626 struct drm_i915_gem_request
*req
,
628 void (*hpd_irq_setup
)(struct drm_i915_private
*dev_priv
);
629 /* clock updates for mode set */
631 /* render clock increase/decrease */
632 /* display clock increase/decrease */
633 /* pll clock increase/decrease */
635 void (*load_csc_matrix
)(struct drm_crtc_state
*crtc_state
);
636 void (*load_luts
)(struct drm_crtc_state
*crtc_state
);
639 enum forcewake_domain_id
{
640 FW_DOMAIN_ID_RENDER
= 0,
641 FW_DOMAIN_ID_BLITTER
,
647 enum forcewake_domains
{
648 FORCEWAKE_RENDER
= (1 << FW_DOMAIN_ID_RENDER
),
649 FORCEWAKE_BLITTER
= (1 << FW_DOMAIN_ID_BLITTER
),
650 FORCEWAKE_MEDIA
= (1 << FW_DOMAIN_ID_MEDIA
),
651 FORCEWAKE_ALL
= (FORCEWAKE_RENDER
|
656 #define FW_REG_READ (1)
657 #define FW_REG_WRITE (2)
659 enum forcewake_domains
660 intel_uncore_forcewake_for_reg(struct drm_i915_private
*dev_priv
,
661 i915_reg_t reg
, unsigned int op
);
663 struct intel_uncore_funcs
{
664 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
665 enum forcewake_domains domains
);
666 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
667 enum forcewake_domains domains
);
669 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
670 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
671 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
672 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
674 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
675 uint8_t val
, bool trace
);
676 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
677 uint16_t val
, bool trace
);
678 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
679 uint32_t val
, bool trace
);
680 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
681 uint64_t val
, bool trace
);
684 struct intel_uncore
{
685 spinlock_t lock
; /** lock is also taken in irq contexts. */
687 struct intel_uncore_funcs funcs
;
690 enum forcewake_domains fw_domains
;
692 struct intel_uncore_forcewake_domain
{
693 struct drm_i915_private
*i915
;
694 enum forcewake_domain_id id
;
695 enum forcewake_domains mask
;
697 struct hrtimer timer
;
704 } fw_domain
[FW_DOMAIN_ID_COUNT
];
706 int unclaimed_mmio_check
;
709 /* Iterate over initialised fw domains */
710 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
711 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
712 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
714 for_each_if ((mask__) & (domain__)->mask)
716 #define for_each_fw_domain(domain__, dev_priv__) \
717 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
719 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
720 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
721 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
724 struct work_struct work
;
726 uint32_t *dmc_payload
;
727 uint32_t dmc_fw_size
;
730 i915_reg_t mmioaddr
[8];
731 uint32_t mmiodata
[8];
733 uint32_t allowed_dc_mask
;
736 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
737 func(is_mobile) sep \
740 func(is_i945gm) sep \
742 func(need_gfx_hws) sep \
744 func(is_pineview) sep \
745 func(is_broadwater) sep \
746 func(is_crestline) sep \
747 func(is_ivybridge) sep \
748 func(is_valleyview) sep \
749 func(is_cherryview) sep \
750 func(is_haswell) sep \
751 func(is_broadwell) sep \
752 func(is_skylake) sep \
753 func(is_broxton) sep \
754 func(is_kabylake) sep \
755 func(is_preliminary) sep \
757 func(has_pipe_cxsr) sep \
758 func(has_hotplug) sep \
759 func(cursor_needs_physical) sep \
760 func(has_overlay) sep \
761 func(overlay_needs_physical) sep \
762 func(supports_tv) sep \
764 func(has_snoop) sep \
766 func(has_fpga_dbg) sep \
769 #define DEFINE_FLAG(name) u8 name:1
770 #define SEP_SEMICOLON ;
772 struct intel_device_info
{
773 u32 display_mmio_offset
;
776 u8 num_sprites
[I915_MAX_PIPES
];
779 u8 ring_mask
; /* Rings supported by the HW */
780 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
781 /* Register offsets for the various display pipes and transcoders */
782 int pipe_offsets
[I915_MAX_TRANSCODERS
];
783 int trans_offsets
[I915_MAX_TRANSCODERS
];
784 int palette_offsets
[I915_MAX_PIPES
];
785 int cursor_offsets
[I915_MAX_PIPES
];
787 /* Slice/subslice/EU info */
790 u8 subslice_per_slice
;
794 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
797 u8 has_subslice_pg
:1;
801 u16 degamma_lut_size
;
809 enum i915_cache_level
{
811 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
812 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
813 caches, eg sampler/render caches, and the
814 large Last-Level-Cache. LLC is coherent with
815 the CPU, but L3 is only visible to the GPU. */
816 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
819 struct i915_ctx_hang_stats
{
820 /* This context had batch pending when hang was declared */
821 unsigned batch_pending
;
823 /* This context had batch active when hang was declared */
824 unsigned batch_active
;
826 /* Time when this context was last blamed for a GPU reset */
827 unsigned long guilty_ts
;
829 /* If the contexts causes a second GPU hang within this time,
830 * it is permanently banned from submitting any more work.
832 unsigned long ban_period_seconds
;
834 /* This context is banned to submit more work */
838 /* This must match up with the value previously used for execbuf2.rsvd1. */
839 #define DEFAULT_CONTEXT_HANDLE 0
842 * struct i915_gem_context - as the name implies, represents a context.
843 * @ref: reference count.
844 * @user_handle: userspace tracking identity for this context.
845 * @remap_slice: l3 row remapping information.
846 * @flags: context specific flags:
847 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
848 * @file_priv: filp associated with this context (NULL for global default
850 * @hang_stats: information about the role of this context in possible GPU
852 * @ppgtt: virtual memory space used by this context.
853 * @legacy_hw_ctx: render context backing object and whether it is correctly
854 * initialized (legacy ring submission mechanism only).
855 * @link: link in the global list of contexts.
857 * Contexts are memory images used by the hardware to store copies of their
860 struct i915_gem_context
{
862 struct drm_i915_private
*i915
;
863 struct drm_i915_file_private
*file_priv
;
864 struct i915_hw_ppgtt
*ppgtt
;
866 struct i915_ctx_hang_stats hang_stats
;
868 /* Unique identifier for this context, used by the hw for tracking */
872 #define CONTEXT_NO_ZEROMAP (1<<0)
874 struct intel_context
{
875 struct drm_i915_gem_object
*state
;
876 struct intel_ringbuffer
*ringbuf
;
877 struct i915_vma
*lrc_vma
;
878 uint32_t *lrc_reg_state
;
882 } engine
[I915_NUM_ENGINES
];
885 struct list_head link
;
899 /* This is always the inner lock when overlapping with struct_mutex and
900 * it's the outer lock when overlapping with stolen_lock. */
903 unsigned int possible_framebuffer_bits
;
904 unsigned int busy_bits
;
905 unsigned int visible_pipes_mask
;
906 struct intel_crtc
*crtc
;
908 struct drm_mm_node compressed_fb
;
909 struct drm_mm_node
*compressed_llb
;
916 struct intel_fbc_state_cache
{
918 unsigned int mode_flags
;
919 uint32_t hsw_bdw_pixel_rate
;
923 unsigned int rotation
;
931 uint32_t pixel_format
;
934 unsigned int tiling_mode
;
938 struct intel_fbc_reg_params
{
942 unsigned int fence_y_offset
;
947 uint32_t pixel_format
;
955 struct intel_fbc_work
{
957 u32 scheduled_vblank
;
958 struct work_struct work
;
961 const char *no_fbc_reason
;
965 * HIGH_RR is the highest eDP panel refresh rate read from EDID
966 * LOW_RR is the lowest eDP panel refresh rate found from EDID
967 * parsing for same resolution.
969 enum drrs_refresh_rate_type
{
972 DRRS_MAX_RR
, /* RR count */
975 enum drrs_support_type
{
976 DRRS_NOT_SUPPORTED
= 0,
977 STATIC_DRRS_SUPPORT
= 1,
978 SEAMLESS_DRRS_SUPPORT
= 2
984 struct delayed_work work
;
986 unsigned busy_frontbuffer_bits
;
987 enum drrs_refresh_rate_type refresh_rate_type
;
988 enum drrs_support_type type
;
995 struct intel_dp
*enabled
;
997 struct delayed_work work
;
998 unsigned busy_frontbuffer_bits
;
1000 bool aux_frame_sync
;
1005 PCH_NONE
= 0, /* No PCH present */
1006 PCH_IBX
, /* Ibexpeak PCH */
1007 PCH_CPT
, /* Cougarpoint PCH */
1008 PCH_LPT
, /* Lynxpoint PCH */
1009 PCH_SPT
, /* Sunrisepoint PCH */
1013 enum intel_sbi_destination
{
1018 #define QUIRK_PIPEA_FORCE (1<<0)
1019 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1020 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1021 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1022 #define QUIRK_PIPEB_FORCE (1<<4)
1023 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1026 struct intel_fbc_work
;
1028 struct intel_gmbus
{
1029 struct i2c_adapter adapter
;
1030 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1033 i915_reg_t gpio_reg
;
1034 struct i2c_algo_bit_data bit_algo
;
1035 struct drm_i915_private
*dev_priv
;
1038 struct i915_suspend_saved_registers
{
1041 u32 savePP_ON_DELAYS
;
1042 u32 savePP_OFF_DELAYS
;
1047 u32 saveFBC_CONTROL
;
1048 u32 saveCACHE_MODE_0
;
1049 u32 saveMI_ARB_STATE
;
1053 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1054 u32 savePCH_PORT_HOTPLUG
;
1058 struct vlv_s0ix_state
{
1065 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1066 u32 media_max_req_count
;
1067 u32 gfx_max_req_count
;
1093 u32 rp_down_timeout
;
1099 /* Display 1 CZ domain */
1104 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1106 /* GT SA CZ domain */
1113 /* Display 2 CZ domain */
1117 u32 clock_gate_dis2
;
1120 struct intel_rps_ei
{
1126 struct intel_gen6_power_mgmt
{
1128 * work, interrupts_enabled and pm_iir are protected by
1129 * dev_priv->irq_lock
1131 struct work_struct work
;
1132 bool interrupts_enabled
;
1137 /* Frequencies are stored in potentially platform dependent multiples.
1138 * In other words, *_freq needs to be multiplied by X to be interesting.
1139 * Soft limits are those which are used for the dynamic reclocking done
1140 * by the driver (raise frequencies under heavy loads, and lower for
1141 * lighter loads). Hard limits are those imposed by the hardware.
1143 * A distinction is made for overclocking, which is never enabled by
1144 * default, and is considered to be above the hard limit if it's
1147 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1148 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1149 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1150 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1151 u8 min_freq
; /* AKA RPn. Minimum frequency */
1152 u8 idle_freq
; /* Frequency to request when we are idle */
1153 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1154 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1155 u8 rp0_freq
; /* Non-overclocked max frequency. */
1156 u16 gpll_ref_freq
; /* vlv/chv GPLL reference frequency */
1158 u8 up_threshold
; /* Current %busy required to uplock */
1159 u8 down_threshold
; /* Current %busy required to downclock */
1162 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1164 spinlock_t client_lock
;
1165 struct list_head clients
;
1169 struct delayed_work delayed_resume_work
;
1172 struct intel_rps_client semaphores
, mmioflips
;
1174 /* manual wa residency calculations */
1175 struct intel_rps_ei up_ei
, down_ei
;
1178 * Protects RPS/RC6 register access and PCU communication.
1179 * Must be taken after struct_mutex if nested. Note that
1180 * this lock may be held for long periods of time when
1181 * talking to hw - so only take it when talking to hw!
1183 struct mutex hw_lock
;
1186 /* defined intel_pm.c */
1187 extern spinlock_t mchdev_lock
;
1189 struct intel_ilk_power_mgmt
{
1197 unsigned long last_time1
;
1198 unsigned long chipset_power
;
1201 unsigned long gfx_power
;
1208 struct drm_i915_private
;
1209 struct i915_power_well
;
1211 struct i915_power_well_ops
{
1213 * Synchronize the well's hw state to match the current sw state, for
1214 * example enable/disable it based on the current refcount. Called
1215 * during driver init and resume time, possibly after first calling
1216 * the enable/disable handlers.
1218 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1219 struct i915_power_well
*power_well
);
1221 * Enable the well and resources that depend on it (for example
1222 * interrupts located on the well). Called after the 0->1 refcount
1225 void (*enable
)(struct drm_i915_private
*dev_priv
,
1226 struct i915_power_well
*power_well
);
1228 * Disable the well and resources that depend on it. Called after
1229 * the 1->0 refcount transition.
1231 void (*disable
)(struct drm_i915_private
*dev_priv
,
1232 struct i915_power_well
*power_well
);
1233 /* Returns the hw enabled state. */
1234 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1235 struct i915_power_well
*power_well
);
1238 /* Power well structure for haswell */
1239 struct i915_power_well
{
1242 /* power well enable/disable usage count */
1244 /* cached hw enabled state */
1246 unsigned long domains
;
1248 const struct i915_power_well_ops
*ops
;
1251 struct i915_power_domains
{
1253 * Power wells needed for initialization at driver init and suspend
1254 * time are on. They are kept on until after the first modeset.
1258 int power_well_count
;
1261 int domain_use_count
[POWER_DOMAIN_NUM
];
1262 struct i915_power_well
*power_wells
;
1265 #define MAX_L3_SLICES 2
1266 struct intel_l3_parity
{
1267 u32
*remap_info
[MAX_L3_SLICES
];
1268 struct work_struct error_work
;
1272 struct i915_gem_mm
{
1273 /** Memory allocator for GTT stolen memory */
1274 struct drm_mm stolen
;
1275 /** Protects the usage of the GTT stolen memory allocator. This is
1276 * always the inner lock when overlapping with struct_mutex. */
1277 struct mutex stolen_lock
;
1279 /** List of all objects in gtt_space. Used to restore gtt
1280 * mappings on resume */
1281 struct list_head bound_list
;
1283 * List of objects which are not bound to the GTT (thus
1284 * are idle and not used by the GPU) but still have
1285 * (presumably uncached) pages still attached.
1287 struct list_head unbound_list
;
1289 /** Usable portion of the GTT for GEM */
1290 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1292 /** PPGTT used for aliasing the PPGTT with the GTT */
1293 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1295 struct notifier_block oom_notifier
;
1296 struct notifier_block vmap_notifier
;
1297 struct shrinker shrinker
;
1298 bool shrinker_no_lock_stealing
;
1300 /** LRU list of objects with fence regs on them. */
1301 struct list_head fence_list
;
1304 * We leave the user IRQ off as much as possible,
1305 * but this means that requests will finish and never
1306 * be retired once the system goes idle. Set a timer to
1307 * fire periodically while the ring is running. When it
1308 * fires, go retire requests.
1310 struct delayed_work retire_work
;
1313 * When we detect an idle GPU, we want to turn on
1314 * powersaving features. So once we see that there
1315 * are no more requests outstanding and no more
1316 * arrive within a small period of time, we fire
1317 * off the idle_work.
1319 struct delayed_work idle_work
;
1322 * Are we in a non-interruptible section of code like
1328 * Is the GPU currently considered idle, or busy executing userspace
1329 * requests? Whilst idle, we attempt to power down the hardware and
1330 * display clocks. In order to reduce the effect on performance, there
1331 * is a slight delay before we do so.
1335 /* the indicator for dispatch video commands on two BSD rings */
1336 unsigned int bsd_ring_dispatch_index
;
1338 /** Bit 6 swizzling required for X tiling */
1339 uint32_t bit_6_swizzle_x
;
1340 /** Bit 6 swizzling required for Y tiling */
1341 uint32_t bit_6_swizzle_y
;
1343 /* accounting, useful for userland debugging */
1344 spinlock_t object_stat_lock
;
1345 size_t object_memory
;
1349 struct drm_i915_error_state_buf
{
1350 struct drm_i915_private
*i915
;
1359 struct i915_error_state_file_priv
{
1360 struct drm_device
*dev
;
1361 struct drm_i915_error_state
*error
;
1364 struct i915_gpu_error
{
1365 /* For hangcheck timer */
1366 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1367 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1368 /* Hang gpu twice in this window and your context gets banned */
1369 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1371 struct workqueue_struct
*hangcheck_wq
;
1372 struct delayed_work hangcheck_work
;
1374 /* For reset and error_state handling. */
1376 /* Protected by the above dev->gpu_error.lock. */
1377 struct drm_i915_error_state
*first_error
;
1379 unsigned long missed_irq_rings
;
1382 * State variable controlling the reset flow and count
1384 * This is a counter which gets incremented when reset is triggered,
1385 * and again when reset has been handled. So odd values (lowest bit set)
1386 * means that reset is in progress and even values that
1387 * (reset_counter >> 1):th reset was successfully completed.
1389 * If reset is not completed succesfully, the I915_WEDGE bit is
1390 * set meaning that hardware is terminally sour and there is no
1391 * recovery. All waiters on the reset_queue will be woken when
1394 * This counter is used by the wait_seqno code to notice that reset
1395 * event happened and it needs to restart the entire ioctl (since most
1396 * likely the seqno it waited for won't ever signal anytime soon).
1398 * This is important for lock-free wait paths, where no contended lock
1399 * naturally enforces the correct ordering between the bail-out of the
1400 * waiter and the gpu reset work code.
1402 atomic_t reset_counter
;
1404 #define I915_RESET_IN_PROGRESS_FLAG 1
1405 #define I915_WEDGED (1 << 31)
1408 * Waitqueue to signal when the reset has completed. Used by clients
1409 * that wait for dev_priv->mm.wedged to settle.
1411 wait_queue_head_t reset_queue
;
1413 /* Userspace knobs for gpu hang simulation;
1414 * combines both a ring mask, and extra flags
1417 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1418 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1420 /* For missed irq/seqno simulation. */
1421 unsigned int test_irq_rings
;
1424 enum modeset_restore
{
1425 MODESET_ON_LID_OPEN
,
1430 #define DP_AUX_A 0x40
1431 #define DP_AUX_B 0x10
1432 #define DP_AUX_C 0x20
1433 #define DP_AUX_D 0x30
1435 #define DDC_PIN_B 0x05
1436 #define DDC_PIN_C 0x04
1437 #define DDC_PIN_D 0x06
1439 struct ddi_vbt_port_info
{
1441 * This is an index in the HDMI/DVI DDI buffer translation table.
1442 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1443 * populate this field.
1445 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1446 uint8_t hdmi_level_shift
;
1448 uint8_t supports_dvi
:1;
1449 uint8_t supports_hdmi
:1;
1450 uint8_t supports_dp
:1;
1452 uint8_t alternate_aux_channel
;
1453 uint8_t alternate_ddc_pin
;
1455 uint8_t dp_boost_level
;
1456 uint8_t hdmi_boost_level
;
1459 enum psr_lines_to_wait
{
1460 PSR_0_LINES_TO_WAIT
= 0,
1462 PSR_4_LINES_TO_WAIT
,
1466 struct intel_vbt_data
{
1467 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1468 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1471 unsigned int int_tv_support
:1;
1472 unsigned int lvds_dither
:1;
1473 unsigned int lvds_vbt
:1;
1474 unsigned int int_crt_support
:1;
1475 unsigned int lvds_use_ssc
:1;
1476 unsigned int display_clock_mode
:1;
1477 unsigned int fdi_rx_polarity_inverted
:1;
1478 unsigned int panel_type
:4;
1480 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1482 enum drrs_support_type drrs_type
;
1493 struct edp_power_seq pps
;
1498 bool require_aux_wakeup
;
1500 enum psr_lines_to_wait lines_to_wait
;
1501 int tp1_wakeup_time
;
1502 int tp2_tp3_wakeup_time
;
1508 bool active_low_pwm
;
1509 u8 min_brightness
; /* min_brightness/255 of max */
1510 enum intel_backlight_type type
;
1516 struct mipi_config
*config
;
1517 struct mipi_pps_data
*pps
;
1521 const u8
*sequence
[MIPI_SEQ_MAX
];
1527 union child_device_config
*child_dev
;
1529 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1530 struct sdvo_device_mapping sdvo_mappings
[2];
1533 enum intel_ddb_partitioning
{
1535 INTEL_DDB_PART_5_6
, /* IVB+ */
1538 struct intel_wm_level
{
1546 struct ilk_wm_values
{
1547 uint32_t wm_pipe
[3];
1549 uint32_t wm_lp_spr
[3];
1550 uint32_t wm_linetime
[3];
1552 enum intel_ddb_partitioning partitioning
;
1555 struct vlv_pipe_wm
{
1566 struct vlv_wm_values
{
1567 struct vlv_pipe_wm pipe
[3];
1568 struct vlv_sr_wm sr
;
1578 struct skl_ddb_entry
{
1579 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1582 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1584 return entry
->end
- entry
->start
;
1587 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1588 const struct skl_ddb_entry
*e2
)
1590 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1596 struct skl_ddb_allocation
{
1597 struct skl_ddb_entry pipe
[I915_MAX_PIPES
];
1598 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1599 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1602 struct skl_wm_values
{
1603 unsigned dirty_pipes
;
1604 struct skl_ddb_allocation ddb
;
1605 uint32_t wm_linetime
[I915_MAX_PIPES
];
1606 uint32_t plane
[I915_MAX_PIPES
][I915_MAX_PLANES
][8];
1607 uint32_t plane_trans
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1610 struct skl_wm_level
{
1611 bool plane_en
[I915_MAX_PLANES
];
1612 uint16_t plane_res_b
[I915_MAX_PLANES
];
1613 uint8_t plane_res_l
[I915_MAX_PLANES
];
1617 * This struct helps tracking the state needed for runtime PM, which puts the
1618 * device in PCI D3 state. Notice that when this happens, nothing on the
1619 * graphics device works, even register access, so we don't get interrupts nor
1622 * Every piece of our code that needs to actually touch the hardware needs to
1623 * either call intel_runtime_pm_get or call intel_display_power_get with the
1624 * appropriate power domain.
1626 * Our driver uses the autosuspend delay feature, which means we'll only really
1627 * suspend if we stay with zero refcount for a certain amount of time. The
1628 * default value is currently very conservative (see intel_runtime_pm_enable), but
1629 * it can be changed with the standard runtime PM files from sysfs.
1631 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1632 * goes back to false exactly before we reenable the IRQs. We use this variable
1633 * to check if someone is trying to enable/disable IRQs while they're supposed
1634 * to be disabled. This shouldn't happen and we'll print some error messages in
1637 * For more, read the Documentation/power/runtime_pm.txt.
1639 struct i915_runtime_pm
{
1640 atomic_t wakeref_count
;
1641 atomic_t atomic_seq
;
1646 enum intel_pipe_crc_source
{
1647 INTEL_PIPE_CRC_SOURCE_NONE
,
1648 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1649 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1650 INTEL_PIPE_CRC_SOURCE_PF
,
1651 INTEL_PIPE_CRC_SOURCE_PIPE
,
1652 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1653 INTEL_PIPE_CRC_SOURCE_TV
,
1654 INTEL_PIPE_CRC_SOURCE_DP_B
,
1655 INTEL_PIPE_CRC_SOURCE_DP_C
,
1656 INTEL_PIPE_CRC_SOURCE_DP_D
,
1657 INTEL_PIPE_CRC_SOURCE_AUTO
,
1658 INTEL_PIPE_CRC_SOURCE_MAX
,
1661 struct intel_pipe_crc_entry
{
1666 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1667 struct intel_pipe_crc
{
1669 bool opened
; /* exclusive access to the result file */
1670 struct intel_pipe_crc_entry
*entries
;
1671 enum intel_pipe_crc_source source
;
1673 wait_queue_head_t wq
;
1676 struct i915_frontbuffer_tracking
{
1680 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1687 struct i915_wa_reg
{
1690 /* bitmask representing WA bits */
1695 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1696 * allowing it for RCS as we don't foresee any requirement of having
1697 * a whitelist for other engines. When it is really required for
1698 * other engines then the limit need to be increased.
1700 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1702 struct i915_workarounds
{
1703 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1705 u32 hw_whitelist_count
[I915_NUM_ENGINES
];
1708 struct i915_virtual_gpu
{
1712 struct i915_execbuffer_params
{
1713 struct drm_device
*dev
;
1714 struct drm_file
*file
;
1715 uint32_t dispatch_flags
;
1716 uint32_t args_batch_start_offset
;
1717 uint64_t batch_obj_vm_offset
;
1718 struct intel_engine_cs
*engine
;
1719 struct drm_i915_gem_object
*batch_obj
;
1720 struct i915_gem_context
*ctx
;
1721 struct drm_i915_gem_request
*request
;
1724 /* used in computing the new watermarks state */
1725 struct intel_wm_config
{
1726 unsigned int num_pipes_active
;
1727 bool sprites_enabled
;
1728 bool sprites_scaled
;
1731 struct drm_i915_private
{
1732 struct drm_device
*dev
;
1733 struct kmem_cache
*objects
;
1734 struct kmem_cache
*vmas
;
1735 struct kmem_cache
*requests
;
1737 const struct intel_device_info info
;
1739 int relative_constants_mode
;
1743 struct intel_uncore uncore
;
1745 struct i915_virtual_gpu vgpu
;
1747 struct intel_gvt gvt
;
1749 struct intel_guc guc
;
1751 struct intel_csr csr
;
1753 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
1755 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1756 * controller on different i2c buses. */
1757 struct mutex gmbus_mutex
;
1760 * Base address of the gmbus and gpio block.
1762 uint32_t gpio_mmio_base
;
1764 /* MMIO base address for MIPI regs */
1765 uint32_t mipi_mmio_base
;
1767 uint32_t psr_mmio_base
;
1769 wait_queue_head_t gmbus_wait_queue
;
1771 struct pci_dev
*bridge_dev
;
1772 struct i915_gem_context
*kernel_context
;
1773 struct intel_engine_cs engine
[I915_NUM_ENGINES
];
1774 struct drm_i915_gem_object
*semaphore_obj
;
1775 uint32_t last_seqno
, next_seqno
;
1777 struct drm_dma_handle
*status_page_dmah
;
1778 struct resource mch_res
;
1780 /* protects the irq masks */
1781 spinlock_t irq_lock
;
1783 /* protects the mmio flip data */
1784 spinlock_t mmio_flip_lock
;
1786 bool display_irqs_enabled
;
1788 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1789 struct pm_qos_request pm_qos
;
1791 /* Sideband mailbox protection */
1792 struct mutex sb_lock
;
1794 /** Cached value of IMR to avoid reads in updating the bitfield */
1797 u32 de_irq_mask
[I915_MAX_PIPES
];
1802 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1804 struct i915_hotplug hotplug
;
1805 struct intel_fbc fbc
;
1806 struct i915_drrs drrs
;
1807 struct intel_opregion opregion
;
1808 struct intel_vbt_data vbt
;
1810 bool preserve_bios_swizzle
;
1813 struct intel_overlay
*overlay
;
1815 /* backlight registers and fields in struct intel_panel */
1816 struct mutex backlight_lock
;
1819 bool no_aux_handshake
;
1821 /* protects panel power sequencer state */
1822 struct mutex pps_mutex
;
1824 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1825 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1827 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1828 unsigned int skl_preferred_vco_freq
;
1829 unsigned int cdclk_freq
, max_cdclk_freq
, atomic_cdclk_freq
;
1830 unsigned int max_dotclk_freq
;
1831 unsigned int rawclk_freq
;
1832 unsigned int hpll_freq
;
1833 unsigned int czclk_freq
;
1836 unsigned int vco
, ref
;
1840 * wq - Driver workqueue for GEM.
1842 * NOTE: Work items scheduled here are not allowed to grab any modeset
1843 * locks, for otherwise the flushing done in the pageflip code will
1844 * result in deadlocks.
1846 struct workqueue_struct
*wq
;
1848 /* Display functions */
1849 struct drm_i915_display_funcs display
;
1851 /* PCH chipset type */
1852 enum intel_pch pch_type
;
1853 unsigned short pch_id
;
1855 unsigned long quirks
;
1857 enum modeset_restore modeset_restore
;
1858 struct mutex modeset_restore_lock
;
1859 struct drm_atomic_state
*modeset_restore_state
;
1861 struct list_head vm_list
; /* Global list of all address spaces */
1862 struct i915_ggtt ggtt
; /* VM representing the global address space */
1864 struct i915_gem_mm mm
;
1865 DECLARE_HASHTABLE(mm_structs
, 7);
1866 struct mutex mm_lock
;
1868 /* The hw wants to have a stable context identifier for the lifetime
1869 * of the context (for OA, PASID, faults, etc). This is limited
1870 * in execlists to 21 bits.
1872 struct ida context_hw_ida
;
1873 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1875 /* Kernel Modesetting */
1877 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1878 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1879 wait_queue_head_t pending_flip_queue
;
1881 #ifdef CONFIG_DEBUG_FS
1882 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1885 /* dpll and cdclk state is protected by connection_mutex */
1886 int num_shared_dpll
;
1887 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1888 const struct intel_dpll_mgr
*dpll_mgr
;
1891 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1892 * Must be global rather than per dpll, because on some platforms
1893 * plls share registers.
1895 struct mutex dpll_lock
;
1897 unsigned int active_crtcs
;
1898 unsigned int min_pixclk
[I915_MAX_PIPES
];
1900 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1902 struct i915_workarounds workarounds
;
1904 struct i915_frontbuffer_tracking fb_tracking
;
1908 bool mchbar_need_disable
;
1910 struct intel_l3_parity l3_parity
;
1912 /* Cannot be determined by PCIID. You must always read a register. */
1915 /* gen6+ rps state */
1916 struct intel_gen6_power_mgmt rps
;
1918 /* ilk-only ips/rps state. Everything in here is protected by the global
1919 * mchdev_lock in intel_pm.c */
1920 struct intel_ilk_power_mgmt ips
;
1922 struct i915_power_domains power_domains
;
1924 struct i915_psr psr
;
1926 struct i915_gpu_error gpu_error
;
1928 struct drm_i915_gem_object
*vlv_pctx
;
1930 #ifdef CONFIG_DRM_FBDEV_EMULATION
1931 /* list of fbdev register on this device */
1932 struct intel_fbdev
*fbdev
;
1933 struct work_struct fbdev_suspend_work
;
1936 struct drm_property
*broadcast_rgb_property
;
1937 struct drm_property
*force_audio_property
;
1939 /* hda/i915 audio component */
1940 struct i915_audio_component
*audio_component
;
1941 bool audio_component_registered
;
1943 * av_mutex - mutex for audio/video sync
1946 struct mutex av_mutex
;
1948 uint32_t hw_context_size
;
1949 struct list_head context_list
;
1953 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1954 u32 chv_phy_control
;
1956 * Shadows for CHV DPLL_MD regs to keep the state
1957 * checker somewhat working in the presence hardware
1958 * crappiness (can't read out DPLL_MD for pipes B & C).
1960 u32 chv_dpll_md
[I915_MAX_PIPES
];
1964 bool suspended_to_idle
;
1965 struct i915_suspend_saved_registers regfile
;
1966 struct vlv_s0ix_state vlv_s0ix_state
;
1970 * Raw watermark latency values:
1971 * in 0.1us units for WM0,
1972 * in 0.5us units for WM1+.
1975 uint16_t pri_latency
[5];
1977 uint16_t spr_latency
[5];
1979 uint16_t cur_latency
[5];
1981 * Raw watermark memory latency values
1982 * for SKL for all 8 levels
1985 uint16_t skl_latency
[8];
1988 * The skl_wm_values structure is a bit too big for stack
1989 * allocation, so we keep the staging struct where we store
1990 * intermediate results here instead.
1992 struct skl_wm_values skl_results
;
1994 /* current hardware state */
1996 struct ilk_wm_values hw
;
1997 struct skl_wm_values skl_hw
;
1998 struct vlv_wm_values vlv
;
2004 * Should be held around atomic WM register writing; also
2005 * protects * intel_crtc->wm.active and
2006 * cstate->wm.need_postvbl_update.
2008 struct mutex wm_mutex
;
2011 * Set during HW readout of watermarks/DDB. Some platforms
2012 * need to know when we're still using BIOS-provided values
2013 * (which we don't fully trust).
2015 bool distrust_bios_wm
;
2018 struct i915_runtime_pm pm
;
2020 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2022 int (*execbuf_submit
)(struct i915_execbuffer_params
*params
,
2023 struct drm_i915_gem_execbuffer2
*args
,
2024 struct list_head
*vmas
);
2025 int (*init_engines
)(struct drm_device
*dev
);
2026 void (*cleanup_engine
)(struct intel_engine_cs
*engine
);
2027 void (*stop_engine
)(struct intel_engine_cs
*engine
);
2030 /* perform PHY state sanity checks? */
2031 bool chv_phy_assert
[2];
2033 struct intel_encoder
*dig_port_map
[I915_MAX_PORTS
];
2036 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2037 * will be rejected. Instead look for a better place.
2041 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
2043 return dev
->dev_private
;
2046 static inline struct drm_i915_private
*dev_to_i915(struct device
*dev
)
2048 return to_i915(dev_get_drvdata(dev
));
2051 static inline struct drm_i915_private
*guc_to_i915(struct intel_guc
*guc
)
2053 return container_of(guc
, struct drm_i915_private
, guc
);
2056 /* Simple iterator over all initialised engines */
2057 #define for_each_engine(engine__, dev_priv__) \
2058 for ((engine__) = &(dev_priv__)->engine[0]; \
2059 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2061 for_each_if (intel_engine_initialized(engine__))
2063 /* Iterator with engine_id */
2064 #define for_each_engine_id(engine__, dev_priv__, id__) \
2065 for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
2066 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2068 for_each_if (((id__) = (engine__)->id, \
2069 intel_engine_initialized(engine__)))
2071 /* Iterator over subset of engines selected by mask */
2072 #define for_each_engine_masked(engine__, dev_priv__, mask__) \
2073 for ((engine__) = &(dev_priv__)->engine[0]; \
2074 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2076 for_each_if (((mask__) & intel_engine_flag(engine__)) && \
2077 intel_engine_initialized(engine__))
2079 enum hdmi_force_audio
{
2080 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
2081 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
2082 HDMI_AUDIO_AUTO
, /* trust EDID */
2083 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
2086 #define I915_GTT_OFFSET_NONE ((u32)-1)
2088 struct drm_i915_gem_object_ops
{
2090 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2092 /* Interface between the GEM object and its backing storage.
2093 * get_pages() is called once prior to the use of the associated set
2094 * of pages before to binding them into the GTT, and put_pages() is
2095 * called after we no longer need them. As we expect there to be
2096 * associated cost with migrating pages between the backing storage
2097 * and making them available for the GPU (e.g. clflush), we may hold
2098 * onto the pages after they are no longer referenced by the GPU
2099 * in case they may be used again shortly (for example migrating the
2100 * pages to a different memory domain within the GTT). put_pages()
2101 * will therefore most likely be called when the object itself is
2102 * being released or under memory pressure (where we attempt to
2103 * reap pages for the shrinker).
2105 int (*get_pages
)(struct drm_i915_gem_object
*);
2106 void (*put_pages
)(struct drm_i915_gem_object
*);
2108 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
2109 void (*release
)(struct drm_i915_gem_object
*);
2113 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2114 * considered to be the frontbuffer for the given plane interface-wise. This
2115 * doesn't mean that the hw necessarily already scans it out, but that any
2116 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2118 * We have one bit per pipe and per scanout plane type.
2120 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2121 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2122 #define INTEL_FRONTBUFFER_BITS \
2123 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2124 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2125 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2126 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2127 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2128 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2129 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2130 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2131 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2132 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2133 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2135 struct drm_i915_gem_object
{
2136 struct drm_gem_object base
;
2138 const struct drm_i915_gem_object_ops
*ops
;
2140 /** List of VMAs backed by this object */
2141 struct list_head vma_list
;
2143 /** Stolen memory for this object, instead of being backed by shmem. */
2144 struct drm_mm_node
*stolen
;
2145 struct list_head global_list
;
2147 struct list_head engine_list
[I915_NUM_ENGINES
];
2148 /** Used in execbuf to temporarily hold a ref */
2149 struct list_head obj_exec_link
;
2151 struct list_head batch_pool_link
;
2154 * This is set if the object is on the active lists (has pending
2155 * rendering and so a non-zero seqno), and is not set if it i s on
2156 * inactive (ready to be unbound) list.
2158 unsigned int active
:I915_NUM_ENGINES
;
2161 * This is set if the object has been written to since last bound
2164 unsigned int dirty
:1;
2167 * Fence register bits (if any) for this object. Will be set
2168 * as needed when mapped into the GTT.
2169 * Protected by dev->struct_mutex.
2171 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
2174 * Advice: are the backing pages purgeable?
2176 unsigned int madv
:2;
2179 * Current tiling mode for the object.
2181 unsigned int tiling_mode
:2;
2183 * Whether the tiling parameters for the currently associated fence
2184 * register have changed. Note that for the purposes of tracking
2185 * tiling changes we also treat the unfenced register, the register
2186 * slot that the object occupies whilst it executes a fenced
2187 * command (such as BLT on gen2/3), as a "fence".
2189 unsigned int fence_dirty
:1;
2192 * Is the object at the current location in the gtt mappable and
2193 * fenceable? Used to avoid costly recalculations.
2195 unsigned int map_and_fenceable
:1;
2198 * Whether the current gtt mapping needs to be mappable (and isn't just
2199 * mappable by accident). Track pin and fault separate for a more
2200 * accurate mappable working set.
2202 unsigned int fault_mappable
:1;
2205 * Is the object to be mapped as read-only to the GPU
2206 * Only honoured if hardware has relevant pte bit
2208 unsigned long gt_ro
:1;
2209 unsigned int cache_level
:3;
2210 unsigned int cache_dirty
:1;
2212 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
2214 unsigned int pin_display
;
2216 struct sg_table
*pages
;
2217 int pages_pin_count
;
2219 struct scatterlist
*sg
;
2224 /** Breadcrumb of last rendering to the buffer.
2225 * There can only be one writer, but we allow for multiple readers.
2226 * If there is a writer that necessarily implies that all other
2227 * read requests are complete - but we may only be lazily clearing
2228 * the read requests. A read request is naturally the most recent
2229 * request on a ring, so we may have two different write and read
2230 * requests on one ring where the write request is older than the
2231 * read request. This allows for the CPU to read from an active
2232 * buffer by only waiting for the write to complete.
2234 struct drm_i915_gem_request
*last_read_req
[I915_NUM_ENGINES
];
2235 struct drm_i915_gem_request
*last_write_req
;
2236 /** Breadcrumb of last fenced GPU access to the buffer. */
2237 struct drm_i915_gem_request
*last_fenced_req
;
2239 /** Current tiling stride for the object, if it's tiled. */
2242 /** References from framebuffers, locks out tiling changes. */
2243 unsigned long framebuffer_references
;
2245 /** Record of address bit 17 of each page at last unbind. */
2246 unsigned long *bit_17
;
2249 /** for phy allocated objects */
2250 struct drm_dma_handle
*phys_handle
;
2252 struct i915_gem_userptr
{
2254 unsigned read_only
:1;
2255 unsigned workers
:4;
2256 #define I915_GEM_USERPTR_MAX_WORKERS 15
2258 struct i915_mm_struct
*mm
;
2259 struct i915_mmu_object
*mmu_object
;
2260 struct work_struct
*work
;
2264 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2267 * Optimised SGL iterator for GEM objects
2269 static __always_inline
struct sgt_iter
{
2270 struct scatterlist
*sgp
;
2277 } __sgt_iter(struct scatterlist
*sgl
, bool dma
) {
2278 struct sgt_iter s
= { .sgp
= sgl
};
2281 s
.max
= s
.curr
= s
.sgp
->offset
;
2282 s
.max
+= s
.sgp
->length
;
2284 s
.dma
= sg_dma_address(s
.sgp
);
2286 s
.pfn
= page_to_pfn(sg_page(s
.sgp
));
2293 * __sg_next - return the next scatterlist entry in a list
2294 * @sg: The current sg entry
2297 * If the entry is the last, return NULL; otherwise, step to the next
2298 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2299 * otherwise just return the pointer to the current element.
2301 static inline struct scatterlist
*__sg_next(struct scatterlist
*sg
)
2303 #ifdef CONFIG_DEBUG_SG
2304 BUG_ON(sg
->sg_magic
!= SG_MAGIC
);
2306 return sg_is_last(sg
) ? NULL
:
2307 likely(!sg_is_chain(++sg
)) ? sg
:
2312 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2313 * @__dmap: DMA address (output)
2314 * @__iter: 'struct sgt_iter' (iterator state, internal)
2315 * @__sgt: sg_table to iterate over (input)
2317 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2318 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2319 ((__dmap) = (__iter).dma + (__iter).curr); \
2320 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2321 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2324 * for_each_sgt_page - iterate over the pages of the given sg_table
2325 * @__pp: page pointer (output)
2326 * @__iter: 'struct sgt_iter' (iterator state, internal)
2327 * @__sgt: sg_table to iterate over (input)
2329 #define for_each_sgt_page(__pp, __iter, __sgt) \
2330 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2331 ((__pp) = (__iter).pfn == 0 ? NULL : \
2332 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2333 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2334 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2337 * Request queue structure.
2339 * The request queue allows us to note sequence numbers that have been emitted
2340 * and may be associated with active buffers to be retired.
2342 * By keeping this list, we can avoid having to do questionable sequence
2343 * number comparisons on buffer last_read|write_seqno. It also allows an
2344 * emission time to be associated with the request for tracking how far ahead
2345 * of the GPU the submission is.
2347 * The requests are reference counted, so upon creation they should have an
2348 * initial reference taken using kref_init
2350 struct drm_i915_gem_request
{
2353 /** On Which ring this request was generated */
2354 struct drm_i915_private
*i915
;
2355 struct intel_engine_cs
*engine
;
2356 unsigned reset_counter
;
2358 /** GEM sequence number associated with the previous request,
2359 * when the HWS breadcrumb is equal to this the GPU is processing
2364 /** GEM sequence number associated with this request,
2365 * when the HWS breadcrumb is equal or greater than this the GPU
2366 * has finished processing this request.
2370 /** Position in the ringbuffer of the start of the request */
2374 * Position in the ringbuffer of the start of the postfix.
2375 * This is required to calculate the maximum available ringbuffer
2376 * space without overwriting the postfix.
2380 /** Position in the ringbuffer of the end of the whole request */
2383 /** Preallocate space in the ringbuffer for the emitting the request */
2387 * Context and ring buffer related to this request
2388 * Contexts are refcounted, so when this request is associated with a
2389 * context, we must increment the context's refcount, to guarantee that
2390 * it persists while any request is linked to it. Requests themselves
2391 * are also refcounted, so the request will only be freed when the last
2392 * reference to it is dismissed, and the code in
2393 * i915_gem_request_free() will then decrement the refcount on the
2396 struct i915_gem_context
*ctx
;
2397 struct intel_ringbuffer
*ringbuf
;
2400 * Context related to the previous request.
2401 * As the contexts are accessed by the hardware until the switch is
2402 * completed to a new context, the hardware may still be writing
2403 * to the context object after the breadcrumb is visible. We must
2404 * not unpin/unbind/prune that object whilst still active and so
2405 * we keep the previous context pinned until the following (this)
2406 * request is retired.
2408 struct i915_gem_context
*previous_context
;
2410 /** Batch buffer related to this request if any (used for
2411 error state dump only) */
2412 struct drm_i915_gem_object
*batch_obj
;
2414 /** Time at which this request was emitted, in jiffies. */
2415 unsigned long emitted_jiffies
;
2417 /** global list entry for this request */
2418 struct list_head list
;
2420 struct drm_i915_file_private
*file_priv
;
2421 /** file_priv list entry for this request */
2422 struct list_head client_list
;
2424 /** process identifier submitting this request */
2428 * The ELSP only accepts two elements at a time, so we queue
2429 * context/tail pairs on a given queue (ring->execlist_queue) until the
2430 * hardware is available. The queue serves a double purpose: we also use
2431 * it to keep track of the up to 2 contexts currently in the hardware
2432 * (usually one in execution and the other queued up by the GPU): We
2433 * only remove elements from the head of the queue when the hardware
2434 * informs us that an element has been completed.
2436 * All accesses to the queue are mediated by a spinlock
2437 * (ring->execlist_lock).
2440 /** Execlist link in the submission queue.*/
2441 struct list_head execlist_link
;
2443 /** Execlists no. of times this request has been sent to the ELSP */
2446 /** Execlists context hardware id. */
2450 struct drm_i915_gem_request
* __must_check
2451 i915_gem_request_alloc(struct intel_engine_cs
*engine
,
2452 struct i915_gem_context
*ctx
);
2453 void i915_gem_request_free(struct kref
*req_ref
);
2454 int i915_gem_request_add_to_client(struct drm_i915_gem_request
*req
,
2455 struct drm_file
*file
);
2457 static inline uint32_t
2458 i915_gem_request_get_seqno(struct drm_i915_gem_request
*req
)
2460 return req
? req
->seqno
: 0;
2463 static inline struct intel_engine_cs
*
2464 i915_gem_request_get_engine(struct drm_i915_gem_request
*req
)
2466 return req
? req
->engine
: NULL
;
2469 static inline struct drm_i915_gem_request
*
2470 i915_gem_request_reference(struct drm_i915_gem_request
*req
)
2473 kref_get(&req
->ref
);
2478 i915_gem_request_unreference(struct drm_i915_gem_request
*req
)
2480 kref_put(&req
->ref
, i915_gem_request_free
);
2483 static inline void i915_gem_request_assign(struct drm_i915_gem_request
**pdst
,
2484 struct drm_i915_gem_request
*src
)
2487 i915_gem_request_reference(src
);
2490 i915_gem_request_unreference(*pdst
);
2496 * XXX: i915_gem_request_completed should be here but currently needs the
2497 * definition of i915_seqno_passed() which is below. It will be moved in
2498 * a later patch when the call to i915_seqno_passed() is obsoleted...
2502 * A command that requires special handling by the command parser.
2504 struct drm_i915_cmd_descriptor
{
2506 * Flags describing how the command parser processes the command.
2508 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2509 * a length mask if not set
2510 * CMD_DESC_SKIP: The command is allowed but does not follow the
2511 * standard length encoding for the opcode range in
2513 * CMD_DESC_REJECT: The command is never allowed
2514 * CMD_DESC_REGISTER: The command should be checked against the
2515 * register whitelist for the appropriate ring
2516 * CMD_DESC_MASTER: The command is allowed if the submitting process
2520 #define CMD_DESC_FIXED (1<<0)
2521 #define CMD_DESC_SKIP (1<<1)
2522 #define CMD_DESC_REJECT (1<<2)
2523 #define CMD_DESC_REGISTER (1<<3)
2524 #define CMD_DESC_BITMASK (1<<4)
2525 #define CMD_DESC_MASTER (1<<5)
2528 * The command's unique identification bits and the bitmask to get them.
2529 * This isn't strictly the opcode field as defined in the spec and may
2530 * also include type, subtype, and/or subop fields.
2538 * The command's length. The command is either fixed length (i.e. does
2539 * not include a length field) or has a length field mask. The flag
2540 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2541 * a length mask. All command entries in a command table must include
2542 * length information.
2550 * Describes where to find a register address in the command to check
2551 * against the ring's register whitelist. Only valid if flags has the
2552 * CMD_DESC_REGISTER bit set.
2554 * A non-zero step value implies that the command may access multiple
2555 * registers in sequence (e.g. LRI), in that case step gives the
2556 * distance in dwords between individual offset fields.
2564 #define MAX_CMD_DESC_BITMASKS 3
2566 * Describes command checks where a particular dword is masked and
2567 * compared against an expected value. If the command does not match
2568 * the expected value, the parser rejects it. Only valid if flags has
2569 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2572 * If the check specifies a non-zero condition_mask then the parser
2573 * only performs the check when the bits specified by condition_mask
2580 u32 condition_offset
;
2582 } bits
[MAX_CMD_DESC_BITMASKS
];
2586 * A table of commands requiring special handling by the command parser.
2588 * Each ring has an array of tables. Each table consists of an array of command
2589 * descriptors, which must be sorted with command opcodes in ascending order.
2591 struct drm_i915_cmd_table
{
2592 const struct drm_i915_cmd_descriptor
*table
;
2596 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2597 #define __I915__(p) ({ \
2598 struct drm_i915_private *__p; \
2599 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2600 __p = (struct drm_i915_private *)p; \
2601 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2602 __p = to_i915((struct drm_device *)p); \
2607 #define INTEL_INFO(p) (&__I915__(p)->info)
2608 #define INTEL_GEN(p) (INTEL_INFO(p)->gen)
2609 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2611 #define REVID_FOREVER 0xff
2612 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2614 #define GEN_FOREVER (0)
2616 * Returns true if Gen is in inclusive range [Start, End].
2618 * Use GEN_FOREVER for unbound start and or end.
2620 #define IS_GEN(p, s, e) ({ \
2621 unsigned int __s = (s), __e = (e); \
2622 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2623 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2624 if ((__s) != GEN_FOREVER) \
2626 if ((__e) == GEN_FOREVER) \
2627 __e = BITS_PER_LONG - 1; \
2630 !!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \
2634 * Return true if revision is in range [since,until] inclusive.
2636 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2638 #define IS_REVID(p, since, until) \
2639 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2641 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2642 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2643 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2644 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2645 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2646 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2647 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2648 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2649 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2650 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2651 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2652 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2653 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2654 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2655 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2656 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2657 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2658 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2659 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2660 INTEL_DEVID(dev) == 0x0152 || \
2661 INTEL_DEVID(dev) == 0x015a)
2662 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2663 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2664 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2665 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->is_broadwell)
2666 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2667 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2668 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2669 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2670 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2671 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2672 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2673 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2674 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2675 (INTEL_DEVID(dev) & 0xf) == 0xe))
2676 /* ULX machines are also considered ULT. */
2677 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2678 (INTEL_DEVID(dev) & 0xf) == 0xe)
2679 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2680 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2681 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2682 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2683 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2684 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2685 /* ULX machines are also considered ULT. */
2686 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2687 INTEL_DEVID(dev) == 0x0A1E)
2688 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2689 INTEL_DEVID(dev) == 0x1913 || \
2690 INTEL_DEVID(dev) == 0x1916 || \
2691 INTEL_DEVID(dev) == 0x1921 || \
2692 INTEL_DEVID(dev) == 0x1926)
2693 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2694 INTEL_DEVID(dev) == 0x1915 || \
2695 INTEL_DEVID(dev) == 0x191E)
2696 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2697 INTEL_DEVID(dev) == 0x5913 || \
2698 INTEL_DEVID(dev) == 0x5916 || \
2699 INTEL_DEVID(dev) == 0x5921 || \
2700 INTEL_DEVID(dev) == 0x5926)
2701 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2702 INTEL_DEVID(dev) == 0x5915 || \
2703 INTEL_DEVID(dev) == 0x591E)
2704 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2705 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2706 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2707 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2709 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2711 #define SKL_REVID_A0 0x0
2712 #define SKL_REVID_B0 0x1
2713 #define SKL_REVID_C0 0x2
2714 #define SKL_REVID_D0 0x3
2715 #define SKL_REVID_E0 0x4
2716 #define SKL_REVID_F0 0x5
2718 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2720 #define BXT_REVID_A0 0x0
2721 #define BXT_REVID_A1 0x1
2722 #define BXT_REVID_B0 0x3
2723 #define BXT_REVID_C0 0x9
2725 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2727 #define KBL_REVID_A0 0x0
2728 #define KBL_REVID_B0 0x1
2729 #define KBL_REVID_C0 0x2
2730 #define KBL_REVID_D0 0x3
2731 #define KBL_REVID_E0 0x4
2733 #define IS_KBL_REVID(p, since, until) \
2734 (IS_KABYLAKE(p) && IS_REVID(p, since, until))
2737 * The genX designation typically refers to the render engine, so render
2738 * capability related checks should use IS_GEN, while display and other checks
2739 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2742 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen_mask & BIT(1))
2743 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen_mask & BIT(2))
2744 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen_mask & BIT(3))
2745 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen_mask & BIT(4))
2746 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen_mask & BIT(5))
2747 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen_mask & BIT(6))
2748 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen_mask & BIT(7))
2749 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen_mask & BIT(8))
2751 #define RENDER_RING (1<<RCS)
2752 #define BSD_RING (1<<VCS)
2753 #define BLT_RING (1<<BCS)
2754 #define VEBOX_RING (1<<VECS)
2755 #define BSD2_RING (1<<VCS2)
2756 #define ALL_ENGINES (~0)
2758 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2759 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2760 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2761 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2762 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2763 #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
2764 #define HAS_EDRAM(dev) (__I915__(dev)->edram_cap & EDRAM_ENABLED)
2765 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2767 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2769 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2770 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2771 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2772 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2773 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2775 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2776 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2778 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2779 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2781 /* WaRsDisableCoarsePowerGating:skl,bxt */
2782 #define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \
2783 IS_SKL_GT3(dev) || \
2787 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2788 * even when in MSI mode. This results in spurious interrupt warnings if the
2789 * legacy irq no. is shared with another device. The kernel then disables that
2790 * interrupt source and so prevents the other device from working properly.
2792 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2793 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2795 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2796 * rows, which changed the alignment requirements and fence programming.
2798 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2800 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2801 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2803 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2804 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2805 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2807 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2809 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2810 INTEL_INFO(dev)->gen >= 9)
2812 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2813 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2814 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2815 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2816 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2817 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2818 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2819 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2820 IS_KABYLAKE(dev) || IS_BROXTON(dev))
2821 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2822 #define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
2824 #define HAS_CSR(dev) (IS_GEN9(dev))
2827 * For now, anything with a GuC requires uCode loading, and then supports
2828 * command submission once loaded. But these are logically independent
2829 * properties, so we have separate macros to test them.
2831 #define HAS_GUC(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2832 #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
2833 #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
2835 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2836 INTEL_INFO(dev)->gen >= 8)
2838 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2839 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2842 #define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu)
2844 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2845 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2846 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2847 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2848 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2849 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2850 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2851 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2852 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2853 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2854 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2856 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2857 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2858 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2859 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2860 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2861 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2862 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2863 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2864 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2866 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2867 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2869 /* DPF == dynamic parity feature */
2870 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2871 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2873 #define GT_FREQUENCY_MULTIPLIER 50
2874 #define GEN9_FREQ_SCALER 3
2876 #include "i915_trace.h"
2878 extern const struct drm_ioctl_desc i915_ioctls
[];
2879 extern int i915_max_ioctl
;
2881 extern int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
);
2882 extern int i915_resume_switcheroo(struct drm_device
*dev
);
2884 int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv
,
2889 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
2890 const char *fmt
, ...);
2892 #define i915_report_error(dev_priv, fmt, ...) \
2893 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2895 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
2896 extern int i915_driver_unload(struct drm_device
*);
2897 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
);
2898 extern void i915_driver_lastclose(struct drm_device
* dev
);
2899 extern void i915_driver_preclose(struct drm_device
*dev
,
2900 struct drm_file
*file
);
2901 extern void i915_driver_postclose(struct drm_device
*dev
,
2902 struct drm_file
*file
);
2903 #ifdef CONFIG_COMPAT
2904 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2907 extern int intel_gpu_reset(struct drm_i915_private
*dev_priv
, u32 engine_mask
);
2908 extern bool intel_has_gpu_reset(struct drm_i915_private
*dev_priv
);
2909 extern int i915_reset(struct drm_i915_private
*dev_priv
);
2910 extern int intel_guc_reset(struct drm_i915_private
*dev_priv
);
2911 extern void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
);
2912 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2913 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2914 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2915 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2916 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2918 /* intel_hotplug.c */
2919 void intel_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
2920 u32 pin_mask
, u32 long_mask
);
2921 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2922 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
2923 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2924 bool intel_hpd_pin_to_port(enum hpd_pin pin
, enum port
*port
);
2927 void i915_queue_hangcheck(struct drm_i915_private
*dev_priv
);
2929 void i915_handle_error(struct drm_i915_private
*dev_priv
,
2931 const char *fmt
, ...);
2933 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2934 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2935 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2937 extern void intel_uncore_sanitize(struct drm_i915_private
*dev_priv
);
2938 extern void intel_uncore_early_sanitize(struct drm_i915_private
*dev_priv
,
2939 bool restore_forcewake
);
2940 extern void intel_uncore_init(struct drm_i915_private
*dev_priv
);
2941 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private
*dev_priv
);
2942 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private
*dev_priv
);
2943 extern void intel_uncore_fini(struct drm_i915_private
*dev_priv
);
2944 extern void intel_uncore_forcewake_reset(struct drm_i915_private
*dev_priv
,
2946 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
2947 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
2948 enum forcewake_domains domains
);
2949 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
2950 enum forcewake_domains domains
);
2951 /* Like above but the caller must manage the uncore.lock itself.
2952 * Must be used with I915_READ_FW and friends.
2954 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
2955 enum forcewake_domains domains
);
2956 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
2957 enum forcewake_domains domains
);
2958 u64
intel_uncore_edram_size(struct drm_i915_private
*dev_priv
);
2960 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
2962 static inline bool intel_gvt_active(struct drm_i915_private
*dev_priv
)
2964 return dev_priv
->gvt
.initialized
;
2967 static inline bool intel_vgpu_active(struct drm_i915_private
*dev_priv
)
2969 return dev_priv
->vgpu
.active
;
2973 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2977 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2980 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2981 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2982 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
2985 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
2986 uint32_t interrupt_mask
,
2987 uint32_t enabled_irq_mask
);
2989 ilk_enable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2991 ilk_update_display_irq(dev_priv
, bits
, bits
);
2994 ilk_disable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2996 ilk_update_display_irq(dev_priv
, bits
, 0);
2998 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
3000 uint32_t interrupt_mask
,
3001 uint32_t enabled_irq_mask
);
3002 static inline void bdw_enable_pipe_irq(struct drm_i915_private
*dev_priv
,
3003 enum pipe pipe
, uint32_t bits
)
3005 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, bits
);
3007 static inline void bdw_disable_pipe_irq(struct drm_i915_private
*dev_priv
,
3008 enum pipe pipe
, uint32_t bits
)
3010 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, 0);
3012 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
3013 uint32_t interrupt_mask
,
3014 uint32_t enabled_irq_mask
);
3016 ibx_enable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3018 ibx_display_interrupt_update(dev_priv
, bits
, bits
);
3021 ibx_disable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3023 ibx_display_interrupt_update(dev_priv
, bits
, 0);
3028 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
3029 struct drm_file
*file_priv
);
3030 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
3031 struct drm_file
*file_priv
);
3032 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
3033 struct drm_file
*file_priv
);
3034 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
3035 struct drm_file
*file_priv
);
3036 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
3037 struct drm_file
*file_priv
);
3038 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
3039 struct drm_file
*file_priv
);
3040 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
3041 struct drm_file
*file_priv
);
3042 void i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
3043 struct drm_i915_gem_request
*req
);
3044 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params
*params
,
3045 struct drm_i915_gem_execbuffer2
*args
,
3046 struct list_head
*vmas
);
3047 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3048 struct drm_file
*file_priv
);
3049 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
3050 struct drm_file
*file_priv
);
3051 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3052 struct drm_file
*file_priv
);
3053 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3054 struct drm_file
*file
);
3055 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3056 struct drm_file
*file
);
3057 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3058 struct drm_file
*file_priv
);
3059 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3060 struct drm_file
*file_priv
);
3061 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
3062 struct drm_file
*file_priv
);
3063 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
3064 struct drm_file
*file_priv
);
3065 void i915_gem_init_userptr(struct drm_i915_private
*dev_priv
);
3066 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
3067 struct drm_file
*file
);
3068 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
3069 struct drm_file
*file_priv
);
3070 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
3071 struct drm_file
*file_priv
);
3072 void i915_gem_load_init(struct drm_device
*dev
);
3073 void i915_gem_load_cleanup(struct drm_device
*dev
);
3074 void i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
);
3075 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
);
3077 void *i915_gem_object_alloc(struct drm_device
*dev
);
3078 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
3079 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3080 const struct drm_i915_gem_object_ops
*ops
);
3081 struct drm_i915_gem_object
*i915_gem_object_create(struct drm_device
*dev
,
3083 struct drm_i915_gem_object
*i915_gem_object_create_from_data(
3084 struct drm_device
*dev
, const void *data
, size_t size
);
3085 void i915_gem_free_object(struct drm_gem_object
*obj
);
3086 void i915_gem_vma_destroy(struct i915_vma
*vma
);
3088 /* Flags used by pin/bind&friends. */
3089 #define PIN_MAPPABLE (1<<0)
3090 #define PIN_NONBLOCK (1<<1)
3091 #define PIN_GLOBAL (1<<2)
3092 #define PIN_OFFSET_BIAS (1<<3)
3093 #define PIN_USER (1<<4)
3094 #define PIN_UPDATE (1<<5)
3095 #define PIN_ZONE_4G (1<<6)
3096 #define PIN_HIGH (1<<7)
3097 #define PIN_OFFSET_FIXED (1<<8)
3098 #define PIN_OFFSET_MASK (~4095)
3100 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3101 struct i915_address_space
*vm
,
3105 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
3106 const struct i915_ggtt_view
*view
,
3110 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
3112 void __i915_vma_set_map_and_fenceable(struct i915_vma
*vma
);
3113 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
3115 * BEWARE: Do not use the function below unless you can _absolutely_
3116 * _guarantee_ VMA in question is _not in use_ anywhere.
3118 int __must_check
__i915_vma_unbind_no_wait(struct i915_vma
*vma
);
3119 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
3120 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
3121 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
3123 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
3124 int *needs_clflush
);
3126 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
3128 static inline int __sg_page_count(struct scatterlist
*sg
)
3130 return sg
->length
>> PAGE_SHIFT
;
3134 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
, int n
);
3136 static inline dma_addr_t
3137 i915_gem_object_get_dma_address(struct drm_i915_gem_object
*obj
, int n
)
3139 if (n
< obj
->get_page
.last
) {
3140 obj
->get_page
.sg
= obj
->pages
->sgl
;
3141 obj
->get_page
.last
= 0;
3144 while (obj
->get_page
.last
+ __sg_page_count(obj
->get_page
.sg
) <= n
) {
3145 obj
->get_page
.last
+= __sg_page_count(obj
->get_page
.sg
++);
3146 if (unlikely(sg_is_chain(obj
->get_page
.sg
)))
3147 obj
->get_page
.sg
= sg_chain_ptr(obj
->get_page
.sg
);
3150 return sg_dma_address(obj
->get_page
.sg
) + ((n
- obj
->get_page
.last
) << PAGE_SHIFT
);
3153 static inline struct page
*
3154 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
3156 if (WARN_ON(n
>= obj
->base
.size
>> PAGE_SHIFT
))
3159 if (n
< obj
->get_page
.last
) {
3160 obj
->get_page
.sg
= obj
->pages
->sgl
;
3161 obj
->get_page
.last
= 0;
3164 while (obj
->get_page
.last
+ __sg_page_count(obj
->get_page
.sg
) <= n
) {
3165 obj
->get_page
.last
+= __sg_page_count(obj
->get_page
.sg
++);
3166 if (unlikely(sg_is_chain(obj
->get_page
.sg
)))
3167 obj
->get_page
.sg
= sg_chain_ptr(obj
->get_page
.sg
);
3170 return nth_page(sg_page(obj
->get_page
.sg
), n
- obj
->get_page
.last
);
3173 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3175 BUG_ON(obj
->pages
== NULL
);
3176 obj
->pages_pin_count
++;
3179 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3181 BUG_ON(obj
->pages_pin_count
== 0);
3182 obj
->pages_pin_count
--;
3186 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3187 * @obj - the object to map into kernel address space
3189 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3190 * pages and then returns a contiguous mapping of the backing storage into
3191 * the kernel address space.
3193 * The caller must hold the struct_mutex, and is responsible for calling
3194 * i915_gem_object_unpin_map() when the mapping is no longer required.
3196 * Returns the pointer through which to access the mapped object, or an
3197 * ERR_PTR() on error.
3199 void *__must_check
i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
);
3202 * i915_gem_object_unpin_map - releases an earlier mapping
3203 * @obj - the object to unmap
3205 * After pinning the object and mapping its pages, once you are finished
3206 * with your access, call i915_gem_object_unpin_map() to release the pin
3207 * upon the mapping. Once the pin count reaches zero, that mapping may be
3210 * The caller must hold the struct_mutex.
3212 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object
*obj
)
3214 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3215 i915_gem_object_unpin_pages(obj
);
3218 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
3219 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3220 struct intel_engine_cs
*to
,
3221 struct drm_i915_gem_request
**to_req
);
3222 void i915_vma_move_to_active(struct i915_vma
*vma
,
3223 struct drm_i915_gem_request
*req
);
3224 int i915_gem_dumb_create(struct drm_file
*file_priv
,
3225 struct drm_device
*dev
,
3226 struct drm_mode_create_dumb
*args
);
3227 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
3228 uint32_t handle
, uint64_t *offset
);
3230 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
3231 struct drm_i915_gem_object
*new,
3232 unsigned frontbuffer_bits
);
3235 * Returns true if seq1 is later than seq2.
3238 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
3240 return (int32_t)(seq1
- seq2
) >= 0;
3243 static inline bool i915_gem_request_started(struct drm_i915_gem_request
*req
,
3244 bool lazy_coherency
)
3246 if (!lazy_coherency
&& req
->engine
->irq_seqno_barrier
)
3247 req
->engine
->irq_seqno_barrier(req
->engine
);
3248 return i915_seqno_passed(req
->engine
->get_seqno(req
->engine
),
3249 req
->previous_seqno
);
3252 static inline bool i915_gem_request_completed(struct drm_i915_gem_request
*req
,
3253 bool lazy_coherency
)
3255 if (!lazy_coherency
&& req
->engine
->irq_seqno_barrier
)
3256 req
->engine
->irq_seqno_barrier(req
->engine
);
3257 return i915_seqno_passed(req
->engine
->get_seqno(req
->engine
),
3261 int __must_check
i915_gem_get_seqno(struct drm_i915_private
*dev_priv
, u32
*seqno
);
3262 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
3264 struct drm_i915_gem_request
*
3265 i915_gem_find_active_request(struct intel_engine_cs
*engine
);
3267 bool i915_gem_retire_requests(struct drm_i915_private
*dev_priv
);
3268 void i915_gem_retire_requests_ring(struct intel_engine_cs
*engine
);
3270 static inline u32
i915_reset_counter(struct i915_gpu_error
*error
)
3272 return atomic_read(&error
->reset_counter
);
3275 static inline bool __i915_reset_in_progress(u32 reset
)
3277 return unlikely(reset
& I915_RESET_IN_PROGRESS_FLAG
);
3280 static inline bool __i915_reset_in_progress_or_wedged(u32 reset
)
3282 return unlikely(reset
& (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
3285 static inline bool __i915_terminally_wedged(u32 reset
)
3287 return unlikely(reset
& I915_WEDGED
);
3290 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
3292 return __i915_reset_in_progress(i915_reset_counter(error
));
3295 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error
*error
)
3297 return __i915_reset_in_progress_or_wedged(i915_reset_counter(error
));
3300 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
3302 return __i915_terminally_wedged(i915_reset_counter(error
));
3305 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
3307 return ((i915_reset_counter(error
) & ~I915_WEDGED
) + 1) / 2;
3310 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private
*dev_priv
)
3312 return dev_priv
->gpu_error
.stop_rings
== 0 ||
3313 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_BAN
;
3316 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private
*dev_priv
)
3318 return dev_priv
->gpu_error
.stop_rings
== 0 ||
3319 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_WARN
;
3322 void i915_gem_reset(struct drm_device
*dev
);
3323 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
3324 int __must_check
i915_gem_init(struct drm_device
*dev
);
3325 int i915_gem_init_engines(struct drm_device
*dev
);
3326 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
3327 void i915_gem_init_swizzling(struct drm_device
*dev
);
3328 void i915_gem_cleanup_engines(struct drm_device
*dev
);
3329 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
3330 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
3331 void __i915_add_request(struct drm_i915_gem_request
*req
,
3332 struct drm_i915_gem_object
*batch_obj
,
3334 #define i915_add_request(req) \
3335 __i915_add_request(req, NULL, true)
3336 #define i915_add_request_no_flush(req) \
3337 __i915_add_request(req, NULL, false)
3338 int __i915_wait_request(struct drm_i915_gem_request
*req
,
3341 struct intel_rps_client
*rps
);
3342 int __must_check
i915_wait_request(struct drm_i915_gem_request
*req
);
3343 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
3345 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
3348 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
3351 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
3353 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3355 const struct i915_ggtt_view
*view
);
3356 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
3357 const struct i915_ggtt_view
*view
);
3358 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
3360 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
3361 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3364 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
3366 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
3367 int tiling_mode
, bool fenced
);
3369 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3370 enum i915_cache_level cache_level
);
3372 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3373 struct dma_buf
*dma_buf
);
3375 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3376 struct drm_gem_object
*gem_obj
, int flags
);
3378 u64
i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
3379 const struct i915_ggtt_view
*view
);
3380 u64
i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
3381 struct i915_address_space
*vm
);
3383 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*o
)
3385 return i915_gem_obj_ggtt_offset_view(o
, &i915_ggtt_view_normal
);
3388 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
3389 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
3390 const struct i915_ggtt_view
*view
);
3391 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
3392 struct i915_address_space
*vm
);
3395 i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
3396 struct i915_address_space
*vm
);
3398 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
3399 const struct i915_ggtt_view
*view
);
3402 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3403 struct i915_address_space
*vm
);
3405 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
3406 const struct i915_ggtt_view
*view
);
3408 static inline struct i915_vma
*
3409 i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
)
3411 return i915_gem_obj_to_ggtt_view(obj
, &i915_ggtt_view_normal
);
3413 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
);
3415 /* Some GGTT VM helpers */
3416 static inline struct i915_hw_ppgtt
*
3417 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3419 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3423 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
3425 return i915_gem_obj_ggtt_bound_view(obj
, &i915_ggtt_view_normal
);
3429 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
);
3431 static inline int __must_check
3432 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
3436 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3437 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3439 return i915_gem_object_pin(obj
, &ggtt
->base
,
3440 alignment
, flags
| PIN_GLOBAL
);
3443 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
3444 const struct i915_ggtt_view
*view
);
3446 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
)
3448 i915_gem_object_ggtt_unpin_view(obj
, &i915_ggtt_view_normal
);
3451 /* i915_gem_fence.c */
3452 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
3453 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
3455 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
3456 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
3458 void i915_gem_restore_fences(struct drm_device
*dev
);
3460 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
3461 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3462 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3464 /* i915_gem_context.c */
3465 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
3466 void i915_gem_context_lost(struct drm_i915_private
*dev_priv
);
3467 void i915_gem_context_fini(struct drm_device
*dev
);
3468 void i915_gem_context_reset(struct drm_device
*dev
);
3469 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
3470 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
3471 int i915_switch_context(struct drm_i915_gem_request
*req
);
3472 void i915_gem_context_free(struct kref
*ctx_ref
);
3473 struct drm_i915_gem_object
*
3474 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
3476 static inline struct i915_gem_context
*
3477 i915_gem_context_lookup(struct drm_i915_file_private
*file_priv
, u32 id
)
3479 struct i915_gem_context
*ctx
;
3481 lockdep_assert_held(&file_priv
->dev_priv
->dev
->struct_mutex
);
3483 ctx
= idr_find(&file_priv
->context_idr
, id
);
3485 return ERR_PTR(-ENOENT
);
3490 static inline void i915_gem_context_reference(struct i915_gem_context
*ctx
)
3492 kref_get(&ctx
->ref
);
3495 static inline void i915_gem_context_unreference(struct i915_gem_context
*ctx
)
3497 lockdep_assert_held(&ctx
->i915
->dev
->struct_mutex
);
3498 kref_put(&ctx
->ref
, i915_gem_context_free
);
3501 static inline bool i915_gem_context_is_default(const struct i915_gem_context
*c
)
3503 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
3506 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
3507 struct drm_file
*file
);
3508 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
3509 struct drm_file
*file
);
3510 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
3511 struct drm_file
*file_priv
);
3512 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
3513 struct drm_file
*file_priv
);
3514 int i915_gem_context_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
3515 struct drm_file
*file
);
3517 /* i915_gem_evict.c */
3518 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
3519 struct i915_address_space
*vm
,
3522 unsigned cache_level
,
3523 unsigned long start
,
3526 int __must_check
i915_gem_evict_for_vma(struct i915_vma
*target
);
3527 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
3529 /* belongs in i915_gem_gtt.h */
3530 static inline void i915_gem_chipset_flush(struct drm_i915_private
*dev_priv
)
3532 if (INTEL_GEN(dev_priv
) < 6)
3533 intel_gtt_chipset_flush();
3536 /* i915_gem_stolen.c */
3537 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3538 struct drm_mm_node
*node
, u64 size
,
3539 unsigned alignment
);
3540 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private
*dev_priv
,
3541 struct drm_mm_node
*node
, u64 size
,
3542 unsigned alignment
, u64 start
,
3544 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3545 struct drm_mm_node
*node
);
3546 int i915_gem_init_stolen(struct drm_device
*dev
);
3547 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3548 struct drm_i915_gem_object
*
3549 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
3550 struct drm_i915_gem_object
*
3551 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
3556 /* i915_gem_shrinker.c */
3557 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3558 unsigned long target
,
3560 #define I915_SHRINK_PURGEABLE 0x1
3561 #define I915_SHRINK_UNBOUND 0x2
3562 #define I915_SHRINK_BOUND 0x4
3563 #define I915_SHRINK_ACTIVE 0x8
3564 #define I915_SHRINK_VMAPS 0x10
3565 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3566 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3567 void i915_gem_shrinker_cleanup(struct drm_i915_private
*dev_priv
);
3570 /* i915_gem_tiling.c */
3571 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3573 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3575 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3576 obj
->tiling_mode
!= I915_TILING_NONE
;
3579 /* i915_gem_debug.c */
3581 int i915_verify_lists(struct drm_device
*dev
);
3583 #define i915_verify_lists(dev) 0
3586 /* i915_debugfs.c */
3587 int i915_debugfs_init(struct drm_minor
*minor
);
3588 void i915_debugfs_cleanup(struct drm_minor
*minor
);
3589 #ifdef CONFIG_DEBUG_FS
3590 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3591 void intel_display_crc_init(struct drm_device
*dev
);
3593 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3595 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
3598 /* i915_gpu_error.c */
3600 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3601 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3602 const struct i915_error_state_file_priv
*error
);
3603 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3604 struct drm_i915_private
*i915
,
3605 size_t count
, loff_t pos
);
3606 static inline void i915_error_state_buf_release(
3607 struct drm_i915_error_state_buf
*eb
)
3611 void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3613 const char *error_msg
);
3614 void i915_error_state_get(struct drm_device
*dev
,
3615 struct i915_error_state_file_priv
*error_priv
);
3616 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
3617 void i915_destroy_error_state(struct drm_device
*dev
);
3619 void i915_get_extra_instdone(struct drm_i915_private
*dev_priv
, uint32_t *instdone
);
3620 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3622 /* i915_cmd_parser.c */
3623 int i915_cmd_parser_get_version(struct drm_i915_private
*dev_priv
);
3624 int i915_cmd_parser_init_ring(struct intel_engine_cs
*engine
);
3625 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*engine
);
3626 bool i915_needs_cmd_parser(struct intel_engine_cs
*engine
);
3627 int i915_parse_cmds(struct intel_engine_cs
*engine
,
3628 struct drm_i915_gem_object
*batch_obj
,
3629 struct drm_i915_gem_object
*shadow_batch_obj
,
3630 u32 batch_start_offset
,
3634 /* i915_suspend.c */
3635 extern int i915_save_state(struct drm_device
*dev
);
3636 extern int i915_restore_state(struct drm_device
*dev
);
3639 void i915_setup_sysfs(struct drm_device
*dev_priv
);
3640 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
3643 extern int intel_setup_gmbus(struct drm_device
*dev
);
3644 extern void intel_teardown_gmbus(struct drm_device
*dev
);
3645 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3648 extern struct i2c_adapter
*
3649 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3650 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3651 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3652 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3654 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3656 extern void intel_i2c_reset(struct drm_device
*dev
);
3659 int intel_bios_init(struct drm_i915_private
*dev_priv
);
3660 bool intel_bios_is_valid_vbt(const void *buf
, size_t size
);
3661 bool intel_bios_is_tv_present(struct drm_i915_private
*dev_priv
);
3662 bool intel_bios_is_lvds_present(struct drm_i915_private
*dev_priv
, u8
*i2c_pin
);
3663 bool intel_bios_is_port_present(struct drm_i915_private
*dev_priv
, enum port port
);
3664 bool intel_bios_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
3665 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private
*dev_priv
, enum port port
);
3666 bool intel_bios_is_dsi_present(struct drm_i915_private
*dev_priv
, enum port
*port
);
3667 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private
*dev_priv
,
3670 /* intel_opregion.c */
3672 extern int intel_opregion_setup(struct drm_i915_private
*dev_priv
);
3673 extern void intel_opregion_register(struct drm_i915_private
*dev_priv
);
3674 extern void intel_opregion_unregister(struct drm_i915_private
*dev_priv
);
3675 extern void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
);
3676 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3678 extern int intel_opregion_notify_adapter(struct drm_i915_private
*dev_priv
,
3680 extern int intel_opregion_get_panel_type(struct drm_i915_private
*dev_priv
);
3682 static inline int intel_opregion_setup(struct drm_i915_private
*dev
) { return 0; }
3683 static inline void intel_opregion_init(struct drm_i915_private
*dev
) { }
3684 static inline void intel_opregion_fini(struct drm_i915_private
*dev
) { }
3685 static inline void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
)
3689 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3694 intel_opregion_notify_adapter(struct drm_i915_private
*dev
, pci_power_t state
)
3698 static inline int intel_opregion_get_panel_type(struct drm_i915_private
*dev
)
3706 extern void intel_register_dsm_handler(void);
3707 extern void intel_unregister_dsm_handler(void);
3709 static inline void intel_register_dsm_handler(void) { return; }
3710 static inline void intel_unregister_dsm_handler(void) { return; }
3711 #endif /* CONFIG_ACPI */
3714 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3715 extern void intel_modeset_init(struct drm_device
*dev
);
3716 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3717 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3718 extern void intel_connector_unregister(struct intel_connector
*);
3719 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
3720 extern void intel_display_resume(struct drm_device
*dev
);
3721 extern void i915_redisable_vga(struct drm_device
*dev
);
3722 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
3723 extern bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
);
3724 extern void intel_init_pch_refclk(struct drm_device
*dev
);
3725 extern void intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
);
3726 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3728 extern void intel_detect_pch(struct drm_device
*dev
);
3730 extern bool i915_semaphore_is_enabled(struct drm_i915_private
*dev_priv
);
3731 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3732 struct drm_file
*file
);
3735 extern struct intel_overlay_error_state
*
3736 intel_overlay_capture_error_state(struct drm_i915_private
*dev_priv
);
3737 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3738 struct intel_overlay_error_state
*error
);
3740 extern struct intel_display_error_state
*
3741 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
);
3742 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3743 struct drm_device
*dev
,
3744 struct intel_display_error_state
*error
);
3746 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3747 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3749 /* intel_sideband.c */
3750 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3751 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3752 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3753 u32
vlv_iosf_sb_read(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
);
3754 void vlv_iosf_sb_write(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
, u32 val
);
3755 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3756 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3757 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3758 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3759 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3760 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3761 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3762 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3763 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3764 enum intel_sbi_destination destination
);
3765 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3766 enum intel_sbi_destination destination
);
3767 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3768 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3770 /* intel_dpio_phy.c */
3771 void chv_set_phy_signal_level(struct intel_encoder
*encoder
,
3772 u32 deemph_reg_value
, u32 margin_reg_value
,
3773 bool uniq_trans_scale
);
3774 void chv_data_lane_soft_reset(struct intel_encoder
*encoder
,
3776 void chv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3777 void chv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3778 void chv_phy_release_cl2_override(struct intel_encoder
*encoder
);
3779 void chv_phy_post_pll_disable(struct intel_encoder
*encoder
);
3781 void vlv_set_phy_signal_level(struct intel_encoder
*encoder
,
3782 u32 demph_reg_value
, u32 preemph_reg_value
,
3783 u32 uniqtranscale_reg_value
, u32 tx3_demph
);
3784 void vlv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3785 void vlv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3786 void vlv_phy_reset_lanes(struct intel_encoder
*encoder
);
3788 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3789 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3791 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3792 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3794 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3795 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3796 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3797 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3799 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3800 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3801 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3802 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3804 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3805 * will be implemented using 2 32-bit writes in an arbitrary order with
3806 * an arbitrary delay between them. This can cause the hardware to
3807 * act upon the intermediate value, possibly leading to corruption and
3808 * machine death. You have been warned.
3810 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3811 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3813 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3814 u32 upper, lower, old_upper, loop = 0; \
3815 upper = I915_READ(upper_reg); \
3817 old_upper = upper; \
3818 lower = I915_READ(lower_reg); \
3819 upper = I915_READ(upper_reg); \
3820 } while (upper != old_upper && loop++ < 2); \
3821 (u64)upper << 32 | lower; })
3823 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3824 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3826 #define __raw_read(x, s) \
3827 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3830 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3833 #define __raw_write(x, s) \
3834 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3835 i915_reg_t reg, uint##x##_t val) \
3837 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3852 /* These are untraced mmio-accessors that are only valid to be used inside
3853 * criticial sections inside IRQ handlers where forcewake is explicitly
3855 * Think twice, and think again, before using these.
3856 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3857 * intel_uncore_forcewake_irqunlock().
3859 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3860 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3861 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3863 /* "Broadcast RGB" property */
3864 #define INTEL_BROADCAST_RGB_AUTO 0
3865 #define INTEL_BROADCAST_RGB_FULL 1
3866 #define INTEL_BROADCAST_RGB_LIMITED 2
3868 static inline i915_reg_t
i915_vgacntrl_reg(struct drm_device
*dev
)
3870 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
3871 return VLV_VGACNTRL
;
3872 else if (INTEL_INFO(dev
)->gen
>= 5)
3873 return CPU_VGACNTRL
;
3878 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3880 unsigned long j
= msecs_to_jiffies(m
);
3882 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3885 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
3887 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
3890 static inline unsigned long
3891 timespec_to_jiffies_timeout(const struct timespec
*value
)
3893 unsigned long j
= timespec_to_jiffies(value
);
3895 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3899 * If you need to wait X milliseconds between events A and B, but event B
3900 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3901 * when event A happened, then just before event B you call this function and
3902 * pass the timestamp as the first argument, and X as the second argument.
3905 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3907 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3910 * Don't re-read the value of "jiffies" every time since it may change
3911 * behind our back and break the math.
3913 tmp_jiffies
= jiffies
;
3914 target_jiffies
= timestamp_jiffies
+
3915 msecs_to_jiffies_timeout(to_wait_ms
);
3917 if (time_after(target_jiffies
, tmp_jiffies
)) {
3918 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3919 while (remaining_jiffies
)
3921 schedule_timeout_uninterruptible(remaining_jiffies
);
3925 static inline void i915_trace_irq_get(struct intel_engine_cs
*engine
,
3926 struct drm_i915_gem_request
*req
)
3928 if (engine
->trace_irq_req
== NULL
&& engine
->irq_get(engine
))
3929 i915_gem_request_assign(&engine
->trace_irq_req
, req
);