drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include "i915_reg.h"
  34 #include "intel_bios.h"
  35 #include "intel_ringbuffer.h"
  36 #include <linux/io-mapping.h>
  37 #include <linux/i2c.h>
  38 #include <linux/i2c-algo-bit.h>
  39 #include <drm/intel-gtt.h>
  40 #include <linux/backlight.h>
  41 #include <linux/intel-iommu.h>
  42 #include <linux/kref.h>
  43
  44 /* General customization:
  45  */
  46
  47 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  48
  49 #define DRIVER_NAME             "i915"
  50 #define DRIVER_DESC             "Intel Graphics"
  51 #define DRIVER_DATE             "20080730"
  52
  53 enum pipe {
  54         PIPE_A = 0,
  55         PIPE_B,
  56         PIPE_C,
  57         I915_MAX_PIPES
  58 };
  59 #define pipe_name(p) ((p) + 'A')
  60
  61 enum transcoder {
  62         TRANSCODER_A = 0,
  63         TRANSCODER_B,
  64         TRANSCODER_C,
  65         TRANSCODER_EDP = 0xF,
  66 };
  67 #define transcoder_name(t) ((t) + 'A')
  68
  69 enum plane {
  70         PLANE_A = 0,
  71         PLANE_B,
  72         PLANE_C,
  73 };
  74 #define plane_name(p) ((p) + 'A')
  75
  76 enum port {
  77         PORT_A = 0,
  78         PORT_B,
  79         PORT_C,
  80         PORT_D,
  81         PORT_E,
  82         I915_MAX_PORTS
  83 };
  84 #define port_name(p) ((p) + 'A')
  85
  86 #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
  87
  88 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
  89
  90 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
  91         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
  92                 if ((intel_encoder)->base.crtc == (__crtc))
  93
  94 struct intel_pch_pll {
  95         int refcount; /* count of number of CRTCs sharing this PLL */
  96         int active; /* count of number of active CRTCs (i.e. DPMS on) */
  97         bool on; /* is the PLL actually active? Disabled during modeset */
  98         int pll_reg;
  99         int fp0_reg;
 100         int fp1_reg;
 101 };
 102 #define I915_NUM_PLLS 2
 103
 104 struct intel_ddi_plls {
 105         int spll_refcount;
 106         int wrpll1_refcount;
 107         int wrpll2_refcount;
 108 };
 109
 110 /* Interface history:
 111  *
 112  * 1.1: Original.
 113  * 1.2: Add Power Management
 114  * 1.3: Add vblank support
 115  * 1.4: Fix cmdbuffer path, add heap destroy
 116  * 1.5: Add vblank pipe configuration
 117  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 118  *      - Support vertical blank on secondary display pipe
 119  */
 120 #define DRIVER_MAJOR            1
 121 #define DRIVER_MINOR            6
 122 #define DRIVER_PATCHLEVEL       0
 123
 124 #define WATCH_COHERENCY 0
 125 #define WATCH_LISTS     0
 126 #define WATCH_GTT       0
 127
 128 #define I915_GEM_PHYS_CURSOR_0 1
 129 #define I915_GEM_PHYS_CURSOR_1 2
 130 #define I915_GEM_PHYS_OVERLAY_REGS 3
 131 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
 132
 133 struct drm_i915_gem_phys_object {
 134         int id;
 135         struct page **page_list;
 136         drm_dma_handle_t *handle;
 137         struct drm_i915_gem_object *cur_obj;
 138 };
 139
 140 struct opregion_header;
 141 struct opregion_acpi;
 142 struct opregion_swsci;
 143 struct opregion_asle;
 144 struct drm_i915_private;
 145
 146 struct intel_opregion {
 147         struct opregion_header __iomem *header;
 148         struct opregion_acpi __iomem *acpi;
 149         struct opregion_swsci __iomem *swsci;
 150         struct opregion_asle __iomem *asle;
 151         void __iomem *vbt;
 152         u32 __iomem *lid_state;
 153 };
 154 #define OPREGION_SIZE            (8*1024)
 155
 156 struct intel_overlay;
 157 struct intel_overlay_error_state;
 158
 159 struct drm_i915_master_private {
 160         drm_local_map_t *sarea;
 161         struct _drm_i915_sarea *sarea_priv;
 162 };
 163 #define I915_FENCE_REG_NONE -1
 164 #define I915_MAX_NUM_FENCES 16
 165 /* 16 fences + sign bit for FENCE_REG_NONE */
 166 #define I915_MAX_NUM_FENCE_BITS 5
 167
 168 struct drm_i915_fence_reg {
 169         struct list_head lru_list;
 170         struct drm_i915_gem_object *obj;
 171         int pin_count;
 172 };
 173
 174 struct sdvo_device_mapping {
 175         u8 initialized;
 176         u8 dvo_port;
 177         u8 slave_addr;
 178         u8 dvo_wiring;
 179         u8 i2c_pin;
 180         u8 ddc_pin;
 181 };
 182
 183 struct intel_display_error_state;
 184
 185 struct drm_i915_error_state {
 186         struct kref ref;
 187         u32 eir;
 188         u32 pgtbl_er;
 189         u32 ier;
 190         u32 ccid;
 191         bool waiting[I915_NUM_RINGS];
 192         u32 pipestat[I915_MAX_PIPES];
 193         u32 tail[I915_NUM_RINGS];
 194         u32 head[I915_NUM_RINGS];
 195         u32 ipeir[I915_NUM_RINGS];
 196         u32 ipehr[I915_NUM_RINGS];
 197         u32 instdone[I915_NUM_RINGS];
 198         u32 acthd[I915_NUM_RINGS];
 199         u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
 200         u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
 201         /* our own tracking of ring head and tail */
 202         u32 cpu_ring_head[I915_NUM_RINGS];
 203         u32 cpu_ring_tail[I915_NUM_RINGS];
 204         u32 error; /* gen6+ */
 205         u32 err_int; /* gen7 */
 206         u32 instpm[I915_NUM_RINGS];
 207         u32 instps[I915_NUM_RINGS];
 208         u32 extra_instdone[I915_NUM_INSTDONE_REG];
 209         u32 seqno[I915_NUM_RINGS];
 210         u64 bbaddr;
 211         u32 fault_reg[I915_NUM_RINGS];
 212         u32 done_reg;
 213         u32 faddr[I915_NUM_RINGS];
 214         u64 fence[I915_MAX_NUM_FENCES];
 215         struct timeval time;
 216         struct drm_i915_error_ring {
 217                 struct drm_i915_error_object {
 218                         int page_count;
 219                         u32 gtt_offset;
 220                         u32 *pages[0];
 221                 } *ringbuffer, *batchbuffer;
 222                 struct drm_i915_error_request {
 223                         long jiffies;
 224                         u32 seqno;
 225                         u32 tail;
 226                 } *requests;
 227                 int num_requests;
 228         } ring[I915_NUM_RINGS];
 229         struct drm_i915_error_buffer {
 230                 u32 size;
 231                 u32 name;
 232                 u32 rseqno, wseqno;
 233                 u32 gtt_offset;
 234                 u32 read_domains;
 235                 u32 write_domain;
 236                 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
 237                 s32 pinned:2;
 238                 u32 tiling:2;
 239                 u32 dirty:1;
 240                 u32 purgeable:1;
 241                 s32 ring:4;
 242                 u32 cache_level:2;
 243         } *active_bo, *pinned_bo;
 244         u32 active_bo_count, pinned_bo_count;
 245         struct intel_overlay_error_state *overlay;
 246         struct intel_display_error_state *display;
 247 };
 248
 249 struct drm_i915_display_funcs {
 250         bool (*fbc_enabled)(struct drm_device *dev);
 251         void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
 252         void (*disable_fbc)(struct drm_device *dev);
 253         int (*get_display_clock_speed)(struct drm_device *dev);
 254         int (*get_fifo_size)(struct drm_device *dev, int plane);
 255         void (*update_wm)(struct drm_device *dev);
 256         void (*update_sprite_wm)(struct drm_device *dev, int pipe,
 257                                  uint32_t sprite_width, int pixel_size);
 258         void (*update_linetime_wm)(struct drm_device *dev, int pipe,
 259                                  struct drm_display_mode *mode);
 260         void (*modeset_global_resources)(struct drm_device *dev);
 261         int (*crtc_mode_set)(struct drm_crtc *crtc,
 262                              struct drm_display_mode *mode,
 263                              struct drm_display_mode *adjusted_mode,
 264                              int x, int y,
 265                              struct drm_framebuffer *old_fb);
 266         void (*crtc_enable)(struct drm_crtc *crtc);
 267         void (*crtc_disable)(struct drm_crtc *crtc);
 268         void (*off)(struct drm_crtc *crtc);
 269         void (*write_eld)(struct drm_connector *connector,
 270                           struct drm_crtc *crtc);
 271         void (*fdi_link_train)(struct drm_crtc *crtc);
 272         void (*init_clock_gating)(struct drm_device *dev);
 273         int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
 274                           struct drm_framebuffer *fb,
 275                           struct drm_i915_gem_object *obj);
 276         int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 277                             int x, int y);
 278         /* clock updates for mode set */
 279         /* cursor updates */
 280         /* render clock increase/decrease */
 281         /* display clock increase/decrease */
 282         /* pll clock increase/decrease */
 283 };
 284
 285 struct drm_i915_gt_funcs {
 286         void (*force_wake_get)(struct drm_i915_private *dev_priv);
 287         void (*force_wake_put)(struct drm_i915_private *dev_priv);
 288 };
 289
 290 #define DEV_INFO_FLAGS \
 291         DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \
 292         DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \
 293         DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \
 294         DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \
 295         DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \
 296         DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \
 297         DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \
 298         DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \
 299         DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \
 300         DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \
 301         DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \
 302         DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \
 303         DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \
 304         DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \
 305         DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \
 306         DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \
 307         DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \
 308         DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \
 309         DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \
 310         DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \
 311         DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \
 312         DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \
 313         DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \
 314         DEV_INFO_FLAG(has_llc)
 315
 316 struct intel_device_info {
 317         u8 gen;
 318         u8 is_mobile:1;
 319         u8 is_i85x:1;
 320         u8 is_i915g:1;
 321         u8 is_i945gm:1;
 322         u8 is_g33:1;
 323         u8 need_gfx_hws:1;
 324         u8 is_g4x:1;
 325         u8 is_pineview:1;
 326         u8 is_broadwater:1;
 327         u8 is_crestline:1;
 328         u8 is_ivybridge:1;
 329         u8 is_valleyview:1;
 330         u8 has_force_wake:1;
 331         u8 is_haswell:1;
 332         u8 has_fbc:1;
 333         u8 has_pipe_cxsr:1;
 334         u8 has_hotplug:1;
 335         u8 cursor_needs_physical:1;
 336         u8 has_overlay:1;
 337         u8 overlay_needs_physical:1;
 338         u8 supports_tv:1;
 339         u8 has_bsd_ring:1;
 340         u8 has_blt_ring:1;
 341         u8 has_llc:1;
 342 };
 343
 344 #define I915_PPGTT_PD_ENTRIES 512
 345 #define I915_PPGTT_PT_ENTRIES 1024
 346 struct i915_hw_ppgtt {
 347         struct drm_device *dev;
 348         unsigned num_pd_entries;
 349         struct page **pt_pages;
 350         uint32_t pd_offset;
 351         dma_addr_t *pt_dma_addr;
 352         dma_addr_t scratch_page_dma_addr;
 353 };
 354
 355
 356 /* This must match up with the value previously used for execbuf2.rsvd1. */
 357 #define DEFAULT_CONTEXT_ID 0
 358 struct i915_hw_context {
 359         int id;
 360         bool is_initialized;
 361         struct drm_i915_file_private *file_priv;
 362         struct intel_ring_buffer *ring;
 363         struct drm_i915_gem_object *obj;
 364 };
 365
 366 enum no_fbc_reason {
 367         FBC_NO_OUTPUT, /* no outputs enabled to compress */
 368         FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
 369         FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
 370         FBC_MODE_TOO_LARGE, /* mode too large for compression */
 371         FBC_BAD_PLANE, /* fbc not supported on plane */
 372         FBC_NOT_TILED, /* buffer not tiled */
 373         FBC_MULTIPLE_PIPES, /* more than one pipe active */
 374         FBC_MODULE_PARAM,
 375 };
 376
 377 enum intel_pch {
 378         PCH_NONE = 0,   /* No PCH present */
 379         PCH_IBX,        /* Ibexpeak PCH */
 380         PCH_CPT,        /* Cougarpoint PCH */
 381         PCH_LPT,        /* Lynxpoint PCH */
 382 };
 383
 384 #define QUIRK_PIPEA_FORCE (1<<0)
 385 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 386 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
 387
 388 struct intel_fbdev;
 389 struct intel_fbc_work;
 390
 391 struct intel_gmbus {
 392         struct i2c_adapter adapter;
 393         bool force_bit;
 394         u32 reg0;
 395         u32 gpio_reg;
 396         struct i2c_algo_bit_data bit_algo;
 397         struct drm_i915_private *dev_priv;
 398 };
 399
 400 struct i915_suspend_saved_registers {
 401         u8 saveLBB;
 402         u32 saveDSPACNTR;
 403         u32 saveDSPBCNTR;
 404         u32 saveDSPARB;
 405         u32 saveHWS;
 406         u32 savePIPEACONF;
 407         u32 savePIPEBCONF;
 408         u32 savePIPEASRC;
 409         u32 savePIPEBSRC;
 410         u32 saveFPA0;
 411         u32 saveFPA1;
 412         u32 saveDPLL_A;
 413         u32 saveDPLL_A_MD;
 414         u32 saveHTOTAL_A;
 415         u32 saveHBLANK_A;
 416         u32 saveHSYNC_A;
 417         u32 saveVTOTAL_A;
 418         u32 saveVBLANK_A;
 419         u32 saveVSYNC_A;
 420         u32 saveBCLRPAT_A;
 421         u32 saveTRANSACONF;
 422         u32 saveTRANS_HTOTAL_A;
 423         u32 saveTRANS_HBLANK_A;
 424         u32 saveTRANS_HSYNC_A;
 425         u32 saveTRANS_VTOTAL_A;
 426         u32 saveTRANS_VBLANK_A;
 427         u32 saveTRANS_VSYNC_A;
 428         u32 savePIPEASTAT;
 429         u32 saveDSPASTRIDE;
 430         u32 saveDSPASIZE;
 431         u32 saveDSPAPOS;
 432         u32 saveDSPAADDR;
 433         u32 saveDSPASURF;
 434         u32 saveDSPATILEOFF;
 435         u32 savePFIT_PGM_RATIOS;
 436         u32 saveBLC_HIST_CTL;
 437         u32 saveBLC_PWM_CTL;
 438         u32 saveBLC_PWM_CTL2;
 439         u32 saveBLC_CPU_PWM_CTL;
 440         u32 saveBLC_CPU_PWM_CTL2;
 441         u32 saveFPB0;
 442         u32 saveFPB1;
 443         u32 saveDPLL_B;
 444         u32 saveDPLL_B_MD;
 445         u32 saveHTOTAL_B;
 446         u32 saveHBLANK_B;
 447         u32 saveHSYNC_B;
 448         u32 saveVTOTAL_B;
 449         u32 saveVBLANK_B;
 450         u32 saveVSYNC_B;
 451         u32 saveBCLRPAT_B;
 452         u32 saveTRANSBCONF;
 453         u32 saveTRANS_HTOTAL_B;
 454         u32 saveTRANS_HBLANK_B;
 455         u32 saveTRANS_HSYNC_B;
 456         u32 saveTRANS_VTOTAL_B;
 457         u32 saveTRANS_VBLANK_B;
 458         u32 saveTRANS_VSYNC_B;
 459         u32 savePIPEBSTAT;
 460         u32 saveDSPBSTRIDE;
 461         u32 saveDSPBSIZE;
 462         u32 saveDSPBPOS;
 463         u32 saveDSPBADDR;
 464         u32 saveDSPBSURF;
 465         u32 saveDSPBTILEOFF;
 466         u32 saveVGA0;
 467         u32 saveVGA1;
 468         u32 saveVGA_PD;
 469         u32 saveVGACNTRL;
 470         u32 saveADPA;
 471         u32 saveLVDS;
 472         u32 savePP_ON_DELAYS;
 473         u32 savePP_OFF_DELAYS;
 474         u32 saveDVOA;
 475         u32 saveDVOB;
 476         u32 saveDVOC;
 477         u32 savePP_ON;
 478         u32 savePP_OFF;
 479         u32 savePP_CONTROL;
 480         u32 savePP_DIVISOR;
 481         u32 savePFIT_CONTROL;
 482         u32 save_palette_a[256];
 483         u32 save_palette_b[256];
 484         u32 saveDPFC_CB_BASE;
 485         u32 saveFBC_CFB_BASE;
 486         u32 saveFBC_LL_BASE;
 487         u32 saveFBC_CONTROL;
 488         u32 saveFBC_CONTROL2;
 489         u32 saveIER;
 490         u32 saveIIR;
 491         u32 saveIMR;
 492         u32 saveDEIER;
 493         u32 saveDEIMR;
 494         u32 saveGTIER;
 495         u32 saveGTIMR;
 496         u32 saveFDI_RXA_IMR;
 497         u32 saveFDI_RXB_IMR;
 498         u32 saveCACHE_MODE_0;
 499         u32 saveMI_ARB_STATE;
 500         u32 saveSWF0[16];
 501         u32 saveSWF1[16];
 502         u32 saveSWF2[3];
 503         u8 saveMSR;
 504         u8 saveSR[8];
 505         u8 saveGR[25];
 506         u8 saveAR_INDEX;
 507         u8 saveAR[21];
 508         u8 saveDACMASK;
 509         u8 saveCR[37];
 510         uint64_t saveFENCE[I915_MAX_NUM_FENCES];
 511         u32 saveCURACNTR;
 512         u32 saveCURAPOS;
 513         u32 saveCURABASE;
 514         u32 saveCURBCNTR;
 515         u32 saveCURBPOS;
 516         u32 saveCURBBASE;
 517         u32 saveCURSIZE;
 518         u32 saveDP_B;
 519         u32 saveDP_C;
 520         u32 saveDP_D;
 521         u32 savePIPEA_GMCH_DATA_M;
 522         u32 savePIPEB_GMCH_DATA_M;
 523         u32 savePIPEA_GMCH_DATA_N;
 524         u32 savePIPEB_GMCH_DATA_N;
 525         u32 savePIPEA_DP_LINK_M;
 526         u32 savePIPEB_DP_LINK_M;
 527         u32 savePIPEA_DP_LINK_N;
 528         u32 savePIPEB_DP_LINK_N;
 529         u32 saveFDI_RXA_CTL;
 530         u32 saveFDI_TXA_CTL;
 531         u32 saveFDI_RXB_CTL;
 532         u32 saveFDI_TXB_CTL;
 533         u32 savePFA_CTL_1;
 534         u32 savePFB_CTL_1;
 535         u32 savePFA_WIN_SZ;
 536         u32 savePFB_WIN_SZ;
 537         u32 savePFA_WIN_POS;
 538         u32 savePFB_WIN_POS;
 539         u32 savePCH_DREF_CONTROL;
 540         u32 saveDISP_ARB_CTL;
 541         u32 savePIPEA_DATA_M1;
 542         u32 savePIPEA_DATA_N1;
 543         u32 savePIPEA_LINK_M1;
 544         u32 savePIPEA_LINK_N1;
 545         u32 savePIPEB_DATA_M1;
 546         u32 savePIPEB_DATA_N1;
 547         u32 savePIPEB_LINK_M1;
 548         u32 savePIPEB_LINK_N1;
 549         u32 saveMCHBAR_RENDER_STANDBY;
 550         u32 savePCH_PORT_HOTPLUG;
 551 };
 552
 553 struct intel_gen6_power_mgmt {
 554         struct work_struct work;
 555         u32 pm_iir;
 556         /* lock - irqsave spinlock that protectects the work_struct and
 557          * pm_iir. */
 558         spinlock_t lock;
 559
 560         /* The below variables an all the rps hw state are protected by
 561          * dev->struct mutext. */
 562         u8 cur_delay;
 563         u8 min_delay;
 564         u8 max_delay;
 565 };
 566
 567 struct intel_ilk_power_mgmt {
 568         u8 cur_delay;
 569         u8 min_delay;
 570         u8 max_delay;
 571         u8 fmax;
 572         u8 fstart;
 573
 574         u64 last_count1;
 575         unsigned long last_time1;
 576         unsigned long chipset_power;
 577         u64 last_count2;
 578         struct timespec last_time2;
 579         unsigned long gfx_power;
 580         u8 corr;
 581
 582         int c_m;
 583         int r_t;
 584 };
 585
 586 typedef struct drm_i915_private {
 587         struct drm_device *dev;
 588
 589         const struct intel_device_info *info;
 590
 591         int relative_constants_mode;
 592
 593         void __iomem *regs;
 594
 595         struct drm_i915_gt_funcs gt;
 596         /** gt_fifo_count and the subsequent register write are synchronized
 597          * with dev->struct_mutex. */
 598         unsigned gt_fifo_count;
 599         /** forcewake_count is protected by gt_lock */
 600         unsigned forcewake_count;
 601         /** gt_lock is also taken in irq contexts. */
 602         struct spinlock gt_lock;
 603
 604         struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
 605
 606         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
 607          * controller on different i2c buses. */
 608         struct mutex gmbus_mutex;
 609
 610         /**
 611          * Base address of the gmbus and gpio block.
 612          */
 613         uint32_t gpio_mmio_base;
 614
 615         struct pci_dev *bridge_dev;
 616         struct intel_ring_buffer ring[I915_NUM_RINGS];
 617         uint32_t next_seqno;
 618
 619         drm_dma_handle_t *status_page_dmah;
 620         uint32_t counter;
 621         struct drm_i915_gem_object *pwrctx;
 622         struct drm_i915_gem_object *renderctx;
 623
 624         struct resource mch_res;
 625
 626         atomic_t irq_received;
 627
 628         /* protects the irq masks */
 629         spinlock_t irq_lock;
 630
 631         /* DPIO indirect register protection */
 632         spinlock_t dpio_lock;
 633
 634         /** Cached value of IMR to avoid reads in updating the bitfield */
 635         u32 pipestat[2];
 636         u32 irq_mask;
 637         u32 gt_irq_mask;
 638         u32 pch_irq_mask;
 639
 640         u32 hotplug_supported_mask;
 641         struct work_struct hotplug_work;
 642
 643         int num_pipe;
 644         int num_pch_pll;
 645
 646         /* For hangcheck timer */
 647 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
 648 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
 649         struct timer_list hangcheck_timer;
 650         int hangcheck_count;
 651         uint32_t last_acthd[I915_NUM_RINGS];
 652         uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
 653
 654         unsigned int stop_rings;
 655
 656         unsigned long cfb_size;
 657         unsigned int cfb_fb;
 658         enum plane cfb_plane;
 659         int cfb_y;
 660         struct intel_fbc_work *fbc_work;
 661
 662         struct intel_opregion opregion;
 663
 664         /* overlay */
 665         struct intel_overlay *overlay;
 666         bool sprite_scaling_enabled;
 667
 668         /* LVDS info */
 669         int backlight_level;  /* restore backlight to this value */
 670         bool backlight_enabled;
 671         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 672         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
 673
 674         /* Feature bits from the VBIOS */
 675         unsigned int int_tv_support:1;
 676         unsigned int lvds_dither:1;
 677         unsigned int lvds_vbt:1;
 678         unsigned int int_crt_support:1;
 679         unsigned int lvds_use_ssc:1;
 680         unsigned int display_clock_mode:1;
 681         int lvds_ssc_freq;
 682         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
 683         unsigned int lvds_val; /* used for checking LVDS channel mode */
 684         struct {
 685                 int rate;
 686                 int lanes;
 687                 int preemphasis;
 688                 int vswing;
 689
 690                 bool initialized;
 691                 bool support;
 692                 int bpp;
 693                 struct edp_power_seq pps;
 694         } edp;
 695         bool no_aux_handshake;
 696
 697         int crt_ddc_pin;
 698         struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
 699         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
 700         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 701
 702         unsigned int fsb_freq, mem_freq, is_ddr3;
 703
 704         spinlock_t error_lock;
 705         /* Protected by dev->error_lock. */
 706         struct drm_i915_error_state *first_error;
 707         struct work_struct error_work;
 708         struct completion error_completion;
 709         struct workqueue_struct *wq;
 710
 711         /* Display functions */
 712         struct drm_i915_display_funcs display;
 713
 714         /* PCH chipset type */
 715         enum intel_pch pch_type;
 716
 717         unsigned long quirks;
 718
 719         /* Register state */
 720         bool modeset_on_lid;
 721
 722         struct {
 723                 /** Bridge to intel-gtt-ko */
 724                 const struct intel_gtt *gtt;
 725                 /** Memory allocator for GTT stolen memory */
 726                 struct drm_mm stolen;
 727                 /** Memory allocator for GTT */
 728                 struct drm_mm gtt_space;
 729                 /** List of all objects in gtt_space. Used to restore gtt
 730                  * mappings on resume */
 731                 struct list_head bound_list;
 732                 /**
 733                  * List of objects which are not bound to the GTT (thus
 734                  * are idle and not used by the GPU) but still have
 735                  * (presumably uncached) pages still attached.
 736                  */
 737                 struct list_head unbound_list;
 738
 739                 /** Usable portion of the GTT for GEM */
 740                 unsigned long gtt_start;
 741                 unsigned long gtt_mappable_end;
 742                 unsigned long gtt_end;
 743
 744                 struct io_mapping *gtt_mapping;
 745                 phys_addr_t gtt_base_addr;
 746                 int gtt_mtrr;
 747
 748                 /** PPGTT used for aliasing the PPGTT with the GTT */
 749                 struct i915_hw_ppgtt *aliasing_ppgtt;
 750
 751                 u32 *l3_remap_info;
 752
 753                 struct shrinker inactive_shrinker;
 754
 755                 /**
 756                  * List of objects currently involved in rendering.
 757                  *
 758                  * Includes buffers having the contents of their GPU caches
 759                  * flushed, not necessarily primitives.  last_rendering_seqno
 760                  * represents when the rendering involved will be completed.
 761                  *
 762                  * A reference is held on the buffer while on this list.
 763                  */
 764                 struct list_head active_list;
 765
 766                 /**
 767                  * LRU list of objects which are not in the ringbuffer and
 768                  * are ready to unbind, but are still in the GTT.
 769                  *
 770                  * last_rendering_seqno is 0 while an object is in this list.
 771                  *
 772                  * A reference is not held on the buffer while on this list,
 773                  * as merely being GTT-bound shouldn't prevent its being
 774                  * freed, and we'll pull it off the list in the free path.
 775                  */
 776                 struct list_head inactive_list;
 777
 778                 /** LRU list of objects with fence regs on them. */
 779                 struct list_head fence_list;
 780
 781                 /**
 782                  * We leave the user IRQ off as much as possible,
 783                  * but this means that requests will finish and never
 784                  * be retired once the system goes idle. Set a timer to
 785                  * fire periodically while the ring is running. When it
 786                  * fires, go retire requests.
 787                  */
 788                 struct delayed_work retire_work;
 789
 790                 /**
 791                  * Are we in a non-interruptible section of code like
 792                  * modesetting?
 793                  */
 794                 bool interruptible;
 795
 796                 /**
 797                  * Flag if the X Server, and thus DRM, is not currently in
 798                  * control of the device.
 799                  *
 800                  * This is set between LeaveVT and EnterVT.  It needs to be
 801                  * replaced with a semaphore.  It also needs to be
 802                  * transitioned away from for kernel modesetting.
 803                  */
 804                 int suspended;
 805
 806                 /**
 807                  * Flag if the hardware appears to be wedged.
 808                  *
 809                  * This is set when attempts to idle the device timeout.
 810                  * It prevents command submission from occurring and makes
 811                  * every pending request fail
 812                  */
 813                 atomic_t wedged;
 814
 815                 /** Bit 6 swizzling required for X tiling */
 816                 uint32_t bit_6_swizzle_x;
 817                 /** Bit 6 swizzling required for Y tiling */
 818                 uint32_t bit_6_swizzle_y;
 819
 820                 /* storage for physical objects */
 821                 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
 822
 823                 /* accounting, useful for userland debugging */
 824                 size_t gtt_total;
 825                 size_t mappable_gtt_total;
 826                 size_t object_memory;
 827                 u32 object_count;
 828         } mm;
 829
 830         /* Old dri1 support infrastructure, beware the dragons ya fools entering
 831          * here! */
 832         struct {
 833                 unsigned allow_batchbuffer : 1;
 834                 u32 __iomem *gfx_hws_cpu_addr;
 835
 836                 unsigned int cpp;
 837                 int back_offset;
 838                 int front_offset;
 839                 int current_page;
 840                 int page_flipping;
 841         } dri1;
 842
 843         /* Kernel Modesetting */
 844
 845         struct sdvo_device_mapping sdvo_mappings[2];
 846         /* indicate whether the LVDS_BORDER should be enabled or not */
 847         unsigned int lvds_border_bits;
 848         /* Panel fitter placement and size for Ironlake+ */
 849         u32 pch_pf_pos, pch_pf_size;
 850
 851         struct drm_crtc *plane_to_crtc_mapping[3];
 852         struct drm_crtc *pipe_to_crtc_mapping[3];
 853         wait_queue_head_t pending_flip_queue;
 854
 855         struct intel_pch_pll pch_plls[I915_NUM_PLLS];
 856         struct intel_ddi_plls ddi_plls;
 857
 858         /* Reclocking support */
 859         bool render_reclock_avail;
 860         bool lvds_downclock_avail;
 861         /* indicates the reduced downclock for LVDS*/
 862         int lvds_downclock;
 863         u16 orig_clock;
 864         int child_dev_num;
 865         struct child_device_config *child_dev;
 866
 867         bool mchbar_need_disable;
 868
 869         /* gen6+ rps state */
 870         struct intel_gen6_power_mgmt rps;
 871
 872         /* ilk-only ips/rps state. Everything in here is protected by the global
 873          * mchdev_lock in intel_pm.c */
 874         struct intel_ilk_power_mgmt ips;
 875
 876         enum no_fbc_reason no_fbc_reason;
 877
 878         struct drm_mm_node *compressed_fb;
 879         struct drm_mm_node *compressed_llb;
 880
 881         unsigned long last_gpu_reset;
 882
 883         /* list of fbdev register on this device */
 884         struct intel_fbdev *fbdev;
 885
 886         struct backlight_device *backlight;
 887
 888         struct drm_property *broadcast_rgb_property;
 889         struct drm_property *force_audio_property;
 890
 891         struct work_struct parity_error_work;
 892         bool hw_contexts_disabled;
 893         uint32_t hw_context_size;
 894
 895         struct i915_suspend_saved_registers regfile;
 896 } drm_i915_private_t;
 897
 898 /* Iterate over initialised rings */
 899 #define for_each_ring(ring__, dev_priv__, i__) \
 900         for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
 901                 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
 902
 903 enum hdmi_force_audio {
 904         HDMI_AUDIO_OFF_DVI = -2,        /* no aux data for HDMI-DVI converter */
 905         HDMI_AUDIO_OFF,                 /* force turn off HDMI audio */
 906         HDMI_AUDIO_AUTO,                /* trust EDID */
 907         HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
 908 };
 909
 910 enum i915_cache_level {
 911         I915_CACHE_NONE = 0,
 912         I915_CACHE_LLC,
 913         I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
 914 };
 915
 916 struct drm_i915_gem_object_ops {
 917         /* Interface between the GEM object and its backing storage.
 918          * get_pages() is called once prior to the use of the associated set
 919          * of pages before to binding them into the GTT, and put_pages() is
 920          * called after we no longer need them. As we expect there to be
 921          * associated cost with migrating pages between the backing storage
 922          * and making them available for the GPU (e.g. clflush), we may hold
 923          * onto the pages after they are no longer referenced by the GPU
 924          * in case they may be used again shortly (for example migrating the
 925          * pages to a different memory domain within the GTT). put_pages()
 926          * will therefore most likely be called when the object itself is
 927          * being released or under memory pressure (where we attempt to
 928          * reap pages for the shrinker).
 929          */
 930         int (*get_pages)(struct drm_i915_gem_object *);
 931         void (*put_pages)(struct drm_i915_gem_object *);
 932 };
 933
 934 struct drm_i915_gem_object {
 935         struct drm_gem_object base;
 936
 937         const struct drm_i915_gem_object_ops *ops;
 938
 939         /** Current space allocated to this object in the GTT, if any. */
 940         struct drm_mm_node *gtt_space;
 941         struct list_head gtt_list;
 942
 943         /** This object's place on the active/inactive lists */
 944         struct list_head ring_list;
 945         struct list_head mm_list;
 946         /** This object's place in the batchbuffer or on the eviction list */
 947         struct list_head exec_list;
 948
 949         /**
 950          * This is set if the object is on the active lists (has pending
 951          * rendering and so a non-zero seqno), and is not set if it i s on
 952          * inactive (ready to be unbound) list.
 953          */
 954         unsigned int active:1;
 955
 956         /**
 957          * This is set if the object has been written to since last bound
 958          * to the GTT
 959          */
 960         unsigned int dirty:1;
 961
 962         /**
 963          * Fence register bits (if any) for this object.  Will be set
 964          * as needed when mapped into the GTT.
 965          * Protected by dev->struct_mutex.
 966          */
 967         signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
 968
 969         /**
 970          * Advice: are the backing pages purgeable?
 971          */
 972         unsigned int madv:2;
 973
 974         /**
 975          * Current tiling mode for the object.
 976          */
 977         unsigned int tiling_mode:2;
 978         /**
 979          * Whether the tiling parameters for the currently associated fence
 980          * register have changed. Note that for the purposes of tracking
 981          * tiling changes we also treat the unfenced register, the register
 982          * slot that the object occupies whilst it executes a fenced
 983          * command (such as BLT on gen2/3), as a "fence".
 984          */
 985         unsigned int fence_dirty:1;
 986
 987         /** How many users have pinned this object in GTT space. The following
 988          * users can each hold at most one reference: pwrite/pread, pin_ioctl
 989          * (via user_pin_count), execbuffer (objects are not allowed multiple
 990          * times for the same batchbuffer), and the framebuffer code. When
 991          * switching/pageflipping, the framebuffer code has at most two buffers
 992          * pinned per crtc.
 993          *
 994          * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
 995          * bits with absolutely no headroom. So use 4 bits. */
 996         unsigned int pin_count:4;
 997 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
 998
 999         /**
1000          * Is the object at the current location in the gtt mappable and
1001          * fenceable? Used to avoid costly recalculations.
1002          */
1003         unsigned int map_and_fenceable:1;
1004
1005         /**
1006          * Whether the current gtt mapping needs to be mappable (and isn't just
1007          * mappable by accident). Track pin and fault separate for a more
1008          * accurate mappable working set.
1009          */
1010         unsigned int fault_mappable:1;
1011         unsigned int pin_mappable:1;
1012
1013         /*
1014          * Is the GPU currently using a fence to access this buffer,
1015          */
1016         unsigned int pending_fenced_gpu_access:1;
1017         unsigned int fenced_gpu_access:1;
1018
1019         unsigned int cache_level:2;
1020
1021         unsigned int has_aliasing_ppgtt_mapping:1;
1022         unsigned int has_global_gtt_mapping:1;
1023         unsigned int has_dma_mapping:1;
1024
1025         struct sg_table *pages;
1026         int pages_pin_count;
1027
1028         /* prime dma-buf support */
1029         void *dma_buf_vmapping;
1030         int vmapping_count;
1031
1032         /**
1033          * Used for performing relocations during execbuffer insertion.
1034          */
1035         struct hlist_node exec_node;
1036         unsigned long exec_handle;
1037         struct drm_i915_gem_exec_object2 *exec_entry;
1038
1039         /**
1040          * Current offset of the object in GTT space.
1041          *
1042          * This is the same as gtt_space->start
1043          */
1044         uint32_t gtt_offset;
1045
1046         struct intel_ring_buffer *ring;
1047
1048         /** Breadcrumb of last rendering to the buffer. */
1049         uint32_t last_read_seqno;
1050         uint32_t last_write_seqno;
1051         /** Breadcrumb of last fenced GPU access to the buffer. */
1052         uint32_t last_fenced_seqno;
1053
1054         /** Current tiling stride for the object, if it's tiled. */
1055         uint32_t stride;
1056
1057         /** Record of address bit 17 of each page at last unbind. */
1058         unsigned long *bit_17;
1059
1060         /** User space pin count and filp owning the pin */
1061         uint32_t user_pin_count;
1062         struct drm_file *pin_filp;
1063
1064         /** for phy allocated objects */
1065         struct drm_i915_gem_phys_object *phys_obj;
1066
1067         /**
1068          * Number of crtcs where this object is currently the fb, but
1069          * will be page flipped away on the next vblank.  When it
1070          * reaches 0, dev_priv->pending_flip_queue will be woken up.
1071          */
1072         atomic_t pending_flip;
1073 };
1074
1075 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1076
1077 /**
1078  * Request queue structure.
1079  *
1080  * The request queue allows us to note sequence numbers that have been emitted
1081  * and may be associated with active buffers to be retired.
1082  *
1083  * By keeping this list, we can avoid having to do questionable
1084  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1085  * an emission time with seqnos for tracking how far ahead of the GPU we are.
1086  */
1087 struct drm_i915_gem_request {
1088         /** On Which ring this request was generated */
1089         struct intel_ring_buffer *ring;
1090
1091         /** GEM sequence number associated with this request. */
1092         uint32_t seqno;
1093
1094         /** Postion in the ringbuffer of the end of the request */
1095         u32 tail;
1096
1097         /** Time at which this request was emitted, in jiffies. */
1098         unsigned long emitted_jiffies;
1099
1100         /** global list entry for this request */
1101         struct list_head list;
1102
1103         struct drm_i915_file_private *file_priv;
1104         /** file_priv list entry for this request */
1105         struct list_head client_list;
1106 };
1107
1108 struct drm_i915_file_private {
1109         struct {
1110                 struct spinlock lock;
1111                 struct list_head request_list;
1112         } mm;
1113         struct idr context_idr;
1114 };
1115
1116 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1117
1118 #define IS_I830(dev)            ((dev)->pci_device == 0x3577)
1119 #define IS_845G(dev)            ((dev)->pci_device == 0x2562)
1120 #define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
1121 #define IS_I865G(dev)           ((dev)->pci_device == 0x2572)
1122 #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
1123 #define IS_I915GM(dev)          ((dev)->pci_device == 0x2592)
1124 #define IS_I945G(dev)           ((dev)->pci_device == 0x2772)
1125 #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
1126 #define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
1127 #define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
1128 #define IS_GM45(dev)            ((dev)->pci_device == 0x2A42)
1129 #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
1130 #define IS_PINEVIEW_G(dev)      ((dev)->pci_device == 0xa001)
1131 #define IS_PINEVIEW_M(dev)      ((dev)->pci_device == 0xa011)
1132 #define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
1133 #define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
1134 #define IS_IRONLAKE_D(dev)      ((dev)->pci_device == 0x0042)
1135 #define IS_IRONLAKE_M(dev)      ((dev)->pci_device == 0x0046)
1136 #define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)
1137 #define IS_IVB_GT1(dev)         ((dev)->pci_device == 0x0156 || \
1138                                  (dev)->pci_device == 0x0152 || \
1139                                  (dev)->pci_device == 0x015a)
1140 #define IS_VALLEYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview)
1141 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1142 #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
1143
1144 /*
1145  * The genX designation typically refers to the render engine, so render
1146  * capability related checks should use IS_GEN, while display and other checks
1147  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1148  * chips, etc.).
1149  */
1150 #define IS_GEN2(dev)    (INTEL_INFO(dev)->gen == 2)
1151 #define IS_GEN3(dev)    (INTEL_INFO(dev)->gen == 3)
1152 #define IS_GEN4(dev)    (INTEL_INFO(dev)->gen == 4)
1153 #define IS_GEN5(dev)    (INTEL_INFO(dev)->gen == 5)
1154 #define IS_GEN6(dev)    (INTEL_INFO(dev)->gen == 6)
1155 #define IS_GEN7(dev)    (INTEL_INFO(dev)->gen == 7)
1156
1157 #define HAS_BSD(dev)            (INTEL_INFO(dev)->has_bsd_ring)
1158 #define HAS_BLT(dev)            (INTEL_INFO(dev)->has_blt_ring)
1159 #define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
1160 #define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
1161
1162 #define HAS_HW_CONTEXTS(dev)    (INTEL_INFO(dev)->gen >= 6)
1163 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1164
1165 #define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
1166 #define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
1167
1168 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1169  * rows, which changed the alignment requirements and fence programming.
1170  */
1171 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1172                                                       IS_I915GM(dev)))
1173 #define SUPPORTS_DIGITAL_OUTPUTS(dev)   (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1174 #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_GEN5(dev))
1175 #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_GEN5(dev))
1176 #define SUPPORTS_EDP(dev)               (IS_IRONLAKE_M(dev))
1177 #define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)
1178 #define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
1179 /* dsparb controlled by hw only */
1180 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1181
1182 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1183 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1184 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1185
1186 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1187
1188 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1189 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1190 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1191 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1192 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1193
1194 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1195
1196 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1197
1198 #define GT_FREQUENCY_MULTIPLIER 50
1199
1200 #include "i915_trace.h"
1201
1202 /**
1203  * RC6 is a special power stage which allows the GPU to enter an very
1204  * low-voltage mode when idle, using down to 0V while at this stage.  This
1205  * stage is entered automatically when the GPU is idle when RC6 support is
1206  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1207  *
1208  * There are different RC6 modes available in Intel GPU, which differentiate
1209  * among each other with the latency required to enter and leave RC6 and
1210  * voltage consumed by the GPU in different states.
1211  *
1212  * The combination of the following flags define which states GPU is allowed
1213  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1214  * RC6pp is deepest RC6. Their support by hardware varies according to the
1215  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1216  * which brings the most power savings; deeper states save more power, but
1217  * require higher latency to switch to and wake up.
1218  */
1219 #define INTEL_RC6_ENABLE                        (1<<0)
1220 #define INTEL_RC6p_ENABLE                       (1<<1)
1221 #define INTEL_RC6pp_ENABLE                      (1<<2)
1222
1223 extern struct drm_ioctl_desc i915_ioctls[];
1224 extern int i915_max_ioctl;
1225 extern unsigned int i915_fbpercrtc __always_unused;
1226 extern int i915_panel_ignore_lid __read_mostly;
1227 extern unsigned int i915_powersave __read_mostly;
1228 extern int i915_semaphores __read_mostly;
1229 extern unsigned int i915_lvds_downclock __read_mostly;
1230 extern int i915_lvds_channel_mode __read_mostly;
1231 extern int i915_panel_use_ssc __read_mostly;
1232 extern int i915_vbt_sdvo_panel_type __read_mostly;
1233 extern int i915_enable_rc6 __read_mostly;
1234 extern int i915_enable_fbc __read_mostly;
1235 extern bool i915_enable_hangcheck __read_mostly;
1236 extern int i915_enable_ppgtt __read_mostly;
1237
1238 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1239 extern int i915_resume(struct drm_device *dev);
1240 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1241 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1242
1243                                 /* i915_dma.c */
1244 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1245 extern void i915_kernel_lost_context(struct drm_device * dev);
1246 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1247 extern int i915_driver_unload(struct drm_device *);
1248 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1249 extern void i915_driver_lastclose(struct drm_device * dev);
1250 extern void i915_driver_preclose(struct drm_device *dev,
1251                                  struct drm_file *file_priv);
1252 extern void i915_driver_postclose(struct drm_device *dev,
1253                                   struct drm_file *file_priv);
1254 extern int i915_driver_device_is_agp(struct drm_device * dev);
1255 #ifdef CONFIG_COMPAT
1256 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1257                               unsigned long arg);
1258 #endif
1259 extern int i915_emit_box(struct drm_device *dev,
1260                          struct drm_clip_rect *box,
1261                          int DR1, int DR4);
1262 extern int intel_gpu_reset(struct drm_device *dev);
1263 extern int i915_reset(struct drm_device *dev);
1264 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1265 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1266 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1267 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1268
1269
1270 /* i915_irq.c */
1271 void i915_hangcheck_elapsed(unsigned long data);
1272 void i915_handle_error(struct drm_device *dev, bool wedged);
1273
1274 extern void intel_irq_init(struct drm_device *dev);
1275 extern void intel_gt_init(struct drm_device *dev);
1276 extern void intel_gt_reset(struct drm_device *dev);
1277
1278 void i915_error_state_free(struct kref *error_ref);
1279
1280 void
1281 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1282
1283 void
1284 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1285
1286 void intel_enable_asle(struct drm_device *dev);
1287
1288 #ifdef CONFIG_DEBUG_FS
1289 extern void i915_destroy_error_state(struct drm_device *dev);
1290 #else
1291 #define i915_destroy_error_state(x)
1292 #endif
1293
1294
1295 /* i915_gem.c */
1296 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1297                         struct drm_file *file_priv);
1298 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1299                           struct drm_file *file_priv);
1300 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1301                          struct drm_file *file_priv);
1302 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1303                           struct drm_file *file_priv);
1304 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1305                         struct drm_file *file_priv);
1306 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1307                         struct drm_file *file_priv);
1308 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1309                               struct drm_file *file_priv);
1310 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1311                              struct drm_file *file_priv);
1312 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1313                         struct drm_file *file_priv);
1314 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1315                          struct drm_file *file_priv);
1316 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1317                        struct drm_file *file_priv);
1318 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1319                          struct drm_file *file_priv);
1320 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1321                         struct drm_file *file_priv);
1322 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1323                                struct drm_file *file);
1324 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1325                                struct drm_file *file);
1326 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1327                             struct drm_file *file_priv);
1328 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1329                            struct drm_file *file_priv);
1330 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1331                            struct drm_file *file_priv);
1332 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1333                            struct drm_file *file_priv);
1334 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1335                         struct drm_file *file_priv);
1336 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1337                         struct drm_file *file_priv);
1338 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1339                                 struct drm_file *file_priv);
1340 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1341                         struct drm_file *file_priv);
1342 void i915_gem_load(struct drm_device *dev);
1343 int i915_gem_init_object(struct drm_gem_object *obj);
1344 void i915_gem_object_init(struct drm_i915_gem_object *obj,
1345                          const struct drm_i915_gem_object_ops *ops);
1346 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1347                                                   size_t size);
1348 void i915_gem_free_object(struct drm_gem_object *obj);
1349 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1350                                      uint32_t alignment,
1351                                      bool map_and_fenceable,
1352                                      bool nonblocking);
1353 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1354 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1355 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1356 void i915_gem_lastclose(struct drm_device *dev);
1357
1358 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
1359 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
1360 {
1361         struct scatterlist *sg = obj->pages->sgl;
1362         int nents = obj->pages->nents;
1363         while (nents > SG_MAX_SINGLE_ALLOC) {
1364                 if (n < SG_MAX_SINGLE_ALLOC - 1)
1365                         break;
1366
1367                 sg = sg_chain_ptr(sg + SG_MAX_SINGLE_ALLOC - 1);
1368                 n -= SG_MAX_SINGLE_ALLOC - 1;
1369                 nents -= SG_MAX_SINGLE_ALLOC - 1;
1370         }
1371         return sg_page(sg+n);
1372 }
1373 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
1374 {
1375         BUG_ON(obj->pages == NULL);
1376         obj->pages_pin_count++;
1377 }
1378 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
1379 {
1380         BUG_ON(obj->pages_pin_count == 0);
1381         obj->pages_pin_count--;
1382 }
1383
1384 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1385 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1386                          struct intel_ring_buffer *to);
1387 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1388                                     struct intel_ring_buffer *ring,
1389                                     u32 seqno);
1390
1391 int i915_gem_dumb_create(struct drm_file *file_priv,
1392                          struct drm_device *dev,
1393                          struct drm_mode_create_dumb *args);
1394 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1395                       uint32_t handle, uint64_t *offset);
1396 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1397                           uint32_t handle);
1398 /**
1399  * Returns true if seq1 is later than seq2.
1400  */
1401 static inline bool
1402 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1403 {
1404         return (int32_t)(seq1 - seq2) >= 0;
1405 }
1406
1407 u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring);
1408
1409 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1410 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1411
1412 static inline bool
1413 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1414 {
1415         if (obj->fence_reg != I915_FENCE_REG_NONE) {
1416                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1417                 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1418                 return true;
1419         } else
1420                 return false;
1421 }
1422
1423 static inline void
1424 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1425 {
1426         if (obj->fence_reg != I915_FENCE_REG_NONE) {
1427                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1428                 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1429         }
1430 }
1431
1432 void i915_gem_retire_requests(struct drm_device *dev);
1433 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1434 int __must_check i915_gem_check_wedge(struct drm_i915_private *dev_priv,
1435                                       bool interruptible);
1436
1437 void i915_gem_reset(struct drm_device *dev);
1438 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1439 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1440                                             uint32_t read_domains,
1441                                             uint32_t write_domain);
1442 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1443 int __must_check i915_gem_init(struct drm_device *dev);
1444 int __must_check i915_gem_init_hw(struct drm_device *dev);
1445 void i915_gem_l3_remap(struct drm_device *dev);
1446 void i915_gem_init_swizzling(struct drm_device *dev);
1447 void i915_gem_init_ppgtt(struct drm_device *dev);
1448 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1449 int __must_check i915_gpu_idle(struct drm_device *dev);
1450 int __must_check i915_gem_idle(struct drm_device *dev);
1451 int i915_add_request(struct intel_ring_buffer *ring,
1452                      struct drm_file *file,
1453                      u32 *seqno);
1454 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1455                                  uint32_t seqno);
1456 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1457 int __must_check
1458 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1459                                   bool write);
1460 int __must_check
1461 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1462 int __must_check
1463 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1464                                      u32 alignment,
1465                                      struct intel_ring_buffer *pipelined);
1466 int i915_gem_attach_phys_object(struct drm_device *dev,
1467                                 struct drm_i915_gem_object *obj,
1468                                 int id,
1469                                 int align);
1470 void i915_gem_detach_phys_object(struct drm_device *dev,
1471                                  struct drm_i915_gem_object *obj);
1472 void i915_gem_free_all_phys_object(struct drm_device *dev);
1473 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1474
1475 uint32_t
1476 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1477                                     uint32_t size,
1478                                     int tiling_mode);
1479
1480 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1481                                     enum i915_cache_level cache_level);
1482
1483 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1484                                 struct dma_buf *dma_buf);
1485
1486 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1487                                 struct drm_gem_object *gem_obj, int flags);
1488
1489 /* i915_gem_context.c */
1490 void i915_gem_context_init(struct drm_device *dev);
1491 void i915_gem_context_fini(struct drm_device *dev);
1492 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
1493 int i915_switch_context(struct intel_ring_buffer *ring,
1494                         struct drm_file *file, int to_id);
1495 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1496                                   struct drm_file *file);
1497 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1498                                    struct drm_file *file);
1499
1500 /* i915_gem_gtt.c */
1501 int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
1502 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1503 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1504                             struct drm_i915_gem_object *obj,
1505                             enum i915_cache_level cache_level);
1506 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1507                               struct drm_i915_gem_object *obj);
1508
1509 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1510 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1511 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1512                                 enum i915_cache_level cache_level);
1513 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1514 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1515 void i915_gem_init_global_gtt(struct drm_device *dev,
1516                               unsigned long start,
1517                               unsigned long mappable_end,
1518                               unsigned long end);
1519
1520 /* i915_gem_evict.c */
1521 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1522                                           unsigned alignment,
1523                                           unsigned cache_level,
1524                                           bool mappable,
1525                                           bool nonblock);
1526 int i915_gem_evict_everything(struct drm_device *dev);
1527
1528 /* i915_gem_stolen.c */
1529 int i915_gem_init_stolen(struct drm_device *dev);
1530 void i915_gem_cleanup_stolen(struct drm_device *dev);
1531
1532 /* i915_gem_tiling.c */
1533 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1534 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1535 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1536
1537 /* i915_gem_debug.c */
1538 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1539                           const char *where, uint32_t mark);
1540 #if WATCH_LISTS
1541 int i915_verify_lists(struct drm_device *dev);
1542 #else
1543 #define i915_verify_lists(dev) 0
1544 #endif
1545 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1546                                      int handle);
1547 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1548                           const char *where, uint32_t mark);
1549
1550 /* i915_debugfs.c */
1551 int i915_debugfs_init(struct drm_minor *minor);
1552 void i915_debugfs_cleanup(struct drm_minor *minor);
1553
1554 /* i915_suspend.c */
1555 extern int i915_save_state(struct drm_device *dev);
1556 extern int i915_restore_state(struct drm_device *dev);
1557
1558 /* i915_suspend.c */
1559 extern int i915_save_state(struct drm_device *dev);
1560 extern int i915_restore_state(struct drm_device *dev);
1561
1562 /* i915_sysfs.c */
1563 void i915_setup_sysfs(struct drm_device *dev_priv);
1564 void i915_teardown_sysfs(struct drm_device *dev_priv);
1565
1566 /* intel_i2c.c */
1567 extern int intel_setup_gmbus(struct drm_device *dev);
1568 extern void intel_teardown_gmbus(struct drm_device *dev);
1569 extern inline bool intel_gmbus_is_port_valid(unsigned port)
1570 {
1571         return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1572 }
1573
1574 extern struct i2c_adapter *intel_gmbus_get_adapter(
1575                 struct drm_i915_private *dev_priv, unsigned port);
1576 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1577 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1578 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1579 {
1580         return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1581 }
1582 extern void intel_i2c_reset(struct drm_device *dev);
1583
1584 /* intel_opregion.c */
1585 extern int intel_opregion_setup(struct drm_device *dev);
1586 #ifdef CONFIG_ACPI
1587 extern void intel_opregion_init(struct drm_device *dev);
1588 extern void intel_opregion_fini(struct drm_device *dev);
1589 extern void intel_opregion_asle_intr(struct drm_device *dev);
1590 extern void intel_opregion_gse_intr(struct drm_device *dev);
1591 extern void intel_opregion_enable_asle(struct drm_device *dev);
1592 #else
1593 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1594 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1595 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1596 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1597 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1598 #endif
1599
1600 /* intel_acpi.c */
1601 #ifdef CONFIG_ACPI
1602 extern void intel_register_dsm_handler(void);
1603 extern void intel_unregister_dsm_handler(void);
1604 #else
1605 static inline void intel_register_dsm_handler(void) { return; }
1606 static inline void intel_unregister_dsm_handler(void) { return; }
1607 #endif /* CONFIG_ACPI */
1608
1609 /* modesetting */
1610 extern void intel_modeset_init_hw(struct drm_device *dev);
1611 extern void intel_modeset_init(struct drm_device *dev);
1612 extern void intel_modeset_gem_init(struct drm_device *dev);
1613 extern void intel_modeset_cleanup(struct drm_device *dev);
1614 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1615 extern void intel_modeset_setup_hw_state(struct drm_device *dev);
1616 extern bool intel_fbc_enabled(struct drm_device *dev);
1617 extern void intel_disable_fbc(struct drm_device *dev);
1618 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1619 extern void ironlake_init_pch_refclk(struct drm_device *dev);
1620 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1621 extern void intel_detect_pch(struct drm_device *dev);
1622 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1623 extern int intel_enable_rc6(const struct drm_device *dev);
1624
1625 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1626 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1627                         struct drm_file *file);
1628
1629 /* overlay */
1630 #ifdef CONFIG_DEBUG_FS
1631 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1632 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1633
1634 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1635 extern void intel_display_print_error_state(struct seq_file *m,
1636                                             struct drm_device *dev,
1637                                             struct intel_display_error_state *error);
1638 #endif
1639
1640 /* On SNB platform, before reading ring registers forcewake bit
1641  * must be set to prevent GT core from power down and stale values being
1642  * returned.
1643  */
1644 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1645 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1646 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1647
1648 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
1649 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
1650
1651 #define __i915_read(x, y) \
1652         u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1653
1654 __i915_read(8, b)
1655 __i915_read(16, w)
1656 __i915_read(32, l)
1657 __i915_read(64, q)
1658 #undef __i915_read
1659
1660 #define __i915_write(x, y) \
1661         void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1662
1663 __i915_write(8, b)
1664 __i915_write(16, w)
1665 __i915_write(32, l)
1666 __i915_write(64, q)
1667 #undef __i915_write
1668
1669 #define I915_READ8(reg)         i915_read8(dev_priv, (reg))
1670 #define I915_WRITE8(reg, val)   i915_write8(dev_priv, (reg), (val))
1671
1672 #define I915_READ16(reg)        i915_read16(dev_priv, (reg))
1673 #define I915_WRITE16(reg, val)  i915_write16(dev_priv, (reg), (val))
1674 #define I915_READ16_NOTRACE(reg)        readw(dev_priv->regs + (reg))
1675 #define I915_WRITE16_NOTRACE(reg, val)  writew(val, dev_priv->regs + (reg))
1676
1677 #define I915_READ(reg)          i915_read32(dev_priv, (reg))
1678 #define I915_WRITE(reg, val)    i915_write32(dev_priv, (reg), (val))
1679 #define I915_READ_NOTRACE(reg)          readl(dev_priv->regs + (reg))
1680 #define I915_WRITE_NOTRACE(reg, val)    writel(val, dev_priv->regs + (reg))
1681
1682 #define I915_WRITE64(reg, val)  i915_write64(dev_priv, (reg), (val))
1683 #define I915_READ64(reg)        i915_read64(dev_priv, (reg))
1684
1685 #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
1686 #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
1687
1688
1689 #endif