1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <drm/intel-gtt.h>
40 /* General customization:
43 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
45 #define DRIVER_NAME "i915"
46 #define DRIVER_DESC "Intel Graphics"
47 #define DRIVER_DATE "20080730"
59 #define I915_NUM_PIPE 2
61 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
66 * 1.2: Add Power Management
67 * 1.3: Add vblank support
68 * 1.4: Fix cmdbuffer path, add heap destroy
69 * 1.5: Add vblank pipe configuration
70 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
71 * - Support vertical blank on secondary display pipe
73 #define DRIVER_MAJOR 1
74 #define DRIVER_MINOR 6
75 #define DRIVER_PATCHLEVEL 0
77 #define WATCH_COHERENCY 0
81 #define WATCH_PWRITE 0
83 #define I915_GEM_PHYS_CURSOR_0 1
84 #define I915_GEM_PHYS_CURSOR_1 2
85 #define I915_GEM_PHYS_OVERLAY_REGS 3
86 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
88 struct drm_i915_gem_phys_object
{
90 struct page
**page_list
;
91 drm_dma_handle_t
*handle
;
92 struct drm_i915_gem_object
*cur_obj
;
96 struct mem_block
*next
;
97 struct mem_block
*prev
;
100 struct drm_file
*file_priv
; /* NULL: free, -1: heap, other: real files */
103 struct opregion_header
;
104 struct opregion_acpi
;
105 struct opregion_swsci
;
106 struct opregion_asle
;
108 struct intel_opregion
{
109 struct opregion_header
*header
;
110 struct opregion_acpi
*acpi
;
111 struct opregion_swsci
*swsci
;
112 struct opregion_asle
*asle
;
115 #define OPREGION_SIZE (8*1024)
117 struct intel_overlay
;
118 struct intel_overlay_error_state
;
120 struct drm_i915_master_private
{
121 drm_local_map_t
*sarea
;
122 struct _drm_i915_sarea
*sarea_priv
;
124 #define I915_FENCE_REG_NONE -1
126 struct drm_i915_fence_reg
{
127 struct list_head lru_list
;
128 struct drm_i915_gem_object
*obj
;
129 uint32_t setup_seqno
;
132 struct sdvo_device_mapping
{
142 struct intel_display_error_state
;
144 struct drm_i915_error_state
{
153 u32 error
; /* gen6+ */
154 u32 bcs_acthd
; /* gen6+ blt engine */
159 u32 vcs_acthd
; /* gen6+ bsd engine */
171 struct drm_i915_error_object
{
175 } *ringbuffer
, *batchbuffer
[2];
176 struct drm_i915_error_buffer
{
189 } *active_bo
, *pinned_bo
;
190 u32 active_bo_count
, pinned_bo_count
;
191 struct intel_overlay_error_state
*overlay
;
192 struct intel_display_error_state
*display
;
195 struct drm_i915_display_funcs
{
196 void (*dpms
)(struct drm_crtc
*crtc
, int mode
);
197 bool (*fbc_enabled
)(struct drm_device
*dev
);
198 void (*enable_fbc
)(struct drm_crtc
*crtc
, unsigned long interval
);
199 void (*disable_fbc
)(struct drm_device
*dev
);
200 int (*get_display_clock_speed
)(struct drm_device
*dev
);
201 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
202 void (*update_wm
)(struct drm_device
*dev
, int planea_clock
,
203 int planeb_clock
, int sr_hdisplay
, int sr_htotal
,
205 /* clock updates for mode set */
207 /* render clock increase/decrease */
208 /* display clock increase/decrease */
209 /* pll clock increase/decrease */
210 /* clock gating init */
213 struct intel_device_info
{
223 u8 is_broadwater
: 1;
227 u8 has_pipe_cxsr
: 1;
229 u8 cursor_needs_physical
: 1;
231 u8 overlay_needs_physical
: 1;
238 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
239 FBC_STOLEN_TOO_SMALL
, /* not enough space to hold compressed buffers */
240 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
241 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
242 FBC_BAD_PLANE
, /* fbc not supported on plane */
243 FBC_NOT_TILED
, /* buffer not tiled */
244 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
248 PCH_IBX
, /* Ibexpeak PCH */
249 PCH_CPT
, /* Cougarpoint PCH */
252 #define QUIRK_PIPEA_FORCE (1<<0)
256 typedef struct drm_i915_private
{
257 struct drm_device
*dev
;
259 const struct intel_device_info
*info
;
266 struct i2c_adapter adapter
;
267 struct i2c_adapter
*force_bit
;
271 struct pci_dev
*bridge_dev
;
272 struct intel_ring_buffer render_ring
;
273 struct intel_ring_buffer bsd_ring
;
274 struct intel_ring_buffer blt_ring
;
277 drm_dma_handle_t
*status_page_dmah
;
278 dma_addr_t dma_status_page
;
280 drm_local_map_t hws_map
;
281 struct drm_i915_gem_object
*pwrctx
;
282 struct drm_i915_gem_object
*renderctx
;
284 struct resource mch_res
;
292 atomic_t irq_received
;
293 /** Protects user_irq_refcount and irq_mask_reg */
294 spinlock_t user_irq_lock
;
296 /** Cached value of IMR to avoid reads in updating the bitfield */
299 /** splitted irq regs for graphics and display engine on Ironlake,
300 irq_mask_reg is still used for display irq. */
302 u32 gt_irq_enable_reg
;
303 u32 de_irq_enable_reg
;
304 u32 pch_irq_mask_reg
;
305 u32 pch_irq_enable_reg
;
307 u32 hotplug_supported_mask
;
308 struct work_struct hotplug_work
;
310 int tex_lru_log_granularity
;
311 int allow_batchbuffer
;
312 struct mem_block
*agp_heap
;
313 unsigned int sr01
, adpa
, ppcr
, dvob
, dvoc
, lvds
;
317 /* For hangcheck timer */
318 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
319 struct timer_list hangcheck_timer
;
322 uint32_t last_instdone
;
323 uint32_t last_instdone1
;
325 unsigned long cfb_size
;
326 unsigned long cfb_pitch
;
327 unsigned long cfb_offset
;
334 struct intel_opregion opregion
;
337 struct intel_overlay
*overlay
;
340 int backlight_level
; /* restore backlight to this value */
341 struct drm_display_mode
*panel_fixed_mode
;
342 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
343 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
345 /* Feature bits from the VBIOS */
346 unsigned int int_tv_support
:1;
347 unsigned int lvds_dither
:1;
348 unsigned int lvds_vbt
:1;
349 unsigned int int_crt_support
:1;
350 unsigned int lvds_use_ssc
:1;
361 struct edp_power_seq pps
;
363 bool no_aux_handshake
;
365 struct notifier_block lid_notifier
;
368 struct drm_i915_fence_reg fence_regs
[16]; /* assume 965 */
369 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
370 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
372 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
374 spinlock_t error_lock
;
375 struct drm_i915_error_state
*first_error
;
376 struct work_struct error_work
;
377 struct completion error_completion
;
378 struct workqueue_struct
*wq
;
380 /* Display functions */
381 struct drm_i915_display_funcs display
;
383 /* PCH chipset type */
384 enum intel_pch pch_type
;
386 unsigned long quirks
;
411 u32 saveTRANS_HTOTAL_A
;
412 u32 saveTRANS_HBLANK_A
;
413 u32 saveTRANS_HSYNC_A
;
414 u32 saveTRANS_VTOTAL_A
;
415 u32 saveTRANS_VBLANK_A
;
416 u32 saveTRANS_VSYNC_A
;
424 u32 savePFIT_PGM_RATIOS
;
425 u32 saveBLC_HIST_CTL
;
427 u32 saveBLC_PWM_CTL2
;
428 u32 saveBLC_CPU_PWM_CTL
;
429 u32 saveBLC_CPU_PWM_CTL2
;
442 u32 saveTRANS_HTOTAL_B
;
443 u32 saveTRANS_HBLANK_B
;
444 u32 saveTRANS_HSYNC_B
;
445 u32 saveTRANS_VTOTAL_B
;
446 u32 saveTRANS_VBLANK_B
;
447 u32 saveTRANS_VSYNC_B
;
461 u32 savePP_ON_DELAYS
;
462 u32 savePP_OFF_DELAYS
;
470 u32 savePFIT_CONTROL
;
471 u32 save_palette_a
[256];
472 u32 save_palette_b
[256];
473 u32 saveDPFC_CB_BASE
;
474 u32 saveFBC_CFB_BASE
;
477 u32 saveFBC_CONTROL2
;
487 u32 saveCACHE_MODE_0
;
488 u32 saveMI_ARB_STATE
;
499 uint64_t saveFENCE
[16];
510 u32 savePIPEA_GMCH_DATA_M
;
511 u32 savePIPEB_GMCH_DATA_M
;
512 u32 savePIPEA_GMCH_DATA_N
;
513 u32 savePIPEB_GMCH_DATA_N
;
514 u32 savePIPEA_DP_LINK_M
;
515 u32 savePIPEB_DP_LINK_M
;
516 u32 savePIPEA_DP_LINK_N
;
517 u32 savePIPEB_DP_LINK_N
;
528 u32 savePCH_DREF_CONTROL
;
529 u32 saveDISP_ARB_CTL
;
530 u32 savePIPEA_DATA_M1
;
531 u32 savePIPEA_DATA_N1
;
532 u32 savePIPEA_LINK_M1
;
533 u32 savePIPEA_LINK_N1
;
534 u32 savePIPEB_DATA_M1
;
535 u32 savePIPEB_DATA_N1
;
536 u32 savePIPEB_LINK_M1
;
537 u32 savePIPEB_LINK_N1
;
538 u32 saveMCHBAR_RENDER_STANDBY
;
541 /** Bridge to intel-gtt-ko */
542 const struct intel_gtt
*gtt
;
543 /** Memory allocator for GTT stolen memory */
544 struct drm_mm stolen
;
545 /** Memory allocator for GTT */
546 struct drm_mm gtt_space
;
547 /** List of all objects in gtt_space. Used to restore gtt
548 * mappings on resume */
549 struct list_head gtt_list
;
550 /** End of mappable part of GTT */
551 unsigned long gtt_mappable_end
;
553 struct io_mapping
*gtt_mapping
;
556 struct shrinker inactive_shrinker
;
559 * List of objects currently involved in rendering.
561 * Includes buffers having the contents of their GPU caches
562 * flushed, not necessarily primitives. last_rendering_seqno
563 * represents when the rendering involved will be completed.
565 * A reference is held on the buffer while on this list.
567 struct list_head active_list
;
570 * List of objects which are not in the ringbuffer but which
571 * still have a write_domain which needs to be flushed before
574 * last_rendering_seqno is 0 while an object is in this list.
576 * A reference is held on the buffer while on this list.
578 struct list_head flushing_list
;
581 * LRU list of objects which are not in the ringbuffer and
582 * are ready to unbind, but are still in the GTT.
584 * last_rendering_seqno is 0 while an object is in this list.
586 * A reference is not held on the buffer while on this list,
587 * as merely being GTT-bound shouldn't prevent its being
588 * freed, and we'll pull it off the list in the free path.
590 struct list_head inactive_list
;
593 * LRU list of objects which are not in the ringbuffer but
594 * are still pinned in the GTT.
596 struct list_head pinned_list
;
598 /** LRU list of objects with fence regs on them. */
599 struct list_head fence_list
;
602 * List of objects currently pending being freed.
604 * These objects are no longer in use, but due to a signal
605 * we were prevented from freeing them at the appointed time.
607 struct list_head deferred_free_list
;
610 * We leave the user IRQ off as much as possible,
611 * but this means that requests will finish and never
612 * be retired once the system goes idle. Set a timer to
613 * fire periodically while the ring is running. When it
614 * fires, go retire requests.
616 struct delayed_work retire_work
;
619 * Flag if the X Server, and thus DRM, is not currently in
620 * control of the device.
622 * This is set between LeaveVT and EnterVT. It needs to be
623 * replaced with a semaphore. It also needs to be
624 * transitioned away from for kernel modesetting.
629 * Flag if the hardware appears to be wedged.
631 * This is set when attempts to idle the device timeout.
632 * It prevents command submission from occuring and makes
633 * every pending request fail
637 /** Bit 6 swizzling required for X tiling */
638 uint32_t bit_6_swizzle_x
;
639 /** Bit 6 swizzling required for Y tiling */
640 uint32_t bit_6_swizzle_y
;
642 /* storage for physical objects */
643 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
645 /* accounting, useful for userland debugging */
647 size_t mappable_gtt_total
;
648 size_t object_memory
;
651 struct sdvo_device_mapping sdvo_mappings
[2];
652 /* indicate whether the LVDS_BORDER should be enabled or not */
653 unsigned int lvds_border_bits
;
654 /* Panel fitter placement and size for Ironlake+ */
655 u32 pch_pf_pos
, pch_pf_size
;
657 struct drm_crtc
*plane_to_crtc_mapping
[2];
658 struct drm_crtc
*pipe_to_crtc_mapping
[2];
659 wait_queue_head_t pending_flip_queue
;
660 bool flip_pending_is_done
;
662 /* Reclocking support */
663 bool render_reclock_avail
;
664 bool lvds_downclock_avail
;
665 /* indicates the reduced downclock for LVDS*/
667 struct work_struct idle_work
;
668 struct timer_list idle_timer
;
672 struct child_device_config
*child_dev
;
673 struct drm_connector
*int_lvds_connector
;
675 bool mchbar_need_disable
;
684 unsigned long last_time1
;
686 struct timespec last_time2
;
687 unsigned long gfx_power
;
691 spinlock_t
*mchdev_lock
;
693 enum no_fbc_reason no_fbc_reason
;
695 struct drm_mm_node
*compressed_fb
;
696 struct drm_mm_node
*compressed_llb
;
698 unsigned long last_gpu_reset
;
700 /* list of fbdev register on this device */
701 struct intel_fbdev
*fbdev
;
702 } drm_i915_private_t
;
704 struct drm_i915_gem_object
{
705 struct drm_gem_object base
;
707 /** Current space allocated to this object in the GTT, if any. */
708 struct drm_mm_node
*gtt_space
;
709 struct list_head gtt_list
;
711 /** This object's place on the active/flushing/inactive lists */
712 struct list_head ring_list
;
713 struct list_head mm_list
;
714 /** This object's place on GPU write list */
715 struct list_head gpu_write_list
;
716 /** This object's place in the batchbuffer or on the eviction list */
717 struct list_head exec_list
;
720 * This is set if the object is on the active or flushing lists
721 * (has pending rendering), and is not set if it's on inactive (ready
724 unsigned int active
: 1;
727 * This is set if the object has been written to since last bound
730 unsigned int dirty
: 1;
733 * This is set if the object has been written to since the last
736 unsigned int pending_gpu_write
: 1;
739 * Fence register bits (if any) for this object. Will be set
740 * as needed when mapped into the GTT.
741 * Protected by dev->struct_mutex.
743 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
745 signed int fence_reg
: 5;
748 * Advice: are the backing pages purgeable?
750 unsigned int madv
: 2;
753 * Current tiling mode for the object.
755 unsigned int tiling_mode
: 2;
756 unsigned int tiling_changed
: 1;
758 /** How many users have pinned this object in GTT space. The following
759 * users can each hold at most one reference: pwrite/pread, pin_ioctl
760 * (via user_pin_count), execbuffer (objects are not allowed multiple
761 * times for the same batchbuffer), and the framebuffer code. When
762 * switching/pageflipping, the framebuffer code has at most two buffers
765 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
766 * bits with absolutely no headroom. So use 4 bits. */
767 unsigned int pin_count
: 4;
768 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
771 * Is the object at the current location in the gtt mappable and
772 * fenceable? Used to avoid costly recalculations.
774 unsigned int map_and_fenceable
: 1;
777 * Whether the current gtt mapping needs to be mappable (and isn't just
778 * mappable by accident). Track pin and fault separate for a more
779 * accurate mappable working set.
781 unsigned int fault_mappable
: 1;
782 unsigned int pin_mappable
: 1;
785 * Is the GPU currently using a fence to access this buffer,
787 unsigned int pending_fenced_gpu_access
:1;
788 unsigned int fenced_gpu_access
:1;
795 struct scatterlist
*sg_list
;
799 * Current offset of the object in GTT space.
801 * This is the same as gtt_space->start
805 /** Breadcrumb of last rendering to the buffer. */
806 uint32_t last_rendering_seqno
;
807 struct intel_ring_buffer
*ring
;
809 /** Breadcrumb of last fenced GPU access to the buffer. */
810 uint32_t last_fenced_seqno
;
811 struct intel_ring_buffer
*last_fenced_ring
;
813 /** Current tiling stride for the object, if it's tiled. */
816 /** Record of address bit 17 of each page at last unbind. */
817 unsigned long *bit_17
;
819 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
823 * If present, while GEM_DOMAIN_CPU is in the read domain this array
824 * flags which individual pages are valid.
826 uint8_t *page_cpu_valid
;
828 /** User space pin count and filp owning the pin */
829 uint32_t user_pin_count
;
830 struct drm_file
*pin_filp
;
832 /** for phy allocated objects */
833 struct drm_i915_gem_phys_object
*phys_obj
;
836 * Number of crtcs where this object is currently the fb, but
837 * will be page flipped away on the next vblank. When it
838 * reaches 0, dev_priv->pending_flip_queue will be woken up.
840 atomic_t pending_flip
;
843 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
846 * Request queue structure.
848 * The request queue allows us to note sequence numbers that have been emitted
849 * and may be associated with active buffers to be retired.
851 * By keeping this list, we can avoid having to do questionable
852 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
853 * an emission time with seqnos for tracking how far ahead of the GPU we are.
855 struct drm_i915_gem_request
{
856 /** On Which ring this request was generated */
857 struct intel_ring_buffer
*ring
;
859 /** GEM sequence number associated with this request. */
862 /** Time at which this request was emitted, in jiffies. */
863 unsigned long emitted_jiffies
;
865 /** global list entry for this request */
866 struct list_head list
;
868 struct drm_i915_file_private
*file_priv
;
869 /** file_priv list entry for this request */
870 struct list_head client_list
;
873 struct drm_i915_file_private
{
875 struct spinlock lock
;
876 struct list_head request_list
;
880 enum intel_chip_family
{
887 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
889 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
890 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
891 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
892 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
893 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
894 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
895 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
896 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
897 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
898 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
899 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
900 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
901 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
902 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
903 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
904 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
905 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
906 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
907 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
909 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
910 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
911 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
912 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
913 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
915 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
916 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
917 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
919 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
920 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
922 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
923 * rows, which changed the alignment requirements and fence programming.
925 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
927 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
928 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
929 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
930 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
931 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
932 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
933 /* dsparb controlled by hw only */
934 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
936 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
937 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
938 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
939 #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
941 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
942 #define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))
944 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
945 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
946 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
948 #include "i915_trace.h"
950 extern struct drm_ioctl_desc i915_ioctls
[];
951 extern int i915_max_ioctl
;
952 extern unsigned int i915_fbpercrtc
;
953 extern unsigned int i915_powersave
;
954 extern unsigned int i915_lvds_downclock
;
956 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
957 extern int i915_resume(struct drm_device
*dev
);
958 extern void i915_save_display(struct drm_device
*dev
);
959 extern void i915_restore_display(struct drm_device
*dev
);
960 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
961 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
964 extern void i915_kernel_lost_context(struct drm_device
* dev
);
965 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
966 extern int i915_driver_unload(struct drm_device
*);
967 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
968 extern void i915_driver_lastclose(struct drm_device
* dev
);
969 extern void i915_driver_preclose(struct drm_device
*dev
,
970 struct drm_file
*file_priv
);
971 extern void i915_driver_postclose(struct drm_device
*dev
,
972 struct drm_file
*file_priv
);
973 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
974 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
976 extern int i915_emit_box(struct drm_device
*dev
,
977 struct drm_clip_rect
*box
,
979 extern int i915_reset(struct drm_device
*dev
, u8 flags
);
980 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
981 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
982 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
983 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
987 void i915_hangcheck_elapsed(unsigned long data
);
988 void i915_handle_error(struct drm_device
*dev
, bool wedged
);
989 extern int i915_irq_emit(struct drm_device
*dev
, void *data
,
990 struct drm_file
*file_priv
);
991 extern int i915_irq_wait(struct drm_device
*dev
, void *data
,
992 struct drm_file
*file_priv
);
993 void i915_trace_irq_get(struct drm_device
*dev
, u32 seqno
);
994 extern void i915_enable_interrupt (struct drm_device
*dev
);
996 extern irqreturn_t
i915_driver_irq_handler(DRM_IRQ_ARGS
);
997 extern void i915_driver_irq_preinstall(struct drm_device
* dev
);
998 extern int i915_driver_irq_postinstall(struct drm_device
*dev
);
999 extern void i915_driver_irq_uninstall(struct drm_device
* dev
);
1000 extern int i915_vblank_pipe_set(struct drm_device
*dev
, void *data
,
1001 struct drm_file
*file_priv
);
1002 extern int i915_vblank_pipe_get(struct drm_device
*dev
, void *data
,
1003 struct drm_file
*file_priv
);
1004 extern int i915_enable_vblank(struct drm_device
*dev
, int crtc
);
1005 extern void i915_disable_vblank(struct drm_device
*dev
, int crtc
);
1006 extern u32
i915_get_vblank_counter(struct drm_device
*dev
, int crtc
);
1007 extern u32
gm45_get_vblank_counter(struct drm_device
*dev
, int crtc
);
1008 extern int i915_vblank_swap(struct drm_device
*dev
, void *data
,
1009 struct drm_file
*file_priv
);
1010 extern void i915_enable_irq(drm_i915_private_t
*dev_priv
, u32 mask
);
1011 extern void i915_disable_irq(drm_i915_private_t
*dev_priv
, u32 mask
);
1012 extern void ironlake_enable_graphics_irq(drm_i915_private_t
*dev_priv
,
1014 extern void ironlake_disable_graphics_irq(drm_i915_private_t
*dev_priv
,
1018 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1021 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1023 void intel_enable_asle (struct drm_device
*dev
);
1025 #ifdef CONFIG_DEBUG_FS
1026 extern void i915_destroy_error_state(struct drm_device
*dev
);
1028 #define i915_destroy_error_state(x)
1033 extern int i915_mem_alloc(struct drm_device
*dev
, void *data
,
1034 struct drm_file
*file_priv
);
1035 extern int i915_mem_free(struct drm_device
*dev
, void *data
,
1036 struct drm_file
*file_priv
);
1037 extern int i915_mem_init_heap(struct drm_device
*dev
, void *data
,
1038 struct drm_file
*file_priv
);
1039 extern int i915_mem_destroy_heap(struct drm_device
*dev
, void *data
,
1040 struct drm_file
*file_priv
);
1041 extern void i915_mem_takedown(struct mem_block
**heap
);
1042 extern void i915_mem_release(struct drm_device
* dev
,
1043 struct drm_file
*file_priv
, struct mem_block
*heap
);
1045 int i915_gem_check_is_wedged(struct drm_device
*dev
);
1046 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
1047 struct drm_file
*file_priv
);
1048 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1049 struct drm_file
*file_priv
);
1050 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
1051 struct drm_file
*file_priv
);
1052 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1053 struct drm_file
*file_priv
);
1054 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1055 struct drm_file
*file_priv
);
1056 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1057 struct drm_file
*file_priv
);
1058 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1059 struct drm_file
*file_priv
);
1060 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1061 struct drm_file
*file_priv
);
1062 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1063 struct drm_file
*file_priv
);
1064 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1065 struct drm_file
*file_priv
);
1066 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
1067 struct drm_file
*file_priv
);
1068 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
1069 struct drm_file
*file_priv
);
1070 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
1071 struct drm_file
*file_priv
);
1072 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
1073 struct drm_file
*file_priv
);
1074 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
1075 struct drm_file
*file_priv
);
1076 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
1077 struct drm_file
*file_priv
);
1078 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
1079 struct drm_file
*file_priv
);
1080 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
1081 struct drm_file
*file_priv
);
1082 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
1083 struct drm_file
*file_priv
);
1084 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
1085 struct drm_file
*file_priv
);
1086 void i915_gem_load(struct drm_device
*dev
);
1087 int i915_gem_init_object(struct drm_gem_object
*obj
);
1088 void i915_gem_flush_ring(struct drm_device
*dev
,
1089 struct intel_ring_buffer
*ring
,
1090 uint32_t invalidate_domains
,
1091 uint32_t flush_domains
);
1092 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
1094 void i915_gem_free_object(struct drm_gem_object
*obj
);
1095 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
1097 bool map_and_fenceable
);
1098 void i915_gem_object_unpin(struct drm_i915_gem_object
*obj
);
1099 int __must_check
i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
1100 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
1101 void i915_gem_lastclose(struct drm_device
*dev
);
1103 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
1104 int __must_check
i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1105 bool interruptible
);
1106 void i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1107 struct intel_ring_buffer
*ring
);
1110 * Returns true if seq1 is later than seq2.
1113 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1115 return (int32_t)(seq1
- seq2
) >= 0;
1119 i915_gem_next_request_seqno(struct drm_device
*dev
,
1120 struct intel_ring_buffer
*ring
)
1122 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1123 return ring
->outstanding_lazy_request
= dev_priv
->next_seqno
;
1126 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
,
1127 struct intel_ring_buffer
*pipelined
,
1128 bool interruptible
);
1129 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
1131 void i915_gem_retire_requests(struct drm_device
*dev
);
1132 void i915_gem_reset(struct drm_device
*dev
);
1133 void i915_gem_clflush_object(struct drm_i915_gem_object
*obj
);
1134 int __must_check
i915_gem_object_set_domain(struct drm_i915_gem_object
*obj
,
1135 uint32_t read_domains
,
1136 uint32_t write_domain
);
1137 int __must_check
i915_gem_object_flush_gpu(struct drm_i915_gem_object
*obj
,
1138 bool interruptible
);
1139 int __must_check
i915_gem_init_ringbuffer(struct drm_device
*dev
);
1140 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
1141 void i915_gem_do_init(struct drm_device
*dev
,
1142 unsigned long start
,
1143 unsigned long mappable_end
,
1145 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
1146 int __must_check
i915_gem_idle(struct drm_device
*dev
);
1147 int __must_check
i915_add_request(struct drm_device
*dev
,
1148 struct drm_file
*file_priv
,
1149 struct drm_i915_gem_request
*request
,
1150 struct intel_ring_buffer
*ring
);
1151 int __must_check
i915_do_wait_request(struct drm_device
*dev
,
1154 struct intel_ring_buffer
*ring
);
1155 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
1157 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
1160 i915_gem_object_set_to_display_plane(struct drm_i915_gem_object
*obj
,
1161 struct intel_ring_buffer
*pipelined
);
1162 int i915_gem_attach_phys_object(struct drm_device
*dev
,
1163 struct drm_i915_gem_object
*obj
,
1166 void i915_gem_detach_phys_object(struct drm_device
*dev
,
1167 struct drm_i915_gem_object
*obj
);
1168 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
1169 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
1171 /* i915_gem_gtt.c */
1172 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
);
1173 int __must_check
i915_gem_gtt_bind_object(struct drm_i915_gem_object
*obj
);
1174 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object
*obj
);
1176 /* i915_gem_evict.c */
1177 int __must_check
i915_gem_evict_something(struct drm_device
*dev
, int min_size
,
1178 unsigned alignment
, bool mappable
);
1179 int __must_check
i915_gem_evict_everything(struct drm_device
*dev
,
1180 bool purgeable_only
);
1181 int __must_check
i915_gem_evict_inactive(struct drm_device
*dev
,
1182 bool purgeable_only
);
1184 /* i915_gem_tiling.c */
1185 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
1186 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1187 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1189 /* i915_gem_debug.c */
1190 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1191 const char *where
, uint32_t mark
);
1193 int i915_verify_lists(struct drm_device
*dev
);
1195 #define i915_verify_lists(dev) 0
1197 void i915_gem_object_check_coherency(struct drm_i915_gem_object
*obj
,
1199 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1200 const char *where
, uint32_t mark
);
1202 /* i915_debugfs.c */
1203 int i915_debugfs_init(struct drm_minor
*minor
);
1204 void i915_debugfs_cleanup(struct drm_minor
*minor
);
1206 /* i915_suspend.c */
1207 extern int i915_save_state(struct drm_device
*dev
);
1208 extern int i915_restore_state(struct drm_device
*dev
);
1210 /* i915_suspend.c */
1211 extern int i915_save_state(struct drm_device
*dev
);
1212 extern int i915_restore_state(struct drm_device
*dev
);
1215 extern int intel_setup_gmbus(struct drm_device
*dev
);
1216 extern void intel_teardown_gmbus(struct drm_device
*dev
);
1217 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
1218 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
1219 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
1221 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
1223 extern void intel_i2c_reset(struct drm_device
*dev
);
1225 /* intel_opregion.c */
1226 extern int intel_opregion_setup(struct drm_device
*dev
);
1228 extern void intel_opregion_init(struct drm_device
*dev
);
1229 extern void intel_opregion_fini(struct drm_device
*dev
);
1230 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
1231 extern void intel_opregion_gse_intr(struct drm_device
*dev
);
1232 extern void intel_opregion_enable_asle(struct drm_device
*dev
);
1234 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
1235 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
1236 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
1237 static inline void intel_opregion_gse_intr(struct drm_device
*dev
) { return; }
1238 static inline void intel_opregion_enable_asle(struct drm_device
*dev
) { return; }
1243 extern void intel_register_dsm_handler(void);
1244 extern void intel_unregister_dsm_handler(void);
1246 static inline void intel_register_dsm_handler(void) { return; }
1247 static inline void intel_unregister_dsm_handler(void) { return; }
1248 #endif /* CONFIG_ACPI */
1251 extern void intel_modeset_init(struct drm_device
*dev
);
1252 extern void intel_modeset_cleanup(struct drm_device
*dev
);
1253 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
1254 extern void i8xx_disable_fbc(struct drm_device
*dev
);
1255 extern void g4x_disable_fbc(struct drm_device
*dev
);
1256 extern void ironlake_disable_fbc(struct drm_device
*dev
);
1257 extern void intel_disable_fbc(struct drm_device
*dev
);
1258 extern void intel_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
);
1259 extern bool intel_fbc_enabled(struct drm_device
*dev
);
1260 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
1261 extern void intel_detect_pch (struct drm_device
*dev
);
1262 extern int intel_trans_dp_port_sel (struct drm_crtc
*crtc
);
1265 #ifdef CONFIG_DEBUG_FS
1266 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
1267 extern void intel_overlay_print_error_state(struct seq_file
*m
, struct intel_overlay_error_state
*error
);
1269 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
1270 extern void intel_display_print_error_state(struct seq_file
*m
,
1271 struct drm_device
*dev
,
1272 struct intel_display_error_state
*error
);
1276 * Lock test for when it's just for synchronization of ring access.
1278 * In that case, we don't need to do it when GEM is initialized as nobody else
1279 * has access to the ring.
1281 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
1282 if (((drm_i915_private_t *)dev->dev_private)->render_ring.obj \
1284 LOCK_TEST_WITH_RETURN(dev, file); \
1288 #define __i915_read(x, y) \
1289 static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1290 u##x val = read##y(dev_priv->regs + reg); \
1291 trace_i915_reg_rw('R', reg, val, sizeof(val)); \
1300 #define __i915_write(x, y) \
1301 static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1302 trace_i915_reg_rw('W', reg, val, sizeof(val)); \
1303 write##y(val, dev_priv->regs + reg); \
1311 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1312 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1314 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1315 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1316 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1317 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1319 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1320 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1321 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1322 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1324 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1325 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1327 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1328 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1331 /* On SNB platform, before reading ring registers forcewake bit
1332 * must be set to prevent GT core from power down and stale values being
1335 static inline u32
i915_safe_read(struct drm_i915_private
*dev_priv
, u32 reg
)
1337 if (IS_GEN6(dev_priv
->dev
)) {
1338 I915_WRITE_NOTRACE(FORCEWAKE
, 1);
1339 POSTING_READ(FORCEWAKE
);
1340 /* XXX How long do we really need to wait here?
1341 * Will different registers/engines require different periods?
1345 return I915_READ(reg
);
1349 i915_write(struct drm_i915_private
*dev_priv
, u32 reg
, u64 val
, int len
)
1351 /* Trace down the write operation before the real write */
1352 trace_i915_reg_rw('W', reg
, val
, len
);
1355 writeq(val
, dev_priv
->regs
+ reg
);
1358 writel(val
, dev_priv
->regs
+ reg
);
1361 writew(val
, dev_priv
->regs
+ reg
);
1364 writeb(val
, dev_priv
->regs
+ reg
);
1369 #define BEGIN_LP_RING(n) \
1370 intel_ring_begin(&dev_priv->render_ring, (n))
1372 #define OUT_RING(x) \
1373 intel_ring_emit(&dev_priv->render_ring, x)
1375 #define ADVANCE_LP_RING() \
1376 intel_ring_advance(&dev_priv->render_ring)
1379 * Reads a dword out of the status page, which is written to from the command
1380 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
1381 * MI_STORE_DATA_IMM.
1383 * The following dwords have a reserved meaning:
1384 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
1385 * 0x04: ring 0 head pointer
1386 * 0x05: ring 1 head pointer (915-class)
1387 * 0x06: ring 2 head pointer (915-class)
1388 * 0x10-0x1b: Context status DWords (GM45)
1389 * 0x1f: Last written status offset. (GM45)
1391 * The area from dword 0x20 to 0x3ff is available for driver usage.
1393 #define READ_HWSP(dev_priv, reg) (((volatile u32 *)\
1394 (dev_priv->render_ring.status_page.page_addr))[reg])
1395 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1396 #define I915_GEM_HWS_INDEX 0x20
1397 #define I915_BREADCRUMB_INDEX 0x21