2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/i915_drm.h>
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
41 static __must_check
int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
43 bool map_and_fenceable
,
45 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
46 struct drm_i915_gem_object
*obj
,
47 struct drm_i915_gem_pwrite
*args
,
48 struct drm_file
*file
);
50 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
51 struct drm_i915_gem_object
*obj
);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
53 struct drm_i915_fence_reg
*fence
,
56 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
57 struct shrink_control
*sc
);
58 static long i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
);
59 static void i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
60 static void i915_gem_object_truncate(struct drm_i915_gem_object
*obj
);
62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
65 i915_gem_release_mmap(obj
);
67 /* As we do not have an associated fence register, we will force
68 * a tiling change if we ever need to acquire one.
70 obj
->fence_dirty
= false;
71 obj
->fence_reg
= I915_FENCE_REG_NONE
;
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
78 spin_lock(&dev_priv
->mm
.object_stat_lock
);
79 dev_priv
->mm
.object_count
++;
80 dev_priv
->mm
.object_memory
+= size
;
81 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
84 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
87 spin_lock(&dev_priv
->mm
.object_stat_lock
);
88 dev_priv
->mm
.object_count
--;
89 dev_priv
->mm
.object_memory
-= size
;
90 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
94 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
98 #define EXIT_COND (!i915_reset_in_progress(error) || \
99 i915_terminally_wedged(error))
104 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
105 * userspace. If it takes that long something really bad is going on and
106 * we should simply try to bail out and fail as gracefully as possible.
108 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
112 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
114 } else if (ret
< 0) {
122 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
124 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
127 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
131 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
135 WARN_ON(i915_verify_lists(dev
));
140 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
142 return i915_gem_obj_ggtt_bound(obj
) && !obj
->active
;
146 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
147 struct drm_file
*file
)
149 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
150 struct drm_i915_gem_init
*args
= data
;
152 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
155 if (args
->gtt_start
>= args
->gtt_end
||
156 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
159 /* GEM with user mode setting was never supported on ilk and later. */
160 if (INTEL_INFO(dev
)->gen
>= 5)
163 mutex_lock(&dev
->struct_mutex
);
164 i915_gem_setup_global_gtt(dev
, args
->gtt_start
, args
->gtt_end
,
166 dev_priv
->gtt
.mappable_end
= args
->gtt_end
;
167 mutex_unlock(&dev
->struct_mutex
);
173 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
174 struct drm_file
*file
)
176 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
177 struct drm_i915_gem_get_aperture
*args
= data
;
178 struct drm_i915_gem_object
*obj
;
182 mutex_lock(&dev
->struct_mutex
);
183 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
185 pinned
+= i915_gem_obj_ggtt_size(obj
);
186 mutex_unlock(&dev
->struct_mutex
);
188 args
->aper_size
= dev_priv
->gtt
.base
.total
;
189 args
->aper_available_size
= args
->aper_size
- pinned
;
194 void *i915_gem_object_alloc(struct drm_device
*dev
)
196 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
197 return kmem_cache_alloc(dev_priv
->slab
, GFP_KERNEL
| __GFP_ZERO
);
200 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
202 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
203 kmem_cache_free(dev_priv
->slab
, obj
);
207 i915_gem_create(struct drm_file
*file
,
208 struct drm_device
*dev
,
212 struct drm_i915_gem_object
*obj
;
216 size
= roundup(size
, PAGE_SIZE
);
220 /* Allocate the new object */
221 obj
= i915_gem_alloc_object(dev
, size
);
225 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
226 /* drop reference from allocate - handle holds it now */
227 drm_gem_object_unreference_unlocked(&obj
->base
);
236 i915_gem_dumb_create(struct drm_file
*file
,
237 struct drm_device
*dev
,
238 struct drm_mode_create_dumb
*args
)
240 /* have to work out size/pitch and return them */
241 args
->pitch
= ALIGN(args
->width
* ((args
->bpp
+ 7) / 8), 64);
242 args
->size
= args
->pitch
* args
->height
;
243 return i915_gem_create(file
, dev
,
244 args
->size
, &args
->handle
);
247 int i915_gem_dumb_destroy(struct drm_file
*file
,
248 struct drm_device
*dev
,
251 return drm_gem_handle_delete(file
, handle
);
255 * Creates a new mm object and returns a handle to it.
258 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
259 struct drm_file
*file
)
261 struct drm_i915_gem_create
*args
= data
;
263 return i915_gem_create(file
, dev
,
264 args
->size
, &args
->handle
);
268 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
269 const char *gpu_vaddr
, int gpu_offset
,
272 int ret
, cpu_offset
= 0;
275 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
276 int this_length
= min(cacheline_end
- gpu_offset
, length
);
277 int swizzled_gpu_offset
= gpu_offset
^ 64;
279 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
280 gpu_vaddr
+ swizzled_gpu_offset
,
285 cpu_offset
+= this_length
;
286 gpu_offset
+= this_length
;
287 length
-= this_length
;
294 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
295 const char __user
*cpu_vaddr
,
298 int ret
, cpu_offset
= 0;
301 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
302 int this_length
= min(cacheline_end
- gpu_offset
, length
);
303 int swizzled_gpu_offset
= gpu_offset
^ 64;
305 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
306 cpu_vaddr
+ cpu_offset
,
311 cpu_offset
+= this_length
;
312 gpu_offset
+= this_length
;
313 length
-= this_length
;
319 /* Per-page copy function for the shmem pread fastpath.
320 * Flushes invalid cachelines before reading the target if
321 * needs_clflush is set. */
323 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
324 char __user
*user_data
,
325 bool page_do_bit17_swizzling
, bool needs_clflush
)
330 if (unlikely(page_do_bit17_swizzling
))
333 vaddr
= kmap_atomic(page
);
335 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
337 ret
= __copy_to_user_inatomic(user_data
,
338 vaddr
+ shmem_page_offset
,
340 kunmap_atomic(vaddr
);
342 return ret
? -EFAULT
: 0;
346 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
349 if (unlikely(swizzled
)) {
350 unsigned long start
= (unsigned long) addr
;
351 unsigned long end
= (unsigned long) addr
+ length
;
353 /* For swizzling simply ensure that we always flush both
354 * channels. Lame, but simple and it works. Swizzled
355 * pwrite/pread is far from a hotpath - current userspace
356 * doesn't use it at all. */
357 start
= round_down(start
, 128);
358 end
= round_up(end
, 128);
360 drm_clflush_virt_range((void *)start
, end
- start
);
362 drm_clflush_virt_range(addr
, length
);
367 /* Only difference to the fast-path function is that this can handle bit17
368 * and uses non-atomic copy and kmap functions. */
370 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
371 char __user
*user_data
,
372 bool page_do_bit17_swizzling
, bool needs_clflush
)
379 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
381 page_do_bit17_swizzling
);
383 if (page_do_bit17_swizzling
)
384 ret
= __copy_to_user_swizzled(user_data
,
385 vaddr
, shmem_page_offset
,
388 ret
= __copy_to_user(user_data
,
389 vaddr
+ shmem_page_offset
,
393 return ret
? - EFAULT
: 0;
397 i915_gem_shmem_pread(struct drm_device
*dev
,
398 struct drm_i915_gem_object
*obj
,
399 struct drm_i915_gem_pread
*args
,
400 struct drm_file
*file
)
402 char __user
*user_data
;
405 int shmem_page_offset
, page_length
, ret
= 0;
406 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
408 int needs_clflush
= 0;
409 struct sg_page_iter sg_iter
;
411 user_data
= to_user_ptr(args
->data_ptr
);
414 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
416 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
417 /* If we're not in the cpu read domain, set ourself into the gtt
418 * read domain and manually flush cachelines (if required). This
419 * optimizes for the case when the gpu will dirty the data
420 * anyway again before the next pread happens. */
421 if (obj
->cache_level
== I915_CACHE_NONE
)
423 if (i915_gem_obj_ggtt_bound(obj
)) {
424 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
430 ret
= i915_gem_object_get_pages(obj
);
434 i915_gem_object_pin_pages(obj
);
436 offset
= args
->offset
;
438 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
439 offset
>> PAGE_SHIFT
) {
440 struct page
*page
= sg_page_iter_page(&sg_iter
);
445 /* Operation in this page
447 * shmem_page_offset = offset within page in shmem file
448 * page_length = bytes to copy for this page
450 shmem_page_offset
= offset_in_page(offset
);
451 page_length
= remain
;
452 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
453 page_length
= PAGE_SIZE
- shmem_page_offset
;
455 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
456 (page_to_phys(page
) & (1 << 17)) != 0;
458 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
459 user_data
, page_do_bit17_swizzling
,
464 mutex_unlock(&dev
->struct_mutex
);
466 if (likely(!i915_prefault_disable
) && !prefaulted
) {
467 ret
= fault_in_multipages_writeable(user_data
, remain
);
468 /* Userspace is tricking us, but we've already clobbered
469 * its pages with the prefault and promised to write the
470 * data up to the first fault. Hence ignore any errors
471 * and just continue. */
476 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
477 user_data
, page_do_bit17_swizzling
,
480 mutex_lock(&dev
->struct_mutex
);
483 mark_page_accessed(page
);
488 remain
-= page_length
;
489 user_data
+= page_length
;
490 offset
+= page_length
;
494 i915_gem_object_unpin_pages(obj
);
500 * Reads data from the object referenced by handle.
502 * On error, the contents of *data are undefined.
505 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
506 struct drm_file
*file
)
508 struct drm_i915_gem_pread
*args
= data
;
509 struct drm_i915_gem_object
*obj
;
515 if (!access_ok(VERIFY_WRITE
,
516 to_user_ptr(args
->data_ptr
),
520 ret
= i915_mutex_lock_interruptible(dev
);
524 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
525 if (&obj
->base
== NULL
) {
530 /* Bounds check source. */
531 if (args
->offset
> obj
->base
.size
||
532 args
->size
> obj
->base
.size
- args
->offset
) {
537 /* prime objects have no backing filp to GEM pread/pwrite
540 if (!obj
->base
.filp
) {
545 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
547 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
550 drm_gem_object_unreference(&obj
->base
);
552 mutex_unlock(&dev
->struct_mutex
);
556 /* This is the fast write path which cannot handle
557 * page faults in the source data
561 fast_user_write(struct io_mapping
*mapping
,
562 loff_t page_base
, int page_offset
,
563 char __user
*user_data
,
566 void __iomem
*vaddr_atomic
;
568 unsigned long unwritten
;
570 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
571 /* We can use the cpu mem copy function because this is X86. */
572 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
573 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
575 io_mapping_unmap_atomic(vaddr_atomic
);
580 * This is the fast pwrite path, where we copy the data directly from the
581 * user into the GTT, uncached.
584 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
585 struct drm_i915_gem_object
*obj
,
586 struct drm_i915_gem_pwrite
*args
,
587 struct drm_file
*file
)
589 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
591 loff_t offset
, page_base
;
592 char __user
*user_data
;
593 int page_offset
, page_length
, ret
;
595 ret
= i915_gem_obj_ggtt_pin(obj
, 0, true, true);
599 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
603 ret
= i915_gem_object_put_fence(obj
);
607 user_data
= to_user_ptr(args
->data_ptr
);
610 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
613 /* Operation in this page
615 * page_base = page offset within aperture
616 * page_offset = offset within page
617 * page_length = bytes to copy for this page
619 page_base
= offset
& PAGE_MASK
;
620 page_offset
= offset_in_page(offset
);
621 page_length
= remain
;
622 if ((page_offset
+ remain
) > PAGE_SIZE
)
623 page_length
= PAGE_SIZE
- page_offset
;
625 /* If we get a fault while copying data, then (presumably) our
626 * source page isn't available. Return the error and we'll
627 * retry in the slow path.
629 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
630 page_offset
, user_data
, page_length
)) {
635 remain
-= page_length
;
636 user_data
+= page_length
;
637 offset
+= page_length
;
641 i915_gem_object_unpin(obj
);
646 /* Per-page copy function for the shmem pwrite fastpath.
647 * Flushes invalid cachelines before writing to the target if
648 * needs_clflush_before is set and flushes out any written cachelines after
649 * writing if needs_clflush is set. */
651 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
652 char __user
*user_data
,
653 bool page_do_bit17_swizzling
,
654 bool needs_clflush_before
,
655 bool needs_clflush_after
)
660 if (unlikely(page_do_bit17_swizzling
))
663 vaddr
= kmap_atomic(page
);
664 if (needs_clflush_before
)
665 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
667 ret
= __copy_from_user_inatomic_nocache(vaddr
+ shmem_page_offset
,
670 if (needs_clflush_after
)
671 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
673 kunmap_atomic(vaddr
);
675 return ret
? -EFAULT
: 0;
678 /* Only difference to the fast-path function is that this can handle bit17
679 * and uses non-atomic copy and kmap functions. */
681 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
682 char __user
*user_data
,
683 bool page_do_bit17_swizzling
,
684 bool needs_clflush_before
,
685 bool needs_clflush_after
)
691 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
692 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
694 page_do_bit17_swizzling
);
695 if (page_do_bit17_swizzling
)
696 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
700 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
703 if (needs_clflush_after
)
704 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
706 page_do_bit17_swizzling
);
709 return ret
? -EFAULT
: 0;
713 i915_gem_shmem_pwrite(struct drm_device
*dev
,
714 struct drm_i915_gem_object
*obj
,
715 struct drm_i915_gem_pwrite
*args
,
716 struct drm_file
*file
)
720 char __user
*user_data
;
721 int shmem_page_offset
, page_length
, ret
= 0;
722 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
723 int hit_slowpath
= 0;
724 int needs_clflush_after
= 0;
725 int needs_clflush_before
= 0;
726 struct sg_page_iter sg_iter
;
728 user_data
= to_user_ptr(args
->data_ptr
);
731 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
733 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
734 /* If we're not in the cpu write domain, set ourself into the gtt
735 * write domain and manually flush cachelines (if required). This
736 * optimizes for the case when the gpu will use the data
737 * right away and we therefore have to clflush anyway. */
738 if (obj
->cache_level
== I915_CACHE_NONE
)
739 needs_clflush_after
= 1;
740 if (i915_gem_obj_ggtt_bound(obj
)) {
741 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
746 /* Same trick applies for invalidate partially written cachelines before
748 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)
749 && obj
->cache_level
== I915_CACHE_NONE
)
750 needs_clflush_before
= 1;
752 ret
= i915_gem_object_get_pages(obj
);
756 i915_gem_object_pin_pages(obj
);
758 offset
= args
->offset
;
761 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
762 offset
>> PAGE_SHIFT
) {
763 struct page
*page
= sg_page_iter_page(&sg_iter
);
764 int partial_cacheline_write
;
769 /* Operation in this page
771 * shmem_page_offset = offset within page in shmem file
772 * page_length = bytes to copy for this page
774 shmem_page_offset
= offset_in_page(offset
);
776 page_length
= remain
;
777 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
778 page_length
= PAGE_SIZE
- shmem_page_offset
;
780 /* If we don't overwrite a cacheline completely we need to be
781 * careful to have up-to-date data by first clflushing. Don't
782 * overcomplicate things and flush the entire patch. */
783 partial_cacheline_write
= needs_clflush_before
&&
784 ((shmem_page_offset
| page_length
)
785 & (boot_cpu_data
.x86_clflush_size
- 1));
787 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
788 (page_to_phys(page
) & (1 << 17)) != 0;
790 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
791 user_data
, page_do_bit17_swizzling
,
792 partial_cacheline_write
,
793 needs_clflush_after
);
798 mutex_unlock(&dev
->struct_mutex
);
799 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
800 user_data
, page_do_bit17_swizzling
,
801 partial_cacheline_write
,
802 needs_clflush_after
);
804 mutex_lock(&dev
->struct_mutex
);
807 set_page_dirty(page
);
808 mark_page_accessed(page
);
813 remain
-= page_length
;
814 user_data
+= page_length
;
815 offset
+= page_length
;
819 i915_gem_object_unpin_pages(obj
);
823 * Fixup: Flush cpu caches in case we didn't flush the dirty
824 * cachelines in-line while writing and the object moved
825 * out of the cpu write domain while we've dropped the lock.
827 if (!needs_clflush_after
&&
828 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
829 i915_gem_clflush_object(obj
);
830 i915_gem_chipset_flush(dev
);
834 if (needs_clflush_after
)
835 i915_gem_chipset_flush(dev
);
841 * Writes data to the object referenced by handle.
843 * On error, the contents of the buffer that were to be modified are undefined.
846 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
847 struct drm_file
*file
)
849 struct drm_i915_gem_pwrite
*args
= data
;
850 struct drm_i915_gem_object
*obj
;
856 if (!access_ok(VERIFY_READ
,
857 to_user_ptr(args
->data_ptr
),
861 if (likely(!i915_prefault_disable
)) {
862 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
868 ret
= i915_mutex_lock_interruptible(dev
);
872 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
873 if (&obj
->base
== NULL
) {
878 /* Bounds check destination. */
879 if (args
->offset
> obj
->base
.size
||
880 args
->size
> obj
->base
.size
- args
->offset
) {
885 /* prime objects have no backing filp to GEM pread/pwrite
888 if (!obj
->base
.filp
) {
893 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
896 /* We can only do the GTT pwrite on untiled buffers, as otherwise
897 * it would end up going through the fenced access, and we'll get
898 * different detiling behavior between reading and writing.
899 * pread/pwrite currently are reading and writing from the CPU
900 * perspective, requiring manual detiling by the client.
903 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
907 if (obj
->cache_level
== I915_CACHE_NONE
&&
908 obj
->tiling_mode
== I915_TILING_NONE
&&
909 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
910 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
911 /* Note that the gtt paths might fail with non-page-backed user
912 * pointers (e.g. gtt mappings when moving data between
913 * textures). Fallback to the shmem path in that case. */
916 if (ret
== -EFAULT
|| ret
== -ENOSPC
)
917 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
920 drm_gem_object_unreference(&obj
->base
);
922 mutex_unlock(&dev
->struct_mutex
);
927 i915_gem_check_wedge(struct i915_gpu_error
*error
,
930 if (i915_reset_in_progress(error
)) {
931 /* Non-interruptible callers can't handle -EAGAIN, hence return
932 * -EIO unconditionally for these. */
936 /* Recovery complete, but the reset failed ... */
937 if (i915_terminally_wedged(error
))
947 * Compare seqno against outstanding lazy request. Emit a request if they are
951 i915_gem_check_olr(struct intel_ring_buffer
*ring
, u32 seqno
)
955 BUG_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
958 if (seqno
== ring
->outstanding_lazy_request
)
959 ret
= i915_add_request(ring
, NULL
);
965 * __wait_seqno - wait until execution of seqno has finished
966 * @ring: the ring expected to report seqno
968 * @reset_counter: reset sequence associated with the given seqno
969 * @interruptible: do an interruptible wait (normally yes)
970 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
972 * Note: It is of utmost importance that the passed in seqno and reset_counter
973 * values have been read by the caller in an smp safe manner. Where read-side
974 * locks are involved, it is sufficient to read the reset_counter before
975 * unlocking the lock that protects the seqno. For lockless tricks, the
976 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
979 * Returns 0 if the seqno was found within the alloted time. Else returns the
980 * errno with remaining time filled in timeout argument.
982 static int __wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
,
983 unsigned reset_counter
,
984 bool interruptible
, struct timespec
*timeout
)
986 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
987 struct timespec before
, now
, wait_time
={1,0};
988 unsigned long timeout_jiffies
;
990 bool wait_forever
= true;
993 if (i915_seqno_passed(ring
->get_seqno(ring
, true), seqno
))
996 trace_i915_gem_request_wait_begin(ring
, seqno
);
998 if (timeout
!= NULL
) {
999 wait_time
= *timeout
;
1000 wait_forever
= false;
1003 timeout_jiffies
= timespec_to_jiffies_timeout(&wait_time
);
1005 if (WARN_ON(!ring
->irq_get(ring
)))
1008 /* Record current time in case interrupted by signal, or wedged * */
1009 getrawmonotonic(&before
);
1012 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1013 i915_reset_in_progress(&dev_priv->gpu_error) || \
1014 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1017 end
= wait_event_interruptible_timeout(ring
->irq_queue
,
1021 end
= wait_event_timeout(ring
->irq_queue
, EXIT_COND
,
1024 /* We need to check whether any gpu reset happened in between
1025 * the caller grabbing the seqno and now ... */
1026 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
1029 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1031 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1034 } while (end
== 0 && wait_forever
);
1036 getrawmonotonic(&now
);
1038 ring
->irq_put(ring
);
1039 trace_i915_gem_request_wait_end(ring
, seqno
);
1043 struct timespec sleep_time
= timespec_sub(now
, before
);
1044 *timeout
= timespec_sub(*timeout
, sleep_time
);
1045 if (!timespec_valid(timeout
)) /* i.e. negative time remains */
1046 set_normalized_timespec(timeout
, 0, 0);
1051 case -EAGAIN
: /* Wedged */
1052 case -ERESTARTSYS
: /* Signal */
1054 case 0: /* Timeout */
1056 default: /* Completed */
1057 WARN_ON(end
< 0); /* We're not aware of other errors */
1063 * Waits for a sequence number to be signaled, and cleans up the
1064 * request and object lists appropriately for that event.
1067 i915_wait_seqno(struct intel_ring_buffer
*ring
, uint32_t seqno
)
1069 struct drm_device
*dev
= ring
->dev
;
1070 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1071 bool interruptible
= dev_priv
->mm
.interruptible
;
1074 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1077 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1081 ret
= i915_gem_check_olr(ring
, seqno
);
1085 return __wait_seqno(ring
, seqno
,
1086 atomic_read(&dev_priv
->gpu_error
.reset_counter
),
1087 interruptible
, NULL
);
1091 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object
*obj
,
1092 struct intel_ring_buffer
*ring
)
1094 i915_gem_retire_requests_ring(ring
);
1096 /* Manually manage the write flush as we may have not yet
1097 * retired the buffer.
1099 * Note that the last_write_seqno is always the earlier of
1100 * the two (read/write) seqno, so if we haved successfully waited,
1101 * we know we have passed the last write.
1103 obj
->last_write_seqno
= 0;
1104 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1110 * Ensures that all rendering to the object has completed and the object is
1111 * safe to unbind from the GTT or access from the CPU.
1113 static __must_check
int
1114 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1117 struct intel_ring_buffer
*ring
= obj
->ring
;
1121 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1125 ret
= i915_wait_seqno(ring
, seqno
);
1129 return i915_gem_object_wait_rendering__tail(obj
, ring
);
1132 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1133 * as the object state may change during this call.
1135 static __must_check
int
1136 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1139 struct drm_device
*dev
= obj
->base
.dev
;
1140 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1141 struct intel_ring_buffer
*ring
= obj
->ring
;
1142 unsigned reset_counter
;
1146 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1147 BUG_ON(!dev_priv
->mm
.interruptible
);
1149 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1153 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1157 ret
= i915_gem_check_olr(ring
, seqno
);
1161 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1162 mutex_unlock(&dev
->struct_mutex
);
1163 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, NULL
);
1164 mutex_lock(&dev
->struct_mutex
);
1168 return i915_gem_object_wait_rendering__tail(obj
, ring
);
1172 * Called when user space prepares to use an object with the CPU, either
1173 * through the mmap ioctl's mapping or a GTT mapping.
1176 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1177 struct drm_file
*file
)
1179 struct drm_i915_gem_set_domain
*args
= data
;
1180 struct drm_i915_gem_object
*obj
;
1181 uint32_t read_domains
= args
->read_domains
;
1182 uint32_t write_domain
= args
->write_domain
;
1185 /* Only handle setting domains to types used by the CPU. */
1186 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1189 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1192 /* Having something in the write domain implies it's in the read
1193 * domain, and only that read domain. Enforce that in the request.
1195 if (write_domain
!= 0 && read_domains
!= write_domain
)
1198 ret
= i915_mutex_lock_interruptible(dev
);
1202 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1203 if (&obj
->base
== NULL
) {
1208 /* Try to flush the object off the GPU without holding the lock.
1209 * We will repeat the flush holding the lock in the normal manner
1210 * to catch cases where we are gazumped.
1212 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, !write_domain
);
1216 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1217 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1219 /* Silently promote "you're not bound, there was nothing to do"
1220 * to success, since the client was just asking us to
1221 * make sure everything was done.
1226 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1230 drm_gem_object_unreference(&obj
->base
);
1232 mutex_unlock(&dev
->struct_mutex
);
1237 * Called when user space has done writes to this buffer
1240 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1241 struct drm_file
*file
)
1243 struct drm_i915_gem_sw_finish
*args
= data
;
1244 struct drm_i915_gem_object
*obj
;
1247 ret
= i915_mutex_lock_interruptible(dev
);
1251 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1252 if (&obj
->base
== NULL
) {
1257 /* Pinned buffers may be scanout, so flush the cache */
1259 i915_gem_object_flush_cpu_write_domain(obj
);
1261 drm_gem_object_unreference(&obj
->base
);
1263 mutex_unlock(&dev
->struct_mutex
);
1268 * Maps the contents of an object, returning the address it is mapped
1271 * While the mapping holds a reference on the contents of the object, it doesn't
1272 * imply a ref on the object itself.
1275 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1276 struct drm_file
*file
)
1278 struct drm_i915_gem_mmap
*args
= data
;
1279 struct drm_gem_object
*obj
;
1282 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1286 /* prime objects have no backing filp to GEM mmap
1290 drm_gem_object_unreference_unlocked(obj
);
1294 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1295 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1297 drm_gem_object_unreference_unlocked(obj
);
1298 if (IS_ERR((void *)addr
))
1301 args
->addr_ptr
= (uint64_t) addr
;
1307 * i915_gem_fault - fault a page into the GTT
1308 * vma: VMA in question
1311 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1312 * from userspace. The fault handler takes care of binding the object to
1313 * the GTT (if needed), allocating and programming a fence register (again,
1314 * only if needed based on whether the old reg is still valid or the object
1315 * is tiled) and inserting a new PTE into the faulting process.
1317 * Note that the faulting process may involve evicting existing objects
1318 * from the GTT and/or fence registers to make room. So performance may
1319 * suffer if the GTT working set is large or there are few fence registers
1322 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1324 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1325 struct drm_device
*dev
= obj
->base
.dev
;
1326 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1327 pgoff_t page_offset
;
1330 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1332 /* We don't use vmf->pgoff since that has the fake offset */
1333 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1336 ret
= i915_mutex_lock_interruptible(dev
);
1340 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1342 /* Access to snoopable pages through the GTT is incoherent. */
1343 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1348 /* Now bind it into the GTT if needed */
1349 ret
= i915_gem_obj_ggtt_pin(obj
, 0, true, false);
1353 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1357 ret
= i915_gem_object_get_fence(obj
);
1361 obj
->fault_mappable
= true;
1363 pfn
= dev_priv
->gtt
.mappable_base
+ i915_gem_obj_ggtt_offset(obj
);
1367 /* Finally, remap it using the new GTT offset */
1368 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1370 i915_gem_object_unpin(obj
);
1372 mutex_unlock(&dev
->struct_mutex
);
1376 /* If this -EIO is due to a gpu hang, give the reset code a
1377 * chance to clean up the mess. Otherwise return the proper
1379 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
1380 return VM_FAULT_SIGBUS
;
1382 /* Give the error handler a chance to run and move the
1383 * objects off the GPU active list. Next time we service the
1384 * fault, we should be able to transition the page into the
1385 * GTT without touching the GPU (and so avoid further
1386 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1387 * with coherency, just lost writes.
1395 * EBUSY is ok: this just means that another thread
1396 * already did the job.
1398 return VM_FAULT_NOPAGE
;
1400 return VM_FAULT_OOM
;
1402 return VM_FAULT_SIGBUS
;
1404 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1405 return VM_FAULT_SIGBUS
;
1410 * i915_gem_release_mmap - remove physical page mappings
1411 * @obj: obj in question
1413 * Preserve the reservation of the mmapping with the DRM core code, but
1414 * relinquish ownership of the pages back to the system.
1416 * It is vital that we remove the page mapping if we have mapped a tiled
1417 * object through the GTT and then lose the fence register due to
1418 * resource pressure. Similarly if the object has been moved out of the
1419 * aperture, than pages mapped into userspace must be revoked. Removing the
1420 * mapping will then trigger a page fault on the next user access, allowing
1421 * fixup by i915_gem_fault().
1424 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1426 if (!obj
->fault_mappable
)
1429 if (obj
->base
.dev
->dev_mapping
)
1430 unmap_mapping_range(obj
->base
.dev
->dev_mapping
,
1431 (loff_t
)obj
->base
.map_list
.hash
.key
<<PAGE_SHIFT
,
1434 obj
->fault_mappable
= false;
1438 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1442 if (INTEL_INFO(dev
)->gen
>= 4 ||
1443 tiling_mode
== I915_TILING_NONE
)
1446 /* Previous chips need a power-of-two fence region when tiling */
1447 if (INTEL_INFO(dev
)->gen
== 3)
1448 gtt_size
= 1024*1024;
1450 gtt_size
= 512*1024;
1452 while (gtt_size
< size
)
1459 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1460 * @obj: object to check
1462 * Return the required GTT alignment for an object, taking into account
1463 * potential fence register mapping.
1466 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1467 int tiling_mode
, bool fenced
)
1470 * Minimum alignment is 4k (GTT page size), but might be greater
1471 * if a fence register is needed for the object.
1473 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1474 tiling_mode
== I915_TILING_NONE
)
1478 * Previous chips need to be aligned to the size of the smallest
1479 * fence register that can contain the object.
1481 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1484 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1486 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1489 if (obj
->base
.map_list
.map
)
1492 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1494 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1498 /* Badly fragmented mmap space? The only way we can recover
1499 * space is by destroying unwanted objects. We can't randomly release
1500 * mmap_offsets as userspace expects them to be persistent for the
1501 * lifetime of the objects. The closest we can is to release the
1502 * offsets on purgeable objects by truncating it and marking it purged,
1503 * which prevents userspace from ever using that object again.
1505 i915_gem_purge(dev_priv
, obj
->base
.size
>> PAGE_SHIFT
);
1506 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1510 i915_gem_shrink_all(dev_priv
);
1511 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1513 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
1518 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1520 if (!obj
->base
.map_list
.map
)
1523 drm_gem_free_mmap_offset(&obj
->base
);
1527 i915_gem_mmap_gtt(struct drm_file
*file
,
1528 struct drm_device
*dev
,
1532 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1533 struct drm_i915_gem_object
*obj
;
1536 ret
= i915_mutex_lock_interruptible(dev
);
1540 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1541 if (&obj
->base
== NULL
) {
1546 if (obj
->base
.size
> dev_priv
->gtt
.mappable_end
) {
1551 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1552 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1557 ret
= i915_gem_object_create_mmap_offset(obj
);
1561 *offset
= (u64
)obj
->base
.map_list
.hash
.key
<< PAGE_SHIFT
;
1564 drm_gem_object_unreference(&obj
->base
);
1566 mutex_unlock(&dev
->struct_mutex
);
1571 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1573 * @data: GTT mapping ioctl data
1574 * @file: GEM object info
1576 * Simply returns the fake offset to userspace so it can mmap it.
1577 * The mmap call will end up in drm_gem_mmap(), which will set things
1578 * up so we can get faults in the handler above.
1580 * The fault handler will take care of binding the object into the GTT
1581 * (since it may have been evicted to make room for something), allocating
1582 * a fence register, and mapping the appropriate aperture address into
1586 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1587 struct drm_file
*file
)
1589 struct drm_i915_gem_mmap_gtt
*args
= data
;
1591 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1594 /* Immediately discard the backing storage */
1596 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1598 struct inode
*inode
;
1600 i915_gem_object_free_mmap_offset(obj
);
1602 if (obj
->base
.filp
== NULL
)
1605 /* Our goal here is to return as much of the memory as
1606 * is possible back to the system as we are called from OOM.
1607 * To do this we must instruct the shmfs to drop all of its
1608 * backing pages, *now*.
1610 inode
= file_inode(obj
->base
.filp
);
1611 shmem_truncate_range(inode
, 0, (loff_t
)-1);
1613 obj
->madv
= __I915_MADV_PURGED
;
1617 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1619 return obj
->madv
== I915_MADV_DONTNEED
;
1623 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1625 struct sg_page_iter sg_iter
;
1628 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1630 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1632 /* In the event of a disaster, abandon all caches and
1633 * hope for the best.
1635 WARN_ON(ret
!= -EIO
);
1636 i915_gem_clflush_object(obj
);
1637 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
1640 if (i915_gem_object_needs_bit17_swizzle(obj
))
1641 i915_gem_object_save_bit_17_swizzle(obj
);
1643 if (obj
->madv
== I915_MADV_DONTNEED
)
1646 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
1647 struct page
*page
= sg_page_iter_page(&sg_iter
);
1650 set_page_dirty(page
);
1652 if (obj
->madv
== I915_MADV_WILLNEED
)
1653 mark_page_accessed(page
);
1655 page_cache_release(page
);
1659 sg_free_table(obj
->pages
);
1664 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
1666 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1668 if (obj
->pages
== NULL
)
1671 if (obj
->pages_pin_count
)
1674 BUG_ON(i915_gem_obj_ggtt_bound(obj
));
1676 /* ->put_pages might need to allocate memory for the bit17 swizzle
1677 * array, hence protect them from being reaped by removing them from gtt
1679 list_del(&obj
->global_list
);
1681 ops
->put_pages(obj
);
1684 if (i915_gem_object_is_purgeable(obj
))
1685 i915_gem_object_truncate(obj
);
1691 __i915_gem_shrink(struct drm_i915_private
*dev_priv
, long target
,
1692 bool purgeable_only
)
1694 struct drm_i915_gem_object
*obj
, *next
;
1695 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
1698 list_for_each_entry_safe(obj
, next
,
1699 &dev_priv
->mm
.unbound_list
,
1701 if ((i915_gem_object_is_purgeable(obj
) || !purgeable_only
) &&
1702 i915_gem_object_put_pages(obj
) == 0) {
1703 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1704 if (count
>= target
)
1709 list_for_each_entry_safe(obj
, next
, &vm
->inactive_list
, mm_list
) {
1710 if ((i915_gem_object_is_purgeable(obj
) || !purgeable_only
) &&
1711 i915_gem_object_unbind(obj
) == 0 &&
1712 i915_gem_object_put_pages(obj
) == 0) {
1713 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1714 if (count
>= target
)
1723 i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
)
1725 return __i915_gem_shrink(dev_priv
, target
, true);
1729 i915_gem_shrink_all(struct drm_i915_private
*dev_priv
)
1731 struct drm_i915_gem_object
*obj
, *next
;
1733 i915_gem_evict_everything(dev_priv
->dev
);
1735 list_for_each_entry_safe(obj
, next
, &dev_priv
->mm
.unbound_list
,
1737 i915_gem_object_put_pages(obj
);
1741 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
1743 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1745 struct address_space
*mapping
;
1746 struct sg_table
*st
;
1747 struct scatterlist
*sg
;
1748 struct sg_page_iter sg_iter
;
1750 unsigned long last_pfn
= 0; /* suppress gcc warning */
1753 /* Assert that the object is not currently in any GPU domain. As it
1754 * wasn't in the GTT, there shouldn't be any way it could have been in
1757 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
1758 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
1760 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
1764 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1765 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
1771 /* Get the list of pages out of our struct file. They'll be pinned
1772 * at this point until we release them.
1774 * Fail silently without starting the shrinker
1776 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
1777 gfp
= mapping_gfp_mask(mapping
);
1778 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1779 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1782 for (i
= 0; i
< page_count
; i
++) {
1783 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1785 i915_gem_purge(dev_priv
, page_count
);
1786 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1789 /* We've tried hard to allocate the memory by reaping
1790 * our own buffer, now let the real VM do its job and
1791 * go down in flames if truly OOM.
1793 gfp
&= ~(__GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
);
1794 gfp
|= __GFP_IO
| __GFP_WAIT
;
1796 i915_gem_shrink_all(dev_priv
);
1797 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1801 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1802 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1804 #ifdef CONFIG_SWIOTLB
1805 if (swiotlb_nr_tbl()) {
1807 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
1812 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
1816 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
1818 sg
->length
+= PAGE_SIZE
;
1820 last_pfn
= page_to_pfn(page
);
1822 #ifdef CONFIG_SWIOTLB
1823 if (!swiotlb_nr_tbl())
1828 if (i915_gem_object_needs_bit17_swizzle(obj
))
1829 i915_gem_object_do_bit_17_swizzle(obj
);
1835 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
1836 page_cache_release(sg_page_iter_page(&sg_iter
));
1839 return PTR_ERR(page
);
1842 /* Ensure that the associated pages are gathered from the backing storage
1843 * and pinned into our object. i915_gem_object_get_pages() may be called
1844 * multiple times before they are released by a single call to
1845 * i915_gem_object_put_pages() - once the pages are no longer referenced
1846 * either as a result of memory pressure (reaping pages under the shrinker)
1847 * or as the object is itself released.
1850 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
1852 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1853 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1859 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1860 DRM_ERROR("Attempting to obtain a purgeable object\n");
1864 BUG_ON(obj
->pages_pin_count
);
1866 ret
= ops
->get_pages(obj
);
1870 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
1875 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1876 struct intel_ring_buffer
*ring
)
1878 struct drm_device
*dev
= obj
->base
.dev
;
1879 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1880 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
1881 u32 seqno
= intel_ring_get_seqno(ring
);
1883 BUG_ON(ring
== NULL
);
1884 if (obj
->ring
!= ring
&& obj
->last_write_seqno
) {
1885 /* Keep the seqno relative to the current ring */
1886 obj
->last_write_seqno
= seqno
;
1890 /* Add a reference if we're newly entering the active list. */
1892 drm_gem_object_reference(&obj
->base
);
1896 /* Move from whatever list we were on to the tail of execution. */
1897 list_move_tail(&obj
->mm_list
, &vm
->active_list
);
1898 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
1900 obj
->last_read_seqno
= seqno
;
1902 if (obj
->fenced_gpu_access
) {
1903 obj
->last_fenced_seqno
= seqno
;
1905 /* Bump MRU to take account of the delayed flush */
1906 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1907 struct drm_i915_fence_reg
*reg
;
1909 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
1910 list_move_tail(®
->lru_list
,
1911 &dev_priv
->mm
.fence_list
);
1917 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
1919 struct drm_device
*dev
= obj
->base
.dev
;
1920 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1921 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
1923 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
1924 BUG_ON(!obj
->active
);
1926 list_move_tail(&obj
->mm_list
, &vm
->inactive_list
);
1928 list_del_init(&obj
->ring_list
);
1931 obj
->last_read_seqno
= 0;
1932 obj
->last_write_seqno
= 0;
1933 obj
->base
.write_domain
= 0;
1935 obj
->last_fenced_seqno
= 0;
1936 obj
->fenced_gpu_access
= false;
1939 drm_gem_object_unreference(&obj
->base
);
1941 WARN_ON(i915_verify_lists(dev
));
1945 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
1947 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1948 struct intel_ring_buffer
*ring
;
1951 /* Carefully retire all requests without writing to the rings */
1952 for_each_ring(ring
, dev_priv
, i
) {
1953 ret
= intel_ring_idle(ring
);
1957 i915_gem_retire_requests(dev
);
1959 /* Finally reset hw state */
1960 for_each_ring(ring
, dev_priv
, i
) {
1961 intel_ring_init_seqno(ring
, seqno
);
1963 for (j
= 0; j
< ARRAY_SIZE(ring
->sync_seqno
); j
++)
1964 ring
->sync_seqno
[j
] = 0;
1970 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
1972 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1978 /* HWS page needs to be set less than what we
1979 * will inject to ring
1981 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
1985 /* Carefully set the last_seqno value so that wrap
1986 * detection still works
1988 dev_priv
->next_seqno
= seqno
;
1989 dev_priv
->last_seqno
= seqno
- 1;
1990 if (dev_priv
->last_seqno
== 0)
1991 dev_priv
->last_seqno
--;
1997 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
1999 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2001 /* reserve 0 for non-seqno */
2002 if (dev_priv
->next_seqno
== 0) {
2003 int ret
= i915_gem_init_seqno(dev
, 0);
2007 dev_priv
->next_seqno
= 1;
2010 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2014 int __i915_add_request(struct intel_ring_buffer
*ring
,
2015 struct drm_file
*file
,
2016 struct drm_i915_gem_object
*obj
,
2019 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
2020 struct drm_i915_gem_request
*request
;
2021 u32 request_ring_position
, request_start
;
2025 request_start
= intel_ring_get_tail(ring
);
2027 * Emit any outstanding flushes - execbuf can fail to emit the flush
2028 * after having emitted the batchbuffer command. Hence we need to fix
2029 * things up similar to emitting the lazy request. The difference here
2030 * is that the flush _must_ happen before the next request, no matter
2033 ret
= intel_ring_flush_all_caches(ring
);
2037 request
= kmalloc(sizeof(*request
), GFP_KERNEL
);
2038 if (request
== NULL
)
2042 /* Record the position of the start of the request so that
2043 * should we detect the updated seqno part-way through the
2044 * GPU processing the request, we never over-estimate the
2045 * position of the head.
2047 request_ring_position
= intel_ring_get_tail(ring
);
2049 ret
= ring
->add_request(ring
);
2055 request
->seqno
= intel_ring_get_seqno(ring
);
2056 request
->ring
= ring
;
2057 request
->head
= request_start
;
2058 request
->tail
= request_ring_position
;
2059 request
->ctx
= ring
->last_context
;
2060 request
->batch_obj
= obj
;
2062 /* Whilst this request exists, batch_obj will be on the
2063 * active_list, and so will hold the active reference. Only when this
2064 * request is retired will the the batch_obj be moved onto the
2065 * inactive_list and lose its active reference. Hence we do not need
2066 * to explicitly hold another reference here.
2070 i915_gem_context_reference(request
->ctx
);
2072 request
->emitted_jiffies
= jiffies
;
2073 was_empty
= list_empty(&ring
->request_list
);
2074 list_add_tail(&request
->list
, &ring
->request_list
);
2075 request
->file_priv
= NULL
;
2078 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2080 spin_lock(&file_priv
->mm
.lock
);
2081 request
->file_priv
= file_priv
;
2082 list_add_tail(&request
->client_list
,
2083 &file_priv
->mm
.request_list
);
2084 spin_unlock(&file_priv
->mm
.lock
);
2087 trace_i915_gem_request_add(ring
, request
->seqno
);
2088 ring
->outstanding_lazy_request
= 0;
2090 if (!dev_priv
->ums
.mm_suspended
) {
2091 i915_queue_hangcheck(ring
->dev
);
2094 queue_delayed_work(dev_priv
->wq
,
2095 &dev_priv
->mm
.retire_work
,
2096 round_jiffies_up_relative(HZ
));
2097 intel_mark_busy(dev_priv
->dev
);
2102 *out_seqno
= request
->seqno
;
2107 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2109 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2114 spin_lock(&file_priv
->mm
.lock
);
2115 if (request
->file_priv
) {
2116 list_del(&request
->client_list
);
2117 request
->file_priv
= NULL
;
2119 spin_unlock(&file_priv
->mm
.lock
);
2122 static bool i915_head_inside_object(u32 acthd
, struct drm_i915_gem_object
*obj
,
2123 struct i915_address_space
*vm
)
2125 if (acthd
>= i915_gem_obj_offset(obj
, vm
) &&
2126 acthd
< i915_gem_obj_offset(obj
, vm
) + obj
->base
.size
)
2132 static bool i915_head_inside_request(const u32 acthd_unmasked
,
2133 const u32 request_start
,
2134 const u32 request_end
)
2136 const u32 acthd
= acthd_unmasked
& HEAD_ADDR
;
2138 if (request_start
< request_end
) {
2139 if (acthd
>= request_start
&& acthd
< request_end
)
2141 } else if (request_start
> request_end
) {
2142 if (acthd
>= request_start
|| acthd
< request_end
)
2149 static struct i915_address_space
*
2150 request_to_vm(struct drm_i915_gem_request
*request
)
2152 struct drm_i915_private
*dev_priv
= request
->ring
->dev
->dev_private
;
2153 struct i915_address_space
*vm
;
2155 vm
= &dev_priv
->gtt
.base
;
2160 static bool i915_request_guilty(struct drm_i915_gem_request
*request
,
2161 const u32 acthd
, bool *inside
)
2163 /* There is a possibility that unmasked head address
2164 * pointing inside the ring, matches the batch_obj address range.
2165 * However this is extremely unlikely.
2167 if (request
->batch_obj
) {
2168 if (i915_head_inside_object(acthd
, request
->batch_obj
,
2169 request_to_vm(request
))) {
2175 if (i915_head_inside_request(acthd
, request
->head
, request
->tail
)) {
2183 static void i915_set_reset_status(struct intel_ring_buffer
*ring
,
2184 struct drm_i915_gem_request
*request
,
2187 struct i915_ctx_hang_stats
*hs
= NULL
;
2188 bool inside
, guilty
;
2189 unsigned long offset
= 0;
2191 /* Innocent until proven guilty */
2194 if (request
->batch_obj
)
2195 offset
= i915_gem_obj_offset(request
->batch_obj
,
2196 request_to_vm(request
));
2198 if (ring
->hangcheck
.action
!= wait
&&
2199 i915_request_guilty(request
, acthd
, &inside
)) {
2200 DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n",
2202 inside
? "inside" : "flushing",
2204 request
->ctx
? request
->ctx
->id
: 0,
2210 /* If contexts are disabled or this is the default context, use
2211 * file_priv->reset_state
2213 if (request
->ctx
&& request
->ctx
->id
!= DEFAULT_CONTEXT_ID
)
2214 hs
= &request
->ctx
->hang_stats
;
2215 else if (request
->file_priv
)
2216 hs
= &request
->file_priv
->hang_stats
;
2222 hs
->batch_pending
++;
2226 static void i915_gem_free_request(struct drm_i915_gem_request
*request
)
2228 list_del(&request
->list
);
2229 i915_gem_request_remove_from_client(request
);
2232 i915_gem_context_unreference(request
->ctx
);
2237 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
2238 struct intel_ring_buffer
*ring
)
2240 u32 completed_seqno
;
2243 acthd
= intel_ring_get_active_head(ring
);
2244 completed_seqno
= ring
->get_seqno(ring
, false);
2246 while (!list_empty(&ring
->request_list
)) {
2247 struct drm_i915_gem_request
*request
;
2249 request
= list_first_entry(&ring
->request_list
,
2250 struct drm_i915_gem_request
,
2253 if (request
->seqno
> completed_seqno
)
2254 i915_set_reset_status(ring
, request
, acthd
);
2256 i915_gem_free_request(request
);
2259 while (!list_empty(&ring
->active_list
)) {
2260 struct drm_i915_gem_object
*obj
;
2262 obj
= list_first_entry(&ring
->active_list
,
2263 struct drm_i915_gem_object
,
2266 i915_gem_object_move_to_inactive(obj
);
2270 void i915_gem_restore_fences(struct drm_device
*dev
)
2272 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2275 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2276 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2279 * Commit delayed tiling changes if we have an object still
2280 * attached to the fence, otherwise just clear the fence.
2283 i915_gem_object_update_fence(reg
->obj
, reg
,
2284 reg
->obj
->tiling_mode
);
2286 i915_gem_write_fence(dev
, i
, NULL
);
2291 void i915_gem_reset(struct drm_device
*dev
)
2293 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2294 struct intel_ring_buffer
*ring
;
2297 for_each_ring(ring
, dev_priv
, i
)
2298 i915_gem_reset_ring_lists(dev_priv
, ring
);
2300 i915_gem_restore_fences(dev
);
2304 * This function clears the request list as sequence numbers are passed.
2307 i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
)
2311 if (list_empty(&ring
->request_list
))
2314 WARN_ON(i915_verify_lists(ring
->dev
));
2316 seqno
= ring
->get_seqno(ring
, true);
2318 while (!list_empty(&ring
->request_list
)) {
2319 struct drm_i915_gem_request
*request
;
2321 request
= list_first_entry(&ring
->request_list
,
2322 struct drm_i915_gem_request
,
2325 if (!i915_seqno_passed(seqno
, request
->seqno
))
2328 trace_i915_gem_request_retire(ring
, request
->seqno
);
2329 /* We know the GPU must have read the request to have
2330 * sent us the seqno + interrupt, so use the position
2331 * of tail of the request to update the last known position
2334 ring
->last_retired_head
= request
->tail
;
2336 i915_gem_free_request(request
);
2339 /* Move any buffers on the active list that are no longer referenced
2340 * by the ringbuffer to the flushing/inactive lists as appropriate.
2342 while (!list_empty(&ring
->active_list
)) {
2343 struct drm_i915_gem_object
*obj
;
2345 obj
= list_first_entry(&ring
->active_list
,
2346 struct drm_i915_gem_object
,
2349 if (!i915_seqno_passed(seqno
, obj
->last_read_seqno
))
2352 i915_gem_object_move_to_inactive(obj
);
2355 if (unlikely(ring
->trace_irq_seqno
&&
2356 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
2357 ring
->irq_put(ring
);
2358 ring
->trace_irq_seqno
= 0;
2361 WARN_ON(i915_verify_lists(ring
->dev
));
2365 i915_gem_retire_requests(struct drm_device
*dev
)
2367 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2368 struct intel_ring_buffer
*ring
;
2371 for_each_ring(ring
, dev_priv
, i
)
2372 i915_gem_retire_requests_ring(ring
);
2376 i915_gem_retire_work_handler(struct work_struct
*work
)
2378 drm_i915_private_t
*dev_priv
;
2379 struct drm_device
*dev
;
2380 struct intel_ring_buffer
*ring
;
2384 dev_priv
= container_of(work
, drm_i915_private_t
,
2385 mm
.retire_work
.work
);
2386 dev
= dev_priv
->dev
;
2388 /* Come back later if the device is busy... */
2389 if (!mutex_trylock(&dev
->struct_mutex
)) {
2390 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2391 round_jiffies_up_relative(HZ
));
2395 i915_gem_retire_requests(dev
);
2397 /* Send a periodic flush down the ring so we don't hold onto GEM
2398 * objects indefinitely.
2401 for_each_ring(ring
, dev_priv
, i
) {
2402 if (ring
->gpu_caches_dirty
)
2403 i915_add_request(ring
, NULL
);
2405 idle
&= list_empty(&ring
->request_list
);
2408 if (!dev_priv
->ums
.mm_suspended
&& !idle
)
2409 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2410 round_jiffies_up_relative(HZ
));
2412 intel_mark_idle(dev
);
2414 mutex_unlock(&dev
->struct_mutex
);
2418 * Ensures that an object will eventually get non-busy by flushing any required
2419 * write domains, emitting any outstanding lazy request and retiring and
2420 * completed requests.
2423 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2428 ret
= i915_gem_check_olr(obj
->ring
, obj
->last_read_seqno
);
2432 i915_gem_retire_requests_ring(obj
->ring
);
2439 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2440 * @DRM_IOCTL_ARGS: standard ioctl arguments
2442 * Returns 0 if successful, else an error is returned with the remaining time in
2443 * the timeout parameter.
2444 * -ETIME: object is still busy after timeout
2445 * -ERESTARTSYS: signal interrupted the wait
2446 * -ENONENT: object doesn't exist
2447 * Also possible, but rare:
2448 * -EAGAIN: GPU wedged
2450 * -ENODEV: Internal IRQ fail
2451 * -E?: The add request failed
2453 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2454 * non-zero timeout parameter the wait ioctl will wait for the given number of
2455 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2456 * without holding struct_mutex the object may become re-busied before this
2457 * function completes. A similar but shorter * race condition exists in the busy
2461 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2463 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2464 struct drm_i915_gem_wait
*args
= data
;
2465 struct drm_i915_gem_object
*obj
;
2466 struct intel_ring_buffer
*ring
= NULL
;
2467 struct timespec timeout_stack
, *timeout
= NULL
;
2468 unsigned reset_counter
;
2472 if (args
->timeout_ns
>= 0) {
2473 timeout_stack
= ns_to_timespec(args
->timeout_ns
);
2474 timeout
= &timeout_stack
;
2477 ret
= i915_mutex_lock_interruptible(dev
);
2481 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2482 if (&obj
->base
== NULL
) {
2483 mutex_unlock(&dev
->struct_mutex
);
2487 /* Need to make sure the object gets inactive eventually. */
2488 ret
= i915_gem_object_flush_active(obj
);
2493 seqno
= obj
->last_read_seqno
;
2500 /* Do this after OLR check to make sure we make forward progress polling
2501 * on this IOCTL with a 0 timeout (like busy ioctl)
2503 if (!args
->timeout_ns
) {
2508 drm_gem_object_unreference(&obj
->base
);
2509 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
2510 mutex_unlock(&dev
->struct_mutex
);
2512 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, timeout
);
2514 args
->timeout_ns
= timespec_to_ns(timeout
);
2518 drm_gem_object_unreference(&obj
->base
);
2519 mutex_unlock(&dev
->struct_mutex
);
2524 * i915_gem_object_sync - sync an object to a ring.
2526 * @obj: object which may be in use on another ring.
2527 * @to: ring we wish to use the object on. May be NULL.
2529 * This code is meant to abstract object synchronization with the GPU.
2530 * Calling with NULL implies synchronizing the object with the CPU
2531 * rather than a particular GPU ring.
2533 * Returns 0 if successful, else propagates up the lower layer error.
2536 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2537 struct intel_ring_buffer
*to
)
2539 struct intel_ring_buffer
*from
= obj
->ring
;
2543 if (from
== NULL
|| to
== from
)
2546 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2547 return i915_gem_object_wait_rendering(obj
, false);
2549 idx
= intel_ring_sync_index(from
, to
);
2551 seqno
= obj
->last_read_seqno
;
2552 if (seqno
<= from
->sync_seqno
[idx
])
2555 ret
= i915_gem_check_olr(obj
->ring
, seqno
);
2559 ret
= to
->sync_to(to
, from
, seqno
);
2561 /* We use last_read_seqno because sync_to()
2562 * might have just caused seqno wrap under
2565 from
->sync_seqno
[idx
] = obj
->last_read_seqno
;
2570 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
2572 u32 old_write_domain
, old_read_domains
;
2574 /* Force a pagefault for domain tracking on next user access */
2575 i915_gem_release_mmap(obj
);
2577 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2580 /* Wait for any direct GTT access to complete */
2583 old_read_domains
= obj
->base
.read_domains
;
2584 old_write_domain
= obj
->base
.write_domain
;
2586 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2587 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2589 trace_i915_gem_object_change_domain(obj
,
2595 * Unbinds an object from the GTT aperture.
2598 i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
2600 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2601 struct i915_vma
*vma
;
2604 if (!i915_gem_obj_ggtt_bound(obj
))
2610 BUG_ON(obj
->pages
== NULL
);
2612 ret
= i915_gem_object_finish_gpu(obj
);
2615 /* Continue on if we fail due to EIO, the GPU is hung so we
2616 * should be safe and we need to cleanup or else we might
2617 * cause memory corruption through use-after-free.
2620 i915_gem_object_finish_gtt(obj
);
2622 /* release the fence reg _after_ flushing */
2623 ret
= i915_gem_object_put_fence(obj
);
2627 trace_i915_gem_object_unbind(obj
);
2629 if (obj
->has_global_gtt_mapping
)
2630 i915_gem_gtt_unbind_object(obj
);
2631 if (obj
->has_aliasing_ppgtt_mapping
) {
2632 i915_ppgtt_unbind_object(dev_priv
->mm
.aliasing_ppgtt
, obj
);
2633 obj
->has_aliasing_ppgtt_mapping
= 0;
2635 i915_gem_gtt_finish_object(obj
);
2636 i915_gem_object_unpin_pages(obj
);
2638 list_del(&obj
->mm_list
);
2639 /* Avoid an unnecessary call to unbind on rebind. */
2640 obj
->map_and_fenceable
= true;
2642 vma
= i915_gem_obj_to_vma(obj
, &dev_priv
->gtt
.base
);
2643 list_del(&vma
->vma_link
);
2644 drm_mm_remove_node(&vma
->node
);
2645 i915_gem_vma_destroy(vma
);
2647 /* Since the unbound list is global, only move to that list if
2648 * no more VMAs exist.
2649 * NB: Until we have real VMAs there will only ever be one */
2650 WARN_ON(!list_empty(&obj
->vma_list
));
2651 if (list_empty(&obj
->vma_list
))
2652 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2657 int i915_gpu_idle(struct drm_device
*dev
)
2659 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2660 struct intel_ring_buffer
*ring
;
2663 /* Flush everything onto the inactive list. */
2664 for_each_ring(ring
, dev_priv
, i
) {
2665 ret
= i915_switch_context(ring
, NULL
, DEFAULT_CONTEXT_ID
);
2669 ret
= intel_ring_idle(ring
);
2677 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
2678 struct drm_i915_gem_object
*obj
)
2680 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2682 int fence_pitch_shift
;
2684 if (INTEL_INFO(dev
)->gen
>= 6) {
2685 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
2686 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2688 fence_reg
= FENCE_REG_965_0
;
2689 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
2692 fence_reg
+= reg
* 8;
2694 /* To w/a incoherency with non-atomic 64-bit register updates,
2695 * we split the 64-bit update into two 32-bit writes. In order
2696 * for a partial fence not to be evaluated between writes, we
2697 * precede the update with write to turn off the fence register,
2698 * and only enable the fence as the last step.
2700 * For extra levels of paranoia, we make sure each step lands
2701 * before applying the next step.
2703 I915_WRITE(fence_reg
, 0);
2704 POSTING_READ(fence_reg
);
2707 u32 size
= i915_gem_obj_ggtt_size(obj
);
2710 val
= (uint64_t)((i915_gem_obj_ggtt_offset(obj
) + size
- 4096) &
2712 val
|= i915_gem_obj_ggtt_offset(obj
) & 0xfffff000;
2713 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
2714 if (obj
->tiling_mode
== I915_TILING_Y
)
2715 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2716 val
|= I965_FENCE_REG_VALID
;
2718 I915_WRITE(fence_reg
+ 4, val
>> 32);
2719 POSTING_READ(fence_reg
+ 4);
2721 I915_WRITE(fence_reg
+ 0, val
);
2722 POSTING_READ(fence_reg
);
2724 I915_WRITE(fence_reg
+ 4, 0);
2725 POSTING_READ(fence_reg
+ 4);
2729 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
2730 struct drm_i915_gem_object
*obj
)
2732 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2736 u32 size
= i915_gem_obj_ggtt_size(obj
);
2740 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I915_FENCE_START_MASK
) ||
2741 (size
& -size
) != size
||
2742 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
2743 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2744 i915_gem_obj_ggtt_offset(obj
), obj
->map_and_fenceable
, size
);
2746 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2751 /* Note: pitch better be a power of two tile widths */
2752 pitch_val
= obj
->stride
/ tile_width
;
2753 pitch_val
= ffs(pitch_val
) - 1;
2755 val
= i915_gem_obj_ggtt_offset(obj
);
2756 if (obj
->tiling_mode
== I915_TILING_Y
)
2757 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2758 val
|= I915_FENCE_SIZE_BITS(size
);
2759 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2760 val
|= I830_FENCE_REG_VALID
;
2765 reg
= FENCE_REG_830_0
+ reg
* 4;
2767 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
2769 I915_WRITE(reg
, val
);
2773 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
2774 struct drm_i915_gem_object
*obj
)
2776 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2780 u32 size
= i915_gem_obj_ggtt_size(obj
);
2783 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I830_FENCE_START_MASK
) ||
2784 (size
& -size
) != size
||
2785 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
2786 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2787 i915_gem_obj_ggtt_offset(obj
), size
);
2789 pitch_val
= obj
->stride
/ 128;
2790 pitch_val
= ffs(pitch_val
) - 1;
2792 val
= i915_gem_obj_ggtt_offset(obj
);
2793 if (obj
->tiling_mode
== I915_TILING_Y
)
2794 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2795 val
|= I830_FENCE_SIZE_BITS(size
);
2796 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2797 val
|= I830_FENCE_REG_VALID
;
2801 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
2802 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
2805 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
2807 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
2810 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
2811 struct drm_i915_gem_object
*obj
)
2813 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2815 /* Ensure that all CPU reads are completed before installing a fence
2816 * and all writes before removing the fence.
2818 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
2821 WARN(obj
&& (!obj
->stride
|| !obj
->tiling_mode
),
2822 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
2823 obj
->stride
, obj
->tiling_mode
);
2825 switch (INTEL_INFO(dev
)->gen
) {
2829 case 4: i965_write_fence_reg(dev
, reg
, obj
); break;
2830 case 3: i915_write_fence_reg(dev
, reg
, obj
); break;
2831 case 2: i830_write_fence_reg(dev
, reg
, obj
); break;
2835 /* And similarly be paranoid that no direct access to this region
2836 * is reordered to before the fence is installed.
2838 if (i915_gem_object_needs_mb(obj
))
2842 static inline int fence_number(struct drm_i915_private
*dev_priv
,
2843 struct drm_i915_fence_reg
*fence
)
2845 return fence
- dev_priv
->fence_regs
;
2848 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
2849 struct drm_i915_fence_reg
*fence
,
2852 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2853 int reg
= fence_number(dev_priv
, fence
);
2855 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
2858 obj
->fence_reg
= reg
;
2860 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
2862 obj
->fence_reg
= I915_FENCE_REG_NONE
;
2864 list_del_init(&fence
->lru_list
);
2866 obj
->fence_dirty
= false;
2870 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
2872 if (obj
->last_fenced_seqno
) {
2873 int ret
= i915_wait_seqno(obj
->ring
, obj
->last_fenced_seqno
);
2877 obj
->last_fenced_seqno
= 0;
2880 obj
->fenced_gpu_access
= false;
2885 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
2887 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2888 struct drm_i915_fence_reg
*fence
;
2891 ret
= i915_gem_object_wait_fence(obj
);
2895 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
2898 fence
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2900 i915_gem_object_fence_lost(obj
);
2901 i915_gem_object_update_fence(obj
, fence
, false);
2906 static struct drm_i915_fence_reg
*
2907 i915_find_fence_reg(struct drm_device
*dev
)
2909 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2910 struct drm_i915_fence_reg
*reg
, *avail
;
2913 /* First try to find a free reg */
2915 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2916 reg
= &dev_priv
->fence_regs
[i
];
2920 if (!reg
->pin_count
)
2927 /* None available, try to steal one or wait for a user to finish */
2928 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
2939 * i915_gem_object_get_fence - set up fencing for an object
2940 * @obj: object to map through a fence reg
2942 * When mapping objects through the GTT, userspace wants to be able to write
2943 * to them without having to worry about swizzling if the object is tiled.
2944 * This function walks the fence regs looking for a free one for @obj,
2945 * stealing one if it can't find any.
2947 * It then sets up the reg based on the object's properties: address, pitch
2948 * and tiling format.
2950 * For an untiled surface, this removes any existing fence.
2953 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
2955 struct drm_device
*dev
= obj
->base
.dev
;
2956 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2957 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
2958 struct drm_i915_fence_reg
*reg
;
2961 /* Have we updated the tiling parameters upon the object and so
2962 * will need to serialise the write to the associated fence register?
2964 if (obj
->fence_dirty
) {
2965 ret
= i915_gem_object_wait_fence(obj
);
2970 /* Just update our place in the LRU if our fence is getting reused. */
2971 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2972 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2973 if (!obj
->fence_dirty
) {
2974 list_move_tail(®
->lru_list
,
2975 &dev_priv
->mm
.fence_list
);
2978 } else if (enable
) {
2979 reg
= i915_find_fence_reg(dev
);
2984 struct drm_i915_gem_object
*old
= reg
->obj
;
2986 ret
= i915_gem_object_wait_fence(old
);
2990 i915_gem_object_fence_lost(old
);
2995 i915_gem_object_update_fence(obj
, reg
, enable
);
3000 static bool i915_gem_valid_gtt_space(struct drm_device
*dev
,
3001 struct drm_mm_node
*gtt_space
,
3002 unsigned long cache_level
)
3004 struct drm_mm_node
*other
;
3006 /* On non-LLC machines we have to be careful when putting differing
3007 * types of snoopable memory together to avoid the prefetcher
3008 * crossing memory domains and dying.
3013 if (!drm_mm_node_allocated(gtt_space
))
3016 if (list_empty(>t_space
->node_list
))
3019 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3020 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3023 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3024 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3030 static void i915_gem_verify_gtt(struct drm_device
*dev
)
3033 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3034 struct drm_i915_gem_object
*obj
;
3037 list_for_each_entry(obj
, &dev_priv
->mm
.gtt_list
, global_list
) {
3038 if (obj
->gtt_space
== NULL
) {
3039 printk(KERN_ERR
"object found on GTT list with no space reserved\n");
3044 if (obj
->cache_level
!= obj
->gtt_space
->color
) {
3045 printk(KERN_ERR
"object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3046 i915_gem_obj_ggtt_offset(obj
),
3047 i915_gem_obj_ggtt_offset(obj
) + i915_gem_obj_ggtt_size(obj
),
3049 obj
->gtt_space
->color
);
3054 if (!i915_gem_valid_gtt_space(dev
,
3056 obj
->cache_level
)) {
3057 printk(KERN_ERR
"invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3058 i915_gem_obj_ggtt_offset(obj
),
3059 i915_gem_obj_ggtt_offset(obj
) + i915_gem_obj_ggtt_size(obj
),
3071 * Finds free space in the GTT aperture and binds the object there.
3074 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
3076 bool map_and_fenceable
,
3079 struct drm_device
*dev
= obj
->base
.dev
;
3080 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3081 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
3082 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
3083 bool mappable
, fenceable
;
3084 size_t gtt_max
= map_and_fenceable
?
3085 dev_priv
->gtt
.mappable_end
: dev_priv
->gtt
.base
.total
;
3086 struct i915_vma
*vma
;
3089 if (WARN_ON(!list_empty(&obj
->vma_list
)))
3092 fence_size
= i915_gem_get_gtt_size(dev
,
3095 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3097 obj
->tiling_mode
, true);
3098 unfenced_alignment
=
3099 i915_gem_get_gtt_alignment(dev
,
3101 obj
->tiling_mode
, false);
3104 alignment
= map_and_fenceable
? fence_alignment
:
3106 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
3107 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
3111 size
= map_and_fenceable
? fence_size
: obj
->base
.size
;
3113 /* If the object is bigger than the entire aperture, reject it early
3114 * before evicting everything in a vain attempt to find space.
3116 if (obj
->base
.size
> gtt_max
) {
3117 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3119 map_and_fenceable
? "mappable" : "total",
3124 ret
= i915_gem_object_get_pages(obj
);
3128 i915_gem_object_pin_pages(obj
);
3130 vma
= i915_gem_vma_create(obj
, &dev_priv
->gtt
.base
);
3137 ret
= drm_mm_insert_node_in_range_generic(&dev_priv
->gtt
.base
.mm
,
3140 obj
->cache_level
, 0, gtt_max
);
3142 ret
= i915_gem_evict_something(dev
, size
, alignment
,
3151 if (WARN_ON(!i915_gem_valid_gtt_space(dev
, &vma
->node
,
3152 obj
->cache_level
))) {
3154 goto err_remove_node
;
3157 ret
= i915_gem_gtt_prepare_object(obj
);
3159 goto err_remove_node
;
3161 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3162 list_add_tail(&obj
->mm_list
, &vm
->inactive_list
);
3163 list_add(&vma
->vma_link
, &obj
->vma_list
);
3166 i915_gem_obj_ggtt_size(obj
) == fence_size
&&
3167 (i915_gem_obj_ggtt_offset(obj
) & (fence_alignment
- 1)) == 0;
3169 mappable
= i915_gem_obj_ggtt_offset(obj
) + obj
->base
.size
<=
3170 dev_priv
->gtt
.mappable_end
;
3172 obj
->map_and_fenceable
= mappable
&& fenceable
;
3174 trace_i915_gem_object_bind(obj
, map_and_fenceable
);
3175 i915_gem_verify_gtt(dev
);
3179 drm_mm_remove_node(&vma
->node
);
3181 i915_gem_vma_destroy(vma
);
3183 i915_gem_object_unpin_pages(obj
);
3188 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
)
3190 /* If we don't have a page list set up, then we're not pinned
3191 * to GPU, and we can ignore the cache flush because it'll happen
3192 * again at bind time.
3194 if (obj
->pages
== NULL
)
3198 * Stolen memory is always coherent with the GPU as it is explicitly
3199 * marked as wc by the system, or the system is cache-coherent.
3204 /* If the GPU is snooping the contents of the CPU cache,
3205 * we do not need to manually clear the CPU cache lines. However,
3206 * the caches are only snooped when the render cache is
3207 * flushed/invalidated. As we always have to emit invalidations
3208 * and flushes when moving into and out of the RENDER domain, correct
3209 * snooping behaviour occurs naturally as the result of our domain
3212 if (obj
->cache_level
!= I915_CACHE_NONE
)
3215 trace_i915_gem_object_clflush(obj
);
3217 drm_clflush_sg(obj
->pages
);
3220 /** Flushes the GTT write domain for the object if it's dirty. */
3222 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3224 uint32_t old_write_domain
;
3226 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3229 /* No actual flushing is required for the GTT write domain. Writes
3230 * to it immediately go to main memory as far as we know, so there's
3231 * no chipset flush. It also doesn't land in render cache.
3233 * However, we do have to enforce the order so that all writes through
3234 * the GTT land before any writes to the device, such as updates to
3239 old_write_domain
= obj
->base
.write_domain
;
3240 obj
->base
.write_domain
= 0;
3242 trace_i915_gem_object_change_domain(obj
,
3243 obj
->base
.read_domains
,
3247 /** Flushes the CPU write domain for the object if it's dirty. */
3249 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3251 uint32_t old_write_domain
;
3253 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3256 i915_gem_clflush_object(obj
);
3257 i915_gem_chipset_flush(obj
->base
.dev
);
3258 old_write_domain
= obj
->base
.write_domain
;
3259 obj
->base
.write_domain
= 0;
3261 trace_i915_gem_object_change_domain(obj
,
3262 obj
->base
.read_domains
,
3267 * Moves a single object to the GTT read, and possibly write domain.
3269 * This function returns when the move is complete, including waiting on
3273 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3275 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
3276 uint32_t old_write_domain
, old_read_domains
;
3279 /* Not valid to be called on unbound objects. */
3280 if (!i915_gem_obj_ggtt_bound(obj
))
3283 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3286 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3290 i915_gem_object_flush_cpu_write_domain(obj
);
3292 /* Serialise direct access to this object with the barriers for
3293 * coherent writes from the GPU, by effectively invalidating the
3294 * GTT domain upon first access.
3296 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3299 old_write_domain
= obj
->base
.write_domain
;
3300 old_read_domains
= obj
->base
.read_domains
;
3302 /* It should now be out of any other write domains, and we can update
3303 * the domain values for our changes.
3305 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3306 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3308 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3309 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3313 trace_i915_gem_object_change_domain(obj
,
3317 /* And bump the LRU for this access */
3318 if (i915_gem_object_is_inactive(obj
))
3319 list_move_tail(&obj
->mm_list
,
3320 &dev_priv
->gtt
.base
.inactive_list
);
3325 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3326 enum i915_cache_level cache_level
)
3328 struct drm_device
*dev
= obj
->base
.dev
;
3329 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3330 struct i915_vma
*vma
;
3333 if (obj
->cache_level
== cache_level
)
3336 if (obj
->pin_count
) {
3337 DRM_DEBUG("can not change the cache level of pinned objects\n");
3341 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
3342 if (!i915_gem_valid_gtt_space(dev
, &vma
->node
, cache_level
)) {
3343 ret
= i915_gem_object_unbind(obj
);
3351 if (i915_gem_obj_bound_any(obj
)) {
3352 ret
= i915_gem_object_finish_gpu(obj
);
3356 i915_gem_object_finish_gtt(obj
);
3358 /* Before SandyBridge, you could not use tiling or fence
3359 * registers with snooped memory, so relinquish any fences
3360 * currently pointing to our region in the aperture.
3362 if (INTEL_INFO(dev
)->gen
< 6) {
3363 ret
= i915_gem_object_put_fence(obj
);
3368 if (obj
->has_global_gtt_mapping
)
3369 i915_gem_gtt_bind_object(obj
, cache_level
);
3370 if (obj
->has_aliasing_ppgtt_mapping
)
3371 i915_ppgtt_bind_object(dev_priv
->mm
.aliasing_ppgtt
,
3375 if (cache_level
== I915_CACHE_NONE
) {
3376 u32 old_read_domains
, old_write_domain
;
3378 /* If we're coming from LLC cached, then we haven't
3379 * actually been tracking whether the data is in the
3380 * CPU cache or not, since we only allow one bit set
3381 * in obj->write_domain and have been skipping the clflushes.
3382 * Just set it to the CPU cache for now.
3384 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
3385 WARN_ON(obj
->base
.read_domains
& ~I915_GEM_DOMAIN_CPU
);
3387 old_read_domains
= obj
->base
.read_domains
;
3388 old_write_domain
= obj
->base
.write_domain
;
3390 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3391 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3393 trace_i915_gem_object_change_domain(obj
,
3398 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3399 vma
->node
.color
= cache_level
;
3400 obj
->cache_level
= cache_level
;
3401 i915_gem_verify_gtt(dev
);
3405 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3406 struct drm_file
*file
)
3408 struct drm_i915_gem_caching
*args
= data
;
3409 struct drm_i915_gem_object
*obj
;
3412 ret
= i915_mutex_lock_interruptible(dev
);
3416 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3417 if (&obj
->base
== NULL
) {
3422 args
->caching
= obj
->cache_level
!= I915_CACHE_NONE
;
3424 drm_gem_object_unreference(&obj
->base
);
3426 mutex_unlock(&dev
->struct_mutex
);
3430 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3431 struct drm_file
*file
)
3433 struct drm_i915_gem_caching
*args
= data
;
3434 struct drm_i915_gem_object
*obj
;
3435 enum i915_cache_level level
;
3438 switch (args
->caching
) {
3439 case I915_CACHING_NONE
:
3440 level
= I915_CACHE_NONE
;
3442 case I915_CACHING_CACHED
:
3443 level
= I915_CACHE_LLC
;
3449 ret
= i915_mutex_lock_interruptible(dev
);
3453 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3454 if (&obj
->base
== NULL
) {
3459 ret
= i915_gem_object_set_cache_level(obj
, level
);
3461 drm_gem_object_unreference(&obj
->base
);
3463 mutex_unlock(&dev
->struct_mutex
);
3468 * Prepare buffer for display plane (scanout, cursors, etc).
3469 * Can be called from an uninterruptible phase (modesetting) and allows
3470 * any flushes to be pipelined (for pageflips).
3473 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3475 struct intel_ring_buffer
*pipelined
)
3477 u32 old_read_domains
, old_write_domain
;
3480 if (pipelined
!= obj
->ring
) {
3481 ret
= i915_gem_object_sync(obj
, pipelined
);
3486 /* The display engine is not coherent with the LLC cache on gen6. As
3487 * a result, we make sure that the pinning that is about to occur is
3488 * done with uncached PTEs. This is lowest common denominator for all
3491 * However for gen6+, we could do better by using the GFDT bit instead
3492 * of uncaching, which would allow us to flush all the LLC-cached data
3493 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3495 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_NONE
);
3499 /* As the user may map the buffer once pinned in the display plane
3500 * (e.g. libkms for the bootup splash), we have to ensure that we
3501 * always use map_and_fenceable for all scanout buffers.
3503 ret
= i915_gem_obj_ggtt_pin(obj
, alignment
, true, false);
3507 i915_gem_object_flush_cpu_write_domain(obj
);
3509 old_write_domain
= obj
->base
.write_domain
;
3510 old_read_domains
= obj
->base
.read_domains
;
3512 /* It should now be out of any other write domains, and we can update
3513 * the domain values for our changes.
3515 obj
->base
.write_domain
= 0;
3516 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3518 trace_i915_gem_object_change_domain(obj
,
3526 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
3530 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
3533 ret
= i915_gem_object_wait_rendering(obj
, false);
3537 /* Ensure that we invalidate the GPU's caches and TLBs. */
3538 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
3543 * Moves a single object to the CPU read, and possibly write domain.
3545 * This function returns when the move is complete, including waiting on
3549 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3551 uint32_t old_write_domain
, old_read_domains
;
3554 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3557 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3561 i915_gem_object_flush_gtt_write_domain(obj
);
3563 old_write_domain
= obj
->base
.write_domain
;
3564 old_read_domains
= obj
->base
.read_domains
;
3566 /* Flush the CPU cache if it's still invalid. */
3567 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3568 i915_gem_clflush_object(obj
);
3570 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3573 /* It should now be out of any other write domains, and we can update
3574 * the domain values for our changes.
3576 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3578 /* If we're writing through the CPU, then the GPU read domains will
3579 * need to be invalidated at next use.
3582 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3583 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3586 trace_i915_gem_object_change_domain(obj
,
3593 /* Throttle our rendering by waiting until the ring has completed our requests
3594 * emitted over 20 msec ago.
3596 * Note that if we were to use the current jiffies each time around the loop,
3597 * we wouldn't escape the function with any frames outstanding if the time to
3598 * render a frame was over 20ms.
3600 * This should get us reasonable parallelism between CPU and GPU but also
3601 * relatively low latency when blocking on a particular request to finish.
3604 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3606 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3607 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3608 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3609 struct drm_i915_gem_request
*request
;
3610 struct intel_ring_buffer
*ring
= NULL
;
3611 unsigned reset_counter
;
3615 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
3619 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
3623 spin_lock(&file_priv
->mm
.lock
);
3624 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3625 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3628 ring
= request
->ring
;
3629 seqno
= request
->seqno
;
3631 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3632 spin_unlock(&file_priv
->mm
.lock
);
3637 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, NULL
);
3639 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3645 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3646 struct i915_address_space
*vm
,
3648 bool map_and_fenceable
,
3653 if (WARN_ON(obj
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
3656 if (i915_gem_obj_ggtt_bound(obj
)) {
3657 if ((alignment
&& i915_gem_obj_ggtt_offset(obj
) & (alignment
- 1)) ||
3658 (map_and_fenceable
&& !obj
->map_and_fenceable
)) {
3659 WARN(obj
->pin_count
,
3660 "bo is already pinned with incorrect alignment:"
3661 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3662 " obj->map_and_fenceable=%d\n",
3663 i915_gem_obj_ggtt_offset(obj
), alignment
,
3665 obj
->map_and_fenceable
);
3666 ret
= i915_gem_object_unbind(obj
);
3672 if (!i915_gem_obj_ggtt_bound(obj
)) {
3673 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3675 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
3681 if (!dev_priv
->mm
.aliasing_ppgtt
)
3682 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3685 if (!obj
->has_global_gtt_mapping
&& map_and_fenceable
)
3686 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3689 obj
->pin_mappable
|= map_and_fenceable
;
3695 i915_gem_object_unpin(struct drm_i915_gem_object
*obj
)
3697 BUG_ON(obj
->pin_count
== 0);
3698 BUG_ON(!i915_gem_obj_ggtt_bound(obj
));
3700 if (--obj
->pin_count
== 0)
3701 obj
->pin_mappable
= false;
3705 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3706 struct drm_file
*file
)
3708 struct drm_i915_gem_pin
*args
= data
;
3709 struct drm_i915_gem_object
*obj
;
3712 ret
= i915_mutex_lock_interruptible(dev
);
3716 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3717 if (&obj
->base
== NULL
) {
3722 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3723 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3728 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3729 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3735 if (obj
->user_pin_count
== 0) {
3736 ret
= i915_gem_obj_ggtt_pin(obj
, args
->alignment
, true, false);
3741 obj
->user_pin_count
++;
3742 obj
->pin_filp
= file
;
3744 /* XXX - flush the CPU caches for pinned objects
3745 * as the X server doesn't manage domains yet
3747 i915_gem_object_flush_cpu_write_domain(obj
);
3748 args
->offset
= i915_gem_obj_ggtt_offset(obj
);
3750 drm_gem_object_unreference(&obj
->base
);
3752 mutex_unlock(&dev
->struct_mutex
);
3757 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3758 struct drm_file
*file
)
3760 struct drm_i915_gem_pin
*args
= data
;
3761 struct drm_i915_gem_object
*obj
;
3764 ret
= i915_mutex_lock_interruptible(dev
);
3768 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3769 if (&obj
->base
== NULL
) {
3774 if (obj
->pin_filp
!= file
) {
3775 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3780 obj
->user_pin_count
--;
3781 if (obj
->user_pin_count
== 0) {
3782 obj
->pin_filp
= NULL
;
3783 i915_gem_object_unpin(obj
);
3787 drm_gem_object_unreference(&obj
->base
);
3789 mutex_unlock(&dev
->struct_mutex
);
3794 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3795 struct drm_file
*file
)
3797 struct drm_i915_gem_busy
*args
= data
;
3798 struct drm_i915_gem_object
*obj
;
3801 ret
= i915_mutex_lock_interruptible(dev
);
3805 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3806 if (&obj
->base
== NULL
) {
3811 /* Count all active objects as busy, even if they are currently not used
3812 * by the gpu. Users of this interface expect objects to eventually
3813 * become non-busy without any further actions, therefore emit any
3814 * necessary flushes here.
3816 ret
= i915_gem_object_flush_active(obj
);
3818 args
->busy
= obj
->active
;
3820 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
3821 args
->busy
|= intel_ring_flag(obj
->ring
) << 16;
3824 drm_gem_object_unreference(&obj
->base
);
3826 mutex_unlock(&dev
->struct_mutex
);
3831 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3832 struct drm_file
*file_priv
)
3834 return i915_gem_ring_throttle(dev
, file_priv
);
3838 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3839 struct drm_file
*file_priv
)
3841 struct drm_i915_gem_madvise
*args
= data
;
3842 struct drm_i915_gem_object
*obj
;
3845 switch (args
->madv
) {
3846 case I915_MADV_DONTNEED
:
3847 case I915_MADV_WILLNEED
:
3853 ret
= i915_mutex_lock_interruptible(dev
);
3857 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
3858 if (&obj
->base
== NULL
) {
3863 if (obj
->pin_count
) {
3868 if (obj
->madv
!= __I915_MADV_PURGED
)
3869 obj
->madv
= args
->madv
;
3871 /* if the object is no longer attached, discard its backing storage */
3872 if (i915_gem_object_is_purgeable(obj
) && obj
->pages
== NULL
)
3873 i915_gem_object_truncate(obj
);
3875 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
3878 drm_gem_object_unreference(&obj
->base
);
3880 mutex_unlock(&dev
->struct_mutex
);
3884 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3885 const struct drm_i915_gem_object_ops
*ops
)
3887 INIT_LIST_HEAD(&obj
->mm_list
);
3888 INIT_LIST_HEAD(&obj
->global_list
);
3889 INIT_LIST_HEAD(&obj
->ring_list
);
3890 INIT_LIST_HEAD(&obj
->exec_list
);
3891 INIT_LIST_HEAD(&obj
->vma_list
);
3895 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3896 obj
->madv
= I915_MADV_WILLNEED
;
3897 /* Avoid an unnecessary call to unbind on the first bind. */
3898 obj
->map_and_fenceable
= true;
3900 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
3903 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
3904 .get_pages
= i915_gem_object_get_pages_gtt
,
3905 .put_pages
= i915_gem_object_put_pages_gtt
,
3908 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
3911 struct drm_i915_gem_object
*obj
;
3912 struct address_space
*mapping
;
3915 obj
= i915_gem_object_alloc(dev
);
3919 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
3920 i915_gem_object_free(obj
);
3924 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
3925 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
3926 /* 965gm cannot relocate objects above 4GiB. */
3927 mask
&= ~__GFP_HIGHMEM
;
3928 mask
|= __GFP_DMA32
;
3931 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
3932 mapping_set_gfp_mask(mapping
, mask
);
3934 i915_gem_object_init(obj
, &i915_gem_object_ops
);
3936 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3937 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3940 /* On some devices, we can have the GPU use the LLC (the CPU
3941 * cache) for about a 10% performance improvement
3942 * compared to uncached. Graphics requests other than
3943 * display scanout are coherent with the CPU in
3944 * accessing this cache. This means in this mode we
3945 * don't need to clflush on the CPU side, and on the
3946 * GPU side we only need to flush internal caches to
3947 * get data visible to the CPU.
3949 * However, we maintain the display planes as UC, and so
3950 * need to rebind when first used as such.
3952 obj
->cache_level
= I915_CACHE_LLC
;
3954 obj
->cache_level
= I915_CACHE_NONE
;
3956 trace_i915_gem_object_create(obj
);
3961 int i915_gem_init_object(struct drm_gem_object
*obj
)
3968 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
3970 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
3971 struct drm_device
*dev
= obj
->base
.dev
;
3972 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3974 trace_i915_gem_object_destroy(obj
);
3977 i915_gem_detach_phys_object(dev
, obj
);
3980 if (WARN_ON(i915_gem_object_unbind(obj
) == -ERESTARTSYS
)) {
3981 bool was_interruptible
;
3983 was_interruptible
= dev_priv
->mm
.interruptible
;
3984 dev_priv
->mm
.interruptible
= false;
3986 WARN_ON(i915_gem_object_unbind(obj
));
3988 dev_priv
->mm
.interruptible
= was_interruptible
;
3991 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
3992 * before progressing. */
3994 i915_gem_object_unpin_pages(obj
);
3996 if (WARN_ON(obj
->pages_pin_count
))
3997 obj
->pages_pin_count
= 0;
3998 i915_gem_object_put_pages(obj
);
3999 i915_gem_object_free_mmap_offset(obj
);
4000 i915_gem_object_release_stolen(obj
);
4004 if (obj
->base
.import_attach
)
4005 drm_prime_gem_destroy(&obj
->base
, NULL
);
4007 drm_gem_object_release(&obj
->base
);
4008 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4011 i915_gem_object_free(obj
);
4014 struct i915_vma
*i915_gem_vma_create(struct drm_i915_gem_object
*obj
,
4015 struct i915_address_space
*vm
)
4017 struct i915_vma
*vma
= kzalloc(sizeof(*vma
), GFP_KERNEL
);
4019 return ERR_PTR(-ENOMEM
);
4021 INIT_LIST_HEAD(&vma
->vma_link
);
4028 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4030 WARN_ON(vma
->node
.allocated
);
4035 i915_gem_idle(struct drm_device
*dev
)
4037 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4040 if (dev_priv
->ums
.mm_suspended
) {
4041 mutex_unlock(&dev
->struct_mutex
);
4045 ret
= i915_gpu_idle(dev
);
4047 mutex_unlock(&dev
->struct_mutex
);
4050 i915_gem_retire_requests(dev
);
4052 /* Under UMS, be paranoid and evict. */
4053 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4054 i915_gem_evict_everything(dev
);
4056 del_timer_sync(&dev_priv
->gpu_error
.hangcheck_timer
);
4058 i915_kernel_lost_context(dev
);
4059 i915_gem_cleanup_ringbuffer(dev
);
4061 /* Cancel the retire work handler, which should be idle now. */
4062 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4067 void i915_gem_l3_remap(struct drm_device
*dev
)
4069 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4073 if (!HAS_L3_GPU_CACHE(dev
))
4076 if (!dev_priv
->l3_parity
.remap_info
)
4079 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
4080 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
4081 POSTING_READ(GEN7_MISCCPCTL
);
4083 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
4084 u32 remap
= I915_READ(GEN7_L3LOG_BASE
+ i
);
4085 if (remap
&& remap
!= dev_priv
->l3_parity
.remap_info
[i
/4])
4086 DRM_DEBUG("0x%x was already programmed to %x\n",
4087 GEN7_L3LOG_BASE
+ i
, remap
);
4088 if (remap
&& !dev_priv
->l3_parity
.remap_info
[i
/4])
4089 DRM_DEBUG_DRIVER("Clearing remapped register\n");
4090 I915_WRITE(GEN7_L3LOG_BASE
+ i
, dev_priv
->l3_parity
.remap_info
[i
/4]);
4093 /* Make sure all the writes land before disabling dop clock gating */
4094 POSTING_READ(GEN7_L3LOG_BASE
);
4096 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
4099 void i915_gem_init_swizzling(struct drm_device
*dev
)
4101 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4103 if (INTEL_INFO(dev
)->gen
< 5 ||
4104 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4107 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4108 DISP_TILE_SURFACE_SWIZZLING
);
4113 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4115 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4116 else if (IS_GEN7(dev
))
4117 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4123 intel_enable_blt(struct drm_device
*dev
)
4128 /* The blitter was dysfunctional on early prototypes */
4129 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
4130 DRM_INFO("BLT not supported on this pre-production hardware;"
4131 " graphics performance will be degraded.\n");
4138 static int i915_gem_init_rings(struct drm_device
*dev
)
4140 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4143 ret
= intel_init_render_ring_buffer(dev
);
4148 ret
= intel_init_bsd_ring_buffer(dev
);
4150 goto cleanup_render_ring
;
4153 if (intel_enable_blt(dev
)) {
4154 ret
= intel_init_blt_ring_buffer(dev
);
4156 goto cleanup_bsd_ring
;
4159 if (HAS_VEBOX(dev
)) {
4160 ret
= intel_init_vebox_ring_buffer(dev
);
4162 goto cleanup_blt_ring
;
4166 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
4168 goto cleanup_vebox_ring
;
4173 intel_cleanup_ring_buffer(&dev_priv
->ring
[VECS
]);
4175 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
4177 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
4178 cleanup_render_ring
:
4179 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
4185 i915_gem_init_hw(struct drm_device
*dev
)
4187 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4190 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
4193 if (dev_priv
->ellc_size
)
4194 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4196 if (HAS_PCH_NOP(dev
)) {
4197 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4198 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4199 I915_WRITE(GEN7_MSG_CTL
, temp
);
4202 i915_gem_l3_remap(dev
);
4204 i915_gem_init_swizzling(dev
);
4206 ret
= i915_gem_init_rings(dev
);
4211 * XXX: There was some w/a described somewhere suggesting loading
4212 * contexts before PPGTT.
4214 i915_gem_context_init(dev
);
4215 if (dev_priv
->mm
.aliasing_ppgtt
) {
4216 ret
= dev_priv
->mm
.aliasing_ppgtt
->enable(dev
);
4218 i915_gem_cleanup_aliasing_ppgtt(dev
);
4219 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4226 int i915_gem_init(struct drm_device
*dev
)
4228 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4231 mutex_lock(&dev
->struct_mutex
);
4233 if (IS_VALLEYVIEW(dev
)) {
4234 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4235 I915_WRITE(VLV_GTLC_WAKE_CTRL
, 1);
4236 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS
) & 1) == 1, 10))
4237 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4240 i915_gem_init_global_gtt(dev
);
4242 ret
= i915_gem_init_hw(dev
);
4243 mutex_unlock(&dev
->struct_mutex
);
4245 i915_gem_cleanup_aliasing_ppgtt(dev
);
4249 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4250 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4251 dev_priv
->dri1
.allow_batchbuffer
= 1;
4256 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4258 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4259 struct intel_ring_buffer
*ring
;
4262 for_each_ring(ring
, dev_priv
, i
)
4263 intel_cleanup_ring_buffer(ring
);
4267 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4268 struct drm_file
*file_priv
)
4270 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4273 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4276 if (i915_reset_in_progress(&dev_priv
->gpu_error
)) {
4277 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4278 atomic_set(&dev_priv
->gpu_error
.reset_counter
, 0);
4281 mutex_lock(&dev
->struct_mutex
);
4282 dev_priv
->ums
.mm_suspended
= 0;
4284 ret
= i915_gem_init_hw(dev
);
4286 mutex_unlock(&dev
->struct_mutex
);
4290 BUG_ON(!list_empty(&dev_priv
->gtt
.base
.active_list
));
4291 mutex_unlock(&dev
->struct_mutex
);
4293 ret
= drm_irq_install(dev
);
4295 goto cleanup_ringbuffer
;
4300 mutex_lock(&dev
->struct_mutex
);
4301 i915_gem_cleanup_ringbuffer(dev
);
4302 dev_priv
->ums
.mm_suspended
= 1;
4303 mutex_unlock(&dev
->struct_mutex
);
4309 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4310 struct drm_file
*file_priv
)
4312 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4315 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4318 drm_irq_uninstall(dev
);
4320 mutex_lock(&dev
->struct_mutex
);
4321 ret
= i915_gem_idle(dev
);
4323 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4324 * We need to replace this with a semaphore, or something.
4325 * And not confound ums.mm_suspended!
4328 dev_priv
->ums
.mm_suspended
= 1;
4329 mutex_unlock(&dev
->struct_mutex
);
4335 i915_gem_lastclose(struct drm_device
*dev
)
4339 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4342 mutex_lock(&dev
->struct_mutex
);
4343 ret
= i915_gem_idle(dev
);
4345 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4346 mutex_unlock(&dev
->struct_mutex
);
4350 init_ring_lists(struct intel_ring_buffer
*ring
)
4352 INIT_LIST_HEAD(&ring
->active_list
);
4353 INIT_LIST_HEAD(&ring
->request_list
);
4356 static void i915_init_vm(struct drm_i915_private
*dev_priv
,
4357 struct i915_address_space
*vm
)
4359 vm
->dev
= dev_priv
->dev
;
4360 INIT_LIST_HEAD(&vm
->active_list
);
4361 INIT_LIST_HEAD(&vm
->inactive_list
);
4362 INIT_LIST_HEAD(&vm
->global_link
);
4363 list_add(&vm
->global_link
, &dev_priv
->vm_list
);
4367 i915_gem_load(struct drm_device
*dev
)
4369 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4373 kmem_cache_create("i915_gem_object",
4374 sizeof(struct drm_i915_gem_object
), 0,
4378 INIT_LIST_HEAD(&dev_priv
->vm_list
);
4379 i915_init_vm(dev_priv
, &dev_priv
->gtt
.base
);
4381 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4382 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4383 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4384 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4385 init_ring_lists(&dev_priv
->ring
[i
]);
4386 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
4387 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4388 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4389 i915_gem_retire_work_handler
);
4390 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
4392 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4394 I915_WRITE(MI_ARB_STATE
,
4395 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
4398 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4400 /* Old X drivers will take 0-2 for front, back, depth buffers */
4401 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4402 dev_priv
->fence_reg_start
= 3;
4404 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
))
4405 dev_priv
->num_fence_regs
= 32;
4406 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4407 dev_priv
->num_fence_regs
= 16;
4409 dev_priv
->num_fence_regs
= 8;
4411 /* Initialize fence registers to zero */
4412 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4413 i915_gem_restore_fences(dev
);
4415 i915_gem_detect_bit_6_swizzle(dev
);
4416 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4418 dev_priv
->mm
.interruptible
= true;
4420 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
4421 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
4422 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
4426 * Create a physically contiguous memory object for this object
4427 * e.g. for cursor + overlay regs
4429 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4430 int id
, int size
, int align
)
4432 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4433 struct drm_i915_gem_phys_object
*phys_obj
;
4436 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4439 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4445 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4446 if (!phys_obj
->handle
) {
4451 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4454 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4462 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4464 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4465 struct drm_i915_gem_phys_object
*phys_obj
;
4467 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4470 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4471 if (phys_obj
->cur_obj
) {
4472 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4476 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4478 drm_pci_free(dev
, phys_obj
->handle
);
4480 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4483 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4487 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4488 i915_gem_free_phys_object(dev
, i
);
4491 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4492 struct drm_i915_gem_object
*obj
)
4494 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4501 vaddr
= obj
->phys_obj
->handle
->vaddr
;
4503 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4504 for (i
= 0; i
< page_count
; i
++) {
4505 struct page
*page
= shmem_read_mapping_page(mapping
, i
);
4506 if (!IS_ERR(page
)) {
4507 char *dst
= kmap_atomic(page
);
4508 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
4511 drm_clflush_pages(&page
, 1);
4513 set_page_dirty(page
);
4514 mark_page_accessed(page
);
4515 page_cache_release(page
);
4518 i915_gem_chipset_flush(dev
);
4520 obj
->phys_obj
->cur_obj
= NULL
;
4521 obj
->phys_obj
= NULL
;
4525 i915_gem_attach_phys_object(struct drm_device
*dev
,
4526 struct drm_i915_gem_object
*obj
,
4530 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4531 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4536 if (id
> I915_MAX_PHYS_OBJECT
)
4539 if (obj
->phys_obj
) {
4540 if (obj
->phys_obj
->id
== id
)
4542 i915_gem_detach_phys_object(dev
, obj
);
4545 /* create a new object */
4546 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4547 ret
= i915_gem_init_phys_object(dev
, id
,
4548 obj
->base
.size
, align
);
4550 DRM_ERROR("failed to init phys object %d size: %zu\n",
4551 id
, obj
->base
.size
);
4556 /* bind to the object */
4557 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4558 obj
->phys_obj
->cur_obj
= obj
;
4560 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4562 for (i
= 0; i
< page_count
; i
++) {
4566 page
= shmem_read_mapping_page(mapping
, i
);
4568 return PTR_ERR(page
);
4570 src
= kmap_atomic(page
);
4571 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4572 memcpy(dst
, src
, PAGE_SIZE
);
4575 mark_page_accessed(page
);
4576 page_cache_release(page
);
4583 i915_gem_phys_pwrite(struct drm_device
*dev
,
4584 struct drm_i915_gem_object
*obj
,
4585 struct drm_i915_gem_pwrite
*args
,
4586 struct drm_file
*file_priv
)
4588 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
4589 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
4591 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
4592 unsigned long unwritten
;
4594 /* The physical object once assigned is fixed for the lifetime
4595 * of the obj, so we can safely drop the lock and continue
4598 mutex_unlock(&dev
->struct_mutex
);
4599 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
4600 mutex_lock(&dev
->struct_mutex
);
4605 i915_gem_chipset_flush(dev
);
4609 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4611 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4613 /* Clean up our request list when the client is going away, so that
4614 * later retire_requests won't dereference our soon-to-be-gone
4617 spin_lock(&file_priv
->mm
.lock
);
4618 while (!list_empty(&file_priv
->mm
.request_list
)) {
4619 struct drm_i915_gem_request
*request
;
4621 request
= list_first_entry(&file_priv
->mm
.request_list
,
4622 struct drm_i915_gem_request
,
4624 list_del(&request
->client_list
);
4625 request
->file_priv
= NULL
;
4627 spin_unlock(&file_priv
->mm
.lock
);
4630 static bool mutex_is_locked_by(struct mutex
*mutex
, struct task_struct
*task
)
4632 if (!mutex_is_locked(mutex
))
4635 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4636 return mutex
->owner
== task
;
4638 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4644 i915_gem_inactive_shrink(struct shrinker
*shrinker
, struct shrink_control
*sc
)
4646 struct drm_i915_private
*dev_priv
=
4647 container_of(shrinker
,
4648 struct drm_i915_private
,
4649 mm
.inactive_shrinker
);
4650 struct drm_device
*dev
= dev_priv
->dev
;
4651 struct drm_i915_gem_object
*obj
;
4652 int nr_to_scan
= sc
->nr_to_scan
;
4656 if (!mutex_trylock(&dev
->struct_mutex
)) {
4657 if (!mutex_is_locked_by(&dev
->struct_mutex
, current
))
4660 if (dev_priv
->mm
.shrinker_no_lock_stealing
)
4667 nr_to_scan
-= i915_gem_purge(dev_priv
, nr_to_scan
);
4669 nr_to_scan
-= __i915_gem_shrink(dev_priv
, nr_to_scan
,
4672 i915_gem_shrink_all(dev_priv
);
4676 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
)
4677 if (obj
->pages_pin_count
== 0)
4678 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4680 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
4684 if (obj
->pin_count
== 0 && obj
->pages_pin_count
== 0)
4685 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4689 mutex_unlock(&dev
->struct_mutex
);
4693 /* All the new VM stuff */
4694 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
4695 struct i915_address_space
*vm
)
4697 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
4698 struct i915_vma
*vma
;
4700 if (vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
)
4701 vm
= &dev_priv
->gtt
.base
;
4703 BUG_ON(list_empty(&o
->vma_list
));
4704 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
4706 return vma
->node
.start
;
4712 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
4713 struct i915_address_space
*vm
)
4715 struct i915_vma
*vma
;
4717 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
4724 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
4726 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
4727 struct i915_address_space
*vm
;
4729 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
)
4730 if (i915_gem_obj_bound(o
, vm
))
4736 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
4737 struct i915_address_space
*vm
)
4739 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
4740 struct i915_vma
*vma
;
4742 if (vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
)
4743 vm
= &dev_priv
->gtt
.base
;
4745 BUG_ON(list_empty(&o
->vma_list
));
4747 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
4749 return vma
->node
.size
;
4754 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4755 struct i915_address_space
*vm
)
4757 struct i915_vma
*vma
;
4758 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)