2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
38 static __must_check
int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object
*obj
);
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
41 static __must_check
int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
,
43 static __must_check
int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object
*obj
,
46 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object
*obj
);
47 static __must_check
int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
49 bool map_and_fenceable
);
50 static void i915_gem_clear_fence_reg(struct drm_device
*dev
,
51 struct drm_i915_fence_reg
*reg
);
52 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
53 struct drm_i915_gem_object
*obj
,
54 struct drm_i915_gem_pwrite
*args
,
55 struct drm_file
*file
);
56 static void i915_gem_free_object_tail(struct drm_i915_gem_object
*obj
);
58 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
63 /* some bookkeeping */
64 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
67 dev_priv
->mm
.object_count
++;
68 dev_priv
->mm
.object_memory
+= size
;
71 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
74 dev_priv
->mm
.object_count
--;
75 dev_priv
->mm
.object_memory
-= size
;
79 i915_gem_check_is_wedged(struct drm_device
*dev
)
81 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
82 struct completion
*x
= &dev_priv
->error_completion
;
86 if (!atomic_read(&dev_priv
->mm
.wedged
))
89 ret
= wait_for_completion_interruptible(x
);
93 /* Success, we reset the GPU! */
94 if (!atomic_read(&dev_priv
->mm
.wedged
))
97 /* GPU is hung, bump the completion count to account for
98 * the token we just consumed so that we never hit zero and
99 * end up waiting upon a subsequent completion event that
102 spin_lock_irqsave(&x
->wait
.lock
, flags
);
104 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
108 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
113 ret
= i915_gem_check_is_wedged(dev
);
117 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
121 if (atomic_read(&dev_priv
->mm
.wedged
)) {
122 mutex_unlock(&dev
->struct_mutex
);
126 WARN_ON(i915_verify_lists(dev
));
131 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
133 return obj
->gtt_space
&& !obj
->active
&& obj
->pin_count
== 0;
136 void i915_gem_do_init(struct drm_device
*dev
,
138 unsigned long mappable_end
,
141 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
143 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
146 dev_priv
->mm
.gtt_total
= end
- start
;
147 dev_priv
->mm
.mappable_gtt_total
= min(end
, mappable_end
) - start
;
148 dev_priv
->mm
.gtt_mappable_end
= mappable_end
;
152 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
153 struct drm_file
*file
)
155 struct drm_i915_gem_init
*args
= data
;
157 if (args
->gtt_start
>= args
->gtt_end
||
158 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
161 mutex_lock(&dev
->struct_mutex
);
162 i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
, args
->gtt_end
);
163 mutex_unlock(&dev
->struct_mutex
);
169 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
170 struct drm_file
*file
)
172 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
173 struct drm_i915_gem_get_aperture
*args
= data
;
174 struct drm_i915_gem_object
*obj
;
177 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
181 mutex_lock(&dev
->struct_mutex
);
182 list_for_each_entry(obj
, &dev_priv
->mm
.pinned_list
, mm_list
)
183 pinned
+= obj
->gtt_space
->size
;
184 mutex_unlock(&dev
->struct_mutex
);
186 args
->aper_size
= dev_priv
->mm
.gtt_total
;
187 args
->aper_available_size
= args
->aper_size
-pinned
;
193 * Creates a new mm object and returns a handle to it.
196 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
197 struct drm_file
*file
)
199 struct drm_i915_gem_create
*args
= data
;
200 struct drm_i915_gem_object
*obj
;
204 args
->size
= roundup(args
->size
, PAGE_SIZE
);
206 /* Allocate the new object */
207 obj
= i915_gem_alloc_object(dev
, args
->size
);
211 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
213 drm_gem_object_release(&obj
->base
);
214 i915_gem_info_remove_obj(dev
->dev_private
, obj
->base
.size
);
219 /* drop reference from allocate - handle holds it now */
220 drm_gem_object_unreference(&obj
->base
);
221 trace_i915_gem_object_create(obj
);
223 args
->handle
= handle
;
227 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
229 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
231 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
232 obj
->tiling_mode
!= I915_TILING_NONE
;
236 slow_shmem_copy(struct page
*dst_page
,
238 struct page
*src_page
,
242 char *dst_vaddr
, *src_vaddr
;
244 dst_vaddr
= kmap(dst_page
);
245 src_vaddr
= kmap(src_page
);
247 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
254 slow_shmem_bit17_copy(struct page
*gpu_page
,
256 struct page
*cpu_page
,
261 char *gpu_vaddr
, *cpu_vaddr
;
263 /* Use the unswizzled path if this page isn't affected. */
264 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
266 return slow_shmem_copy(cpu_page
, cpu_offset
,
267 gpu_page
, gpu_offset
, length
);
269 return slow_shmem_copy(gpu_page
, gpu_offset
,
270 cpu_page
, cpu_offset
, length
);
273 gpu_vaddr
= kmap(gpu_page
);
274 cpu_vaddr
= kmap(cpu_page
);
276 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
277 * XORing with the other bits (A9 for Y, A9 and A10 for X)
280 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
281 int this_length
= min(cacheline_end
- gpu_offset
, length
);
282 int swizzled_gpu_offset
= gpu_offset
^ 64;
285 memcpy(cpu_vaddr
+ cpu_offset
,
286 gpu_vaddr
+ swizzled_gpu_offset
,
289 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
290 cpu_vaddr
+ cpu_offset
,
293 cpu_offset
+= this_length
;
294 gpu_offset
+= this_length
;
295 length
-= this_length
;
303 * This is the fast shmem pread path, which attempts to copy_from_user directly
304 * from the backing pages of the object to the user's address space. On a
305 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
308 i915_gem_shmem_pread_fast(struct drm_device
*dev
,
309 struct drm_i915_gem_object
*obj
,
310 struct drm_i915_gem_pread
*args
,
311 struct drm_file
*file
)
313 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
316 char __user
*user_data
;
317 int page_offset
, page_length
;
319 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
322 offset
= args
->offset
;
329 /* Operation in this page
331 * page_offset = offset within page
332 * page_length = bytes to copy for this page
334 page_offset
= offset
& (PAGE_SIZE
-1);
335 page_length
= remain
;
336 if ((page_offset
+ remain
) > PAGE_SIZE
)
337 page_length
= PAGE_SIZE
- page_offset
;
339 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
340 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
342 return PTR_ERR(page
);
344 vaddr
= kmap_atomic(page
);
345 ret
= __copy_to_user_inatomic(user_data
,
348 kunmap_atomic(vaddr
);
350 mark_page_accessed(page
);
351 page_cache_release(page
);
355 remain
-= page_length
;
356 user_data
+= page_length
;
357 offset
+= page_length
;
364 * This is the fallback shmem pread path, which allocates temporary storage
365 * in kernel space to copy_to_user into outside of the struct_mutex, so we
366 * can copy out of the object's backing pages while holding the struct mutex
367 * and not take page faults.
370 i915_gem_shmem_pread_slow(struct drm_device
*dev
,
371 struct drm_i915_gem_object
*obj
,
372 struct drm_i915_gem_pread
*args
,
373 struct drm_file
*file
)
375 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
376 struct mm_struct
*mm
= current
->mm
;
377 struct page
**user_pages
;
379 loff_t offset
, pinned_pages
, i
;
380 loff_t first_data_page
, last_data_page
, num_pages
;
381 int shmem_page_offset
;
382 int data_page_index
, data_page_offset
;
385 uint64_t data_ptr
= args
->data_ptr
;
386 int do_bit17_swizzling
;
390 /* Pin the user pages containing the data. We can't fault while
391 * holding the struct mutex, yet we want to hold it while
392 * dereferencing the user data.
394 first_data_page
= data_ptr
/ PAGE_SIZE
;
395 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
396 num_pages
= last_data_page
- first_data_page
+ 1;
398 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
399 if (user_pages
== NULL
)
402 mutex_unlock(&dev
->struct_mutex
);
403 down_read(&mm
->mmap_sem
);
404 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
405 num_pages
, 1, 0, user_pages
, NULL
);
406 up_read(&mm
->mmap_sem
);
407 mutex_lock(&dev
->struct_mutex
);
408 if (pinned_pages
< num_pages
) {
413 ret
= i915_gem_object_set_cpu_read_domain_range(obj
,
419 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
421 offset
= args
->offset
;
426 /* Operation in this page
428 * shmem_page_offset = offset within page in shmem file
429 * data_page_index = page number in get_user_pages return
430 * data_page_offset = offset with data_page_index page.
431 * page_length = bytes to copy for this page
433 shmem_page_offset
= offset
& ~PAGE_MASK
;
434 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
435 data_page_offset
= data_ptr
& ~PAGE_MASK
;
437 page_length
= remain
;
438 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
439 page_length
= PAGE_SIZE
- shmem_page_offset
;
440 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
441 page_length
= PAGE_SIZE
- data_page_offset
;
443 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
444 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
446 return PTR_ERR(page
);
448 if (do_bit17_swizzling
) {
449 slow_shmem_bit17_copy(page
,
451 user_pages
[data_page_index
],
456 slow_shmem_copy(user_pages
[data_page_index
],
463 mark_page_accessed(page
);
464 page_cache_release(page
);
466 remain
-= page_length
;
467 data_ptr
+= page_length
;
468 offset
+= page_length
;
472 for (i
= 0; i
< pinned_pages
; i
++) {
473 SetPageDirty(user_pages
[i
]);
474 mark_page_accessed(user_pages
[i
]);
475 page_cache_release(user_pages
[i
]);
477 drm_free_large(user_pages
);
483 * Reads data from the object referenced by handle.
485 * On error, the contents of *data are undefined.
488 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
489 struct drm_file
*file
)
491 struct drm_i915_gem_pread
*args
= data
;
492 struct drm_i915_gem_object
*obj
;
498 if (!access_ok(VERIFY_WRITE
,
499 (char __user
*)(uintptr_t)args
->data_ptr
,
503 ret
= fault_in_pages_writeable((char __user
*)(uintptr_t)args
->data_ptr
,
508 ret
= i915_mutex_lock_interruptible(dev
);
512 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
518 /* Bounds check source. */
519 if (args
->offset
> obj
->base
.size
||
520 args
->size
> obj
->base
.size
- args
->offset
) {
525 ret
= i915_gem_object_set_cpu_read_domain_range(obj
,
532 if (!i915_gem_object_needs_bit17_swizzle(obj
))
533 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file
);
535 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file
);
538 drm_gem_object_unreference(&obj
->base
);
540 mutex_unlock(&dev
->struct_mutex
);
544 /* This is the fast write path which cannot handle
545 * page faults in the source data
549 fast_user_write(struct io_mapping
*mapping
,
550 loff_t page_base
, int page_offset
,
551 char __user
*user_data
,
555 unsigned long unwritten
;
557 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
558 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
560 io_mapping_unmap_atomic(vaddr_atomic
);
564 /* Here's the write path which can sleep for
569 slow_kernel_write(struct io_mapping
*mapping
,
570 loff_t gtt_base
, int gtt_offset
,
571 struct page
*user_page
, int user_offset
,
574 char __iomem
*dst_vaddr
;
577 dst_vaddr
= io_mapping_map_wc(mapping
, gtt_base
);
578 src_vaddr
= kmap(user_page
);
580 memcpy_toio(dst_vaddr
+ gtt_offset
,
581 src_vaddr
+ user_offset
,
585 io_mapping_unmap(dst_vaddr
);
589 * This is the fast pwrite path, where we copy the data directly from the
590 * user into the GTT, uncached.
593 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
594 struct drm_i915_gem_object
*obj
,
595 struct drm_i915_gem_pwrite
*args
,
596 struct drm_file
*file
)
598 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
600 loff_t offset
, page_base
;
601 char __user
*user_data
;
602 int page_offset
, page_length
;
604 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
607 offset
= obj
->gtt_offset
+ args
->offset
;
610 /* Operation in this page
612 * page_base = page offset within aperture
613 * page_offset = offset within page
614 * page_length = bytes to copy for this page
616 page_base
= (offset
& ~(PAGE_SIZE
-1));
617 page_offset
= offset
& (PAGE_SIZE
-1);
618 page_length
= remain
;
619 if ((page_offset
+ remain
) > PAGE_SIZE
)
620 page_length
= PAGE_SIZE
- page_offset
;
622 /* If we get a fault while copying data, then (presumably) our
623 * source page isn't available. Return the error and we'll
624 * retry in the slow path.
626 if (fast_user_write(dev_priv
->mm
.gtt_mapping
, page_base
,
627 page_offset
, user_data
, page_length
))
631 remain
-= page_length
;
632 user_data
+= page_length
;
633 offset
+= page_length
;
640 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
641 * the memory and maps it using kmap_atomic for copying.
643 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
644 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
647 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
,
648 struct drm_i915_gem_object
*obj
,
649 struct drm_i915_gem_pwrite
*args
,
650 struct drm_file
*file
)
652 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
654 loff_t gtt_page_base
, offset
;
655 loff_t first_data_page
, last_data_page
, num_pages
;
656 loff_t pinned_pages
, i
;
657 struct page
**user_pages
;
658 struct mm_struct
*mm
= current
->mm
;
659 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
661 uint64_t data_ptr
= args
->data_ptr
;
665 /* Pin the user pages containing the data. We can't fault while
666 * holding the struct mutex, and all of the pwrite implementations
667 * want to hold it while dereferencing the user data.
669 first_data_page
= data_ptr
/ PAGE_SIZE
;
670 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
671 num_pages
= last_data_page
- first_data_page
+ 1;
673 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
674 if (user_pages
== NULL
)
677 mutex_unlock(&dev
->struct_mutex
);
678 down_read(&mm
->mmap_sem
);
679 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
680 num_pages
, 0, 0, user_pages
, NULL
);
681 up_read(&mm
->mmap_sem
);
682 mutex_lock(&dev
->struct_mutex
);
683 if (pinned_pages
< num_pages
) {
685 goto out_unpin_pages
;
688 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
690 goto out_unpin_pages
;
692 ret
= i915_gem_object_put_fence(obj
);
694 goto out_unpin_pages
;
696 offset
= obj
->gtt_offset
+ args
->offset
;
699 /* Operation in this page
701 * gtt_page_base = page offset within aperture
702 * gtt_page_offset = offset within page in aperture
703 * data_page_index = page number in get_user_pages return
704 * data_page_offset = offset with data_page_index page.
705 * page_length = bytes to copy for this page
707 gtt_page_base
= offset
& PAGE_MASK
;
708 gtt_page_offset
= offset
& ~PAGE_MASK
;
709 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
710 data_page_offset
= data_ptr
& ~PAGE_MASK
;
712 page_length
= remain
;
713 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
714 page_length
= PAGE_SIZE
- gtt_page_offset
;
715 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
716 page_length
= PAGE_SIZE
- data_page_offset
;
718 slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
719 gtt_page_base
, gtt_page_offset
,
720 user_pages
[data_page_index
],
724 remain
-= page_length
;
725 offset
+= page_length
;
726 data_ptr
+= page_length
;
730 for (i
= 0; i
< pinned_pages
; i
++)
731 page_cache_release(user_pages
[i
]);
732 drm_free_large(user_pages
);
738 * This is the fast shmem pwrite path, which attempts to directly
739 * copy_from_user into the kmapped pages backing the object.
742 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
,
743 struct drm_i915_gem_object
*obj
,
744 struct drm_i915_gem_pwrite
*args
,
745 struct drm_file
*file
)
747 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
750 char __user
*user_data
;
751 int page_offset
, page_length
;
753 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
756 offset
= args
->offset
;
764 /* Operation in this page
766 * page_offset = offset within page
767 * page_length = bytes to copy for this page
769 page_offset
= offset
& (PAGE_SIZE
-1);
770 page_length
= remain
;
771 if ((page_offset
+ remain
) > PAGE_SIZE
)
772 page_length
= PAGE_SIZE
- page_offset
;
774 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
775 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
777 return PTR_ERR(page
);
779 vaddr
= kmap_atomic(page
, KM_USER0
);
780 ret
= __copy_from_user_inatomic(vaddr
+ page_offset
,
783 kunmap_atomic(vaddr
, KM_USER0
);
785 set_page_dirty(page
);
786 mark_page_accessed(page
);
787 page_cache_release(page
);
789 /* If we get a fault while copying data, then (presumably) our
790 * source page isn't available. Return the error and we'll
791 * retry in the slow path.
796 remain
-= page_length
;
797 user_data
+= page_length
;
798 offset
+= page_length
;
805 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
806 * the memory and maps it using kmap_atomic for copying.
808 * This avoids taking mmap_sem for faulting on the user's address while the
809 * struct_mutex is held.
812 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
,
813 struct drm_i915_gem_object
*obj
,
814 struct drm_i915_gem_pwrite
*args
,
815 struct drm_file
*file
)
817 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
818 struct mm_struct
*mm
= current
->mm
;
819 struct page
**user_pages
;
821 loff_t offset
, pinned_pages
, i
;
822 loff_t first_data_page
, last_data_page
, num_pages
;
823 int shmem_page_offset
;
824 int data_page_index
, data_page_offset
;
827 uint64_t data_ptr
= args
->data_ptr
;
828 int do_bit17_swizzling
;
832 /* Pin the user pages containing the data. We can't fault while
833 * holding the struct mutex, and all of the pwrite implementations
834 * want to hold it while dereferencing the user data.
836 first_data_page
= data_ptr
/ PAGE_SIZE
;
837 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
838 num_pages
= last_data_page
- first_data_page
+ 1;
840 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
841 if (user_pages
== NULL
)
844 mutex_unlock(&dev
->struct_mutex
);
845 down_read(&mm
->mmap_sem
);
846 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
847 num_pages
, 0, 0, user_pages
, NULL
);
848 up_read(&mm
->mmap_sem
);
849 mutex_lock(&dev
->struct_mutex
);
850 if (pinned_pages
< num_pages
) {
855 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
859 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
861 offset
= args
->offset
;
867 /* Operation in this page
869 * shmem_page_offset = offset within page in shmem file
870 * data_page_index = page number in get_user_pages return
871 * data_page_offset = offset with data_page_index page.
872 * page_length = bytes to copy for this page
874 shmem_page_offset
= offset
& ~PAGE_MASK
;
875 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
876 data_page_offset
= data_ptr
& ~PAGE_MASK
;
878 page_length
= remain
;
879 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
880 page_length
= PAGE_SIZE
- shmem_page_offset
;
881 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
882 page_length
= PAGE_SIZE
- data_page_offset
;
884 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
885 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
891 if (do_bit17_swizzling
) {
892 slow_shmem_bit17_copy(page
,
894 user_pages
[data_page_index
],
899 slow_shmem_copy(page
,
901 user_pages
[data_page_index
],
906 set_page_dirty(page
);
907 mark_page_accessed(page
);
908 page_cache_release(page
);
910 remain
-= page_length
;
911 data_ptr
+= page_length
;
912 offset
+= page_length
;
916 for (i
= 0; i
< pinned_pages
; i
++)
917 page_cache_release(user_pages
[i
]);
918 drm_free_large(user_pages
);
924 * Writes data to the object referenced by handle.
926 * On error, the contents of the buffer that were to be modified are undefined.
929 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
930 struct drm_file
*file
)
932 struct drm_i915_gem_pwrite
*args
= data
;
933 struct drm_i915_gem_object
*obj
;
939 if (!access_ok(VERIFY_READ
,
940 (char __user
*)(uintptr_t)args
->data_ptr
,
944 ret
= fault_in_pages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
949 ret
= i915_mutex_lock_interruptible(dev
);
953 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
959 /* Bounds check destination. */
960 if (args
->offset
> obj
->base
.size
||
961 args
->size
> obj
->base
.size
- args
->offset
) {
966 /* We can only do the GTT pwrite on untiled buffers, as otherwise
967 * it would end up going through the fenced access, and we'll get
968 * different detiling behavior between reading and writing.
969 * pread/pwrite currently are reading and writing from the CPU
970 * perspective, requiring manual detiling by the client.
973 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
974 else if (obj
->gtt_space
&&
975 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
976 ret
= i915_gem_object_pin(obj
, 0, true);
980 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
984 ret
= i915_gem_object_put_fence(obj
);
988 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
990 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
, file
);
993 i915_gem_object_unpin(obj
);
995 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
1000 if (!i915_gem_object_needs_bit17_swizzle(obj
))
1001 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file
);
1003 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file
);
1007 drm_gem_object_unreference(&obj
->base
);
1009 mutex_unlock(&dev
->struct_mutex
);
1014 * Called when user space prepares to use an object with the CPU, either
1015 * through the mmap ioctl's mapping or a GTT mapping.
1018 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1019 struct drm_file
*file
)
1021 struct drm_i915_gem_set_domain
*args
= data
;
1022 struct drm_i915_gem_object
*obj
;
1023 uint32_t read_domains
= args
->read_domains
;
1024 uint32_t write_domain
= args
->write_domain
;
1027 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1030 /* Only handle setting domains to types used by the CPU. */
1031 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1034 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1037 /* Having something in the write domain implies it's in the read
1038 * domain, and only that read domain. Enforce that in the request.
1040 if (write_domain
!= 0 && read_domains
!= write_domain
)
1043 ret
= i915_mutex_lock_interruptible(dev
);
1047 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1053 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1054 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1056 /* Silently promote "you're not bound, there was nothing to do"
1057 * to success, since the client was just asking us to
1058 * make sure everything was done.
1063 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1066 drm_gem_object_unreference(&obj
->base
);
1068 mutex_unlock(&dev
->struct_mutex
);
1073 * Called when user space has done writes to this buffer
1076 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1077 struct drm_file
*file
)
1079 struct drm_i915_gem_sw_finish
*args
= data
;
1080 struct drm_i915_gem_object
*obj
;
1083 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1086 ret
= i915_mutex_lock_interruptible(dev
);
1090 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1096 /* Pinned buffers may be scanout, so flush the cache */
1098 i915_gem_object_flush_cpu_write_domain(obj
);
1100 drm_gem_object_unreference(&obj
->base
);
1102 mutex_unlock(&dev
->struct_mutex
);
1107 * Maps the contents of an object, returning the address it is mapped
1110 * While the mapping holds a reference on the contents of the object, it doesn't
1111 * imply a ref on the object itself.
1114 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1115 struct drm_file
*file
)
1117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1118 struct drm_i915_gem_mmap
*args
= data
;
1119 struct drm_gem_object
*obj
;
1123 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1126 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1130 if (obj
->size
> dev_priv
->mm
.gtt_mappable_end
) {
1131 drm_gem_object_unreference_unlocked(obj
);
1135 offset
= args
->offset
;
1137 down_write(¤t
->mm
->mmap_sem
);
1138 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1139 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1141 up_write(¤t
->mm
->mmap_sem
);
1142 drm_gem_object_unreference_unlocked(obj
);
1143 if (IS_ERR((void *)addr
))
1146 args
->addr_ptr
= (uint64_t) addr
;
1152 * i915_gem_fault - fault a page into the GTT
1153 * vma: VMA in question
1156 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1157 * from userspace. The fault handler takes care of binding the object to
1158 * the GTT (if needed), allocating and programming a fence register (again,
1159 * only if needed based on whether the old reg is still valid or the object
1160 * is tiled) and inserting a new PTE into the faulting process.
1162 * Note that the faulting process may involve evicting existing objects
1163 * from the GTT and/or fence registers to make room. So performance may
1164 * suffer if the GTT working set is large or there are few fence registers
1167 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1169 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1170 struct drm_device
*dev
= obj
->base
.dev
;
1171 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1172 pgoff_t page_offset
;
1175 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1177 /* We don't use vmf->pgoff since that has the fake offset */
1178 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1181 /* Now bind it into the GTT if needed */
1182 mutex_lock(&dev
->struct_mutex
);
1184 if (!obj
->map_and_fenceable
) {
1185 ret
= i915_gem_object_unbind(obj
);
1189 if (!obj
->gtt_space
) {
1190 ret
= i915_gem_object_bind_to_gtt(obj
, 0, true);
1195 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1199 if (obj
->tiling_mode
== I915_TILING_NONE
)
1200 ret
= i915_gem_object_put_fence(obj
);
1202 ret
= i915_gem_object_get_fence(obj
, NULL
, true);
1206 if (i915_gem_object_is_inactive(obj
))
1207 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1209 obj
->fault_mappable
= true;
1211 pfn
= ((dev
->agp
->base
+ obj
->gtt_offset
) >> PAGE_SHIFT
) +
1214 /* Finally, remap it using the new GTT offset */
1215 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1217 mutex_unlock(&dev
->struct_mutex
);
1224 return VM_FAULT_NOPAGE
;
1226 return VM_FAULT_OOM
;
1228 return VM_FAULT_SIGBUS
;
1233 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1234 * @obj: obj in question
1236 * GEM memory mapping works by handing back to userspace a fake mmap offset
1237 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1238 * up the object based on the offset and sets up the various memory mapping
1241 * This routine allocates and attaches a fake offset for @obj.
1244 i915_gem_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1246 struct drm_device
*dev
= obj
->base
.dev
;
1247 struct drm_gem_mm
*mm
= dev
->mm_private
;
1248 struct drm_map_list
*list
;
1249 struct drm_local_map
*map
;
1252 /* Set the object up for mmap'ing */
1253 list
= &obj
->base
.map_list
;
1254 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1259 map
->type
= _DRM_GEM
;
1260 map
->size
= obj
->base
.size
;
1263 /* Get a DRM GEM mmap offset allocated... */
1264 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1265 obj
->base
.size
/ PAGE_SIZE
,
1267 if (!list
->file_offset_node
) {
1268 DRM_ERROR("failed to allocate offset for bo %d\n",
1274 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1275 obj
->base
.size
/ PAGE_SIZE
,
1277 if (!list
->file_offset_node
) {
1282 list
->hash
.key
= list
->file_offset_node
->start
;
1283 ret
= drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
);
1285 DRM_ERROR("failed to add to map hash\n");
1292 drm_mm_put_block(list
->file_offset_node
);
1301 * i915_gem_release_mmap - remove physical page mappings
1302 * @obj: obj in question
1304 * Preserve the reservation of the mmapping with the DRM core code, but
1305 * relinquish ownership of the pages back to the system.
1307 * It is vital that we remove the page mapping if we have mapped a tiled
1308 * object through the GTT and then lose the fence register due to
1309 * resource pressure. Similarly if the object has been moved out of the
1310 * aperture, than pages mapped into userspace must be revoked. Removing the
1311 * mapping will then trigger a page fault on the next user access, allowing
1312 * fixup by i915_gem_fault().
1315 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1317 if (!obj
->fault_mappable
)
1320 unmap_mapping_range(obj
->base
.dev
->dev_mapping
,
1321 (loff_t
)obj
->base
.map_list
.hash
.key
<<PAGE_SHIFT
,
1324 obj
->fault_mappable
= false;
1328 i915_gem_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1330 struct drm_device
*dev
= obj
->base
.dev
;
1331 struct drm_gem_mm
*mm
= dev
->mm_private
;
1332 struct drm_map_list
*list
= &obj
->base
.map_list
;
1334 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1335 drm_mm_put_block(list
->file_offset_node
);
1341 i915_gem_get_gtt_size(struct drm_i915_gem_object
*obj
)
1343 struct drm_device
*dev
= obj
->base
.dev
;
1346 if (INTEL_INFO(dev
)->gen
>= 4 ||
1347 obj
->tiling_mode
== I915_TILING_NONE
)
1348 return obj
->base
.size
;
1350 /* Previous chips need a power-of-two fence region when tiling */
1351 if (INTEL_INFO(dev
)->gen
== 3)
1356 while (size
< obj
->base
.size
)
1363 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1364 * @obj: object to check
1366 * Return the required GTT alignment for an object, taking into account
1367 * potential fence register mapping.
1370 i915_gem_get_gtt_alignment(struct drm_i915_gem_object
*obj
)
1372 struct drm_device
*dev
= obj
->base
.dev
;
1375 * Minimum alignment is 4k (GTT page size), but might be greater
1376 * if a fence register is needed for the object.
1378 if (INTEL_INFO(dev
)->gen
>= 4 ||
1379 obj
->tiling_mode
== I915_TILING_NONE
)
1383 * Previous chips need to be aligned to the size of the smallest
1384 * fence register that can contain the object.
1386 return i915_gem_get_gtt_size(obj
);
1390 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1392 * @obj: object to check
1394 * Return the required GTT alignment for an object, only taking into account
1395 * unfenced tiled surface requirements.
1398 i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object
*obj
)
1400 struct drm_device
*dev
= obj
->base
.dev
;
1404 * Minimum alignment is 4k (GTT page size) for sane hw.
1406 if (INTEL_INFO(dev
)->gen
>= 4 || IS_G33(dev
) ||
1407 obj
->tiling_mode
== I915_TILING_NONE
)
1411 * Older chips need unfenced tiled buffers to be aligned to the left
1412 * edge of an even tile row (where tile rows are counted as if the bo is
1413 * placed in a fenced gtt region).
1416 (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
)))
1421 return tile_height
* obj
->stride
* 2;
1425 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1427 * @data: GTT mapping ioctl data
1428 * @file: GEM object info
1430 * Simply returns the fake offset to userspace so it can mmap it.
1431 * The mmap call will end up in drm_gem_mmap(), which will set things
1432 * up so we can get faults in the handler above.
1434 * The fault handler will take care of binding the object into the GTT
1435 * (since it may have been evicted to make room for something), allocating
1436 * a fence register, and mapping the appropriate aperture address into
1440 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1441 struct drm_file
*file
)
1443 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1444 struct drm_i915_gem_mmap_gtt
*args
= data
;
1445 struct drm_i915_gem_object
*obj
;
1448 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1451 ret
= i915_mutex_lock_interruptible(dev
);
1455 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1461 if (obj
->base
.size
> dev_priv
->mm
.gtt_mappable_end
) {
1466 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1467 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1472 if (!obj
->base
.map_list
.map
) {
1473 ret
= i915_gem_create_mmap_offset(obj
);
1478 args
->offset
= (u64
)obj
->base
.map_list
.hash
.key
<< PAGE_SHIFT
;
1481 drm_gem_object_unreference(&obj
->base
);
1483 mutex_unlock(&dev
->struct_mutex
);
1488 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
,
1492 struct address_space
*mapping
;
1493 struct inode
*inode
;
1496 /* Get the list of pages out of our struct file. They'll be pinned
1497 * at this point until we release them.
1499 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1500 BUG_ON(obj
->pages
!= NULL
);
1501 obj
->pages
= drm_malloc_ab(page_count
, sizeof(struct page
*));
1502 if (obj
->pages
== NULL
)
1505 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1506 mapping
= inode
->i_mapping
;
1507 for (i
= 0; i
< page_count
; i
++) {
1508 page
= read_cache_page_gfp(mapping
, i
,
1516 obj
->pages
[i
] = page
;
1519 if (obj
->tiling_mode
!= I915_TILING_NONE
)
1520 i915_gem_object_do_bit_17_swizzle(obj
);
1526 page_cache_release(obj
->pages
[i
]);
1528 drm_free_large(obj
->pages
);
1530 return PTR_ERR(page
);
1534 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1536 int page_count
= obj
->base
.size
/ PAGE_SIZE
;
1539 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1541 if (obj
->tiling_mode
!= I915_TILING_NONE
)
1542 i915_gem_object_save_bit_17_swizzle(obj
);
1544 if (obj
->madv
== I915_MADV_DONTNEED
)
1547 for (i
= 0; i
< page_count
; i
++) {
1549 set_page_dirty(obj
->pages
[i
]);
1551 if (obj
->madv
== I915_MADV_WILLNEED
)
1552 mark_page_accessed(obj
->pages
[i
]);
1554 page_cache_release(obj
->pages
[i
]);
1558 drm_free_large(obj
->pages
);
1563 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1564 struct intel_ring_buffer
*ring
,
1567 struct drm_device
*dev
= obj
->base
.dev
;
1568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1570 BUG_ON(ring
== NULL
);
1573 /* Add a reference if we're newly entering the active list. */
1575 drm_gem_object_reference(&obj
->base
);
1579 /* Move from whatever list we were on to the tail of execution. */
1580 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.active_list
);
1581 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
1583 obj
->last_rendering_seqno
= seqno
;
1584 if (obj
->fenced_gpu_access
) {
1585 struct drm_i915_fence_reg
*reg
;
1587 BUG_ON(obj
->fence_reg
== I915_FENCE_REG_NONE
);
1589 obj
->last_fenced_seqno
= seqno
;
1590 obj
->last_fenced_ring
= ring
;
1592 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
1593 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
1598 i915_gem_object_move_off_active(struct drm_i915_gem_object
*obj
)
1600 list_del_init(&obj
->ring_list
);
1601 obj
->last_rendering_seqno
= 0;
1605 i915_gem_object_move_to_flushing(struct drm_i915_gem_object
*obj
)
1607 struct drm_device
*dev
= obj
->base
.dev
;
1608 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1610 BUG_ON(!obj
->active
);
1611 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.flushing_list
);
1613 i915_gem_object_move_off_active(obj
);
1617 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
1619 struct drm_device
*dev
= obj
->base
.dev
;
1620 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1622 if (obj
->pin_count
!= 0)
1623 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.pinned_list
);
1625 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1627 BUG_ON(!list_empty(&obj
->gpu_write_list
));
1628 BUG_ON(!obj
->active
);
1631 i915_gem_object_move_off_active(obj
);
1632 obj
->fenced_gpu_access
= false;
1635 obj
->pending_gpu_write
= false;
1636 drm_gem_object_unreference(&obj
->base
);
1638 WARN_ON(i915_verify_lists(dev
));
1641 /* Immediately discard the backing storage */
1643 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1645 struct inode
*inode
;
1647 /* Our goal here is to return as much of the memory as
1648 * is possible back to the system as we are called from OOM.
1649 * To do this we must instruct the shmfs to drop all of its
1650 * backing pages, *now*. Here we mirror the actions taken
1651 * when by shmem_delete_inode() to release the backing store.
1653 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1654 truncate_inode_pages(inode
->i_mapping
, 0);
1655 if (inode
->i_op
->truncate_range
)
1656 inode
->i_op
->truncate_range(inode
, 0, (loff_t
)-1);
1658 obj
->madv
= __I915_MADV_PURGED
;
1662 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1664 return obj
->madv
== I915_MADV_DONTNEED
;
1668 i915_gem_process_flushing_list(struct drm_device
*dev
,
1669 uint32_t flush_domains
,
1670 struct intel_ring_buffer
*ring
)
1672 struct drm_i915_gem_object
*obj
, *next
;
1674 list_for_each_entry_safe(obj
, next
,
1675 &ring
->gpu_write_list
,
1677 if (obj
->base
.write_domain
& flush_domains
) {
1678 uint32_t old_write_domain
= obj
->base
.write_domain
;
1680 obj
->base
.write_domain
= 0;
1681 list_del_init(&obj
->gpu_write_list
);
1682 i915_gem_object_move_to_active(obj
, ring
,
1683 i915_gem_next_request_seqno(dev
, ring
));
1685 trace_i915_gem_object_change_domain(obj
,
1686 obj
->base
.read_domains
,
1693 i915_add_request(struct drm_device
*dev
,
1694 struct drm_file
*file
,
1695 struct drm_i915_gem_request
*request
,
1696 struct intel_ring_buffer
*ring
)
1698 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1699 struct drm_i915_file_private
*file_priv
= NULL
;
1704 BUG_ON(request
== NULL
);
1707 file_priv
= file
->driver_priv
;
1709 ret
= ring
->add_request(ring
, &seqno
);
1713 ring
->outstanding_lazy_request
= false;
1715 request
->seqno
= seqno
;
1716 request
->ring
= ring
;
1717 request
->emitted_jiffies
= jiffies
;
1718 was_empty
= list_empty(&ring
->request_list
);
1719 list_add_tail(&request
->list
, &ring
->request_list
);
1722 spin_lock(&file_priv
->mm
.lock
);
1723 request
->file_priv
= file_priv
;
1724 list_add_tail(&request
->client_list
,
1725 &file_priv
->mm
.request_list
);
1726 spin_unlock(&file_priv
->mm
.lock
);
1729 if (!dev_priv
->mm
.suspended
) {
1730 mod_timer(&dev_priv
->hangcheck_timer
,
1731 jiffies
+ msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1733 queue_delayed_work(dev_priv
->wq
,
1734 &dev_priv
->mm
.retire_work
, HZ
);
1740 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1742 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1747 spin_lock(&file_priv
->mm
.lock
);
1748 list_del(&request
->client_list
);
1749 request
->file_priv
= NULL
;
1750 spin_unlock(&file_priv
->mm
.lock
);
1753 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
1754 struct intel_ring_buffer
*ring
)
1756 while (!list_empty(&ring
->request_list
)) {
1757 struct drm_i915_gem_request
*request
;
1759 request
= list_first_entry(&ring
->request_list
,
1760 struct drm_i915_gem_request
,
1763 list_del(&request
->list
);
1764 i915_gem_request_remove_from_client(request
);
1768 while (!list_empty(&ring
->active_list
)) {
1769 struct drm_i915_gem_object
*obj
;
1771 obj
= list_first_entry(&ring
->active_list
,
1772 struct drm_i915_gem_object
,
1775 obj
->base
.write_domain
= 0;
1776 list_del_init(&obj
->gpu_write_list
);
1777 i915_gem_object_move_to_inactive(obj
);
1781 static void i915_gem_reset_fences(struct drm_device
*dev
)
1783 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1786 for (i
= 0; i
< 16; i
++) {
1787 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
1788 struct drm_i915_gem_object
*obj
= reg
->obj
;
1793 if (obj
->tiling_mode
)
1794 i915_gem_release_mmap(obj
);
1796 reg
->obj
->fence_reg
= I915_FENCE_REG_NONE
;
1797 reg
->obj
->fenced_gpu_access
= false;
1798 reg
->obj
->last_fenced_seqno
= 0;
1799 reg
->obj
->last_fenced_ring
= NULL
;
1800 i915_gem_clear_fence_reg(dev
, reg
);
1804 void i915_gem_reset(struct drm_device
*dev
)
1806 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1807 struct drm_i915_gem_object
*obj
;
1810 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
1811 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->ring
[i
]);
1813 /* Remove anything from the flushing lists. The GPU cache is likely
1814 * to be lost on reset along with the data, so simply move the
1815 * lost bo to the inactive list.
1817 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
1818 obj
= list_first_entry(&dev_priv
->mm
.flushing_list
,
1819 struct drm_i915_gem_object
,
1822 obj
->base
.write_domain
= 0;
1823 list_del_init(&obj
->gpu_write_list
);
1824 i915_gem_object_move_to_inactive(obj
);
1827 /* Move everything out of the GPU domains to ensure we do any
1828 * necessary invalidation upon reuse.
1830 list_for_each_entry(obj
,
1831 &dev_priv
->mm
.inactive_list
,
1834 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
1837 /* The fence registers are invalidated so clear them out */
1838 i915_gem_reset_fences(dev
);
1842 * This function clears the request list as sequence numbers are passed.
1845 i915_gem_retire_requests_ring(struct drm_device
*dev
,
1846 struct intel_ring_buffer
*ring
)
1848 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1852 if (!ring
->status_page
.page_addr
||
1853 list_empty(&ring
->request_list
))
1856 WARN_ON(i915_verify_lists(dev
));
1858 seqno
= ring
->get_seqno(ring
);
1860 for (i
= 0; i
< ARRAY_SIZE(ring
->sync_seqno
); i
++)
1861 if (seqno
>= ring
->sync_seqno
[i
])
1862 ring
->sync_seqno
[i
] = 0;
1864 while (!list_empty(&ring
->request_list
)) {
1865 struct drm_i915_gem_request
*request
;
1867 request
= list_first_entry(&ring
->request_list
,
1868 struct drm_i915_gem_request
,
1871 if (!i915_seqno_passed(seqno
, request
->seqno
))
1874 trace_i915_gem_request_retire(dev
, request
->seqno
);
1876 list_del(&request
->list
);
1877 i915_gem_request_remove_from_client(request
);
1881 /* Move any buffers on the active list that are no longer referenced
1882 * by the ringbuffer to the flushing/inactive lists as appropriate.
1884 while (!list_empty(&ring
->active_list
)) {
1885 struct drm_i915_gem_object
*obj
;
1887 obj
= list_first_entry(&ring
->active_list
,
1888 struct drm_i915_gem_object
,
1891 if (!i915_seqno_passed(seqno
, obj
->last_rendering_seqno
))
1894 if (obj
->base
.write_domain
!= 0)
1895 i915_gem_object_move_to_flushing(obj
);
1897 i915_gem_object_move_to_inactive(obj
);
1900 if (unlikely (dev_priv
->trace_irq_seqno
&&
1901 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
1902 ring
->irq_put(ring
);
1903 dev_priv
->trace_irq_seqno
= 0;
1906 WARN_ON(i915_verify_lists(dev
));
1910 i915_gem_retire_requests(struct drm_device
*dev
)
1912 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1915 if (!list_empty(&dev_priv
->mm
.deferred_free_list
)) {
1916 struct drm_i915_gem_object
*obj
, *next
;
1918 /* We must be careful that during unbind() we do not
1919 * accidentally infinitely recurse into retire requests.
1921 * retire -> free -> unbind -> wait -> retire_ring
1923 list_for_each_entry_safe(obj
, next
,
1924 &dev_priv
->mm
.deferred_free_list
,
1926 i915_gem_free_object_tail(obj
);
1929 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
1930 i915_gem_retire_requests_ring(dev
, &dev_priv
->ring
[i
]);
1934 i915_gem_retire_work_handler(struct work_struct
*work
)
1936 drm_i915_private_t
*dev_priv
;
1937 struct drm_device
*dev
;
1941 dev_priv
= container_of(work
, drm_i915_private_t
,
1942 mm
.retire_work
.work
);
1943 dev
= dev_priv
->dev
;
1945 /* Come back later if the device is busy... */
1946 if (!mutex_trylock(&dev
->struct_mutex
)) {
1947 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1951 i915_gem_retire_requests(dev
);
1953 /* Send a periodic flush down the ring so we don't hold onto GEM
1954 * objects indefinitely.
1957 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1958 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[i
];
1960 if (!list_empty(&ring
->gpu_write_list
)) {
1961 struct drm_i915_gem_request
*request
;
1964 ret
= i915_gem_flush_ring(dev
, ring
, 0,
1965 I915_GEM_GPU_DOMAINS
);
1966 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1967 if (ret
|| request
== NULL
||
1968 i915_add_request(dev
, NULL
, request
, ring
))
1972 idle
&= list_empty(&ring
->request_list
);
1975 if (!dev_priv
->mm
.suspended
&& !idle
)
1976 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1978 mutex_unlock(&dev
->struct_mutex
);
1982 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
,
1983 bool interruptible
, struct intel_ring_buffer
*ring
)
1985 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1991 if (atomic_read(&dev_priv
->mm
.wedged
))
1994 if (seqno
== ring
->outstanding_lazy_request
) {
1995 struct drm_i915_gem_request
*request
;
1997 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1998 if (request
== NULL
)
2001 ret
= i915_add_request(dev
, NULL
, request
, ring
);
2007 seqno
= request
->seqno
;
2010 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
2011 if (HAS_PCH_SPLIT(dev
))
2012 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
2014 ier
= I915_READ(IER
);
2016 DRM_ERROR("something (likely vbetool) disabled "
2017 "interrupts, re-enabling\n");
2018 i915_driver_irq_preinstall(dev
);
2019 i915_driver_irq_postinstall(dev
);
2022 trace_i915_gem_request_wait_begin(dev
, seqno
);
2024 ring
->waiting_seqno
= seqno
;
2025 if (ring
->irq_get(ring
)) {
2027 ret
= wait_event_interruptible(ring
->irq_queue
,
2028 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
2029 || atomic_read(&dev_priv
->mm
.wedged
));
2031 wait_event(ring
->irq_queue
,
2032 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
2033 || atomic_read(&dev_priv
->mm
.wedged
));
2035 ring
->irq_put(ring
);
2036 } else if (wait_for(i915_seqno_passed(ring
->get_seqno(ring
),
2038 atomic_read(&dev_priv
->mm
.wedged
), 3000))
2040 ring
->waiting_seqno
= 0;
2042 trace_i915_gem_request_wait_end(dev
, seqno
);
2044 if (atomic_read(&dev_priv
->mm
.wedged
))
2047 if (ret
&& ret
!= -ERESTARTSYS
)
2048 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2049 __func__
, ret
, seqno
, ring
->get_seqno(ring
),
2050 dev_priv
->next_seqno
);
2052 /* Directly dispatch request retiring. While we have the work queue
2053 * to handle this, the waiter on a request often wants an associated
2054 * buffer to have made it to the inactive list, and we would need
2055 * a separate wait queue to handle that.
2058 i915_gem_retire_requests_ring(dev
, ring
);
2064 * Waits for a sequence number to be signaled, and cleans up the
2065 * request and object lists appropriately for that event.
2068 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
,
2069 struct intel_ring_buffer
*ring
)
2071 return i915_do_wait_request(dev
, seqno
, 1, ring
);
2075 * Ensures that all rendering to the object has completed and the object is
2076 * safe to unbind from the GTT or access from the CPU.
2079 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
2082 struct drm_device
*dev
= obj
->base
.dev
;
2085 /* This function only exists to support waiting for existing rendering,
2086 * not for emitting required flushes.
2088 BUG_ON((obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
2090 /* If there is rendering queued on the buffer being evicted, wait for
2094 ret
= i915_do_wait_request(dev
,
2095 obj
->last_rendering_seqno
,
2106 * Unbinds an object from the GTT aperture.
2109 i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
2113 if (obj
->gtt_space
== NULL
)
2116 if (obj
->pin_count
!= 0) {
2117 DRM_ERROR("Attempting to unbind pinned buffer\n");
2121 /* blow away mappings if mapped through GTT */
2122 i915_gem_release_mmap(obj
);
2124 /* Move the object to the CPU domain to ensure that
2125 * any possible CPU writes while it's not in the GTT
2126 * are flushed when we go to remap it. This will
2127 * also ensure that all pending GPU writes are finished
2130 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2131 if (ret
== -ERESTARTSYS
)
2133 /* Continue on if we fail due to EIO, the GPU is hung so we
2134 * should be safe and we need to cleanup or else we might
2135 * cause memory corruption through use-after-free.
2138 i915_gem_clflush_object(obj
);
2139 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2142 /* release the fence reg _after_ flushing */
2143 ret
= i915_gem_object_put_fence(obj
);
2144 if (ret
== -ERESTARTSYS
)
2147 i915_gem_gtt_unbind_object(obj
);
2148 i915_gem_object_put_pages_gtt(obj
);
2150 list_del_init(&obj
->gtt_list
);
2151 list_del_init(&obj
->mm_list
);
2152 /* Avoid an unnecessary call to unbind on rebind. */
2153 obj
->map_and_fenceable
= true;
2155 drm_mm_put_block(obj
->gtt_space
);
2156 obj
->gtt_space
= NULL
;
2157 obj
->gtt_offset
= 0;
2159 if (i915_gem_object_is_purgeable(obj
))
2160 i915_gem_object_truncate(obj
);
2162 trace_i915_gem_object_unbind(obj
);
2168 i915_gem_flush_ring(struct drm_device
*dev
,
2169 struct intel_ring_buffer
*ring
,
2170 uint32_t invalidate_domains
,
2171 uint32_t flush_domains
)
2175 ret
= ring
->flush(ring
, invalidate_domains
, flush_domains
);
2179 i915_gem_process_flushing_list(dev
, flush_domains
, ring
);
2183 static int i915_ring_idle(struct drm_device
*dev
,
2184 struct intel_ring_buffer
*ring
)
2188 if (list_empty(&ring
->gpu_write_list
) && list_empty(&ring
->active_list
))
2191 if (!list_empty(&ring
->gpu_write_list
)) {
2192 ret
= i915_gem_flush_ring(dev
, ring
,
2193 I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2198 return i915_wait_request(dev
,
2199 i915_gem_next_request_seqno(dev
, ring
),
2204 i915_gpu_idle(struct drm_device
*dev
)
2206 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2210 lists_empty
= (list_empty(&dev_priv
->mm
.flushing_list
) &&
2211 list_empty(&dev_priv
->mm
.active_list
));
2215 /* Flush everything onto the inactive list. */
2216 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
2217 ret
= i915_ring_idle(dev
, &dev_priv
->ring
[i
]);
2225 static int sandybridge_write_fence_reg(struct drm_i915_gem_object
*obj
,
2226 struct intel_ring_buffer
*pipelined
)
2228 struct drm_device
*dev
= obj
->base
.dev
;
2229 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2230 u32 size
= obj
->gtt_space
->size
;
2231 int regnum
= obj
->fence_reg
;
2234 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2236 val
|= obj
->gtt_offset
& 0xfffff000;
2237 val
|= (uint64_t)((obj
->stride
/ 128) - 1) <<
2238 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2240 if (obj
->tiling_mode
== I915_TILING_Y
)
2241 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2242 val
|= I965_FENCE_REG_VALID
;
2245 int ret
= intel_ring_begin(pipelined
, 6);
2249 intel_ring_emit(pipelined
, MI_NOOP
);
2250 intel_ring_emit(pipelined
, MI_LOAD_REGISTER_IMM(2));
2251 intel_ring_emit(pipelined
, FENCE_REG_SANDYBRIDGE_0
+ regnum
*8);
2252 intel_ring_emit(pipelined
, (u32
)val
);
2253 intel_ring_emit(pipelined
, FENCE_REG_SANDYBRIDGE_0
+ regnum
*8 + 4);
2254 intel_ring_emit(pipelined
, (u32
)(val
>> 32));
2255 intel_ring_advance(pipelined
);
2257 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ regnum
* 8, val
);
2262 static int i965_write_fence_reg(struct drm_i915_gem_object
*obj
,
2263 struct intel_ring_buffer
*pipelined
)
2265 struct drm_device
*dev
= obj
->base
.dev
;
2266 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2267 u32 size
= obj
->gtt_space
->size
;
2268 int regnum
= obj
->fence_reg
;
2271 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2273 val
|= obj
->gtt_offset
& 0xfffff000;
2274 val
|= ((obj
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2275 if (obj
->tiling_mode
== I915_TILING_Y
)
2276 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2277 val
|= I965_FENCE_REG_VALID
;
2280 int ret
= intel_ring_begin(pipelined
, 6);
2284 intel_ring_emit(pipelined
, MI_NOOP
);
2285 intel_ring_emit(pipelined
, MI_LOAD_REGISTER_IMM(2));
2286 intel_ring_emit(pipelined
, FENCE_REG_965_0
+ regnum
*8);
2287 intel_ring_emit(pipelined
, (u32
)val
);
2288 intel_ring_emit(pipelined
, FENCE_REG_965_0
+ regnum
*8 + 4);
2289 intel_ring_emit(pipelined
, (u32
)(val
>> 32));
2290 intel_ring_advance(pipelined
);
2292 I915_WRITE64(FENCE_REG_965_0
+ regnum
* 8, val
);
2297 static int i915_write_fence_reg(struct drm_i915_gem_object
*obj
,
2298 struct intel_ring_buffer
*pipelined
)
2300 struct drm_device
*dev
= obj
->base
.dev
;
2301 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2302 u32 size
= obj
->gtt_space
->size
;
2303 u32 fence_reg
, val
, pitch_val
;
2306 if (WARN((obj
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2307 (size
& -size
) != size
||
2308 (obj
->gtt_offset
& (size
- 1)),
2309 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2310 obj
->gtt_offset
, obj
->map_and_fenceable
, size
))
2313 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2318 /* Note: pitch better be a power of two tile widths */
2319 pitch_val
= obj
->stride
/ tile_width
;
2320 pitch_val
= ffs(pitch_val
) - 1;
2322 val
= obj
->gtt_offset
;
2323 if (obj
->tiling_mode
== I915_TILING_Y
)
2324 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2325 val
|= I915_FENCE_SIZE_BITS(size
);
2326 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2327 val
|= I830_FENCE_REG_VALID
;
2329 fence_reg
= obj
->fence_reg
;
2331 fence_reg
= FENCE_REG_830_0
+ fence_reg
* 4;
2333 fence_reg
= FENCE_REG_945_8
+ (fence_reg
- 8) * 4;
2336 int ret
= intel_ring_begin(pipelined
, 4);
2340 intel_ring_emit(pipelined
, MI_NOOP
);
2341 intel_ring_emit(pipelined
, MI_LOAD_REGISTER_IMM(1));
2342 intel_ring_emit(pipelined
, fence_reg
);
2343 intel_ring_emit(pipelined
, val
);
2344 intel_ring_advance(pipelined
);
2346 I915_WRITE(fence_reg
, val
);
2351 static int i830_write_fence_reg(struct drm_i915_gem_object
*obj
,
2352 struct intel_ring_buffer
*pipelined
)
2354 struct drm_device
*dev
= obj
->base
.dev
;
2355 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2356 u32 size
= obj
->gtt_space
->size
;
2357 int regnum
= obj
->fence_reg
;
2361 if (WARN((obj
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2362 (size
& -size
) != size
||
2363 (obj
->gtt_offset
& (size
- 1)),
2364 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2365 obj
->gtt_offset
, size
))
2368 pitch_val
= obj
->stride
/ 128;
2369 pitch_val
= ffs(pitch_val
) - 1;
2371 val
= obj
->gtt_offset
;
2372 if (obj
->tiling_mode
== I915_TILING_Y
)
2373 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2374 val
|= I830_FENCE_SIZE_BITS(size
);
2375 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2376 val
|= I830_FENCE_REG_VALID
;
2379 int ret
= intel_ring_begin(pipelined
, 4);
2383 intel_ring_emit(pipelined
, MI_NOOP
);
2384 intel_ring_emit(pipelined
, MI_LOAD_REGISTER_IMM(1));
2385 intel_ring_emit(pipelined
, FENCE_REG_830_0
+ regnum
*4);
2386 intel_ring_emit(pipelined
, val
);
2387 intel_ring_advance(pipelined
);
2389 I915_WRITE(FENCE_REG_830_0
+ regnum
* 4, val
);
2394 static bool ring_passed_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
2396 return i915_seqno_passed(ring
->get_seqno(ring
), seqno
);
2400 i915_gem_object_flush_fence(struct drm_i915_gem_object
*obj
,
2401 struct intel_ring_buffer
*pipelined
,
2406 if (obj
->fenced_gpu_access
) {
2407 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) {
2408 ret
= i915_gem_flush_ring(obj
->base
.dev
,
2409 obj
->last_fenced_ring
,
2410 0, obj
->base
.write_domain
);
2415 obj
->fenced_gpu_access
= false;
2418 if (obj
->last_fenced_seqno
&& pipelined
!= obj
->last_fenced_ring
) {
2419 if (!ring_passed_seqno(obj
->last_fenced_ring
,
2420 obj
->last_fenced_seqno
)) {
2421 ret
= i915_do_wait_request(obj
->base
.dev
,
2422 obj
->last_fenced_seqno
,
2424 obj
->last_fenced_ring
);
2429 obj
->last_fenced_seqno
= 0;
2430 obj
->last_fenced_ring
= NULL
;
2433 /* Ensure that all CPU reads are completed before installing a fence
2434 * and all writes before removing the fence.
2436 if (obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
)
2443 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
2447 if (obj
->tiling_mode
)
2448 i915_gem_release_mmap(obj
);
2450 ret
= i915_gem_object_flush_fence(obj
, NULL
, true);
2454 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2455 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2456 i915_gem_clear_fence_reg(obj
->base
.dev
,
2457 &dev_priv
->fence_regs
[obj
->fence_reg
]);
2459 obj
->fence_reg
= I915_FENCE_REG_NONE
;
2465 static struct drm_i915_fence_reg
*
2466 i915_find_fence_reg(struct drm_device
*dev
,
2467 struct intel_ring_buffer
*pipelined
)
2469 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2470 struct drm_i915_fence_reg
*reg
, *first
, *avail
;
2473 /* First try to find a free reg */
2475 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2476 reg
= &dev_priv
->fence_regs
[i
];
2480 if (!reg
->obj
->pin_count
)
2487 /* None available, try to steal one or wait for a user to finish */
2488 avail
= first
= NULL
;
2489 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
2490 if (reg
->obj
->pin_count
)
2497 !reg
->obj
->last_fenced_ring
||
2498 reg
->obj
->last_fenced_ring
== pipelined
) {
2511 * i915_gem_object_get_fence - set up a fence reg for an object
2512 * @obj: object to map through a fence reg
2513 * @pipelined: ring on which to queue the change, or NULL for CPU access
2514 * @interruptible: must we wait uninterruptibly for the register to retire?
2516 * When mapping objects through the GTT, userspace wants to be able to write
2517 * to them without having to worry about swizzling if the object is tiled.
2519 * This function walks the fence regs looking for a free one for @obj,
2520 * stealing one if it can't find any.
2522 * It then sets up the reg based on the object's properties: address, pitch
2523 * and tiling format.
2526 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
,
2527 struct intel_ring_buffer
*pipelined
,
2530 struct drm_device
*dev
= obj
->base
.dev
;
2531 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2532 struct drm_i915_fence_reg
*reg
;
2535 /* XXX disable pipelining. There are bugs. Shocking. */
2538 /* Just update our place in the LRU if our fence is getting reused. */
2539 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2540 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2541 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2543 if (!obj
->fenced_gpu_access
&& !obj
->last_fenced_seqno
)
2547 if (reg
->setup_seqno
) {
2548 if (!ring_passed_seqno(obj
->last_fenced_ring
,
2549 reg
->setup_seqno
)) {
2550 ret
= i915_do_wait_request(obj
->base
.dev
,
2553 obj
->last_fenced_ring
);
2558 reg
->setup_seqno
= 0;
2560 } else if (obj
->last_fenced_ring
&&
2561 obj
->last_fenced_ring
!= pipelined
) {
2562 ret
= i915_gem_object_flush_fence(obj
,
2567 } else if (obj
->tiling_changed
) {
2568 if (obj
->fenced_gpu_access
) {
2569 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) {
2570 ret
= i915_gem_flush_ring(obj
->base
.dev
, obj
->ring
,
2571 0, obj
->base
.write_domain
);
2576 obj
->fenced_gpu_access
= false;
2580 if (!obj
->fenced_gpu_access
&& !obj
->last_fenced_seqno
)
2582 BUG_ON(!pipelined
&& reg
->setup_seqno
);
2584 if (obj
->tiling_changed
) {
2587 i915_gem_next_request_seqno(dev
, pipelined
);
2588 obj
->last_fenced_seqno
= reg
->setup_seqno
;
2589 obj
->last_fenced_ring
= pipelined
;
2597 reg
= i915_find_fence_reg(dev
, pipelined
);
2601 ret
= i915_gem_object_flush_fence(obj
, pipelined
, interruptible
);
2606 struct drm_i915_gem_object
*old
= reg
->obj
;
2608 drm_gem_object_reference(&old
->base
);
2610 if (old
->tiling_mode
)
2611 i915_gem_release_mmap(old
);
2613 ret
= i915_gem_object_flush_fence(old
,
2617 drm_gem_object_unreference(&old
->base
);
2621 if (old
->last_fenced_seqno
== 0 && obj
->last_fenced_seqno
== 0)
2624 old
->fence_reg
= I915_FENCE_REG_NONE
;
2625 old
->last_fenced_ring
= pipelined
;
2626 old
->last_fenced_seqno
=
2627 pipelined
? i915_gem_next_request_seqno(dev
, pipelined
) : 0;
2629 drm_gem_object_unreference(&old
->base
);
2630 } else if (obj
->last_fenced_seqno
== 0)
2634 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2635 obj
->fence_reg
= reg
- dev_priv
->fence_regs
;
2636 obj
->last_fenced_ring
= pipelined
;
2639 pipelined
? i915_gem_next_request_seqno(dev
, pipelined
) : 0;
2640 obj
->last_fenced_seqno
= reg
->setup_seqno
;
2643 obj
->tiling_changed
= false;
2644 switch (INTEL_INFO(dev
)->gen
) {
2646 ret
= sandybridge_write_fence_reg(obj
, pipelined
);
2650 ret
= i965_write_fence_reg(obj
, pipelined
);
2653 ret
= i915_write_fence_reg(obj
, pipelined
);
2656 ret
= i830_write_fence_reg(obj
, pipelined
);
2664 * i915_gem_clear_fence_reg - clear out fence register info
2665 * @obj: object to clear
2667 * Zeroes out the fence register itself and clears out the associated
2668 * data structures in dev_priv and obj.
2671 i915_gem_clear_fence_reg(struct drm_device
*dev
,
2672 struct drm_i915_fence_reg
*reg
)
2674 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2675 uint32_t fence_reg
= reg
- dev_priv
->fence_regs
;
2677 switch (INTEL_INFO(dev
)->gen
) {
2679 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ fence_reg
*8, 0);
2683 I915_WRITE64(FENCE_REG_965_0
+ fence_reg
*8, 0);
2687 fence_reg
= FENCE_REG_945_8
+ (fence_reg
- 8) * 4;
2690 fence_reg
= FENCE_REG_830_0
+ fence_reg
* 4;
2692 I915_WRITE(fence_reg
, 0);
2696 list_del_init(®
->lru_list
);
2698 reg
->setup_seqno
= 0;
2702 * Finds free space in the GTT aperture and binds the object there.
2705 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
2707 bool map_and_fenceable
)
2709 struct drm_device
*dev
= obj
->base
.dev
;
2710 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2711 struct drm_mm_node
*free_space
;
2712 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2713 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
2714 bool mappable
, fenceable
;
2717 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2718 DRM_ERROR("Attempting to bind a purgeable object\n");
2722 fence_size
= i915_gem_get_gtt_size(obj
);
2723 fence_alignment
= i915_gem_get_gtt_alignment(obj
);
2724 unfenced_alignment
= i915_gem_get_unfenced_gtt_alignment(obj
);
2727 alignment
= map_and_fenceable
? fence_alignment
:
2729 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
2730 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2734 size
= map_and_fenceable
? fence_size
: obj
->base
.size
;
2736 /* If the object is bigger than the entire aperture, reject it early
2737 * before evicting everything in a vain attempt to find space.
2739 if (obj
->base
.size
>
2740 (map_and_fenceable
? dev_priv
->mm
.gtt_mappable_end
: dev_priv
->mm
.gtt_total
)) {
2741 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2746 if (map_and_fenceable
)
2748 drm_mm_search_free_in_range(&dev_priv
->mm
.gtt_space
,
2750 dev_priv
->mm
.gtt_mappable_end
,
2753 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2754 size
, alignment
, 0);
2756 if (free_space
!= NULL
) {
2757 if (map_and_fenceable
)
2759 drm_mm_get_block_range_generic(free_space
,
2761 dev_priv
->mm
.gtt_mappable_end
,
2765 drm_mm_get_block(free_space
, size
, alignment
);
2767 if (obj
->gtt_space
== NULL
) {
2768 /* If the gtt is empty and we're still having trouble
2769 * fitting our object in, we're out of memory.
2771 ret
= i915_gem_evict_something(dev
, size
, alignment
,
2779 ret
= i915_gem_object_get_pages_gtt(obj
, gfpmask
);
2781 drm_mm_put_block(obj
->gtt_space
);
2782 obj
->gtt_space
= NULL
;
2784 if (ret
== -ENOMEM
) {
2785 /* first try to reclaim some memory by clearing the GTT */
2786 ret
= i915_gem_evict_everything(dev
, false);
2788 /* now try to shrink everyone else */
2803 ret
= i915_gem_gtt_bind_object(obj
);
2805 i915_gem_object_put_pages_gtt(obj
);
2806 drm_mm_put_block(obj
->gtt_space
);
2807 obj
->gtt_space
= NULL
;
2809 if (i915_gem_evict_everything(dev
, false))
2815 list_add_tail(&obj
->gtt_list
, &dev_priv
->mm
.gtt_list
);
2816 list_add_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
2818 /* Assert that the object is not currently in any GPU domain. As it
2819 * wasn't in the GTT, there shouldn't be any way it could have been in
2822 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2823 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2825 obj
->gtt_offset
= obj
->gtt_space
->start
;
2828 obj
->gtt_space
->size
== fence_size
&&
2829 (obj
->gtt_space
->start
& (fence_alignment
-1)) == 0;
2832 obj
->gtt_offset
+ obj
->base
.size
<= dev_priv
->mm
.gtt_mappable_end
;
2834 obj
->map_and_fenceable
= mappable
&& fenceable
;
2836 trace_i915_gem_object_bind(obj
, obj
->gtt_offset
, map_and_fenceable
);
2841 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
)
2843 /* If we don't have a page list set up, then we're not pinned
2844 * to GPU, and we can ignore the cache flush because it'll happen
2845 * again at bind time.
2847 if (obj
->pages
== NULL
)
2850 trace_i915_gem_object_clflush(obj
);
2852 drm_clflush_pages(obj
->pages
, obj
->base
.size
/ PAGE_SIZE
);
2855 /** Flushes any GPU write domain for the object if it's dirty. */
2857 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object
*obj
)
2859 struct drm_device
*dev
= obj
->base
.dev
;
2861 if ((obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2864 /* Queue the GPU write cache flushing we need. */
2865 return i915_gem_flush_ring(dev
, obj
->ring
, 0, obj
->base
.write_domain
);
2868 /** Flushes the GTT write domain for the object if it's dirty. */
2870 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
2872 uint32_t old_write_domain
;
2874 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
2877 /* No actual flushing is required for the GTT write domain. Writes
2878 * to it immediately go to main memory as far as we know, so there's
2879 * no chipset flush. It also doesn't land in render cache.
2881 * However, we do have to enforce the order so that all writes through
2882 * the GTT land before any writes to the device, such as updates to
2887 i915_gem_release_mmap(obj
);
2889 old_write_domain
= obj
->base
.write_domain
;
2890 obj
->base
.write_domain
= 0;
2892 trace_i915_gem_object_change_domain(obj
,
2893 obj
->base
.read_domains
,
2897 /** Flushes the CPU write domain for the object if it's dirty. */
2899 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
2901 uint32_t old_write_domain
;
2903 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
2906 i915_gem_clflush_object(obj
);
2907 intel_gtt_chipset_flush();
2908 old_write_domain
= obj
->base
.write_domain
;
2909 obj
->base
.write_domain
= 0;
2911 trace_i915_gem_object_change_domain(obj
,
2912 obj
->base
.read_domains
,
2917 * Moves a single object to the GTT read, and possibly write domain.
2919 * This function returns when the move is complete, including waiting on
2923 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
2925 uint32_t old_write_domain
, old_read_domains
;
2928 /* Not valid to be called on unbound objects. */
2929 if (obj
->gtt_space
== NULL
)
2932 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2936 if (obj
->pending_gpu_write
|| write
) {
2937 ret
= i915_gem_object_wait_rendering(obj
, true);
2942 i915_gem_object_flush_cpu_write_domain(obj
);
2944 old_write_domain
= obj
->base
.write_domain
;
2945 old_read_domains
= obj
->base
.read_domains
;
2947 /* It should now be out of any other write domains, and we can update
2948 * the domain values for our changes.
2950 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2951 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
2953 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
2954 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
2958 trace_i915_gem_object_change_domain(obj
,
2966 * Prepare buffer for display plane. Use uninterruptible for possible flush
2967 * wait, as in modesetting process we're not supposed to be interrupted.
2970 i915_gem_object_set_to_display_plane(struct drm_i915_gem_object
*obj
,
2971 struct intel_ring_buffer
*pipelined
)
2973 uint32_t old_read_domains
;
2976 /* Not valid to be called on unbound objects. */
2977 if (obj
->gtt_space
== NULL
)
2980 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2985 /* Currently, we are always called from an non-interruptible context. */
2986 if (pipelined
!= obj
->ring
) {
2987 ret
= i915_gem_object_wait_rendering(obj
, false);
2992 i915_gem_object_flush_cpu_write_domain(obj
);
2994 old_read_domains
= obj
->base
.read_domains
;
2995 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
2997 trace_i915_gem_object_change_domain(obj
,
2999 obj
->base
.write_domain
);
3005 i915_gem_object_flush_gpu(struct drm_i915_gem_object
*obj
,
3013 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) {
3014 ret
= i915_gem_flush_ring(obj
->base
.dev
, obj
->ring
,
3015 0, obj
->base
.write_domain
);
3020 return i915_gem_object_wait_rendering(obj
, interruptible
);
3024 * Moves a single object to the CPU read, and possibly write domain.
3026 * This function returns when the move is complete, including waiting on
3030 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3032 uint32_t old_write_domain
, old_read_domains
;
3035 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
3039 ret
= i915_gem_object_wait_rendering(obj
, true);
3043 i915_gem_object_flush_gtt_write_domain(obj
);
3045 /* If we have a partially-valid cache of the object in the CPU,
3046 * finish invalidating it and free the per-page flags.
3048 i915_gem_object_set_to_full_cpu_read_domain(obj
);
3050 old_write_domain
= obj
->base
.write_domain
;
3051 old_read_domains
= obj
->base
.read_domains
;
3053 /* Flush the CPU cache if it's still invalid. */
3054 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3055 i915_gem_clflush_object(obj
);
3057 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3060 /* It should now be out of any other write domains, and we can update
3061 * the domain values for our changes.
3063 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3065 /* If we're writing through the CPU, then the GPU read domains will
3066 * need to be invalidated at next use.
3069 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3070 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3073 trace_i915_gem_object_change_domain(obj
,
3081 * Moves the object from a partially CPU read to a full one.
3083 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3084 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3087 i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object
*obj
)
3089 if (!obj
->page_cpu_valid
)
3092 /* If we're partially in the CPU read domain, finish moving it in.
3094 if (obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) {
3097 for (i
= 0; i
<= (obj
->base
.size
- 1) / PAGE_SIZE
; i
++) {
3098 if (obj
->page_cpu_valid
[i
])
3100 drm_clflush_pages(obj
->pages
+ i
, 1);
3104 /* Free the page_cpu_valid mappings which are now stale, whether
3105 * or not we've got I915_GEM_DOMAIN_CPU.
3107 kfree(obj
->page_cpu_valid
);
3108 obj
->page_cpu_valid
= NULL
;
3112 * Set the CPU read domain on a range of the object.
3114 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3115 * not entirely valid. The page_cpu_valid member of the object flags which
3116 * pages have been flushed, and will be respected by
3117 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3118 * of the whole object.
3120 * This function returns when the move is complete, including waiting on
3124 i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object
*obj
,
3125 uint64_t offset
, uint64_t size
)
3127 uint32_t old_read_domains
;
3130 if (offset
== 0 && size
== obj
->base
.size
)
3131 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3133 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
3137 ret
= i915_gem_object_wait_rendering(obj
, true);
3141 i915_gem_object_flush_gtt_write_domain(obj
);
3143 /* If we're already fully in the CPU read domain, we're done. */
3144 if (obj
->page_cpu_valid
== NULL
&&
3145 (obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3148 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3149 * newly adding I915_GEM_DOMAIN_CPU
3151 if (obj
->page_cpu_valid
== NULL
) {
3152 obj
->page_cpu_valid
= kzalloc(obj
->base
.size
/ PAGE_SIZE
,
3154 if (obj
->page_cpu_valid
== NULL
)
3156 } else if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3157 memset(obj
->page_cpu_valid
, 0, obj
->base
.size
/ PAGE_SIZE
);
3159 /* Flush the cache on any pages that are still invalid from the CPU's
3162 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3164 if (obj
->page_cpu_valid
[i
])
3167 drm_clflush_pages(obj
->pages
+ i
, 1);
3169 obj
->page_cpu_valid
[i
] = 1;
3172 /* It should now be out of any other write domains, and we can update
3173 * the domain values for our changes.
3175 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3177 old_read_domains
= obj
->base
.read_domains
;
3178 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3180 trace_i915_gem_object_change_domain(obj
,
3182 obj
->base
.write_domain
);
3187 /* Throttle our rendering by waiting until the ring has completed our requests
3188 * emitted over 20 msec ago.
3190 * Note that if we were to use the current jiffies each time around the loop,
3191 * we wouldn't escape the function with any frames outstanding if the time to
3192 * render a frame was over 20ms.
3194 * This should get us reasonable parallelism between CPU and GPU but also
3195 * relatively low latency when blocking on a particular request to finish.
3198 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3200 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3201 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3202 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3203 struct drm_i915_gem_request
*request
;
3204 struct intel_ring_buffer
*ring
= NULL
;
3208 spin_lock(&file_priv
->mm
.lock
);
3209 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3210 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3213 ring
= request
->ring
;
3214 seqno
= request
->seqno
;
3216 spin_unlock(&file_priv
->mm
.lock
);
3222 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
3223 /* And wait for the seqno passing without holding any locks and
3224 * causing extra latency for others. This is safe as the irq
3225 * generation is designed to be run atomically and so is
3228 if (ring
->irq_get(ring
)) {
3229 ret
= wait_event_interruptible(ring
->irq_queue
,
3230 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
3231 || atomic_read(&dev_priv
->mm
.wedged
));
3232 ring
->irq_put(ring
);
3234 if (ret
== 0 && atomic_read(&dev_priv
->mm
.wedged
))
3240 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3246 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3248 bool map_and_fenceable
)
3250 struct drm_device
*dev
= obj
->base
.dev
;
3251 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3254 BUG_ON(obj
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
3255 WARN_ON(i915_verify_lists(dev
));
3257 if (obj
->gtt_space
!= NULL
) {
3258 if ((alignment
&& obj
->gtt_offset
& (alignment
- 1)) ||
3259 (map_and_fenceable
&& !obj
->map_and_fenceable
)) {
3260 WARN(obj
->pin_count
,
3261 "bo is already pinned with incorrect alignment:"
3262 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3263 " obj->map_and_fenceable=%d\n",
3264 obj
->gtt_offset
, alignment
,
3266 obj
->map_and_fenceable
);
3267 ret
= i915_gem_object_unbind(obj
);
3273 if (obj
->gtt_space
== NULL
) {
3274 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
3280 if (obj
->pin_count
++ == 0) {
3282 list_move_tail(&obj
->mm_list
,
3283 &dev_priv
->mm
.pinned_list
);
3285 obj
->pin_mappable
|= map_and_fenceable
;
3287 WARN_ON(i915_verify_lists(dev
));
3292 i915_gem_object_unpin(struct drm_i915_gem_object
*obj
)
3294 struct drm_device
*dev
= obj
->base
.dev
;
3295 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3297 WARN_ON(i915_verify_lists(dev
));
3298 BUG_ON(obj
->pin_count
== 0);
3299 BUG_ON(obj
->gtt_space
== NULL
);
3301 if (--obj
->pin_count
== 0) {
3303 list_move_tail(&obj
->mm_list
,
3304 &dev_priv
->mm
.inactive_list
);
3305 obj
->pin_mappable
= false;
3307 WARN_ON(i915_verify_lists(dev
));
3311 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3312 struct drm_file
*file
)
3314 struct drm_i915_gem_pin
*args
= data
;
3315 struct drm_i915_gem_object
*obj
;
3318 ret
= i915_mutex_lock_interruptible(dev
);
3322 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3328 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3329 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3334 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3335 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3341 obj
->user_pin_count
++;
3342 obj
->pin_filp
= file
;
3343 if (obj
->user_pin_count
== 1) {
3344 ret
= i915_gem_object_pin(obj
, args
->alignment
, true);
3349 /* XXX - flush the CPU caches for pinned objects
3350 * as the X server doesn't manage domains yet
3352 i915_gem_object_flush_cpu_write_domain(obj
);
3353 args
->offset
= obj
->gtt_offset
;
3355 drm_gem_object_unreference(&obj
->base
);
3357 mutex_unlock(&dev
->struct_mutex
);
3362 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3363 struct drm_file
*file
)
3365 struct drm_i915_gem_pin
*args
= data
;
3366 struct drm_i915_gem_object
*obj
;
3369 ret
= i915_mutex_lock_interruptible(dev
);
3373 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3379 if (obj
->pin_filp
!= file
) {
3380 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3385 obj
->user_pin_count
--;
3386 if (obj
->user_pin_count
== 0) {
3387 obj
->pin_filp
= NULL
;
3388 i915_gem_object_unpin(obj
);
3392 drm_gem_object_unreference(&obj
->base
);
3394 mutex_unlock(&dev
->struct_mutex
);
3399 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3400 struct drm_file
*file
)
3402 struct drm_i915_gem_busy
*args
= data
;
3403 struct drm_i915_gem_object
*obj
;
3406 ret
= i915_mutex_lock_interruptible(dev
);
3410 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3416 /* Count all active objects as busy, even if they are currently not used
3417 * by the gpu. Users of this interface expect objects to eventually
3418 * become non-busy without any further actions, therefore emit any
3419 * necessary flushes here.
3421 args
->busy
= obj
->active
;
3423 /* Unconditionally flush objects, even when the gpu still uses this
3424 * object. Userspace calling this function indicates that it wants to
3425 * use this buffer rather sooner than later, so issuing the required
3426 * flush earlier is beneficial.
3428 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) {
3429 ret
= i915_gem_flush_ring(dev
, obj
->ring
,
3430 0, obj
->base
.write_domain
);
3431 } else if (obj
->ring
->outstanding_lazy_request
==
3432 obj
->last_rendering_seqno
) {
3433 struct drm_i915_gem_request
*request
;
3435 /* This ring is not being cleared by active usage,
3436 * so emit a request to do so.
3438 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
3440 ret
= i915_add_request(dev
,
3447 /* Update the active list for the hardware's current position.
3448 * Otherwise this only updates on a delayed timer or when irqs
3449 * are actually unmasked, and our working set ends up being
3450 * larger than required.
3452 i915_gem_retire_requests_ring(dev
, obj
->ring
);
3454 args
->busy
= obj
->active
;
3457 drm_gem_object_unreference(&obj
->base
);
3459 mutex_unlock(&dev
->struct_mutex
);
3464 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3465 struct drm_file
*file_priv
)
3467 return i915_gem_ring_throttle(dev
, file_priv
);
3471 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3472 struct drm_file
*file_priv
)
3474 struct drm_i915_gem_madvise
*args
= data
;
3475 struct drm_i915_gem_object
*obj
;
3478 switch (args
->madv
) {
3479 case I915_MADV_DONTNEED
:
3480 case I915_MADV_WILLNEED
:
3486 ret
= i915_mutex_lock_interruptible(dev
);
3490 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
3496 if (obj
->pin_count
) {
3501 if (obj
->madv
!= __I915_MADV_PURGED
)
3502 obj
->madv
= args
->madv
;
3504 /* if the object is no longer bound, discard its backing storage */
3505 if (i915_gem_object_is_purgeable(obj
) &&
3506 obj
->gtt_space
== NULL
)
3507 i915_gem_object_truncate(obj
);
3509 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
3512 drm_gem_object_unreference(&obj
->base
);
3514 mutex_unlock(&dev
->struct_mutex
);
3518 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
3521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3522 struct drm_i915_gem_object
*obj
;
3524 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
3528 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
3533 i915_gem_info_add_obj(dev_priv
, size
);
3535 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3536 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3538 obj
->agp_type
= AGP_USER_MEMORY
;
3539 obj
->base
.driver_private
= NULL
;
3540 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3541 INIT_LIST_HEAD(&obj
->mm_list
);
3542 INIT_LIST_HEAD(&obj
->gtt_list
);
3543 INIT_LIST_HEAD(&obj
->ring_list
);
3544 INIT_LIST_HEAD(&obj
->exec_list
);
3545 INIT_LIST_HEAD(&obj
->gpu_write_list
);
3546 obj
->madv
= I915_MADV_WILLNEED
;
3547 /* Avoid an unnecessary call to unbind on the first bind. */
3548 obj
->map_and_fenceable
= true;
3553 int i915_gem_init_object(struct drm_gem_object
*obj
)
3560 static void i915_gem_free_object_tail(struct drm_i915_gem_object
*obj
)
3562 struct drm_device
*dev
= obj
->base
.dev
;
3563 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3566 ret
= i915_gem_object_unbind(obj
);
3567 if (ret
== -ERESTARTSYS
) {
3568 list_move(&obj
->mm_list
,
3569 &dev_priv
->mm
.deferred_free_list
);
3573 if (obj
->base
.map_list
.map
)
3574 i915_gem_free_mmap_offset(obj
);
3576 drm_gem_object_release(&obj
->base
);
3577 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
3579 kfree(obj
->page_cpu_valid
);
3584 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
3586 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
3587 struct drm_device
*dev
= obj
->base
.dev
;
3589 trace_i915_gem_object_destroy(obj
);
3591 while (obj
->pin_count
> 0)
3592 i915_gem_object_unpin(obj
);
3595 i915_gem_detach_phys_object(dev
, obj
);
3597 i915_gem_free_object_tail(obj
);
3601 i915_gem_idle(struct drm_device
*dev
)
3603 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3606 mutex_lock(&dev
->struct_mutex
);
3608 if (dev_priv
->mm
.suspended
) {
3609 mutex_unlock(&dev
->struct_mutex
);
3613 ret
= i915_gpu_idle(dev
);
3615 mutex_unlock(&dev
->struct_mutex
);
3619 /* Under UMS, be paranoid and evict. */
3620 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
3621 ret
= i915_gem_evict_inactive(dev
, false);
3623 mutex_unlock(&dev
->struct_mutex
);
3628 i915_gem_reset_fences(dev
);
3630 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3631 * We need to replace this with a semaphore, or something.
3632 * And not confound mm.suspended!
3634 dev_priv
->mm
.suspended
= 1;
3635 del_timer_sync(&dev_priv
->hangcheck_timer
);
3637 i915_kernel_lost_context(dev
);
3638 i915_gem_cleanup_ringbuffer(dev
);
3640 mutex_unlock(&dev
->struct_mutex
);
3642 /* Cancel the retire work handler, which should be idle now. */
3643 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
3649 i915_gem_init_ringbuffer(struct drm_device
*dev
)
3651 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3654 ret
= intel_init_render_ring_buffer(dev
);
3659 ret
= intel_init_bsd_ring_buffer(dev
);
3661 goto cleanup_render_ring
;
3665 ret
= intel_init_blt_ring_buffer(dev
);
3667 goto cleanup_bsd_ring
;
3670 dev_priv
->next_seqno
= 1;
3675 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
3676 cleanup_render_ring
:
3677 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
3682 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
3684 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3687 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
3688 intel_cleanup_ring_buffer(&dev_priv
->ring
[i
]);
3692 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
3693 struct drm_file
*file_priv
)
3695 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3698 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3701 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3702 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3703 atomic_set(&dev_priv
->mm
.wedged
, 0);
3706 mutex_lock(&dev
->struct_mutex
);
3707 dev_priv
->mm
.suspended
= 0;
3709 ret
= i915_gem_init_ringbuffer(dev
);
3711 mutex_unlock(&dev
->struct_mutex
);
3715 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
3716 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
3717 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
3718 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
3719 BUG_ON(!list_empty(&dev_priv
->ring
[i
].active_list
));
3720 BUG_ON(!list_empty(&dev_priv
->ring
[i
].request_list
));
3722 mutex_unlock(&dev
->struct_mutex
);
3724 ret
= drm_irq_install(dev
);
3726 goto cleanup_ringbuffer
;
3731 mutex_lock(&dev
->struct_mutex
);
3732 i915_gem_cleanup_ringbuffer(dev
);
3733 dev_priv
->mm
.suspended
= 1;
3734 mutex_unlock(&dev
->struct_mutex
);
3740 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
3741 struct drm_file
*file_priv
)
3743 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3746 drm_irq_uninstall(dev
);
3747 return i915_gem_idle(dev
);
3751 i915_gem_lastclose(struct drm_device
*dev
)
3755 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3758 ret
= i915_gem_idle(dev
);
3760 DRM_ERROR("failed to idle hardware: %d\n", ret
);
3764 init_ring_lists(struct intel_ring_buffer
*ring
)
3766 INIT_LIST_HEAD(&ring
->active_list
);
3767 INIT_LIST_HEAD(&ring
->request_list
);
3768 INIT_LIST_HEAD(&ring
->gpu_write_list
);
3772 i915_gem_load(struct drm_device
*dev
)
3775 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3777 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
3778 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
3779 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
3780 INIT_LIST_HEAD(&dev_priv
->mm
.pinned_list
);
3781 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
3782 INIT_LIST_HEAD(&dev_priv
->mm
.deferred_free_list
);
3783 INIT_LIST_HEAD(&dev_priv
->mm
.gtt_list
);
3784 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
3785 init_ring_lists(&dev_priv
->ring
[i
]);
3786 for (i
= 0; i
< 16; i
++)
3787 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
3788 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
3789 i915_gem_retire_work_handler
);
3790 init_completion(&dev_priv
->error_completion
);
3792 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3794 u32 tmp
= I915_READ(MI_ARB_STATE
);
3795 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
3796 /* arb state is a masked write, so set bit + bit in mask */
3797 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
3798 I915_WRITE(MI_ARB_STATE
, tmp
);
3802 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
3804 /* Old X drivers will take 0-2 for front, back, depth buffers */
3805 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3806 dev_priv
->fence_reg_start
= 3;
3808 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
3809 dev_priv
->num_fence_regs
= 16;
3811 dev_priv
->num_fence_regs
= 8;
3813 /* Initialize fence registers to zero */
3814 switch (INTEL_INFO(dev
)->gen
) {
3816 for (i
= 0; i
< 16; i
++)
3817 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (i
* 8), 0);
3821 for (i
= 0; i
< 16; i
++)
3822 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
3825 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
3826 for (i
= 0; i
< 8; i
++)
3827 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
3829 for (i
= 0; i
< 8; i
++)
3830 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
3833 i915_gem_detect_bit_6_swizzle(dev
);
3834 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
3836 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
3837 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
3838 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
3842 * Create a physically contiguous memory object for this object
3843 * e.g. for cursor + overlay regs
3845 static int i915_gem_init_phys_object(struct drm_device
*dev
,
3846 int id
, int size
, int align
)
3848 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3849 struct drm_i915_gem_phys_object
*phys_obj
;
3852 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
3855 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
3861 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
3862 if (!phys_obj
->handle
) {
3867 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
3870 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
3878 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
3880 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3881 struct drm_i915_gem_phys_object
*phys_obj
;
3883 if (!dev_priv
->mm
.phys_objs
[id
- 1])
3886 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
3887 if (phys_obj
->cur_obj
) {
3888 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
3892 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
3894 drm_pci_free(dev
, phys_obj
->handle
);
3896 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
3899 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
3903 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
3904 i915_gem_free_phys_object(dev
, i
);
3907 void i915_gem_detach_phys_object(struct drm_device
*dev
,
3908 struct drm_i915_gem_object
*obj
)
3910 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3917 vaddr
= obj
->phys_obj
->handle
->vaddr
;
3919 page_count
= obj
->base
.size
/ PAGE_SIZE
;
3920 for (i
= 0; i
< page_count
; i
++) {
3921 struct page
*page
= read_cache_page_gfp(mapping
, i
,
3922 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
3923 if (!IS_ERR(page
)) {
3924 char *dst
= kmap_atomic(page
);
3925 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
3928 drm_clflush_pages(&page
, 1);
3930 set_page_dirty(page
);
3931 mark_page_accessed(page
);
3932 page_cache_release(page
);
3935 intel_gtt_chipset_flush();
3937 obj
->phys_obj
->cur_obj
= NULL
;
3938 obj
->phys_obj
= NULL
;
3942 i915_gem_attach_phys_object(struct drm_device
*dev
,
3943 struct drm_i915_gem_object
*obj
,
3947 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3948 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3953 if (id
> I915_MAX_PHYS_OBJECT
)
3956 if (obj
->phys_obj
) {
3957 if (obj
->phys_obj
->id
== id
)
3959 i915_gem_detach_phys_object(dev
, obj
);
3962 /* create a new object */
3963 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
3964 ret
= i915_gem_init_phys_object(dev
, id
,
3965 obj
->base
.size
, align
);
3967 DRM_ERROR("failed to init phys object %d size: %zu\n",
3968 id
, obj
->base
.size
);
3973 /* bind to the object */
3974 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
3975 obj
->phys_obj
->cur_obj
= obj
;
3977 page_count
= obj
->base
.size
/ PAGE_SIZE
;
3979 for (i
= 0; i
< page_count
; i
++) {
3983 page
= read_cache_page_gfp(mapping
, i
,
3984 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
3986 return PTR_ERR(page
);
3988 src
= kmap_atomic(page
);
3989 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
3990 memcpy(dst
, src
, PAGE_SIZE
);
3993 mark_page_accessed(page
);
3994 page_cache_release(page
);
4001 i915_gem_phys_pwrite(struct drm_device
*dev
,
4002 struct drm_i915_gem_object
*obj
,
4003 struct drm_i915_gem_pwrite
*args
,
4004 struct drm_file
*file_priv
)
4006 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
4007 char __user
*user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4009 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
4010 unsigned long unwritten
;
4012 /* The physical object once assigned is fixed for the lifetime
4013 * of the obj, so we can safely drop the lock and continue
4016 mutex_unlock(&dev
->struct_mutex
);
4017 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
4018 mutex_lock(&dev
->struct_mutex
);
4023 intel_gtt_chipset_flush();
4027 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4029 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4031 /* Clean up our request list when the client is going away, so that
4032 * later retire_requests won't dereference our soon-to-be-gone
4035 spin_lock(&file_priv
->mm
.lock
);
4036 while (!list_empty(&file_priv
->mm
.request_list
)) {
4037 struct drm_i915_gem_request
*request
;
4039 request
= list_first_entry(&file_priv
->mm
.request_list
,
4040 struct drm_i915_gem_request
,
4042 list_del(&request
->client_list
);
4043 request
->file_priv
= NULL
;
4045 spin_unlock(&file_priv
->mm
.lock
);
4049 i915_gpu_is_active(struct drm_device
*dev
)
4051 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4054 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
4055 list_empty(&dev_priv
->mm
.active_list
);
4057 return !lists_empty
;
4061 i915_gem_inactive_shrink(struct shrinker
*shrinker
,
4065 struct drm_i915_private
*dev_priv
=
4066 container_of(shrinker
,
4067 struct drm_i915_private
,
4068 mm
.inactive_shrinker
);
4069 struct drm_device
*dev
= dev_priv
->dev
;
4070 struct drm_i915_gem_object
*obj
, *next
;
4073 if (!mutex_trylock(&dev
->struct_mutex
))
4076 /* "fast-path" to count number of available objects */
4077 if (nr_to_scan
== 0) {
4079 list_for_each_entry(obj
,
4080 &dev_priv
->mm
.inactive_list
,
4083 mutex_unlock(&dev
->struct_mutex
);
4084 return cnt
/ 100 * sysctl_vfs_cache_pressure
;
4088 /* first scan for clean buffers */
4089 i915_gem_retire_requests(dev
);
4091 list_for_each_entry_safe(obj
, next
,
4092 &dev_priv
->mm
.inactive_list
,
4094 if (i915_gem_object_is_purgeable(obj
)) {
4095 if (i915_gem_object_unbind(obj
) == 0 &&
4101 /* second pass, evict/count anything still on the inactive list */
4103 list_for_each_entry_safe(obj
, next
,
4104 &dev_priv
->mm
.inactive_list
,
4107 i915_gem_object_unbind(obj
) == 0)
4113 if (nr_to_scan
&& i915_gpu_is_active(dev
)) {
4115 * We are desperate for pages, so as a last resort, wait
4116 * for the GPU to finish and discard whatever we can.
4117 * This has a dramatic impact to reduce the number of
4118 * OOM-killer events whilst running the GPU aggressively.
4120 if (i915_gpu_idle(dev
) == 0)
4123 mutex_unlock(&dev
->struct_mutex
);
4124 return cnt
/ 100 * sysctl_vfs_cache_pressure
;