2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/oom.h>
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
43 static __must_check
int
44 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
47 i915_gem_object_retire(struct drm_i915_gem_object
*obj
);
49 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
50 struct drm_i915_gem_object
*obj
);
51 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
52 struct drm_i915_fence_reg
*fence
,
55 static unsigned long i915_gem_shrinker_count(struct shrinker
*shrinker
,
56 struct shrink_control
*sc
);
57 static unsigned long i915_gem_shrinker_scan(struct shrinker
*shrinker
,
58 struct shrink_control
*sc
);
59 static int i915_gem_shrinker_oom(struct notifier_block
*nb
,
62 static unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
64 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
65 enum i915_cache_level level
)
67 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
70 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
72 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
75 return obj
->pin_display
;
78 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
81 i915_gem_release_mmap(obj
);
83 /* As we do not have an associated fence register, we will force
84 * a tiling change if we ever need to acquire one.
86 obj
->fence_dirty
= false;
87 obj
->fence_reg
= I915_FENCE_REG_NONE
;
90 /* some bookkeeping */
91 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
94 spin_lock(&dev_priv
->mm
.object_stat_lock
);
95 dev_priv
->mm
.object_count
++;
96 dev_priv
->mm
.object_memory
+= size
;
97 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
100 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
103 spin_lock(&dev_priv
->mm
.object_stat_lock
);
104 dev_priv
->mm
.object_count
--;
105 dev_priv
->mm
.object_memory
-= size
;
106 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
110 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
114 #define EXIT_COND (!i915_reset_in_progress(error) || \
115 i915_terminally_wedged(error))
120 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
121 * userspace. If it takes that long something really bad is going on and
122 * we should simply try to bail out and fail as gracefully as possible.
124 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
128 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
130 } else if (ret
< 0) {
138 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
140 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
143 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
147 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
151 WARN_ON(i915_verify_lists(dev
));
156 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
157 struct drm_file
*file
)
159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
160 struct drm_i915_gem_get_aperture
*args
= data
;
161 struct drm_i915_gem_object
*obj
;
165 mutex_lock(&dev
->struct_mutex
);
166 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
167 if (i915_gem_obj_is_pinned(obj
))
168 pinned
+= i915_gem_obj_ggtt_size(obj
);
169 mutex_unlock(&dev
->struct_mutex
);
171 args
->aper_size
= dev_priv
->gtt
.base
.total
;
172 args
->aper_available_size
= args
->aper_size
- pinned
;
178 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
180 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
181 char *vaddr
= obj
->phys_handle
->vaddr
;
183 struct scatterlist
*sg
;
186 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
189 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
193 page
= shmem_read_mapping_page(mapping
, i
);
195 return PTR_ERR(page
);
197 src
= kmap_atomic(page
);
198 memcpy(vaddr
, src
, PAGE_SIZE
);
199 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
202 page_cache_release(page
);
206 i915_gem_chipset_flush(obj
->base
.dev
);
208 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
212 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
219 sg
->length
= obj
->base
.size
;
221 sg_dma_address(sg
) = obj
->phys_handle
->busaddr
;
222 sg_dma_len(sg
) = obj
->base
.size
;
225 obj
->has_dma_mapping
= true;
230 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
)
234 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
236 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
238 /* In the event of a disaster, abandon all caches and
241 WARN_ON(ret
!= -EIO
);
242 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
245 if (obj
->madv
== I915_MADV_DONTNEED
)
249 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
250 char *vaddr
= obj
->phys_handle
->vaddr
;
253 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
257 page
= shmem_read_mapping_page(mapping
, i
);
261 dst
= kmap_atomic(page
);
262 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
263 memcpy(dst
, vaddr
, PAGE_SIZE
);
266 set_page_dirty(page
);
267 if (obj
->madv
== I915_MADV_WILLNEED
)
268 mark_page_accessed(page
);
269 page_cache_release(page
);
275 sg_free_table(obj
->pages
);
278 obj
->has_dma_mapping
= false;
282 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
284 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
287 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
288 .get_pages
= i915_gem_object_get_pages_phys
,
289 .put_pages
= i915_gem_object_put_pages_phys
,
290 .release
= i915_gem_object_release_phys
,
294 drop_pages(struct drm_i915_gem_object
*obj
)
296 struct i915_vma
*vma
, *next
;
299 drm_gem_object_reference(&obj
->base
);
300 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
)
301 if (i915_vma_unbind(vma
))
304 ret
= i915_gem_object_put_pages(obj
);
305 drm_gem_object_unreference(&obj
->base
);
311 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
314 drm_dma_handle_t
*phys
;
317 if (obj
->phys_handle
) {
318 if ((unsigned long)obj
->phys_handle
->vaddr
& (align
-1))
324 if (obj
->madv
!= I915_MADV_WILLNEED
)
327 if (obj
->base
.filp
== NULL
)
330 ret
= drop_pages(obj
);
334 /* create a new object */
335 phys
= drm_pci_alloc(obj
->base
.dev
, obj
->base
.size
, align
);
339 obj
->phys_handle
= phys
;
340 obj
->ops
= &i915_gem_phys_ops
;
342 return i915_gem_object_get_pages(obj
);
346 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
347 struct drm_i915_gem_pwrite
*args
,
348 struct drm_file
*file_priv
)
350 struct drm_device
*dev
= obj
->base
.dev
;
351 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
352 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
355 /* We manually control the domain here and pretend that it
356 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
358 ret
= i915_gem_object_wait_rendering(obj
, false);
362 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
363 unsigned long unwritten
;
365 /* The physical object once assigned is fixed for the lifetime
366 * of the obj, so we can safely drop the lock and continue
369 mutex_unlock(&dev
->struct_mutex
);
370 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
371 mutex_lock(&dev
->struct_mutex
);
376 drm_clflush_virt_range(vaddr
, args
->size
);
377 i915_gem_chipset_flush(dev
);
381 void *i915_gem_object_alloc(struct drm_device
*dev
)
383 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
384 return kmem_cache_zalloc(dev_priv
->slab
, GFP_KERNEL
);
387 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
389 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
390 kmem_cache_free(dev_priv
->slab
, obj
);
394 i915_gem_create(struct drm_file
*file
,
395 struct drm_device
*dev
,
399 struct drm_i915_gem_object
*obj
;
403 size
= roundup(size
, PAGE_SIZE
);
407 /* Allocate the new object */
408 obj
= i915_gem_alloc_object(dev
, size
);
412 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
413 /* drop reference from allocate - handle holds it now */
414 drm_gem_object_unreference_unlocked(&obj
->base
);
423 i915_gem_dumb_create(struct drm_file
*file
,
424 struct drm_device
*dev
,
425 struct drm_mode_create_dumb
*args
)
427 /* have to work out size/pitch and return them */
428 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
429 args
->size
= args
->pitch
* args
->height
;
430 return i915_gem_create(file
, dev
,
431 args
->size
, &args
->handle
);
435 * Creates a new mm object and returns a handle to it.
438 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
439 struct drm_file
*file
)
441 struct drm_i915_gem_create
*args
= data
;
443 return i915_gem_create(file
, dev
,
444 args
->size
, &args
->handle
);
448 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
449 const char *gpu_vaddr
, int gpu_offset
,
452 int ret
, cpu_offset
= 0;
455 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
456 int this_length
= min(cacheline_end
- gpu_offset
, length
);
457 int swizzled_gpu_offset
= gpu_offset
^ 64;
459 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
460 gpu_vaddr
+ swizzled_gpu_offset
,
465 cpu_offset
+= this_length
;
466 gpu_offset
+= this_length
;
467 length
-= this_length
;
474 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
475 const char __user
*cpu_vaddr
,
478 int ret
, cpu_offset
= 0;
481 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
482 int this_length
= min(cacheline_end
- gpu_offset
, length
);
483 int swizzled_gpu_offset
= gpu_offset
^ 64;
485 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
486 cpu_vaddr
+ cpu_offset
,
491 cpu_offset
+= this_length
;
492 gpu_offset
+= this_length
;
493 length
-= this_length
;
500 * Pins the specified object's pages and synchronizes the object with
501 * GPU accesses. Sets needs_clflush to non-zero if the caller should
502 * flush the object from the CPU cache.
504 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
514 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
515 /* If we're not in the cpu read domain, set ourself into the gtt
516 * read domain and manually flush cachelines (if required). This
517 * optimizes for the case when the gpu will dirty the data
518 * anyway again before the next pread happens. */
519 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
521 ret
= i915_gem_object_wait_rendering(obj
, true);
525 i915_gem_object_retire(obj
);
528 ret
= i915_gem_object_get_pages(obj
);
532 i915_gem_object_pin_pages(obj
);
537 /* Per-page copy function for the shmem pread fastpath.
538 * Flushes invalid cachelines before reading the target if
539 * needs_clflush is set. */
541 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
542 char __user
*user_data
,
543 bool page_do_bit17_swizzling
, bool needs_clflush
)
548 if (unlikely(page_do_bit17_swizzling
))
551 vaddr
= kmap_atomic(page
);
553 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
555 ret
= __copy_to_user_inatomic(user_data
,
556 vaddr
+ shmem_page_offset
,
558 kunmap_atomic(vaddr
);
560 return ret
? -EFAULT
: 0;
564 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
567 if (unlikely(swizzled
)) {
568 unsigned long start
= (unsigned long) addr
;
569 unsigned long end
= (unsigned long) addr
+ length
;
571 /* For swizzling simply ensure that we always flush both
572 * channels. Lame, but simple and it works. Swizzled
573 * pwrite/pread is far from a hotpath - current userspace
574 * doesn't use it at all. */
575 start
= round_down(start
, 128);
576 end
= round_up(end
, 128);
578 drm_clflush_virt_range((void *)start
, end
- start
);
580 drm_clflush_virt_range(addr
, length
);
585 /* Only difference to the fast-path function is that this can handle bit17
586 * and uses non-atomic copy and kmap functions. */
588 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
589 char __user
*user_data
,
590 bool page_do_bit17_swizzling
, bool needs_clflush
)
597 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
599 page_do_bit17_swizzling
);
601 if (page_do_bit17_swizzling
)
602 ret
= __copy_to_user_swizzled(user_data
,
603 vaddr
, shmem_page_offset
,
606 ret
= __copy_to_user(user_data
,
607 vaddr
+ shmem_page_offset
,
611 return ret
? - EFAULT
: 0;
615 i915_gem_shmem_pread(struct drm_device
*dev
,
616 struct drm_i915_gem_object
*obj
,
617 struct drm_i915_gem_pread
*args
,
618 struct drm_file
*file
)
620 char __user
*user_data
;
623 int shmem_page_offset
, page_length
, ret
= 0;
624 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
626 int needs_clflush
= 0;
627 struct sg_page_iter sg_iter
;
629 user_data
= to_user_ptr(args
->data_ptr
);
632 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
634 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
638 offset
= args
->offset
;
640 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
641 offset
>> PAGE_SHIFT
) {
642 struct page
*page
= sg_page_iter_page(&sg_iter
);
647 /* Operation in this page
649 * shmem_page_offset = offset within page in shmem file
650 * page_length = bytes to copy for this page
652 shmem_page_offset
= offset_in_page(offset
);
653 page_length
= remain
;
654 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
655 page_length
= PAGE_SIZE
- shmem_page_offset
;
657 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
658 (page_to_phys(page
) & (1 << 17)) != 0;
660 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
661 user_data
, page_do_bit17_swizzling
,
666 mutex_unlock(&dev
->struct_mutex
);
668 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
669 ret
= fault_in_multipages_writeable(user_data
, remain
);
670 /* Userspace is tricking us, but we've already clobbered
671 * its pages with the prefault and promised to write the
672 * data up to the first fault. Hence ignore any errors
673 * and just continue. */
678 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
679 user_data
, page_do_bit17_swizzling
,
682 mutex_lock(&dev
->struct_mutex
);
688 remain
-= page_length
;
689 user_data
+= page_length
;
690 offset
+= page_length
;
694 i915_gem_object_unpin_pages(obj
);
700 * Reads data from the object referenced by handle.
702 * On error, the contents of *data are undefined.
705 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
706 struct drm_file
*file
)
708 struct drm_i915_gem_pread
*args
= data
;
709 struct drm_i915_gem_object
*obj
;
715 if (!access_ok(VERIFY_WRITE
,
716 to_user_ptr(args
->data_ptr
),
720 ret
= i915_mutex_lock_interruptible(dev
);
724 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
725 if (&obj
->base
== NULL
) {
730 /* Bounds check source. */
731 if (args
->offset
> obj
->base
.size
||
732 args
->size
> obj
->base
.size
- args
->offset
) {
737 /* prime objects have no backing filp to GEM pread/pwrite
740 if (!obj
->base
.filp
) {
745 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
747 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
750 drm_gem_object_unreference(&obj
->base
);
752 mutex_unlock(&dev
->struct_mutex
);
756 /* This is the fast write path which cannot handle
757 * page faults in the source data
761 fast_user_write(struct io_mapping
*mapping
,
762 loff_t page_base
, int page_offset
,
763 char __user
*user_data
,
766 void __iomem
*vaddr_atomic
;
768 unsigned long unwritten
;
770 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
771 /* We can use the cpu mem copy function because this is X86. */
772 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
773 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
775 io_mapping_unmap_atomic(vaddr_atomic
);
780 * This is the fast pwrite path, where we copy the data directly from the
781 * user into the GTT, uncached.
784 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
785 struct drm_i915_gem_object
*obj
,
786 struct drm_i915_gem_pwrite
*args
,
787 struct drm_file
*file
)
789 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
791 loff_t offset
, page_base
;
792 char __user
*user_data
;
793 int page_offset
, page_length
, ret
;
795 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
799 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
803 ret
= i915_gem_object_put_fence(obj
);
807 user_data
= to_user_ptr(args
->data_ptr
);
810 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
813 /* Operation in this page
815 * page_base = page offset within aperture
816 * page_offset = offset within page
817 * page_length = bytes to copy for this page
819 page_base
= offset
& PAGE_MASK
;
820 page_offset
= offset_in_page(offset
);
821 page_length
= remain
;
822 if ((page_offset
+ remain
) > PAGE_SIZE
)
823 page_length
= PAGE_SIZE
- page_offset
;
825 /* If we get a fault while copying data, then (presumably) our
826 * source page isn't available. Return the error and we'll
827 * retry in the slow path.
829 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
830 page_offset
, user_data
, page_length
)) {
835 remain
-= page_length
;
836 user_data
+= page_length
;
837 offset
+= page_length
;
841 i915_gem_object_ggtt_unpin(obj
);
846 /* Per-page copy function for the shmem pwrite fastpath.
847 * Flushes invalid cachelines before writing to the target if
848 * needs_clflush_before is set and flushes out any written cachelines after
849 * writing if needs_clflush is set. */
851 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
852 char __user
*user_data
,
853 bool page_do_bit17_swizzling
,
854 bool needs_clflush_before
,
855 bool needs_clflush_after
)
860 if (unlikely(page_do_bit17_swizzling
))
863 vaddr
= kmap_atomic(page
);
864 if (needs_clflush_before
)
865 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
867 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
868 user_data
, page_length
);
869 if (needs_clflush_after
)
870 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
872 kunmap_atomic(vaddr
);
874 return ret
? -EFAULT
: 0;
877 /* Only difference to the fast-path function is that this can handle bit17
878 * and uses non-atomic copy and kmap functions. */
880 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
881 char __user
*user_data
,
882 bool page_do_bit17_swizzling
,
883 bool needs_clflush_before
,
884 bool needs_clflush_after
)
890 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
891 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
893 page_do_bit17_swizzling
);
894 if (page_do_bit17_swizzling
)
895 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
899 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
902 if (needs_clflush_after
)
903 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
905 page_do_bit17_swizzling
);
908 return ret
? -EFAULT
: 0;
912 i915_gem_shmem_pwrite(struct drm_device
*dev
,
913 struct drm_i915_gem_object
*obj
,
914 struct drm_i915_gem_pwrite
*args
,
915 struct drm_file
*file
)
919 char __user
*user_data
;
920 int shmem_page_offset
, page_length
, ret
= 0;
921 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
922 int hit_slowpath
= 0;
923 int needs_clflush_after
= 0;
924 int needs_clflush_before
= 0;
925 struct sg_page_iter sg_iter
;
927 user_data
= to_user_ptr(args
->data_ptr
);
930 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
932 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
933 /* If we're not in the cpu write domain, set ourself into the gtt
934 * write domain and manually flush cachelines (if required). This
935 * optimizes for the case when the gpu will use the data
936 * right away and we therefore have to clflush anyway. */
937 needs_clflush_after
= cpu_write_needs_clflush(obj
);
938 ret
= i915_gem_object_wait_rendering(obj
, false);
942 i915_gem_object_retire(obj
);
944 /* Same trick applies to invalidate partially written cachelines read
946 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
947 needs_clflush_before
=
948 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
950 ret
= i915_gem_object_get_pages(obj
);
954 i915_gem_object_pin_pages(obj
);
956 offset
= args
->offset
;
959 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
960 offset
>> PAGE_SHIFT
) {
961 struct page
*page
= sg_page_iter_page(&sg_iter
);
962 int partial_cacheline_write
;
967 /* Operation in this page
969 * shmem_page_offset = offset within page in shmem file
970 * page_length = bytes to copy for this page
972 shmem_page_offset
= offset_in_page(offset
);
974 page_length
= remain
;
975 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
976 page_length
= PAGE_SIZE
- shmem_page_offset
;
978 /* If we don't overwrite a cacheline completely we need to be
979 * careful to have up-to-date data by first clflushing. Don't
980 * overcomplicate things and flush the entire patch. */
981 partial_cacheline_write
= needs_clflush_before
&&
982 ((shmem_page_offset
| page_length
)
983 & (boot_cpu_data
.x86_clflush_size
- 1));
985 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
986 (page_to_phys(page
) & (1 << 17)) != 0;
988 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
989 user_data
, page_do_bit17_swizzling
,
990 partial_cacheline_write
,
991 needs_clflush_after
);
996 mutex_unlock(&dev
->struct_mutex
);
997 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
998 user_data
, page_do_bit17_swizzling
,
999 partial_cacheline_write
,
1000 needs_clflush_after
);
1002 mutex_lock(&dev
->struct_mutex
);
1008 remain
-= page_length
;
1009 user_data
+= page_length
;
1010 offset
+= page_length
;
1014 i915_gem_object_unpin_pages(obj
);
1018 * Fixup: Flush cpu caches in case we didn't flush the dirty
1019 * cachelines in-line while writing and the object moved
1020 * out of the cpu write domain while we've dropped the lock.
1022 if (!needs_clflush_after
&&
1023 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1024 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
1025 i915_gem_chipset_flush(dev
);
1029 if (needs_clflush_after
)
1030 i915_gem_chipset_flush(dev
);
1036 * Writes data to the object referenced by handle.
1038 * On error, the contents of the buffer that were to be modified are undefined.
1041 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1042 struct drm_file
*file
)
1044 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1045 struct drm_i915_gem_pwrite
*args
= data
;
1046 struct drm_i915_gem_object
*obj
;
1049 if (args
->size
== 0)
1052 if (!access_ok(VERIFY_READ
,
1053 to_user_ptr(args
->data_ptr
),
1057 if (likely(!i915
.prefault_disable
)) {
1058 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
1064 intel_runtime_pm_get(dev_priv
);
1066 ret
= i915_mutex_lock_interruptible(dev
);
1070 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1071 if (&obj
->base
== NULL
) {
1076 /* Bounds check destination. */
1077 if (args
->offset
> obj
->base
.size
||
1078 args
->size
> obj
->base
.size
- args
->offset
) {
1083 /* prime objects have no backing filp to GEM pread/pwrite
1086 if (!obj
->base
.filp
) {
1091 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1094 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1095 * it would end up going through the fenced access, and we'll get
1096 * different detiling behavior between reading and writing.
1097 * pread/pwrite currently are reading and writing from the CPU
1098 * perspective, requiring manual detiling by the client.
1100 if (obj
->tiling_mode
== I915_TILING_NONE
&&
1101 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
1102 cpu_write_needs_clflush(obj
)) {
1103 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1104 /* Note that the gtt paths might fail with non-page-backed user
1105 * pointers (e.g. gtt mappings when moving data between
1106 * textures). Fallback to the shmem path in that case. */
1109 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1110 if (obj
->phys_handle
)
1111 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1113 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
1117 drm_gem_object_unreference(&obj
->base
);
1119 mutex_unlock(&dev
->struct_mutex
);
1121 intel_runtime_pm_put(dev_priv
);
1127 i915_gem_check_wedge(struct i915_gpu_error
*error
,
1130 if (i915_reset_in_progress(error
)) {
1131 /* Non-interruptible callers can't handle -EAGAIN, hence return
1132 * -EIO unconditionally for these. */
1136 /* Recovery complete, but the reset failed ... */
1137 if (i915_terminally_wedged(error
))
1141 * Check if GPU Reset is in progress - we need intel_ring_begin
1142 * to work properly to reinit the hw state while the gpu is
1143 * still marked as reset-in-progress. Handle this with a flag.
1145 if (!error
->reload_in_reset
)
1153 * Compare arbitrary request against outstanding lazy request. Emit on match.
1156 i915_gem_check_olr(struct drm_i915_gem_request
*req
)
1160 WARN_ON(!mutex_is_locked(&req
->ring
->dev
->struct_mutex
));
1163 if (req
== req
->ring
->outstanding_lazy_request
)
1164 ret
= i915_add_request(req
->ring
);
1169 static void fake_irq(unsigned long data
)
1171 wake_up_process((struct task_struct
*)data
);
1174 static bool missed_irq(struct drm_i915_private
*dev_priv
,
1175 struct intel_engine_cs
*ring
)
1177 return test_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
1180 static bool can_wait_boost(struct drm_i915_file_private
*file_priv
)
1182 if (file_priv
== NULL
)
1185 return !atomic_xchg(&file_priv
->rps_wait_boost
, true);
1189 * __i915_wait_request - wait until execution of request has finished
1191 * @reset_counter: reset sequence associated with the given request
1192 * @interruptible: do an interruptible wait (normally yes)
1193 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1195 * Note: It is of utmost importance that the passed in seqno and reset_counter
1196 * values have been read by the caller in an smp safe manner. Where read-side
1197 * locks are involved, it is sufficient to read the reset_counter before
1198 * unlocking the lock that protects the seqno. For lockless tricks, the
1199 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1202 * Returns 0 if the request was found within the alloted time. Else returns the
1203 * errno with remaining time filled in timeout argument.
1205 int __i915_wait_request(struct drm_i915_gem_request
*req
,
1206 unsigned reset_counter
,
1209 struct drm_i915_file_private
*file_priv
)
1211 struct intel_engine_cs
*ring
= i915_gem_request_get_ring(req
);
1212 struct drm_device
*dev
= ring
->dev
;
1213 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1214 const bool irq_test_in_progress
=
1215 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_ring_flag(ring
);
1217 unsigned long timeout_expire
;
1221 WARN(!intel_irqs_enabled(dev_priv
), "IRQs disabled");
1223 if (i915_gem_request_completed(req
, true))
1226 timeout_expire
= timeout
?
1227 jiffies
+ nsecs_to_jiffies_timeout((u64
)*timeout
) : 0;
1229 if (INTEL_INFO(dev
)->gen
>= 6 && ring
->id
== RCS
&& can_wait_boost(file_priv
)) {
1230 gen6_rps_boost(dev_priv
);
1232 mod_delayed_work(dev_priv
->wq
,
1233 &file_priv
->mm
.idle_work
,
1234 msecs_to_jiffies(100));
1237 if (!irq_test_in_progress
&& WARN_ON(!ring
->irq_get(ring
)))
1240 /* Record current time in case interrupted by signal, or wedged */
1241 trace_i915_gem_request_wait_begin(req
);
1242 before
= ktime_get_raw_ns();
1244 struct timer_list timer
;
1246 prepare_to_wait(&ring
->irq_queue
, &wait
,
1247 interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
);
1249 /* We need to check whether any gpu reset happened in between
1250 * the caller grabbing the seqno and now ... */
1251 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
)) {
1252 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1253 * is truely gone. */
1254 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1260 if (i915_gem_request_completed(req
, false)) {
1265 if (interruptible
&& signal_pending(current
)) {
1270 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1275 timer
.function
= NULL
;
1276 if (timeout
|| missed_irq(dev_priv
, ring
)) {
1277 unsigned long expire
;
1279 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1280 expire
= missed_irq(dev_priv
, ring
) ? jiffies
+ 1 : timeout_expire
;
1281 mod_timer(&timer
, expire
);
1286 if (timer
.function
) {
1287 del_singleshot_timer_sync(&timer
);
1288 destroy_timer_on_stack(&timer
);
1291 now
= ktime_get_raw_ns();
1292 trace_i915_gem_request_wait_end(req
);
1294 if (!irq_test_in_progress
)
1295 ring
->irq_put(ring
);
1297 finish_wait(&ring
->irq_queue
, &wait
);
1300 s64 tres
= *timeout
- (now
- before
);
1302 *timeout
= tres
< 0 ? 0 : tres
;
1305 * Apparently ktime isn't accurate enough and occasionally has a
1306 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1307 * things up to make the test happy. We allow up to 1 jiffy.
1309 * This is a regrssion from the timespec->ktime conversion.
1311 if (ret
== -ETIME
&& *timeout
< jiffies_to_usecs(1)*1000)
1319 * Waits for a request to be signaled, and cleans up the
1320 * request and object lists appropriately for that event.
1323 i915_wait_request(struct drm_i915_gem_request
*req
)
1325 struct drm_device
*dev
;
1326 struct drm_i915_private
*dev_priv
;
1328 unsigned reset_counter
;
1331 BUG_ON(req
== NULL
);
1333 dev
= req
->ring
->dev
;
1334 dev_priv
= dev
->dev_private
;
1335 interruptible
= dev_priv
->mm
.interruptible
;
1337 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1339 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1343 ret
= i915_gem_check_olr(req
);
1347 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1348 i915_gem_request_reference(req
);
1349 ret
= __i915_wait_request(req
, reset_counter
,
1350 interruptible
, NULL
, NULL
);
1351 i915_gem_request_unreference(req
);
1356 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object
*obj
)
1361 /* Manually manage the write flush as we may have not yet
1362 * retired the buffer.
1364 * Note that the last_write_req is always the earlier of
1365 * the two (read/write) requests, so if we haved successfully waited,
1366 * we know we have passed the last write.
1368 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
1374 * Ensures that all rendering to the object has completed and the object is
1375 * safe to unbind from the GTT or access from the CPU.
1377 static __must_check
int
1378 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1381 struct drm_i915_gem_request
*req
;
1384 req
= readonly
? obj
->last_write_req
: obj
->last_read_req
;
1388 ret
= i915_wait_request(req
);
1392 return i915_gem_object_wait_rendering__tail(obj
);
1395 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1396 * as the object state may change during this call.
1398 static __must_check
int
1399 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1400 struct drm_i915_file_private
*file_priv
,
1403 struct drm_i915_gem_request
*req
;
1404 struct drm_device
*dev
= obj
->base
.dev
;
1405 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1406 unsigned reset_counter
;
1409 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1410 BUG_ON(!dev_priv
->mm
.interruptible
);
1412 req
= readonly
? obj
->last_write_req
: obj
->last_read_req
;
1416 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1420 ret
= i915_gem_check_olr(req
);
1424 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1425 i915_gem_request_reference(req
);
1426 mutex_unlock(&dev
->struct_mutex
);
1427 ret
= __i915_wait_request(req
, reset_counter
, true, NULL
, file_priv
);
1428 mutex_lock(&dev
->struct_mutex
);
1429 i915_gem_request_unreference(req
);
1433 return i915_gem_object_wait_rendering__tail(obj
);
1437 * Called when user space prepares to use an object with the CPU, either
1438 * through the mmap ioctl's mapping or a GTT mapping.
1441 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1442 struct drm_file
*file
)
1444 struct drm_i915_gem_set_domain
*args
= data
;
1445 struct drm_i915_gem_object
*obj
;
1446 uint32_t read_domains
= args
->read_domains
;
1447 uint32_t write_domain
= args
->write_domain
;
1450 /* Only handle setting domains to types used by the CPU. */
1451 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1454 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1457 /* Having something in the write domain implies it's in the read
1458 * domain, and only that read domain. Enforce that in the request.
1460 if (write_domain
!= 0 && read_domains
!= write_domain
)
1463 ret
= i915_mutex_lock_interruptible(dev
);
1467 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1468 if (&obj
->base
== NULL
) {
1473 /* Try to flush the object off the GPU without holding the lock.
1474 * We will repeat the flush holding the lock in the normal manner
1475 * to catch cases where we are gazumped.
1477 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1483 if (read_domains
& I915_GEM_DOMAIN_GTT
)
1484 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1486 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1489 drm_gem_object_unreference(&obj
->base
);
1491 mutex_unlock(&dev
->struct_mutex
);
1496 * Called when user space has done writes to this buffer
1499 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1500 struct drm_file
*file
)
1502 struct drm_i915_gem_sw_finish
*args
= data
;
1503 struct drm_i915_gem_object
*obj
;
1506 ret
= i915_mutex_lock_interruptible(dev
);
1510 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1511 if (&obj
->base
== NULL
) {
1516 /* Pinned buffers may be scanout, so flush the cache */
1517 if (obj
->pin_display
)
1518 i915_gem_object_flush_cpu_write_domain(obj
);
1520 drm_gem_object_unreference(&obj
->base
);
1522 mutex_unlock(&dev
->struct_mutex
);
1527 * Maps the contents of an object, returning the address it is mapped
1530 * While the mapping holds a reference on the contents of the object, it doesn't
1531 * imply a ref on the object itself.
1535 * DRM driver writers who look a this function as an example for how to do GEM
1536 * mmap support, please don't implement mmap support like here. The modern way
1537 * to implement DRM mmap support is with an mmap offset ioctl (like
1538 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1539 * That way debug tooling like valgrind will understand what's going on, hiding
1540 * the mmap call in a driver private ioctl will break that. The i915 driver only
1541 * does cpu mmaps this way because we didn't know better.
1544 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1545 struct drm_file
*file
)
1547 struct drm_i915_gem_mmap
*args
= data
;
1548 struct drm_gem_object
*obj
;
1551 if (args
->flags
& ~(I915_MMAP_WC
))
1554 if (args
->flags
& I915_MMAP_WC
&& !cpu_has_pat
)
1557 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1561 /* prime objects have no backing filp to GEM mmap
1565 drm_gem_object_unreference_unlocked(obj
);
1569 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1570 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1572 if (args
->flags
& I915_MMAP_WC
) {
1573 struct mm_struct
*mm
= current
->mm
;
1574 struct vm_area_struct
*vma
;
1576 down_write(&mm
->mmap_sem
);
1577 vma
= find_vma(mm
, addr
);
1580 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1583 up_write(&mm
->mmap_sem
);
1585 drm_gem_object_unreference_unlocked(obj
);
1586 if (IS_ERR((void *)addr
))
1589 args
->addr_ptr
= (uint64_t) addr
;
1595 * i915_gem_fault - fault a page into the GTT
1596 * vma: VMA in question
1599 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1600 * from userspace. The fault handler takes care of binding the object to
1601 * the GTT (if needed), allocating and programming a fence register (again,
1602 * only if needed based on whether the old reg is still valid or the object
1603 * is tiled) and inserting a new PTE into the faulting process.
1605 * Note that the faulting process may involve evicting existing objects
1606 * from the GTT and/or fence registers to make room. So performance may
1607 * suffer if the GTT working set is large or there are few fence registers
1610 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1612 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1613 struct drm_device
*dev
= obj
->base
.dev
;
1614 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1615 pgoff_t page_offset
;
1618 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1620 intel_runtime_pm_get(dev_priv
);
1622 /* We don't use vmf->pgoff since that has the fake offset */
1623 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1626 ret
= i915_mutex_lock_interruptible(dev
);
1630 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1632 /* Try to flush the object off the GPU first without holding the lock.
1633 * Upon reacquiring the lock, we will perform our sanity checks and then
1634 * repeat the flush holding the lock in the normal manner to catch cases
1635 * where we are gazumped.
1637 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
1641 /* Access to snoopable pages through the GTT is incoherent. */
1642 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1647 /* Now bind it into the GTT if needed */
1648 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
);
1652 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1656 ret
= i915_gem_object_get_fence(obj
);
1660 /* Finally, remap it using the new GTT offset */
1661 pfn
= dev_priv
->gtt
.mappable_base
+ i915_gem_obj_ggtt_offset(obj
);
1664 if (!obj
->fault_mappable
) {
1665 unsigned long size
= min_t(unsigned long,
1666 vma
->vm_end
- vma
->vm_start
,
1670 for (i
= 0; i
< size
>> PAGE_SHIFT
; i
++) {
1671 ret
= vm_insert_pfn(vma
,
1672 (unsigned long)vma
->vm_start
+ i
* PAGE_SIZE
,
1678 obj
->fault_mappable
= true;
1680 ret
= vm_insert_pfn(vma
,
1681 (unsigned long)vmf
->virtual_address
,
1684 i915_gem_object_ggtt_unpin(obj
);
1686 mutex_unlock(&dev
->struct_mutex
);
1691 * We eat errors when the gpu is terminally wedged to avoid
1692 * userspace unduly crashing (gl has no provisions for mmaps to
1693 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1694 * and so needs to be reported.
1696 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1697 ret
= VM_FAULT_SIGBUS
;
1702 * EAGAIN means the gpu is hung and we'll wait for the error
1703 * handler to reset everything when re-faulting in
1704 * i915_mutex_lock_interruptible.
1711 * EBUSY is ok: this just means that another thread
1712 * already did the job.
1714 ret
= VM_FAULT_NOPAGE
;
1721 ret
= VM_FAULT_SIGBUS
;
1724 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1725 ret
= VM_FAULT_SIGBUS
;
1729 intel_runtime_pm_put(dev_priv
);
1734 * i915_gem_release_mmap - remove physical page mappings
1735 * @obj: obj in question
1737 * Preserve the reservation of the mmapping with the DRM core code, but
1738 * relinquish ownership of the pages back to the system.
1740 * It is vital that we remove the page mapping if we have mapped a tiled
1741 * object through the GTT and then lose the fence register due to
1742 * resource pressure. Similarly if the object has been moved out of the
1743 * aperture, than pages mapped into userspace must be revoked. Removing the
1744 * mapping will then trigger a page fault on the next user access, allowing
1745 * fixup by i915_gem_fault().
1748 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1750 if (!obj
->fault_mappable
)
1753 drm_vma_node_unmap(&obj
->base
.vma_node
,
1754 obj
->base
.dev
->anon_inode
->i_mapping
);
1755 obj
->fault_mappable
= false;
1759 i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
1761 struct drm_i915_gem_object
*obj
;
1763 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
1764 i915_gem_release_mmap(obj
);
1768 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1772 if (INTEL_INFO(dev
)->gen
>= 4 ||
1773 tiling_mode
== I915_TILING_NONE
)
1776 /* Previous chips need a power-of-two fence region when tiling */
1777 if (INTEL_INFO(dev
)->gen
== 3)
1778 gtt_size
= 1024*1024;
1780 gtt_size
= 512*1024;
1782 while (gtt_size
< size
)
1789 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1790 * @obj: object to check
1792 * Return the required GTT alignment for an object, taking into account
1793 * potential fence register mapping.
1796 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1797 int tiling_mode
, bool fenced
)
1800 * Minimum alignment is 4k (GTT page size), but might be greater
1801 * if a fence register is needed for the object.
1803 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1804 tiling_mode
== I915_TILING_NONE
)
1808 * Previous chips need to be aligned to the size of the smallest
1809 * fence register that can contain the object.
1811 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1814 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1816 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1819 if (drm_vma_node_has_offset(&obj
->base
.vma_node
))
1822 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1824 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1828 /* Badly fragmented mmap space? The only way we can recover
1829 * space is by destroying unwanted objects. We can't randomly release
1830 * mmap_offsets as userspace expects them to be persistent for the
1831 * lifetime of the objects. The closest we can is to release the
1832 * offsets on purgeable objects by truncating it and marking it purged,
1833 * which prevents userspace from ever using that object again.
1835 i915_gem_shrink(dev_priv
,
1836 obj
->base
.size
>> PAGE_SHIFT
,
1838 I915_SHRINK_UNBOUND
|
1839 I915_SHRINK_PURGEABLE
);
1840 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1844 i915_gem_shrink_all(dev_priv
);
1845 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1847 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
1852 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1854 drm_gem_free_mmap_offset(&obj
->base
);
1858 i915_gem_mmap_gtt(struct drm_file
*file
,
1859 struct drm_device
*dev
,
1863 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1864 struct drm_i915_gem_object
*obj
;
1867 ret
= i915_mutex_lock_interruptible(dev
);
1871 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1872 if (&obj
->base
== NULL
) {
1877 if (obj
->base
.size
> dev_priv
->gtt
.mappable_end
) {
1882 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1883 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1888 ret
= i915_gem_object_create_mmap_offset(obj
);
1892 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
1895 drm_gem_object_unreference(&obj
->base
);
1897 mutex_unlock(&dev
->struct_mutex
);
1902 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1904 * @data: GTT mapping ioctl data
1905 * @file: GEM object info
1907 * Simply returns the fake offset to userspace so it can mmap it.
1908 * The mmap call will end up in drm_gem_mmap(), which will set things
1909 * up so we can get faults in the handler above.
1911 * The fault handler will take care of binding the object into the GTT
1912 * (since it may have been evicted to make room for something), allocating
1913 * a fence register, and mapping the appropriate aperture address into
1917 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1918 struct drm_file
*file
)
1920 struct drm_i915_gem_mmap_gtt
*args
= data
;
1922 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1926 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1928 return obj
->madv
== I915_MADV_DONTNEED
;
1931 /* Immediately discard the backing storage */
1933 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1935 i915_gem_object_free_mmap_offset(obj
);
1937 if (obj
->base
.filp
== NULL
)
1940 /* Our goal here is to return as much of the memory as
1941 * is possible back to the system as we are called from OOM.
1942 * To do this we must instruct the shmfs to drop all of its
1943 * backing pages, *now*.
1945 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
1946 obj
->madv
= __I915_MADV_PURGED
;
1949 /* Try to discard unwanted pages */
1951 i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
1953 struct address_space
*mapping
;
1955 switch (obj
->madv
) {
1956 case I915_MADV_DONTNEED
:
1957 i915_gem_object_truncate(obj
);
1958 case __I915_MADV_PURGED
:
1962 if (obj
->base
.filp
== NULL
)
1965 mapping
= file_inode(obj
->base
.filp
)->i_mapping
,
1966 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
1970 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1972 struct sg_page_iter sg_iter
;
1975 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1977 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1979 /* In the event of a disaster, abandon all caches and
1980 * hope for the best.
1982 WARN_ON(ret
!= -EIO
);
1983 i915_gem_clflush_object(obj
, true);
1984 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
1987 if (i915_gem_object_needs_bit17_swizzle(obj
))
1988 i915_gem_object_save_bit_17_swizzle(obj
);
1990 if (obj
->madv
== I915_MADV_DONTNEED
)
1993 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
1994 struct page
*page
= sg_page_iter_page(&sg_iter
);
1997 set_page_dirty(page
);
1999 if (obj
->madv
== I915_MADV_WILLNEED
)
2000 mark_page_accessed(page
);
2002 page_cache_release(page
);
2006 sg_free_table(obj
->pages
);
2011 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
2013 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2015 if (obj
->pages
== NULL
)
2018 if (obj
->pages_pin_count
)
2021 BUG_ON(i915_gem_obj_bound_any(obj
));
2023 /* ->put_pages might need to allocate memory for the bit17 swizzle
2024 * array, hence protect them from being reaped by removing them from gtt
2026 list_del(&obj
->global_list
);
2028 ops
->put_pages(obj
);
2031 i915_gem_object_invalidate(obj
);
2037 i915_gem_shrink(struct drm_i915_private
*dev_priv
,
2038 long target
, unsigned flags
)
2041 struct list_head
*list
;
2044 { &dev_priv
->mm
.unbound_list
, I915_SHRINK_UNBOUND
},
2045 { &dev_priv
->mm
.bound_list
, I915_SHRINK_BOUND
},
2048 unsigned long count
= 0;
2051 * As we may completely rewrite the (un)bound list whilst unbinding
2052 * (due to retiring requests) we have to strictly process only
2053 * one element of the list at the time, and recheck the list
2054 * on every iteration.
2056 * In particular, we must hold a reference whilst removing the
2057 * object as we may end up waiting for and/or retiring the objects.
2058 * This might release the final reference (held by the active list)
2059 * and result in the object being freed from under us. This is
2060 * similar to the precautions the eviction code must take whilst
2063 * Also note that although these lists do not hold a reference to
2064 * the object we can safely grab one here: The final object
2065 * unreferencing and the bound_list are both protected by the
2066 * dev->struct_mutex and so we won't ever be able to observe an
2067 * object on the bound_list with a reference count equals 0.
2069 for (phase
= phases
; phase
->list
; phase
++) {
2070 struct list_head still_in_list
;
2072 if ((flags
& phase
->bit
) == 0)
2075 INIT_LIST_HEAD(&still_in_list
);
2076 while (count
< target
&& !list_empty(phase
->list
)) {
2077 struct drm_i915_gem_object
*obj
;
2078 struct i915_vma
*vma
, *v
;
2080 obj
= list_first_entry(phase
->list
,
2081 typeof(*obj
), global_list
);
2082 list_move_tail(&obj
->global_list
, &still_in_list
);
2084 if (flags
& I915_SHRINK_PURGEABLE
&&
2085 !i915_gem_object_is_purgeable(obj
))
2088 drm_gem_object_reference(&obj
->base
);
2090 /* For the unbound phase, this should be a no-op! */
2091 list_for_each_entry_safe(vma
, v
,
2092 &obj
->vma_list
, vma_link
)
2093 if (i915_vma_unbind(vma
))
2096 if (i915_gem_object_put_pages(obj
) == 0)
2097 count
+= obj
->base
.size
>> PAGE_SHIFT
;
2099 drm_gem_object_unreference(&obj
->base
);
2101 list_splice(&still_in_list
, phase
->list
);
2107 static unsigned long
2108 i915_gem_shrink_all(struct drm_i915_private
*dev_priv
)
2110 i915_gem_evict_everything(dev_priv
->dev
);
2111 return i915_gem_shrink(dev_priv
, LONG_MAX
,
2112 I915_SHRINK_BOUND
| I915_SHRINK_UNBOUND
);
2116 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2118 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2120 struct address_space
*mapping
;
2121 struct sg_table
*st
;
2122 struct scatterlist
*sg
;
2123 struct sg_page_iter sg_iter
;
2125 unsigned long last_pfn
= 0; /* suppress gcc warning */
2128 /* Assert that the object is not currently in any GPU domain. As it
2129 * wasn't in the GTT, there shouldn't be any way it could have been in
2132 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2133 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2135 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2139 page_count
= obj
->base
.size
/ PAGE_SIZE
;
2140 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2145 /* Get the list of pages out of our struct file. They'll be pinned
2146 * at this point until we release them.
2148 * Fail silently without starting the shrinker
2150 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
2151 gfp
= mapping_gfp_mask(mapping
);
2152 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
2153 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
2156 for (i
= 0; i
< page_count
; i
++) {
2157 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2159 i915_gem_shrink(dev_priv
,
2162 I915_SHRINK_UNBOUND
|
2163 I915_SHRINK_PURGEABLE
);
2164 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2167 /* We've tried hard to allocate the memory by reaping
2168 * our own buffer, now let the real VM do its job and
2169 * go down in flames if truly OOM.
2171 i915_gem_shrink_all(dev_priv
);
2172 page
= shmem_read_mapping_page(mapping
, i
);
2176 #ifdef CONFIG_SWIOTLB
2177 if (swiotlb_nr_tbl()) {
2179 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2184 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
2188 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2190 sg
->length
+= PAGE_SIZE
;
2192 last_pfn
= page_to_pfn(page
);
2194 /* Check that the i965g/gm workaround works. */
2195 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2197 #ifdef CONFIG_SWIOTLB
2198 if (!swiotlb_nr_tbl())
2203 if (i915_gem_object_needs_bit17_swizzle(obj
))
2204 i915_gem_object_do_bit_17_swizzle(obj
);
2206 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
2207 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2208 i915_gem_object_pin_pages(obj
);
2214 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
2215 page_cache_release(sg_page_iter_page(&sg_iter
));
2219 /* shmemfs first checks if there is enough memory to allocate the page
2220 * and reports ENOSPC should there be insufficient, along with the usual
2221 * ENOMEM for a genuine allocation failure.
2223 * We use ENOSPC in our driver to mean that we have run out of aperture
2224 * space and so want to translate the error from shmemfs back to our
2225 * usual understanding of ENOMEM.
2227 if (PTR_ERR(page
) == -ENOSPC
)
2230 return PTR_ERR(page
);
2233 /* Ensure that the associated pages are gathered from the backing storage
2234 * and pinned into our object. i915_gem_object_get_pages() may be called
2235 * multiple times before they are released by a single call to
2236 * i915_gem_object_put_pages() - once the pages are no longer referenced
2237 * either as a result of memory pressure (reaping pages under the shrinker)
2238 * or as the object is itself released.
2241 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2243 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2244 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2250 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2251 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2255 BUG_ON(obj
->pages_pin_count
);
2257 ret
= ops
->get_pages(obj
);
2261 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2266 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
2267 struct intel_engine_cs
*ring
)
2269 struct drm_i915_gem_request
*req
;
2270 struct intel_engine_cs
*old_ring
;
2272 BUG_ON(ring
== NULL
);
2274 req
= intel_ring_get_request(ring
);
2275 old_ring
= i915_gem_request_get_ring(obj
->last_read_req
);
2277 if (old_ring
!= ring
&& obj
->last_write_req
) {
2278 /* Keep the request relative to the current ring */
2279 i915_gem_request_assign(&obj
->last_write_req
, req
);
2282 /* Add a reference if we're newly entering the active list. */
2284 drm_gem_object_reference(&obj
->base
);
2288 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
2290 i915_gem_request_assign(&obj
->last_read_req
, req
);
2293 void i915_vma_move_to_active(struct i915_vma
*vma
,
2294 struct intel_engine_cs
*ring
)
2296 list_move_tail(&vma
->mm_list
, &vma
->vm
->active_list
);
2297 return i915_gem_object_move_to_active(vma
->obj
, ring
);
2301 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
2303 struct i915_vma
*vma
;
2305 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
2306 BUG_ON(!obj
->active
);
2308 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
2309 if (!list_empty(&vma
->mm_list
))
2310 list_move_tail(&vma
->mm_list
, &vma
->vm
->inactive_list
);
2313 intel_fb_obj_flush(obj
, true);
2315 list_del_init(&obj
->ring_list
);
2317 i915_gem_request_assign(&obj
->last_read_req
, NULL
);
2318 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
2319 obj
->base
.write_domain
= 0;
2321 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
2324 drm_gem_object_unreference(&obj
->base
);
2326 WARN_ON(i915_verify_lists(dev
));
2330 i915_gem_object_retire(struct drm_i915_gem_object
*obj
)
2332 if (obj
->last_read_req
== NULL
)
2335 if (i915_gem_request_completed(obj
->last_read_req
, true))
2336 i915_gem_object_move_to_inactive(obj
);
2340 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
2342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2343 struct intel_engine_cs
*ring
;
2346 /* Carefully retire all requests without writing to the rings */
2347 for_each_ring(ring
, dev_priv
, i
) {
2348 ret
= intel_ring_idle(ring
);
2352 i915_gem_retire_requests(dev
);
2354 /* Finally reset hw state */
2355 for_each_ring(ring
, dev_priv
, i
) {
2356 intel_ring_init_seqno(ring
, seqno
);
2358 for (j
= 0; j
< ARRAY_SIZE(ring
->semaphore
.sync_seqno
); j
++)
2359 ring
->semaphore
.sync_seqno
[j
] = 0;
2365 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2367 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2373 /* HWS page needs to be set less than what we
2374 * will inject to ring
2376 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
2380 /* Carefully set the last_seqno value so that wrap
2381 * detection still works
2383 dev_priv
->next_seqno
= seqno
;
2384 dev_priv
->last_seqno
= seqno
- 1;
2385 if (dev_priv
->last_seqno
== 0)
2386 dev_priv
->last_seqno
--;
2392 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
2394 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2396 /* reserve 0 for non-seqno */
2397 if (dev_priv
->next_seqno
== 0) {
2398 int ret
= i915_gem_init_seqno(dev
, 0);
2402 dev_priv
->next_seqno
= 1;
2405 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2409 int __i915_add_request(struct intel_engine_cs
*ring
,
2410 struct drm_file
*file
,
2411 struct drm_i915_gem_object
*obj
)
2413 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2414 struct drm_i915_gem_request
*request
;
2415 struct intel_ringbuffer
*ringbuf
;
2419 request
= ring
->outstanding_lazy_request
;
2420 if (WARN_ON(request
== NULL
))
2423 if (i915
.enable_execlists
) {
2424 ringbuf
= request
->ctx
->engine
[ring
->id
].ringbuf
;
2426 ringbuf
= ring
->buffer
;
2428 request_start
= intel_ring_get_tail(ringbuf
);
2430 * Emit any outstanding flushes - execbuf can fail to emit the flush
2431 * after having emitted the batchbuffer command. Hence we need to fix
2432 * things up similar to emitting the lazy request. The difference here
2433 * is that the flush _must_ happen before the next request, no matter
2436 if (i915
.enable_execlists
) {
2437 ret
= logical_ring_flush_all_caches(ringbuf
, request
->ctx
);
2441 ret
= intel_ring_flush_all_caches(ring
);
2446 /* Record the position of the start of the request so that
2447 * should we detect the updated seqno part-way through the
2448 * GPU processing the request, we never over-estimate the
2449 * position of the head.
2451 request
->postfix
= intel_ring_get_tail(ringbuf
);
2453 if (i915
.enable_execlists
) {
2454 ret
= ring
->emit_request(ringbuf
, request
);
2458 ret
= ring
->add_request(ring
);
2463 request
->head
= request_start
;
2464 request
->tail
= intel_ring_get_tail(ringbuf
);
2466 /* Whilst this request exists, batch_obj will be on the
2467 * active_list, and so will hold the active reference. Only when this
2468 * request is retired will the the batch_obj be moved onto the
2469 * inactive_list and lose its active reference. Hence we do not need
2470 * to explicitly hold another reference here.
2472 request
->batch_obj
= obj
;
2474 if (!i915
.enable_execlists
) {
2475 /* Hold a reference to the current context so that we can inspect
2476 * it later in case a hangcheck error event fires.
2478 request
->ctx
= ring
->last_context
;
2480 i915_gem_context_reference(request
->ctx
);
2483 request
->emitted_jiffies
= jiffies
;
2484 list_add_tail(&request
->list
, &ring
->request_list
);
2485 request
->file_priv
= NULL
;
2488 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2490 spin_lock(&file_priv
->mm
.lock
);
2491 request
->file_priv
= file_priv
;
2492 list_add_tail(&request
->client_list
,
2493 &file_priv
->mm
.request_list
);
2494 spin_unlock(&file_priv
->mm
.lock
);
2497 trace_i915_gem_request_add(request
);
2498 ring
->outstanding_lazy_request
= NULL
;
2500 i915_queue_hangcheck(ring
->dev
);
2502 cancel_delayed_work_sync(&dev_priv
->mm
.idle_work
);
2503 queue_delayed_work(dev_priv
->wq
,
2504 &dev_priv
->mm
.retire_work
,
2505 round_jiffies_up_relative(HZ
));
2506 intel_mark_busy(dev_priv
->dev
);
2512 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2514 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2519 spin_lock(&file_priv
->mm
.lock
);
2520 list_del(&request
->client_list
);
2521 request
->file_priv
= NULL
;
2522 spin_unlock(&file_priv
->mm
.lock
);
2525 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2526 const struct intel_context
*ctx
)
2528 unsigned long elapsed
;
2530 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2532 if (ctx
->hang_stats
.banned
)
2535 if (ctx
->hang_stats
.ban_period_seconds
&&
2536 elapsed
<= ctx
->hang_stats
.ban_period_seconds
) {
2537 if (!i915_gem_context_is_default(ctx
)) {
2538 DRM_DEBUG("context hanging too fast, banning!\n");
2540 } else if (i915_stop_ring_allow_ban(dev_priv
)) {
2541 if (i915_stop_ring_allow_warn(dev_priv
))
2542 DRM_ERROR("gpu hanging too fast, banning!\n");
2550 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2551 struct intel_context
*ctx
,
2554 struct i915_ctx_hang_stats
*hs
;
2559 hs
= &ctx
->hang_stats
;
2562 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2564 hs
->guilty_ts
= get_seconds();
2566 hs
->batch_pending
++;
2570 static void i915_gem_free_request(struct drm_i915_gem_request
*request
)
2572 list_del(&request
->list
);
2573 i915_gem_request_remove_from_client(request
);
2575 i915_gem_request_unreference(request
);
2578 void i915_gem_request_free(struct kref
*req_ref
)
2580 struct drm_i915_gem_request
*req
= container_of(req_ref
,
2582 struct intel_context
*ctx
= req
->ctx
;
2585 if (i915
.enable_execlists
) {
2586 struct intel_engine_cs
*ring
= req
->ring
;
2588 if (ctx
!= ring
->default_context
)
2589 intel_lr_context_unpin(ring
, ctx
);
2592 i915_gem_context_unreference(ctx
);
2598 struct drm_i915_gem_request
*
2599 i915_gem_find_active_request(struct intel_engine_cs
*ring
)
2601 struct drm_i915_gem_request
*request
;
2603 list_for_each_entry(request
, &ring
->request_list
, list
) {
2604 if (i915_gem_request_completed(request
, false))
2613 static void i915_gem_reset_ring_status(struct drm_i915_private
*dev_priv
,
2614 struct intel_engine_cs
*ring
)
2616 struct drm_i915_gem_request
*request
;
2619 request
= i915_gem_find_active_request(ring
);
2621 if (request
== NULL
)
2624 ring_hung
= ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
2626 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
2628 list_for_each_entry_continue(request
, &ring
->request_list
, list
)
2629 i915_set_reset_status(dev_priv
, request
->ctx
, false);
2632 static void i915_gem_reset_ring_cleanup(struct drm_i915_private
*dev_priv
,
2633 struct intel_engine_cs
*ring
)
2635 while (!list_empty(&ring
->active_list
)) {
2636 struct drm_i915_gem_object
*obj
;
2638 obj
= list_first_entry(&ring
->active_list
,
2639 struct drm_i915_gem_object
,
2642 i915_gem_object_move_to_inactive(obj
);
2646 * Clear the execlists queue up before freeing the requests, as those
2647 * are the ones that keep the context and ringbuffer backing objects
2650 while (!list_empty(&ring
->execlist_queue
)) {
2651 struct drm_i915_gem_request
*submit_req
;
2653 submit_req
= list_first_entry(&ring
->execlist_queue
,
2654 struct drm_i915_gem_request
,
2656 list_del(&submit_req
->execlist_link
);
2657 intel_runtime_pm_put(dev_priv
);
2659 if (submit_req
->ctx
!= ring
->default_context
)
2660 intel_lr_context_unpin(ring
, submit_req
->ctx
);
2662 i915_gem_context_unreference(submit_req
->ctx
);
2667 * We must free the requests after all the corresponding objects have
2668 * been moved off active lists. Which is the same order as the normal
2669 * retire_requests function does. This is important if object hold
2670 * implicit references on things like e.g. ppgtt address spaces through
2673 while (!list_empty(&ring
->request_list
)) {
2674 struct drm_i915_gem_request
*request
;
2676 request
= list_first_entry(&ring
->request_list
,
2677 struct drm_i915_gem_request
,
2680 i915_gem_free_request(request
);
2683 /* This may not have been flushed before the reset, so clean it now */
2684 i915_gem_request_assign(&ring
->outstanding_lazy_request
, NULL
);
2687 void i915_gem_restore_fences(struct drm_device
*dev
)
2689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2692 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2693 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2696 * Commit delayed tiling changes if we have an object still
2697 * attached to the fence, otherwise just clear the fence.
2700 i915_gem_object_update_fence(reg
->obj
, reg
,
2701 reg
->obj
->tiling_mode
);
2703 i915_gem_write_fence(dev
, i
, NULL
);
2708 void i915_gem_reset(struct drm_device
*dev
)
2710 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2711 struct intel_engine_cs
*ring
;
2715 * Before we free the objects from the requests, we need to inspect
2716 * them for finding the guilty party. As the requests only borrow
2717 * their reference to the objects, the inspection must be done first.
2719 for_each_ring(ring
, dev_priv
, i
)
2720 i915_gem_reset_ring_status(dev_priv
, ring
);
2722 for_each_ring(ring
, dev_priv
, i
)
2723 i915_gem_reset_ring_cleanup(dev_priv
, ring
);
2725 i915_gem_context_reset(dev
);
2727 i915_gem_restore_fences(dev
);
2731 * This function clears the request list as sequence numbers are passed.
2734 i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
)
2736 if (list_empty(&ring
->request_list
))
2739 WARN_ON(i915_verify_lists(ring
->dev
));
2741 /* Move any buffers on the active list that are no longer referenced
2742 * by the ringbuffer to the flushing/inactive lists as appropriate,
2743 * before we free the context associated with the requests.
2745 while (!list_empty(&ring
->active_list
)) {
2746 struct drm_i915_gem_object
*obj
;
2748 obj
= list_first_entry(&ring
->active_list
,
2749 struct drm_i915_gem_object
,
2752 if (!i915_gem_request_completed(obj
->last_read_req
, true))
2755 i915_gem_object_move_to_inactive(obj
);
2759 while (!list_empty(&ring
->request_list
)) {
2760 struct drm_i915_gem_request
*request
;
2761 struct intel_ringbuffer
*ringbuf
;
2763 request
= list_first_entry(&ring
->request_list
,
2764 struct drm_i915_gem_request
,
2767 if (!i915_gem_request_completed(request
, true))
2770 trace_i915_gem_request_retire(request
);
2772 /* This is one of the few common intersection points
2773 * between legacy ringbuffer submission and execlists:
2774 * we need to tell them apart in order to find the correct
2775 * ringbuffer to which the request belongs to.
2777 if (i915
.enable_execlists
) {
2778 struct intel_context
*ctx
= request
->ctx
;
2779 ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
2781 ringbuf
= ring
->buffer
;
2783 /* We know the GPU must have read the request to have
2784 * sent us the seqno + interrupt, so use the position
2785 * of tail of the request to update the last known position
2788 ringbuf
->last_retired_head
= request
->postfix
;
2790 i915_gem_free_request(request
);
2793 if (unlikely(ring
->trace_irq_req
&&
2794 i915_gem_request_completed(ring
->trace_irq_req
, true))) {
2795 ring
->irq_put(ring
);
2796 i915_gem_request_assign(&ring
->trace_irq_req
, NULL
);
2799 WARN_ON(i915_verify_lists(ring
->dev
));
2803 i915_gem_retire_requests(struct drm_device
*dev
)
2805 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2806 struct intel_engine_cs
*ring
;
2810 for_each_ring(ring
, dev_priv
, i
) {
2811 i915_gem_retire_requests_ring(ring
);
2812 idle
&= list_empty(&ring
->request_list
);
2813 if (i915
.enable_execlists
) {
2814 unsigned long flags
;
2816 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
2817 idle
&= list_empty(&ring
->execlist_queue
);
2818 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
2820 intel_execlists_retire_requests(ring
);
2825 mod_delayed_work(dev_priv
->wq
,
2826 &dev_priv
->mm
.idle_work
,
2827 msecs_to_jiffies(100));
2833 i915_gem_retire_work_handler(struct work_struct
*work
)
2835 struct drm_i915_private
*dev_priv
=
2836 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
2837 struct drm_device
*dev
= dev_priv
->dev
;
2840 /* Come back later if the device is busy... */
2842 if (mutex_trylock(&dev
->struct_mutex
)) {
2843 idle
= i915_gem_retire_requests(dev
);
2844 mutex_unlock(&dev
->struct_mutex
);
2847 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2848 round_jiffies_up_relative(HZ
));
2852 i915_gem_idle_work_handler(struct work_struct
*work
)
2854 struct drm_i915_private
*dev_priv
=
2855 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
2857 intel_mark_idle(dev_priv
->dev
);
2861 * Ensures that an object will eventually get non-busy by flushing any required
2862 * write domains, emitting any outstanding lazy request and retiring and
2863 * completed requests.
2866 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2868 struct intel_engine_cs
*ring
;
2872 ring
= i915_gem_request_get_ring(obj
->last_read_req
);
2874 ret
= i915_gem_check_olr(obj
->last_read_req
);
2878 i915_gem_retire_requests_ring(ring
);
2885 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2886 * @DRM_IOCTL_ARGS: standard ioctl arguments
2888 * Returns 0 if successful, else an error is returned with the remaining time in
2889 * the timeout parameter.
2890 * -ETIME: object is still busy after timeout
2891 * -ERESTARTSYS: signal interrupted the wait
2892 * -ENONENT: object doesn't exist
2893 * Also possible, but rare:
2894 * -EAGAIN: GPU wedged
2896 * -ENODEV: Internal IRQ fail
2897 * -E?: The add request failed
2899 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2900 * non-zero timeout parameter the wait ioctl will wait for the given number of
2901 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2902 * without holding struct_mutex the object may become re-busied before this
2903 * function completes. A similar but shorter * race condition exists in the busy
2907 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2909 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2910 struct drm_i915_gem_wait
*args
= data
;
2911 struct drm_i915_gem_object
*obj
;
2912 struct drm_i915_gem_request
*req
;
2913 unsigned reset_counter
;
2916 if (args
->flags
!= 0)
2919 ret
= i915_mutex_lock_interruptible(dev
);
2923 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2924 if (&obj
->base
== NULL
) {
2925 mutex_unlock(&dev
->struct_mutex
);
2929 /* Need to make sure the object gets inactive eventually. */
2930 ret
= i915_gem_object_flush_active(obj
);
2934 if (!obj
->active
|| !obj
->last_read_req
)
2937 req
= obj
->last_read_req
;
2939 /* Do this after OLR check to make sure we make forward progress polling
2940 * on this IOCTL with a timeout <=0 (like busy ioctl)
2942 if (args
->timeout_ns
<= 0) {
2947 drm_gem_object_unreference(&obj
->base
);
2948 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
2949 i915_gem_request_reference(req
);
2950 mutex_unlock(&dev
->struct_mutex
);
2952 ret
= __i915_wait_request(req
, reset_counter
, true, &args
->timeout_ns
,
2954 mutex_lock(&dev
->struct_mutex
);
2955 i915_gem_request_unreference(req
);
2956 mutex_unlock(&dev
->struct_mutex
);
2960 drm_gem_object_unreference(&obj
->base
);
2961 mutex_unlock(&dev
->struct_mutex
);
2966 * i915_gem_object_sync - sync an object to a ring.
2968 * @obj: object which may be in use on another ring.
2969 * @to: ring we wish to use the object on. May be NULL.
2971 * This code is meant to abstract object synchronization with the GPU.
2972 * Calling with NULL implies synchronizing the object with the CPU
2973 * rather than a particular GPU ring.
2975 * Returns 0 if successful, else propagates up the lower layer error.
2978 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2979 struct intel_engine_cs
*to
)
2981 struct intel_engine_cs
*from
;
2985 from
= i915_gem_request_get_ring(obj
->last_read_req
);
2987 if (from
== NULL
|| to
== from
)
2990 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2991 return i915_gem_object_wait_rendering(obj
, false);
2993 idx
= intel_ring_sync_index(from
, to
);
2995 seqno
= i915_gem_request_get_seqno(obj
->last_read_req
);
2996 /* Optimization: Avoid semaphore sync when we are sure we already
2997 * waited for an object with higher seqno */
2998 if (seqno
<= from
->semaphore
.sync_seqno
[idx
])
3001 ret
= i915_gem_check_olr(obj
->last_read_req
);
3005 trace_i915_gem_ring_sync_to(from
, to
, obj
->last_read_req
);
3006 ret
= to
->semaphore
.sync_to(to
, from
, seqno
);
3008 /* We use last_read_req because sync_to()
3009 * might have just caused seqno wrap under
3012 from
->semaphore
.sync_seqno
[idx
] =
3013 i915_gem_request_get_seqno(obj
->last_read_req
);
3018 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
3020 u32 old_write_domain
, old_read_domains
;
3022 /* Force a pagefault for domain tracking on next user access */
3023 i915_gem_release_mmap(obj
);
3025 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3028 /* Wait for any direct GTT access to complete */
3031 old_read_domains
= obj
->base
.read_domains
;
3032 old_write_domain
= obj
->base
.write_domain
;
3034 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
3035 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
3037 trace_i915_gem_object_change_domain(obj
,
3042 int i915_vma_unbind(struct i915_vma
*vma
)
3044 struct drm_i915_gem_object
*obj
= vma
->obj
;
3045 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3048 if (list_empty(&vma
->vma_link
))
3051 if (!drm_mm_node_allocated(&vma
->node
)) {
3052 i915_gem_vma_destroy(vma
);
3059 BUG_ON(obj
->pages
== NULL
);
3061 ret
= i915_gem_object_finish_gpu(obj
);
3064 /* Continue on if we fail due to EIO, the GPU is hung so we
3065 * should be safe and we need to cleanup or else we might
3066 * cause memory corruption through use-after-free.
3069 if (i915_is_ggtt(vma
->vm
) &&
3070 vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3071 i915_gem_object_finish_gtt(obj
);
3073 /* release the fence reg _after_ flushing */
3074 ret
= i915_gem_object_put_fence(obj
);
3079 trace_i915_vma_unbind(vma
);
3081 vma
->unbind_vma(vma
);
3083 list_del_init(&vma
->mm_list
);
3084 if (i915_is_ggtt(vma
->vm
)) {
3085 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3086 obj
->map_and_fenceable
= false;
3087 } else if (vma
->ggtt_view
.pages
) {
3088 sg_free_table(vma
->ggtt_view
.pages
);
3089 kfree(vma
->ggtt_view
.pages
);
3090 vma
->ggtt_view
.pages
= NULL
;
3094 drm_mm_remove_node(&vma
->node
);
3095 i915_gem_vma_destroy(vma
);
3097 /* Since the unbound list is global, only move to that list if
3098 * no more VMAs exist. */
3099 if (list_empty(&obj
->vma_list
)) {
3100 /* Throw away the active reference before
3101 * moving to the unbound list. */
3102 i915_gem_object_retire(obj
);
3104 i915_gem_gtt_finish_object(obj
);
3105 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
3108 /* And finally now the object is completely decoupled from this vma,
3109 * we can drop its hold on the backing storage and allow it to be
3110 * reaped by the shrinker.
3112 i915_gem_object_unpin_pages(obj
);
3117 int i915_gpu_idle(struct drm_device
*dev
)
3119 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3120 struct intel_engine_cs
*ring
;
3123 /* Flush everything onto the inactive list. */
3124 for_each_ring(ring
, dev_priv
, i
) {
3125 if (!i915
.enable_execlists
) {
3126 ret
= i915_switch_context(ring
, ring
->default_context
);
3131 ret
= intel_ring_idle(ring
);
3139 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
3140 struct drm_i915_gem_object
*obj
)
3142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3144 int fence_pitch_shift
;
3146 if (INTEL_INFO(dev
)->gen
>= 6) {
3147 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
3148 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
3150 fence_reg
= FENCE_REG_965_0
;
3151 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
3154 fence_reg
+= reg
* 8;
3156 /* To w/a incoherency with non-atomic 64-bit register updates,
3157 * we split the 64-bit update into two 32-bit writes. In order
3158 * for a partial fence not to be evaluated between writes, we
3159 * precede the update with write to turn off the fence register,
3160 * and only enable the fence as the last step.
3162 * For extra levels of paranoia, we make sure each step lands
3163 * before applying the next step.
3165 I915_WRITE(fence_reg
, 0);
3166 POSTING_READ(fence_reg
);
3169 u32 size
= i915_gem_obj_ggtt_size(obj
);
3172 val
= (uint64_t)((i915_gem_obj_ggtt_offset(obj
) + size
- 4096) &
3174 val
|= i915_gem_obj_ggtt_offset(obj
) & 0xfffff000;
3175 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
3176 if (obj
->tiling_mode
== I915_TILING_Y
)
3177 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
3178 val
|= I965_FENCE_REG_VALID
;
3180 I915_WRITE(fence_reg
+ 4, val
>> 32);
3181 POSTING_READ(fence_reg
+ 4);
3183 I915_WRITE(fence_reg
+ 0, val
);
3184 POSTING_READ(fence_reg
);
3186 I915_WRITE(fence_reg
+ 4, 0);
3187 POSTING_READ(fence_reg
+ 4);
3191 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
3192 struct drm_i915_gem_object
*obj
)
3194 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3198 u32 size
= i915_gem_obj_ggtt_size(obj
);
3202 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I915_FENCE_START_MASK
) ||
3203 (size
& -size
) != size
||
3204 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3205 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3206 i915_gem_obj_ggtt_offset(obj
), obj
->map_and_fenceable
, size
);
3208 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
3213 /* Note: pitch better be a power of two tile widths */
3214 pitch_val
= obj
->stride
/ tile_width
;
3215 pitch_val
= ffs(pitch_val
) - 1;
3217 val
= i915_gem_obj_ggtt_offset(obj
);
3218 if (obj
->tiling_mode
== I915_TILING_Y
)
3219 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3220 val
|= I915_FENCE_SIZE_BITS(size
);
3221 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3222 val
|= I830_FENCE_REG_VALID
;
3227 reg
= FENCE_REG_830_0
+ reg
* 4;
3229 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
3231 I915_WRITE(reg
, val
);
3235 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
3236 struct drm_i915_gem_object
*obj
)
3238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3242 u32 size
= i915_gem_obj_ggtt_size(obj
);
3245 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I830_FENCE_START_MASK
) ||
3246 (size
& -size
) != size
||
3247 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3248 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3249 i915_gem_obj_ggtt_offset(obj
), size
);
3251 pitch_val
= obj
->stride
/ 128;
3252 pitch_val
= ffs(pitch_val
) - 1;
3254 val
= i915_gem_obj_ggtt_offset(obj
);
3255 if (obj
->tiling_mode
== I915_TILING_Y
)
3256 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3257 val
|= I830_FENCE_SIZE_BITS(size
);
3258 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3259 val
|= I830_FENCE_REG_VALID
;
3263 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
3264 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
3267 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
3269 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
3272 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
3273 struct drm_i915_gem_object
*obj
)
3275 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3277 /* Ensure that all CPU reads are completed before installing a fence
3278 * and all writes before removing the fence.
3280 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
3283 WARN(obj
&& (!obj
->stride
|| !obj
->tiling_mode
),
3284 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3285 obj
->stride
, obj
->tiling_mode
);
3288 i830_write_fence_reg(dev
, reg
, obj
);
3289 else if (IS_GEN3(dev
))
3290 i915_write_fence_reg(dev
, reg
, obj
);
3291 else if (INTEL_INFO(dev
)->gen
>= 4)
3292 i965_write_fence_reg(dev
, reg
, obj
);
3294 /* And similarly be paranoid that no direct access to this region
3295 * is reordered to before the fence is installed.
3297 if (i915_gem_object_needs_mb(obj
))
3301 static inline int fence_number(struct drm_i915_private
*dev_priv
,
3302 struct drm_i915_fence_reg
*fence
)
3304 return fence
- dev_priv
->fence_regs
;
3307 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
3308 struct drm_i915_fence_reg
*fence
,
3311 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3312 int reg
= fence_number(dev_priv
, fence
);
3314 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
3317 obj
->fence_reg
= reg
;
3319 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
3321 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3323 list_del_init(&fence
->lru_list
);
3325 obj
->fence_dirty
= false;
3329 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
3331 if (obj
->last_fenced_req
) {
3332 int ret
= i915_wait_request(obj
->last_fenced_req
);
3336 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
3343 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
3345 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3346 struct drm_i915_fence_reg
*fence
;
3349 ret
= i915_gem_object_wait_fence(obj
);
3353 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
3356 fence
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3358 if (WARN_ON(fence
->pin_count
))
3361 i915_gem_object_fence_lost(obj
);
3362 i915_gem_object_update_fence(obj
, fence
, false);
3367 static struct drm_i915_fence_reg
*
3368 i915_find_fence_reg(struct drm_device
*dev
)
3370 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3371 struct drm_i915_fence_reg
*reg
, *avail
;
3374 /* First try to find a free reg */
3376 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
3377 reg
= &dev_priv
->fence_regs
[i
];
3381 if (!reg
->pin_count
)
3388 /* None available, try to steal one or wait for a user to finish */
3389 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
3397 /* Wait for completion of pending flips which consume fences */
3398 if (intel_has_pending_fb_unpin(dev
))
3399 return ERR_PTR(-EAGAIN
);
3401 return ERR_PTR(-EDEADLK
);
3405 * i915_gem_object_get_fence - set up fencing for an object
3406 * @obj: object to map through a fence reg
3408 * When mapping objects through the GTT, userspace wants to be able to write
3409 * to them without having to worry about swizzling if the object is tiled.
3410 * This function walks the fence regs looking for a free one for @obj,
3411 * stealing one if it can't find any.
3413 * It then sets up the reg based on the object's properties: address, pitch
3414 * and tiling format.
3416 * For an untiled surface, this removes any existing fence.
3419 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
3421 struct drm_device
*dev
= obj
->base
.dev
;
3422 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3423 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
3424 struct drm_i915_fence_reg
*reg
;
3427 /* Have we updated the tiling parameters upon the object and so
3428 * will need to serialise the write to the associated fence register?
3430 if (obj
->fence_dirty
) {
3431 ret
= i915_gem_object_wait_fence(obj
);
3436 /* Just update our place in the LRU if our fence is getting reused. */
3437 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
3438 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3439 if (!obj
->fence_dirty
) {
3440 list_move_tail(®
->lru_list
,
3441 &dev_priv
->mm
.fence_list
);
3444 } else if (enable
) {
3445 if (WARN_ON(!obj
->map_and_fenceable
))
3448 reg
= i915_find_fence_reg(dev
);
3450 return PTR_ERR(reg
);
3453 struct drm_i915_gem_object
*old
= reg
->obj
;
3455 ret
= i915_gem_object_wait_fence(old
);
3459 i915_gem_object_fence_lost(old
);
3464 i915_gem_object_update_fence(obj
, reg
, enable
);
3469 static bool i915_gem_valid_gtt_space(struct i915_vma
*vma
,
3470 unsigned long cache_level
)
3472 struct drm_mm_node
*gtt_space
= &vma
->node
;
3473 struct drm_mm_node
*other
;
3476 * On some machines we have to be careful when putting differing types
3477 * of snoopable memory together to avoid the prefetcher crossing memory
3478 * domains and dying. During vm initialisation, we decide whether or not
3479 * these constraints apply and set the drm_mm.color_adjust
3482 if (vma
->vm
->mm
.color_adjust
== NULL
)
3485 if (!drm_mm_node_allocated(gtt_space
))
3488 if (list_empty(>t_space
->node_list
))
3491 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3492 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3495 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3496 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3503 * Finds free space in the GTT aperture and binds the object there.
3505 static struct i915_vma
*
3506 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3507 struct i915_address_space
*vm
,
3510 const struct i915_ggtt_view
*view
)
3512 struct drm_device
*dev
= obj
->base
.dev
;
3513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3514 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
3515 unsigned long start
=
3516 flags
& PIN_OFFSET_BIAS
? flags
& PIN_OFFSET_MASK
: 0;
3518 flags
& PIN_MAPPABLE
? dev_priv
->gtt
.mappable_end
: vm
->total
;
3519 struct i915_vma
*vma
;
3522 fence_size
= i915_gem_get_gtt_size(dev
,
3525 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3527 obj
->tiling_mode
, true);
3528 unfenced_alignment
=
3529 i915_gem_get_gtt_alignment(dev
,
3531 obj
->tiling_mode
, false);
3534 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3536 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3537 DRM_DEBUG("Invalid object alignment requested %u\n", alignment
);
3538 return ERR_PTR(-EINVAL
);
3541 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3543 /* If the object is bigger than the entire aperture, reject it early
3544 * before evicting everything in a vain attempt to find space.
3546 if (obj
->base
.size
> end
) {
3547 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3549 flags
& PIN_MAPPABLE
? "mappable" : "total",
3551 return ERR_PTR(-E2BIG
);
3554 ret
= i915_gem_object_get_pages(obj
);
3556 return ERR_PTR(ret
);
3558 i915_gem_object_pin_pages(obj
);
3560 vma
= i915_gem_obj_lookup_or_create_vma_view(obj
, vm
, view
);
3565 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3569 DRM_MM_SEARCH_DEFAULT
,
3570 DRM_MM_CREATE_DEFAULT
);
3572 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3581 if (WARN_ON(!i915_gem_valid_gtt_space(vma
, obj
->cache_level
))) {
3583 goto err_remove_node
;
3586 ret
= i915_gem_gtt_prepare_object(obj
);
3588 goto err_remove_node
;
3590 trace_i915_vma_bind(vma
, flags
);
3591 ret
= i915_vma_bind(vma
, obj
->cache_level
,
3592 flags
& PIN_GLOBAL
? GLOBAL_BIND
: 0);
3594 goto err_finish_gtt
;
3596 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3597 list_add_tail(&vma
->mm_list
, &vm
->inactive_list
);
3602 i915_gem_gtt_finish_object(obj
);
3604 drm_mm_remove_node(&vma
->node
);
3606 i915_gem_vma_destroy(vma
);
3609 i915_gem_object_unpin_pages(obj
);
3614 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3617 /* If we don't have a page list set up, then we're not pinned
3618 * to GPU, and we can ignore the cache flush because it'll happen
3619 * again at bind time.
3621 if (obj
->pages
== NULL
)
3625 * Stolen memory is always coherent with the GPU as it is explicitly
3626 * marked as wc by the system, or the system is cache-coherent.
3628 if (obj
->stolen
|| obj
->phys_handle
)
3631 /* If the GPU is snooping the contents of the CPU cache,
3632 * we do not need to manually clear the CPU cache lines. However,
3633 * the caches are only snooped when the render cache is
3634 * flushed/invalidated. As we always have to emit invalidations
3635 * and flushes when moving into and out of the RENDER domain, correct
3636 * snooping behaviour occurs naturally as the result of our domain
3639 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
)) {
3640 obj
->cache_dirty
= true;
3644 trace_i915_gem_object_clflush(obj
);
3645 drm_clflush_sg(obj
->pages
);
3646 obj
->cache_dirty
= false;
3651 /** Flushes the GTT write domain for the object if it's dirty. */
3653 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3655 uint32_t old_write_domain
;
3657 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3660 /* No actual flushing is required for the GTT write domain. Writes
3661 * to it immediately go to main memory as far as we know, so there's
3662 * no chipset flush. It also doesn't land in render cache.
3664 * However, we do have to enforce the order so that all writes through
3665 * the GTT land before any writes to the device, such as updates to
3670 old_write_domain
= obj
->base
.write_domain
;
3671 obj
->base
.write_domain
= 0;
3673 intel_fb_obj_flush(obj
, false);
3675 trace_i915_gem_object_change_domain(obj
,
3676 obj
->base
.read_domains
,
3680 /** Flushes the CPU write domain for the object if it's dirty. */
3682 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3684 uint32_t old_write_domain
;
3686 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3689 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
3690 i915_gem_chipset_flush(obj
->base
.dev
);
3692 old_write_domain
= obj
->base
.write_domain
;
3693 obj
->base
.write_domain
= 0;
3695 intel_fb_obj_flush(obj
, false);
3697 trace_i915_gem_object_change_domain(obj
,
3698 obj
->base
.read_domains
,
3703 * Moves a single object to the GTT read, and possibly write domain.
3705 * This function returns when the move is complete, including waiting on
3709 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3711 uint32_t old_write_domain
, old_read_domains
;
3712 struct i915_vma
*vma
;
3715 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3718 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3722 i915_gem_object_retire(obj
);
3724 /* Flush and acquire obj->pages so that we are coherent through
3725 * direct access in memory with previous cached writes through
3726 * shmemfs and that our cache domain tracking remains valid.
3727 * For example, if the obj->filp was moved to swap without us
3728 * being notified and releasing the pages, we would mistakenly
3729 * continue to assume that the obj remained out of the CPU cached
3732 ret
= i915_gem_object_get_pages(obj
);
3736 i915_gem_object_flush_cpu_write_domain(obj
);
3738 /* Serialise direct access to this object with the barriers for
3739 * coherent writes from the GPU, by effectively invalidating the
3740 * GTT domain upon first access.
3742 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3745 old_write_domain
= obj
->base
.write_domain
;
3746 old_read_domains
= obj
->base
.read_domains
;
3748 /* It should now be out of any other write domains, and we can update
3749 * the domain values for our changes.
3751 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3752 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3754 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3755 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3760 intel_fb_obj_invalidate(obj
, NULL
);
3762 trace_i915_gem_object_change_domain(obj
,
3766 /* And bump the LRU for this access */
3767 vma
= i915_gem_obj_to_ggtt(obj
);
3768 if (vma
&& drm_mm_node_allocated(&vma
->node
) && !obj
->active
)
3769 list_move_tail(&vma
->mm_list
,
3770 &to_i915(obj
->base
.dev
)->gtt
.base
.inactive_list
);
3775 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3776 enum i915_cache_level cache_level
)
3778 struct drm_device
*dev
= obj
->base
.dev
;
3779 struct i915_vma
*vma
, *next
;
3782 if (obj
->cache_level
== cache_level
)
3785 if (i915_gem_obj_is_pinned(obj
)) {
3786 DRM_DEBUG("can not change the cache level of pinned objects\n");
3790 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
3791 if (!i915_gem_valid_gtt_space(vma
, cache_level
)) {
3792 ret
= i915_vma_unbind(vma
);
3798 if (i915_gem_obj_bound_any(obj
)) {
3799 ret
= i915_gem_object_finish_gpu(obj
);
3803 i915_gem_object_finish_gtt(obj
);
3805 /* Before SandyBridge, you could not use tiling or fence
3806 * registers with snooped memory, so relinquish any fences
3807 * currently pointing to our region in the aperture.
3809 if (INTEL_INFO(dev
)->gen
< 6) {
3810 ret
= i915_gem_object_put_fence(obj
);
3815 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3816 if (drm_mm_node_allocated(&vma
->node
)) {
3817 ret
= i915_vma_bind(vma
, cache_level
,
3818 vma
->bound
& GLOBAL_BIND
);
3824 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3825 vma
->node
.color
= cache_level
;
3826 obj
->cache_level
= cache_level
;
3828 if (obj
->cache_dirty
&&
3829 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
3830 cpu_write_needs_clflush(obj
)) {
3831 if (i915_gem_clflush_object(obj
, true))
3832 i915_gem_chipset_flush(obj
->base
.dev
);
3838 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3839 struct drm_file
*file
)
3841 struct drm_i915_gem_caching
*args
= data
;
3842 struct drm_i915_gem_object
*obj
;
3845 ret
= i915_mutex_lock_interruptible(dev
);
3849 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3850 if (&obj
->base
== NULL
) {
3855 switch (obj
->cache_level
) {
3856 case I915_CACHE_LLC
:
3857 case I915_CACHE_L3_LLC
:
3858 args
->caching
= I915_CACHING_CACHED
;
3862 args
->caching
= I915_CACHING_DISPLAY
;
3866 args
->caching
= I915_CACHING_NONE
;
3870 drm_gem_object_unreference(&obj
->base
);
3872 mutex_unlock(&dev
->struct_mutex
);
3876 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3877 struct drm_file
*file
)
3879 struct drm_i915_gem_caching
*args
= data
;
3880 struct drm_i915_gem_object
*obj
;
3881 enum i915_cache_level level
;
3884 switch (args
->caching
) {
3885 case I915_CACHING_NONE
:
3886 level
= I915_CACHE_NONE
;
3888 case I915_CACHING_CACHED
:
3889 level
= I915_CACHE_LLC
;
3891 case I915_CACHING_DISPLAY
:
3892 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
3898 ret
= i915_mutex_lock_interruptible(dev
);
3902 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3903 if (&obj
->base
== NULL
) {
3908 ret
= i915_gem_object_set_cache_level(obj
, level
);
3910 drm_gem_object_unreference(&obj
->base
);
3912 mutex_unlock(&dev
->struct_mutex
);
3916 static bool is_pin_display(struct drm_i915_gem_object
*obj
)
3918 struct i915_vma
*vma
;
3920 vma
= i915_gem_obj_to_ggtt(obj
);
3924 /* There are 2 sources that pin objects:
3925 * 1. The display engine (scanouts, sprites, cursors);
3926 * 2. Reservations for execbuffer;
3928 * We can ignore reservations as we hold the struct_mutex and
3929 * are only called outside of the reservation path.
3931 return vma
->pin_count
;
3935 * Prepare buffer for display plane (scanout, cursors, etc).
3936 * Can be called from an uninterruptible phase (modesetting) and allows
3937 * any flushes to be pipelined (for pageflips).
3940 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3942 struct intel_engine_cs
*pipelined
)
3944 u32 old_read_domains
, old_write_domain
;
3945 bool was_pin_display
;
3948 if (pipelined
!= i915_gem_request_get_ring(obj
->last_read_req
)) {
3949 ret
= i915_gem_object_sync(obj
, pipelined
);
3954 /* Mark the pin_display early so that we account for the
3955 * display coherency whilst setting up the cache domains.
3957 was_pin_display
= obj
->pin_display
;
3958 obj
->pin_display
= true;
3960 /* The display engine is not coherent with the LLC cache on gen6. As
3961 * a result, we make sure that the pinning that is about to occur is
3962 * done with uncached PTEs. This is lowest common denominator for all
3965 * However for gen6+, we could do better by using the GFDT bit instead
3966 * of uncaching, which would allow us to flush all the LLC-cached data
3967 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3969 ret
= i915_gem_object_set_cache_level(obj
,
3970 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
3972 goto err_unpin_display
;
3974 /* As the user may map the buffer once pinned in the display plane
3975 * (e.g. libkms for the bootup splash), we have to ensure that we
3976 * always use map_and_fenceable for all scanout buffers.
3978 ret
= i915_gem_obj_ggtt_pin(obj
, alignment
, PIN_MAPPABLE
);
3980 goto err_unpin_display
;
3982 i915_gem_object_flush_cpu_write_domain(obj
);
3984 old_write_domain
= obj
->base
.write_domain
;
3985 old_read_domains
= obj
->base
.read_domains
;
3987 /* It should now be out of any other write domains, and we can update
3988 * the domain values for our changes.
3990 obj
->base
.write_domain
= 0;
3991 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3993 trace_i915_gem_object_change_domain(obj
,
4000 WARN_ON(was_pin_display
!= is_pin_display(obj
));
4001 obj
->pin_display
= was_pin_display
;
4006 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
)
4008 i915_gem_object_ggtt_unpin(obj
);
4009 obj
->pin_display
= is_pin_display(obj
);
4013 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
4017 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
4020 ret
= i915_gem_object_wait_rendering(obj
, false);
4024 /* Ensure that we invalidate the GPU's caches and TLBs. */
4025 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
4030 * Moves a single object to the CPU read, and possibly write domain.
4032 * This function returns when the move is complete, including waiting on
4036 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
4038 uint32_t old_write_domain
, old_read_domains
;
4041 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
4044 ret
= i915_gem_object_wait_rendering(obj
, !write
);
4048 i915_gem_object_retire(obj
);
4049 i915_gem_object_flush_gtt_write_domain(obj
);
4051 old_write_domain
= obj
->base
.write_domain
;
4052 old_read_domains
= obj
->base
.read_domains
;
4054 /* Flush the CPU cache if it's still invalid. */
4055 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
4056 i915_gem_clflush_object(obj
, false);
4058 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
4061 /* It should now be out of any other write domains, and we can update
4062 * the domain values for our changes.
4064 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
4066 /* If we're writing through the CPU, then the GPU read domains will
4067 * need to be invalidated at next use.
4070 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4071 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4075 intel_fb_obj_invalidate(obj
, NULL
);
4077 trace_i915_gem_object_change_domain(obj
,
4084 /* Throttle our rendering by waiting until the ring has completed our requests
4085 * emitted over 20 msec ago.
4087 * Note that if we were to use the current jiffies each time around the loop,
4088 * we wouldn't escape the function with any frames outstanding if the time to
4089 * render a frame was over 20ms.
4091 * This should get us reasonable parallelism between CPU and GPU but also
4092 * relatively low latency when blocking on a particular request to finish.
4095 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
4097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4098 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4099 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
4100 struct drm_i915_gem_request
*request
, *target
= NULL
;
4101 unsigned reset_counter
;
4104 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
4108 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
4112 spin_lock(&file_priv
->mm
.lock
);
4113 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
4114 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
4119 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
4121 i915_gem_request_reference(target
);
4122 spin_unlock(&file_priv
->mm
.lock
);
4127 ret
= __i915_wait_request(target
, reset_counter
, true, NULL
, NULL
);
4129 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
4131 mutex_lock(&dev
->struct_mutex
);
4132 i915_gem_request_unreference(target
);
4133 mutex_unlock(&dev
->struct_mutex
);
4139 i915_vma_misplaced(struct i915_vma
*vma
, uint32_t alignment
, uint64_t flags
)
4141 struct drm_i915_gem_object
*obj
= vma
->obj
;
4144 vma
->node
.start
& (alignment
- 1))
4147 if (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)
4150 if (flags
& PIN_OFFSET_BIAS
&&
4151 vma
->node
.start
< (flags
& PIN_OFFSET_MASK
))
4158 i915_gem_object_pin_view(struct drm_i915_gem_object
*obj
,
4159 struct i915_address_space
*vm
,
4162 const struct i915_ggtt_view
*view
)
4164 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4165 struct i915_vma
*vma
;
4169 if (WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
))
4172 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
4175 if (WARN_ON((flags
& (PIN_MAPPABLE
| PIN_GLOBAL
)) == PIN_MAPPABLE
))
4178 vma
= i915_gem_obj_to_vma_view(obj
, vm
, view
);
4180 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
4183 if (i915_vma_misplaced(vma
, alignment
, flags
)) {
4184 WARN(vma
->pin_count
,
4185 "bo is already pinned with incorrect alignment:"
4186 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4187 " obj->map_and_fenceable=%d\n",
4188 i915_gem_obj_offset_view(obj
, vm
, view
->type
),
4190 !!(flags
& PIN_MAPPABLE
),
4191 obj
->map_and_fenceable
);
4192 ret
= i915_vma_unbind(vma
);
4200 bound
= vma
? vma
->bound
: 0;
4201 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
4202 vma
= i915_gem_object_bind_to_vm(obj
, vm
, alignment
,
4205 return PTR_ERR(vma
);
4208 if (flags
& PIN_GLOBAL
&& !(vma
->bound
& GLOBAL_BIND
)) {
4209 ret
= i915_vma_bind(vma
, obj
->cache_level
, GLOBAL_BIND
);
4214 if ((bound
^ vma
->bound
) & GLOBAL_BIND
) {
4215 bool mappable
, fenceable
;
4216 u32 fence_size
, fence_alignment
;
4218 fence_size
= i915_gem_get_gtt_size(obj
->base
.dev
,
4221 fence_alignment
= i915_gem_get_gtt_alignment(obj
->base
.dev
,
4226 fenceable
= (vma
->node
.size
== fence_size
&&
4227 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
4229 mappable
= (vma
->node
.start
+ obj
->base
.size
<=
4230 dev_priv
->gtt
.mappable_end
);
4232 obj
->map_and_fenceable
= mappable
&& fenceable
;
4235 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
4238 if (flags
& PIN_MAPPABLE
)
4239 obj
->pin_mappable
|= true;
4245 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
)
4247 struct i915_vma
*vma
= i915_gem_obj_to_ggtt(obj
);
4250 BUG_ON(vma
->pin_count
== 0);
4251 BUG_ON(!i915_gem_obj_ggtt_bound(obj
));
4253 if (--vma
->pin_count
== 0)
4254 obj
->pin_mappable
= false;
4258 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
4260 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4261 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4262 struct i915_vma
*ggtt_vma
= i915_gem_obj_to_ggtt(obj
);
4264 WARN_ON(!ggtt_vma
||
4265 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
>
4266 ggtt_vma
->pin_count
);
4267 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
4274 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
4276 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4277 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4278 WARN_ON(dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
<= 0);
4279 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
4284 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4285 struct drm_file
*file
)
4287 struct drm_i915_gem_busy
*args
= data
;
4288 struct drm_i915_gem_object
*obj
;
4291 ret
= i915_mutex_lock_interruptible(dev
);
4295 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4296 if (&obj
->base
== NULL
) {
4301 /* Count all active objects as busy, even if they are currently not used
4302 * by the gpu. Users of this interface expect objects to eventually
4303 * become non-busy without any further actions, therefore emit any
4304 * necessary flushes here.
4306 ret
= i915_gem_object_flush_active(obj
);
4308 args
->busy
= obj
->active
;
4309 if (obj
->last_read_req
) {
4310 struct intel_engine_cs
*ring
;
4311 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
4312 ring
= i915_gem_request_get_ring(obj
->last_read_req
);
4313 args
->busy
|= intel_ring_flag(ring
) << 16;
4316 drm_gem_object_unreference(&obj
->base
);
4318 mutex_unlock(&dev
->struct_mutex
);
4323 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4324 struct drm_file
*file_priv
)
4326 return i915_gem_ring_throttle(dev
, file_priv
);
4330 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4331 struct drm_file
*file_priv
)
4333 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4334 struct drm_i915_gem_madvise
*args
= data
;
4335 struct drm_i915_gem_object
*obj
;
4338 switch (args
->madv
) {
4339 case I915_MADV_DONTNEED
:
4340 case I915_MADV_WILLNEED
:
4346 ret
= i915_mutex_lock_interruptible(dev
);
4350 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
4351 if (&obj
->base
== NULL
) {
4356 if (i915_gem_obj_is_pinned(obj
)) {
4362 obj
->tiling_mode
!= I915_TILING_NONE
&&
4363 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
4364 if (obj
->madv
== I915_MADV_WILLNEED
)
4365 i915_gem_object_unpin_pages(obj
);
4366 if (args
->madv
== I915_MADV_WILLNEED
)
4367 i915_gem_object_pin_pages(obj
);
4370 if (obj
->madv
!= __I915_MADV_PURGED
)
4371 obj
->madv
= args
->madv
;
4373 /* if the object is no longer attached, discard its backing storage */
4374 if (i915_gem_object_is_purgeable(obj
) && obj
->pages
== NULL
)
4375 i915_gem_object_truncate(obj
);
4377 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4380 drm_gem_object_unreference(&obj
->base
);
4382 mutex_unlock(&dev
->struct_mutex
);
4386 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4387 const struct drm_i915_gem_object_ops
*ops
)
4389 INIT_LIST_HEAD(&obj
->global_list
);
4390 INIT_LIST_HEAD(&obj
->ring_list
);
4391 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4392 INIT_LIST_HEAD(&obj
->vma_list
);
4393 INIT_LIST_HEAD(&obj
->batch_pool_list
);
4397 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4398 obj
->madv
= I915_MADV_WILLNEED
;
4400 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4403 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4404 .get_pages
= i915_gem_object_get_pages_gtt
,
4405 .put_pages
= i915_gem_object_put_pages_gtt
,
4408 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
4411 struct drm_i915_gem_object
*obj
;
4412 struct address_space
*mapping
;
4415 obj
= i915_gem_object_alloc(dev
);
4419 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4420 i915_gem_object_free(obj
);
4424 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4425 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4426 /* 965gm cannot relocate objects above 4GiB. */
4427 mask
&= ~__GFP_HIGHMEM
;
4428 mask
|= __GFP_DMA32
;
4431 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4432 mapping_set_gfp_mask(mapping
, mask
);
4434 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4436 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4437 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4440 /* On some devices, we can have the GPU use the LLC (the CPU
4441 * cache) for about a 10% performance improvement
4442 * compared to uncached. Graphics requests other than
4443 * display scanout are coherent with the CPU in
4444 * accessing this cache. This means in this mode we
4445 * don't need to clflush on the CPU side, and on the
4446 * GPU side we only need to flush internal caches to
4447 * get data visible to the CPU.
4449 * However, we maintain the display planes as UC, and so
4450 * need to rebind when first used as such.
4452 obj
->cache_level
= I915_CACHE_LLC
;
4454 obj
->cache_level
= I915_CACHE_NONE
;
4456 trace_i915_gem_object_create(obj
);
4461 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4463 /* If we are the last user of the backing storage (be it shmemfs
4464 * pages or stolen etc), we know that the pages are going to be
4465 * immediately released. In this case, we can then skip copying
4466 * back the contents from the GPU.
4469 if (obj
->madv
!= I915_MADV_WILLNEED
)
4472 if (obj
->base
.filp
== NULL
)
4475 /* At first glance, this looks racy, but then again so would be
4476 * userspace racing mmap against close. However, the first external
4477 * reference to the filp can only be obtained through the
4478 * i915_gem_mmap_ioctl() which safeguards us against the user
4479 * acquiring such a reference whilst we are in the middle of
4480 * freeing the object.
4482 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4485 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4487 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4488 struct drm_device
*dev
= obj
->base
.dev
;
4489 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4490 struct i915_vma
*vma
, *next
;
4492 intel_runtime_pm_get(dev_priv
);
4494 trace_i915_gem_object_destroy(obj
);
4496 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4500 ret
= i915_vma_unbind(vma
);
4501 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4502 bool was_interruptible
;
4504 was_interruptible
= dev_priv
->mm
.interruptible
;
4505 dev_priv
->mm
.interruptible
= false;
4507 WARN_ON(i915_vma_unbind(vma
));
4509 dev_priv
->mm
.interruptible
= was_interruptible
;
4513 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4514 * before progressing. */
4516 i915_gem_object_unpin_pages(obj
);
4518 WARN_ON(obj
->frontbuffer_bits
);
4520 if (obj
->pages
&& obj
->madv
== I915_MADV_WILLNEED
&&
4521 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
&&
4522 obj
->tiling_mode
!= I915_TILING_NONE
)
4523 i915_gem_object_unpin_pages(obj
);
4525 if (WARN_ON(obj
->pages_pin_count
))
4526 obj
->pages_pin_count
= 0;
4527 if (discard_backing_storage(obj
))
4528 obj
->madv
= I915_MADV_DONTNEED
;
4529 i915_gem_object_put_pages(obj
);
4530 i915_gem_object_free_mmap_offset(obj
);
4534 if (obj
->base
.import_attach
)
4535 drm_prime_gem_destroy(&obj
->base
, NULL
);
4537 if (obj
->ops
->release
)
4538 obj
->ops
->release(obj
);
4540 drm_gem_object_release(&obj
->base
);
4541 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4544 i915_gem_object_free(obj
);
4546 intel_runtime_pm_put(dev_priv
);
4549 struct i915_vma
*i915_gem_obj_to_vma_view(struct drm_i915_gem_object
*obj
,
4550 struct i915_address_space
*vm
,
4551 const struct i915_ggtt_view
*view
)
4553 struct i915_vma
*vma
;
4554 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4555 if (vma
->vm
== vm
&& vma
->ggtt_view
.type
== view
->type
)
4561 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4563 struct i915_address_space
*vm
= NULL
;
4564 WARN_ON(vma
->node
.allocated
);
4566 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4567 if (!list_empty(&vma
->exec_list
))
4572 if (!i915_is_ggtt(vm
))
4573 i915_ppgtt_put(i915_vm_to_ppgtt(vm
));
4575 list_del(&vma
->vma_link
);
4581 i915_gem_stop_ringbuffers(struct drm_device
*dev
)
4583 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4584 struct intel_engine_cs
*ring
;
4587 for_each_ring(ring
, dev_priv
, i
)
4588 dev_priv
->gt
.stop_ring(ring
);
4592 i915_gem_suspend(struct drm_device
*dev
)
4594 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4597 mutex_lock(&dev
->struct_mutex
);
4598 ret
= i915_gpu_idle(dev
);
4602 i915_gem_retire_requests(dev
);
4604 /* Under UMS, be paranoid and evict. */
4605 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4606 i915_gem_evict_everything(dev
);
4608 i915_gem_stop_ringbuffers(dev
);
4609 mutex_unlock(&dev
->struct_mutex
);
4611 del_timer_sync(&dev_priv
->gpu_error
.hangcheck_timer
);
4612 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4613 flush_delayed_work(&dev_priv
->mm
.idle_work
);
4615 /* Assert that we sucessfully flushed all the work and
4616 * reset the GPU back to its idle, low power state.
4618 WARN_ON(dev_priv
->mm
.busy
);
4623 mutex_unlock(&dev
->struct_mutex
);
4627 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
)
4629 struct drm_device
*dev
= ring
->dev
;
4630 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4631 u32 reg_base
= GEN7_L3LOG_BASE
+ (slice
* 0x200);
4632 u32
*remap_info
= dev_priv
->l3_parity
.remap_info
[slice
];
4635 if (!HAS_L3_DPF(dev
) || !remap_info
)
4638 ret
= intel_ring_begin(ring
, GEN7_L3LOG_SIZE
/ 4 * 3);
4643 * Note: We do not worry about the concurrent register cacheline hang
4644 * here because no other code should access these registers other than
4645 * at initialization time.
4647 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
4648 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
4649 intel_ring_emit(ring
, reg_base
+ i
);
4650 intel_ring_emit(ring
, remap_info
[i
/4]);
4653 intel_ring_advance(ring
);
4658 void i915_gem_init_swizzling(struct drm_device
*dev
)
4660 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4662 if (INTEL_INFO(dev
)->gen
< 5 ||
4663 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4666 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4667 DISP_TILE_SURFACE_SWIZZLING
);
4672 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4674 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4675 else if (IS_GEN7(dev
))
4676 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4677 else if (IS_GEN8(dev
))
4678 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4684 intel_enable_blt(struct drm_device
*dev
)
4689 /* The blitter was dysfunctional on early prototypes */
4690 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
4691 DRM_INFO("BLT not supported on this pre-production hardware;"
4692 " graphics performance will be degraded.\n");
4699 static void init_unused_ring(struct drm_device
*dev
, u32 base
)
4701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4703 I915_WRITE(RING_CTL(base
), 0);
4704 I915_WRITE(RING_HEAD(base
), 0);
4705 I915_WRITE(RING_TAIL(base
), 0);
4706 I915_WRITE(RING_START(base
), 0);
4709 static void init_unused_rings(struct drm_device
*dev
)
4712 init_unused_ring(dev
, PRB1_BASE
);
4713 init_unused_ring(dev
, SRB0_BASE
);
4714 init_unused_ring(dev
, SRB1_BASE
);
4715 init_unused_ring(dev
, SRB2_BASE
);
4716 init_unused_ring(dev
, SRB3_BASE
);
4717 } else if (IS_GEN2(dev
)) {
4718 init_unused_ring(dev
, SRB0_BASE
);
4719 init_unused_ring(dev
, SRB1_BASE
);
4720 } else if (IS_GEN3(dev
)) {
4721 init_unused_ring(dev
, PRB1_BASE
);
4722 init_unused_ring(dev
, PRB2_BASE
);
4726 int i915_gem_init_rings(struct drm_device
*dev
)
4728 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4731 ret
= intel_init_render_ring_buffer(dev
);
4736 ret
= intel_init_bsd_ring_buffer(dev
);
4738 goto cleanup_render_ring
;
4741 if (intel_enable_blt(dev
)) {
4742 ret
= intel_init_blt_ring_buffer(dev
);
4744 goto cleanup_bsd_ring
;
4747 if (HAS_VEBOX(dev
)) {
4748 ret
= intel_init_vebox_ring_buffer(dev
);
4750 goto cleanup_blt_ring
;
4753 if (HAS_BSD2(dev
)) {
4754 ret
= intel_init_bsd2_ring_buffer(dev
);
4756 goto cleanup_vebox_ring
;
4759 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
4761 goto cleanup_bsd2_ring
;
4766 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS2
]);
4768 intel_cleanup_ring_buffer(&dev_priv
->ring
[VECS
]);
4770 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
4772 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
4773 cleanup_render_ring
:
4774 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
4780 i915_gem_init_hw(struct drm_device
*dev
)
4782 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4783 struct intel_engine_cs
*ring
;
4786 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
4789 if (dev_priv
->ellc_size
)
4790 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4792 if (IS_HASWELL(dev
))
4793 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
4794 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
4796 if (HAS_PCH_NOP(dev
)) {
4797 if (IS_IVYBRIDGE(dev
)) {
4798 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4799 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4800 I915_WRITE(GEN7_MSG_CTL
, temp
);
4801 } else if (INTEL_INFO(dev
)->gen
>= 7) {
4802 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
4803 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
4804 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
4808 i915_gem_init_swizzling(dev
);
4811 * At least 830 can leave some of the unused rings
4812 * "active" (ie. head != tail) after resume which
4813 * will prevent c3 entry. Makes sure all unused rings
4816 init_unused_rings(dev
);
4818 for_each_ring(ring
, dev_priv
, i
) {
4819 ret
= ring
->init_hw(ring
);
4824 for (i
= 0; i
< NUM_L3_SLICES(dev
); i
++)
4825 i915_gem_l3_remap(&dev_priv
->ring
[RCS
], i
);
4828 * XXX: Contexts should only be initialized once. Doing a switch to the
4829 * default context switch however is something we'd like to do after
4830 * reset or thaw (the latter may not actually be necessary for HW, but
4831 * goes with our code better). Context switching requires rings (for
4832 * the do_switch), but before enabling PPGTT. So don't move this.
4834 ret
= i915_gem_context_enable(dev_priv
);
4835 if (ret
&& ret
!= -EIO
) {
4836 DRM_ERROR("Context enable failed %d\n", ret
);
4837 i915_gem_cleanup_ringbuffer(dev
);
4842 ret
= i915_ppgtt_init_hw(dev
);
4843 if (ret
&& ret
!= -EIO
) {
4844 DRM_ERROR("PPGTT enable failed %d\n", ret
);
4845 i915_gem_cleanup_ringbuffer(dev
);
4851 int i915_gem_init(struct drm_device
*dev
)
4853 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4856 i915
.enable_execlists
= intel_sanitize_enable_execlists(dev
,
4857 i915
.enable_execlists
);
4859 mutex_lock(&dev
->struct_mutex
);
4861 if (IS_VALLEYVIEW(dev
)) {
4862 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4863 I915_WRITE(VLV_GTLC_WAKE_CTRL
, VLV_GTLC_ALLOWWAKEREQ
);
4864 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS
) &
4865 VLV_GTLC_ALLOWWAKEACK
), 10))
4866 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4869 if (!i915
.enable_execlists
) {
4870 dev_priv
->gt
.do_execbuf
= i915_gem_ringbuffer_submission
;
4871 dev_priv
->gt
.init_rings
= i915_gem_init_rings
;
4872 dev_priv
->gt
.cleanup_ring
= intel_cleanup_ring_buffer
;
4873 dev_priv
->gt
.stop_ring
= intel_stop_ring_buffer
;
4875 dev_priv
->gt
.do_execbuf
= intel_execlists_submission
;
4876 dev_priv
->gt
.init_rings
= intel_logical_rings_init
;
4877 dev_priv
->gt
.cleanup_ring
= intel_logical_ring_cleanup
;
4878 dev_priv
->gt
.stop_ring
= intel_logical_ring_stop
;
4881 ret
= i915_gem_init_userptr(dev
);
4885 i915_gem_init_global_gtt(dev
);
4887 ret
= i915_gem_context_init(dev
);
4891 ret
= dev_priv
->gt
.init_rings(dev
);
4895 ret
= i915_gem_init_hw(dev
);
4897 /* Allow ring initialisation to fail by marking the GPU as
4898 * wedged. But we only want to do this where the GPU is angry,
4899 * for all other failure, such as an allocation failure, bail.
4901 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4902 atomic_set_mask(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
4907 mutex_unlock(&dev
->struct_mutex
);
4913 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4915 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4916 struct intel_engine_cs
*ring
;
4919 for_each_ring(ring
, dev_priv
, i
)
4920 dev_priv
->gt
.cleanup_ring(ring
);
4924 init_ring_lists(struct intel_engine_cs
*ring
)
4926 INIT_LIST_HEAD(&ring
->active_list
);
4927 INIT_LIST_HEAD(&ring
->request_list
);
4930 void i915_init_vm(struct drm_i915_private
*dev_priv
,
4931 struct i915_address_space
*vm
)
4933 if (!i915_is_ggtt(vm
))
4934 drm_mm_init(&vm
->mm
, vm
->start
, vm
->total
);
4935 vm
->dev
= dev_priv
->dev
;
4936 INIT_LIST_HEAD(&vm
->active_list
);
4937 INIT_LIST_HEAD(&vm
->inactive_list
);
4938 INIT_LIST_HEAD(&vm
->global_link
);
4939 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
4943 i915_gem_load(struct drm_device
*dev
)
4945 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4949 kmem_cache_create("i915_gem_object",
4950 sizeof(struct drm_i915_gem_object
), 0,
4954 INIT_LIST_HEAD(&dev_priv
->vm_list
);
4955 i915_init_vm(dev_priv
, &dev_priv
->gtt
.base
);
4957 INIT_LIST_HEAD(&dev_priv
->context_list
);
4958 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4959 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4960 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4961 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4962 init_ring_lists(&dev_priv
->ring
[i
]);
4963 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
4964 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4965 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4966 i915_gem_retire_work_handler
);
4967 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
4968 i915_gem_idle_work_handler
);
4969 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
4971 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4972 if (!drm_core_check_feature(dev
, DRIVER_MODESET
) && IS_GEN3(dev
)) {
4973 I915_WRITE(MI_ARB_STATE
,
4974 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
4977 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4979 /* Old X drivers will take 0-2 for front, back, depth buffers */
4980 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4981 dev_priv
->fence_reg_start
= 3;
4983 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
))
4984 dev_priv
->num_fence_regs
= 32;
4985 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4986 dev_priv
->num_fence_regs
= 16;
4988 dev_priv
->num_fence_regs
= 8;
4990 /* Initialize fence registers to zero */
4991 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4992 i915_gem_restore_fences(dev
);
4994 i915_gem_detect_bit_6_swizzle(dev
);
4995 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4997 dev_priv
->mm
.interruptible
= true;
4999 dev_priv
->mm
.shrinker
.scan_objects
= i915_gem_shrinker_scan
;
5000 dev_priv
->mm
.shrinker
.count_objects
= i915_gem_shrinker_count
;
5001 dev_priv
->mm
.shrinker
.seeks
= DEFAULT_SEEKS
;
5002 register_shrinker(&dev_priv
->mm
.shrinker
);
5004 dev_priv
->mm
.oom_notifier
.notifier_call
= i915_gem_shrinker_oom
;
5005 register_oom_notifier(&dev_priv
->mm
.oom_notifier
);
5007 i915_gem_batch_pool_init(dev
, &dev_priv
->mm
.batch_pool
);
5009 mutex_init(&dev_priv
->fb_tracking
.lock
);
5012 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5014 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5016 cancel_delayed_work_sync(&file_priv
->mm
.idle_work
);
5018 /* Clean up our request list when the client is going away, so that
5019 * later retire_requests won't dereference our soon-to-be-gone
5022 spin_lock(&file_priv
->mm
.lock
);
5023 while (!list_empty(&file_priv
->mm
.request_list
)) {
5024 struct drm_i915_gem_request
*request
;
5026 request
= list_first_entry(&file_priv
->mm
.request_list
,
5027 struct drm_i915_gem_request
,
5029 list_del(&request
->client_list
);
5030 request
->file_priv
= NULL
;
5032 spin_unlock(&file_priv
->mm
.lock
);
5036 i915_gem_file_idle_work_handler(struct work_struct
*work
)
5038 struct drm_i915_file_private
*file_priv
=
5039 container_of(work
, typeof(*file_priv
), mm
.idle_work
.work
);
5041 atomic_set(&file_priv
->rps_wait_boost
, false);
5044 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
5046 struct drm_i915_file_private
*file_priv
;
5049 DRM_DEBUG_DRIVER("\n");
5051 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
5055 file
->driver_priv
= file_priv
;
5056 file_priv
->dev_priv
= dev
->dev_private
;
5057 file_priv
->file
= file
;
5059 spin_lock_init(&file_priv
->mm
.lock
);
5060 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
5061 INIT_DELAYED_WORK(&file_priv
->mm
.idle_work
,
5062 i915_gem_file_idle_work_handler
);
5064 ret
= i915_gem_context_open(dev
, file
);
5072 * i915_gem_track_fb - update frontbuffer tracking
5073 * old: current GEM buffer for the frontbuffer slots
5074 * new: new GEM buffer for the frontbuffer slots
5075 * frontbuffer_bits: bitmask of frontbuffer slots
5077 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5078 * from @old and setting them in @new. Both @old and @new can be NULL.
5080 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
5081 struct drm_i915_gem_object
*new,
5082 unsigned frontbuffer_bits
)
5085 WARN_ON(!mutex_is_locked(&old
->base
.dev
->struct_mutex
));
5086 WARN_ON(!(old
->frontbuffer_bits
& frontbuffer_bits
));
5087 old
->frontbuffer_bits
&= ~frontbuffer_bits
;
5091 WARN_ON(!mutex_is_locked(&new->base
.dev
->struct_mutex
));
5092 WARN_ON(new->frontbuffer_bits
& frontbuffer_bits
);
5093 new->frontbuffer_bits
|= frontbuffer_bits
;
5097 static bool mutex_is_locked_by(struct mutex
*mutex
, struct task_struct
*task
)
5099 if (!mutex_is_locked(mutex
))
5102 #if defined(CONFIG_SMP) && !defined(CONFIG_DEBUG_MUTEXES)
5103 return mutex
->owner
== task
;
5105 /* Since UP may be pre-empted, we cannot assume that we own the lock */
5110 static bool i915_gem_shrinker_lock(struct drm_device
*dev
, bool *unlock
)
5112 if (!mutex_trylock(&dev
->struct_mutex
)) {
5113 if (!mutex_is_locked_by(&dev
->struct_mutex
, current
))
5116 if (to_i915(dev
)->mm
.shrinker_no_lock_stealing
)
5126 static int num_vma_bound(struct drm_i915_gem_object
*obj
)
5128 struct i915_vma
*vma
;
5131 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
5132 if (drm_mm_node_allocated(&vma
->node
))
5138 static unsigned long
5139 i915_gem_shrinker_count(struct shrinker
*shrinker
, struct shrink_control
*sc
)
5141 struct drm_i915_private
*dev_priv
=
5142 container_of(shrinker
, struct drm_i915_private
, mm
.shrinker
);
5143 struct drm_device
*dev
= dev_priv
->dev
;
5144 struct drm_i915_gem_object
*obj
;
5145 unsigned long count
;
5148 if (!i915_gem_shrinker_lock(dev
, &unlock
))
5152 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
)
5153 if (obj
->pages_pin_count
== 0)
5154 count
+= obj
->base
.size
>> PAGE_SHIFT
;
5156 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
5157 if (!i915_gem_obj_is_pinned(obj
) &&
5158 obj
->pages_pin_count
== num_vma_bound(obj
))
5159 count
+= obj
->base
.size
>> PAGE_SHIFT
;
5163 mutex_unlock(&dev
->struct_mutex
);
5168 /* All the new VM stuff */
5169 unsigned long i915_gem_obj_offset_view(struct drm_i915_gem_object
*o
,
5170 struct i915_address_space
*vm
,
5171 enum i915_ggtt_view_type view
)
5173 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5174 struct i915_vma
*vma
;
5176 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5178 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5179 if (vma
->vm
== vm
&& vma
->ggtt_view
.type
== view
)
5180 return vma
->node
.start
;
5183 WARN(1, "%s vma for this object not found.\n",
5184 i915_is_ggtt(vm
) ? "global" : "ppgtt");
5188 bool i915_gem_obj_bound_view(struct drm_i915_gem_object
*o
,
5189 struct i915_address_space
*vm
,
5190 enum i915_ggtt_view_type view
)
5192 struct i915_vma
*vma
;
5194 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5195 if (vma
->vm
== vm
&&
5196 vma
->ggtt_view
.type
== view
&&
5197 drm_mm_node_allocated(&vma
->node
))
5203 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
5205 struct i915_vma
*vma
;
5207 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5208 if (drm_mm_node_allocated(&vma
->node
))
5214 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
5215 struct i915_address_space
*vm
)
5217 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5218 struct i915_vma
*vma
;
5220 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5222 BUG_ON(list_empty(&o
->vma_list
));
5224 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5226 return vma
->node
.size
;
5231 static unsigned long
5232 i915_gem_shrinker_scan(struct shrinker
*shrinker
, struct shrink_control
*sc
)
5234 struct drm_i915_private
*dev_priv
=
5235 container_of(shrinker
, struct drm_i915_private
, mm
.shrinker
);
5236 struct drm_device
*dev
= dev_priv
->dev
;
5237 unsigned long freed
;
5240 if (!i915_gem_shrinker_lock(dev
, &unlock
))
5243 freed
= i915_gem_shrink(dev_priv
,
5246 I915_SHRINK_UNBOUND
|
5247 I915_SHRINK_PURGEABLE
);
5248 if (freed
< sc
->nr_to_scan
)
5249 freed
+= i915_gem_shrink(dev_priv
,
5250 sc
->nr_to_scan
- freed
,
5252 I915_SHRINK_UNBOUND
);
5254 mutex_unlock(&dev
->struct_mutex
);
5260 i915_gem_shrinker_oom(struct notifier_block
*nb
, unsigned long event
, void *ptr
)
5262 struct drm_i915_private
*dev_priv
=
5263 container_of(nb
, struct drm_i915_private
, mm
.oom_notifier
);
5264 struct drm_device
*dev
= dev_priv
->dev
;
5265 struct drm_i915_gem_object
*obj
;
5266 unsigned long timeout
= msecs_to_jiffies(5000) + 1;
5267 unsigned long pinned
, bound
, unbound
, freed_pages
;
5268 bool was_interruptible
;
5271 while (!i915_gem_shrinker_lock(dev
, &unlock
) && --timeout
) {
5272 schedule_timeout_killable(1);
5273 if (fatal_signal_pending(current
))
5277 pr_err("Unable to purge GPU memory due lock contention.\n");
5281 was_interruptible
= dev_priv
->mm
.interruptible
;
5282 dev_priv
->mm
.interruptible
= false;
5284 freed_pages
= i915_gem_shrink_all(dev_priv
);
5286 dev_priv
->mm
.interruptible
= was_interruptible
;
5288 /* Because we may be allocating inside our own driver, we cannot
5289 * assert that there are no objects with pinned pages that are not
5290 * being pointed to by hardware.
5292 unbound
= bound
= pinned
= 0;
5293 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
5294 if (!obj
->base
.filp
) /* not backed by a freeable object */
5297 if (obj
->pages_pin_count
)
5298 pinned
+= obj
->base
.size
;
5300 unbound
+= obj
->base
.size
;
5302 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
5303 if (!obj
->base
.filp
)
5306 if (obj
->pages_pin_count
)
5307 pinned
+= obj
->base
.size
;
5309 bound
+= obj
->base
.size
;
5313 mutex_unlock(&dev
->struct_mutex
);
5315 if (freed_pages
|| unbound
|| bound
)
5316 pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5317 freed_pages
<< PAGE_SHIFT
, pinned
);
5318 if (unbound
|| bound
)
5319 pr_err("%lu and %lu bytes still available in the "
5320 "bound and unbound GPU page lists.\n",
5323 *(unsigned long *)ptr
+= freed_pages
;
5327 struct i915_vma
*i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
)
5329 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
5330 struct i915_vma
*vma
;
5332 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
5333 if (vma
->vm
== ggtt
&&
5334 vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
)