2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
43 static __must_check
int
44 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
47 i915_gem_object_retire(struct drm_i915_gem_object
*obj
);
49 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
50 struct drm_i915_gem_object
*obj
);
51 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
52 struct drm_i915_fence_reg
*fence
,
55 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
56 enum i915_cache_level level
)
58 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
61 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
63 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
66 return obj
->pin_display
;
69 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
72 i915_gem_release_mmap(obj
);
74 /* As we do not have an associated fence register, we will force
75 * a tiling change if we ever need to acquire one.
77 obj
->fence_dirty
= false;
78 obj
->fence_reg
= I915_FENCE_REG_NONE
;
81 /* some bookkeeping */
82 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
85 spin_lock(&dev_priv
->mm
.object_stat_lock
);
86 dev_priv
->mm
.object_count
++;
87 dev_priv
->mm
.object_memory
+= size
;
88 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
91 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
94 spin_lock(&dev_priv
->mm
.object_stat_lock
);
95 dev_priv
->mm
.object_count
--;
96 dev_priv
->mm
.object_memory
-= size
;
97 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
101 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
105 #define EXIT_COND (!i915_reset_in_progress(error) || \
106 i915_terminally_wedged(error))
111 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
112 * userspace. If it takes that long something really bad is going on and
113 * we should simply try to bail out and fail as gracefully as possible.
115 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
119 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
121 } else if (ret
< 0) {
129 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
134 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
138 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
142 WARN_ON(i915_verify_lists(dev
));
147 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
148 struct drm_file
*file
)
150 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
151 struct drm_i915_gem_get_aperture
*args
= data
;
152 struct drm_i915_gem_object
*obj
;
156 mutex_lock(&dev
->struct_mutex
);
157 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
158 if (i915_gem_obj_is_pinned(obj
))
159 pinned
+= i915_gem_obj_ggtt_size(obj
);
160 mutex_unlock(&dev
->struct_mutex
);
162 args
->aper_size
= dev_priv
->gtt
.base
.total
;
163 args
->aper_available_size
= args
->aper_size
- pinned
;
169 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
171 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
172 char *vaddr
= obj
->phys_handle
->vaddr
;
174 struct scatterlist
*sg
;
177 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
180 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
184 page
= shmem_read_mapping_page(mapping
, i
);
186 return PTR_ERR(page
);
188 src
= kmap_atomic(page
);
189 memcpy(vaddr
, src
, PAGE_SIZE
);
190 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
193 page_cache_release(page
);
197 i915_gem_chipset_flush(obj
->base
.dev
);
199 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
203 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
210 sg
->length
= obj
->base
.size
;
212 sg_dma_address(sg
) = obj
->phys_handle
->busaddr
;
213 sg_dma_len(sg
) = obj
->base
.size
;
216 obj
->has_dma_mapping
= true;
221 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
)
225 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
227 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
229 /* In the event of a disaster, abandon all caches and
232 WARN_ON(ret
!= -EIO
);
233 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
236 if (obj
->madv
== I915_MADV_DONTNEED
)
240 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
241 char *vaddr
= obj
->phys_handle
->vaddr
;
244 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
248 page
= shmem_read_mapping_page(mapping
, i
);
252 dst
= kmap_atomic(page
);
253 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
254 memcpy(dst
, vaddr
, PAGE_SIZE
);
257 set_page_dirty(page
);
258 if (obj
->madv
== I915_MADV_WILLNEED
)
259 mark_page_accessed(page
);
260 page_cache_release(page
);
266 sg_free_table(obj
->pages
);
269 obj
->has_dma_mapping
= false;
273 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
275 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
278 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
279 .get_pages
= i915_gem_object_get_pages_phys
,
280 .put_pages
= i915_gem_object_put_pages_phys
,
281 .release
= i915_gem_object_release_phys
,
285 drop_pages(struct drm_i915_gem_object
*obj
)
287 struct i915_vma
*vma
, *next
;
290 drm_gem_object_reference(&obj
->base
);
291 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
)
292 if (i915_vma_unbind(vma
))
295 ret
= i915_gem_object_put_pages(obj
);
296 drm_gem_object_unreference(&obj
->base
);
302 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
305 drm_dma_handle_t
*phys
;
308 if (obj
->phys_handle
) {
309 if ((unsigned long)obj
->phys_handle
->vaddr
& (align
-1))
315 if (obj
->madv
!= I915_MADV_WILLNEED
)
318 if (obj
->base
.filp
== NULL
)
321 ret
= drop_pages(obj
);
325 /* create a new object */
326 phys
= drm_pci_alloc(obj
->base
.dev
, obj
->base
.size
, align
);
330 obj
->phys_handle
= phys
;
331 obj
->ops
= &i915_gem_phys_ops
;
333 return i915_gem_object_get_pages(obj
);
337 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
338 struct drm_i915_gem_pwrite
*args
,
339 struct drm_file
*file_priv
)
341 struct drm_device
*dev
= obj
->base
.dev
;
342 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
343 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
346 /* We manually control the domain here and pretend that it
347 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
349 ret
= i915_gem_object_wait_rendering(obj
, false);
353 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_CPU
);
354 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
355 unsigned long unwritten
;
357 /* The physical object once assigned is fixed for the lifetime
358 * of the obj, so we can safely drop the lock and continue
361 mutex_unlock(&dev
->struct_mutex
);
362 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
363 mutex_lock(&dev
->struct_mutex
);
370 drm_clflush_virt_range(vaddr
, args
->size
);
371 i915_gem_chipset_flush(dev
);
374 intel_fb_obj_flush(obj
, false);
378 void *i915_gem_object_alloc(struct drm_device
*dev
)
380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
381 return kmem_cache_zalloc(dev_priv
->objects
, GFP_KERNEL
);
384 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
386 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
387 kmem_cache_free(dev_priv
->objects
, obj
);
391 i915_gem_create(struct drm_file
*file
,
392 struct drm_device
*dev
,
396 struct drm_i915_gem_object
*obj
;
400 size
= roundup(size
, PAGE_SIZE
);
404 /* Allocate the new object */
405 obj
= i915_gem_alloc_object(dev
, size
);
409 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
410 /* drop reference from allocate - handle holds it now */
411 drm_gem_object_unreference_unlocked(&obj
->base
);
420 i915_gem_dumb_create(struct drm_file
*file
,
421 struct drm_device
*dev
,
422 struct drm_mode_create_dumb
*args
)
424 /* have to work out size/pitch and return them */
425 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
426 args
->size
= args
->pitch
* args
->height
;
427 return i915_gem_create(file
, dev
,
428 args
->size
, &args
->handle
);
432 * Creates a new mm object and returns a handle to it.
435 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
436 struct drm_file
*file
)
438 struct drm_i915_gem_create
*args
= data
;
440 return i915_gem_create(file
, dev
,
441 args
->size
, &args
->handle
);
445 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
446 const char *gpu_vaddr
, int gpu_offset
,
449 int ret
, cpu_offset
= 0;
452 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
453 int this_length
= min(cacheline_end
- gpu_offset
, length
);
454 int swizzled_gpu_offset
= gpu_offset
^ 64;
456 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
457 gpu_vaddr
+ swizzled_gpu_offset
,
462 cpu_offset
+= this_length
;
463 gpu_offset
+= this_length
;
464 length
-= this_length
;
471 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
472 const char __user
*cpu_vaddr
,
475 int ret
, cpu_offset
= 0;
478 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
479 int this_length
= min(cacheline_end
- gpu_offset
, length
);
480 int swizzled_gpu_offset
= gpu_offset
^ 64;
482 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
483 cpu_vaddr
+ cpu_offset
,
488 cpu_offset
+= this_length
;
489 gpu_offset
+= this_length
;
490 length
-= this_length
;
497 * Pins the specified object's pages and synchronizes the object with
498 * GPU accesses. Sets needs_clflush to non-zero if the caller should
499 * flush the object from the CPU cache.
501 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
511 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
512 /* If we're not in the cpu read domain, set ourself into the gtt
513 * read domain and manually flush cachelines (if required). This
514 * optimizes for the case when the gpu will dirty the data
515 * anyway again before the next pread happens. */
516 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
518 ret
= i915_gem_object_wait_rendering(obj
, true);
522 i915_gem_object_retire(obj
);
525 ret
= i915_gem_object_get_pages(obj
);
529 i915_gem_object_pin_pages(obj
);
534 /* Per-page copy function for the shmem pread fastpath.
535 * Flushes invalid cachelines before reading the target if
536 * needs_clflush is set. */
538 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
539 char __user
*user_data
,
540 bool page_do_bit17_swizzling
, bool needs_clflush
)
545 if (unlikely(page_do_bit17_swizzling
))
548 vaddr
= kmap_atomic(page
);
550 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
552 ret
= __copy_to_user_inatomic(user_data
,
553 vaddr
+ shmem_page_offset
,
555 kunmap_atomic(vaddr
);
557 return ret
? -EFAULT
: 0;
561 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
564 if (unlikely(swizzled
)) {
565 unsigned long start
= (unsigned long) addr
;
566 unsigned long end
= (unsigned long) addr
+ length
;
568 /* For swizzling simply ensure that we always flush both
569 * channels. Lame, but simple and it works. Swizzled
570 * pwrite/pread is far from a hotpath - current userspace
571 * doesn't use it at all. */
572 start
= round_down(start
, 128);
573 end
= round_up(end
, 128);
575 drm_clflush_virt_range((void *)start
, end
- start
);
577 drm_clflush_virt_range(addr
, length
);
582 /* Only difference to the fast-path function is that this can handle bit17
583 * and uses non-atomic copy and kmap functions. */
585 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
586 char __user
*user_data
,
587 bool page_do_bit17_swizzling
, bool needs_clflush
)
594 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
596 page_do_bit17_swizzling
);
598 if (page_do_bit17_swizzling
)
599 ret
= __copy_to_user_swizzled(user_data
,
600 vaddr
, shmem_page_offset
,
603 ret
= __copy_to_user(user_data
,
604 vaddr
+ shmem_page_offset
,
608 return ret
? - EFAULT
: 0;
612 i915_gem_shmem_pread(struct drm_device
*dev
,
613 struct drm_i915_gem_object
*obj
,
614 struct drm_i915_gem_pread
*args
,
615 struct drm_file
*file
)
617 char __user
*user_data
;
620 int shmem_page_offset
, page_length
, ret
= 0;
621 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
623 int needs_clflush
= 0;
624 struct sg_page_iter sg_iter
;
626 user_data
= to_user_ptr(args
->data_ptr
);
629 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
631 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
635 offset
= args
->offset
;
637 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
638 offset
>> PAGE_SHIFT
) {
639 struct page
*page
= sg_page_iter_page(&sg_iter
);
644 /* Operation in this page
646 * shmem_page_offset = offset within page in shmem file
647 * page_length = bytes to copy for this page
649 shmem_page_offset
= offset_in_page(offset
);
650 page_length
= remain
;
651 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
652 page_length
= PAGE_SIZE
- shmem_page_offset
;
654 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
655 (page_to_phys(page
) & (1 << 17)) != 0;
657 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
658 user_data
, page_do_bit17_swizzling
,
663 mutex_unlock(&dev
->struct_mutex
);
665 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
666 ret
= fault_in_multipages_writeable(user_data
, remain
);
667 /* Userspace is tricking us, but we've already clobbered
668 * its pages with the prefault and promised to write the
669 * data up to the first fault. Hence ignore any errors
670 * and just continue. */
675 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
676 user_data
, page_do_bit17_swizzling
,
679 mutex_lock(&dev
->struct_mutex
);
685 remain
-= page_length
;
686 user_data
+= page_length
;
687 offset
+= page_length
;
691 i915_gem_object_unpin_pages(obj
);
697 * Reads data from the object referenced by handle.
699 * On error, the contents of *data are undefined.
702 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
703 struct drm_file
*file
)
705 struct drm_i915_gem_pread
*args
= data
;
706 struct drm_i915_gem_object
*obj
;
712 if (!access_ok(VERIFY_WRITE
,
713 to_user_ptr(args
->data_ptr
),
717 ret
= i915_mutex_lock_interruptible(dev
);
721 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
722 if (&obj
->base
== NULL
) {
727 /* Bounds check source. */
728 if (args
->offset
> obj
->base
.size
||
729 args
->size
> obj
->base
.size
- args
->offset
) {
734 /* prime objects have no backing filp to GEM pread/pwrite
737 if (!obj
->base
.filp
) {
742 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
744 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
747 drm_gem_object_unreference(&obj
->base
);
749 mutex_unlock(&dev
->struct_mutex
);
753 /* This is the fast write path which cannot handle
754 * page faults in the source data
758 fast_user_write(struct io_mapping
*mapping
,
759 loff_t page_base
, int page_offset
,
760 char __user
*user_data
,
763 void __iomem
*vaddr_atomic
;
765 unsigned long unwritten
;
767 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
768 /* We can use the cpu mem copy function because this is X86. */
769 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
770 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
772 io_mapping_unmap_atomic(vaddr_atomic
);
777 * This is the fast pwrite path, where we copy the data directly from the
778 * user into the GTT, uncached.
781 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
782 struct drm_i915_gem_object
*obj
,
783 struct drm_i915_gem_pwrite
*args
,
784 struct drm_file
*file
)
786 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
788 loff_t offset
, page_base
;
789 char __user
*user_data
;
790 int page_offset
, page_length
, ret
;
792 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
796 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
800 ret
= i915_gem_object_put_fence(obj
);
804 user_data
= to_user_ptr(args
->data_ptr
);
807 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
809 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_GTT
);
812 /* Operation in this page
814 * page_base = page offset within aperture
815 * page_offset = offset within page
816 * page_length = bytes to copy for this page
818 page_base
= offset
& PAGE_MASK
;
819 page_offset
= offset_in_page(offset
);
820 page_length
= remain
;
821 if ((page_offset
+ remain
) > PAGE_SIZE
)
822 page_length
= PAGE_SIZE
- page_offset
;
824 /* If we get a fault while copying data, then (presumably) our
825 * source page isn't available. Return the error and we'll
826 * retry in the slow path.
828 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
829 page_offset
, user_data
, page_length
)) {
834 remain
-= page_length
;
835 user_data
+= page_length
;
836 offset
+= page_length
;
840 intel_fb_obj_flush(obj
, false);
842 i915_gem_object_ggtt_unpin(obj
);
847 /* Per-page copy function for the shmem pwrite fastpath.
848 * Flushes invalid cachelines before writing to the target if
849 * needs_clflush_before is set and flushes out any written cachelines after
850 * writing if needs_clflush is set. */
852 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
853 char __user
*user_data
,
854 bool page_do_bit17_swizzling
,
855 bool needs_clflush_before
,
856 bool needs_clflush_after
)
861 if (unlikely(page_do_bit17_swizzling
))
864 vaddr
= kmap_atomic(page
);
865 if (needs_clflush_before
)
866 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
868 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
869 user_data
, page_length
);
870 if (needs_clflush_after
)
871 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
873 kunmap_atomic(vaddr
);
875 return ret
? -EFAULT
: 0;
878 /* Only difference to the fast-path function is that this can handle bit17
879 * and uses non-atomic copy and kmap functions. */
881 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
882 char __user
*user_data
,
883 bool page_do_bit17_swizzling
,
884 bool needs_clflush_before
,
885 bool needs_clflush_after
)
891 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
892 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
894 page_do_bit17_swizzling
);
895 if (page_do_bit17_swizzling
)
896 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
900 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
903 if (needs_clflush_after
)
904 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
906 page_do_bit17_swizzling
);
909 return ret
? -EFAULT
: 0;
913 i915_gem_shmem_pwrite(struct drm_device
*dev
,
914 struct drm_i915_gem_object
*obj
,
915 struct drm_i915_gem_pwrite
*args
,
916 struct drm_file
*file
)
920 char __user
*user_data
;
921 int shmem_page_offset
, page_length
, ret
= 0;
922 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
923 int hit_slowpath
= 0;
924 int needs_clflush_after
= 0;
925 int needs_clflush_before
= 0;
926 struct sg_page_iter sg_iter
;
928 user_data
= to_user_ptr(args
->data_ptr
);
931 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
933 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
934 /* If we're not in the cpu write domain, set ourself into the gtt
935 * write domain and manually flush cachelines (if required). This
936 * optimizes for the case when the gpu will use the data
937 * right away and we therefore have to clflush anyway. */
938 needs_clflush_after
= cpu_write_needs_clflush(obj
);
939 ret
= i915_gem_object_wait_rendering(obj
, false);
943 i915_gem_object_retire(obj
);
945 /* Same trick applies to invalidate partially written cachelines read
947 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
948 needs_clflush_before
=
949 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
951 ret
= i915_gem_object_get_pages(obj
);
955 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_CPU
);
957 i915_gem_object_pin_pages(obj
);
959 offset
= args
->offset
;
962 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
963 offset
>> PAGE_SHIFT
) {
964 struct page
*page
= sg_page_iter_page(&sg_iter
);
965 int partial_cacheline_write
;
970 /* Operation in this page
972 * shmem_page_offset = offset within page in shmem file
973 * page_length = bytes to copy for this page
975 shmem_page_offset
= offset_in_page(offset
);
977 page_length
= remain
;
978 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
979 page_length
= PAGE_SIZE
- shmem_page_offset
;
981 /* If we don't overwrite a cacheline completely we need to be
982 * careful to have up-to-date data by first clflushing. Don't
983 * overcomplicate things and flush the entire patch. */
984 partial_cacheline_write
= needs_clflush_before
&&
985 ((shmem_page_offset
| page_length
)
986 & (boot_cpu_data
.x86_clflush_size
- 1));
988 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
989 (page_to_phys(page
) & (1 << 17)) != 0;
991 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
992 user_data
, page_do_bit17_swizzling
,
993 partial_cacheline_write
,
994 needs_clflush_after
);
999 mutex_unlock(&dev
->struct_mutex
);
1000 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
1001 user_data
, page_do_bit17_swizzling
,
1002 partial_cacheline_write
,
1003 needs_clflush_after
);
1005 mutex_lock(&dev
->struct_mutex
);
1011 remain
-= page_length
;
1012 user_data
+= page_length
;
1013 offset
+= page_length
;
1017 i915_gem_object_unpin_pages(obj
);
1021 * Fixup: Flush cpu caches in case we didn't flush the dirty
1022 * cachelines in-line while writing and the object moved
1023 * out of the cpu write domain while we've dropped the lock.
1025 if (!needs_clflush_after
&&
1026 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1027 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
1028 i915_gem_chipset_flush(dev
);
1032 if (needs_clflush_after
)
1033 i915_gem_chipset_flush(dev
);
1035 intel_fb_obj_flush(obj
, false);
1040 * Writes data to the object referenced by handle.
1042 * On error, the contents of the buffer that were to be modified are undefined.
1045 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1046 struct drm_file
*file
)
1048 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1049 struct drm_i915_gem_pwrite
*args
= data
;
1050 struct drm_i915_gem_object
*obj
;
1053 if (args
->size
== 0)
1056 if (!access_ok(VERIFY_READ
,
1057 to_user_ptr(args
->data_ptr
),
1061 if (likely(!i915
.prefault_disable
)) {
1062 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
1068 intel_runtime_pm_get(dev_priv
);
1070 ret
= i915_mutex_lock_interruptible(dev
);
1074 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1075 if (&obj
->base
== NULL
) {
1080 /* Bounds check destination. */
1081 if (args
->offset
> obj
->base
.size
||
1082 args
->size
> obj
->base
.size
- args
->offset
) {
1087 /* prime objects have no backing filp to GEM pread/pwrite
1090 if (!obj
->base
.filp
) {
1095 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1098 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1099 * it would end up going through the fenced access, and we'll get
1100 * different detiling behavior between reading and writing.
1101 * pread/pwrite currently are reading and writing from the CPU
1102 * perspective, requiring manual detiling by the client.
1104 if (obj
->tiling_mode
== I915_TILING_NONE
&&
1105 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
1106 cpu_write_needs_clflush(obj
)) {
1107 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1108 /* Note that the gtt paths might fail with non-page-backed user
1109 * pointers (e.g. gtt mappings when moving data between
1110 * textures). Fallback to the shmem path in that case. */
1113 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1114 if (obj
->phys_handle
)
1115 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1117 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
1121 drm_gem_object_unreference(&obj
->base
);
1123 mutex_unlock(&dev
->struct_mutex
);
1125 intel_runtime_pm_put(dev_priv
);
1131 i915_gem_check_wedge(struct i915_gpu_error
*error
,
1134 if (i915_reset_in_progress(error
)) {
1135 /* Non-interruptible callers can't handle -EAGAIN, hence return
1136 * -EIO unconditionally for these. */
1140 /* Recovery complete, but the reset failed ... */
1141 if (i915_terminally_wedged(error
))
1145 * Check if GPU Reset is in progress - we need intel_ring_begin
1146 * to work properly to reinit the hw state while the gpu is
1147 * still marked as reset-in-progress. Handle this with a flag.
1149 if (!error
->reload_in_reset
)
1157 * Compare arbitrary request against outstanding lazy request. Emit on match.
1160 i915_gem_check_olr(struct drm_i915_gem_request
*req
)
1164 WARN_ON(!mutex_is_locked(&req
->ring
->dev
->struct_mutex
));
1167 if (req
== req
->ring
->outstanding_lazy_request
)
1168 ret
= i915_add_request(req
->ring
);
1173 static void fake_irq(unsigned long data
)
1175 wake_up_process((struct task_struct
*)data
);
1178 static bool missed_irq(struct drm_i915_private
*dev_priv
,
1179 struct intel_engine_cs
*ring
)
1181 return test_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
1184 static int __i915_spin_request(struct drm_i915_gem_request
*rq
)
1186 unsigned long timeout
;
1188 if (i915_gem_request_get_ring(rq
)->irq_refcount
)
1191 timeout
= jiffies
+ 1;
1192 while (!need_resched()) {
1193 if (i915_gem_request_completed(rq
, true))
1196 if (time_after_eq(jiffies
, timeout
))
1199 cpu_relax_lowlatency();
1201 if (i915_gem_request_completed(rq
, false))
1208 * __i915_wait_request - wait until execution of request has finished
1210 * @reset_counter: reset sequence associated with the given request
1211 * @interruptible: do an interruptible wait (normally yes)
1212 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1214 * Note: It is of utmost importance that the passed in seqno and reset_counter
1215 * values have been read by the caller in an smp safe manner. Where read-side
1216 * locks are involved, it is sufficient to read the reset_counter before
1217 * unlocking the lock that protects the seqno. For lockless tricks, the
1218 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1221 * Returns 0 if the request was found within the alloted time. Else returns the
1222 * errno with remaining time filled in timeout argument.
1224 int __i915_wait_request(struct drm_i915_gem_request
*req
,
1225 unsigned reset_counter
,
1228 struct drm_i915_file_private
*file_priv
)
1230 struct intel_engine_cs
*ring
= i915_gem_request_get_ring(req
);
1231 struct drm_device
*dev
= ring
->dev
;
1232 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1233 const bool irq_test_in_progress
=
1234 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_ring_flag(ring
);
1236 unsigned long timeout_expire
;
1240 WARN(!intel_irqs_enabled(dev_priv
), "IRQs disabled");
1242 if (i915_gem_request_completed(req
, true))
1245 timeout_expire
= timeout
?
1246 jiffies
+ nsecs_to_jiffies_timeout((u64
)*timeout
) : 0;
1248 if (INTEL_INFO(dev
)->gen
>= 6)
1249 gen6_rps_boost(dev_priv
, file_priv
);
1251 /* Record current time in case interrupted by signal, or wedged */
1252 trace_i915_gem_request_wait_begin(req
);
1253 before
= ktime_get_raw_ns();
1255 /* Optimistic spin for the next jiffie before touching IRQs */
1256 ret
= __i915_spin_request(req
);
1260 if (!irq_test_in_progress
&& WARN_ON(!ring
->irq_get(ring
))) {
1266 struct timer_list timer
;
1268 prepare_to_wait(&ring
->irq_queue
, &wait
,
1269 interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
);
1271 /* We need to check whether any gpu reset happened in between
1272 * the caller grabbing the seqno and now ... */
1273 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
)) {
1274 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1275 * is truely gone. */
1276 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1282 if (i915_gem_request_completed(req
, false)) {
1287 if (interruptible
&& signal_pending(current
)) {
1292 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1297 timer
.function
= NULL
;
1298 if (timeout
|| missed_irq(dev_priv
, ring
)) {
1299 unsigned long expire
;
1301 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1302 expire
= missed_irq(dev_priv
, ring
) ? jiffies
+ 1 : timeout_expire
;
1303 mod_timer(&timer
, expire
);
1308 if (timer
.function
) {
1309 del_singleshot_timer_sync(&timer
);
1310 destroy_timer_on_stack(&timer
);
1313 if (!irq_test_in_progress
)
1314 ring
->irq_put(ring
);
1316 finish_wait(&ring
->irq_queue
, &wait
);
1319 now
= ktime_get_raw_ns();
1320 trace_i915_gem_request_wait_end(req
);
1323 s64 tres
= *timeout
- (now
- before
);
1325 *timeout
= tres
< 0 ? 0 : tres
;
1328 * Apparently ktime isn't accurate enough and occasionally has a
1329 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1330 * things up to make the test happy. We allow up to 1 jiffy.
1332 * This is a regrssion from the timespec->ktime conversion.
1334 if (ret
== -ETIME
&& *timeout
< jiffies_to_usecs(1)*1000)
1342 * Waits for a request to be signaled, and cleans up the
1343 * request and object lists appropriately for that event.
1346 i915_wait_request(struct drm_i915_gem_request
*req
)
1348 struct drm_device
*dev
;
1349 struct drm_i915_private
*dev_priv
;
1351 unsigned reset_counter
;
1354 BUG_ON(req
== NULL
);
1356 dev
= req
->ring
->dev
;
1357 dev_priv
= dev
->dev_private
;
1358 interruptible
= dev_priv
->mm
.interruptible
;
1360 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1362 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1366 ret
= i915_gem_check_olr(req
);
1370 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1371 i915_gem_request_reference(req
);
1372 ret
= __i915_wait_request(req
, reset_counter
,
1373 interruptible
, NULL
, NULL
);
1374 i915_gem_request_unreference(req
);
1379 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object
*obj
)
1384 /* Manually manage the write flush as we may have not yet
1385 * retired the buffer.
1387 * Note that the last_write_req is always the earlier of
1388 * the two (read/write) requests, so if we haved successfully waited,
1389 * we know we have passed the last write.
1391 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
1397 * Ensures that all rendering to the object has completed and the object is
1398 * safe to unbind from the GTT or access from the CPU.
1400 static __must_check
int
1401 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1404 struct drm_i915_gem_request
*req
;
1407 req
= readonly
? obj
->last_write_req
: obj
->last_read_req
;
1411 ret
= i915_wait_request(req
);
1415 return i915_gem_object_wait_rendering__tail(obj
);
1418 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1419 * as the object state may change during this call.
1421 static __must_check
int
1422 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1423 struct drm_i915_file_private
*file_priv
,
1426 struct drm_i915_gem_request
*req
;
1427 struct drm_device
*dev
= obj
->base
.dev
;
1428 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1429 unsigned reset_counter
;
1432 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1433 BUG_ON(!dev_priv
->mm
.interruptible
);
1435 req
= readonly
? obj
->last_write_req
: obj
->last_read_req
;
1439 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1443 ret
= i915_gem_check_olr(req
);
1447 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1448 i915_gem_request_reference(req
);
1449 mutex_unlock(&dev
->struct_mutex
);
1450 ret
= __i915_wait_request(req
, reset_counter
, true, NULL
, file_priv
);
1451 mutex_lock(&dev
->struct_mutex
);
1452 i915_gem_request_unreference(req
);
1456 return i915_gem_object_wait_rendering__tail(obj
);
1460 * Called when user space prepares to use an object with the CPU, either
1461 * through the mmap ioctl's mapping or a GTT mapping.
1464 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1465 struct drm_file
*file
)
1467 struct drm_i915_gem_set_domain
*args
= data
;
1468 struct drm_i915_gem_object
*obj
;
1469 uint32_t read_domains
= args
->read_domains
;
1470 uint32_t write_domain
= args
->write_domain
;
1473 /* Only handle setting domains to types used by the CPU. */
1474 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1477 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1480 /* Having something in the write domain implies it's in the read
1481 * domain, and only that read domain. Enforce that in the request.
1483 if (write_domain
!= 0 && read_domains
!= write_domain
)
1486 ret
= i915_mutex_lock_interruptible(dev
);
1490 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1491 if (&obj
->base
== NULL
) {
1496 /* Try to flush the object off the GPU without holding the lock.
1497 * We will repeat the flush holding the lock in the normal manner
1498 * to catch cases where we are gazumped.
1500 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1506 if (read_domains
& I915_GEM_DOMAIN_GTT
)
1507 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1509 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1512 drm_gem_object_unreference(&obj
->base
);
1514 mutex_unlock(&dev
->struct_mutex
);
1519 * Called when user space has done writes to this buffer
1522 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1523 struct drm_file
*file
)
1525 struct drm_i915_gem_sw_finish
*args
= data
;
1526 struct drm_i915_gem_object
*obj
;
1529 ret
= i915_mutex_lock_interruptible(dev
);
1533 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1534 if (&obj
->base
== NULL
) {
1539 /* Pinned buffers may be scanout, so flush the cache */
1540 if (obj
->pin_display
)
1541 i915_gem_object_flush_cpu_write_domain(obj
);
1543 drm_gem_object_unreference(&obj
->base
);
1545 mutex_unlock(&dev
->struct_mutex
);
1550 * Maps the contents of an object, returning the address it is mapped
1553 * While the mapping holds a reference on the contents of the object, it doesn't
1554 * imply a ref on the object itself.
1558 * DRM driver writers who look a this function as an example for how to do GEM
1559 * mmap support, please don't implement mmap support like here. The modern way
1560 * to implement DRM mmap support is with an mmap offset ioctl (like
1561 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1562 * That way debug tooling like valgrind will understand what's going on, hiding
1563 * the mmap call in a driver private ioctl will break that. The i915 driver only
1564 * does cpu mmaps this way because we didn't know better.
1567 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1568 struct drm_file
*file
)
1570 struct drm_i915_gem_mmap
*args
= data
;
1571 struct drm_gem_object
*obj
;
1574 if (args
->flags
& ~(I915_MMAP_WC
))
1577 if (args
->flags
& I915_MMAP_WC
&& !cpu_has_pat
)
1580 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1584 /* prime objects have no backing filp to GEM mmap
1588 drm_gem_object_unreference_unlocked(obj
);
1592 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1593 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1595 if (args
->flags
& I915_MMAP_WC
) {
1596 struct mm_struct
*mm
= current
->mm
;
1597 struct vm_area_struct
*vma
;
1599 down_write(&mm
->mmap_sem
);
1600 vma
= find_vma(mm
, addr
);
1603 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1606 up_write(&mm
->mmap_sem
);
1608 drm_gem_object_unreference_unlocked(obj
);
1609 if (IS_ERR((void *)addr
))
1612 args
->addr_ptr
= (uint64_t) addr
;
1618 * i915_gem_fault - fault a page into the GTT
1619 * vma: VMA in question
1622 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1623 * from userspace. The fault handler takes care of binding the object to
1624 * the GTT (if needed), allocating and programming a fence register (again,
1625 * only if needed based on whether the old reg is still valid or the object
1626 * is tiled) and inserting a new PTE into the faulting process.
1628 * Note that the faulting process may involve evicting existing objects
1629 * from the GTT and/or fence registers to make room. So performance may
1630 * suffer if the GTT working set is large or there are few fence registers
1633 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1635 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1636 struct drm_device
*dev
= obj
->base
.dev
;
1637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1638 pgoff_t page_offset
;
1641 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1643 intel_runtime_pm_get(dev_priv
);
1645 /* We don't use vmf->pgoff since that has the fake offset */
1646 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1649 ret
= i915_mutex_lock_interruptible(dev
);
1653 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1655 /* Try to flush the object off the GPU first without holding the lock.
1656 * Upon reacquiring the lock, we will perform our sanity checks and then
1657 * repeat the flush holding the lock in the normal manner to catch cases
1658 * where we are gazumped.
1660 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
1664 /* Access to snoopable pages through the GTT is incoherent. */
1665 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1670 /* Now bind it into the GTT if needed */
1671 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
);
1675 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1679 ret
= i915_gem_object_get_fence(obj
);
1683 /* Finally, remap it using the new GTT offset */
1684 pfn
= dev_priv
->gtt
.mappable_base
+ i915_gem_obj_ggtt_offset(obj
);
1687 if (!obj
->fault_mappable
) {
1688 unsigned long size
= min_t(unsigned long,
1689 vma
->vm_end
- vma
->vm_start
,
1693 for (i
= 0; i
< size
>> PAGE_SHIFT
; i
++) {
1694 ret
= vm_insert_pfn(vma
,
1695 (unsigned long)vma
->vm_start
+ i
* PAGE_SIZE
,
1701 obj
->fault_mappable
= true;
1703 ret
= vm_insert_pfn(vma
,
1704 (unsigned long)vmf
->virtual_address
,
1707 i915_gem_object_ggtt_unpin(obj
);
1709 mutex_unlock(&dev
->struct_mutex
);
1714 * We eat errors when the gpu is terminally wedged to avoid
1715 * userspace unduly crashing (gl has no provisions for mmaps to
1716 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1717 * and so needs to be reported.
1719 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1720 ret
= VM_FAULT_SIGBUS
;
1725 * EAGAIN means the gpu is hung and we'll wait for the error
1726 * handler to reset everything when re-faulting in
1727 * i915_mutex_lock_interruptible.
1734 * EBUSY is ok: this just means that another thread
1735 * already did the job.
1737 ret
= VM_FAULT_NOPAGE
;
1744 ret
= VM_FAULT_SIGBUS
;
1747 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1748 ret
= VM_FAULT_SIGBUS
;
1752 intel_runtime_pm_put(dev_priv
);
1757 * i915_gem_release_mmap - remove physical page mappings
1758 * @obj: obj in question
1760 * Preserve the reservation of the mmapping with the DRM core code, but
1761 * relinquish ownership of the pages back to the system.
1763 * It is vital that we remove the page mapping if we have mapped a tiled
1764 * object through the GTT and then lose the fence register due to
1765 * resource pressure. Similarly if the object has been moved out of the
1766 * aperture, than pages mapped into userspace must be revoked. Removing the
1767 * mapping will then trigger a page fault on the next user access, allowing
1768 * fixup by i915_gem_fault().
1771 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1773 if (!obj
->fault_mappable
)
1776 drm_vma_node_unmap(&obj
->base
.vma_node
,
1777 obj
->base
.dev
->anon_inode
->i_mapping
);
1778 obj
->fault_mappable
= false;
1782 i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
1784 struct drm_i915_gem_object
*obj
;
1786 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
1787 i915_gem_release_mmap(obj
);
1791 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1795 if (INTEL_INFO(dev
)->gen
>= 4 ||
1796 tiling_mode
== I915_TILING_NONE
)
1799 /* Previous chips need a power-of-two fence region when tiling */
1800 if (INTEL_INFO(dev
)->gen
== 3)
1801 gtt_size
= 1024*1024;
1803 gtt_size
= 512*1024;
1805 while (gtt_size
< size
)
1812 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1813 * @obj: object to check
1815 * Return the required GTT alignment for an object, taking into account
1816 * potential fence register mapping.
1819 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1820 int tiling_mode
, bool fenced
)
1823 * Minimum alignment is 4k (GTT page size), but might be greater
1824 * if a fence register is needed for the object.
1826 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1827 tiling_mode
== I915_TILING_NONE
)
1831 * Previous chips need to be aligned to the size of the smallest
1832 * fence register that can contain the object.
1834 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1837 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1839 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1842 if (drm_vma_node_has_offset(&obj
->base
.vma_node
))
1845 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1847 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1851 /* Badly fragmented mmap space? The only way we can recover
1852 * space is by destroying unwanted objects. We can't randomly release
1853 * mmap_offsets as userspace expects them to be persistent for the
1854 * lifetime of the objects. The closest we can is to release the
1855 * offsets on purgeable objects by truncating it and marking it purged,
1856 * which prevents userspace from ever using that object again.
1858 i915_gem_shrink(dev_priv
,
1859 obj
->base
.size
>> PAGE_SHIFT
,
1861 I915_SHRINK_UNBOUND
|
1862 I915_SHRINK_PURGEABLE
);
1863 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1867 i915_gem_shrink_all(dev_priv
);
1868 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1870 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
1875 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1877 drm_gem_free_mmap_offset(&obj
->base
);
1881 i915_gem_mmap_gtt(struct drm_file
*file
,
1882 struct drm_device
*dev
,
1886 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1887 struct drm_i915_gem_object
*obj
;
1890 ret
= i915_mutex_lock_interruptible(dev
);
1894 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1895 if (&obj
->base
== NULL
) {
1900 if (obj
->base
.size
> dev_priv
->gtt
.mappable_end
) {
1905 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1906 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1911 ret
= i915_gem_object_create_mmap_offset(obj
);
1915 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
1918 drm_gem_object_unreference(&obj
->base
);
1920 mutex_unlock(&dev
->struct_mutex
);
1925 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1927 * @data: GTT mapping ioctl data
1928 * @file: GEM object info
1930 * Simply returns the fake offset to userspace so it can mmap it.
1931 * The mmap call will end up in drm_gem_mmap(), which will set things
1932 * up so we can get faults in the handler above.
1934 * The fault handler will take care of binding the object into the GTT
1935 * (since it may have been evicted to make room for something), allocating
1936 * a fence register, and mapping the appropriate aperture address into
1940 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1941 struct drm_file
*file
)
1943 struct drm_i915_gem_mmap_gtt
*args
= data
;
1945 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1948 /* Immediately discard the backing storage */
1950 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1952 i915_gem_object_free_mmap_offset(obj
);
1954 if (obj
->base
.filp
== NULL
)
1957 /* Our goal here is to return as much of the memory as
1958 * is possible back to the system as we are called from OOM.
1959 * To do this we must instruct the shmfs to drop all of its
1960 * backing pages, *now*.
1962 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
1963 obj
->madv
= __I915_MADV_PURGED
;
1966 /* Try to discard unwanted pages */
1968 i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
1970 struct address_space
*mapping
;
1972 switch (obj
->madv
) {
1973 case I915_MADV_DONTNEED
:
1974 i915_gem_object_truncate(obj
);
1975 case __I915_MADV_PURGED
:
1979 if (obj
->base
.filp
== NULL
)
1982 mapping
= file_inode(obj
->base
.filp
)->i_mapping
,
1983 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
1987 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1989 struct sg_page_iter sg_iter
;
1992 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1994 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1996 /* In the event of a disaster, abandon all caches and
1997 * hope for the best.
1999 WARN_ON(ret
!= -EIO
);
2000 i915_gem_clflush_object(obj
, true);
2001 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2004 if (i915_gem_object_needs_bit17_swizzle(obj
))
2005 i915_gem_object_save_bit_17_swizzle(obj
);
2007 if (obj
->madv
== I915_MADV_DONTNEED
)
2010 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
2011 struct page
*page
= sg_page_iter_page(&sg_iter
);
2014 set_page_dirty(page
);
2016 if (obj
->madv
== I915_MADV_WILLNEED
)
2017 mark_page_accessed(page
);
2019 page_cache_release(page
);
2023 sg_free_table(obj
->pages
);
2028 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
2030 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2032 if (obj
->pages
== NULL
)
2035 if (obj
->pages_pin_count
)
2038 BUG_ON(i915_gem_obj_bound_any(obj
));
2040 /* ->put_pages might need to allocate memory for the bit17 swizzle
2041 * array, hence protect them from being reaped by removing them from gtt
2043 list_del(&obj
->global_list
);
2045 ops
->put_pages(obj
);
2048 i915_gem_object_invalidate(obj
);
2054 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2056 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2058 struct address_space
*mapping
;
2059 struct sg_table
*st
;
2060 struct scatterlist
*sg
;
2061 struct sg_page_iter sg_iter
;
2063 unsigned long last_pfn
= 0; /* suppress gcc warning */
2066 /* Assert that the object is not currently in any GPU domain. As it
2067 * wasn't in the GTT, there shouldn't be any way it could have been in
2070 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2071 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2073 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2077 page_count
= obj
->base
.size
/ PAGE_SIZE
;
2078 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2083 /* Get the list of pages out of our struct file. They'll be pinned
2084 * at this point until we release them.
2086 * Fail silently without starting the shrinker
2088 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
2089 gfp
= mapping_gfp_mask(mapping
);
2090 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
2091 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
2094 for (i
= 0; i
< page_count
; i
++) {
2095 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2097 i915_gem_shrink(dev_priv
,
2100 I915_SHRINK_UNBOUND
|
2101 I915_SHRINK_PURGEABLE
);
2102 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2105 /* We've tried hard to allocate the memory by reaping
2106 * our own buffer, now let the real VM do its job and
2107 * go down in flames if truly OOM.
2109 i915_gem_shrink_all(dev_priv
);
2110 page
= shmem_read_mapping_page(mapping
, i
);
2114 #ifdef CONFIG_SWIOTLB
2115 if (swiotlb_nr_tbl()) {
2117 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2122 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
2126 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2128 sg
->length
+= PAGE_SIZE
;
2130 last_pfn
= page_to_pfn(page
);
2132 /* Check that the i965g/gm workaround works. */
2133 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2135 #ifdef CONFIG_SWIOTLB
2136 if (!swiotlb_nr_tbl())
2141 if (i915_gem_object_needs_bit17_swizzle(obj
))
2142 i915_gem_object_do_bit_17_swizzle(obj
);
2144 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
2145 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2146 i915_gem_object_pin_pages(obj
);
2152 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
2153 page_cache_release(sg_page_iter_page(&sg_iter
));
2157 /* shmemfs first checks if there is enough memory to allocate the page
2158 * and reports ENOSPC should there be insufficient, along with the usual
2159 * ENOMEM for a genuine allocation failure.
2161 * We use ENOSPC in our driver to mean that we have run out of aperture
2162 * space and so want to translate the error from shmemfs back to our
2163 * usual understanding of ENOMEM.
2165 if (PTR_ERR(page
) == -ENOSPC
)
2168 return PTR_ERR(page
);
2171 /* Ensure that the associated pages are gathered from the backing storage
2172 * and pinned into our object. i915_gem_object_get_pages() may be called
2173 * multiple times before they are released by a single call to
2174 * i915_gem_object_put_pages() - once the pages are no longer referenced
2175 * either as a result of memory pressure (reaping pages under the shrinker)
2176 * or as the object is itself released.
2179 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2181 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2182 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2188 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2189 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2193 BUG_ON(obj
->pages_pin_count
);
2195 ret
= ops
->get_pages(obj
);
2199 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2201 obj
->get_page
.sg
= obj
->pages
->sgl
;
2202 obj
->get_page
.last
= 0;
2208 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
2209 struct intel_engine_cs
*ring
)
2211 struct drm_i915_gem_request
*req
;
2212 struct intel_engine_cs
*old_ring
;
2214 BUG_ON(ring
== NULL
);
2216 req
= intel_ring_get_request(ring
);
2217 old_ring
= i915_gem_request_get_ring(obj
->last_read_req
);
2219 if (old_ring
!= ring
&& obj
->last_write_req
) {
2220 /* Keep the request relative to the current ring */
2221 i915_gem_request_assign(&obj
->last_write_req
, req
);
2224 /* Add a reference if we're newly entering the active list. */
2226 drm_gem_object_reference(&obj
->base
);
2230 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
2232 i915_gem_request_assign(&obj
->last_read_req
, req
);
2235 void i915_vma_move_to_active(struct i915_vma
*vma
,
2236 struct intel_engine_cs
*ring
)
2238 list_move_tail(&vma
->mm_list
, &vma
->vm
->active_list
);
2239 return i915_gem_object_move_to_active(vma
->obj
, ring
);
2243 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
2245 struct i915_vma
*vma
;
2247 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
2248 BUG_ON(!obj
->active
);
2250 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
2251 if (!list_empty(&vma
->mm_list
))
2252 list_move_tail(&vma
->mm_list
, &vma
->vm
->inactive_list
);
2255 intel_fb_obj_flush(obj
, true);
2257 list_del_init(&obj
->ring_list
);
2259 i915_gem_request_assign(&obj
->last_read_req
, NULL
);
2260 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
2261 obj
->base
.write_domain
= 0;
2263 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
2266 drm_gem_object_unreference(&obj
->base
);
2268 WARN_ON(i915_verify_lists(dev
));
2272 i915_gem_object_retire(struct drm_i915_gem_object
*obj
)
2274 if (obj
->last_read_req
== NULL
)
2277 if (i915_gem_request_completed(obj
->last_read_req
, true))
2278 i915_gem_object_move_to_inactive(obj
);
2282 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
2284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2285 struct intel_engine_cs
*ring
;
2288 /* Carefully retire all requests without writing to the rings */
2289 for_each_ring(ring
, dev_priv
, i
) {
2290 ret
= intel_ring_idle(ring
);
2294 i915_gem_retire_requests(dev
);
2296 /* Finally reset hw state */
2297 for_each_ring(ring
, dev_priv
, i
) {
2298 intel_ring_init_seqno(ring
, seqno
);
2300 for (j
= 0; j
< ARRAY_SIZE(ring
->semaphore
.sync_seqno
); j
++)
2301 ring
->semaphore
.sync_seqno
[j
] = 0;
2307 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2315 /* HWS page needs to be set less than what we
2316 * will inject to ring
2318 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
2322 /* Carefully set the last_seqno value so that wrap
2323 * detection still works
2325 dev_priv
->next_seqno
= seqno
;
2326 dev_priv
->last_seqno
= seqno
- 1;
2327 if (dev_priv
->last_seqno
== 0)
2328 dev_priv
->last_seqno
--;
2334 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
2336 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2338 /* reserve 0 for non-seqno */
2339 if (dev_priv
->next_seqno
== 0) {
2340 int ret
= i915_gem_init_seqno(dev
, 0);
2344 dev_priv
->next_seqno
= 1;
2347 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2351 int __i915_add_request(struct intel_engine_cs
*ring
,
2352 struct drm_file
*file
,
2353 struct drm_i915_gem_object
*obj
)
2355 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2356 struct drm_i915_gem_request
*request
;
2357 struct intel_ringbuffer
*ringbuf
;
2361 request
= ring
->outstanding_lazy_request
;
2362 if (WARN_ON(request
== NULL
))
2365 if (i915
.enable_execlists
) {
2366 ringbuf
= request
->ctx
->engine
[ring
->id
].ringbuf
;
2368 ringbuf
= ring
->buffer
;
2370 request_start
= intel_ring_get_tail(ringbuf
);
2372 * Emit any outstanding flushes - execbuf can fail to emit the flush
2373 * after having emitted the batchbuffer command. Hence we need to fix
2374 * things up similar to emitting the lazy request. The difference here
2375 * is that the flush _must_ happen before the next request, no matter
2378 if (i915
.enable_execlists
) {
2379 ret
= logical_ring_flush_all_caches(ringbuf
, request
->ctx
);
2383 ret
= intel_ring_flush_all_caches(ring
);
2388 /* Record the position of the start of the request so that
2389 * should we detect the updated seqno part-way through the
2390 * GPU processing the request, we never over-estimate the
2391 * position of the head.
2393 request
->postfix
= intel_ring_get_tail(ringbuf
);
2395 if (i915
.enable_execlists
) {
2396 ret
= ring
->emit_request(ringbuf
, request
);
2400 ret
= ring
->add_request(ring
);
2405 request
->head
= request_start
;
2406 request
->tail
= intel_ring_get_tail(ringbuf
);
2408 /* Whilst this request exists, batch_obj will be on the
2409 * active_list, and so will hold the active reference. Only when this
2410 * request is retired will the the batch_obj be moved onto the
2411 * inactive_list and lose its active reference. Hence we do not need
2412 * to explicitly hold another reference here.
2414 request
->batch_obj
= obj
;
2416 if (!i915
.enable_execlists
) {
2417 /* Hold a reference to the current context so that we can inspect
2418 * it later in case a hangcheck error event fires.
2420 request
->ctx
= ring
->last_context
;
2422 i915_gem_context_reference(request
->ctx
);
2425 request
->emitted_jiffies
= jiffies
;
2426 list_add_tail(&request
->list
, &ring
->request_list
);
2427 request
->file_priv
= NULL
;
2430 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2432 spin_lock(&file_priv
->mm
.lock
);
2433 request
->file_priv
= file_priv
;
2434 list_add_tail(&request
->client_list
,
2435 &file_priv
->mm
.request_list
);
2436 spin_unlock(&file_priv
->mm
.lock
);
2438 request
->pid
= get_pid(task_pid(current
));
2441 trace_i915_gem_request_add(request
);
2442 ring
->outstanding_lazy_request
= NULL
;
2444 i915_queue_hangcheck(ring
->dev
);
2446 queue_delayed_work(dev_priv
->wq
,
2447 &dev_priv
->mm
.retire_work
,
2448 round_jiffies_up_relative(HZ
));
2449 intel_mark_busy(dev_priv
->dev
);
2455 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2457 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2462 spin_lock(&file_priv
->mm
.lock
);
2463 list_del(&request
->client_list
);
2464 request
->file_priv
= NULL
;
2465 spin_unlock(&file_priv
->mm
.lock
);
2468 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2469 const struct intel_context
*ctx
)
2471 unsigned long elapsed
;
2473 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2475 if (ctx
->hang_stats
.banned
)
2478 if (ctx
->hang_stats
.ban_period_seconds
&&
2479 elapsed
<= ctx
->hang_stats
.ban_period_seconds
) {
2480 if (!i915_gem_context_is_default(ctx
)) {
2481 DRM_DEBUG("context hanging too fast, banning!\n");
2483 } else if (i915_stop_ring_allow_ban(dev_priv
)) {
2484 if (i915_stop_ring_allow_warn(dev_priv
))
2485 DRM_ERROR("gpu hanging too fast, banning!\n");
2493 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2494 struct intel_context
*ctx
,
2497 struct i915_ctx_hang_stats
*hs
;
2502 hs
= &ctx
->hang_stats
;
2505 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2507 hs
->guilty_ts
= get_seconds();
2509 hs
->batch_pending
++;
2513 static void i915_gem_free_request(struct drm_i915_gem_request
*request
)
2515 list_del(&request
->list
);
2516 i915_gem_request_remove_from_client(request
);
2518 put_pid(request
->pid
);
2520 i915_gem_request_unreference(request
);
2523 void i915_gem_request_free(struct kref
*req_ref
)
2525 struct drm_i915_gem_request
*req
= container_of(req_ref
,
2527 struct intel_context
*ctx
= req
->ctx
;
2530 if (i915
.enable_execlists
) {
2531 struct intel_engine_cs
*ring
= req
->ring
;
2533 if (ctx
!= ring
->default_context
)
2534 intel_lr_context_unpin(ring
, ctx
);
2537 i915_gem_context_unreference(ctx
);
2540 kmem_cache_free(req
->i915
->requests
, req
);
2543 int i915_gem_request_alloc(struct intel_engine_cs
*ring
,
2544 struct intel_context
*ctx
)
2546 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
2547 struct drm_i915_gem_request
*rq
;
2550 if (ring
->outstanding_lazy_request
)
2553 rq
= kmem_cache_zalloc(dev_priv
->requests
, GFP_KERNEL
);
2557 kref_init(&rq
->ref
);
2558 rq
->i915
= dev_priv
;
2560 ret
= i915_gem_get_seqno(ring
->dev
, &rq
->seqno
);
2568 if (i915
.enable_execlists
)
2569 ret
= intel_logical_ring_alloc_request_extras(rq
, ctx
);
2571 ret
= intel_ring_alloc_request_extras(rq
);
2577 ring
->outstanding_lazy_request
= rq
;
2581 struct drm_i915_gem_request
*
2582 i915_gem_find_active_request(struct intel_engine_cs
*ring
)
2584 struct drm_i915_gem_request
*request
;
2586 list_for_each_entry(request
, &ring
->request_list
, list
) {
2587 if (i915_gem_request_completed(request
, false))
2596 static void i915_gem_reset_ring_status(struct drm_i915_private
*dev_priv
,
2597 struct intel_engine_cs
*ring
)
2599 struct drm_i915_gem_request
*request
;
2602 request
= i915_gem_find_active_request(ring
);
2604 if (request
== NULL
)
2607 ring_hung
= ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
2609 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
2611 list_for_each_entry_continue(request
, &ring
->request_list
, list
)
2612 i915_set_reset_status(dev_priv
, request
->ctx
, false);
2615 static void i915_gem_reset_ring_cleanup(struct drm_i915_private
*dev_priv
,
2616 struct intel_engine_cs
*ring
)
2618 while (!list_empty(&ring
->active_list
)) {
2619 struct drm_i915_gem_object
*obj
;
2621 obj
= list_first_entry(&ring
->active_list
,
2622 struct drm_i915_gem_object
,
2625 i915_gem_object_move_to_inactive(obj
);
2629 * Clear the execlists queue up before freeing the requests, as those
2630 * are the ones that keep the context and ringbuffer backing objects
2633 while (!list_empty(&ring
->execlist_queue
)) {
2634 struct drm_i915_gem_request
*submit_req
;
2636 submit_req
= list_first_entry(&ring
->execlist_queue
,
2637 struct drm_i915_gem_request
,
2639 list_del(&submit_req
->execlist_link
);
2641 if (submit_req
->ctx
!= ring
->default_context
)
2642 intel_lr_context_unpin(ring
, submit_req
->ctx
);
2644 i915_gem_request_unreference(submit_req
);
2648 * We must free the requests after all the corresponding objects have
2649 * been moved off active lists. Which is the same order as the normal
2650 * retire_requests function does. This is important if object hold
2651 * implicit references on things like e.g. ppgtt address spaces through
2654 while (!list_empty(&ring
->request_list
)) {
2655 struct drm_i915_gem_request
*request
;
2657 request
= list_first_entry(&ring
->request_list
,
2658 struct drm_i915_gem_request
,
2661 i915_gem_free_request(request
);
2664 /* This may not have been flushed before the reset, so clean it now */
2665 i915_gem_request_assign(&ring
->outstanding_lazy_request
, NULL
);
2668 void i915_gem_restore_fences(struct drm_device
*dev
)
2670 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2673 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2674 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2677 * Commit delayed tiling changes if we have an object still
2678 * attached to the fence, otherwise just clear the fence.
2681 i915_gem_object_update_fence(reg
->obj
, reg
,
2682 reg
->obj
->tiling_mode
);
2684 i915_gem_write_fence(dev
, i
, NULL
);
2689 void i915_gem_reset(struct drm_device
*dev
)
2691 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2692 struct intel_engine_cs
*ring
;
2696 * Before we free the objects from the requests, we need to inspect
2697 * them for finding the guilty party. As the requests only borrow
2698 * their reference to the objects, the inspection must be done first.
2700 for_each_ring(ring
, dev_priv
, i
)
2701 i915_gem_reset_ring_status(dev_priv
, ring
);
2703 for_each_ring(ring
, dev_priv
, i
)
2704 i915_gem_reset_ring_cleanup(dev_priv
, ring
);
2706 i915_gem_context_reset(dev
);
2708 i915_gem_restore_fences(dev
);
2712 * This function clears the request list as sequence numbers are passed.
2715 i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
)
2717 if (list_empty(&ring
->request_list
))
2720 WARN_ON(i915_verify_lists(ring
->dev
));
2722 /* Retire requests first as we use it above for the early return.
2723 * If we retire requests last, we may use a later seqno and so clear
2724 * the requests lists without clearing the active list, leading to
2727 while (!list_empty(&ring
->request_list
)) {
2728 struct drm_i915_gem_request
*request
;
2730 request
= list_first_entry(&ring
->request_list
,
2731 struct drm_i915_gem_request
,
2734 if (!i915_gem_request_completed(request
, true))
2737 trace_i915_gem_request_retire(request
);
2739 /* We know the GPU must have read the request to have
2740 * sent us the seqno + interrupt, so use the position
2741 * of tail of the request to update the last known position
2744 request
->ringbuf
->last_retired_head
= request
->postfix
;
2746 i915_gem_free_request(request
);
2749 /* Move any buffers on the active list that are no longer referenced
2750 * by the ringbuffer to the flushing/inactive lists as appropriate,
2751 * before we free the context associated with the requests.
2753 while (!list_empty(&ring
->active_list
)) {
2754 struct drm_i915_gem_object
*obj
;
2756 obj
= list_first_entry(&ring
->active_list
,
2757 struct drm_i915_gem_object
,
2760 if (!i915_gem_request_completed(obj
->last_read_req
, true))
2763 i915_gem_object_move_to_inactive(obj
);
2766 if (unlikely(ring
->trace_irq_req
&&
2767 i915_gem_request_completed(ring
->trace_irq_req
, true))) {
2768 ring
->irq_put(ring
);
2769 i915_gem_request_assign(&ring
->trace_irq_req
, NULL
);
2772 WARN_ON(i915_verify_lists(ring
->dev
));
2776 i915_gem_retire_requests(struct drm_device
*dev
)
2778 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2779 struct intel_engine_cs
*ring
;
2783 for_each_ring(ring
, dev_priv
, i
) {
2784 i915_gem_retire_requests_ring(ring
);
2785 idle
&= list_empty(&ring
->request_list
);
2786 if (i915
.enable_execlists
) {
2787 unsigned long flags
;
2789 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
2790 idle
&= list_empty(&ring
->execlist_queue
);
2791 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
2793 intel_execlists_retire_requests(ring
);
2798 mod_delayed_work(dev_priv
->wq
,
2799 &dev_priv
->mm
.idle_work
,
2800 msecs_to_jiffies(100));
2806 i915_gem_retire_work_handler(struct work_struct
*work
)
2808 struct drm_i915_private
*dev_priv
=
2809 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
2810 struct drm_device
*dev
= dev_priv
->dev
;
2813 /* Come back later if the device is busy... */
2815 if (mutex_trylock(&dev
->struct_mutex
)) {
2816 idle
= i915_gem_retire_requests(dev
);
2817 mutex_unlock(&dev
->struct_mutex
);
2820 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2821 round_jiffies_up_relative(HZ
));
2825 i915_gem_idle_work_handler(struct work_struct
*work
)
2827 struct drm_i915_private
*dev_priv
=
2828 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
2829 struct drm_device
*dev
= dev_priv
->dev
;
2830 struct intel_engine_cs
*ring
;
2833 for_each_ring(ring
, dev_priv
, i
)
2834 if (!list_empty(&ring
->request_list
))
2837 intel_mark_idle(dev
);
2839 if (mutex_trylock(&dev
->struct_mutex
)) {
2840 struct intel_engine_cs
*ring
;
2843 for_each_ring(ring
, dev_priv
, i
)
2844 i915_gem_batch_pool_fini(&ring
->batch_pool
);
2846 mutex_unlock(&dev
->struct_mutex
);
2851 * Ensures that an object will eventually get non-busy by flushing any required
2852 * write domains, emitting any outstanding lazy request and retiring and
2853 * completed requests.
2856 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2858 struct intel_engine_cs
*ring
;
2862 ring
= i915_gem_request_get_ring(obj
->last_read_req
);
2864 ret
= i915_gem_check_olr(obj
->last_read_req
);
2868 i915_gem_retire_requests_ring(ring
);
2875 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2876 * @DRM_IOCTL_ARGS: standard ioctl arguments
2878 * Returns 0 if successful, else an error is returned with the remaining time in
2879 * the timeout parameter.
2880 * -ETIME: object is still busy after timeout
2881 * -ERESTARTSYS: signal interrupted the wait
2882 * -ENONENT: object doesn't exist
2883 * Also possible, but rare:
2884 * -EAGAIN: GPU wedged
2886 * -ENODEV: Internal IRQ fail
2887 * -E?: The add request failed
2889 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2890 * non-zero timeout parameter the wait ioctl will wait for the given number of
2891 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2892 * without holding struct_mutex the object may become re-busied before this
2893 * function completes. A similar but shorter * race condition exists in the busy
2897 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2899 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2900 struct drm_i915_gem_wait
*args
= data
;
2901 struct drm_i915_gem_object
*obj
;
2902 struct drm_i915_gem_request
*req
;
2903 unsigned reset_counter
;
2906 if (args
->flags
!= 0)
2909 ret
= i915_mutex_lock_interruptible(dev
);
2913 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2914 if (&obj
->base
== NULL
) {
2915 mutex_unlock(&dev
->struct_mutex
);
2919 /* Need to make sure the object gets inactive eventually. */
2920 ret
= i915_gem_object_flush_active(obj
);
2924 if (!obj
->active
|| !obj
->last_read_req
)
2927 req
= obj
->last_read_req
;
2929 /* Do this after OLR check to make sure we make forward progress polling
2930 * on this IOCTL with a timeout == 0 (like busy ioctl)
2932 if (args
->timeout_ns
== 0) {
2937 drm_gem_object_unreference(&obj
->base
);
2938 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
2939 i915_gem_request_reference(req
);
2940 mutex_unlock(&dev
->struct_mutex
);
2942 ret
= __i915_wait_request(req
, reset_counter
, true,
2943 args
->timeout_ns
> 0 ? &args
->timeout_ns
: NULL
,
2945 i915_gem_request_unreference__unlocked(req
);
2949 drm_gem_object_unreference(&obj
->base
);
2950 mutex_unlock(&dev
->struct_mutex
);
2955 * i915_gem_object_sync - sync an object to a ring.
2957 * @obj: object which may be in use on another ring.
2958 * @to: ring we wish to use the object on. May be NULL.
2960 * This code is meant to abstract object synchronization with the GPU.
2961 * Calling with NULL implies synchronizing the object with the CPU
2962 * rather than a particular GPU ring.
2964 * Returns 0 if successful, else propagates up the lower layer error.
2967 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2968 struct intel_engine_cs
*to
)
2970 struct intel_engine_cs
*from
;
2974 from
= i915_gem_request_get_ring(obj
->last_read_req
);
2976 if (from
== NULL
|| to
== from
)
2979 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2980 return i915_gem_object_wait_rendering(obj
, false);
2982 idx
= intel_ring_sync_index(from
, to
);
2984 seqno
= i915_gem_request_get_seqno(obj
->last_read_req
);
2985 /* Optimization: Avoid semaphore sync when we are sure we already
2986 * waited for an object with higher seqno */
2987 if (seqno
<= from
->semaphore
.sync_seqno
[idx
])
2990 ret
= i915_gem_check_olr(obj
->last_read_req
);
2994 trace_i915_gem_ring_sync_to(from
, to
, obj
->last_read_req
);
2995 ret
= to
->semaphore
.sync_to(to
, from
, seqno
);
2997 /* We use last_read_req because sync_to()
2998 * might have just caused seqno wrap under
3001 from
->semaphore
.sync_seqno
[idx
] =
3002 i915_gem_request_get_seqno(obj
->last_read_req
);
3007 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
3009 u32 old_write_domain
, old_read_domains
;
3011 /* Force a pagefault for domain tracking on next user access */
3012 i915_gem_release_mmap(obj
);
3014 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3017 /* Wait for any direct GTT access to complete */
3020 old_read_domains
= obj
->base
.read_domains
;
3021 old_write_domain
= obj
->base
.write_domain
;
3023 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
3024 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
3026 trace_i915_gem_object_change_domain(obj
,
3031 int i915_vma_unbind(struct i915_vma
*vma
)
3033 struct drm_i915_gem_object
*obj
= vma
->obj
;
3034 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3037 if (list_empty(&vma
->vma_link
))
3040 if (!drm_mm_node_allocated(&vma
->node
)) {
3041 i915_gem_vma_destroy(vma
);
3048 BUG_ON(obj
->pages
== NULL
);
3050 ret
= i915_gem_object_finish_gpu(obj
);
3053 /* Continue on if we fail due to EIO, the GPU is hung so we
3054 * should be safe and we need to cleanup or else we might
3055 * cause memory corruption through use-after-free.
3058 if (i915_is_ggtt(vma
->vm
) &&
3059 vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3060 i915_gem_object_finish_gtt(obj
);
3062 /* release the fence reg _after_ flushing */
3063 ret
= i915_gem_object_put_fence(obj
);
3068 trace_i915_vma_unbind(vma
);
3070 vma
->unbind_vma(vma
);
3072 list_del_init(&vma
->mm_list
);
3073 if (i915_is_ggtt(vma
->vm
)) {
3074 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3075 obj
->map_and_fenceable
= false;
3076 } else if (vma
->ggtt_view
.pages
) {
3077 sg_free_table(vma
->ggtt_view
.pages
);
3078 kfree(vma
->ggtt_view
.pages
);
3079 vma
->ggtt_view
.pages
= NULL
;
3083 drm_mm_remove_node(&vma
->node
);
3084 i915_gem_vma_destroy(vma
);
3086 /* Since the unbound list is global, only move to that list if
3087 * no more VMAs exist. */
3088 if (list_empty(&obj
->vma_list
)) {
3089 /* Throw away the active reference before
3090 * moving to the unbound list. */
3091 i915_gem_object_retire(obj
);
3093 i915_gem_gtt_finish_object(obj
);
3094 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
3097 /* And finally now the object is completely decoupled from this vma,
3098 * we can drop its hold on the backing storage and allow it to be
3099 * reaped by the shrinker.
3101 i915_gem_object_unpin_pages(obj
);
3106 int i915_gpu_idle(struct drm_device
*dev
)
3108 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3109 struct intel_engine_cs
*ring
;
3112 /* Flush everything onto the inactive list. */
3113 for_each_ring(ring
, dev_priv
, i
) {
3114 if (!i915
.enable_execlists
) {
3115 ret
= i915_switch_context(ring
, ring
->default_context
);
3120 ret
= intel_ring_idle(ring
);
3128 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
3129 struct drm_i915_gem_object
*obj
)
3131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3133 int fence_pitch_shift
;
3135 if (INTEL_INFO(dev
)->gen
>= 6) {
3136 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
3137 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
3139 fence_reg
= FENCE_REG_965_0
;
3140 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
3143 fence_reg
+= reg
* 8;
3145 /* To w/a incoherency with non-atomic 64-bit register updates,
3146 * we split the 64-bit update into two 32-bit writes. In order
3147 * for a partial fence not to be evaluated between writes, we
3148 * precede the update with write to turn off the fence register,
3149 * and only enable the fence as the last step.
3151 * For extra levels of paranoia, we make sure each step lands
3152 * before applying the next step.
3154 I915_WRITE(fence_reg
, 0);
3155 POSTING_READ(fence_reg
);
3158 u32 size
= i915_gem_obj_ggtt_size(obj
);
3161 /* Adjust fence size to match tiled area */
3162 if (obj
->tiling_mode
!= I915_TILING_NONE
) {
3163 uint32_t row_size
= obj
->stride
*
3164 (obj
->tiling_mode
== I915_TILING_Y
? 32 : 8);
3165 size
= (size
/ row_size
) * row_size
;
3168 val
= (uint64_t)((i915_gem_obj_ggtt_offset(obj
) + size
- 4096) &
3170 val
|= i915_gem_obj_ggtt_offset(obj
) & 0xfffff000;
3171 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
3172 if (obj
->tiling_mode
== I915_TILING_Y
)
3173 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
3174 val
|= I965_FENCE_REG_VALID
;
3176 I915_WRITE(fence_reg
+ 4, val
>> 32);
3177 POSTING_READ(fence_reg
+ 4);
3179 I915_WRITE(fence_reg
+ 0, val
);
3180 POSTING_READ(fence_reg
);
3182 I915_WRITE(fence_reg
+ 4, 0);
3183 POSTING_READ(fence_reg
+ 4);
3187 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
3188 struct drm_i915_gem_object
*obj
)
3190 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3194 u32 size
= i915_gem_obj_ggtt_size(obj
);
3198 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I915_FENCE_START_MASK
) ||
3199 (size
& -size
) != size
||
3200 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3201 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3202 i915_gem_obj_ggtt_offset(obj
), obj
->map_and_fenceable
, size
);
3204 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
3209 /* Note: pitch better be a power of two tile widths */
3210 pitch_val
= obj
->stride
/ tile_width
;
3211 pitch_val
= ffs(pitch_val
) - 1;
3213 val
= i915_gem_obj_ggtt_offset(obj
);
3214 if (obj
->tiling_mode
== I915_TILING_Y
)
3215 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3216 val
|= I915_FENCE_SIZE_BITS(size
);
3217 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3218 val
|= I830_FENCE_REG_VALID
;
3223 reg
= FENCE_REG_830_0
+ reg
* 4;
3225 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
3227 I915_WRITE(reg
, val
);
3231 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
3232 struct drm_i915_gem_object
*obj
)
3234 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3238 u32 size
= i915_gem_obj_ggtt_size(obj
);
3241 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I830_FENCE_START_MASK
) ||
3242 (size
& -size
) != size
||
3243 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3244 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3245 i915_gem_obj_ggtt_offset(obj
), size
);
3247 pitch_val
= obj
->stride
/ 128;
3248 pitch_val
= ffs(pitch_val
) - 1;
3250 val
= i915_gem_obj_ggtt_offset(obj
);
3251 if (obj
->tiling_mode
== I915_TILING_Y
)
3252 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3253 val
|= I830_FENCE_SIZE_BITS(size
);
3254 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3255 val
|= I830_FENCE_REG_VALID
;
3259 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
3260 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
3263 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
3265 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
3268 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
3269 struct drm_i915_gem_object
*obj
)
3271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3273 /* Ensure that all CPU reads are completed before installing a fence
3274 * and all writes before removing the fence.
3276 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
3279 WARN(obj
&& (!obj
->stride
|| !obj
->tiling_mode
),
3280 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3281 obj
->stride
, obj
->tiling_mode
);
3284 i830_write_fence_reg(dev
, reg
, obj
);
3285 else if (IS_GEN3(dev
))
3286 i915_write_fence_reg(dev
, reg
, obj
);
3287 else if (INTEL_INFO(dev
)->gen
>= 4)
3288 i965_write_fence_reg(dev
, reg
, obj
);
3290 /* And similarly be paranoid that no direct access to this region
3291 * is reordered to before the fence is installed.
3293 if (i915_gem_object_needs_mb(obj
))
3297 static inline int fence_number(struct drm_i915_private
*dev_priv
,
3298 struct drm_i915_fence_reg
*fence
)
3300 return fence
- dev_priv
->fence_regs
;
3303 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
3304 struct drm_i915_fence_reg
*fence
,
3307 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3308 int reg
= fence_number(dev_priv
, fence
);
3310 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
3313 obj
->fence_reg
= reg
;
3315 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
3317 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3319 list_del_init(&fence
->lru_list
);
3321 obj
->fence_dirty
= false;
3325 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
3327 if (obj
->last_fenced_req
) {
3328 int ret
= i915_wait_request(obj
->last_fenced_req
);
3332 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
3339 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
3341 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3342 struct drm_i915_fence_reg
*fence
;
3345 ret
= i915_gem_object_wait_fence(obj
);
3349 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
3352 fence
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3354 if (WARN_ON(fence
->pin_count
))
3357 i915_gem_object_fence_lost(obj
);
3358 i915_gem_object_update_fence(obj
, fence
, false);
3363 static struct drm_i915_fence_reg
*
3364 i915_find_fence_reg(struct drm_device
*dev
)
3366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3367 struct drm_i915_fence_reg
*reg
, *avail
;
3370 /* First try to find a free reg */
3372 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
3373 reg
= &dev_priv
->fence_regs
[i
];
3377 if (!reg
->pin_count
)
3384 /* None available, try to steal one or wait for a user to finish */
3385 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
3393 /* Wait for completion of pending flips which consume fences */
3394 if (intel_has_pending_fb_unpin(dev
))
3395 return ERR_PTR(-EAGAIN
);
3397 return ERR_PTR(-EDEADLK
);
3401 * i915_gem_object_get_fence - set up fencing for an object
3402 * @obj: object to map through a fence reg
3404 * When mapping objects through the GTT, userspace wants to be able to write
3405 * to them without having to worry about swizzling if the object is tiled.
3406 * This function walks the fence regs looking for a free one for @obj,
3407 * stealing one if it can't find any.
3409 * It then sets up the reg based on the object's properties: address, pitch
3410 * and tiling format.
3412 * For an untiled surface, this removes any existing fence.
3415 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
3417 struct drm_device
*dev
= obj
->base
.dev
;
3418 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3419 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
3420 struct drm_i915_fence_reg
*reg
;
3423 /* Have we updated the tiling parameters upon the object and so
3424 * will need to serialise the write to the associated fence register?
3426 if (obj
->fence_dirty
) {
3427 ret
= i915_gem_object_wait_fence(obj
);
3432 /* Just update our place in the LRU if our fence is getting reused. */
3433 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
3434 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3435 if (!obj
->fence_dirty
) {
3436 list_move_tail(®
->lru_list
,
3437 &dev_priv
->mm
.fence_list
);
3440 } else if (enable
) {
3441 if (WARN_ON(!obj
->map_and_fenceable
))
3444 reg
= i915_find_fence_reg(dev
);
3446 return PTR_ERR(reg
);
3449 struct drm_i915_gem_object
*old
= reg
->obj
;
3451 ret
= i915_gem_object_wait_fence(old
);
3455 i915_gem_object_fence_lost(old
);
3460 i915_gem_object_update_fence(obj
, reg
, enable
);
3465 static bool i915_gem_valid_gtt_space(struct i915_vma
*vma
,
3466 unsigned long cache_level
)
3468 struct drm_mm_node
*gtt_space
= &vma
->node
;
3469 struct drm_mm_node
*other
;
3472 * On some machines we have to be careful when putting differing types
3473 * of snoopable memory together to avoid the prefetcher crossing memory
3474 * domains and dying. During vm initialisation, we decide whether or not
3475 * these constraints apply and set the drm_mm.color_adjust
3478 if (vma
->vm
->mm
.color_adjust
== NULL
)
3481 if (!drm_mm_node_allocated(gtt_space
))
3484 if (list_empty(>t_space
->node_list
))
3487 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3488 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3491 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3492 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3499 * Finds free space in the GTT aperture and binds the object there.
3501 static struct i915_vma
*
3502 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3503 struct i915_address_space
*vm
,
3504 const struct i915_ggtt_view
*ggtt_view
,
3508 struct drm_device
*dev
= obj
->base
.dev
;
3509 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3510 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
3511 unsigned long start
=
3512 flags
& PIN_OFFSET_BIAS
? flags
& PIN_OFFSET_MASK
: 0;
3514 flags
& PIN_MAPPABLE
? dev_priv
->gtt
.mappable_end
: vm
->total
;
3515 struct i915_vma
*vma
;
3518 if(WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
3519 return ERR_PTR(-EINVAL
);
3521 fence_size
= i915_gem_get_gtt_size(dev
,
3524 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3526 obj
->tiling_mode
, true);
3527 unfenced_alignment
=
3528 i915_gem_get_gtt_alignment(dev
,
3530 obj
->tiling_mode
, false);
3533 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3535 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3536 DRM_DEBUG("Invalid object alignment requested %u\n", alignment
);
3537 return ERR_PTR(-EINVAL
);
3540 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3542 /* If the object is bigger than the entire aperture, reject it early
3543 * before evicting everything in a vain attempt to find space.
3545 if (obj
->base
.size
> end
) {
3546 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3548 flags
& PIN_MAPPABLE
? "mappable" : "total",
3550 return ERR_PTR(-E2BIG
);
3553 ret
= i915_gem_object_get_pages(obj
);
3555 return ERR_PTR(ret
);
3557 i915_gem_object_pin_pages(obj
);
3559 vma
= ggtt_view
? i915_gem_obj_lookup_or_create_ggtt_vma(obj
, ggtt_view
) :
3560 i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3566 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3570 DRM_MM_SEARCH_DEFAULT
,
3571 DRM_MM_CREATE_DEFAULT
);
3573 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3582 if (WARN_ON(!i915_gem_valid_gtt_space(vma
, obj
->cache_level
))) {
3584 goto err_remove_node
;
3587 ret
= i915_gem_gtt_prepare_object(obj
);
3589 goto err_remove_node
;
3591 trace_i915_vma_bind(vma
, flags
);
3592 ret
= i915_vma_bind(vma
, obj
->cache_level
,
3593 flags
& PIN_GLOBAL
? GLOBAL_BIND
: 0);
3595 goto err_finish_gtt
;
3597 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3598 list_add_tail(&vma
->mm_list
, &vm
->inactive_list
);
3603 i915_gem_gtt_finish_object(obj
);
3605 drm_mm_remove_node(&vma
->node
);
3607 i915_gem_vma_destroy(vma
);
3610 i915_gem_object_unpin_pages(obj
);
3615 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3618 /* If we don't have a page list set up, then we're not pinned
3619 * to GPU, and we can ignore the cache flush because it'll happen
3620 * again at bind time.
3622 if (obj
->pages
== NULL
)
3626 * Stolen memory is always coherent with the GPU as it is explicitly
3627 * marked as wc by the system, or the system is cache-coherent.
3629 if (obj
->stolen
|| obj
->phys_handle
)
3632 /* If the GPU is snooping the contents of the CPU cache,
3633 * we do not need to manually clear the CPU cache lines. However,
3634 * the caches are only snooped when the render cache is
3635 * flushed/invalidated. As we always have to emit invalidations
3636 * and flushes when moving into and out of the RENDER domain, correct
3637 * snooping behaviour occurs naturally as the result of our domain
3640 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
)) {
3641 obj
->cache_dirty
= true;
3645 trace_i915_gem_object_clflush(obj
);
3646 drm_clflush_sg(obj
->pages
);
3647 obj
->cache_dirty
= false;
3652 /** Flushes the GTT write domain for the object if it's dirty. */
3654 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3656 uint32_t old_write_domain
;
3658 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3661 /* No actual flushing is required for the GTT write domain. Writes
3662 * to it immediately go to main memory as far as we know, so there's
3663 * no chipset flush. It also doesn't land in render cache.
3665 * However, we do have to enforce the order so that all writes through
3666 * the GTT land before any writes to the device, such as updates to
3671 old_write_domain
= obj
->base
.write_domain
;
3672 obj
->base
.write_domain
= 0;
3674 intel_fb_obj_flush(obj
, false);
3676 trace_i915_gem_object_change_domain(obj
,
3677 obj
->base
.read_domains
,
3681 /** Flushes the CPU write domain for the object if it's dirty. */
3683 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3685 uint32_t old_write_domain
;
3687 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3690 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
3691 i915_gem_chipset_flush(obj
->base
.dev
);
3693 old_write_domain
= obj
->base
.write_domain
;
3694 obj
->base
.write_domain
= 0;
3696 intel_fb_obj_flush(obj
, false);
3698 trace_i915_gem_object_change_domain(obj
,
3699 obj
->base
.read_domains
,
3704 * Moves a single object to the GTT read, and possibly write domain.
3706 * This function returns when the move is complete, including waiting on
3710 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3712 uint32_t old_write_domain
, old_read_domains
;
3713 struct i915_vma
*vma
;
3716 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3719 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3723 i915_gem_object_retire(obj
);
3725 /* Flush and acquire obj->pages so that we are coherent through
3726 * direct access in memory with previous cached writes through
3727 * shmemfs and that our cache domain tracking remains valid.
3728 * For example, if the obj->filp was moved to swap without us
3729 * being notified and releasing the pages, we would mistakenly
3730 * continue to assume that the obj remained out of the CPU cached
3733 ret
= i915_gem_object_get_pages(obj
);
3737 i915_gem_object_flush_cpu_write_domain(obj
);
3739 /* Serialise direct access to this object with the barriers for
3740 * coherent writes from the GPU, by effectively invalidating the
3741 * GTT domain upon first access.
3743 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3746 old_write_domain
= obj
->base
.write_domain
;
3747 old_read_domains
= obj
->base
.read_domains
;
3749 /* It should now be out of any other write domains, and we can update
3750 * the domain values for our changes.
3752 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3753 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3755 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3756 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3761 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_GTT
);
3763 trace_i915_gem_object_change_domain(obj
,
3767 /* And bump the LRU for this access */
3768 vma
= i915_gem_obj_to_ggtt(obj
);
3769 if (vma
&& drm_mm_node_allocated(&vma
->node
) && !obj
->active
)
3770 list_move_tail(&vma
->mm_list
,
3771 &to_i915(obj
->base
.dev
)->gtt
.base
.inactive_list
);
3776 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3777 enum i915_cache_level cache_level
)
3779 struct drm_device
*dev
= obj
->base
.dev
;
3780 struct i915_vma
*vma
, *next
;
3783 if (obj
->cache_level
== cache_level
)
3786 if (i915_gem_obj_is_pinned(obj
)) {
3787 DRM_DEBUG("can not change the cache level of pinned objects\n");
3791 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
3792 if (!i915_gem_valid_gtt_space(vma
, cache_level
)) {
3793 ret
= i915_vma_unbind(vma
);
3799 if (i915_gem_obj_bound_any(obj
)) {
3800 ret
= i915_gem_object_finish_gpu(obj
);
3804 i915_gem_object_finish_gtt(obj
);
3806 /* Before SandyBridge, you could not use tiling or fence
3807 * registers with snooped memory, so relinquish any fences
3808 * currently pointing to our region in the aperture.
3810 if (INTEL_INFO(dev
)->gen
< 6) {
3811 ret
= i915_gem_object_put_fence(obj
);
3816 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3817 if (drm_mm_node_allocated(&vma
->node
)) {
3818 ret
= i915_vma_bind(vma
, cache_level
,
3819 vma
->bound
& GLOBAL_BIND
);
3825 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3826 vma
->node
.color
= cache_level
;
3827 obj
->cache_level
= cache_level
;
3829 if (obj
->cache_dirty
&&
3830 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
3831 cpu_write_needs_clflush(obj
)) {
3832 if (i915_gem_clflush_object(obj
, true))
3833 i915_gem_chipset_flush(obj
->base
.dev
);
3839 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3840 struct drm_file
*file
)
3842 struct drm_i915_gem_caching
*args
= data
;
3843 struct drm_i915_gem_object
*obj
;
3846 ret
= i915_mutex_lock_interruptible(dev
);
3850 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3851 if (&obj
->base
== NULL
) {
3856 switch (obj
->cache_level
) {
3857 case I915_CACHE_LLC
:
3858 case I915_CACHE_L3_LLC
:
3859 args
->caching
= I915_CACHING_CACHED
;
3863 args
->caching
= I915_CACHING_DISPLAY
;
3867 args
->caching
= I915_CACHING_NONE
;
3871 drm_gem_object_unreference(&obj
->base
);
3873 mutex_unlock(&dev
->struct_mutex
);
3877 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3878 struct drm_file
*file
)
3880 struct drm_i915_gem_caching
*args
= data
;
3881 struct drm_i915_gem_object
*obj
;
3882 enum i915_cache_level level
;
3885 switch (args
->caching
) {
3886 case I915_CACHING_NONE
:
3887 level
= I915_CACHE_NONE
;
3889 case I915_CACHING_CACHED
:
3890 level
= I915_CACHE_LLC
;
3892 case I915_CACHING_DISPLAY
:
3893 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
3899 ret
= i915_mutex_lock_interruptible(dev
);
3903 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3904 if (&obj
->base
== NULL
) {
3909 ret
= i915_gem_object_set_cache_level(obj
, level
);
3911 drm_gem_object_unreference(&obj
->base
);
3913 mutex_unlock(&dev
->struct_mutex
);
3917 static bool is_pin_display(struct drm_i915_gem_object
*obj
)
3919 struct i915_vma
*vma
;
3921 vma
= i915_gem_obj_to_ggtt(obj
);
3925 /* There are 2 sources that pin objects:
3926 * 1. The display engine (scanouts, sprites, cursors);
3927 * 2. Reservations for execbuffer;
3929 * We can ignore reservations as we hold the struct_mutex and
3930 * are only called outside of the reservation path.
3932 return vma
->pin_count
;
3936 * Prepare buffer for display plane (scanout, cursors, etc).
3937 * Can be called from an uninterruptible phase (modesetting) and allows
3938 * any flushes to be pipelined (for pageflips).
3941 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3943 struct intel_engine_cs
*pipelined
,
3944 const struct i915_ggtt_view
*view
)
3946 u32 old_read_domains
, old_write_domain
;
3947 bool was_pin_display
;
3950 if (pipelined
!= i915_gem_request_get_ring(obj
->last_read_req
)) {
3951 ret
= i915_gem_object_sync(obj
, pipelined
);
3956 /* Mark the pin_display early so that we account for the
3957 * display coherency whilst setting up the cache domains.
3959 was_pin_display
= obj
->pin_display
;
3960 obj
->pin_display
= true;
3962 /* The display engine is not coherent with the LLC cache on gen6. As
3963 * a result, we make sure that the pinning that is about to occur is
3964 * done with uncached PTEs. This is lowest common denominator for all
3967 * However for gen6+, we could do better by using the GFDT bit instead
3968 * of uncaching, which would allow us to flush all the LLC-cached data
3969 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3971 ret
= i915_gem_object_set_cache_level(obj
,
3972 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
3974 goto err_unpin_display
;
3976 /* As the user may map the buffer once pinned in the display plane
3977 * (e.g. libkms for the bootup splash), we have to ensure that we
3978 * always use map_and_fenceable for all scanout buffers.
3980 ret
= i915_gem_object_ggtt_pin(obj
, view
, alignment
,
3981 view
->type
== I915_GGTT_VIEW_NORMAL
?
3984 goto err_unpin_display
;
3986 i915_gem_object_flush_cpu_write_domain(obj
);
3988 old_write_domain
= obj
->base
.write_domain
;
3989 old_read_domains
= obj
->base
.read_domains
;
3991 /* It should now be out of any other write domains, and we can update
3992 * the domain values for our changes.
3994 obj
->base
.write_domain
= 0;
3995 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3997 trace_i915_gem_object_change_domain(obj
,
4004 WARN_ON(was_pin_display
!= is_pin_display(obj
));
4005 obj
->pin_display
= was_pin_display
;
4010 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
4011 const struct i915_ggtt_view
*view
)
4013 i915_gem_object_ggtt_unpin_view(obj
, view
);
4015 obj
->pin_display
= is_pin_display(obj
);
4019 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
4023 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
4026 ret
= i915_gem_object_wait_rendering(obj
, false);
4030 /* Ensure that we invalidate the GPU's caches and TLBs. */
4031 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
4036 * Moves a single object to the CPU read, and possibly write domain.
4038 * This function returns when the move is complete, including waiting on
4042 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
4044 uint32_t old_write_domain
, old_read_domains
;
4047 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
4050 ret
= i915_gem_object_wait_rendering(obj
, !write
);
4054 i915_gem_object_retire(obj
);
4055 i915_gem_object_flush_gtt_write_domain(obj
);
4057 old_write_domain
= obj
->base
.write_domain
;
4058 old_read_domains
= obj
->base
.read_domains
;
4060 /* Flush the CPU cache if it's still invalid. */
4061 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
4062 i915_gem_clflush_object(obj
, false);
4064 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
4067 /* It should now be out of any other write domains, and we can update
4068 * the domain values for our changes.
4070 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
4072 /* If we're writing through the CPU, then the GPU read domains will
4073 * need to be invalidated at next use.
4076 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4077 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4081 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_CPU
);
4083 trace_i915_gem_object_change_domain(obj
,
4090 /* Throttle our rendering by waiting until the ring has completed our requests
4091 * emitted over 20 msec ago.
4093 * Note that if we were to use the current jiffies each time around the loop,
4094 * we wouldn't escape the function with any frames outstanding if the time to
4095 * render a frame was over 20ms.
4097 * This should get us reasonable parallelism between CPU and GPU but also
4098 * relatively low latency when blocking on a particular request to finish.
4101 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
4103 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4104 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4105 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
4106 struct drm_i915_gem_request
*request
, *target
= NULL
;
4107 unsigned reset_counter
;
4110 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
4114 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
4118 spin_lock(&file_priv
->mm
.lock
);
4119 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
4120 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
4125 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
4127 i915_gem_request_reference(target
);
4128 spin_unlock(&file_priv
->mm
.lock
);
4133 ret
= __i915_wait_request(target
, reset_counter
, true, NULL
, NULL
);
4135 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
4137 i915_gem_request_unreference__unlocked(target
);
4143 i915_vma_misplaced(struct i915_vma
*vma
, uint32_t alignment
, uint64_t flags
)
4145 struct drm_i915_gem_object
*obj
= vma
->obj
;
4148 vma
->node
.start
& (alignment
- 1))
4151 if (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)
4154 if (flags
& PIN_OFFSET_BIAS
&&
4155 vma
->node
.start
< (flags
& PIN_OFFSET_MASK
))
4162 i915_gem_object_do_pin(struct drm_i915_gem_object
*obj
,
4163 struct i915_address_space
*vm
,
4164 const struct i915_ggtt_view
*ggtt_view
,
4168 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4169 struct i915_vma
*vma
;
4173 if (WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
))
4176 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
4179 if (WARN_ON((flags
& (PIN_MAPPABLE
| PIN_GLOBAL
)) == PIN_MAPPABLE
))
4182 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
4185 vma
= ggtt_view
? i915_gem_obj_to_ggtt_view(obj
, ggtt_view
) :
4186 i915_gem_obj_to_vma(obj
, vm
);
4189 return PTR_ERR(vma
);
4192 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
4195 if (i915_vma_misplaced(vma
, alignment
, flags
)) {
4196 unsigned long offset
;
4197 offset
= ggtt_view
? i915_gem_obj_ggtt_offset_view(obj
, ggtt_view
) :
4198 i915_gem_obj_offset(obj
, vm
);
4199 WARN(vma
->pin_count
,
4200 "bo is already pinned in %s with incorrect alignment:"
4201 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4202 " obj->map_and_fenceable=%d\n",
4203 ggtt_view
? "ggtt" : "ppgtt",
4206 !!(flags
& PIN_MAPPABLE
),
4207 obj
->map_and_fenceable
);
4208 ret
= i915_vma_unbind(vma
);
4216 bound
= vma
? vma
->bound
: 0;
4217 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
4218 /* In true PPGTT, bind has possibly changed PDEs, which
4219 * means we must do a context switch before the GPU can
4220 * accurately read some of the VMAs.
4222 vma
= i915_gem_object_bind_to_vm(obj
, vm
, ggtt_view
, alignment
,
4225 return PTR_ERR(vma
);
4228 if (flags
& PIN_GLOBAL
&& !(vma
->bound
& GLOBAL_BIND
)) {
4229 ret
= i915_vma_bind(vma
, obj
->cache_level
, GLOBAL_BIND
);
4234 if ((bound
^ vma
->bound
) & GLOBAL_BIND
) {
4235 bool mappable
, fenceable
;
4236 u32 fence_size
, fence_alignment
;
4238 fence_size
= i915_gem_get_gtt_size(obj
->base
.dev
,
4241 fence_alignment
= i915_gem_get_gtt_alignment(obj
->base
.dev
,
4246 fenceable
= (vma
->node
.size
== fence_size
&&
4247 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
4249 mappable
= (vma
->node
.start
+ fence_size
<=
4250 dev_priv
->gtt
.mappable_end
);
4252 obj
->map_and_fenceable
= mappable
&& fenceable
;
4255 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
4258 if (flags
& PIN_MAPPABLE
)
4259 obj
->pin_mappable
|= true;
4265 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
4266 struct i915_address_space
*vm
,
4270 return i915_gem_object_do_pin(obj
, vm
,
4271 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
,
4276 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
4277 const struct i915_ggtt_view
*view
,
4281 if (WARN_ONCE(!view
, "no view specified"))
4284 return i915_gem_object_do_pin(obj
, i915_obj_to_ggtt(obj
), view
,
4285 alignment
, flags
| PIN_GLOBAL
);
4289 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
4290 const struct i915_ggtt_view
*view
)
4292 struct i915_vma
*vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
4295 WARN_ON(vma
->pin_count
== 0);
4296 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj
, view
));
4298 if (--vma
->pin_count
== 0 && view
->type
== I915_GGTT_VIEW_NORMAL
)
4299 obj
->pin_mappable
= false;
4303 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
4305 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4306 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4307 struct i915_vma
*ggtt_vma
= i915_gem_obj_to_ggtt(obj
);
4309 WARN_ON(!ggtt_vma
||
4310 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
>
4311 ggtt_vma
->pin_count
);
4312 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
4319 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
4321 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4322 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4323 WARN_ON(dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
<= 0);
4324 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
4329 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4330 struct drm_file
*file
)
4332 struct drm_i915_gem_busy
*args
= data
;
4333 struct drm_i915_gem_object
*obj
;
4336 ret
= i915_mutex_lock_interruptible(dev
);
4340 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4341 if (&obj
->base
== NULL
) {
4346 /* Count all active objects as busy, even if they are currently not used
4347 * by the gpu. Users of this interface expect objects to eventually
4348 * become non-busy without any further actions, therefore emit any
4349 * necessary flushes here.
4351 ret
= i915_gem_object_flush_active(obj
);
4353 args
->busy
= obj
->active
;
4354 if (obj
->last_read_req
) {
4355 struct intel_engine_cs
*ring
;
4356 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
4357 ring
= i915_gem_request_get_ring(obj
->last_read_req
);
4358 args
->busy
|= intel_ring_flag(ring
) << 16;
4361 drm_gem_object_unreference(&obj
->base
);
4363 mutex_unlock(&dev
->struct_mutex
);
4368 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4369 struct drm_file
*file_priv
)
4371 return i915_gem_ring_throttle(dev
, file_priv
);
4375 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4376 struct drm_file
*file_priv
)
4378 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4379 struct drm_i915_gem_madvise
*args
= data
;
4380 struct drm_i915_gem_object
*obj
;
4383 switch (args
->madv
) {
4384 case I915_MADV_DONTNEED
:
4385 case I915_MADV_WILLNEED
:
4391 ret
= i915_mutex_lock_interruptible(dev
);
4395 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
4396 if (&obj
->base
== NULL
) {
4401 if (i915_gem_obj_is_pinned(obj
)) {
4407 obj
->tiling_mode
!= I915_TILING_NONE
&&
4408 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
4409 if (obj
->madv
== I915_MADV_WILLNEED
)
4410 i915_gem_object_unpin_pages(obj
);
4411 if (args
->madv
== I915_MADV_WILLNEED
)
4412 i915_gem_object_pin_pages(obj
);
4415 if (obj
->madv
!= __I915_MADV_PURGED
)
4416 obj
->madv
= args
->madv
;
4418 /* if the object is no longer attached, discard its backing storage */
4419 if (obj
->madv
== I915_MADV_DONTNEED
&& obj
->pages
== NULL
)
4420 i915_gem_object_truncate(obj
);
4422 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4425 drm_gem_object_unreference(&obj
->base
);
4427 mutex_unlock(&dev
->struct_mutex
);
4431 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4432 const struct drm_i915_gem_object_ops
*ops
)
4434 INIT_LIST_HEAD(&obj
->global_list
);
4435 INIT_LIST_HEAD(&obj
->ring_list
);
4436 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4437 INIT_LIST_HEAD(&obj
->vma_list
);
4438 INIT_LIST_HEAD(&obj
->batch_pool_link
);
4442 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4443 obj
->madv
= I915_MADV_WILLNEED
;
4445 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4448 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4449 .get_pages
= i915_gem_object_get_pages_gtt
,
4450 .put_pages
= i915_gem_object_put_pages_gtt
,
4453 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
4456 struct drm_i915_gem_object
*obj
;
4457 struct address_space
*mapping
;
4460 obj
= i915_gem_object_alloc(dev
);
4464 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4465 i915_gem_object_free(obj
);
4469 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4470 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4471 /* 965gm cannot relocate objects above 4GiB. */
4472 mask
&= ~__GFP_HIGHMEM
;
4473 mask
|= __GFP_DMA32
;
4476 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4477 mapping_set_gfp_mask(mapping
, mask
);
4479 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4481 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4482 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4485 /* On some devices, we can have the GPU use the LLC (the CPU
4486 * cache) for about a 10% performance improvement
4487 * compared to uncached. Graphics requests other than
4488 * display scanout are coherent with the CPU in
4489 * accessing this cache. This means in this mode we
4490 * don't need to clflush on the CPU side, and on the
4491 * GPU side we only need to flush internal caches to
4492 * get data visible to the CPU.
4494 * However, we maintain the display planes as UC, and so
4495 * need to rebind when first used as such.
4497 obj
->cache_level
= I915_CACHE_LLC
;
4499 obj
->cache_level
= I915_CACHE_NONE
;
4501 trace_i915_gem_object_create(obj
);
4506 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4508 /* If we are the last user of the backing storage (be it shmemfs
4509 * pages or stolen etc), we know that the pages are going to be
4510 * immediately released. In this case, we can then skip copying
4511 * back the contents from the GPU.
4514 if (obj
->madv
!= I915_MADV_WILLNEED
)
4517 if (obj
->base
.filp
== NULL
)
4520 /* At first glance, this looks racy, but then again so would be
4521 * userspace racing mmap against close. However, the first external
4522 * reference to the filp can only be obtained through the
4523 * i915_gem_mmap_ioctl() which safeguards us against the user
4524 * acquiring such a reference whilst we are in the middle of
4525 * freeing the object.
4527 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4530 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4532 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4533 struct drm_device
*dev
= obj
->base
.dev
;
4534 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4535 struct i915_vma
*vma
, *next
;
4537 intel_runtime_pm_get(dev_priv
);
4539 trace_i915_gem_object_destroy(obj
);
4541 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4545 ret
= i915_vma_unbind(vma
);
4546 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4547 bool was_interruptible
;
4549 was_interruptible
= dev_priv
->mm
.interruptible
;
4550 dev_priv
->mm
.interruptible
= false;
4552 WARN_ON(i915_vma_unbind(vma
));
4554 dev_priv
->mm
.interruptible
= was_interruptible
;
4558 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4559 * before progressing. */
4561 i915_gem_object_unpin_pages(obj
);
4563 WARN_ON(obj
->frontbuffer_bits
);
4565 if (obj
->pages
&& obj
->madv
== I915_MADV_WILLNEED
&&
4566 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
&&
4567 obj
->tiling_mode
!= I915_TILING_NONE
)
4568 i915_gem_object_unpin_pages(obj
);
4570 if (WARN_ON(obj
->pages_pin_count
))
4571 obj
->pages_pin_count
= 0;
4572 if (discard_backing_storage(obj
))
4573 obj
->madv
= I915_MADV_DONTNEED
;
4574 i915_gem_object_put_pages(obj
);
4575 i915_gem_object_free_mmap_offset(obj
);
4579 if (obj
->base
.import_attach
)
4580 drm_prime_gem_destroy(&obj
->base
, NULL
);
4582 if (obj
->ops
->release
)
4583 obj
->ops
->release(obj
);
4585 drm_gem_object_release(&obj
->base
);
4586 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4589 i915_gem_object_free(obj
);
4591 intel_runtime_pm_put(dev_priv
);
4594 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4595 struct i915_address_space
*vm
)
4597 struct i915_vma
*vma
;
4598 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
4599 if (i915_is_ggtt(vma
->vm
) &&
4600 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
4608 struct i915_vma
*i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
4609 const struct i915_ggtt_view
*view
)
4611 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
4612 struct i915_vma
*vma
;
4614 if (WARN_ONCE(!view
, "no view specified"))
4615 return ERR_PTR(-EINVAL
);
4617 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4618 if (vma
->vm
== ggtt
&&
4619 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
4624 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4626 struct i915_address_space
*vm
= NULL
;
4627 WARN_ON(vma
->node
.allocated
);
4629 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4630 if (!list_empty(&vma
->exec_list
))
4635 if (!i915_is_ggtt(vm
))
4636 i915_ppgtt_put(i915_vm_to_ppgtt(vm
));
4638 list_del(&vma
->vma_link
);
4640 kmem_cache_free(to_i915(vma
->obj
->base
.dev
)->vmas
, vma
);
4644 i915_gem_stop_ringbuffers(struct drm_device
*dev
)
4646 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4647 struct intel_engine_cs
*ring
;
4650 for_each_ring(ring
, dev_priv
, i
)
4651 dev_priv
->gt
.stop_ring(ring
);
4655 i915_gem_suspend(struct drm_device
*dev
)
4657 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4660 mutex_lock(&dev
->struct_mutex
);
4661 ret
= i915_gpu_idle(dev
);
4665 i915_gem_retire_requests(dev
);
4667 i915_gem_stop_ringbuffers(dev
);
4668 mutex_unlock(&dev
->struct_mutex
);
4670 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
4671 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4672 flush_delayed_work(&dev_priv
->mm
.idle_work
);
4674 /* Assert that we sucessfully flushed all the work and
4675 * reset the GPU back to its idle, low power state.
4677 WARN_ON(dev_priv
->mm
.busy
);
4682 mutex_unlock(&dev
->struct_mutex
);
4686 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
)
4688 struct drm_device
*dev
= ring
->dev
;
4689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4690 u32 reg_base
= GEN7_L3LOG_BASE
+ (slice
* 0x200);
4691 u32
*remap_info
= dev_priv
->l3_parity
.remap_info
[slice
];
4694 if (!HAS_L3_DPF(dev
) || !remap_info
)
4697 ret
= intel_ring_begin(ring
, GEN7_L3LOG_SIZE
/ 4 * 3);
4702 * Note: We do not worry about the concurrent register cacheline hang
4703 * here because no other code should access these registers other than
4704 * at initialization time.
4706 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
4707 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
4708 intel_ring_emit(ring
, reg_base
+ i
);
4709 intel_ring_emit(ring
, remap_info
[i
/4]);
4712 intel_ring_advance(ring
);
4717 void i915_gem_init_swizzling(struct drm_device
*dev
)
4719 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4721 if (INTEL_INFO(dev
)->gen
< 5 ||
4722 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4725 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4726 DISP_TILE_SURFACE_SWIZZLING
);
4731 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4733 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4734 else if (IS_GEN7(dev
))
4735 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4736 else if (IS_GEN8(dev
))
4737 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4743 intel_enable_blt(struct drm_device
*dev
)
4748 /* The blitter was dysfunctional on early prototypes */
4749 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
4750 DRM_INFO("BLT not supported on this pre-production hardware;"
4751 " graphics performance will be degraded.\n");
4758 static void init_unused_ring(struct drm_device
*dev
, u32 base
)
4760 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4762 I915_WRITE(RING_CTL(base
), 0);
4763 I915_WRITE(RING_HEAD(base
), 0);
4764 I915_WRITE(RING_TAIL(base
), 0);
4765 I915_WRITE(RING_START(base
), 0);
4768 static void init_unused_rings(struct drm_device
*dev
)
4771 init_unused_ring(dev
, PRB1_BASE
);
4772 init_unused_ring(dev
, SRB0_BASE
);
4773 init_unused_ring(dev
, SRB1_BASE
);
4774 init_unused_ring(dev
, SRB2_BASE
);
4775 init_unused_ring(dev
, SRB3_BASE
);
4776 } else if (IS_GEN2(dev
)) {
4777 init_unused_ring(dev
, SRB0_BASE
);
4778 init_unused_ring(dev
, SRB1_BASE
);
4779 } else if (IS_GEN3(dev
)) {
4780 init_unused_ring(dev
, PRB1_BASE
);
4781 init_unused_ring(dev
, PRB2_BASE
);
4785 int i915_gem_init_rings(struct drm_device
*dev
)
4787 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4790 ret
= intel_init_render_ring_buffer(dev
);
4795 ret
= intel_init_bsd_ring_buffer(dev
);
4797 goto cleanup_render_ring
;
4800 if (intel_enable_blt(dev
)) {
4801 ret
= intel_init_blt_ring_buffer(dev
);
4803 goto cleanup_bsd_ring
;
4806 if (HAS_VEBOX(dev
)) {
4807 ret
= intel_init_vebox_ring_buffer(dev
);
4809 goto cleanup_blt_ring
;
4812 if (HAS_BSD2(dev
)) {
4813 ret
= intel_init_bsd2_ring_buffer(dev
);
4815 goto cleanup_vebox_ring
;
4818 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
4820 goto cleanup_bsd2_ring
;
4825 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS2
]);
4827 intel_cleanup_ring_buffer(&dev_priv
->ring
[VECS
]);
4829 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
4831 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
4832 cleanup_render_ring
:
4833 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
4839 i915_gem_init_hw(struct drm_device
*dev
)
4841 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4842 struct intel_engine_cs
*ring
;
4845 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
4848 /* Double layer security blanket, see i915_gem_init() */
4849 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4851 if (dev_priv
->ellc_size
)
4852 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4854 if (IS_HASWELL(dev
))
4855 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
4856 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
4858 if (HAS_PCH_NOP(dev
)) {
4859 if (IS_IVYBRIDGE(dev
)) {
4860 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4861 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4862 I915_WRITE(GEN7_MSG_CTL
, temp
);
4863 } else if (INTEL_INFO(dev
)->gen
>= 7) {
4864 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
4865 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
4866 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
4870 i915_gem_init_swizzling(dev
);
4873 * At least 830 can leave some of the unused rings
4874 * "active" (ie. head != tail) after resume which
4875 * will prevent c3 entry. Makes sure all unused rings
4878 init_unused_rings(dev
);
4880 for_each_ring(ring
, dev_priv
, i
) {
4881 ret
= ring
->init_hw(ring
);
4886 for (i
= 0; i
< NUM_L3_SLICES(dev
); i
++)
4887 i915_gem_l3_remap(&dev_priv
->ring
[RCS
], i
);
4889 ret
= i915_ppgtt_init_hw(dev
);
4890 if (ret
&& ret
!= -EIO
) {
4891 DRM_ERROR("PPGTT enable failed %d\n", ret
);
4892 i915_gem_cleanup_ringbuffer(dev
);
4895 ret
= i915_gem_context_enable(dev_priv
);
4896 if (ret
&& ret
!= -EIO
) {
4897 DRM_ERROR("Context enable failed %d\n", ret
);
4898 i915_gem_cleanup_ringbuffer(dev
);
4904 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4908 int i915_gem_init(struct drm_device
*dev
)
4910 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4913 i915
.enable_execlists
= intel_sanitize_enable_execlists(dev
,
4914 i915
.enable_execlists
);
4916 mutex_lock(&dev
->struct_mutex
);
4918 if (IS_VALLEYVIEW(dev
)) {
4919 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4920 I915_WRITE(VLV_GTLC_WAKE_CTRL
, VLV_GTLC_ALLOWWAKEREQ
);
4921 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS
) &
4922 VLV_GTLC_ALLOWWAKEACK
), 10))
4923 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4926 if (!i915
.enable_execlists
) {
4927 dev_priv
->gt
.execbuf_submit
= i915_gem_ringbuffer_submission
;
4928 dev_priv
->gt
.init_rings
= i915_gem_init_rings
;
4929 dev_priv
->gt
.cleanup_ring
= intel_cleanup_ring_buffer
;
4930 dev_priv
->gt
.stop_ring
= intel_stop_ring_buffer
;
4932 dev_priv
->gt
.execbuf_submit
= intel_execlists_submission
;
4933 dev_priv
->gt
.init_rings
= intel_logical_rings_init
;
4934 dev_priv
->gt
.cleanup_ring
= intel_logical_ring_cleanup
;
4935 dev_priv
->gt
.stop_ring
= intel_logical_ring_stop
;
4938 /* This is just a security blanket to placate dragons.
4939 * On some systems, we very sporadically observe that the first TLBs
4940 * used by the CS may be stale, despite us poking the TLB reset. If
4941 * we hold the forcewake during initialisation these problems
4942 * just magically go away.
4944 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4946 ret
= i915_gem_init_userptr(dev
);
4950 i915_gem_init_global_gtt(dev
);
4952 ret
= i915_gem_context_init(dev
);
4956 ret
= dev_priv
->gt
.init_rings(dev
);
4960 ret
= i915_gem_init_hw(dev
);
4962 /* Allow ring initialisation to fail by marking the GPU as
4963 * wedged. But we only want to do this where the GPU is angry,
4964 * for all other failure, such as an allocation failure, bail.
4966 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4967 atomic_set_mask(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
4972 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4973 mutex_unlock(&dev
->struct_mutex
);
4979 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4981 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4982 struct intel_engine_cs
*ring
;
4985 for_each_ring(ring
, dev_priv
, i
)
4986 dev_priv
->gt
.cleanup_ring(ring
);
4990 init_ring_lists(struct intel_engine_cs
*ring
)
4992 INIT_LIST_HEAD(&ring
->active_list
);
4993 INIT_LIST_HEAD(&ring
->request_list
);
4996 void i915_init_vm(struct drm_i915_private
*dev_priv
,
4997 struct i915_address_space
*vm
)
4999 if (!i915_is_ggtt(vm
))
5000 drm_mm_init(&vm
->mm
, vm
->start
, vm
->total
);
5001 vm
->dev
= dev_priv
->dev
;
5002 INIT_LIST_HEAD(&vm
->active_list
);
5003 INIT_LIST_HEAD(&vm
->inactive_list
);
5004 INIT_LIST_HEAD(&vm
->global_link
);
5005 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
5009 i915_gem_load(struct drm_device
*dev
)
5011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5015 kmem_cache_create("i915_gem_object",
5016 sizeof(struct drm_i915_gem_object
), 0,
5020 kmem_cache_create("i915_gem_vma",
5021 sizeof(struct i915_vma
), 0,
5024 dev_priv
->requests
=
5025 kmem_cache_create("i915_gem_request",
5026 sizeof(struct drm_i915_gem_request
), 0,
5030 INIT_LIST_HEAD(&dev_priv
->vm_list
);
5031 i915_init_vm(dev_priv
, &dev_priv
->gtt
.base
);
5033 INIT_LIST_HEAD(&dev_priv
->context_list
);
5034 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
5035 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
5036 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5037 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
5038 init_ring_lists(&dev_priv
->ring
[i
]);
5039 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
5040 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
5041 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
5042 i915_gem_retire_work_handler
);
5043 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
5044 i915_gem_idle_work_handler
);
5045 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
5047 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
5049 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
))
5050 dev_priv
->num_fence_regs
= 32;
5051 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
5052 dev_priv
->num_fence_regs
= 16;
5054 dev_priv
->num_fence_regs
= 8;
5056 if (intel_vgpu_active(dev
))
5057 dev_priv
->num_fence_regs
=
5058 I915_READ(vgtif_reg(avail_rs
.fence_num
));
5060 /* Initialize fence registers to zero */
5061 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5062 i915_gem_restore_fences(dev
);
5064 i915_gem_detect_bit_6_swizzle(dev
);
5065 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
5067 dev_priv
->mm
.interruptible
= true;
5069 i915_gem_shrinker_init(dev_priv
);
5071 mutex_init(&dev_priv
->fb_tracking
.lock
);
5074 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5076 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5078 /* Clean up our request list when the client is going away, so that
5079 * later retire_requests won't dereference our soon-to-be-gone
5082 spin_lock(&file_priv
->mm
.lock
);
5083 while (!list_empty(&file_priv
->mm
.request_list
)) {
5084 struct drm_i915_gem_request
*request
;
5086 request
= list_first_entry(&file_priv
->mm
.request_list
,
5087 struct drm_i915_gem_request
,
5089 list_del(&request
->client_list
);
5090 request
->file_priv
= NULL
;
5092 spin_unlock(&file_priv
->mm
.lock
);
5094 if (!list_empty(&file_priv
->rps_boost
)) {
5095 mutex_lock(&to_i915(dev
)->rps
.hw_lock
);
5096 list_del(&file_priv
->rps_boost
);
5097 mutex_unlock(&to_i915(dev
)->rps
.hw_lock
);
5101 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
5103 struct drm_i915_file_private
*file_priv
;
5106 DRM_DEBUG_DRIVER("\n");
5108 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
5112 file
->driver_priv
= file_priv
;
5113 file_priv
->dev_priv
= dev
->dev_private
;
5114 file_priv
->file
= file
;
5115 INIT_LIST_HEAD(&file_priv
->rps_boost
);
5117 spin_lock_init(&file_priv
->mm
.lock
);
5118 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
5120 ret
= i915_gem_context_open(dev
, file
);
5128 * i915_gem_track_fb - update frontbuffer tracking
5129 * old: current GEM buffer for the frontbuffer slots
5130 * new: new GEM buffer for the frontbuffer slots
5131 * frontbuffer_bits: bitmask of frontbuffer slots
5133 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5134 * from @old and setting them in @new. Both @old and @new can be NULL.
5136 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
5137 struct drm_i915_gem_object
*new,
5138 unsigned frontbuffer_bits
)
5141 WARN_ON(!mutex_is_locked(&old
->base
.dev
->struct_mutex
));
5142 WARN_ON(!(old
->frontbuffer_bits
& frontbuffer_bits
));
5143 old
->frontbuffer_bits
&= ~frontbuffer_bits
;
5147 WARN_ON(!mutex_is_locked(&new->base
.dev
->struct_mutex
));
5148 WARN_ON(new->frontbuffer_bits
& frontbuffer_bits
);
5149 new->frontbuffer_bits
|= frontbuffer_bits
;
5153 /* All the new VM stuff */
5155 i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
5156 struct i915_address_space
*vm
)
5158 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5159 struct i915_vma
*vma
;
5161 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5163 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5164 if (i915_is_ggtt(vma
->vm
) &&
5165 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5168 return vma
->node
.start
;
5171 WARN(1, "%s vma for this object not found.\n",
5172 i915_is_ggtt(vm
) ? "global" : "ppgtt");
5177 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
5178 const struct i915_ggtt_view
*view
)
5180 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5181 struct i915_vma
*vma
;
5183 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5184 if (vma
->vm
== ggtt
&&
5185 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
5186 return vma
->node
.start
;
5188 WARN(1, "global vma for this object not found.\n");
5192 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
5193 struct i915_address_space
*vm
)
5195 struct i915_vma
*vma
;
5197 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5198 if (i915_is_ggtt(vma
->vm
) &&
5199 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5201 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
5208 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
5209 const struct i915_ggtt_view
*view
)
5211 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5212 struct i915_vma
*vma
;
5214 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5215 if (vma
->vm
== ggtt
&&
5216 i915_ggtt_view_equal(&vma
->ggtt_view
, view
) &&
5217 drm_mm_node_allocated(&vma
->node
))
5223 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
5225 struct i915_vma
*vma
;
5227 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5228 if (drm_mm_node_allocated(&vma
->node
))
5234 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
5235 struct i915_address_space
*vm
)
5237 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5238 struct i915_vma
*vma
;
5240 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5242 BUG_ON(list_empty(&o
->vma_list
));
5244 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5245 if (i915_is_ggtt(vma
->vm
) &&
5246 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5249 return vma
->node
.size
;
5254 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
)
5256 struct i915_vma
*vma
;
5257 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
5258 if (i915_is_ggtt(vma
->vm
) &&
5259 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5261 if (vma
->pin_count
> 0)