2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/oom.h>
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
,
44 static __must_check
int
45 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
48 i915_gem_object_retire(struct drm_i915_gem_object
*obj
);
50 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
51 struct drm_i915_gem_object
*obj
);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
53 struct drm_i915_fence_reg
*fence
,
56 static unsigned long i915_gem_shrinker_count(struct shrinker
*shrinker
,
57 struct shrink_control
*sc
);
58 static unsigned long i915_gem_shrinker_scan(struct shrinker
*shrinker
,
59 struct shrink_control
*sc
);
60 static int i915_gem_shrinker_oom(struct notifier_block
*nb
,
63 static unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
65 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
66 enum i915_cache_level level
)
68 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
71 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
73 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
76 return obj
->pin_display
;
79 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
82 i915_gem_release_mmap(obj
);
84 /* As we do not have an associated fence register, we will force
85 * a tiling change if we ever need to acquire one.
87 obj
->fence_dirty
= false;
88 obj
->fence_reg
= I915_FENCE_REG_NONE
;
91 /* some bookkeeping */
92 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
95 spin_lock(&dev_priv
->mm
.object_stat_lock
);
96 dev_priv
->mm
.object_count
++;
97 dev_priv
->mm
.object_memory
+= size
;
98 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
101 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
104 spin_lock(&dev_priv
->mm
.object_stat_lock
);
105 dev_priv
->mm
.object_count
--;
106 dev_priv
->mm
.object_memory
-= size
;
107 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
111 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
115 #define EXIT_COND (!i915_reset_in_progress(error) || \
116 i915_terminally_wedged(error))
121 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
122 * userspace. If it takes that long something really bad is going on and
123 * we should simply try to bail out and fail as gracefully as possible.
125 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
129 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
131 } else if (ret
< 0) {
139 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
144 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
148 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
152 WARN_ON(i915_verify_lists(dev
));
157 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
159 return i915_gem_obj_bound_any(obj
) && !obj
->active
;
163 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
164 struct drm_file
*file
)
166 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
167 struct drm_i915_gem_get_aperture
*args
= data
;
168 struct drm_i915_gem_object
*obj
;
172 mutex_lock(&dev
->struct_mutex
);
173 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
174 if (i915_gem_obj_is_pinned(obj
))
175 pinned
+= i915_gem_obj_ggtt_size(obj
);
176 mutex_unlock(&dev
->struct_mutex
);
178 args
->aper_size
= dev_priv
->gtt
.base
.total
;
179 args
->aper_available_size
= args
->aper_size
- pinned
;
185 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
187 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
188 char *vaddr
= obj
->phys_handle
->vaddr
;
190 struct scatterlist
*sg
;
193 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
196 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
200 page
= shmem_read_mapping_page(mapping
, i
);
202 return PTR_ERR(page
);
204 src
= kmap_atomic(page
);
205 memcpy(vaddr
, src
, PAGE_SIZE
);
206 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
209 page_cache_release(page
);
213 i915_gem_chipset_flush(obj
->base
.dev
);
215 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
219 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
226 sg
->length
= obj
->base
.size
;
228 sg_dma_address(sg
) = obj
->phys_handle
->busaddr
;
229 sg_dma_len(sg
) = obj
->base
.size
;
232 obj
->has_dma_mapping
= true;
237 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
)
241 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
243 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
245 /* In the event of a disaster, abandon all caches and
248 WARN_ON(ret
!= -EIO
);
249 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
252 if (obj
->madv
== I915_MADV_DONTNEED
)
256 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
257 char *vaddr
= obj
->phys_handle
->vaddr
;
260 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
264 page
= shmem_read_mapping_page(mapping
, i
);
268 dst
= kmap_atomic(page
);
269 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
270 memcpy(dst
, vaddr
, PAGE_SIZE
);
273 set_page_dirty(page
);
274 if (obj
->madv
== I915_MADV_WILLNEED
)
275 mark_page_accessed(page
);
276 page_cache_release(page
);
282 sg_free_table(obj
->pages
);
285 obj
->has_dma_mapping
= false;
289 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
291 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
294 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
295 .get_pages
= i915_gem_object_get_pages_phys
,
296 .put_pages
= i915_gem_object_put_pages_phys
,
297 .release
= i915_gem_object_release_phys
,
301 drop_pages(struct drm_i915_gem_object
*obj
)
303 struct i915_vma
*vma
, *next
;
306 drm_gem_object_reference(&obj
->base
);
307 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
)
308 if (i915_vma_unbind(vma
))
311 ret
= i915_gem_object_put_pages(obj
);
312 drm_gem_object_unreference(&obj
->base
);
318 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
321 drm_dma_handle_t
*phys
;
324 if (obj
->phys_handle
) {
325 if ((unsigned long)obj
->phys_handle
->vaddr
& (align
-1))
331 if (obj
->madv
!= I915_MADV_WILLNEED
)
334 if (obj
->base
.filp
== NULL
)
337 ret
= drop_pages(obj
);
341 /* create a new object */
342 phys
= drm_pci_alloc(obj
->base
.dev
, obj
->base
.size
, align
);
346 obj
->phys_handle
= phys
;
347 obj
->ops
= &i915_gem_phys_ops
;
349 return i915_gem_object_get_pages(obj
);
353 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
354 struct drm_i915_gem_pwrite
*args
,
355 struct drm_file
*file_priv
)
357 struct drm_device
*dev
= obj
->base
.dev
;
358 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
359 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
362 /* We manually control the domain here and pretend that it
363 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
365 ret
= i915_gem_object_wait_rendering(obj
, false);
369 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
370 unsigned long unwritten
;
372 /* The physical object once assigned is fixed for the lifetime
373 * of the obj, so we can safely drop the lock and continue
376 mutex_unlock(&dev
->struct_mutex
);
377 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
378 mutex_lock(&dev
->struct_mutex
);
383 drm_clflush_virt_range(vaddr
, args
->size
);
384 i915_gem_chipset_flush(dev
);
388 void *i915_gem_object_alloc(struct drm_device
*dev
)
390 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
391 return kmem_cache_zalloc(dev_priv
->slab
, GFP_KERNEL
);
394 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
396 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
397 kmem_cache_free(dev_priv
->slab
, obj
);
401 i915_gem_create(struct drm_file
*file
,
402 struct drm_device
*dev
,
407 struct drm_i915_gem_object
*obj
;
411 size
= roundup(size
, PAGE_SIZE
);
415 /* Allocate the new object */
416 obj
= i915_gem_alloc_object(dev
, size
);
420 obj
->base
.dumb
= dumb
;
421 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
422 /* drop reference from allocate - handle holds it now */
423 drm_gem_object_unreference_unlocked(&obj
->base
);
432 i915_gem_dumb_create(struct drm_file
*file
,
433 struct drm_device
*dev
,
434 struct drm_mode_create_dumb
*args
)
436 /* have to work out size/pitch and return them */
437 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
438 args
->size
= args
->pitch
* args
->height
;
439 return i915_gem_create(file
, dev
,
440 args
->size
, true, &args
->handle
);
444 * Creates a new mm object and returns a handle to it.
447 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
448 struct drm_file
*file
)
450 struct drm_i915_gem_create
*args
= data
;
452 return i915_gem_create(file
, dev
,
453 args
->size
, false, &args
->handle
);
457 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
458 const char *gpu_vaddr
, int gpu_offset
,
461 int ret
, cpu_offset
= 0;
464 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
465 int this_length
= min(cacheline_end
- gpu_offset
, length
);
466 int swizzled_gpu_offset
= gpu_offset
^ 64;
468 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
469 gpu_vaddr
+ swizzled_gpu_offset
,
474 cpu_offset
+= this_length
;
475 gpu_offset
+= this_length
;
476 length
-= this_length
;
483 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
484 const char __user
*cpu_vaddr
,
487 int ret
, cpu_offset
= 0;
490 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
491 int this_length
= min(cacheline_end
- gpu_offset
, length
);
492 int swizzled_gpu_offset
= gpu_offset
^ 64;
494 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
495 cpu_vaddr
+ cpu_offset
,
500 cpu_offset
+= this_length
;
501 gpu_offset
+= this_length
;
502 length
-= this_length
;
509 * Pins the specified object's pages and synchronizes the object with
510 * GPU accesses. Sets needs_clflush to non-zero if the caller should
511 * flush the object from the CPU cache.
513 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
523 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
524 /* If we're not in the cpu read domain, set ourself into the gtt
525 * read domain and manually flush cachelines (if required). This
526 * optimizes for the case when the gpu will dirty the data
527 * anyway again before the next pread happens. */
528 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
530 ret
= i915_gem_object_wait_rendering(obj
, true);
534 i915_gem_object_retire(obj
);
537 ret
= i915_gem_object_get_pages(obj
);
541 i915_gem_object_pin_pages(obj
);
546 /* Per-page copy function for the shmem pread fastpath.
547 * Flushes invalid cachelines before reading the target if
548 * needs_clflush is set. */
550 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
551 char __user
*user_data
,
552 bool page_do_bit17_swizzling
, bool needs_clflush
)
557 if (unlikely(page_do_bit17_swizzling
))
560 vaddr
= kmap_atomic(page
);
562 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
564 ret
= __copy_to_user_inatomic(user_data
,
565 vaddr
+ shmem_page_offset
,
567 kunmap_atomic(vaddr
);
569 return ret
? -EFAULT
: 0;
573 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
576 if (unlikely(swizzled
)) {
577 unsigned long start
= (unsigned long) addr
;
578 unsigned long end
= (unsigned long) addr
+ length
;
580 /* For swizzling simply ensure that we always flush both
581 * channels. Lame, but simple and it works. Swizzled
582 * pwrite/pread is far from a hotpath - current userspace
583 * doesn't use it at all. */
584 start
= round_down(start
, 128);
585 end
= round_up(end
, 128);
587 drm_clflush_virt_range((void *)start
, end
- start
);
589 drm_clflush_virt_range(addr
, length
);
594 /* Only difference to the fast-path function is that this can handle bit17
595 * and uses non-atomic copy and kmap functions. */
597 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
598 char __user
*user_data
,
599 bool page_do_bit17_swizzling
, bool needs_clflush
)
606 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
608 page_do_bit17_swizzling
);
610 if (page_do_bit17_swizzling
)
611 ret
= __copy_to_user_swizzled(user_data
,
612 vaddr
, shmem_page_offset
,
615 ret
= __copy_to_user(user_data
,
616 vaddr
+ shmem_page_offset
,
620 return ret
? - EFAULT
: 0;
624 i915_gem_shmem_pread(struct drm_device
*dev
,
625 struct drm_i915_gem_object
*obj
,
626 struct drm_i915_gem_pread
*args
,
627 struct drm_file
*file
)
629 char __user
*user_data
;
632 int shmem_page_offset
, page_length
, ret
= 0;
633 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
635 int needs_clflush
= 0;
636 struct sg_page_iter sg_iter
;
638 user_data
= to_user_ptr(args
->data_ptr
);
641 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
643 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
647 offset
= args
->offset
;
649 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
650 offset
>> PAGE_SHIFT
) {
651 struct page
*page
= sg_page_iter_page(&sg_iter
);
656 /* Operation in this page
658 * shmem_page_offset = offset within page in shmem file
659 * page_length = bytes to copy for this page
661 shmem_page_offset
= offset_in_page(offset
);
662 page_length
= remain
;
663 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
664 page_length
= PAGE_SIZE
- shmem_page_offset
;
666 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
667 (page_to_phys(page
) & (1 << 17)) != 0;
669 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
670 user_data
, page_do_bit17_swizzling
,
675 mutex_unlock(&dev
->struct_mutex
);
677 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
678 ret
= fault_in_multipages_writeable(user_data
, remain
);
679 /* Userspace is tricking us, but we've already clobbered
680 * its pages with the prefault and promised to write the
681 * data up to the first fault. Hence ignore any errors
682 * and just continue. */
687 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
688 user_data
, page_do_bit17_swizzling
,
691 mutex_lock(&dev
->struct_mutex
);
697 remain
-= page_length
;
698 user_data
+= page_length
;
699 offset
+= page_length
;
703 i915_gem_object_unpin_pages(obj
);
709 * Reads data from the object referenced by handle.
711 * On error, the contents of *data are undefined.
714 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
715 struct drm_file
*file
)
717 struct drm_i915_gem_pread
*args
= data
;
718 struct drm_i915_gem_object
*obj
;
724 if (!access_ok(VERIFY_WRITE
,
725 to_user_ptr(args
->data_ptr
),
729 ret
= i915_mutex_lock_interruptible(dev
);
733 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
734 if (&obj
->base
== NULL
) {
739 /* Bounds check source. */
740 if (args
->offset
> obj
->base
.size
||
741 args
->size
> obj
->base
.size
- args
->offset
) {
746 /* prime objects have no backing filp to GEM pread/pwrite
749 if (!obj
->base
.filp
) {
754 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
756 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
759 drm_gem_object_unreference(&obj
->base
);
761 mutex_unlock(&dev
->struct_mutex
);
765 /* This is the fast write path which cannot handle
766 * page faults in the source data
770 fast_user_write(struct io_mapping
*mapping
,
771 loff_t page_base
, int page_offset
,
772 char __user
*user_data
,
775 void __iomem
*vaddr_atomic
;
777 unsigned long unwritten
;
779 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
780 /* We can use the cpu mem copy function because this is X86. */
781 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
782 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
784 io_mapping_unmap_atomic(vaddr_atomic
);
789 * This is the fast pwrite path, where we copy the data directly from the
790 * user into the GTT, uncached.
793 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
794 struct drm_i915_gem_object
*obj
,
795 struct drm_i915_gem_pwrite
*args
,
796 struct drm_file
*file
)
798 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
800 loff_t offset
, page_base
;
801 char __user
*user_data
;
802 int page_offset
, page_length
, ret
;
804 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
808 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
812 ret
= i915_gem_object_put_fence(obj
);
816 user_data
= to_user_ptr(args
->data_ptr
);
819 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
822 /* Operation in this page
824 * page_base = page offset within aperture
825 * page_offset = offset within page
826 * page_length = bytes to copy for this page
828 page_base
= offset
& PAGE_MASK
;
829 page_offset
= offset_in_page(offset
);
830 page_length
= remain
;
831 if ((page_offset
+ remain
) > PAGE_SIZE
)
832 page_length
= PAGE_SIZE
- page_offset
;
834 /* If we get a fault while copying data, then (presumably) our
835 * source page isn't available. Return the error and we'll
836 * retry in the slow path.
838 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
839 page_offset
, user_data
, page_length
)) {
844 remain
-= page_length
;
845 user_data
+= page_length
;
846 offset
+= page_length
;
850 i915_gem_object_ggtt_unpin(obj
);
855 /* Per-page copy function for the shmem pwrite fastpath.
856 * Flushes invalid cachelines before writing to the target if
857 * needs_clflush_before is set and flushes out any written cachelines after
858 * writing if needs_clflush is set. */
860 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
861 char __user
*user_data
,
862 bool page_do_bit17_swizzling
,
863 bool needs_clflush_before
,
864 bool needs_clflush_after
)
869 if (unlikely(page_do_bit17_swizzling
))
872 vaddr
= kmap_atomic(page
);
873 if (needs_clflush_before
)
874 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
876 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
877 user_data
, page_length
);
878 if (needs_clflush_after
)
879 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
881 kunmap_atomic(vaddr
);
883 return ret
? -EFAULT
: 0;
886 /* Only difference to the fast-path function is that this can handle bit17
887 * and uses non-atomic copy and kmap functions. */
889 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
890 char __user
*user_data
,
891 bool page_do_bit17_swizzling
,
892 bool needs_clflush_before
,
893 bool needs_clflush_after
)
899 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
900 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
902 page_do_bit17_swizzling
);
903 if (page_do_bit17_swizzling
)
904 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
908 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
911 if (needs_clflush_after
)
912 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
914 page_do_bit17_swizzling
);
917 return ret
? -EFAULT
: 0;
921 i915_gem_shmem_pwrite(struct drm_device
*dev
,
922 struct drm_i915_gem_object
*obj
,
923 struct drm_i915_gem_pwrite
*args
,
924 struct drm_file
*file
)
928 char __user
*user_data
;
929 int shmem_page_offset
, page_length
, ret
= 0;
930 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
931 int hit_slowpath
= 0;
932 int needs_clflush_after
= 0;
933 int needs_clflush_before
= 0;
934 struct sg_page_iter sg_iter
;
936 user_data
= to_user_ptr(args
->data_ptr
);
939 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
941 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
942 /* If we're not in the cpu write domain, set ourself into the gtt
943 * write domain and manually flush cachelines (if required). This
944 * optimizes for the case when the gpu will use the data
945 * right away and we therefore have to clflush anyway. */
946 needs_clflush_after
= cpu_write_needs_clflush(obj
);
947 ret
= i915_gem_object_wait_rendering(obj
, false);
951 i915_gem_object_retire(obj
);
953 /* Same trick applies to invalidate partially written cachelines read
955 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
956 needs_clflush_before
=
957 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
959 ret
= i915_gem_object_get_pages(obj
);
963 i915_gem_object_pin_pages(obj
);
965 offset
= args
->offset
;
968 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
969 offset
>> PAGE_SHIFT
) {
970 struct page
*page
= sg_page_iter_page(&sg_iter
);
971 int partial_cacheline_write
;
976 /* Operation in this page
978 * shmem_page_offset = offset within page in shmem file
979 * page_length = bytes to copy for this page
981 shmem_page_offset
= offset_in_page(offset
);
983 page_length
= remain
;
984 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
985 page_length
= PAGE_SIZE
- shmem_page_offset
;
987 /* If we don't overwrite a cacheline completely we need to be
988 * careful to have up-to-date data by first clflushing. Don't
989 * overcomplicate things and flush the entire patch. */
990 partial_cacheline_write
= needs_clflush_before
&&
991 ((shmem_page_offset
| page_length
)
992 & (boot_cpu_data
.x86_clflush_size
- 1));
994 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
995 (page_to_phys(page
) & (1 << 17)) != 0;
997 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
998 user_data
, page_do_bit17_swizzling
,
999 partial_cacheline_write
,
1000 needs_clflush_after
);
1005 mutex_unlock(&dev
->struct_mutex
);
1006 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
1007 user_data
, page_do_bit17_swizzling
,
1008 partial_cacheline_write
,
1009 needs_clflush_after
);
1011 mutex_lock(&dev
->struct_mutex
);
1017 remain
-= page_length
;
1018 user_data
+= page_length
;
1019 offset
+= page_length
;
1023 i915_gem_object_unpin_pages(obj
);
1027 * Fixup: Flush cpu caches in case we didn't flush the dirty
1028 * cachelines in-line while writing and the object moved
1029 * out of the cpu write domain while we've dropped the lock.
1031 if (!needs_clflush_after
&&
1032 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1033 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
1034 i915_gem_chipset_flush(dev
);
1038 if (needs_clflush_after
)
1039 i915_gem_chipset_flush(dev
);
1045 * Writes data to the object referenced by handle.
1047 * On error, the contents of the buffer that were to be modified are undefined.
1050 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1051 struct drm_file
*file
)
1053 struct drm_i915_gem_pwrite
*args
= data
;
1054 struct drm_i915_gem_object
*obj
;
1057 if (args
->size
== 0)
1060 if (!access_ok(VERIFY_READ
,
1061 to_user_ptr(args
->data_ptr
),
1065 if (likely(!i915
.prefault_disable
)) {
1066 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
1072 ret
= i915_mutex_lock_interruptible(dev
);
1076 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1077 if (&obj
->base
== NULL
) {
1082 /* Bounds check destination. */
1083 if (args
->offset
> obj
->base
.size
||
1084 args
->size
> obj
->base
.size
- args
->offset
) {
1089 /* prime objects have no backing filp to GEM pread/pwrite
1092 if (!obj
->base
.filp
) {
1097 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1100 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1101 * it would end up going through the fenced access, and we'll get
1102 * different detiling behavior between reading and writing.
1103 * pread/pwrite currently are reading and writing from the CPU
1104 * perspective, requiring manual detiling by the client.
1106 if (obj
->tiling_mode
== I915_TILING_NONE
&&
1107 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
1108 cpu_write_needs_clflush(obj
)) {
1109 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1110 /* Note that the gtt paths might fail with non-page-backed user
1111 * pointers (e.g. gtt mappings when moving data between
1112 * textures). Fallback to the shmem path in that case. */
1115 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1116 if (obj
->phys_handle
)
1117 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1119 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
1123 drm_gem_object_unreference(&obj
->base
);
1125 mutex_unlock(&dev
->struct_mutex
);
1130 i915_gem_check_wedge(struct i915_gpu_error
*error
,
1133 if (i915_reset_in_progress(error
)) {
1134 /* Non-interruptible callers can't handle -EAGAIN, hence return
1135 * -EIO unconditionally for these. */
1139 /* Recovery complete, but the reset failed ... */
1140 if (i915_terminally_wedged(error
))
1144 * Check if GPU Reset is in progress - we need intel_ring_begin
1145 * to work properly to reinit the hw state while the gpu is
1146 * still marked as reset-in-progress. Handle this with a flag.
1148 if (!error
->reload_in_reset
)
1156 * Compare seqno against outstanding lazy request. Emit a request if they are
1160 i915_gem_check_olr(struct intel_engine_cs
*ring
, u32 seqno
)
1164 BUG_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
1167 if (seqno
== i915_gem_request_get_seqno(ring
->outstanding_lazy_request
))
1168 ret
= i915_add_request(ring
, NULL
);
1173 static void fake_irq(unsigned long data
)
1175 wake_up_process((struct task_struct
*)data
);
1178 static bool missed_irq(struct drm_i915_private
*dev_priv
,
1179 struct intel_engine_cs
*ring
)
1181 return test_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
1184 static bool can_wait_boost(struct drm_i915_file_private
*file_priv
)
1186 if (file_priv
== NULL
)
1189 return !atomic_xchg(&file_priv
->rps_wait_boost
, true);
1193 * __i915_wait_seqno - wait until execution of seqno has finished
1194 * @ring: the ring expected to report seqno
1196 * @reset_counter: reset sequence associated with the given seqno
1197 * @interruptible: do an interruptible wait (normally yes)
1198 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1200 * Note: It is of utmost importance that the passed in seqno and reset_counter
1201 * values have been read by the caller in an smp safe manner. Where read-side
1202 * locks are involved, it is sufficient to read the reset_counter before
1203 * unlocking the lock that protects the seqno. For lockless tricks, the
1204 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1207 * Returns 0 if the seqno was found within the alloted time. Else returns the
1208 * errno with remaining time filled in timeout argument.
1210 int __i915_wait_seqno(struct intel_engine_cs
*ring
, u32 seqno
,
1211 unsigned reset_counter
,
1214 struct drm_i915_file_private
*file_priv
)
1216 struct drm_device
*dev
= ring
->dev
;
1217 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1218 const bool irq_test_in_progress
=
1219 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_ring_flag(ring
);
1221 unsigned long timeout_expire
;
1225 WARN(!intel_irqs_enabled(dev_priv
), "IRQs disabled");
1227 if (i915_seqno_passed(ring
->get_seqno(ring
, true), seqno
))
1230 timeout_expire
= timeout
? jiffies
+ nsecs_to_jiffies((u64
)*timeout
) : 0;
1232 if (INTEL_INFO(dev
)->gen
>= 6 && ring
->id
== RCS
&& can_wait_boost(file_priv
)) {
1233 gen6_rps_boost(dev_priv
);
1235 mod_delayed_work(dev_priv
->wq
,
1236 &file_priv
->mm
.idle_work
,
1237 msecs_to_jiffies(100));
1240 if (!irq_test_in_progress
&& WARN_ON(!ring
->irq_get(ring
)))
1243 /* Record current time in case interrupted by signal, or wedged */
1244 trace_i915_gem_request_wait_begin(ring
, seqno
);
1245 before
= ktime_get_raw_ns();
1247 struct timer_list timer
;
1249 prepare_to_wait(&ring
->irq_queue
, &wait
,
1250 interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
);
1252 /* We need to check whether any gpu reset happened in between
1253 * the caller grabbing the seqno and now ... */
1254 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
)) {
1255 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1256 * is truely gone. */
1257 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1263 if (i915_seqno_passed(ring
->get_seqno(ring
, false), seqno
)) {
1268 if (interruptible
&& signal_pending(current
)) {
1273 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1278 timer
.function
= NULL
;
1279 if (timeout
|| missed_irq(dev_priv
, ring
)) {
1280 unsigned long expire
;
1282 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1283 expire
= missed_irq(dev_priv
, ring
) ? jiffies
+ 1 : timeout_expire
;
1284 mod_timer(&timer
, expire
);
1289 if (timer
.function
) {
1290 del_singleshot_timer_sync(&timer
);
1291 destroy_timer_on_stack(&timer
);
1294 now
= ktime_get_raw_ns();
1295 trace_i915_gem_request_wait_end(ring
, seqno
);
1297 if (!irq_test_in_progress
)
1298 ring
->irq_put(ring
);
1300 finish_wait(&ring
->irq_queue
, &wait
);
1303 s64 tres
= *timeout
- (now
- before
);
1305 *timeout
= tres
< 0 ? 0 : tres
;
1312 * Waits for a sequence number to be signaled, and cleans up the
1313 * request and object lists appropriately for that event.
1316 i915_wait_seqno(struct intel_engine_cs
*ring
, uint32_t seqno
)
1318 struct drm_device
*dev
= ring
->dev
;
1319 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1320 bool interruptible
= dev_priv
->mm
.interruptible
;
1321 unsigned reset_counter
;
1324 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1327 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1331 ret
= i915_gem_check_olr(ring
, seqno
);
1335 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1336 return __i915_wait_seqno(ring
, seqno
, reset_counter
, interruptible
,
1341 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object
*obj
)
1346 /* Manually manage the write flush as we may have not yet
1347 * retired the buffer.
1349 * Note that the last_write_req is always the earlier of
1350 * the two (read/write) requests, so if we haved successfully waited,
1351 * we know we have passed the last write.
1353 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
1359 * Ensures that all rendering to the object has completed and the object is
1360 * safe to unbind from the GTT or access from the CPU.
1362 static __must_check
int
1363 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1366 struct drm_i915_gem_request
*req
;
1367 struct intel_engine_cs
*ring
= obj
->ring
;
1371 req
= readonly
? obj
->last_write_req
: obj
->last_read_req
;
1375 seqno
= i915_gem_request_get_seqno(req
);
1376 WARN_ON(seqno
== 0);
1378 ret
= i915_wait_seqno(ring
, seqno
);
1382 return i915_gem_object_wait_rendering__tail(obj
);
1385 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1386 * as the object state may change during this call.
1388 static __must_check
int
1389 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1390 struct drm_i915_file_private
*file_priv
,
1393 struct drm_i915_gem_request
*req
;
1394 struct drm_device
*dev
= obj
->base
.dev
;
1395 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1396 struct intel_engine_cs
*ring
= obj
->ring
;
1397 unsigned reset_counter
;
1401 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1402 BUG_ON(!dev_priv
->mm
.interruptible
);
1404 req
= readonly
? obj
->last_write_req
: obj
->last_read_req
;
1408 seqno
= i915_gem_request_get_seqno(req
);
1409 WARN_ON(seqno
== 0);
1411 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1415 ret
= i915_gem_check_olr(ring
, seqno
);
1419 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1420 i915_gem_request_reference(req
);
1421 mutex_unlock(&dev
->struct_mutex
);
1422 ret
= __i915_wait_seqno(ring
, seqno
, reset_counter
, true, NULL
,
1424 mutex_lock(&dev
->struct_mutex
);
1425 i915_gem_request_unreference(req
);
1429 return i915_gem_object_wait_rendering__tail(obj
);
1433 * Called when user space prepares to use an object with the CPU, either
1434 * through the mmap ioctl's mapping or a GTT mapping.
1437 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1438 struct drm_file
*file
)
1440 struct drm_i915_gem_set_domain
*args
= data
;
1441 struct drm_i915_gem_object
*obj
;
1442 uint32_t read_domains
= args
->read_domains
;
1443 uint32_t write_domain
= args
->write_domain
;
1446 /* Only handle setting domains to types used by the CPU. */
1447 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1450 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1453 /* Having something in the write domain implies it's in the read
1454 * domain, and only that read domain. Enforce that in the request.
1456 if (write_domain
!= 0 && read_domains
!= write_domain
)
1459 ret
= i915_mutex_lock_interruptible(dev
);
1463 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1464 if (&obj
->base
== NULL
) {
1469 /* Try to flush the object off the GPU without holding the lock.
1470 * We will repeat the flush holding the lock in the normal manner
1471 * to catch cases where we are gazumped.
1473 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1479 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1480 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1482 /* Silently promote "you're not bound, there was nothing to do"
1483 * to success, since the client was just asking us to
1484 * make sure everything was done.
1489 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1493 drm_gem_object_unreference(&obj
->base
);
1495 mutex_unlock(&dev
->struct_mutex
);
1500 * Called when user space has done writes to this buffer
1503 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1504 struct drm_file
*file
)
1506 struct drm_i915_gem_sw_finish
*args
= data
;
1507 struct drm_i915_gem_object
*obj
;
1510 ret
= i915_mutex_lock_interruptible(dev
);
1514 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1515 if (&obj
->base
== NULL
) {
1520 /* Pinned buffers may be scanout, so flush the cache */
1521 if (obj
->pin_display
)
1522 i915_gem_object_flush_cpu_write_domain(obj
, true);
1524 drm_gem_object_unreference(&obj
->base
);
1526 mutex_unlock(&dev
->struct_mutex
);
1531 * Maps the contents of an object, returning the address it is mapped
1534 * While the mapping holds a reference on the contents of the object, it doesn't
1535 * imply a ref on the object itself.
1539 * DRM driver writers who look a this function as an example for how to do GEM
1540 * mmap support, please don't implement mmap support like here. The modern way
1541 * to implement DRM mmap support is with an mmap offset ioctl (like
1542 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1543 * That way debug tooling like valgrind will understand what's going on, hiding
1544 * the mmap call in a driver private ioctl will break that. The i915 driver only
1545 * does cpu mmaps this way because we didn't know better.
1548 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1549 struct drm_file
*file
)
1551 struct drm_i915_gem_mmap
*args
= data
;
1552 struct drm_gem_object
*obj
;
1555 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1559 /* prime objects have no backing filp to GEM mmap
1563 drm_gem_object_unreference_unlocked(obj
);
1567 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1568 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1570 drm_gem_object_unreference_unlocked(obj
);
1571 if (IS_ERR((void *)addr
))
1574 args
->addr_ptr
= (uint64_t) addr
;
1580 * i915_gem_fault - fault a page into the GTT
1581 * vma: VMA in question
1584 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1585 * from userspace. The fault handler takes care of binding the object to
1586 * the GTT (if needed), allocating and programming a fence register (again,
1587 * only if needed based on whether the old reg is still valid or the object
1588 * is tiled) and inserting a new PTE into the faulting process.
1590 * Note that the faulting process may involve evicting existing objects
1591 * from the GTT and/or fence registers to make room. So performance may
1592 * suffer if the GTT working set is large or there are few fence registers
1595 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1597 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1598 struct drm_device
*dev
= obj
->base
.dev
;
1599 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1600 pgoff_t page_offset
;
1603 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1605 intel_runtime_pm_get(dev_priv
);
1607 /* We don't use vmf->pgoff since that has the fake offset */
1608 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1611 ret
= i915_mutex_lock_interruptible(dev
);
1615 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1617 /* Try to flush the object off the GPU first without holding the lock.
1618 * Upon reacquiring the lock, we will perform our sanity checks and then
1619 * repeat the flush holding the lock in the normal manner to catch cases
1620 * where we are gazumped.
1622 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
1626 /* Access to snoopable pages through the GTT is incoherent. */
1627 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1632 /* Now bind it into the GTT if needed */
1633 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
);
1637 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1641 ret
= i915_gem_object_get_fence(obj
);
1645 /* Finally, remap it using the new GTT offset */
1646 pfn
= dev_priv
->gtt
.mappable_base
+ i915_gem_obj_ggtt_offset(obj
);
1649 if (!obj
->fault_mappable
) {
1650 unsigned long size
= min_t(unsigned long,
1651 vma
->vm_end
- vma
->vm_start
,
1655 for (i
= 0; i
< size
>> PAGE_SHIFT
; i
++) {
1656 ret
= vm_insert_pfn(vma
,
1657 (unsigned long)vma
->vm_start
+ i
* PAGE_SIZE
,
1663 obj
->fault_mappable
= true;
1665 ret
= vm_insert_pfn(vma
,
1666 (unsigned long)vmf
->virtual_address
,
1669 i915_gem_object_ggtt_unpin(obj
);
1671 mutex_unlock(&dev
->struct_mutex
);
1676 * We eat errors when the gpu is terminally wedged to avoid
1677 * userspace unduly crashing (gl has no provisions for mmaps to
1678 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1679 * and so needs to be reported.
1681 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1682 ret
= VM_FAULT_SIGBUS
;
1687 * EAGAIN means the gpu is hung and we'll wait for the error
1688 * handler to reset everything when re-faulting in
1689 * i915_mutex_lock_interruptible.
1696 * EBUSY is ok: this just means that another thread
1697 * already did the job.
1699 ret
= VM_FAULT_NOPAGE
;
1706 ret
= VM_FAULT_SIGBUS
;
1709 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1710 ret
= VM_FAULT_SIGBUS
;
1714 intel_runtime_pm_put(dev_priv
);
1719 * i915_gem_release_mmap - remove physical page mappings
1720 * @obj: obj in question
1722 * Preserve the reservation of the mmapping with the DRM core code, but
1723 * relinquish ownership of the pages back to the system.
1725 * It is vital that we remove the page mapping if we have mapped a tiled
1726 * object through the GTT and then lose the fence register due to
1727 * resource pressure. Similarly if the object has been moved out of the
1728 * aperture, than pages mapped into userspace must be revoked. Removing the
1729 * mapping will then trigger a page fault on the next user access, allowing
1730 * fixup by i915_gem_fault().
1733 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1735 if (!obj
->fault_mappable
)
1738 drm_vma_node_unmap(&obj
->base
.vma_node
,
1739 obj
->base
.dev
->anon_inode
->i_mapping
);
1740 obj
->fault_mappable
= false;
1744 i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
1746 struct drm_i915_gem_object
*obj
;
1748 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
1749 i915_gem_release_mmap(obj
);
1753 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1757 if (INTEL_INFO(dev
)->gen
>= 4 ||
1758 tiling_mode
== I915_TILING_NONE
)
1761 /* Previous chips need a power-of-two fence region when tiling */
1762 if (INTEL_INFO(dev
)->gen
== 3)
1763 gtt_size
= 1024*1024;
1765 gtt_size
= 512*1024;
1767 while (gtt_size
< size
)
1774 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1775 * @obj: object to check
1777 * Return the required GTT alignment for an object, taking into account
1778 * potential fence register mapping.
1781 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1782 int tiling_mode
, bool fenced
)
1785 * Minimum alignment is 4k (GTT page size), but might be greater
1786 * if a fence register is needed for the object.
1788 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1789 tiling_mode
== I915_TILING_NONE
)
1793 * Previous chips need to be aligned to the size of the smallest
1794 * fence register that can contain the object.
1796 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1799 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1801 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1804 if (drm_vma_node_has_offset(&obj
->base
.vma_node
))
1807 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1809 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1813 /* Badly fragmented mmap space? The only way we can recover
1814 * space is by destroying unwanted objects. We can't randomly release
1815 * mmap_offsets as userspace expects them to be persistent for the
1816 * lifetime of the objects. The closest we can is to release the
1817 * offsets on purgeable objects by truncating it and marking it purged,
1818 * which prevents userspace from ever using that object again.
1820 i915_gem_shrink(dev_priv
,
1821 obj
->base
.size
>> PAGE_SHIFT
,
1823 I915_SHRINK_UNBOUND
|
1824 I915_SHRINK_PURGEABLE
);
1825 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1829 i915_gem_shrink_all(dev_priv
);
1830 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1832 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
1837 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1839 drm_gem_free_mmap_offset(&obj
->base
);
1843 i915_gem_mmap_gtt(struct drm_file
*file
,
1844 struct drm_device
*dev
,
1845 uint32_t handle
, bool dumb
,
1848 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1849 struct drm_i915_gem_object
*obj
;
1852 ret
= i915_mutex_lock_interruptible(dev
);
1856 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1857 if (&obj
->base
== NULL
) {
1863 * We don't allow dumb mmaps on objects created using another
1866 WARN_ONCE(dumb
&& !(obj
->base
.dumb
|| obj
->base
.import_attach
),
1867 "Illegal dumb map of accelerated buffer.\n");
1869 if (obj
->base
.size
> dev_priv
->gtt
.mappable_end
) {
1874 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1875 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1880 ret
= i915_gem_object_create_mmap_offset(obj
);
1884 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
1887 drm_gem_object_unreference(&obj
->base
);
1889 mutex_unlock(&dev
->struct_mutex
);
1894 i915_gem_dumb_map_offset(struct drm_file
*file
,
1895 struct drm_device
*dev
,
1899 return i915_gem_mmap_gtt(file
, dev
, handle
, true, offset
);
1903 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1905 * @data: GTT mapping ioctl data
1906 * @file: GEM object info
1908 * Simply returns the fake offset to userspace so it can mmap it.
1909 * The mmap call will end up in drm_gem_mmap(), which will set things
1910 * up so we can get faults in the handler above.
1912 * The fault handler will take care of binding the object into the GTT
1913 * (since it may have been evicted to make room for something), allocating
1914 * a fence register, and mapping the appropriate aperture address into
1918 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1919 struct drm_file
*file
)
1921 struct drm_i915_gem_mmap_gtt
*args
= data
;
1923 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, false, &args
->offset
);
1927 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1929 return obj
->madv
== I915_MADV_DONTNEED
;
1932 /* Immediately discard the backing storage */
1934 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1936 i915_gem_object_free_mmap_offset(obj
);
1938 if (obj
->base
.filp
== NULL
)
1941 /* Our goal here is to return as much of the memory as
1942 * is possible back to the system as we are called from OOM.
1943 * To do this we must instruct the shmfs to drop all of its
1944 * backing pages, *now*.
1946 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
1947 obj
->madv
= __I915_MADV_PURGED
;
1950 /* Try to discard unwanted pages */
1952 i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
1954 struct address_space
*mapping
;
1956 switch (obj
->madv
) {
1957 case I915_MADV_DONTNEED
:
1958 i915_gem_object_truncate(obj
);
1959 case __I915_MADV_PURGED
:
1963 if (obj
->base
.filp
== NULL
)
1966 mapping
= file_inode(obj
->base
.filp
)->i_mapping
,
1967 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
1971 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1973 struct sg_page_iter sg_iter
;
1976 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1978 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1980 /* In the event of a disaster, abandon all caches and
1981 * hope for the best.
1983 WARN_ON(ret
!= -EIO
);
1984 i915_gem_clflush_object(obj
, true);
1985 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
1988 if (i915_gem_object_needs_bit17_swizzle(obj
))
1989 i915_gem_object_save_bit_17_swizzle(obj
);
1991 if (obj
->madv
== I915_MADV_DONTNEED
)
1994 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
1995 struct page
*page
= sg_page_iter_page(&sg_iter
);
1998 set_page_dirty(page
);
2000 if (obj
->madv
== I915_MADV_WILLNEED
)
2001 mark_page_accessed(page
);
2003 page_cache_release(page
);
2007 sg_free_table(obj
->pages
);
2012 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
2014 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2016 if (obj
->pages
== NULL
)
2019 if (obj
->pages_pin_count
)
2022 BUG_ON(i915_gem_obj_bound_any(obj
));
2024 /* ->put_pages might need to allocate memory for the bit17 swizzle
2025 * array, hence protect them from being reaped by removing them from gtt
2027 list_del(&obj
->global_list
);
2029 ops
->put_pages(obj
);
2032 i915_gem_object_invalidate(obj
);
2038 i915_gem_shrink(struct drm_i915_private
*dev_priv
,
2039 long target
, unsigned flags
)
2042 struct list_head
*list
;
2045 { &dev_priv
->mm
.unbound_list
, I915_SHRINK_UNBOUND
},
2046 { &dev_priv
->mm
.bound_list
, I915_SHRINK_BOUND
},
2049 unsigned long count
= 0;
2052 * As we may completely rewrite the (un)bound list whilst unbinding
2053 * (due to retiring requests) we have to strictly process only
2054 * one element of the list at the time, and recheck the list
2055 * on every iteration.
2057 * In particular, we must hold a reference whilst removing the
2058 * object as we may end up waiting for and/or retiring the objects.
2059 * This might release the final reference (held by the active list)
2060 * and result in the object being freed from under us. This is
2061 * similar to the precautions the eviction code must take whilst
2064 * Also note that although these lists do not hold a reference to
2065 * the object we can safely grab one here: The final object
2066 * unreferencing and the bound_list are both protected by the
2067 * dev->struct_mutex and so we won't ever be able to observe an
2068 * object on the bound_list with a reference count equals 0.
2070 for (phase
= phases
; phase
->list
; phase
++) {
2071 struct list_head still_in_list
;
2073 if ((flags
& phase
->bit
) == 0)
2076 INIT_LIST_HEAD(&still_in_list
);
2077 while (count
< target
&& !list_empty(phase
->list
)) {
2078 struct drm_i915_gem_object
*obj
;
2079 struct i915_vma
*vma
, *v
;
2081 obj
= list_first_entry(phase
->list
,
2082 typeof(*obj
), global_list
);
2083 list_move_tail(&obj
->global_list
, &still_in_list
);
2085 if (flags
& I915_SHRINK_PURGEABLE
&&
2086 !i915_gem_object_is_purgeable(obj
))
2089 drm_gem_object_reference(&obj
->base
);
2091 /* For the unbound phase, this should be a no-op! */
2092 list_for_each_entry_safe(vma
, v
,
2093 &obj
->vma_list
, vma_link
)
2094 if (i915_vma_unbind(vma
))
2097 if (i915_gem_object_put_pages(obj
) == 0)
2098 count
+= obj
->base
.size
>> PAGE_SHIFT
;
2100 drm_gem_object_unreference(&obj
->base
);
2102 list_splice(&still_in_list
, phase
->list
);
2108 static unsigned long
2109 i915_gem_shrink_all(struct drm_i915_private
*dev_priv
)
2111 i915_gem_evict_everything(dev_priv
->dev
);
2112 return i915_gem_shrink(dev_priv
, LONG_MAX
,
2113 I915_SHRINK_BOUND
| I915_SHRINK_UNBOUND
);
2117 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2119 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2121 struct address_space
*mapping
;
2122 struct sg_table
*st
;
2123 struct scatterlist
*sg
;
2124 struct sg_page_iter sg_iter
;
2126 unsigned long last_pfn
= 0; /* suppress gcc warning */
2129 /* Assert that the object is not currently in any GPU domain. As it
2130 * wasn't in the GTT, there shouldn't be any way it could have been in
2133 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2134 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2136 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2140 page_count
= obj
->base
.size
/ PAGE_SIZE
;
2141 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2146 /* Get the list of pages out of our struct file. They'll be pinned
2147 * at this point until we release them.
2149 * Fail silently without starting the shrinker
2151 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
2152 gfp
= mapping_gfp_mask(mapping
);
2153 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
2154 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
2157 for (i
= 0; i
< page_count
; i
++) {
2158 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2160 i915_gem_shrink(dev_priv
,
2163 I915_SHRINK_UNBOUND
|
2164 I915_SHRINK_PURGEABLE
);
2165 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2168 /* We've tried hard to allocate the memory by reaping
2169 * our own buffer, now let the real VM do its job and
2170 * go down in flames if truly OOM.
2172 i915_gem_shrink_all(dev_priv
);
2173 page
= shmem_read_mapping_page(mapping
, i
);
2177 #ifdef CONFIG_SWIOTLB
2178 if (swiotlb_nr_tbl()) {
2180 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2185 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
2189 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2191 sg
->length
+= PAGE_SIZE
;
2193 last_pfn
= page_to_pfn(page
);
2195 /* Check that the i965g/gm workaround works. */
2196 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2198 #ifdef CONFIG_SWIOTLB
2199 if (!swiotlb_nr_tbl())
2204 if (i915_gem_object_needs_bit17_swizzle(obj
))
2205 i915_gem_object_do_bit_17_swizzle(obj
);
2207 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
2208 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2209 i915_gem_object_pin_pages(obj
);
2215 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
2216 page_cache_release(sg_page_iter_page(&sg_iter
));
2220 /* shmemfs first checks if there is enough memory to allocate the page
2221 * and reports ENOSPC should there be insufficient, along with the usual
2222 * ENOMEM for a genuine allocation failure.
2224 * We use ENOSPC in our driver to mean that we have run out of aperture
2225 * space and so want to translate the error from shmemfs back to our
2226 * usual understanding of ENOMEM.
2228 if (PTR_ERR(page
) == -ENOSPC
)
2231 return PTR_ERR(page
);
2234 /* Ensure that the associated pages are gathered from the backing storage
2235 * and pinned into our object. i915_gem_object_get_pages() may be called
2236 * multiple times before they are released by a single call to
2237 * i915_gem_object_put_pages() - once the pages are no longer referenced
2238 * either as a result of memory pressure (reaping pages under the shrinker)
2239 * or as the object is itself released.
2242 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2244 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2245 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2251 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2252 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2256 BUG_ON(obj
->pages_pin_count
);
2258 ret
= ops
->get_pages(obj
);
2262 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2267 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
2268 struct intel_engine_cs
*ring
)
2270 struct drm_i915_gem_request
*req
= intel_ring_get_request(ring
);
2272 BUG_ON(ring
== NULL
);
2273 if (obj
->ring
!= ring
&& obj
->last_write_req
) {
2274 /* Keep the request relative to the current ring */
2275 i915_gem_request_assign(&obj
->last_write_req
, req
);
2279 /* Add a reference if we're newly entering the active list. */
2281 drm_gem_object_reference(&obj
->base
);
2285 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
2287 i915_gem_request_assign(&obj
->last_read_req
, req
);
2290 void i915_vma_move_to_active(struct i915_vma
*vma
,
2291 struct intel_engine_cs
*ring
)
2293 list_move_tail(&vma
->mm_list
, &vma
->vm
->active_list
);
2294 return i915_gem_object_move_to_active(vma
->obj
, ring
);
2298 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
2300 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2301 struct i915_address_space
*vm
;
2302 struct i915_vma
*vma
;
2304 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
2305 BUG_ON(!obj
->active
);
2307 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
2308 vma
= i915_gem_obj_to_vma(obj
, vm
);
2309 if (vma
&& !list_empty(&vma
->mm_list
))
2310 list_move_tail(&vma
->mm_list
, &vm
->inactive_list
);
2313 intel_fb_obj_flush(obj
, true);
2315 list_del_init(&obj
->ring_list
);
2318 i915_gem_request_assign(&obj
->last_read_req
, NULL
);
2319 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
2320 obj
->base
.write_domain
= 0;
2322 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
2325 drm_gem_object_unreference(&obj
->base
);
2327 WARN_ON(i915_verify_lists(dev
));
2331 i915_gem_object_retire(struct drm_i915_gem_object
*obj
)
2333 struct intel_engine_cs
*ring
= obj
->ring
;
2338 if (i915_seqno_passed(ring
->get_seqno(ring
, true),
2339 i915_gem_request_get_seqno(obj
->last_read_req
)))
2340 i915_gem_object_move_to_inactive(obj
);
2344 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
2346 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2347 struct intel_engine_cs
*ring
;
2350 /* Carefully retire all requests without writing to the rings */
2351 for_each_ring(ring
, dev_priv
, i
) {
2352 ret
= intel_ring_idle(ring
);
2356 i915_gem_retire_requests(dev
);
2358 /* Finally reset hw state */
2359 for_each_ring(ring
, dev_priv
, i
) {
2360 intel_ring_init_seqno(ring
, seqno
);
2362 for (j
= 0; j
< ARRAY_SIZE(ring
->semaphore
.sync_seqno
); j
++)
2363 ring
->semaphore
.sync_seqno
[j
] = 0;
2369 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2371 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2377 /* HWS page needs to be set less than what we
2378 * will inject to ring
2380 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
2384 /* Carefully set the last_seqno value so that wrap
2385 * detection still works
2387 dev_priv
->next_seqno
= seqno
;
2388 dev_priv
->last_seqno
= seqno
- 1;
2389 if (dev_priv
->last_seqno
== 0)
2390 dev_priv
->last_seqno
--;
2396 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
2398 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2400 /* reserve 0 for non-seqno */
2401 if (dev_priv
->next_seqno
== 0) {
2402 int ret
= i915_gem_init_seqno(dev
, 0);
2406 dev_priv
->next_seqno
= 1;
2409 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2413 int __i915_add_request(struct intel_engine_cs
*ring
,
2414 struct drm_file
*file
,
2415 struct drm_i915_gem_object
*obj
,
2418 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2419 struct drm_i915_gem_request
*request
;
2420 struct intel_ringbuffer
*ringbuf
;
2421 u32 request_ring_position
, request_start
;
2424 request
= ring
->outstanding_lazy_request
;
2425 if (WARN_ON(request
== NULL
))
2428 if (i915
.enable_execlists
) {
2429 struct intel_context
*ctx
= request
->ctx
;
2430 ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
2432 ringbuf
= ring
->buffer
;
2434 request_start
= intel_ring_get_tail(ringbuf
);
2436 * Emit any outstanding flushes - execbuf can fail to emit the flush
2437 * after having emitted the batchbuffer command. Hence we need to fix
2438 * things up similar to emitting the lazy request. The difference here
2439 * is that the flush _must_ happen before the next request, no matter
2442 if (i915
.enable_execlists
) {
2443 ret
= logical_ring_flush_all_caches(ringbuf
);
2447 ret
= intel_ring_flush_all_caches(ring
);
2452 /* Record the position of the start of the request so that
2453 * should we detect the updated seqno part-way through the
2454 * GPU processing the request, we never over-estimate the
2455 * position of the head.
2457 request_ring_position
= intel_ring_get_tail(ringbuf
);
2459 if (i915
.enable_execlists
) {
2460 ret
= ring
->emit_request(ringbuf
);
2464 ret
= ring
->add_request(ring
);
2469 request
->ring
= ring
;
2470 request
->head
= request_start
;
2471 request
->tail
= request_ring_position
;
2473 /* Whilst this request exists, batch_obj will be on the
2474 * active_list, and so will hold the active reference. Only when this
2475 * request is retired will the the batch_obj be moved onto the
2476 * inactive_list and lose its active reference. Hence we do not need
2477 * to explicitly hold another reference here.
2479 request
->batch_obj
= obj
;
2481 if (!i915
.enable_execlists
) {
2482 /* Hold a reference to the current context so that we can inspect
2483 * it later in case a hangcheck error event fires.
2485 request
->ctx
= ring
->last_context
;
2487 i915_gem_context_reference(request
->ctx
);
2490 request
->emitted_jiffies
= jiffies
;
2491 list_add_tail(&request
->list
, &ring
->request_list
);
2492 request
->file_priv
= NULL
;
2495 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2497 spin_lock(&file_priv
->mm
.lock
);
2498 request
->file_priv
= file_priv
;
2499 list_add_tail(&request
->client_list
,
2500 &file_priv
->mm
.request_list
);
2501 spin_unlock(&file_priv
->mm
.lock
);
2504 trace_i915_gem_request_add(ring
, request
->seqno
);
2505 ring
->outstanding_lazy_request
= NULL
;
2507 i915_queue_hangcheck(ring
->dev
);
2509 cancel_delayed_work_sync(&dev_priv
->mm
.idle_work
);
2510 queue_delayed_work(dev_priv
->wq
,
2511 &dev_priv
->mm
.retire_work
,
2512 round_jiffies_up_relative(HZ
));
2513 intel_mark_busy(dev_priv
->dev
);
2516 *out_seqno
= request
->seqno
;
2521 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2523 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2528 spin_lock(&file_priv
->mm
.lock
);
2529 list_del(&request
->client_list
);
2530 request
->file_priv
= NULL
;
2531 spin_unlock(&file_priv
->mm
.lock
);
2534 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2535 const struct intel_context
*ctx
)
2537 unsigned long elapsed
;
2539 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2541 if (ctx
->hang_stats
.banned
)
2544 if (elapsed
<= DRM_I915_CTX_BAN_PERIOD
) {
2545 if (!i915_gem_context_is_default(ctx
)) {
2546 DRM_DEBUG("context hanging too fast, banning!\n");
2548 } else if (i915_stop_ring_allow_ban(dev_priv
)) {
2549 if (i915_stop_ring_allow_warn(dev_priv
))
2550 DRM_ERROR("gpu hanging too fast, banning!\n");
2558 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2559 struct intel_context
*ctx
,
2562 struct i915_ctx_hang_stats
*hs
;
2567 hs
= &ctx
->hang_stats
;
2570 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2572 hs
->guilty_ts
= get_seconds();
2574 hs
->batch_pending
++;
2578 static void i915_gem_free_request(struct drm_i915_gem_request
*request
)
2580 list_del(&request
->list
);
2581 i915_gem_request_remove_from_client(request
);
2583 i915_gem_request_unreference(request
);
2586 void i915_gem_request_free(struct kref
*req_ref
)
2588 struct drm_i915_gem_request
*req
= container_of(req_ref
,
2590 struct intel_context
*ctx
= req
->ctx
;
2593 if (i915
.enable_execlists
) {
2594 struct intel_engine_cs
*ring
= req
->ring
;
2596 if (ctx
!= ring
->default_context
)
2597 intel_lr_context_unpin(ring
, ctx
);
2600 i915_gem_context_unreference(ctx
);
2606 struct drm_i915_gem_request
*
2607 i915_gem_find_active_request(struct intel_engine_cs
*ring
)
2609 struct drm_i915_gem_request
*request
;
2610 u32 completed_seqno
;
2612 completed_seqno
= ring
->get_seqno(ring
, false);
2614 list_for_each_entry(request
, &ring
->request_list
, list
) {
2615 if (i915_seqno_passed(completed_seqno
, request
->seqno
))
2624 static void i915_gem_reset_ring_status(struct drm_i915_private
*dev_priv
,
2625 struct intel_engine_cs
*ring
)
2627 struct drm_i915_gem_request
*request
;
2630 request
= i915_gem_find_active_request(ring
);
2632 if (request
== NULL
)
2635 ring_hung
= ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
2637 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
2639 list_for_each_entry_continue(request
, &ring
->request_list
, list
)
2640 i915_set_reset_status(dev_priv
, request
->ctx
, false);
2643 static void i915_gem_reset_ring_cleanup(struct drm_i915_private
*dev_priv
,
2644 struct intel_engine_cs
*ring
)
2646 while (!list_empty(&ring
->active_list
)) {
2647 struct drm_i915_gem_object
*obj
;
2649 obj
= list_first_entry(&ring
->active_list
,
2650 struct drm_i915_gem_object
,
2653 i915_gem_object_move_to_inactive(obj
);
2657 * Clear the execlists queue up before freeing the requests, as those
2658 * are the ones that keep the context and ringbuffer backing objects
2661 while (!list_empty(&ring
->execlist_queue
)) {
2662 struct intel_ctx_submit_request
*submit_req
;
2664 submit_req
= list_first_entry(&ring
->execlist_queue
,
2665 struct intel_ctx_submit_request
,
2667 list_del(&submit_req
->execlist_link
);
2668 intel_runtime_pm_put(dev_priv
);
2669 i915_gem_context_unreference(submit_req
->ctx
);
2674 * We must free the requests after all the corresponding objects have
2675 * been moved off active lists. Which is the same order as the normal
2676 * retire_requests function does. This is important if object hold
2677 * implicit references on things like e.g. ppgtt address spaces through
2680 while (!list_empty(&ring
->request_list
)) {
2681 struct drm_i915_gem_request
*request
;
2683 request
= list_first_entry(&ring
->request_list
,
2684 struct drm_i915_gem_request
,
2687 i915_gem_free_request(request
);
2690 /* This may not have been flushed before the reset, so clean it now */
2691 i915_gem_request_assign(&ring
->outstanding_lazy_request
, NULL
);
2694 void i915_gem_restore_fences(struct drm_device
*dev
)
2696 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2699 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2700 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2703 * Commit delayed tiling changes if we have an object still
2704 * attached to the fence, otherwise just clear the fence.
2707 i915_gem_object_update_fence(reg
->obj
, reg
,
2708 reg
->obj
->tiling_mode
);
2710 i915_gem_write_fence(dev
, i
, NULL
);
2715 void i915_gem_reset(struct drm_device
*dev
)
2717 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2718 struct intel_engine_cs
*ring
;
2722 * Before we free the objects from the requests, we need to inspect
2723 * them for finding the guilty party. As the requests only borrow
2724 * their reference to the objects, the inspection must be done first.
2726 for_each_ring(ring
, dev_priv
, i
)
2727 i915_gem_reset_ring_status(dev_priv
, ring
);
2729 for_each_ring(ring
, dev_priv
, i
)
2730 i915_gem_reset_ring_cleanup(dev_priv
, ring
);
2732 i915_gem_context_reset(dev
);
2734 i915_gem_restore_fences(dev
);
2738 * This function clears the request list as sequence numbers are passed.
2741 i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
)
2745 if (list_empty(&ring
->request_list
))
2748 WARN_ON(i915_verify_lists(ring
->dev
));
2750 seqno
= ring
->get_seqno(ring
, true);
2752 /* Move any buffers on the active list that are no longer referenced
2753 * by the ringbuffer to the flushing/inactive lists as appropriate,
2754 * before we free the context associated with the requests.
2756 while (!list_empty(&ring
->active_list
)) {
2757 struct drm_i915_gem_object
*obj
;
2759 obj
= list_first_entry(&ring
->active_list
,
2760 struct drm_i915_gem_object
,
2763 if (!i915_seqno_passed(seqno
,
2764 i915_gem_request_get_seqno(obj
->last_read_req
)))
2767 i915_gem_object_move_to_inactive(obj
);
2771 while (!list_empty(&ring
->request_list
)) {
2772 struct drm_i915_gem_request
*request
;
2773 struct intel_ringbuffer
*ringbuf
;
2775 request
= list_first_entry(&ring
->request_list
,
2776 struct drm_i915_gem_request
,
2779 if (!i915_seqno_passed(seqno
, request
->seqno
))
2782 trace_i915_gem_request_retire(ring
, request
->seqno
);
2784 /* This is one of the few common intersection points
2785 * between legacy ringbuffer submission and execlists:
2786 * we need to tell them apart in order to find the correct
2787 * ringbuffer to which the request belongs to.
2789 if (i915
.enable_execlists
) {
2790 struct intel_context
*ctx
= request
->ctx
;
2791 ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
2793 ringbuf
= ring
->buffer
;
2795 /* We know the GPU must have read the request to have
2796 * sent us the seqno + interrupt, so use the position
2797 * of tail of the request to update the last known position
2800 ringbuf
->last_retired_head
= request
->tail
;
2802 i915_gem_free_request(request
);
2805 if (unlikely(ring
->trace_irq_seqno
&&
2806 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
2807 ring
->irq_put(ring
);
2808 ring
->trace_irq_seqno
= 0;
2811 WARN_ON(i915_verify_lists(ring
->dev
));
2815 i915_gem_retire_requests(struct drm_device
*dev
)
2817 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2818 struct intel_engine_cs
*ring
;
2822 for_each_ring(ring
, dev_priv
, i
) {
2823 i915_gem_retire_requests_ring(ring
);
2824 idle
&= list_empty(&ring
->request_list
);
2825 if (i915
.enable_execlists
) {
2826 unsigned long flags
;
2828 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
2829 idle
&= list_empty(&ring
->execlist_queue
);
2830 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
2832 intel_execlists_retire_requests(ring
);
2837 mod_delayed_work(dev_priv
->wq
,
2838 &dev_priv
->mm
.idle_work
,
2839 msecs_to_jiffies(100));
2845 i915_gem_retire_work_handler(struct work_struct
*work
)
2847 struct drm_i915_private
*dev_priv
=
2848 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
2849 struct drm_device
*dev
= dev_priv
->dev
;
2852 /* Come back later if the device is busy... */
2854 if (mutex_trylock(&dev
->struct_mutex
)) {
2855 idle
= i915_gem_retire_requests(dev
);
2856 mutex_unlock(&dev
->struct_mutex
);
2859 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2860 round_jiffies_up_relative(HZ
));
2864 i915_gem_idle_work_handler(struct work_struct
*work
)
2866 struct drm_i915_private
*dev_priv
=
2867 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
2869 intel_mark_idle(dev_priv
->dev
);
2873 * Ensures that an object will eventually get non-busy by flushing any required
2874 * write domains, emitting any outstanding lazy request and retiring and
2875 * completed requests.
2878 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2883 ret
= i915_gem_check_olr(obj
->ring
,
2884 i915_gem_request_get_seqno(obj
->last_read_req
));
2888 i915_gem_retire_requests_ring(obj
->ring
);
2895 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2896 * @DRM_IOCTL_ARGS: standard ioctl arguments
2898 * Returns 0 if successful, else an error is returned with the remaining time in
2899 * the timeout parameter.
2900 * -ETIME: object is still busy after timeout
2901 * -ERESTARTSYS: signal interrupted the wait
2902 * -ENONENT: object doesn't exist
2903 * Also possible, but rare:
2904 * -EAGAIN: GPU wedged
2906 * -ENODEV: Internal IRQ fail
2907 * -E?: The add request failed
2909 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2910 * non-zero timeout parameter the wait ioctl will wait for the given number of
2911 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2912 * without holding struct_mutex the object may become re-busied before this
2913 * function completes. A similar but shorter * race condition exists in the busy
2917 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2919 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2920 struct drm_i915_gem_wait
*args
= data
;
2921 struct drm_i915_gem_object
*obj
;
2922 struct drm_i915_gem_request
*req
;
2923 struct intel_engine_cs
*ring
= NULL
;
2924 unsigned reset_counter
;
2928 if (args
->flags
!= 0)
2931 ret
= i915_mutex_lock_interruptible(dev
);
2935 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2936 if (&obj
->base
== NULL
) {
2937 mutex_unlock(&dev
->struct_mutex
);
2941 /* Need to make sure the object gets inactive eventually. */
2942 ret
= i915_gem_object_flush_active(obj
);
2946 if (!obj
->active
|| !obj
->last_read_req
)
2949 req
= obj
->last_read_req
;
2950 seqno
= i915_gem_request_get_seqno(req
);
2951 WARN_ON(seqno
== 0);
2954 /* Do this after OLR check to make sure we make forward progress polling
2955 * on this IOCTL with a timeout <=0 (like busy ioctl)
2957 if (args
->timeout_ns
<= 0) {
2962 drm_gem_object_unreference(&obj
->base
);
2963 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
2964 i915_gem_request_reference(req
);
2965 mutex_unlock(&dev
->struct_mutex
);
2967 ret
= __i915_wait_seqno(ring
, seqno
, reset_counter
, true, &args
->timeout_ns
,
2969 mutex_lock(&dev
->struct_mutex
);
2970 i915_gem_request_unreference(req
);
2971 mutex_unlock(&dev
->struct_mutex
);
2975 drm_gem_object_unreference(&obj
->base
);
2976 mutex_unlock(&dev
->struct_mutex
);
2981 * i915_gem_object_sync - sync an object to a ring.
2983 * @obj: object which may be in use on another ring.
2984 * @to: ring we wish to use the object on. May be NULL.
2986 * This code is meant to abstract object synchronization with the GPU.
2987 * Calling with NULL implies synchronizing the object with the CPU
2988 * rather than a particular GPU ring.
2990 * Returns 0 if successful, else propagates up the lower layer error.
2993 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2994 struct intel_engine_cs
*to
)
2996 struct intel_engine_cs
*from
= obj
->ring
;
3000 if (from
== NULL
|| to
== from
)
3003 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
3004 return i915_gem_object_wait_rendering(obj
, false);
3006 idx
= intel_ring_sync_index(from
, to
);
3008 seqno
= i915_gem_request_get_seqno(obj
->last_read_req
);
3009 /* Optimization: Avoid semaphore sync when we are sure we already
3010 * waited for an object with higher seqno */
3011 if (seqno
<= from
->semaphore
.sync_seqno
[idx
])
3014 ret
= i915_gem_check_olr(obj
->ring
, seqno
);
3018 trace_i915_gem_ring_sync_to(from
, to
, seqno
);
3019 ret
= to
->semaphore
.sync_to(to
, from
, seqno
);
3021 /* We use last_read_req because sync_to()
3022 * might have just caused seqno wrap under
3025 from
->semaphore
.sync_seqno
[idx
] =
3026 i915_gem_request_get_seqno(obj
->last_read_req
);
3031 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
3033 u32 old_write_domain
, old_read_domains
;
3035 /* Force a pagefault for domain tracking on next user access */
3036 i915_gem_release_mmap(obj
);
3038 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3041 /* Wait for any direct GTT access to complete */
3044 old_read_domains
= obj
->base
.read_domains
;
3045 old_write_domain
= obj
->base
.write_domain
;
3047 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
3048 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
3050 trace_i915_gem_object_change_domain(obj
,
3055 int i915_vma_unbind(struct i915_vma
*vma
)
3057 struct drm_i915_gem_object
*obj
= vma
->obj
;
3058 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3061 if (list_empty(&vma
->vma_link
))
3064 if (!drm_mm_node_allocated(&vma
->node
)) {
3065 i915_gem_vma_destroy(vma
);
3072 BUG_ON(obj
->pages
== NULL
);
3074 ret
= i915_gem_object_finish_gpu(obj
);
3077 /* Continue on if we fail due to EIO, the GPU is hung so we
3078 * should be safe and we need to cleanup or else we might
3079 * cause memory corruption through use-after-free.
3082 /* Throw away the active reference before moving to the unbound list */
3083 i915_gem_object_retire(obj
);
3085 if (i915_is_ggtt(vma
->vm
)) {
3086 i915_gem_object_finish_gtt(obj
);
3088 /* release the fence reg _after_ flushing */
3089 ret
= i915_gem_object_put_fence(obj
);
3094 trace_i915_vma_unbind(vma
);
3096 vma
->unbind_vma(vma
);
3098 list_del_init(&vma
->mm_list
);
3099 if (i915_is_ggtt(vma
->vm
))
3100 obj
->map_and_fenceable
= false;
3102 drm_mm_remove_node(&vma
->node
);
3103 i915_gem_vma_destroy(vma
);
3105 /* Since the unbound list is global, only move to that list if
3106 * no more VMAs exist. */
3107 if (list_empty(&obj
->vma_list
)) {
3108 i915_gem_gtt_finish_object(obj
);
3109 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
3112 /* And finally now the object is completely decoupled from this vma,
3113 * we can drop its hold on the backing storage and allow it to be
3114 * reaped by the shrinker.
3116 i915_gem_object_unpin_pages(obj
);
3121 int i915_gpu_idle(struct drm_device
*dev
)
3123 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3124 struct intel_engine_cs
*ring
;
3127 /* Flush everything onto the inactive list. */
3128 for_each_ring(ring
, dev_priv
, i
) {
3129 if (!i915
.enable_execlists
) {
3130 ret
= i915_switch_context(ring
, ring
->default_context
);
3135 ret
= intel_ring_idle(ring
);
3143 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
3144 struct drm_i915_gem_object
*obj
)
3146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3148 int fence_pitch_shift
;
3150 if (INTEL_INFO(dev
)->gen
>= 6) {
3151 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
3152 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
3154 fence_reg
= FENCE_REG_965_0
;
3155 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
3158 fence_reg
+= reg
* 8;
3160 /* To w/a incoherency with non-atomic 64-bit register updates,
3161 * we split the 64-bit update into two 32-bit writes. In order
3162 * for a partial fence not to be evaluated between writes, we
3163 * precede the update with write to turn off the fence register,
3164 * and only enable the fence as the last step.
3166 * For extra levels of paranoia, we make sure each step lands
3167 * before applying the next step.
3169 I915_WRITE(fence_reg
, 0);
3170 POSTING_READ(fence_reg
);
3173 u32 size
= i915_gem_obj_ggtt_size(obj
);
3176 val
= (uint64_t)((i915_gem_obj_ggtt_offset(obj
) + size
- 4096) &
3178 val
|= i915_gem_obj_ggtt_offset(obj
) & 0xfffff000;
3179 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
3180 if (obj
->tiling_mode
== I915_TILING_Y
)
3181 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
3182 val
|= I965_FENCE_REG_VALID
;
3184 I915_WRITE(fence_reg
+ 4, val
>> 32);
3185 POSTING_READ(fence_reg
+ 4);
3187 I915_WRITE(fence_reg
+ 0, val
);
3188 POSTING_READ(fence_reg
);
3190 I915_WRITE(fence_reg
+ 4, 0);
3191 POSTING_READ(fence_reg
+ 4);
3195 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
3196 struct drm_i915_gem_object
*obj
)
3198 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3202 u32 size
= i915_gem_obj_ggtt_size(obj
);
3206 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I915_FENCE_START_MASK
) ||
3207 (size
& -size
) != size
||
3208 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3209 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3210 i915_gem_obj_ggtt_offset(obj
), obj
->map_and_fenceable
, size
);
3212 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
3217 /* Note: pitch better be a power of two tile widths */
3218 pitch_val
= obj
->stride
/ tile_width
;
3219 pitch_val
= ffs(pitch_val
) - 1;
3221 val
= i915_gem_obj_ggtt_offset(obj
);
3222 if (obj
->tiling_mode
== I915_TILING_Y
)
3223 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3224 val
|= I915_FENCE_SIZE_BITS(size
);
3225 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3226 val
|= I830_FENCE_REG_VALID
;
3231 reg
= FENCE_REG_830_0
+ reg
* 4;
3233 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
3235 I915_WRITE(reg
, val
);
3239 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
3240 struct drm_i915_gem_object
*obj
)
3242 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3246 u32 size
= i915_gem_obj_ggtt_size(obj
);
3249 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I830_FENCE_START_MASK
) ||
3250 (size
& -size
) != size
||
3251 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3252 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3253 i915_gem_obj_ggtt_offset(obj
), size
);
3255 pitch_val
= obj
->stride
/ 128;
3256 pitch_val
= ffs(pitch_val
) - 1;
3258 val
= i915_gem_obj_ggtt_offset(obj
);
3259 if (obj
->tiling_mode
== I915_TILING_Y
)
3260 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3261 val
|= I830_FENCE_SIZE_BITS(size
);
3262 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3263 val
|= I830_FENCE_REG_VALID
;
3267 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
3268 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
3271 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
3273 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
3276 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
3277 struct drm_i915_gem_object
*obj
)
3279 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3281 /* Ensure that all CPU reads are completed before installing a fence
3282 * and all writes before removing the fence.
3284 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
3287 WARN(obj
&& (!obj
->stride
|| !obj
->tiling_mode
),
3288 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3289 obj
->stride
, obj
->tiling_mode
);
3291 switch (INTEL_INFO(dev
)->gen
) {
3297 case 4: i965_write_fence_reg(dev
, reg
, obj
); break;
3298 case 3: i915_write_fence_reg(dev
, reg
, obj
); break;
3299 case 2: i830_write_fence_reg(dev
, reg
, obj
); break;
3303 /* And similarly be paranoid that no direct access to this region
3304 * is reordered to before the fence is installed.
3306 if (i915_gem_object_needs_mb(obj
))
3310 static inline int fence_number(struct drm_i915_private
*dev_priv
,
3311 struct drm_i915_fence_reg
*fence
)
3313 return fence
- dev_priv
->fence_regs
;
3316 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
3317 struct drm_i915_fence_reg
*fence
,
3320 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3321 int reg
= fence_number(dev_priv
, fence
);
3323 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
3326 obj
->fence_reg
= reg
;
3328 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
3330 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3332 list_del_init(&fence
->lru_list
);
3334 obj
->fence_dirty
= false;
3338 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
3340 if (obj
->last_fenced_req
) {
3341 int ret
= i915_wait_seqno(obj
->ring
,
3342 i915_gem_request_get_seqno(obj
->last_fenced_req
));
3346 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
3353 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
3355 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3356 struct drm_i915_fence_reg
*fence
;
3359 ret
= i915_gem_object_wait_fence(obj
);
3363 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
3366 fence
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3368 if (WARN_ON(fence
->pin_count
))
3371 i915_gem_object_fence_lost(obj
);
3372 i915_gem_object_update_fence(obj
, fence
, false);
3377 static struct drm_i915_fence_reg
*
3378 i915_find_fence_reg(struct drm_device
*dev
)
3380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3381 struct drm_i915_fence_reg
*reg
, *avail
;
3384 /* First try to find a free reg */
3386 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
3387 reg
= &dev_priv
->fence_regs
[i
];
3391 if (!reg
->pin_count
)
3398 /* None available, try to steal one or wait for a user to finish */
3399 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
3407 /* Wait for completion of pending flips which consume fences */
3408 if (intel_has_pending_fb_unpin(dev
))
3409 return ERR_PTR(-EAGAIN
);
3411 return ERR_PTR(-EDEADLK
);
3415 * i915_gem_object_get_fence - set up fencing for an object
3416 * @obj: object to map through a fence reg
3418 * When mapping objects through the GTT, userspace wants to be able to write
3419 * to them without having to worry about swizzling if the object is tiled.
3420 * This function walks the fence regs looking for a free one for @obj,
3421 * stealing one if it can't find any.
3423 * It then sets up the reg based on the object's properties: address, pitch
3424 * and tiling format.
3426 * For an untiled surface, this removes any existing fence.
3429 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
3431 struct drm_device
*dev
= obj
->base
.dev
;
3432 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3433 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
3434 struct drm_i915_fence_reg
*reg
;
3437 /* Have we updated the tiling parameters upon the object and so
3438 * will need to serialise the write to the associated fence register?
3440 if (obj
->fence_dirty
) {
3441 ret
= i915_gem_object_wait_fence(obj
);
3446 /* Just update our place in the LRU if our fence is getting reused. */
3447 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
3448 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3449 if (!obj
->fence_dirty
) {
3450 list_move_tail(®
->lru_list
,
3451 &dev_priv
->mm
.fence_list
);
3454 } else if (enable
) {
3455 if (WARN_ON(!obj
->map_and_fenceable
))
3458 reg
= i915_find_fence_reg(dev
);
3460 return PTR_ERR(reg
);
3463 struct drm_i915_gem_object
*old
= reg
->obj
;
3465 ret
= i915_gem_object_wait_fence(old
);
3469 i915_gem_object_fence_lost(old
);
3474 i915_gem_object_update_fence(obj
, reg
, enable
);
3479 static bool i915_gem_valid_gtt_space(struct i915_vma
*vma
,
3480 unsigned long cache_level
)
3482 struct drm_mm_node
*gtt_space
= &vma
->node
;
3483 struct drm_mm_node
*other
;
3486 * On some machines we have to be careful when putting differing types
3487 * of snoopable memory together to avoid the prefetcher crossing memory
3488 * domains and dying. During vm initialisation, we decide whether or not
3489 * these constraints apply and set the drm_mm.color_adjust
3492 if (vma
->vm
->mm
.color_adjust
== NULL
)
3495 if (!drm_mm_node_allocated(gtt_space
))
3498 if (list_empty(>t_space
->node_list
))
3501 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3502 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3505 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3506 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3513 * Finds free space in the GTT aperture and binds the object there.
3515 static struct i915_vma
*
3516 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3517 struct i915_address_space
*vm
,
3521 struct drm_device
*dev
= obj
->base
.dev
;
3522 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3523 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
3524 unsigned long start
=
3525 flags
& PIN_OFFSET_BIAS
? flags
& PIN_OFFSET_MASK
: 0;
3527 flags
& PIN_MAPPABLE
? dev_priv
->gtt
.mappable_end
: vm
->total
;
3528 struct i915_vma
*vma
;
3531 fence_size
= i915_gem_get_gtt_size(dev
,
3534 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3536 obj
->tiling_mode
, true);
3537 unfenced_alignment
=
3538 i915_gem_get_gtt_alignment(dev
,
3540 obj
->tiling_mode
, false);
3543 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3545 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3546 DRM_DEBUG("Invalid object alignment requested %u\n", alignment
);
3547 return ERR_PTR(-EINVAL
);
3550 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3552 /* If the object is bigger than the entire aperture, reject it early
3553 * before evicting everything in a vain attempt to find space.
3555 if (obj
->base
.size
> end
) {
3556 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3558 flags
& PIN_MAPPABLE
? "mappable" : "total",
3560 return ERR_PTR(-E2BIG
);
3563 ret
= i915_gem_object_get_pages(obj
);
3565 return ERR_PTR(ret
);
3567 i915_gem_object_pin_pages(obj
);
3569 vma
= i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3574 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3578 DRM_MM_SEARCH_DEFAULT
,
3579 DRM_MM_CREATE_DEFAULT
);
3581 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3590 if (WARN_ON(!i915_gem_valid_gtt_space(vma
, obj
->cache_level
))) {
3592 goto err_remove_node
;
3595 ret
= i915_gem_gtt_prepare_object(obj
);
3597 goto err_remove_node
;
3599 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3600 list_add_tail(&vma
->mm_list
, &vm
->inactive_list
);
3602 trace_i915_vma_bind(vma
, flags
);
3603 vma
->bind_vma(vma
, obj
->cache_level
,
3604 flags
& PIN_GLOBAL
? GLOBAL_BIND
: 0);
3609 drm_mm_remove_node(&vma
->node
);
3611 i915_gem_vma_destroy(vma
);
3614 i915_gem_object_unpin_pages(obj
);
3619 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3622 /* If we don't have a page list set up, then we're not pinned
3623 * to GPU, and we can ignore the cache flush because it'll happen
3624 * again at bind time.
3626 if (obj
->pages
== NULL
)
3630 * Stolen memory is always coherent with the GPU as it is explicitly
3631 * marked as wc by the system, or the system is cache-coherent.
3633 if (obj
->stolen
|| obj
->phys_handle
)
3636 /* If the GPU is snooping the contents of the CPU cache,
3637 * we do not need to manually clear the CPU cache lines. However,
3638 * the caches are only snooped when the render cache is
3639 * flushed/invalidated. As we always have to emit invalidations
3640 * and flushes when moving into and out of the RENDER domain, correct
3641 * snooping behaviour occurs naturally as the result of our domain
3644 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
3647 trace_i915_gem_object_clflush(obj
);
3648 drm_clflush_sg(obj
->pages
);
3653 /** Flushes the GTT write domain for the object if it's dirty. */
3655 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3657 uint32_t old_write_domain
;
3659 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3662 /* No actual flushing is required for the GTT write domain. Writes
3663 * to it immediately go to main memory as far as we know, so there's
3664 * no chipset flush. It also doesn't land in render cache.
3666 * However, we do have to enforce the order so that all writes through
3667 * the GTT land before any writes to the device, such as updates to
3672 old_write_domain
= obj
->base
.write_domain
;
3673 obj
->base
.write_domain
= 0;
3675 intel_fb_obj_flush(obj
, false);
3677 trace_i915_gem_object_change_domain(obj
,
3678 obj
->base
.read_domains
,
3682 /** Flushes the CPU write domain for the object if it's dirty. */
3684 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
,
3687 uint32_t old_write_domain
;
3689 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3692 if (i915_gem_clflush_object(obj
, force
))
3693 i915_gem_chipset_flush(obj
->base
.dev
);
3695 old_write_domain
= obj
->base
.write_domain
;
3696 obj
->base
.write_domain
= 0;
3698 intel_fb_obj_flush(obj
, false);
3700 trace_i915_gem_object_change_domain(obj
,
3701 obj
->base
.read_domains
,
3706 * Moves a single object to the GTT read, and possibly write domain.
3708 * This function returns when the move is complete, including waiting on
3712 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3714 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3715 struct i915_vma
*vma
= i915_gem_obj_to_ggtt(obj
);
3716 uint32_t old_write_domain
, old_read_domains
;
3719 /* Not valid to be called on unbound objects. */
3723 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3726 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3730 i915_gem_object_retire(obj
);
3731 i915_gem_object_flush_cpu_write_domain(obj
, false);
3733 /* Serialise direct access to this object with the barriers for
3734 * coherent writes from the GPU, by effectively invalidating the
3735 * GTT domain upon first access.
3737 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3740 old_write_domain
= obj
->base
.write_domain
;
3741 old_read_domains
= obj
->base
.read_domains
;
3743 /* It should now be out of any other write domains, and we can update
3744 * the domain values for our changes.
3746 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3747 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3749 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3750 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3755 intel_fb_obj_invalidate(obj
, NULL
);
3757 trace_i915_gem_object_change_domain(obj
,
3761 /* And bump the LRU for this access */
3762 if (i915_gem_object_is_inactive(obj
))
3763 list_move_tail(&vma
->mm_list
,
3764 &dev_priv
->gtt
.base
.inactive_list
);
3769 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3770 enum i915_cache_level cache_level
)
3772 struct drm_device
*dev
= obj
->base
.dev
;
3773 struct i915_vma
*vma
, *next
;
3776 if (obj
->cache_level
== cache_level
)
3779 if (i915_gem_obj_is_pinned(obj
)) {
3780 DRM_DEBUG("can not change the cache level of pinned objects\n");
3784 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
3785 if (!i915_gem_valid_gtt_space(vma
, cache_level
)) {
3786 ret
= i915_vma_unbind(vma
);
3792 if (i915_gem_obj_bound_any(obj
)) {
3793 ret
= i915_gem_object_finish_gpu(obj
);
3797 i915_gem_object_finish_gtt(obj
);
3799 /* Before SandyBridge, you could not use tiling or fence
3800 * registers with snooped memory, so relinquish any fences
3801 * currently pointing to our region in the aperture.
3803 if (INTEL_INFO(dev
)->gen
< 6) {
3804 ret
= i915_gem_object_put_fence(obj
);
3809 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3810 if (drm_mm_node_allocated(&vma
->node
))
3811 vma
->bind_vma(vma
, cache_level
,
3812 vma
->bound
& GLOBAL_BIND
);
3815 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3816 vma
->node
.color
= cache_level
;
3817 obj
->cache_level
= cache_level
;
3819 if (cpu_write_needs_clflush(obj
)) {
3820 u32 old_read_domains
, old_write_domain
;
3822 /* If we're coming from LLC cached, then we haven't
3823 * actually been tracking whether the data is in the
3824 * CPU cache or not, since we only allow one bit set
3825 * in obj->write_domain and have been skipping the clflushes.
3826 * Just set it to the CPU cache for now.
3828 i915_gem_object_retire(obj
);
3829 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
3831 old_read_domains
= obj
->base
.read_domains
;
3832 old_write_domain
= obj
->base
.write_domain
;
3834 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3835 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3837 trace_i915_gem_object_change_domain(obj
,
3845 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3846 struct drm_file
*file
)
3848 struct drm_i915_gem_caching
*args
= data
;
3849 struct drm_i915_gem_object
*obj
;
3852 ret
= i915_mutex_lock_interruptible(dev
);
3856 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3857 if (&obj
->base
== NULL
) {
3862 switch (obj
->cache_level
) {
3863 case I915_CACHE_LLC
:
3864 case I915_CACHE_L3_LLC
:
3865 args
->caching
= I915_CACHING_CACHED
;
3869 args
->caching
= I915_CACHING_DISPLAY
;
3873 args
->caching
= I915_CACHING_NONE
;
3877 drm_gem_object_unreference(&obj
->base
);
3879 mutex_unlock(&dev
->struct_mutex
);
3883 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3884 struct drm_file
*file
)
3886 struct drm_i915_gem_caching
*args
= data
;
3887 struct drm_i915_gem_object
*obj
;
3888 enum i915_cache_level level
;
3891 switch (args
->caching
) {
3892 case I915_CACHING_NONE
:
3893 level
= I915_CACHE_NONE
;
3895 case I915_CACHING_CACHED
:
3896 level
= I915_CACHE_LLC
;
3898 case I915_CACHING_DISPLAY
:
3899 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
3905 ret
= i915_mutex_lock_interruptible(dev
);
3909 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3910 if (&obj
->base
== NULL
) {
3915 ret
= i915_gem_object_set_cache_level(obj
, level
);
3917 drm_gem_object_unreference(&obj
->base
);
3919 mutex_unlock(&dev
->struct_mutex
);
3923 static bool is_pin_display(struct drm_i915_gem_object
*obj
)
3925 struct i915_vma
*vma
;
3927 vma
= i915_gem_obj_to_ggtt(obj
);
3931 /* There are 2 sources that pin objects:
3932 * 1. The display engine (scanouts, sprites, cursors);
3933 * 2. Reservations for execbuffer;
3935 * We can ignore reservations as we hold the struct_mutex and
3936 * are only called outside of the reservation path.
3938 return vma
->pin_count
;
3942 * Prepare buffer for display plane (scanout, cursors, etc).
3943 * Can be called from an uninterruptible phase (modesetting) and allows
3944 * any flushes to be pipelined (for pageflips).
3947 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3949 struct intel_engine_cs
*pipelined
)
3951 u32 old_read_domains
, old_write_domain
;
3952 bool was_pin_display
;
3955 if (pipelined
!= obj
->ring
) {
3956 ret
= i915_gem_object_sync(obj
, pipelined
);
3961 /* Mark the pin_display early so that we account for the
3962 * display coherency whilst setting up the cache domains.
3964 was_pin_display
= obj
->pin_display
;
3965 obj
->pin_display
= true;
3967 /* The display engine is not coherent with the LLC cache on gen6. As
3968 * a result, we make sure that the pinning that is about to occur is
3969 * done with uncached PTEs. This is lowest common denominator for all
3972 * However for gen6+, we could do better by using the GFDT bit instead
3973 * of uncaching, which would allow us to flush all the LLC-cached data
3974 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3976 ret
= i915_gem_object_set_cache_level(obj
,
3977 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
3979 goto err_unpin_display
;
3981 /* As the user may map the buffer once pinned in the display plane
3982 * (e.g. libkms for the bootup splash), we have to ensure that we
3983 * always use map_and_fenceable for all scanout buffers.
3985 ret
= i915_gem_obj_ggtt_pin(obj
, alignment
, PIN_MAPPABLE
);
3987 goto err_unpin_display
;
3989 i915_gem_object_flush_cpu_write_domain(obj
, true);
3991 old_write_domain
= obj
->base
.write_domain
;
3992 old_read_domains
= obj
->base
.read_domains
;
3994 /* It should now be out of any other write domains, and we can update
3995 * the domain values for our changes.
3997 obj
->base
.write_domain
= 0;
3998 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
4000 trace_i915_gem_object_change_domain(obj
,
4007 WARN_ON(was_pin_display
!= is_pin_display(obj
));
4008 obj
->pin_display
= was_pin_display
;
4013 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
)
4015 i915_gem_object_ggtt_unpin(obj
);
4016 obj
->pin_display
= is_pin_display(obj
);
4020 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
4024 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
4027 ret
= i915_gem_object_wait_rendering(obj
, false);
4031 /* Ensure that we invalidate the GPU's caches and TLBs. */
4032 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
4037 * Moves a single object to the CPU read, and possibly write domain.
4039 * This function returns when the move is complete, including waiting on
4043 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
4045 uint32_t old_write_domain
, old_read_domains
;
4048 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
4051 ret
= i915_gem_object_wait_rendering(obj
, !write
);
4055 i915_gem_object_retire(obj
);
4056 i915_gem_object_flush_gtt_write_domain(obj
);
4058 old_write_domain
= obj
->base
.write_domain
;
4059 old_read_domains
= obj
->base
.read_domains
;
4061 /* Flush the CPU cache if it's still invalid. */
4062 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
4063 i915_gem_clflush_object(obj
, false);
4065 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
4068 /* It should now be out of any other write domains, and we can update
4069 * the domain values for our changes.
4071 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
4073 /* If we're writing through the CPU, then the GPU read domains will
4074 * need to be invalidated at next use.
4077 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4078 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4082 intel_fb_obj_invalidate(obj
, NULL
);
4084 trace_i915_gem_object_change_domain(obj
,
4091 /* Throttle our rendering by waiting until the ring has completed our requests
4092 * emitted over 20 msec ago.
4094 * Note that if we were to use the current jiffies each time around the loop,
4095 * we wouldn't escape the function with any frames outstanding if the time to
4096 * render a frame was over 20ms.
4098 * This should get us reasonable parallelism between CPU and GPU but also
4099 * relatively low latency when blocking on a particular request to finish.
4102 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
4104 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4105 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4106 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
4107 struct drm_i915_gem_request
*request
, *target
= NULL
;
4108 unsigned reset_counter
;
4111 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
4115 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
4119 spin_lock(&file_priv
->mm
.lock
);
4120 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
4121 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
4126 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
4128 i915_gem_request_reference(target
);
4129 spin_unlock(&file_priv
->mm
.lock
);
4134 ret
= __i915_wait_seqno(i915_gem_request_get_ring(target
),
4135 i915_gem_request_get_seqno(target
),
4136 reset_counter
, true, NULL
, NULL
);
4138 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
4140 mutex_lock(&dev
->struct_mutex
);
4141 i915_gem_request_unreference(target
);
4142 mutex_unlock(&dev
->struct_mutex
);
4148 i915_vma_misplaced(struct i915_vma
*vma
, uint32_t alignment
, uint64_t flags
)
4150 struct drm_i915_gem_object
*obj
= vma
->obj
;
4153 vma
->node
.start
& (alignment
- 1))
4156 if (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)
4159 if (flags
& PIN_OFFSET_BIAS
&&
4160 vma
->node
.start
< (flags
& PIN_OFFSET_MASK
))
4167 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
4168 struct i915_address_space
*vm
,
4172 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4173 struct i915_vma
*vma
;
4177 if (WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
))
4180 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
4183 if (WARN_ON((flags
& (PIN_MAPPABLE
| PIN_GLOBAL
)) == PIN_MAPPABLE
))
4186 vma
= i915_gem_obj_to_vma(obj
, vm
);
4188 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
4191 if (i915_vma_misplaced(vma
, alignment
, flags
)) {
4192 WARN(vma
->pin_count
,
4193 "bo is already pinned with incorrect alignment:"
4194 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4195 " obj->map_and_fenceable=%d\n",
4196 i915_gem_obj_offset(obj
, vm
), alignment
,
4197 !!(flags
& PIN_MAPPABLE
),
4198 obj
->map_and_fenceable
);
4199 ret
= i915_vma_unbind(vma
);
4207 bound
= vma
? vma
->bound
: 0;
4208 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
4209 vma
= i915_gem_object_bind_to_vm(obj
, vm
, alignment
, flags
);
4211 return PTR_ERR(vma
);
4214 if (flags
& PIN_GLOBAL
&& !(vma
->bound
& GLOBAL_BIND
))
4215 vma
->bind_vma(vma
, obj
->cache_level
, GLOBAL_BIND
);
4217 if ((bound
^ vma
->bound
) & GLOBAL_BIND
) {
4218 bool mappable
, fenceable
;
4219 u32 fence_size
, fence_alignment
;
4221 fence_size
= i915_gem_get_gtt_size(obj
->base
.dev
,
4224 fence_alignment
= i915_gem_get_gtt_alignment(obj
->base
.dev
,
4229 fenceable
= (vma
->node
.size
== fence_size
&&
4230 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
4232 mappable
= (vma
->node
.start
+ obj
->base
.size
<=
4233 dev_priv
->gtt
.mappable_end
);
4235 obj
->map_and_fenceable
= mappable
&& fenceable
;
4238 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
4241 if (flags
& PIN_MAPPABLE
)
4242 obj
->pin_mappable
|= true;
4248 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
)
4250 struct i915_vma
*vma
= i915_gem_obj_to_ggtt(obj
);
4253 BUG_ON(vma
->pin_count
== 0);
4254 BUG_ON(!i915_gem_obj_ggtt_bound(obj
));
4256 if (--vma
->pin_count
== 0)
4257 obj
->pin_mappable
= false;
4261 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
4263 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4264 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4265 struct i915_vma
*ggtt_vma
= i915_gem_obj_to_ggtt(obj
);
4267 WARN_ON(!ggtt_vma
||
4268 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
>
4269 ggtt_vma
->pin_count
);
4270 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
4277 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
4279 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4280 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4281 WARN_ON(dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
<= 0);
4282 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
4287 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4288 struct drm_file
*file
)
4290 struct drm_i915_gem_busy
*args
= data
;
4291 struct drm_i915_gem_object
*obj
;
4294 ret
= i915_mutex_lock_interruptible(dev
);
4298 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4299 if (&obj
->base
== NULL
) {
4304 /* Count all active objects as busy, even if they are currently not used
4305 * by the gpu. Users of this interface expect objects to eventually
4306 * become non-busy without any further actions, therefore emit any
4307 * necessary flushes here.
4309 ret
= i915_gem_object_flush_active(obj
);
4311 args
->busy
= obj
->active
;
4313 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
4314 args
->busy
|= intel_ring_flag(obj
->ring
) << 16;
4317 drm_gem_object_unreference(&obj
->base
);
4319 mutex_unlock(&dev
->struct_mutex
);
4324 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4325 struct drm_file
*file_priv
)
4327 return i915_gem_ring_throttle(dev
, file_priv
);
4331 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4332 struct drm_file
*file_priv
)
4334 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4335 struct drm_i915_gem_madvise
*args
= data
;
4336 struct drm_i915_gem_object
*obj
;
4339 switch (args
->madv
) {
4340 case I915_MADV_DONTNEED
:
4341 case I915_MADV_WILLNEED
:
4347 ret
= i915_mutex_lock_interruptible(dev
);
4351 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
4352 if (&obj
->base
== NULL
) {
4357 if (i915_gem_obj_is_pinned(obj
)) {
4363 obj
->tiling_mode
!= I915_TILING_NONE
&&
4364 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
4365 if (obj
->madv
== I915_MADV_WILLNEED
)
4366 i915_gem_object_unpin_pages(obj
);
4367 if (args
->madv
== I915_MADV_WILLNEED
)
4368 i915_gem_object_pin_pages(obj
);
4371 if (obj
->madv
!= __I915_MADV_PURGED
)
4372 obj
->madv
= args
->madv
;
4374 /* if the object is no longer attached, discard its backing storage */
4375 if (i915_gem_object_is_purgeable(obj
) && obj
->pages
== NULL
)
4376 i915_gem_object_truncate(obj
);
4378 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4381 drm_gem_object_unreference(&obj
->base
);
4383 mutex_unlock(&dev
->struct_mutex
);
4387 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4388 const struct drm_i915_gem_object_ops
*ops
)
4390 INIT_LIST_HEAD(&obj
->global_list
);
4391 INIT_LIST_HEAD(&obj
->ring_list
);
4392 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4393 INIT_LIST_HEAD(&obj
->vma_list
);
4397 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4398 obj
->madv
= I915_MADV_WILLNEED
;
4400 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4403 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4404 .get_pages
= i915_gem_object_get_pages_gtt
,
4405 .put_pages
= i915_gem_object_put_pages_gtt
,
4408 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
4411 struct drm_i915_gem_object
*obj
;
4412 struct address_space
*mapping
;
4415 obj
= i915_gem_object_alloc(dev
);
4419 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4420 i915_gem_object_free(obj
);
4424 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4425 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4426 /* 965gm cannot relocate objects above 4GiB. */
4427 mask
&= ~__GFP_HIGHMEM
;
4428 mask
|= __GFP_DMA32
;
4431 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4432 mapping_set_gfp_mask(mapping
, mask
);
4434 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4436 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4437 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4440 /* On some devices, we can have the GPU use the LLC (the CPU
4441 * cache) for about a 10% performance improvement
4442 * compared to uncached. Graphics requests other than
4443 * display scanout are coherent with the CPU in
4444 * accessing this cache. This means in this mode we
4445 * don't need to clflush on the CPU side, and on the
4446 * GPU side we only need to flush internal caches to
4447 * get data visible to the CPU.
4449 * However, we maintain the display planes as UC, and so
4450 * need to rebind when first used as such.
4452 obj
->cache_level
= I915_CACHE_LLC
;
4454 obj
->cache_level
= I915_CACHE_NONE
;
4456 trace_i915_gem_object_create(obj
);
4461 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4463 /* If we are the last user of the backing storage (be it shmemfs
4464 * pages or stolen etc), we know that the pages are going to be
4465 * immediately released. In this case, we can then skip copying
4466 * back the contents from the GPU.
4469 if (obj
->madv
!= I915_MADV_WILLNEED
)
4472 if (obj
->base
.filp
== NULL
)
4475 /* At first glance, this looks racy, but then again so would be
4476 * userspace racing mmap against close. However, the first external
4477 * reference to the filp can only be obtained through the
4478 * i915_gem_mmap_ioctl() which safeguards us against the user
4479 * acquiring such a reference whilst we are in the middle of
4480 * freeing the object.
4482 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4485 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4487 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4488 struct drm_device
*dev
= obj
->base
.dev
;
4489 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4490 struct i915_vma
*vma
, *next
;
4492 intel_runtime_pm_get(dev_priv
);
4494 trace_i915_gem_object_destroy(obj
);
4496 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4500 ret
= i915_vma_unbind(vma
);
4501 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4502 bool was_interruptible
;
4504 was_interruptible
= dev_priv
->mm
.interruptible
;
4505 dev_priv
->mm
.interruptible
= false;
4507 WARN_ON(i915_vma_unbind(vma
));
4509 dev_priv
->mm
.interruptible
= was_interruptible
;
4513 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4514 * before progressing. */
4516 i915_gem_object_unpin_pages(obj
);
4518 WARN_ON(obj
->frontbuffer_bits
);
4520 if (obj
->pages
&& obj
->madv
== I915_MADV_WILLNEED
&&
4521 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
&&
4522 obj
->tiling_mode
!= I915_TILING_NONE
)
4523 i915_gem_object_unpin_pages(obj
);
4525 if (WARN_ON(obj
->pages_pin_count
))
4526 obj
->pages_pin_count
= 0;
4527 if (discard_backing_storage(obj
))
4528 obj
->madv
= I915_MADV_DONTNEED
;
4529 i915_gem_object_put_pages(obj
);
4530 i915_gem_object_free_mmap_offset(obj
);
4534 if (obj
->base
.import_attach
)
4535 drm_prime_gem_destroy(&obj
->base
, NULL
);
4537 if (obj
->ops
->release
)
4538 obj
->ops
->release(obj
);
4540 drm_gem_object_release(&obj
->base
);
4541 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4544 i915_gem_object_free(obj
);
4546 intel_runtime_pm_put(dev_priv
);
4549 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4550 struct i915_address_space
*vm
)
4552 struct i915_vma
*vma
;
4553 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4560 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4562 struct i915_address_space
*vm
= NULL
;
4563 WARN_ON(vma
->node
.allocated
);
4565 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4566 if (!list_empty(&vma
->exec_list
))
4571 if (!i915_is_ggtt(vm
))
4572 i915_ppgtt_put(i915_vm_to_ppgtt(vm
));
4574 list_del(&vma
->vma_link
);
4580 i915_gem_stop_ringbuffers(struct drm_device
*dev
)
4582 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4583 struct intel_engine_cs
*ring
;
4586 for_each_ring(ring
, dev_priv
, i
)
4587 dev_priv
->gt
.stop_ring(ring
);
4591 i915_gem_suspend(struct drm_device
*dev
)
4593 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4596 mutex_lock(&dev
->struct_mutex
);
4597 ret
= i915_gpu_idle(dev
);
4601 i915_gem_retire_requests(dev
);
4603 /* Under UMS, be paranoid and evict. */
4604 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4605 i915_gem_evict_everything(dev
);
4607 i915_gem_stop_ringbuffers(dev
);
4608 mutex_unlock(&dev
->struct_mutex
);
4610 del_timer_sync(&dev_priv
->gpu_error
.hangcheck_timer
);
4611 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4612 flush_delayed_work(&dev_priv
->mm
.idle_work
);
4614 /* Assert that we sucessfully flushed all the work and
4615 * reset the GPU back to its idle, low power state.
4617 WARN_ON(dev_priv
->mm
.busy
);
4622 mutex_unlock(&dev
->struct_mutex
);
4626 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
)
4628 struct drm_device
*dev
= ring
->dev
;
4629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4630 u32 reg_base
= GEN7_L3LOG_BASE
+ (slice
* 0x200);
4631 u32
*remap_info
= dev_priv
->l3_parity
.remap_info
[slice
];
4634 if (!HAS_L3_DPF(dev
) || !remap_info
)
4637 ret
= intel_ring_begin(ring
, GEN7_L3LOG_SIZE
/ 4 * 3);
4642 * Note: We do not worry about the concurrent register cacheline hang
4643 * here because no other code should access these registers other than
4644 * at initialization time.
4646 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
4647 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
4648 intel_ring_emit(ring
, reg_base
+ i
);
4649 intel_ring_emit(ring
, remap_info
[i
/4]);
4652 intel_ring_advance(ring
);
4657 void i915_gem_init_swizzling(struct drm_device
*dev
)
4659 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4661 if (INTEL_INFO(dev
)->gen
< 5 ||
4662 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4665 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4666 DISP_TILE_SURFACE_SWIZZLING
);
4671 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4673 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4674 else if (IS_GEN7(dev
))
4675 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4676 else if (IS_GEN8(dev
))
4677 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4683 intel_enable_blt(struct drm_device
*dev
)
4688 /* The blitter was dysfunctional on early prototypes */
4689 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
4690 DRM_INFO("BLT not supported on this pre-production hardware;"
4691 " graphics performance will be degraded.\n");
4698 static void init_unused_ring(struct drm_device
*dev
, u32 base
)
4700 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4702 I915_WRITE(RING_CTL(base
), 0);
4703 I915_WRITE(RING_HEAD(base
), 0);
4704 I915_WRITE(RING_TAIL(base
), 0);
4705 I915_WRITE(RING_START(base
), 0);
4708 static void init_unused_rings(struct drm_device
*dev
)
4711 init_unused_ring(dev
, PRB1_BASE
);
4712 init_unused_ring(dev
, SRB0_BASE
);
4713 init_unused_ring(dev
, SRB1_BASE
);
4714 init_unused_ring(dev
, SRB2_BASE
);
4715 init_unused_ring(dev
, SRB3_BASE
);
4716 } else if (IS_GEN2(dev
)) {
4717 init_unused_ring(dev
, SRB0_BASE
);
4718 init_unused_ring(dev
, SRB1_BASE
);
4719 } else if (IS_GEN3(dev
)) {
4720 init_unused_ring(dev
, PRB1_BASE
);
4721 init_unused_ring(dev
, PRB2_BASE
);
4725 int i915_gem_init_rings(struct drm_device
*dev
)
4727 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4731 * At least 830 can leave some of the unused rings
4732 * "active" (ie. head != tail) after resume which
4733 * will prevent c3 entry. Makes sure all unused rings
4736 init_unused_rings(dev
);
4738 ret
= intel_init_render_ring_buffer(dev
);
4743 ret
= intel_init_bsd_ring_buffer(dev
);
4745 goto cleanup_render_ring
;
4748 if (intel_enable_blt(dev
)) {
4749 ret
= intel_init_blt_ring_buffer(dev
);
4751 goto cleanup_bsd_ring
;
4754 if (HAS_VEBOX(dev
)) {
4755 ret
= intel_init_vebox_ring_buffer(dev
);
4757 goto cleanup_blt_ring
;
4760 if (HAS_BSD2(dev
)) {
4761 ret
= intel_init_bsd2_ring_buffer(dev
);
4763 goto cleanup_vebox_ring
;
4766 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
4768 goto cleanup_bsd2_ring
;
4773 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS2
]);
4775 intel_cleanup_ring_buffer(&dev_priv
->ring
[VECS
]);
4777 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
4779 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
4780 cleanup_render_ring
:
4781 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
4787 i915_gem_init_hw(struct drm_device
*dev
)
4789 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4792 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
4795 if (dev_priv
->ellc_size
)
4796 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4798 if (IS_HASWELL(dev
))
4799 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
4800 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
4802 if (HAS_PCH_NOP(dev
)) {
4803 if (IS_IVYBRIDGE(dev
)) {
4804 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4805 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4806 I915_WRITE(GEN7_MSG_CTL
, temp
);
4807 } else if (INTEL_INFO(dev
)->gen
>= 7) {
4808 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
4809 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
4810 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
4814 i915_gem_init_swizzling(dev
);
4816 ret
= dev_priv
->gt
.init_rings(dev
);
4820 for (i
= 0; i
< NUM_L3_SLICES(dev
); i
++)
4821 i915_gem_l3_remap(&dev_priv
->ring
[RCS
], i
);
4824 * XXX: Contexts should only be initialized once. Doing a switch to the
4825 * default context switch however is something we'd like to do after
4826 * reset or thaw (the latter may not actually be necessary for HW, but
4827 * goes with our code better). Context switching requires rings (for
4828 * the do_switch), but before enabling PPGTT. So don't move this.
4830 ret
= i915_gem_context_enable(dev_priv
);
4831 if (ret
&& ret
!= -EIO
) {
4832 DRM_ERROR("Context enable failed %d\n", ret
);
4833 i915_gem_cleanup_ringbuffer(dev
);
4838 ret
= i915_ppgtt_init_hw(dev
);
4839 if (ret
&& ret
!= -EIO
) {
4840 DRM_ERROR("PPGTT enable failed %d\n", ret
);
4841 i915_gem_cleanup_ringbuffer(dev
);
4847 int i915_gem_init(struct drm_device
*dev
)
4849 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4852 i915
.enable_execlists
= intel_sanitize_enable_execlists(dev
,
4853 i915
.enable_execlists
);
4855 mutex_lock(&dev
->struct_mutex
);
4857 if (IS_VALLEYVIEW(dev
)) {
4858 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4859 I915_WRITE(VLV_GTLC_WAKE_CTRL
, VLV_GTLC_ALLOWWAKEREQ
);
4860 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS
) &
4861 VLV_GTLC_ALLOWWAKEACK
), 10))
4862 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4865 if (!i915
.enable_execlists
) {
4866 dev_priv
->gt
.do_execbuf
= i915_gem_ringbuffer_submission
;
4867 dev_priv
->gt
.init_rings
= i915_gem_init_rings
;
4868 dev_priv
->gt
.cleanup_ring
= intel_cleanup_ring_buffer
;
4869 dev_priv
->gt
.stop_ring
= intel_stop_ring_buffer
;
4871 dev_priv
->gt
.do_execbuf
= intel_execlists_submission
;
4872 dev_priv
->gt
.init_rings
= intel_logical_rings_init
;
4873 dev_priv
->gt
.cleanup_ring
= intel_logical_ring_cleanup
;
4874 dev_priv
->gt
.stop_ring
= intel_logical_ring_stop
;
4877 ret
= i915_gem_init_userptr(dev
);
4879 mutex_unlock(&dev
->struct_mutex
);
4883 i915_gem_init_global_gtt(dev
);
4885 ret
= i915_gem_context_init(dev
);
4887 mutex_unlock(&dev
->struct_mutex
);
4891 ret
= i915_gem_init_hw(dev
);
4893 /* Allow ring initialisation to fail by marking the GPU as
4894 * wedged. But we only want to do this where the GPU is angry,
4895 * for all other failure, such as an allocation failure, bail.
4897 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4898 atomic_set_mask(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
4901 mutex_unlock(&dev
->struct_mutex
);
4907 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4909 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4910 struct intel_engine_cs
*ring
;
4913 for_each_ring(ring
, dev_priv
, i
)
4914 dev_priv
->gt
.cleanup_ring(ring
);
4918 init_ring_lists(struct intel_engine_cs
*ring
)
4920 INIT_LIST_HEAD(&ring
->active_list
);
4921 INIT_LIST_HEAD(&ring
->request_list
);
4924 void i915_init_vm(struct drm_i915_private
*dev_priv
,
4925 struct i915_address_space
*vm
)
4927 if (!i915_is_ggtt(vm
))
4928 drm_mm_init(&vm
->mm
, vm
->start
, vm
->total
);
4929 vm
->dev
= dev_priv
->dev
;
4930 INIT_LIST_HEAD(&vm
->active_list
);
4931 INIT_LIST_HEAD(&vm
->inactive_list
);
4932 INIT_LIST_HEAD(&vm
->global_link
);
4933 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
4937 i915_gem_load(struct drm_device
*dev
)
4939 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4943 kmem_cache_create("i915_gem_object",
4944 sizeof(struct drm_i915_gem_object
), 0,
4948 INIT_LIST_HEAD(&dev_priv
->vm_list
);
4949 i915_init_vm(dev_priv
, &dev_priv
->gtt
.base
);
4951 INIT_LIST_HEAD(&dev_priv
->context_list
);
4952 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4953 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4954 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4955 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4956 init_ring_lists(&dev_priv
->ring
[i
]);
4957 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
4958 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4959 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4960 i915_gem_retire_work_handler
);
4961 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
4962 i915_gem_idle_work_handler
);
4963 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
4965 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4966 if (!drm_core_check_feature(dev
, DRIVER_MODESET
) && IS_GEN3(dev
)) {
4967 I915_WRITE(MI_ARB_STATE
,
4968 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
4971 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4973 /* Old X drivers will take 0-2 for front, back, depth buffers */
4974 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4975 dev_priv
->fence_reg_start
= 3;
4977 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
))
4978 dev_priv
->num_fence_regs
= 32;
4979 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4980 dev_priv
->num_fence_regs
= 16;
4982 dev_priv
->num_fence_regs
= 8;
4984 /* Initialize fence registers to zero */
4985 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4986 i915_gem_restore_fences(dev
);
4988 i915_gem_detect_bit_6_swizzle(dev
);
4989 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4991 dev_priv
->mm
.interruptible
= true;
4993 dev_priv
->mm
.shrinker
.scan_objects
= i915_gem_shrinker_scan
;
4994 dev_priv
->mm
.shrinker
.count_objects
= i915_gem_shrinker_count
;
4995 dev_priv
->mm
.shrinker
.seeks
= DEFAULT_SEEKS
;
4996 register_shrinker(&dev_priv
->mm
.shrinker
);
4998 dev_priv
->mm
.oom_notifier
.notifier_call
= i915_gem_shrinker_oom
;
4999 register_oom_notifier(&dev_priv
->mm
.oom_notifier
);
5001 mutex_init(&dev_priv
->fb_tracking
.lock
);
5004 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5006 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5008 cancel_delayed_work_sync(&file_priv
->mm
.idle_work
);
5010 /* Clean up our request list when the client is going away, so that
5011 * later retire_requests won't dereference our soon-to-be-gone
5014 spin_lock(&file_priv
->mm
.lock
);
5015 while (!list_empty(&file_priv
->mm
.request_list
)) {
5016 struct drm_i915_gem_request
*request
;
5018 request
= list_first_entry(&file_priv
->mm
.request_list
,
5019 struct drm_i915_gem_request
,
5021 list_del(&request
->client_list
);
5022 request
->file_priv
= NULL
;
5024 spin_unlock(&file_priv
->mm
.lock
);
5028 i915_gem_file_idle_work_handler(struct work_struct
*work
)
5030 struct drm_i915_file_private
*file_priv
=
5031 container_of(work
, typeof(*file_priv
), mm
.idle_work
.work
);
5033 atomic_set(&file_priv
->rps_wait_boost
, false);
5036 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
5038 struct drm_i915_file_private
*file_priv
;
5041 DRM_DEBUG_DRIVER("\n");
5043 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
5047 file
->driver_priv
= file_priv
;
5048 file_priv
->dev_priv
= dev
->dev_private
;
5049 file_priv
->file
= file
;
5051 spin_lock_init(&file_priv
->mm
.lock
);
5052 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
5053 INIT_DELAYED_WORK(&file_priv
->mm
.idle_work
,
5054 i915_gem_file_idle_work_handler
);
5056 ret
= i915_gem_context_open(dev
, file
);
5064 * i915_gem_track_fb - update frontbuffer tracking
5065 * old: current GEM buffer for the frontbuffer slots
5066 * new: new GEM buffer for the frontbuffer slots
5067 * frontbuffer_bits: bitmask of frontbuffer slots
5069 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5070 * from @old and setting them in @new. Both @old and @new can be NULL.
5072 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
5073 struct drm_i915_gem_object
*new,
5074 unsigned frontbuffer_bits
)
5077 WARN_ON(!mutex_is_locked(&old
->base
.dev
->struct_mutex
));
5078 WARN_ON(!(old
->frontbuffer_bits
& frontbuffer_bits
));
5079 old
->frontbuffer_bits
&= ~frontbuffer_bits
;
5083 WARN_ON(!mutex_is_locked(&new->base
.dev
->struct_mutex
));
5084 WARN_ON(new->frontbuffer_bits
& frontbuffer_bits
);
5085 new->frontbuffer_bits
|= frontbuffer_bits
;
5089 static bool mutex_is_locked_by(struct mutex
*mutex
, struct task_struct
*task
)
5091 if (!mutex_is_locked(mutex
))
5094 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5095 return mutex
->owner
== task
;
5097 /* Since UP may be pre-empted, we cannot assume that we own the lock */
5102 static bool i915_gem_shrinker_lock(struct drm_device
*dev
, bool *unlock
)
5104 if (!mutex_trylock(&dev
->struct_mutex
)) {
5105 if (!mutex_is_locked_by(&dev
->struct_mutex
, current
))
5108 if (to_i915(dev
)->mm
.shrinker_no_lock_stealing
)
5118 static int num_vma_bound(struct drm_i915_gem_object
*obj
)
5120 struct i915_vma
*vma
;
5123 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
5124 if (drm_mm_node_allocated(&vma
->node
))
5130 static unsigned long
5131 i915_gem_shrinker_count(struct shrinker
*shrinker
, struct shrink_control
*sc
)
5133 struct drm_i915_private
*dev_priv
=
5134 container_of(shrinker
, struct drm_i915_private
, mm
.shrinker
);
5135 struct drm_device
*dev
= dev_priv
->dev
;
5136 struct drm_i915_gem_object
*obj
;
5137 unsigned long count
;
5140 if (!i915_gem_shrinker_lock(dev
, &unlock
))
5144 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
)
5145 if (obj
->pages_pin_count
== 0)
5146 count
+= obj
->base
.size
>> PAGE_SHIFT
;
5148 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
5149 if (!i915_gem_obj_is_pinned(obj
) &&
5150 obj
->pages_pin_count
== num_vma_bound(obj
))
5151 count
+= obj
->base
.size
>> PAGE_SHIFT
;
5155 mutex_unlock(&dev
->struct_mutex
);
5160 /* All the new VM stuff */
5161 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
5162 struct i915_address_space
*vm
)
5164 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5165 struct i915_vma
*vma
;
5167 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5169 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5171 return vma
->node
.start
;
5174 WARN(1, "%s vma for this object not found.\n",
5175 i915_is_ggtt(vm
) ? "global" : "ppgtt");
5179 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
5180 struct i915_address_space
*vm
)
5182 struct i915_vma
*vma
;
5184 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5185 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
5191 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
5193 struct i915_vma
*vma
;
5195 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5196 if (drm_mm_node_allocated(&vma
->node
))
5202 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
5203 struct i915_address_space
*vm
)
5205 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5206 struct i915_vma
*vma
;
5208 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5210 BUG_ON(list_empty(&o
->vma_list
));
5212 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5214 return vma
->node
.size
;
5219 static unsigned long
5220 i915_gem_shrinker_scan(struct shrinker
*shrinker
, struct shrink_control
*sc
)
5222 struct drm_i915_private
*dev_priv
=
5223 container_of(shrinker
, struct drm_i915_private
, mm
.shrinker
);
5224 struct drm_device
*dev
= dev_priv
->dev
;
5225 unsigned long freed
;
5228 if (!i915_gem_shrinker_lock(dev
, &unlock
))
5231 freed
= i915_gem_shrink(dev_priv
,
5234 I915_SHRINK_UNBOUND
|
5235 I915_SHRINK_PURGEABLE
);
5236 if (freed
< sc
->nr_to_scan
)
5237 freed
+= i915_gem_shrink(dev_priv
,
5238 sc
->nr_to_scan
- freed
,
5240 I915_SHRINK_UNBOUND
);
5242 mutex_unlock(&dev
->struct_mutex
);
5248 i915_gem_shrinker_oom(struct notifier_block
*nb
, unsigned long event
, void *ptr
)
5250 struct drm_i915_private
*dev_priv
=
5251 container_of(nb
, struct drm_i915_private
, mm
.oom_notifier
);
5252 struct drm_device
*dev
= dev_priv
->dev
;
5253 struct drm_i915_gem_object
*obj
;
5254 unsigned long timeout
= msecs_to_jiffies(5000) + 1;
5255 unsigned long pinned
, bound
, unbound
, freed_pages
;
5256 bool was_interruptible
;
5259 while (!i915_gem_shrinker_lock(dev
, &unlock
) && --timeout
) {
5260 schedule_timeout_killable(1);
5261 if (fatal_signal_pending(current
))
5265 pr_err("Unable to purge GPU memory due lock contention.\n");
5269 was_interruptible
= dev_priv
->mm
.interruptible
;
5270 dev_priv
->mm
.interruptible
= false;
5272 freed_pages
= i915_gem_shrink_all(dev_priv
);
5274 dev_priv
->mm
.interruptible
= was_interruptible
;
5276 /* Because we may be allocating inside our own driver, we cannot
5277 * assert that there are no objects with pinned pages that are not
5278 * being pointed to by hardware.
5280 unbound
= bound
= pinned
= 0;
5281 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
5282 if (!obj
->base
.filp
) /* not backed by a freeable object */
5285 if (obj
->pages_pin_count
)
5286 pinned
+= obj
->base
.size
;
5288 unbound
+= obj
->base
.size
;
5290 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
5291 if (!obj
->base
.filp
)
5294 if (obj
->pages_pin_count
)
5295 pinned
+= obj
->base
.size
;
5297 bound
+= obj
->base
.size
;
5301 mutex_unlock(&dev
->struct_mutex
);
5303 if (freed_pages
|| unbound
|| bound
)
5304 pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5305 freed_pages
<< PAGE_SHIFT
, pinned
);
5306 if (unbound
|| bound
)
5307 pr_err("%lu and %lu bytes still available in the "
5308 "bound and unbound GPU page lists.\n",
5311 *(unsigned long *)ptr
+= freed_pages
;
5315 struct i915_vma
*i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
)
5317 struct i915_vma
*vma
;
5319 vma
= list_first_entry(&obj
->vma_list
, typeof(*vma
), vma_link
);
5320 if (vma
->vm
!= i915_obj_to_ggtt(obj
))