2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
38 #include <linux/dma-buf.h>
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
42 static __must_check
int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
44 bool map_and_fenceable
);
45 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
46 struct drm_i915_gem_object
*obj
,
47 struct drm_i915_gem_pwrite
*args
,
48 struct drm_file
*file
);
50 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
51 struct drm_i915_gem_object
*obj
);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
53 struct drm_i915_fence_reg
*fence
,
56 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
57 struct shrink_control
*sc
);
58 static void i915_gem_object_truncate(struct drm_i915_gem_object
*obj
);
60 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
63 i915_gem_release_mmap(obj
);
65 /* As we do not have an associated fence register, we will force
66 * a tiling change if we ever need to acquire one.
68 obj
->fence_dirty
= false;
69 obj
->fence_reg
= I915_FENCE_REG_NONE
;
72 /* some bookkeeping */
73 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
76 dev_priv
->mm
.object_count
++;
77 dev_priv
->mm
.object_memory
+= size
;
80 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
83 dev_priv
->mm
.object_count
--;
84 dev_priv
->mm
.object_memory
-= size
;
88 i915_gem_wait_for_error(struct drm_device
*dev
)
90 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
91 struct completion
*x
= &dev_priv
->error_completion
;
95 if (!atomic_read(&dev_priv
->mm
.wedged
))
99 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
100 * userspace. If it takes that long something really bad is going on and
101 * we should simply try to bail out and fail as gracefully as possible.
103 ret
= wait_for_completion_interruptible_timeout(x
, 10*HZ
);
105 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
107 } else if (ret
< 0) {
111 if (atomic_read(&dev_priv
->mm
.wedged
)) {
112 /* GPU is hung, bump the completion count to account for
113 * the token we just consumed so that we never hit zero and
114 * end up waiting upon a subsequent completion event that
117 spin_lock_irqsave(&x
->wait
.lock
, flags
);
119 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
124 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
128 ret
= i915_gem_wait_for_error(dev
);
132 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
136 WARN_ON(i915_verify_lists(dev
));
141 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
147 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
148 struct drm_file
*file
)
150 struct drm_i915_gem_init
*args
= data
;
152 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
155 if (args
->gtt_start
>= args
->gtt_end
||
156 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
159 /* GEM with user mode setting was never supported on ilk and later. */
160 if (INTEL_INFO(dev
)->gen
>= 5)
163 mutex_lock(&dev
->struct_mutex
);
164 i915_gem_init_global_gtt(dev
, args
->gtt_start
,
165 args
->gtt_end
, args
->gtt_end
);
166 mutex_unlock(&dev
->struct_mutex
);
172 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
173 struct drm_file
*file
)
175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
176 struct drm_i915_gem_get_aperture
*args
= data
;
177 struct drm_i915_gem_object
*obj
;
181 mutex_lock(&dev
->struct_mutex
);
182 list_for_each_entry(obj
, &dev_priv
->mm
.gtt_list
, gtt_list
)
184 pinned
+= obj
->gtt_space
->size
;
185 mutex_unlock(&dev
->struct_mutex
);
187 args
->aper_size
= dev_priv
->mm
.gtt_total
;
188 args
->aper_available_size
= args
->aper_size
- pinned
;
194 i915_gem_create(struct drm_file
*file
,
195 struct drm_device
*dev
,
199 struct drm_i915_gem_object
*obj
;
203 size
= roundup(size
, PAGE_SIZE
);
207 /* Allocate the new object */
208 obj
= i915_gem_alloc_object(dev
, size
);
212 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
214 drm_gem_object_release(&obj
->base
);
215 i915_gem_info_remove_obj(dev
->dev_private
, obj
->base
.size
);
220 /* drop reference from allocate - handle holds it now */
221 drm_gem_object_unreference(&obj
->base
);
222 trace_i915_gem_object_create(obj
);
229 i915_gem_dumb_create(struct drm_file
*file
,
230 struct drm_device
*dev
,
231 struct drm_mode_create_dumb
*args
)
233 /* have to work out size/pitch and return them */
234 args
->pitch
= ALIGN(args
->width
* ((args
->bpp
+ 7) / 8), 64);
235 args
->size
= args
->pitch
* args
->height
;
236 return i915_gem_create(file
, dev
,
237 args
->size
, &args
->handle
);
240 int i915_gem_dumb_destroy(struct drm_file
*file
,
241 struct drm_device
*dev
,
244 return drm_gem_handle_delete(file
, handle
);
248 * Creates a new mm object and returns a handle to it.
251 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
252 struct drm_file
*file
)
254 struct drm_i915_gem_create
*args
= data
;
256 return i915_gem_create(file
, dev
,
257 args
->size
, &args
->handle
);
260 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
262 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
264 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
265 obj
->tiling_mode
!= I915_TILING_NONE
;
269 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
270 const char *gpu_vaddr
, int gpu_offset
,
273 int ret
, cpu_offset
= 0;
276 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
277 int this_length
= min(cacheline_end
- gpu_offset
, length
);
278 int swizzled_gpu_offset
= gpu_offset
^ 64;
280 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
281 gpu_vaddr
+ swizzled_gpu_offset
,
286 cpu_offset
+= this_length
;
287 gpu_offset
+= this_length
;
288 length
-= this_length
;
295 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
296 const char __user
*cpu_vaddr
,
299 int ret
, cpu_offset
= 0;
302 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
303 int this_length
= min(cacheline_end
- gpu_offset
, length
);
304 int swizzled_gpu_offset
= gpu_offset
^ 64;
306 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
307 cpu_vaddr
+ cpu_offset
,
312 cpu_offset
+= this_length
;
313 gpu_offset
+= this_length
;
314 length
-= this_length
;
320 /* Per-page copy function for the shmem pread fastpath.
321 * Flushes invalid cachelines before reading the target if
322 * needs_clflush is set. */
324 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
325 char __user
*user_data
,
326 bool page_do_bit17_swizzling
, bool needs_clflush
)
331 if (unlikely(page_do_bit17_swizzling
))
334 vaddr
= kmap_atomic(page
);
336 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
338 ret
= __copy_to_user_inatomic(user_data
,
339 vaddr
+ shmem_page_offset
,
341 kunmap_atomic(vaddr
);
347 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
350 if (unlikely(swizzled
)) {
351 unsigned long start
= (unsigned long) addr
;
352 unsigned long end
= (unsigned long) addr
+ length
;
354 /* For swizzling simply ensure that we always flush both
355 * channels. Lame, but simple and it works. Swizzled
356 * pwrite/pread is far from a hotpath - current userspace
357 * doesn't use it at all. */
358 start
= round_down(start
, 128);
359 end
= round_up(end
, 128);
361 drm_clflush_virt_range((void *)start
, end
- start
);
363 drm_clflush_virt_range(addr
, length
);
368 /* Only difference to the fast-path function is that this can handle bit17
369 * and uses non-atomic copy and kmap functions. */
371 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
372 char __user
*user_data
,
373 bool page_do_bit17_swizzling
, bool needs_clflush
)
380 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
382 page_do_bit17_swizzling
);
384 if (page_do_bit17_swizzling
)
385 ret
= __copy_to_user_swizzled(user_data
,
386 vaddr
, shmem_page_offset
,
389 ret
= __copy_to_user(user_data
,
390 vaddr
+ shmem_page_offset
,
398 i915_gem_shmem_pread(struct drm_device
*dev
,
399 struct drm_i915_gem_object
*obj
,
400 struct drm_i915_gem_pread
*args
,
401 struct drm_file
*file
)
403 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
404 char __user
*user_data
;
407 int shmem_page_offset
, page_length
, ret
= 0;
408 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
409 int hit_slowpath
= 0;
411 int needs_clflush
= 0;
414 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
417 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
419 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
420 /* If we're not in the cpu read domain, set ourself into the gtt
421 * read domain and manually flush cachelines (if required). This
422 * optimizes for the case when the gpu will dirty the data
423 * anyway again before the next pread happens. */
424 if (obj
->cache_level
== I915_CACHE_NONE
)
426 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
431 offset
= args
->offset
;
436 /* Operation in this page
438 * shmem_page_offset = offset within page in shmem file
439 * page_length = bytes to copy for this page
441 shmem_page_offset
= offset_in_page(offset
);
442 page_length
= remain
;
443 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
444 page_length
= PAGE_SIZE
- shmem_page_offset
;
447 page
= obj
->pages
[offset
>> PAGE_SHIFT
];
450 page
= shmem_read_mapping_page(mapping
, offset
>> PAGE_SHIFT
);
458 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
459 (page_to_phys(page
) & (1 << 17)) != 0;
461 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
462 user_data
, page_do_bit17_swizzling
,
468 page_cache_get(page
);
469 mutex_unlock(&dev
->struct_mutex
);
472 ret
= fault_in_multipages_writeable(user_data
, remain
);
473 /* Userspace is tricking us, but we've already clobbered
474 * its pages with the prefault and promised to write the
475 * data up to the first fault. Hence ignore any errors
476 * and just continue. */
481 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
482 user_data
, page_do_bit17_swizzling
,
485 mutex_lock(&dev
->struct_mutex
);
486 page_cache_release(page
);
488 mark_page_accessed(page
);
490 page_cache_release(page
);
497 remain
-= page_length
;
498 user_data
+= page_length
;
499 offset
+= page_length
;
504 /* Fixup: Kill any reinstated backing storage pages */
505 if (obj
->madv
== __I915_MADV_PURGED
)
506 i915_gem_object_truncate(obj
);
513 * Reads data from the object referenced by handle.
515 * On error, the contents of *data are undefined.
518 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
519 struct drm_file
*file
)
521 struct drm_i915_gem_pread
*args
= data
;
522 struct drm_i915_gem_object
*obj
;
528 if (!access_ok(VERIFY_WRITE
,
529 (char __user
*)(uintptr_t)args
->data_ptr
,
533 ret
= i915_mutex_lock_interruptible(dev
);
537 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
538 if (&obj
->base
== NULL
) {
543 /* Bounds check source. */
544 if (args
->offset
> obj
->base
.size
||
545 args
->size
> obj
->base
.size
- args
->offset
) {
550 /* prime objects have no backing filp to GEM pread/pwrite
553 if (!obj
->base
.filp
) {
558 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
560 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
563 drm_gem_object_unreference(&obj
->base
);
565 mutex_unlock(&dev
->struct_mutex
);
569 /* This is the fast write path which cannot handle
570 * page faults in the source data
574 fast_user_write(struct io_mapping
*mapping
,
575 loff_t page_base
, int page_offset
,
576 char __user
*user_data
,
579 void __iomem
*vaddr_atomic
;
581 unsigned long unwritten
;
583 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
584 /* We can use the cpu mem copy function because this is X86. */
585 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
586 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
588 io_mapping_unmap_atomic(vaddr_atomic
);
593 * This is the fast pwrite path, where we copy the data directly from the
594 * user into the GTT, uncached.
597 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
598 struct drm_i915_gem_object
*obj
,
599 struct drm_i915_gem_pwrite
*args
,
600 struct drm_file
*file
)
602 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
604 loff_t offset
, page_base
;
605 char __user
*user_data
;
606 int page_offset
, page_length
, ret
;
608 ret
= i915_gem_object_pin(obj
, 0, true);
612 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
616 ret
= i915_gem_object_put_fence(obj
);
620 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
623 offset
= obj
->gtt_offset
+ args
->offset
;
626 /* Operation in this page
628 * page_base = page offset within aperture
629 * page_offset = offset within page
630 * page_length = bytes to copy for this page
632 page_base
= offset
& PAGE_MASK
;
633 page_offset
= offset_in_page(offset
);
634 page_length
= remain
;
635 if ((page_offset
+ remain
) > PAGE_SIZE
)
636 page_length
= PAGE_SIZE
- page_offset
;
638 /* If we get a fault while copying data, then (presumably) our
639 * source page isn't available. Return the error and we'll
640 * retry in the slow path.
642 if (fast_user_write(dev_priv
->mm
.gtt_mapping
, page_base
,
643 page_offset
, user_data
, page_length
)) {
648 remain
-= page_length
;
649 user_data
+= page_length
;
650 offset
+= page_length
;
654 i915_gem_object_unpin(obj
);
659 /* Per-page copy function for the shmem pwrite fastpath.
660 * Flushes invalid cachelines before writing to the target if
661 * needs_clflush_before is set and flushes out any written cachelines after
662 * writing if needs_clflush is set. */
664 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
665 char __user
*user_data
,
666 bool page_do_bit17_swizzling
,
667 bool needs_clflush_before
,
668 bool needs_clflush_after
)
673 if (unlikely(page_do_bit17_swizzling
))
676 vaddr
= kmap_atomic(page
);
677 if (needs_clflush_before
)
678 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
680 ret
= __copy_from_user_inatomic_nocache(vaddr
+ shmem_page_offset
,
683 if (needs_clflush_after
)
684 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
686 kunmap_atomic(vaddr
);
691 /* Only difference to the fast-path function is that this can handle bit17
692 * and uses non-atomic copy and kmap functions. */
694 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
695 char __user
*user_data
,
696 bool page_do_bit17_swizzling
,
697 bool needs_clflush_before
,
698 bool needs_clflush_after
)
704 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
705 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
707 page_do_bit17_swizzling
);
708 if (page_do_bit17_swizzling
)
709 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
713 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
716 if (needs_clflush_after
)
717 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
719 page_do_bit17_swizzling
);
726 i915_gem_shmem_pwrite(struct drm_device
*dev
,
727 struct drm_i915_gem_object
*obj
,
728 struct drm_i915_gem_pwrite
*args
,
729 struct drm_file
*file
)
731 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
734 char __user
*user_data
;
735 int shmem_page_offset
, page_length
, ret
= 0;
736 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
737 int hit_slowpath
= 0;
738 int needs_clflush_after
= 0;
739 int needs_clflush_before
= 0;
742 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
745 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
747 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
748 /* If we're not in the cpu write domain, set ourself into the gtt
749 * write domain and manually flush cachelines (if required). This
750 * optimizes for the case when the gpu will use the data
751 * right away and we therefore have to clflush anyway. */
752 if (obj
->cache_level
== I915_CACHE_NONE
)
753 needs_clflush_after
= 1;
754 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
758 /* Same trick applies for invalidate partially written cachelines before
760 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)
761 && obj
->cache_level
== I915_CACHE_NONE
)
762 needs_clflush_before
= 1;
764 offset
= args
->offset
;
769 int partial_cacheline_write
;
771 /* Operation in this page
773 * shmem_page_offset = offset within page in shmem file
774 * page_length = bytes to copy for this page
776 shmem_page_offset
= offset_in_page(offset
);
778 page_length
= remain
;
779 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
780 page_length
= PAGE_SIZE
- shmem_page_offset
;
782 /* If we don't overwrite a cacheline completely we need to be
783 * careful to have up-to-date data by first clflushing. Don't
784 * overcomplicate things and flush the entire patch. */
785 partial_cacheline_write
= needs_clflush_before
&&
786 ((shmem_page_offset
| page_length
)
787 & (boot_cpu_data
.x86_clflush_size
- 1));
790 page
= obj
->pages
[offset
>> PAGE_SHIFT
];
793 page
= shmem_read_mapping_page(mapping
, offset
>> PAGE_SHIFT
);
801 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
802 (page_to_phys(page
) & (1 << 17)) != 0;
804 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
805 user_data
, page_do_bit17_swizzling
,
806 partial_cacheline_write
,
807 needs_clflush_after
);
812 page_cache_get(page
);
813 mutex_unlock(&dev
->struct_mutex
);
815 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
816 user_data
, page_do_bit17_swizzling
,
817 partial_cacheline_write
,
818 needs_clflush_after
);
820 mutex_lock(&dev
->struct_mutex
);
821 page_cache_release(page
);
823 set_page_dirty(page
);
824 mark_page_accessed(page
);
826 page_cache_release(page
);
833 remain
-= page_length
;
834 user_data
+= page_length
;
835 offset
+= page_length
;
840 /* Fixup: Kill any reinstated backing storage pages */
841 if (obj
->madv
== __I915_MADV_PURGED
)
842 i915_gem_object_truncate(obj
);
843 /* and flush dirty cachelines in case the object isn't in the cpu write
845 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
846 i915_gem_clflush_object(obj
);
847 intel_gtt_chipset_flush();
851 if (needs_clflush_after
)
852 intel_gtt_chipset_flush();
858 * Writes data to the object referenced by handle.
860 * On error, the contents of the buffer that were to be modified are undefined.
863 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
864 struct drm_file
*file
)
866 struct drm_i915_gem_pwrite
*args
= data
;
867 struct drm_i915_gem_object
*obj
;
873 if (!access_ok(VERIFY_READ
,
874 (char __user
*)(uintptr_t)args
->data_ptr
,
878 ret
= fault_in_multipages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
883 ret
= i915_mutex_lock_interruptible(dev
);
887 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
888 if (&obj
->base
== NULL
) {
893 /* Bounds check destination. */
894 if (args
->offset
> obj
->base
.size
||
895 args
->size
> obj
->base
.size
- args
->offset
) {
900 /* prime objects have no backing filp to GEM pread/pwrite
903 if (!obj
->base
.filp
) {
908 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
911 /* We can only do the GTT pwrite on untiled buffers, as otherwise
912 * it would end up going through the fenced access, and we'll get
913 * different detiling behavior between reading and writing.
914 * pread/pwrite currently are reading and writing from the CPU
915 * perspective, requiring manual detiling by the client.
918 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
922 if (obj
->gtt_space
&&
923 obj
->cache_level
== I915_CACHE_NONE
&&
924 obj
->tiling_mode
== I915_TILING_NONE
&&
925 obj
->map_and_fenceable
&&
926 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
927 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
928 /* Note that the gtt paths might fail with non-page-backed user
929 * pointers (e.g. gtt mappings when moving data between
930 * textures). Fallback to the shmem path in that case. */
934 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
937 drm_gem_object_unreference(&obj
->base
);
939 mutex_unlock(&dev
->struct_mutex
);
944 * Called when user space prepares to use an object with the CPU, either
945 * through the mmap ioctl's mapping or a GTT mapping.
948 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
949 struct drm_file
*file
)
951 struct drm_i915_gem_set_domain
*args
= data
;
952 struct drm_i915_gem_object
*obj
;
953 uint32_t read_domains
= args
->read_domains
;
954 uint32_t write_domain
= args
->write_domain
;
957 /* Only handle setting domains to types used by the CPU. */
958 if (write_domain
& I915_GEM_GPU_DOMAINS
)
961 if (read_domains
& I915_GEM_GPU_DOMAINS
)
964 /* Having something in the write domain implies it's in the read
965 * domain, and only that read domain. Enforce that in the request.
967 if (write_domain
!= 0 && read_domains
!= write_domain
)
970 ret
= i915_mutex_lock_interruptible(dev
);
974 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
975 if (&obj
->base
== NULL
) {
980 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
981 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
983 /* Silently promote "you're not bound, there was nothing to do"
984 * to success, since the client was just asking us to
985 * make sure everything was done.
990 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
993 drm_gem_object_unreference(&obj
->base
);
995 mutex_unlock(&dev
->struct_mutex
);
1000 * Called when user space has done writes to this buffer
1003 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1004 struct drm_file
*file
)
1006 struct drm_i915_gem_sw_finish
*args
= data
;
1007 struct drm_i915_gem_object
*obj
;
1010 ret
= i915_mutex_lock_interruptible(dev
);
1014 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1015 if (&obj
->base
== NULL
) {
1020 /* Pinned buffers may be scanout, so flush the cache */
1022 i915_gem_object_flush_cpu_write_domain(obj
);
1024 drm_gem_object_unreference(&obj
->base
);
1026 mutex_unlock(&dev
->struct_mutex
);
1031 * Maps the contents of an object, returning the address it is mapped
1034 * While the mapping holds a reference on the contents of the object, it doesn't
1035 * imply a ref on the object itself.
1038 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1039 struct drm_file
*file
)
1041 struct drm_i915_gem_mmap
*args
= data
;
1042 struct drm_gem_object
*obj
;
1045 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1049 /* prime objects have no backing filp to GEM mmap
1053 drm_gem_object_unreference_unlocked(obj
);
1057 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1058 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1060 drm_gem_object_unreference_unlocked(obj
);
1061 if (IS_ERR((void *)addr
))
1064 args
->addr_ptr
= (uint64_t) addr
;
1070 * i915_gem_fault - fault a page into the GTT
1071 * vma: VMA in question
1074 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1075 * from userspace. The fault handler takes care of binding the object to
1076 * the GTT (if needed), allocating and programming a fence register (again,
1077 * only if needed based on whether the old reg is still valid or the object
1078 * is tiled) and inserting a new PTE into the faulting process.
1080 * Note that the faulting process may involve evicting existing objects
1081 * from the GTT and/or fence registers to make room. So performance may
1082 * suffer if the GTT working set is large or there are few fence registers
1085 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1087 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1088 struct drm_device
*dev
= obj
->base
.dev
;
1089 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1090 pgoff_t page_offset
;
1093 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1095 /* We don't use vmf->pgoff since that has the fake offset */
1096 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1099 ret
= i915_mutex_lock_interruptible(dev
);
1103 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1105 /* Now bind it into the GTT if needed */
1106 if (!obj
->map_and_fenceable
) {
1107 ret
= i915_gem_object_unbind(obj
);
1111 if (!obj
->gtt_space
) {
1112 ret
= i915_gem_object_bind_to_gtt(obj
, 0, true);
1116 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1121 if (!obj
->has_global_gtt_mapping
)
1122 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
1124 ret
= i915_gem_object_get_fence(obj
);
1128 if (i915_gem_object_is_inactive(obj
))
1129 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1131 obj
->fault_mappable
= true;
1133 pfn
= ((dev_priv
->mm
.gtt_base_addr
+ obj
->gtt_offset
) >> PAGE_SHIFT
) +
1136 /* Finally, remap it using the new GTT offset */
1137 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1139 mutex_unlock(&dev
->struct_mutex
);
1143 /* If this -EIO is due to a gpu hang, give the reset code a
1144 * chance to clean up the mess. Otherwise return the proper
1146 if (!atomic_read(&dev_priv
->mm
.wedged
))
1147 return VM_FAULT_SIGBUS
;
1149 /* Give the error handler a chance to run and move the
1150 * objects off the GPU active list. Next time we service the
1151 * fault, we should be able to transition the page into the
1152 * GTT without touching the GPU (and so avoid further
1153 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1154 * with coherency, just lost writes.
1160 return VM_FAULT_NOPAGE
;
1162 return VM_FAULT_OOM
;
1164 return VM_FAULT_SIGBUS
;
1169 * i915_gem_release_mmap - remove physical page mappings
1170 * @obj: obj in question
1172 * Preserve the reservation of the mmapping with the DRM core code, but
1173 * relinquish ownership of the pages back to the system.
1175 * It is vital that we remove the page mapping if we have mapped a tiled
1176 * object through the GTT and then lose the fence register due to
1177 * resource pressure. Similarly if the object has been moved out of the
1178 * aperture, than pages mapped into userspace must be revoked. Removing the
1179 * mapping will then trigger a page fault on the next user access, allowing
1180 * fixup by i915_gem_fault().
1183 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1185 if (!obj
->fault_mappable
)
1188 if (obj
->base
.dev
->dev_mapping
)
1189 unmap_mapping_range(obj
->base
.dev
->dev_mapping
,
1190 (loff_t
)obj
->base
.map_list
.hash
.key
<<PAGE_SHIFT
,
1193 obj
->fault_mappable
= false;
1197 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1201 if (INTEL_INFO(dev
)->gen
>= 4 ||
1202 tiling_mode
== I915_TILING_NONE
)
1205 /* Previous chips need a power-of-two fence region when tiling */
1206 if (INTEL_INFO(dev
)->gen
== 3)
1207 gtt_size
= 1024*1024;
1209 gtt_size
= 512*1024;
1211 while (gtt_size
< size
)
1218 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1219 * @obj: object to check
1221 * Return the required GTT alignment for an object, taking into account
1222 * potential fence register mapping.
1225 i915_gem_get_gtt_alignment(struct drm_device
*dev
,
1230 * Minimum alignment is 4k (GTT page size), but might be greater
1231 * if a fence register is needed for the object.
1233 if (INTEL_INFO(dev
)->gen
>= 4 ||
1234 tiling_mode
== I915_TILING_NONE
)
1238 * Previous chips need to be aligned to the size of the smallest
1239 * fence register that can contain the object.
1241 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1245 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1248 * @size: size of the object
1249 * @tiling_mode: tiling mode of the object
1251 * Return the required GTT alignment for an object, only taking into account
1252 * unfenced tiled surface requirements.
1255 i915_gem_get_unfenced_gtt_alignment(struct drm_device
*dev
,
1260 * Minimum alignment is 4k (GTT page size) for sane hw.
1262 if (INTEL_INFO(dev
)->gen
>= 4 || IS_G33(dev
) ||
1263 tiling_mode
== I915_TILING_NONE
)
1266 /* Previous hardware however needs to be aligned to a power-of-two
1267 * tile height. The simplest method for determining this is to reuse
1268 * the power-of-tile object size.
1270 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1274 i915_gem_mmap_gtt(struct drm_file
*file
,
1275 struct drm_device
*dev
,
1279 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1280 struct drm_i915_gem_object
*obj
;
1283 ret
= i915_mutex_lock_interruptible(dev
);
1287 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1288 if (&obj
->base
== NULL
) {
1293 if (obj
->base
.size
> dev_priv
->mm
.gtt_mappable_end
) {
1298 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1299 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1304 if (!obj
->base
.map_list
.map
) {
1305 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1310 *offset
= (u64
)obj
->base
.map_list
.hash
.key
<< PAGE_SHIFT
;
1313 drm_gem_object_unreference(&obj
->base
);
1315 mutex_unlock(&dev
->struct_mutex
);
1320 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1322 * @data: GTT mapping ioctl data
1323 * @file: GEM object info
1325 * Simply returns the fake offset to userspace so it can mmap it.
1326 * The mmap call will end up in drm_gem_mmap(), which will set things
1327 * up so we can get faults in the handler above.
1329 * The fault handler will take care of binding the object into the GTT
1330 * (since it may have been evicted to make room for something), allocating
1331 * a fence register, and mapping the appropriate aperture address into
1335 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1336 struct drm_file
*file
)
1338 struct drm_i915_gem_mmap_gtt
*args
= data
;
1340 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1344 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
,
1348 struct address_space
*mapping
;
1349 struct inode
*inode
;
1352 if (obj
->pages
|| obj
->sg_table
)
1355 /* Get the list of pages out of our struct file. They'll be pinned
1356 * at this point until we release them.
1358 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1359 BUG_ON(obj
->pages
!= NULL
);
1360 obj
->pages
= drm_malloc_ab(page_count
, sizeof(struct page
*));
1361 if (obj
->pages
== NULL
)
1364 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1365 mapping
= inode
->i_mapping
;
1366 gfpmask
|= mapping_gfp_mask(mapping
);
1368 for (i
= 0; i
< page_count
; i
++) {
1369 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfpmask
);
1373 obj
->pages
[i
] = page
;
1376 if (i915_gem_object_needs_bit17_swizzle(obj
))
1377 i915_gem_object_do_bit_17_swizzle(obj
);
1383 page_cache_release(obj
->pages
[i
]);
1385 drm_free_large(obj
->pages
);
1387 return PTR_ERR(page
);
1391 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1393 int page_count
= obj
->base
.size
/ PAGE_SIZE
;
1399 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1401 if (i915_gem_object_needs_bit17_swizzle(obj
))
1402 i915_gem_object_save_bit_17_swizzle(obj
);
1404 if (obj
->madv
== I915_MADV_DONTNEED
)
1407 for (i
= 0; i
< page_count
; i
++) {
1409 set_page_dirty(obj
->pages
[i
]);
1411 if (obj
->madv
== I915_MADV_WILLNEED
)
1412 mark_page_accessed(obj
->pages
[i
]);
1414 page_cache_release(obj
->pages
[i
]);
1418 drm_free_large(obj
->pages
);
1423 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1424 struct intel_ring_buffer
*ring
,
1427 struct drm_device
*dev
= obj
->base
.dev
;
1428 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1430 BUG_ON(ring
== NULL
);
1433 /* Add a reference if we're newly entering the active list. */
1435 drm_gem_object_reference(&obj
->base
);
1439 /* Move from whatever list we were on to the tail of execution. */
1440 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.active_list
);
1441 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
1443 obj
->last_read_seqno
= seqno
;
1445 if (obj
->fenced_gpu_access
) {
1446 obj
->last_fenced_seqno
= seqno
;
1448 /* Bump MRU to take account of the delayed flush */
1449 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1450 struct drm_i915_fence_reg
*reg
;
1452 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
1453 list_move_tail(®
->lru_list
,
1454 &dev_priv
->mm
.fence_list
);
1460 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
1462 struct drm_device
*dev
= obj
->base
.dev
;
1463 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1465 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1467 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
1468 BUG_ON(!obj
->active
);
1470 list_del_init(&obj
->ring_list
);
1473 obj
->last_read_seqno
= 0;
1474 obj
->last_write_seqno
= 0;
1475 obj
->base
.write_domain
= 0;
1477 obj
->last_fenced_seqno
= 0;
1478 obj
->fenced_gpu_access
= false;
1481 drm_gem_object_unreference(&obj
->base
);
1483 WARN_ON(i915_verify_lists(dev
));
1486 /* Immediately discard the backing storage */
1488 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1490 struct inode
*inode
;
1492 /* Our goal here is to return as much of the memory as
1493 * is possible back to the system as we are called from OOM.
1494 * To do this we must instruct the shmfs to drop all of its
1495 * backing pages, *now*.
1497 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1498 shmem_truncate_range(inode
, 0, (loff_t
)-1);
1500 if (obj
->base
.map_list
.map
)
1501 drm_gem_free_mmap_offset(&obj
->base
);
1503 obj
->madv
= __I915_MADV_PURGED
;
1507 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1509 return obj
->madv
== I915_MADV_DONTNEED
;
1513 i915_gem_get_seqno(struct drm_device
*dev
)
1515 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1516 u32 seqno
= dev_priv
->next_seqno
;
1518 /* reserve 0 for non-seqno */
1519 if (++dev_priv
->next_seqno
== 0)
1520 dev_priv
->next_seqno
= 1;
1526 i915_gem_next_request_seqno(struct intel_ring_buffer
*ring
)
1528 if (ring
->outstanding_lazy_request
== 0)
1529 ring
->outstanding_lazy_request
= i915_gem_get_seqno(ring
->dev
);
1531 return ring
->outstanding_lazy_request
;
1535 i915_add_request(struct intel_ring_buffer
*ring
,
1536 struct drm_file
*file
,
1537 struct drm_i915_gem_request
*request
)
1539 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1541 u32 request_ring_position
;
1546 * Emit any outstanding flushes - execbuf can fail to emit the flush
1547 * after having emitted the batchbuffer command. Hence we need to fix
1548 * things up similar to emitting the lazy request. The difference here
1549 * is that the flush _must_ happen before the next request, no matter
1552 if (ring
->gpu_caches_dirty
) {
1553 ret
= i915_gem_flush_ring(ring
, 0, I915_GEM_GPU_DOMAINS
);
1557 ring
->gpu_caches_dirty
= false;
1560 if (request
== NULL
) {
1561 request
= kmalloc(sizeof(*request
), GFP_KERNEL
);
1562 if (request
== NULL
)
1566 seqno
= i915_gem_next_request_seqno(ring
);
1568 /* Record the position of the start of the request so that
1569 * should we detect the updated seqno part-way through the
1570 * GPU processing the request, we never over-estimate the
1571 * position of the head.
1573 request_ring_position
= intel_ring_get_tail(ring
);
1575 ret
= ring
->add_request(ring
, &seqno
);
1581 trace_i915_gem_request_add(ring
, seqno
);
1583 request
->seqno
= seqno
;
1584 request
->ring
= ring
;
1585 request
->tail
= request_ring_position
;
1586 request
->emitted_jiffies
= jiffies
;
1587 was_empty
= list_empty(&ring
->request_list
);
1588 list_add_tail(&request
->list
, &ring
->request_list
);
1589 request
->file_priv
= NULL
;
1592 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1594 spin_lock(&file_priv
->mm
.lock
);
1595 request
->file_priv
= file_priv
;
1596 list_add_tail(&request
->client_list
,
1597 &file_priv
->mm
.request_list
);
1598 spin_unlock(&file_priv
->mm
.lock
);
1601 ring
->outstanding_lazy_request
= 0;
1603 if (!dev_priv
->mm
.suspended
) {
1604 if (i915_enable_hangcheck
) {
1605 mod_timer(&dev_priv
->hangcheck_timer
,
1607 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1610 queue_delayed_work(dev_priv
->wq
,
1611 &dev_priv
->mm
.retire_work
, HZ
);
1618 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1620 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1625 spin_lock(&file_priv
->mm
.lock
);
1626 if (request
->file_priv
) {
1627 list_del(&request
->client_list
);
1628 request
->file_priv
= NULL
;
1630 spin_unlock(&file_priv
->mm
.lock
);
1633 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
1634 struct intel_ring_buffer
*ring
)
1636 while (!list_empty(&ring
->request_list
)) {
1637 struct drm_i915_gem_request
*request
;
1639 request
= list_first_entry(&ring
->request_list
,
1640 struct drm_i915_gem_request
,
1643 list_del(&request
->list
);
1644 i915_gem_request_remove_from_client(request
);
1648 while (!list_empty(&ring
->active_list
)) {
1649 struct drm_i915_gem_object
*obj
;
1651 obj
= list_first_entry(&ring
->active_list
,
1652 struct drm_i915_gem_object
,
1655 i915_gem_object_move_to_inactive(obj
);
1659 static void i915_gem_reset_fences(struct drm_device
*dev
)
1661 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1664 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
1665 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
1667 i915_gem_write_fence(dev
, i
, NULL
);
1670 i915_gem_object_fence_lost(reg
->obj
);
1674 INIT_LIST_HEAD(®
->lru_list
);
1677 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
1680 void i915_gem_reset(struct drm_device
*dev
)
1682 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1683 struct drm_i915_gem_object
*obj
;
1684 struct intel_ring_buffer
*ring
;
1687 for_each_ring(ring
, dev_priv
, i
)
1688 i915_gem_reset_ring_lists(dev_priv
, ring
);
1690 /* Move everything out of the GPU domains to ensure we do any
1691 * necessary invalidation upon reuse.
1693 list_for_each_entry(obj
,
1694 &dev_priv
->mm
.inactive_list
,
1697 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
1700 /* The fence registers are invalidated so clear them out */
1701 i915_gem_reset_fences(dev
);
1705 * This function clears the request list as sequence numbers are passed.
1708 i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
)
1713 if (list_empty(&ring
->request_list
))
1716 WARN_ON(i915_verify_lists(ring
->dev
));
1718 seqno
= ring
->get_seqno(ring
);
1720 for (i
= 0; i
< ARRAY_SIZE(ring
->sync_seqno
); i
++)
1721 if (seqno
>= ring
->sync_seqno
[i
])
1722 ring
->sync_seqno
[i
] = 0;
1724 while (!list_empty(&ring
->request_list
)) {
1725 struct drm_i915_gem_request
*request
;
1727 request
= list_first_entry(&ring
->request_list
,
1728 struct drm_i915_gem_request
,
1731 if (!i915_seqno_passed(seqno
, request
->seqno
))
1734 trace_i915_gem_request_retire(ring
, request
->seqno
);
1735 /* We know the GPU must have read the request to have
1736 * sent us the seqno + interrupt, so use the position
1737 * of tail of the request to update the last known position
1740 ring
->last_retired_head
= request
->tail
;
1742 list_del(&request
->list
);
1743 i915_gem_request_remove_from_client(request
);
1747 /* Move any buffers on the active list that are no longer referenced
1748 * by the ringbuffer to the flushing/inactive lists as appropriate.
1750 while (!list_empty(&ring
->active_list
)) {
1751 struct drm_i915_gem_object
*obj
;
1753 obj
= list_first_entry(&ring
->active_list
,
1754 struct drm_i915_gem_object
,
1757 if (!i915_seqno_passed(seqno
, obj
->last_read_seqno
))
1760 i915_gem_object_move_to_inactive(obj
);
1763 if (unlikely(ring
->trace_irq_seqno
&&
1764 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
1765 ring
->irq_put(ring
);
1766 ring
->trace_irq_seqno
= 0;
1769 WARN_ON(i915_verify_lists(ring
->dev
));
1773 i915_gem_retire_requests(struct drm_device
*dev
)
1775 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1776 struct intel_ring_buffer
*ring
;
1779 for_each_ring(ring
, dev_priv
, i
)
1780 i915_gem_retire_requests_ring(ring
);
1784 i915_gem_retire_work_handler(struct work_struct
*work
)
1786 drm_i915_private_t
*dev_priv
;
1787 struct drm_device
*dev
;
1788 struct intel_ring_buffer
*ring
;
1792 dev_priv
= container_of(work
, drm_i915_private_t
,
1793 mm
.retire_work
.work
);
1794 dev
= dev_priv
->dev
;
1796 /* Come back later if the device is busy... */
1797 if (!mutex_trylock(&dev
->struct_mutex
)) {
1798 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1802 i915_gem_retire_requests(dev
);
1804 /* Send a periodic flush down the ring so we don't hold onto GEM
1805 * objects indefinitely.
1808 for_each_ring(ring
, dev_priv
, i
) {
1809 if (ring
->gpu_caches_dirty
)
1810 i915_add_request(ring
, NULL
, NULL
);
1812 idle
&= list_empty(&ring
->request_list
);
1815 if (!dev_priv
->mm
.suspended
&& !idle
)
1816 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1818 mutex_unlock(&dev
->struct_mutex
);
1822 i915_gem_check_wedge(struct drm_i915_private
*dev_priv
,
1825 if (atomic_read(&dev_priv
->mm
.wedged
)) {
1826 struct completion
*x
= &dev_priv
->error_completion
;
1827 bool recovery_complete
;
1828 unsigned long flags
;
1830 /* Give the error handler a chance to run. */
1831 spin_lock_irqsave(&x
->wait
.lock
, flags
);
1832 recovery_complete
= x
->done
> 0;
1833 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
1835 /* Non-interruptible callers can't handle -EAGAIN, hence return
1836 * -EIO unconditionally for these. */
1840 /* Recovery complete, but still wedged means reset failure. */
1841 if (recovery_complete
)
1851 * Compare seqno against outstanding lazy request. Emit a request if they are
1855 i915_gem_check_olr(struct intel_ring_buffer
*ring
, u32 seqno
)
1859 BUG_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
1862 if (seqno
== ring
->outstanding_lazy_request
)
1863 ret
= i915_add_request(ring
, NULL
, NULL
);
1869 * __wait_seqno - wait until execution of seqno has finished
1870 * @ring: the ring expected to report seqno
1872 * @interruptible: do an interruptible wait (normally yes)
1873 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1875 * Returns 0 if the seqno was found within the alloted time. Else returns the
1876 * errno with remaining time filled in timeout argument.
1878 static int __wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
,
1879 bool interruptible
, struct timespec
*timeout
)
1881 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1882 struct timespec before
, now
, wait_time
={1,0};
1883 unsigned long timeout_jiffies
;
1885 bool wait_forever
= true;
1888 if (i915_seqno_passed(ring
->get_seqno(ring
), seqno
))
1891 trace_i915_gem_request_wait_begin(ring
, seqno
);
1893 if (timeout
!= NULL
) {
1894 wait_time
= *timeout
;
1895 wait_forever
= false;
1898 timeout_jiffies
= timespec_to_jiffies(&wait_time
);
1900 if (WARN_ON(!ring
->irq_get(ring
)))
1903 /* Record current time in case interrupted by signal, or wedged * */
1904 getrawmonotonic(&before
);
1907 (i915_seqno_passed(ring->get_seqno(ring), seqno) || \
1908 atomic_read(&dev_priv->mm.wedged))
1911 end
= wait_event_interruptible_timeout(ring
->irq_queue
,
1915 end
= wait_event_timeout(ring
->irq_queue
, EXIT_COND
,
1918 ret
= i915_gem_check_wedge(dev_priv
, interruptible
);
1921 } while (end
== 0 && wait_forever
);
1923 getrawmonotonic(&now
);
1925 ring
->irq_put(ring
);
1926 trace_i915_gem_request_wait_end(ring
, seqno
);
1930 struct timespec sleep_time
= timespec_sub(now
, before
);
1931 *timeout
= timespec_sub(*timeout
, sleep_time
);
1936 case -EAGAIN
: /* Wedged */
1937 case -ERESTARTSYS
: /* Signal */
1939 case 0: /* Timeout */
1941 set_normalized_timespec(timeout
, 0, 0);
1943 default: /* Completed */
1944 WARN_ON(end
< 0); /* We're not aware of other errors */
1950 * Waits for a sequence number to be signaled, and cleans up the
1951 * request and object lists appropriately for that event.
1954 i915_wait_seqno(struct intel_ring_buffer
*ring
, uint32_t seqno
)
1956 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1961 ret
= i915_gem_check_wedge(dev_priv
, dev_priv
->mm
.interruptible
);
1965 ret
= i915_gem_check_olr(ring
, seqno
);
1969 ret
= __wait_seqno(ring
, seqno
, dev_priv
->mm
.interruptible
, NULL
);
1975 * Ensures that all rendering to the object has completed and the object is
1976 * safe to unbind from the GTT or access from the CPU.
1978 static __must_check
int
1979 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1985 /* If there is rendering queued on the buffer being evicted, wait for
1989 seqno
= obj
->last_write_seqno
;
1991 seqno
= obj
->last_read_seqno
;
1995 ret
= i915_wait_seqno(obj
->ring
, seqno
);
1999 /* Manually manage the write flush as we may have not yet retired
2002 if (obj
->last_write_seqno
&&
2003 i915_seqno_passed(seqno
, obj
->last_write_seqno
)) {
2004 obj
->last_write_seqno
= 0;
2005 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
2008 i915_gem_retire_requests_ring(obj
->ring
);
2013 * Ensures that an object will eventually get non-busy by flushing any required
2014 * write domains, emitting any outstanding lazy request and retiring and
2015 * completed requests.
2018 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2023 ret
= i915_gem_check_olr(obj
->ring
, obj
->last_read_seqno
);
2027 i915_gem_retire_requests_ring(obj
->ring
);
2034 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2035 * @DRM_IOCTL_ARGS: standard ioctl arguments
2037 * Returns 0 if successful, else an error is returned with the remaining time in
2038 * the timeout parameter.
2039 * -ETIME: object is still busy after timeout
2040 * -ERESTARTSYS: signal interrupted the wait
2041 * -ENONENT: object doesn't exist
2042 * Also possible, but rare:
2043 * -EAGAIN: GPU wedged
2045 * -ENODEV: Internal IRQ fail
2046 * -E?: The add request failed
2048 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2049 * non-zero timeout parameter the wait ioctl will wait for the given number of
2050 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2051 * without holding struct_mutex the object may become re-busied before this
2052 * function completes. A similar but shorter * race condition exists in the busy
2056 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2058 struct drm_i915_gem_wait
*args
= data
;
2059 struct drm_i915_gem_object
*obj
;
2060 struct intel_ring_buffer
*ring
= NULL
;
2061 struct timespec timeout_stack
, *timeout
= NULL
;
2065 if (args
->timeout_ns
>= 0) {
2066 timeout_stack
= ns_to_timespec(args
->timeout_ns
);
2067 timeout
= &timeout_stack
;
2070 ret
= i915_mutex_lock_interruptible(dev
);
2074 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2075 if (&obj
->base
== NULL
) {
2076 mutex_unlock(&dev
->struct_mutex
);
2080 /* Need to make sure the object gets inactive eventually. */
2081 ret
= i915_gem_object_flush_active(obj
);
2086 seqno
= obj
->last_read_seqno
;
2093 /* Do this after OLR check to make sure we make forward progress polling
2094 * on this IOCTL with a 0 timeout (like busy ioctl)
2096 if (!args
->timeout_ns
) {
2101 drm_gem_object_unreference(&obj
->base
);
2102 mutex_unlock(&dev
->struct_mutex
);
2104 ret
= __wait_seqno(ring
, seqno
, true, timeout
);
2106 WARN_ON(!timespec_valid(timeout
));
2107 args
->timeout_ns
= timespec_to_ns(timeout
);
2112 drm_gem_object_unreference(&obj
->base
);
2113 mutex_unlock(&dev
->struct_mutex
);
2118 * i915_gem_object_sync - sync an object to a ring.
2120 * @obj: object which may be in use on another ring.
2121 * @to: ring we wish to use the object on. May be NULL.
2123 * This code is meant to abstract object synchronization with the GPU.
2124 * Calling with NULL implies synchronizing the object with the CPU
2125 * rather than a particular GPU ring.
2127 * Returns 0 if successful, else propagates up the lower layer error.
2130 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2131 struct intel_ring_buffer
*to
)
2133 struct intel_ring_buffer
*from
= obj
->ring
;
2137 if (from
== NULL
|| to
== from
)
2140 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2141 return i915_gem_object_wait_rendering(obj
, false);
2143 idx
= intel_ring_sync_index(from
, to
);
2145 seqno
= obj
->last_read_seqno
;
2146 if (seqno
<= from
->sync_seqno
[idx
])
2149 ret
= i915_gem_check_olr(obj
->ring
, seqno
);
2153 ret
= to
->sync_to(to
, from
, seqno
);
2155 from
->sync_seqno
[idx
] = seqno
;
2160 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
2162 u32 old_write_domain
, old_read_domains
;
2164 /* Act a barrier for all accesses through the GTT */
2167 /* Force a pagefault for domain tracking on next user access */
2168 i915_gem_release_mmap(obj
);
2170 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2173 old_read_domains
= obj
->base
.read_domains
;
2174 old_write_domain
= obj
->base
.write_domain
;
2176 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2177 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2179 trace_i915_gem_object_change_domain(obj
,
2185 * Unbinds an object from the GTT aperture.
2188 i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
2190 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2193 if (obj
->gtt_space
== NULL
)
2199 ret
= i915_gem_object_finish_gpu(obj
);
2202 /* Continue on if we fail due to EIO, the GPU is hung so we
2203 * should be safe and we need to cleanup or else we might
2204 * cause memory corruption through use-after-free.
2207 i915_gem_object_finish_gtt(obj
);
2209 /* Move the object to the CPU domain to ensure that
2210 * any possible CPU writes while it's not in the GTT
2211 * are flushed when we go to remap it.
2214 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2215 if (ret
== -ERESTARTSYS
)
2218 /* In the event of a disaster, abandon all caches and
2219 * hope for the best.
2221 i915_gem_clflush_object(obj
);
2222 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2225 /* release the fence reg _after_ flushing */
2226 ret
= i915_gem_object_put_fence(obj
);
2230 trace_i915_gem_object_unbind(obj
);
2232 if (obj
->has_global_gtt_mapping
)
2233 i915_gem_gtt_unbind_object(obj
);
2234 if (obj
->has_aliasing_ppgtt_mapping
) {
2235 i915_ppgtt_unbind_object(dev_priv
->mm
.aliasing_ppgtt
, obj
);
2236 obj
->has_aliasing_ppgtt_mapping
= 0;
2238 i915_gem_gtt_finish_object(obj
);
2240 i915_gem_object_put_pages_gtt(obj
);
2242 list_del_init(&obj
->gtt_list
);
2243 list_del_init(&obj
->mm_list
);
2244 /* Avoid an unnecessary call to unbind on rebind. */
2245 obj
->map_and_fenceable
= true;
2247 drm_mm_put_block(obj
->gtt_space
);
2248 obj
->gtt_space
= NULL
;
2249 obj
->gtt_offset
= 0;
2251 if (i915_gem_object_is_purgeable(obj
))
2252 i915_gem_object_truncate(obj
);
2258 i915_gem_flush_ring(struct intel_ring_buffer
*ring
,
2259 uint32_t invalidate_domains
,
2260 uint32_t flush_domains
)
2264 if (((invalidate_domains
| flush_domains
) & I915_GEM_GPU_DOMAINS
) == 0)
2267 trace_i915_gem_ring_flush(ring
, invalidate_domains
, flush_domains
);
2269 ret
= ring
->flush(ring
, invalidate_domains
, flush_domains
);
2276 static int i915_ring_idle(struct intel_ring_buffer
*ring
)
2278 if (list_empty(&ring
->active_list
))
2281 return i915_wait_seqno(ring
, i915_gem_next_request_seqno(ring
));
2284 int i915_gpu_idle(struct drm_device
*dev
)
2286 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2287 struct intel_ring_buffer
*ring
;
2290 /* Flush everything onto the inactive list. */
2291 for_each_ring(ring
, dev_priv
, i
) {
2292 ret
= i915_ring_idle(ring
);
2296 ret
= i915_switch_context(ring
, NULL
, DEFAULT_CONTEXT_ID
);
2304 static void sandybridge_write_fence_reg(struct drm_device
*dev
, int reg
,
2305 struct drm_i915_gem_object
*obj
)
2307 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2311 u32 size
= obj
->gtt_space
->size
;
2313 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2315 val
|= obj
->gtt_offset
& 0xfffff000;
2316 val
|= (uint64_t)((obj
->stride
/ 128) - 1) <<
2317 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2319 if (obj
->tiling_mode
== I915_TILING_Y
)
2320 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2321 val
|= I965_FENCE_REG_VALID
;
2325 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ reg
* 8, val
);
2326 POSTING_READ(FENCE_REG_SANDYBRIDGE_0
+ reg
* 8);
2329 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
2330 struct drm_i915_gem_object
*obj
)
2332 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2336 u32 size
= obj
->gtt_space
->size
;
2338 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2340 val
|= obj
->gtt_offset
& 0xfffff000;
2341 val
|= ((obj
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2342 if (obj
->tiling_mode
== I915_TILING_Y
)
2343 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2344 val
|= I965_FENCE_REG_VALID
;
2348 I915_WRITE64(FENCE_REG_965_0
+ reg
* 8, val
);
2349 POSTING_READ(FENCE_REG_965_0
+ reg
* 8);
2352 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
2353 struct drm_i915_gem_object
*obj
)
2355 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2359 u32 size
= obj
->gtt_space
->size
;
2363 WARN((obj
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2364 (size
& -size
) != size
||
2365 (obj
->gtt_offset
& (size
- 1)),
2366 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2367 obj
->gtt_offset
, obj
->map_and_fenceable
, size
);
2369 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2374 /* Note: pitch better be a power of two tile widths */
2375 pitch_val
= obj
->stride
/ tile_width
;
2376 pitch_val
= ffs(pitch_val
) - 1;
2378 val
= obj
->gtt_offset
;
2379 if (obj
->tiling_mode
== I915_TILING_Y
)
2380 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2381 val
|= I915_FENCE_SIZE_BITS(size
);
2382 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2383 val
|= I830_FENCE_REG_VALID
;
2388 reg
= FENCE_REG_830_0
+ reg
* 4;
2390 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
2392 I915_WRITE(reg
, val
);
2396 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
2397 struct drm_i915_gem_object
*obj
)
2399 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2403 u32 size
= obj
->gtt_space
->size
;
2406 WARN((obj
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2407 (size
& -size
) != size
||
2408 (obj
->gtt_offset
& (size
- 1)),
2409 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2410 obj
->gtt_offset
, size
);
2412 pitch_val
= obj
->stride
/ 128;
2413 pitch_val
= ffs(pitch_val
) - 1;
2415 val
= obj
->gtt_offset
;
2416 if (obj
->tiling_mode
== I915_TILING_Y
)
2417 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2418 val
|= I830_FENCE_SIZE_BITS(size
);
2419 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2420 val
|= I830_FENCE_REG_VALID
;
2424 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
2425 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
2428 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
2429 struct drm_i915_gem_object
*obj
)
2431 switch (INTEL_INFO(dev
)->gen
) {
2433 case 6: sandybridge_write_fence_reg(dev
, reg
, obj
); break;
2435 case 4: i965_write_fence_reg(dev
, reg
, obj
); break;
2436 case 3: i915_write_fence_reg(dev
, reg
, obj
); break;
2437 case 2: i830_write_fence_reg(dev
, reg
, obj
); break;
2442 static inline int fence_number(struct drm_i915_private
*dev_priv
,
2443 struct drm_i915_fence_reg
*fence
)
2445 return fence
- dev_priv
->fence_regs
;
2448 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
2449 struct drm_i915_fence_reg
*fence
,
2452 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2453 int reg
= fence_number(dev_priv
, fence
);
2455 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
2458 obj
->fence_reg
= reg
;
2460 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
2462 obj
->fence_reg
= I915_FENCE_REG_NONE
;
2464 list_del_init(&fence
->lru_list
);
2469 i915_gem_object_flush_fence(struct drm_i915_gem_object
*obj
)
2471 if (obj
->last_fenced_seqno
) {
2472 int ret
= i915_wait_seqno(obj
->ring
, obj
->last_fenced_seqno
);
2476 obj
->last_fenced_seqno
= 0;
2479 /* Ensure that all CPU reads are completed before installing a fence
2480 * and all writes before removing the fence.
2482 if (obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
)
2485 obj
->fenced_gpu_access
= false;
2490 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
2492 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2495 ret
= i915_gem_object_flush_fence(obj
);
2499 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
2502 i915_gem_object_update_fence(obj
,
2503 &dev_priv
->fence_regs
[obj
->fence_reg
],
2505 i915_gem_object_fence_lost(obj
);
2510 static struct drm_i915_fence_reg
*
2511 i915_find_fence_reg(struct drm_device
*dev
)
2513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2514 struct drm_i915_fence_reg
*reg
, *avail
;
2517 /* First try to find a free reg */
2519 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2520 reg
= &dev_priv
->fence_regs
[i
];
2524 if (!reg
->pin_count
)
2531 /* None available, try to steal one or wait for a user to finish */
2532 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
2543 * i915_gem_object_get_fence - set up fencing for an object
2544 * @obj: object to map through a fence reg
2546 * When mapping objects through the GTT, userspace wants to be able to write
2547 * to them without having to worry about swizzling if the object is tiled.
2548 * This function walks the fence regs looking for a free one for @obj,
2549 * stealing one if it can't find any.
2551 * It then sets up the reg based on the object's properties: address, pitch
2552 * and tiling format.
2554 * For an untiled surface, this removes any existing fence.
2557 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
2559 struct drm_device
*dev
= obj
->base
.dev
;
2560 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2561 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
2562 struct drm_i915_fence_reg
*reg
;
2565 /* Have we updated the tiling parameters upon the object and so
2566 * will need to serialise the write to the associated fence register?
2568 if (obj
->fence_dirty
) {
2569 ret
= i915_gem_object_flush_fence(obj
);
2574 /* Just update our place in the LRU if our fence is getting reused. */
2575 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2576 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2577 if (!obj
->fence_dirty
) {
2578 list_move_tail(®
->lru_list
,
2579 &dev_priv
->mm
.fence_list
);
2582 } else if (enable
) {
2583 reg
= i915_find_fence_reg(dev
);
2588 struct drm_i915_gem_object
*old
= reg
->obj
;
2590 ret
= i915_gem_object_flush_fence(old
);
2594 i915_gem_object_fence_lost(old
);
2599 i915_gem_object_update_fence(obj
, reg
, enable
);
2600 obj
->fence_dirty
= false;
2606 * Finds free space in the GTT aperture and binds the object there.
2609 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
2611 bool map_and_fenceable
)
2613 struct drm_device
*dev
= obj
->base
.dev
;
2614 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2615 struct drm_mm_node
*free_space
;
2616 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2617 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
2618 bool mappable
, fenceable
;
2621 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2622 DRM_ERROR("Attempting to bind a purgeable object\n");
2626 fence_size
= i915_gem_get_gtt_size(dev
,
2629 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
2632 unfenced_alignment
=
2633 i915_gem_get_unfenced_gtt_alignment(dev
,
2638 alignment
= map_and_fenceable
? fence_alignment
:
2640 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
2641 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2645 size
= map_and_fenceable
? fence_size
: obj
->base
.size
;
2647 /* If the object is bigger than the entire aperture, reject it early
2648 * before evicting everything in a vain attempt to find space.
2650 if (obj
->base
.size
>
2651 (map_and_fenceable
? dev_priv
->mm
.gtt_mappable_end
: dev_priv
->mm
.gtt_total
)) {
2652 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2657 if (map_and_fenceable
)
2659 drm_mm_search_free_in_range(&dev_priv
->mm
.gtt_space
,
2661 0, dev_priv
->mm
.gtt_mappable_end
,
2664 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2665 size
, alignment
, 0);
2667 if (free_space
!= NULL
) {
2668 if (map_and_fenceable
)
2670 drm_mm_get_block_range_generic(free_space
,
2672 0, dev_priv
->mm
.gtt_mappable_end
,
2676 drm_mm_get_block(free_space
, size
, alignment
);
2678 if (obj
->gtt_space
== NULL
) {
2679 /* If the gtt is empty and we're still having trouble
2680 * fitting our object in, we're out of memory.
2682 ret
= i915_gem_evict_something(dev
, size
, alignment
,
2690 ret
= i915_gem_object_get_pages_gtt(obj
, gfpmask
);
2692 drm_mm_put_block(obj
->gtt_space
);
2693 obj
->gtt_space
= NULL
;
2695 if (ret
== -ENOMEM
) {
2696 /* first try to reclaim some memory by clearing the GTT */
2697 ret
= i915_gem_evict_everything(dev
, false);
2699 /* now try to shrink everyone else */
2714 ret
= i915_gem_gtt_prepare_object(obj
);
2716 i915_gem_object_put_pages_gtt(obj
);
2717 drm_mm_put_block(obj
->gtt_space
);
2718 obj
->gtt_space
= NULL
;
2720 if (i915_gem_evict_everything(dev
, false))
2726 if (!dev_priv
->mm
.aliasing_ppgtt
)
2727 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
2729 list_add_tail(&obj
->gtt_list
, &dev_priv
->mm
.gtt_list
);
2730 list_add_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
2732 /* Assert that the object is not currently in any GPU domain. As it
2733 * wasn't in the GTT, there shouldn't be any way it could have been in
2736 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2737 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2739 obj
->gtt_offset
= obj
->gtt_space
->start
;
2742 obj
->gtt_space
->size
== fence_size
&&
2743 (obj
->gtt_space
->start
& (fence_alignment
- 1)) == 0;
2746 obj
->gtt_offset
+ obj
->base
.size
<= dev_priv
->mm
.gtt_mappable_end
;
2748 obj
->map_and_fenceable
= mappable
&& fenceable
;
2750 trace_i915_gem_object_bind(obj
, map_and_fenceable
);
2755 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
)
2757 /* If we don't have a page list set up, then we're not pinned
2758 * to GPU, and we can ignore the cache flush because it'll happen
2759 * again at bind time.
2761 if (obj
->pages
== NULL
)
2764 /* If the GPU is snooping the contents of the CPU cache,
2765 * we do not need to manually clear the CPU cache lines. However,
2766 * the caches are only snooped when the render cache is
2767 * flushed/invalidated. As we always have to emit invalidations
2768 * and flushes when moving into and out of the RENDER domain, correct
2769 * snooping behaviour occurs naturally as the result of our domain
2772 if (obj
->cache_level
!= I915_CACHE_NONE
)
2775 trace_i915_gem_object_clflush(obj
);
2777 drm_clflush_pages(obj
->pages
, obj
->base
.size
/ PAGE_SIZE
);
2780 /** Flushes the GTT write domain for the object if it's dirty. */
2782 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
2784 uint32_t old_write_domain
;
2786 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
2789 /* No actual flushing is required for the GTT write domain. Writes
2790 * to it immediately go to main memory as far as we know, so there's
2791 * no chipset flush. It also doesn't land in render cache.
2793 * However, we do have to enforce the order so that all writes through
2794 * the GTT land before any writes to the device, such as updates to
2799 old_write_domain
= obj
->base
.write_domain
;
2800 obj
->base
.write_domain
= 0;
2802 trace_i915_gem_object_change_domain(obj
,
2803 obj
->base
.read_domains
,
2807 /** Flushes the CPU write domain for the object if it's dirty. */
2809 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
2811 uint32_t old_write_domain
;
2813 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
2816 i915_gem_clflush_object(obj
);
2817 intel_gtt_chipset_flush();
2818 old_write_domain
= obj
->base
.write_domain
;
2819 obj
->base
.write_domain
= 0;
2821 trace_i915_gem_object_change_domain(obj
,
2822 obj
->base
.read_domains
,
2827 * Moves a single object to the GTT read, and possibly write domain.
2829 * This function returns when the move is complete, including waiting on
2833 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
2835 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2836 uint32_t old_write_domain
, old_read_domains
;
2839 /* Not valid to be called on unbound objects. */
2840 if (obj
->gtt_space
== NULL
)
2843 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
2846 ret
= i915_gem_object_wait_rendering(obj
, !write
);
2850 i915_gem_object_flush_cpu_write_domain(obj
);
2852 old_write_domain
= obj
->base
.write_domain
;
2853 old_read_domains
= obj
->base
.read_domains
;
2855 /* It should now be out of any other write domains, and we can update
2856 * the domain values for our changes.
2858 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2859 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
2861 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
2862 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
2866 trace_i915_gem_object_change_domain(obj
,
2870 /* And bump the LRU for this access */
2871 if (i915_gem_object_is_inactive(obj
))
2872 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
2877 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2878 enum i915_cache_level cache_level
)
2880 struct drm_device
*dev
= obj
->base
.dev
;
2881 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2884 if (obj
->cache_level
== cache_level
)
2887 if (obj
->pin_count
) {
2888 DRM_DEBUG("can not change the cache level of pinned objects\n");
2892 if (obj
->gtt_space
) {
2893 ret
= i915_gem_object_finish_gpu(obj
);
2897 i915_gem_object_finish_gtt(obj
);
2899 /* Before SandyBridge, you could not use tiling or fence
2900 * registers with snooped memory, so relinquish any fences
2901 * currently pointing to our region in the aperture.
2903 if (INTEL_INFO(obj
->base
.dev
)->gen
< 6) {
2904 ret
= i915_gem_object_put_fence(obj
);
2909 if (obj
->has_global_gtt_mapping
)
2910 i915_gem_gtt_bind_object(obj
, cache_level
);
2911 if (obj
->has_aliasing_ppgtt_mapping
)
2912 i915_ppgtt_bind_object(dev_priv
->mm
.aliasing_ppgtt
,
2916 if (cache_level
== I915_CACHE_NONE
) {
2917 u32 old_read_domains
, old_write_domain
;
2919 /* If we're coming from LLC cached, then we haven't
2920 * actually been tracking whether the data is in the
2921 * CPU cache or not, since we only allow one bit set
2922 * in obj->write_domain and have been skipping the clflushes.
2923 * Just set it to the CPU cache for now.
2925 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
2926 WARN_ON(obj
->base
.read_domains
& ~I915_GEM_DOMAIN_CPU
);
2928 old_read_domains
= obj
->base
.read_domains
;
2929 old_write_domain
= obj
->base
.write_domain
;
2931 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
2932 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2934 trace_i915_gem_object_change_domain(obj
,
2939 obj
->cache_level
= cache_level
;
2944 * Prepare buffer for display plane (scanout, cursors, etc).
2945 * Can be called from an uninterruptible phase (modesetting) and allows
2946 * any flushes to be pipelined (for pageflips).
2949 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2951 struct intel_ring_buffer
*pipelined
)
2953 u32 old_read_domains
, old_write_domain
;
2956 if (pipelined
!= obj
->ring
) {
2957 ret
= i915_gem_object_sync(obj
, pipelined
);
2962 /* The display engine is not coherent with the LLC cache on gen6. As
2963 * a result, we make sure that the pinning that is about to occur is
2964 * done with uncached PTEs. This is lowest common denominator for all
2967 * However for gen6+, we could do better by using the GFDT bit instead
2968 * of uncaching, which would allow us to flush all the LLC-cached data
2969 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
2971 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_NONE
);
2975 /* As the user may map the buffer once pinned in the display plane
2976 * (e.g. libkms for the bootup splash), we have to ensure that we
2977 * always use map_and_fenceable for all scanout buffers.
2979 ret
= i915_gem_object_pin(obj
, alignment
, true);
2983 i915_gem_object_flush_cpu_write_domain(obj
);
2985 old_write_domain
= obj
->base
.write_domain
;
2986 old_read_domains
= obj
->base
.read_domains
;
2988 /* It should now be out of any other write domains, and we can update
2989 * the domain values for our changes.
2991 obj
->base
.write_domain
= 0;
2992 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
2994 trace_i915_gem_object_change_domain(obj
,
3002 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
3006 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
3009 ret
= i915_gem_object_wait_rendering(obj
, false);
3013 /* Ensure that we invalidate the GPU's caches and TLBs. */
3014 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
3019 * Moves a single object to the CPU read, and possibly write domain.
3021 * This function returns when the move is complete, including waiting on
3025 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3027 uint32_t old_write_domain
, old_read_domains
;
3030 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3033 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3037 i915_gem_object_flush_gtt_write_domain(obj
);
3039 old_write_domain
= obj
->base
.write_domain
;
3040 old_read_domains
= obj
->base
.read_domains
;
3042 /* Flush the CPU cache if it's still invalid. */
3043 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3044 i915_gem_clflush_object(obj
);
3046 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3049 /* It should now be out of any other write domains, and we can update
3050 * the domain values for our changes.
3052 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3054 /* If we're writing through the CPU, then the GPU read domains will
3055 * need to be invalidated at next use.
3058 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3059 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3062 trace_i915_gem_object_change_domain(obj
,
3069 /* Throttle our rendering by waiting until the ring has completed our requests
3070 * emitted over 20 msec ago.
3072 * Note that if we were to use the current jiffies each time around the loop,
3073 * we wouldn't escape the function with any frames outstanding if the time to
3074 * render a frame was over 20ms.
3076 * This should get us reasonable parallelism between CPU and GPU but also
3077 * relatively low latency when blocking on a particular request to finish.
3080 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3082 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3083 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3084 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3085 struct drm_i915_gem_request
*request
;
3086 struct intel_ring_buffer
*ring
= NULL
;
3090 if (atomic_read(&dev_priv
->mm
.wedged
))
3093 spin_lock(&file_priv
->mm
.lock
);
3094 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3095 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3098 ring
= request
->ring
;
3099 seqno
= request
->seqno
;
3101 spin_unlock(&file_priv
->mm
.lock
);
3106 ret
= __wait_seqno(ring
, seqno
, true, NULL
);
3108 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3114 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3116 bool map_and_fenceable
)
3120 BUG_ON(obj
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
3122 if (obj
->gtt_space
!= NULL
) {
3123 if ((alignment
&& obj
->gtt_offset
& (alignment
- 1)) ||
3124 (map_and_fenceable
&& !obj
->map_and_fenceable
)) {
3125 WARN(obj
->pin_count
,
3126 "bo is already pinned with incorrect alignment:"
3127 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3128 " obj->map_and_fenceable=%d\n",
3129 obj
->gtt_offset
, alignment
,
3131 obj
->map_and_fenceable
);
3132 ret
= i915_gem_object_unbind(obj
);
3138 if (obj
->gtt_space
== NULL
) {
3139 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
3145 if (!obj
->has_global_gtt_mapping
&& map_and_fenceable
)
3146 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3149 obj
->pin_mappable
|= map_and_fenceable
;
3155 i915_gem_object_unpin(struct drm_i915_gem_object
*obj
)
3157 BUG_ON(obj
->pin_count
== 0);
3158 BUG_ON(obj
->gtt_space
== NULL
);
3160 if (--obj
->pin_count
== 0)
3161 obj
->pin_mappable
= false;
3165 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3166 struct drm_file
*file
)
3168 struct drm_i915_gem_pin
*args
= data
;
3169 struct drm_i915_gem_object
*obj
;
3172 ret
= i915_mutex_lock_interruptible(dev
);
3176 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3177 if (&obj
->base
== NULL
) {
3182 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3183 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3188 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3189 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3195 obj
->user_pin_count
++;
3196 obj
->pin_filp
= file
;
3197 if (obj
->user_pin_count
== 1) {
3198 ret
= i915_gem_object_pin(obj
, args
->alignment
, true);
3203 /* XXX - flush the CPU caches for pinned objects
3204 * as the X server doesn't manage domains yet
3206 i915_gem_object_flush_cpu_write_domain(obj
);
3207 args
->offset
= obj
->gtt_offset
;
3209 drm_gem_object_unreference(&obj
->base
);
3211 mutex_unlock(&dev
->struct_mutex
);
3216 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3217 struct drm_file
*file
)
3219 struct drm_i915_gem_pin
*args
= data
;
3220 struct drm_i915_gem_object
*obj
;
3223 ret
= i915_mutex_lock_interruptible(dev
);
3227 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3228 if (&obj
->base
== NULL
) {
3233 if (obj
->pin_filp
!= file
) {
3234 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3239 obj
->user_pin_count
--;
3240 if (obj
->user_pin_count
== 0) {
3241 obj
->pin_filp
= NULL
;
3242 i915_gem_object_unpin(obj
);
3246 drm_gem_object_unreference(&obj
->base
);
3248 mutex_unlock(&dev
->struct_mutex
);
3253 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3254 struct drm_file
*file
)
3256 struct drm_i915_gem_busy
*args
= data
;
3257 struct drm_i915_gem_object
*obj
;
3260 ret
= i915_mutex_lock_interruptible(dev
);
3264 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3265 if (&obj
->base
== NULL
) {
3270 /* Count all active objects as busy, even if they are currently not used
3271 * by the gpu. Users of this interface expect objects to eventually
3272 * become non-busy without any further actions, therefore emit any
3273 * necessary flushes here.
3275 ret
= i915_gem_object_flush_active(obj
);
3277 args
->busy
= obj
->active
;
3279 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
3280 args
->busy
|= intel_ring_flag(obj
->ring
) << 16;
3283 drm_gem_object_unreference(&obj
->base
);
3285 mutex_unlock(&dev
->struct_mutex
);
3290 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3291 struct drm_file
*file_priv
)
3293 return i915_gem_ring_throttle(dev
, file_priv
);
3297 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3298 struct drm_file
*file_priv
)
3300 struct drm_i915_gem_madvise
*args
= data
;
3301 struct drm_i915_gem_object
*obj
;
3304 switch (args
->madv
) {
3305 case I915_MADV_DONTNEED
:
3306 case I915_MADV_WILLNEED
:
3312 ret
= i915_mutex_lock_interruptible(dev
);
3316 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
3317 if (&obj
->base
== NULL
) {
3322 if (obj
->pin_count
) {
3327 if (obj
->madv
!= __I915_MADV_PURGED
)
3328 obj
->madv
= args
->madv
;
3330 /* if the object is no longer bound, discard its backing storage */
3331 if (i915_gem_object_is_purgeable(obj
) &&
3332 obj
->gtt_space
== NULL
)
3333 i915_gem_object_truncate(obj
);
3335 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
3338 drm_gem_object_unreference(&obj
->base
);
3340 mutex_unlock(&dev
->struct_mutex
);
3344 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
3347 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3348 struct drm_i915_gem_object
*obj
;
3349 struct address_space
*mapping
;
3352 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
3356 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
3361 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
3362 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
3363 /* 965gm cannot relocate objects above 4GiB. */
3364 mask
&= ~__GFP_HIGHMEM
;
3365 mask
|= __GFP_DMA32
;
3368 mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3369 mapping_set_gfp_mask(mapping
, mask
);
3371 i915_gem_info_add_obj(dev_priv
, size
);
3373 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3374 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3377 /* On some devices, we can have the GPU use the LLC (the CPU
3378 * cache) for about a 10% performance improvement
3379 * compared to uncached. Graphics requests other than
3380 * display scanout are coherent with the CPU in
3381 * accessing this cache. This means in this mode we
3382 * don't need to clflush on the CPU side, and on the
3383 * GPU side we only need to flush internal caches to
3384 * get data visible to the CPU.
3386 * However, we maintain the display planes as UC, and so
3387 * need to rebind when first used as such.
3389 obj
->cache_level
= I915_CACHE_LLC
;
3391 obj
->cache_level
= I915_CACHE_NONE
;
3393 obj
->base
.driver_private
= NULL
;
3394 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3395 INIT_LIST_HEAD(&obj
->mm_list
);
3396 INIT_LIST_HEAD(&obj
->gtt_list
);
3397 INIT_LIST_HEAD(&obj
->ring_list
);
3398 INIT_LIST_HEAD(&obj
->exec_list
);
3399 obj
->madv
= I915_MADV_WILLNEED
;
3400 /* Avoid an unnecessary call to unbind on the first bind. */
3401 obj
->map_and_fenceable
= true;
3406 int i915_gem_init_object(struct drm_gem_object
*obj
)
3413 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
3415 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
3416 struct drm_device
*dev
= obj
->base
.dev
;
3417 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3419 trace_i915_gem_object_destroy(obj
);
3421 if (gem_obj
->import_attach
)
3422 drm_prime_gem_destroy(gem_obj
, obj
->sg_table
);
3425 i915_gem_detach_phys_object(dev
, obj
);
3428 if (WARN_ON(i915_gem_object_unbind(obj
) == -ERESTARTSYS
)) {
3429 bool was_interruptible
;
3431 was_interruptible
= dev_priv
->mm
.interruptible
;
3432 dev_priv
->mm
.interruptible
= false;
3434 WARN_ON(i915_gem_object_unbind(obj
));
3436 dev_priv
->mm
.interruptible
= was_interruptible
;
3439 if (obj
->base
.map_list
.map
)
3440 drm_gem_free_mmap_offset(&obj
->base
);
3442 drm_gem_object_release(&obj
->base
);
3443 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
3450 i915_gem_idle(struct drm_device
*dev
)
3452 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3455 mutex_lock(&dev
->struct_mutex
);
3457 if (dev_priv
->mm
.suspended
) {
3458 mutex_unlock(&dev
->struct_mutex
);
3462 ret
= i915_gpu_idle(dev
);
3464 mutex_unlock(&dev
->struct_mutex
);
3467 i915_gem_retire_requests(dev
);
3469 /* Under UMS, be paranoid and evict. */
3470 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3471 i915_gem_evict_everything(dev
, false);
3473 i915_gem_reset_fences(dev
);
3475 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3476 * We need to replace this with a semaphore, or something.
3477 * And not confound mm.suspended!
3479 dev_priv
->mm
.suspended
= 1;
3480 del_timer_sync(&dev_priv
->hangcheck_timer
);
3482 i915_kernel_lost_context(dev
);
3483 i915_gem_cleanup_ringbuffer(dev
);
3485 mutex_unlock(&dev
->struct_mutex
);
3487 /* Cancel the retire work handler, which should be idle now. */
3488 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
3493 void i915_gem_l3_remap(struct drm_device
*dev
)
3495 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3499 if (!IS_IVYBRIDGE(dev
))
3502 if (!dev_priv
->mm
.l3_remap_info
)
3505 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
3506 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
3507 POSTING_READ(GEN7_MISCCPCTL
);
3509 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
3510 u32 remap
= I915_READ(GEN7_L3LOG_BASE
+ i
);
3511 if (remap
&& remap
!= dev_priv
->mm
.l3_remap_info
[i
/4])
3512 DRM_DEBUG("0x%x was already programmed to %x\n",
3513 GEN7_L3LOG_BASE
+ i
, remap
);
3514 if (remap
&& !dev_priv
->mm
.l3_remap_info
[i
/4])
3515 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3516 I915_WRITE(GEN7_L3LOG_BASE
+ i
, dev_priv
->mm
.l3_remap_info
[i
/4]);
3519 /* Make sure all the writes land before disabling dop clock gating */
3520 POSTING_READ(GEN7_L3LOG_BASE
);
3522 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
3525 void i915_gem_init_swizzling(struct drm_device
*dev
)
3527 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3529 if (INTEL_INFO(dev
)->gen
< 5 ||
3530 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
3533 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
3534 DISP_TILE_SURFACE_SWIZZLING
);
3539 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
3541 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
3543 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
3546 void i915_gem_init_ppgtt(struct drm_device
*dev
)
3548 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3550 struct intel_ring_buffer
*ring
;
3551 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
3552 uint32_t __iomem
*pd_addr
;
3556 if (!dev_priv
->mm
.aliasing_ppgtt
)
3560 pd_addr
= dev_priv
->mm
.gtt
->gtt
+ ppgtt
->pd_offset
/sizeof(uint32_t);
3561 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
3564 if (dev_priv
->mm
.gtt
->needs_dmar
)
3565 pt_addr
= ppgtt
->pt_dma_addr
[i
];
3567 pt_addr
= page_to_phys(ppgtt
->pt_pages
[i
]);
3569 pd_entry
= GEN6_PDE_ADDR_ENCODE(pt_addr
);
3570 pd_entry
|= GEN6_PDE_VALID
;
3572 writel(pd_entry
, pd_addr
+ i
);
3576 pd_offset
= ppgtt
->pd_offset
;
3577 pd_offset
/= 64; /* in cachelines, */
3580 if (INTEL_INFO(dev
)->gen
== 6) {
3581 uint32_t ecochk
, gab_ctl
, ecobits
;
3583 ecobits
= I915_READ(GAC_ECO_BITS
);
3584 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
3586 gab_ctl
= I915_READ(GAB_CTL
);
3587 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
3589 ecochk
= I915_READ(GAM_ECOCHK
);
3590 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
|
3591 ECOCHK_PPGTT_CACHE64B
);
3592 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
3593 } else if (INTEL_INFO(dev
)->gen
>= 7) {
3594 I915_WRITE(GAM_ECOCHK
, ECOCHK_PPGTT_CACHE64B
);
3595 /* GFX_MODE is per-ring on gen7+ */
3598 for_each_ring(ring
, dev_priv
, i
) {
3599 if (INTEL_INFO(dev
)->gen
>= 7)
3600 I915_WRITE(RING_MODE_GEN7(ring
),
3601 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
3603 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
3604 I915_WRITE(RING_PP_DIR_BASE(ring
), pd_offset
);
3609 intel_enable_blt(struct drm_device
*dev
)
3614 /* The blitter was dysfunctional on early prototypes */
3615 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
3616 DRM_INFO("BLT not supported on this pre-production hardware;"
3617 " graphics performance will be degraded.\n");
3625 i915_gem_init_hw(struct drm_device
*dev
)
3627 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3630 if (!intel_enable_gtt())
3633 i915_gem_l3_remap(dev
);
3635 i915_gem_init_swizzling(dev
);
3637 ret
= intel_init_render_ring_buffer(dev
);
3642 ret
= intel_init_bsd_ring_buffer(dev
);
3644 goto cleanup_render_ring
;
3647 if (intel_enable_blt(dev
)) {
3648 ret
= intel_init_blt_ring_buffer(dev
);
3650 goto cleanup_bsd_ring
;
3653 dev_priv
->next_seqno
= 1;
3656 * XXX: There was some w/a described somewhere suggesting loading
3657 * contexts before PPGTT.
3659 i915_gem_context_init(dev
);
3660 i915_gem_init_ppgtt(dev
);
3665 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
3666 cleanup_render_ring
:
3667 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
3672 intel_enable_ppgtt(struct drm_device
*dev
)
3674 if (i915_enable_ppgtt
>= 0)
3675 return i915_enable_ppgtt
;
3677 #ifdef CONFIG_INTEL_IOMMU
3678 /* Disable ppgtt on SNB if VT-d is on. */
3679 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
3686 int i915_gem_init(struct drm_device
*dev
)
3688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3689 unsigned long gtt_size
, mappable_size
;
3692 gtt_size
= dev_priv
->mm
.gtt
->gtt_total_entries
<< PAGE_SHIFT
;
3693 mappable_size
= dev_priv
->mm
.gtt
->gtt_mappable_entries
<< PAGE_SHIFT
;
3695 mutex_lock(&dev
->struct_mutex
);
3696 if (intel_enable_ppgtt(dev
) && HAS_ALIASING_PPGTT(dev
)) {
3697 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
3698 * aperture accordingly when using aliasing ppgtt. */
3699 gtt_size
-= I915_PPGTT_PD_ENTRIES
*PAGE_SIZE
;
3701 i915_gem_init_global_gtt(dev
, 0, mappable_size
, gtt_size
);
3703 ret
= i915_gem_init_aliasing_ppgtt(dev
);
3705 mutex_unlock(&dev
->struct_mutex
);
3709 /* Let GEM Manage all of the aperture.
3711 * However, leave one page at the end still bound to the scratch
3712 * page. There are a number of places where the hardware
3713 * apparently prefetches past the end of the object, and we've
3714 * seen multiple hangs with the GPU head pointer stuck in a
3715 * batchbuffer bound at the last page of the aperture. One page
3716 * should be enough to keep any prefetching inside of the
3719 i915_gem_init_global_gtt(dev
, 0, mappable_size
,
3723 ret
= i915_gem_init_hw(dev
);
3724 mutex_unlock(&dev
->struct_mutex
);
3726 i915_gem_cleanup_aliasing_ppgtt(dev
);
3730 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
3731 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3732 dev_priv
->dri1
.allow_batchbuffer
= 1;
3737 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
3739 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3740 struct intel_ring_buffer
*ring
;
3743 for_each_ring(ring
, dev_priv
, i
)
3744 intel_cleanup_ring_buffer(ring
);
3748 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
3749 struct drm_file
*file_priv
)
3751 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3754 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3757 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3758 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3759 atomic_set(&dev_priv
->mm
.wedged
, 0);
3762 mutex_lock(&dev
->struct_mutex
);
3763 dev_priv
->mm
.suspended
= 0;
3765 ret
= i915_gem_init_hw(dev
);
3767 mutex_unlock(&dev
->struct_mutex
);
3771 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
3772 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
3773 mutex_unlock(&dev
->struct_mutex
);
3775 ret
= drm_irq_install(dev
);
3777 goto cleanup_ringbuffer
;
3782 mutex_lock(&dev
->struct_mutex
);
3783 i915_gem_cleanup_ringbuffer(dev
);
3784 dev_priv
->mm
.suspended
= 1;
3785 mutex_unlock(&dev
->struct_mutex
);
3791 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
3792 struct drm_file
*file_priv
)
3794 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3797 drm_irq_uninstall(dev
);
3798 return i915_gem_idle(dev
);
3802 i915_gem_lastclose(struct drm_device
*dev
)
3806 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3809 ret
= i915_gem_idle(dev
);
3811 DRM_ERROR("failed to idle hardware: %d\n", ret
);
3815 init_ring_lists(struct intel_ring_buffer
*ring
)
3817 INIT_LIST_HEAD(&ring
->active_list
);
3818 INIT_LIST_HEAD(&ring
->request_list
);
3822 i915_gem_load(struct drm_device
*dev
)
3825 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3827 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
3828 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
3829 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
3830 INIT_LIST_HEAD(&dev_priv
->mm
.gtt_list
);
3831 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
3832 init_ring_lists(&dev_priv
->ring
[i
]);
3833 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
3834 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
3835 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
3836 i915_gem_retire_work_handler
);
3837 init_completion(&dev_priv
->error_completion
);
3839 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3841 I915_WRITE(MI_ARB_STATE
,
3842 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
3845 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
3847 /* Old X drivers will take 0-2 for front, back, depth buffers */
3848 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3849 dev_priv
->fence_reg_start
= 3;
3851 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
3852 dev_priv
->num_fence_regs
= 16;
3854 dev_priv
->num_fence_regs
= 8;
3856 /* Initialize fence registers to zero */
3857 i915_gem_reset_fences(dev
);
3859 i915_gem_detect_bit_6_swizzle(dev
);
3860 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
3862 dev_priv
->mm
.interruptible
= true;
3864 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
3865 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
3866 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
3870 * Create a physically contiguous memory object for this object
3871 * e.g. for cursor + overlay regs
3873 static int i915_gem_init_phys_object(struct drm_device
*dev
,
3874 int id
, int size
, int align
)
3876 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3877 struct drm_i915_gem_phys_object
*phys_obj
;
3880 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
3883 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
3889 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
3890 if (!phys_obj
->handle
) {
3895 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
3898 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
3906 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
3908 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3909 struct drm_i915_gem_phys_object
*phys_obj
;
3911 if (!dev_priv
->mm
.phys_objs
[id
- 1])
3914 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
3915 if (phys_obj
->cur_obj
) {
3916 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
3920 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
3922 drm_pci_free(dev
, phys_obj
->handle
);
3924 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
3927 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
3931 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
3932 i915_gem_free_phys_object(dev
, i
);
3935 void i915_gem_detach_phys_object(struct drm_device
*dev
,
3936 struct drm_i915_gem_object
*obj
)
3938 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3945 vaddr
= obj
->phys_obj
->handle
->vaddr
;
3947 page_count
= obj
->base
.size
/ PAGE_SIZE
;
3948 for (i
= 0; i
< page_count
; i
++) {
3949 struct page
*page
= shmem_read_mapping_page(mapping
, i
);
3950 if (!IS_ERR(page
)) {
3951 char *dst
= kmap_atomic(page
);
3952 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
3955 drm_clflush_pages(&page
, 1);
3957 set_page_dirty(page
);
3958 mark_page_accessed(page
);
3959 page_cache_release(page
);
3962 intel_gtt_chipset_flush();
3964 obj
->phys_obj
->cur_obj
= NULL
;
3965 obj
->phys_obj
= NULL
;
3969 i915_gem_attach_phys_object(struct drm_device
*dev
,
3970 struct drm_i915_gem_object
*obj
,
3974 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3975 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3980 if (id
> I915_MAX_PHYS_OBJECT
)
3983 if (obj
->phys_obj
) {
3984 if (obj
->phys_obj
->id
== id
)
3986 i915_gem_detach_phys_object(dev
, obj
);
3989 /* create a new object */
3990 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
3991 ret
= i915_gem_init_phys_object(dev
, id
,
3992 obj
->base
.size
, align
);
3994 DRM_ERROR("failed to init phys object %d size: %zu\n",
3995 id
, obj
->base
.size
);
4000 /* bind to the object */
4001 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4002 obj
->phys_obj
->cur_obj
= obj
;
4004 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4006 for (i
= 0; i
< page_count
; i
++) {
4010 page
= shmem_read_mapping_page(mapping
, i
);
4012 return PTR_ERR(page
);
4014 src
= kmap_atomic(page
);
4015 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4016 memcpy(dst
, src
, PAGE_SIZE
);
4019 mark_page_accessed(page
);
4020 page_cache_release(page
);
4027 i915_gem_phys_pwrite(struct drm_device
*dev
,
4028 struct drm_i915_gem_object
*obj
,
4029 struct drm_i915_gem_pwrite
*args
,
4030 struct drm_file
*file_priv
)
4032 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
4033 char __user
*user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4035 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
4036 unsigned long unwritten
;
4038 /* The physical object once assigned is fixed for the lifetime
4039 * of the obj, so we can safely drop the lock and continue
4042 mutex_unlock(&dev
->struct_mutex
);
4043 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
4044 mutex_lock(&dev
->struct_mutex
);
4049 intel_gtt_chipset_flush();
4053 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4055 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4057 /* Clean up our request list when the client is going away, so that
4058 * later retire_requests won't dereference our soon-to-be-gone
4061 spin_lock(&file_priv
->mm
.lock
);
4062 while (!list_empty(&file_priv
->mm
.request_list
)) {
4063 struct drm_i915_gem_request
*request
;
4065 request
= list_first_entry(&file_priv
->mm
.request_list
,
4066 struct drm_i915_gem_request
,
4068 list_del(&request
->client_list
);
4069 request
->file_priv
= NULL
;
4071 spin_unlock(&file_priv
->mm
.lock
);
4075 i915_gpu_is_active(struct drm_device
*dev
)
4077 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4078 return !list_empty(&dev_priv
->mm
.active_list
);
4082 i915_gem_inactive_shrink(struct shrinker
*shrinker
, struct shrink_control
*sc
)
4084 struct drm_i915_private
*dev_priv
=
4085 container_of(shrinker
,
4086 struct drm_i915_private
,
4087 mm
.inactive_shrinker
);
4088 struct drm_device
*dev
= dev_priv
->dev
;
4089 struct drm_i915_gem_object
*obj
, *next
;
4090 int nr_to_scan
= sc
->nr_to_scan
;
4093 if (!mutex_trylock(&dev
->struct_mutex
))
4096 /* "fast-path" to count number of available objects */
4097 if (nr_to_scan
== 0) {
4099 list_for_each_entry(obj
,
4100 &dev_priv
->mm
.inactive_list
,
4103 mutex_unlock(&dev
->struct_mutex
);
4104 return cnt
/ 100 * sysctl_vfs_cache_pressure
;
4108 /* first scan for clean buffers */
4109 i915_gem_retire_requests(dev
);
4111 list_for_each_entry_safe(obj
, next
,
4112 &dev_priv
->mm
.inactive_list
,
4114 if (i915_gem_object_is_purgeable(obj
)) {
4115 if (i915_gem_object_unbind(obj
) == 0 &&
4121 /* second pass, evict/count anything still on the inactive list */
4123 list_for_each_entry_safe(obj
, next
,
4124 &dev_priv
->mm
.inactive_list
,
4127 i915_gem_object_unbind(obj
) == 0)
4133 if (nr_to_scan
&& i915_gpu_is_active(dev
)) {
4135 * We are desperate for pages, so as a last resort, wait
4136 * for the GPU to finish and discard whatever we can.
4137 * This has a dramatic impact to reduce the number of
4138 * OOM-killer events whilst running the GPU aggressively.
4140 if (i915_gpu_idle(dev
) == 0)
4143 mutex_unlock(&dev
->struct_mutex
);
4144 return cnt
/ 100 * sysctl_vfs_cache_pressure
;