2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 #define RQ_BUG_ON(expr)
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
46 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
);
48 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
);
50 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
51 enum i915_cache_level level
)
53 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
56 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
58 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
61 return obj
->pin_display
;
64 /* some bookkeeping */
65 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
68 spin_lock(&dev_priv
->mm
.object_stat_lock
);
69 dev_priv
->mm
.object_count
++;
70 dev_priv
->mm
.object_memory
+= size
;
71 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
74 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
77 spin_lock(&dev_priv
->mm
.object_stat_lock
);
78 dev_priv
->mm
.object_count
--;
79 dev_priv
->mm
.object_memory
-= size
;
80 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
84 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
88 #define EXIT_COND (!i915_reset_in_progress(error) || \
89 i915_terminally_wedged(error))
94 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
95 * userspace. If it takes that long something really bad is going on and
96 * we should simply try to bail out and fail as gracefully as possible.
98 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
102 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
104 } else if (ret
< 0) {
112 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
114 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
117 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
121 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
125 WARN_ON(i915_verify_lists(dev
));
130 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
131 struct drm_file
*file
)
133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
134 struct drm_i915_gem_get_aperture
*args
= data
;
135 struct i915_gtt
*ggtt
= &dev_priv
->gtt
;
136 struct i915_vma
*vma
;
140 mutex_lock(&dev
->struct_mutex
);
141 list_for_each_entry(vma
, &ggtt
->base
.active_list
, mm_list
)
143 pinned
+= vma
->node
.size
;
144 list_for_each_entry(vma
, &ggtt
->base
.inactive_list
, mm_list
)
146 pinned
+= vma
->node
.size
;
147 mutex_unlock(&dev
->struct_mutex
);
149 args
->aper_size
= dev_priv
->gtt
.base
.total
;
150 args
->aper_available_size
= args
->aper_size
- pinned
;
156 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
158 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
159 char *vaddr
= obj
->phys_handle
->vaddr
;
161 struct scatterlist
*sg
;
164 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
167 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
171 page
= shmem_read_mapping_page(mapping
, i
);
173 return PTR_ERR(page
);
175 src
= kmap_atomic(page
);
176 memcpy(vaddr
, src
, PAGE_SIZE
);
177 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
180 page_cache_release(page
);
184 i915_gem_chipset_flush(obj
->base
.dev
);
186 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
190 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
197 sg
->length
= obj
->base
.size
;
199 sg_dma_address(sg
) = obj
->phys_handle
->busaddr
;
200 sg_dma_len(sg
) = obj
->base
.size
;
207 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
)
211 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
213 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
215 /* In the event of a disaster, abandon all caches and
218 WARN_ON(ret
!= -EIO
);
219 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
222 if (obj
->madv
== I915_MADV_DONTNEED
)
226 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
227 char *vaddr
= obj
->phys_handle
->vaddr
;
230 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
234 page
= shmem_read_mapping_page(mapping
, i
);
238 dst
= kmap_atomic(page
);
239 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
240 memcpy(dst
, vaddr
, PAGE_SIZE
);
243 set_page_dirty(page
);
244 if (obj
->madv
== I915_MADV_WILLNEED
)
245 mark_page_accessed(page
);
246 page_cache_release(page
);
252 sg_free_table(obj
->pages
);
257 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
259 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
262 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
263 .get_pages
= i915_gem_object_get_pages_phys
,
264 .put_pages
= i915_gem_object_put_pages_phys
,
265 .release
= i915_gem_object_release_phys
,
269 drop_pages(struct drm_i915_gem_object
*obj
)
271 struct i915_vma
*vma
, *next
;
274 drm_gem_object_reference(&obj
->base
);
275 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
)
276 if (i915_vma_unbind(vma
))
279 ret
= i915_gem_object_put_pages(obj
);
280 drm_gem_object_unreference(&obj
->base
);
286 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
289 drm_dma_handle_t
*phys
;
292 if (obj
->phys_handle
) {
293 if ((unsigned long)obj
->phys_handle
->vaddr
& (align
-1))
299 if (obj
->madv
!= I915_MADV_WILLNEED
)
302 if (obj
->base
.filp
== NULL
)
305 ret
= drop_pages(obj
);
309 /* create a new object */
310 phys
= drm_pci_alloc(obj
->base
.dev
, obj
->base
.size
, align
);
314 obj
->phys_handle
= phys
;
315 obj
->ops
= &i915_gem_phys_ops
;
317 return i915_gem_object_get_pages(obj
);
321 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
322 struct drm_i915_gem_pwrite
*args
,
323 struct drm_file
*file_priv
)
325 struct drm_device
*dev
= obj
->base
.dev
;
326 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
327 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
330 /* We manually control the domain here and pretend that it
331 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
333 ret
= i915_gem_object_wait_rendering(obj
, false);
337 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
338 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
339 unsigned long unwritten
;
341 /* The physical object once assigned is fixed for the lifetime
342 * of the obj, so we can safely drop the lock and continue
345 mutex_unlock(&dev
->struct_mutex
);
346 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
347 mutex_lock(&dev
->struct_mutex
);
354 drm_clflush_virt_range(vaddr
, args
->size
);
355 i915_gem_chipset_flush(dev
);
358 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
362 void *i915_gem_object_alloc(struct drm_device
*dev
)
364 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
365 return kmem_cache_zalloc(dev_priv
->objects
, GFP_KERNEL
);
368 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
370 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
371 kmem_cache_free(dev_priv
->objects
, obj
);
375 i915_gem_create(struct drm_file
*file
,
376 struct drm_device
*dev
,
380 struct drm_i915_gem_object
*obj
;
384 size
= roundup(size
, PAGE_SIZE
);
388 /* Allocate the new object */
389 obj
= i915_gem_alloc_object(dev
, size
);
393 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
394 /* drop reference from allocate - handle holds it now */
395 drm_gem_object_unreference_unlocked(&obj
->base
);
404 i915_gem_dumb_create(struct drm_file
*file
,
405 struct drm_device
*dev
,
406 struct drm_mode_create_dumb
*args
)
408 /* have to work out size/pitch and return them */
409 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
410 args
->size
= args
->pitch
* args
->height
;
411 return i915_gem_create(file
, dev
,
412 args
->size
, &args
->handle
);
416 * Creates a new mm object and returns a handle to it.
419 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
420 struct drm_file
*file
)
422 struct drm_i915_gem_create
*args
= data
;
424 return i915_gem_create(file
, dev
,
425 args
->size
, &args
->handle
);
429 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
430 const char *gpu_vaddr
, int gpu_offset
,
433 int ret
, cpu_offset
= 0;
436 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
437 int this_length
= min(cacheline_end
- gpu_offset
, length
);
438 int swizzled_gpu_offset
= gpu_offset
^ 64;
440 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
441 gpu_vaddr
+ swizzled_gpu_offset
,
446 cpu_offset
+= this_length
;
447 gpu_offset
+= this_length
;
448 length
-= this_length
;
455 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
456 const char __user
*cpu_vaddr
,
459 int ret
, cpu_offset
= 0;
462 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
463 int this_length
= min(cacheline_end
- gpu_offset
, length
);
464 int swizzled_gpu_offset
= gpu_offset
^ 64;
466 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
467 cpu_vaddr
+ cpu_offset
,
472 cpu_offset
+= this_length
;
473 gpu_offset
+= this_length
;
474 length
-= this_length
;
481 * Pins the specified object's pages and synchronizes the object with
482 * GPU accesses. Sets needs_clflush to non-zero if the caller should
483 * flush the object from the CPU cache.
485 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
495 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
496 /* If we're not in the cpu read domain, set ourself into the gtt
497 * read domain and manually flush cachelines (if required). This
498 * optimizes for the case when the gpu will dirty the data
499 * anyway again before the next pread happens. */
500 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
502 ret
= i915_gem_object_wait_rendering(obj
, true);
507 ret
= i915_gem_object_get_pages(obj
);
511 i915_gem_object_pin_pages(obj
);
516 /* Per-page copy function for the shmem pread fastpath.
517 * Flushes invalid cachelines before reading the target if
518 * needs_clflush is set. */
520 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
521 char __user
*user_data
,
522 bool page_do_bit17_swizzling
, bool needs_clflush
)
527 if (unlikely(page_do_bit17_swizzling
))
530 vaddr
= kmap_atomic(page
);
532 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
534 ret
= __copy_to_user_inatomic(user_data
,
535 vaddr
+ shmem_page_offset
,
537 kunmap_atomic(vaddr
);
539 return ret
? -EFAULT
: 0;
543 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
546 if (unlikely(swizzled
)) {
547 unsigned long start
= (unsigned long) addr
;
548 unsigned long end
= (unsigned long) addr
+ length
;
550 /* For swizzling simply ensure that we always flush both
551 * channels. Lame, but simple and it works. Swizzled
552 * pwrite/pread is far from a hotpath - current userspace
553 * doesn't use it at all. */
554 start
= round_down(start
, 128);
555 end
= round_up(end
, 128);
557 drm_clflush_virt_range((void *)start
, end
- start
);
559 drm_clflush_virt_range(addr
, length
);
564 /* Only difference to the fast-path function is that this can handle bit17
565 * and uses non-atomic copy and kmap functions. */
567 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
568 char __user
*user_data
,
569 bool page_do_bit17_swizzling
, bool needs_clflush
)
576 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
578 page_do_bit17_swizzling
);
580 if (page_do_bit17_swizzling
)
581 ret
= __copy_to_user_swizzled(user_data
,
582 vaddr
, shmem_page_offset
,
585 ret
= __copy_to_user(user_data
,
586 vaddr
+ shmem_page_offset
,
590 return ret
? - EFAULT
: 0;
594 i915_gem_shmem_pread(struct drm_device
*dev
,
595 struct drm_i915_gem_object
*obj
,
596 struct drm_i915_gem_pread
*args
,
597 struct drm_file
*file
)
599 char __user
*user_data
;
602 int shmem_page_offset
, page_length
, ret
= 0;
603 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
605 int needs_clflush
= 0;
606 struct sg_page_iter sg_iter
;
608 user_data
= to_user_ptr(args
->data_ptr
);
611 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
613 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
617 offset
= args
->offset
;
619 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
620 offset
>> PAGE_SHIFT
) {
621 struct page
*page
= sg_page_iter_page(&sg_iter
);
626 /* Operation in this page
628 * shmem_page_offset = offset within page in shmem file
629 * page_length = bytes to copy for this page
631 shmem_page_offset
= offset_in_page(offset
);
632 page_length
= remain
;
633 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
634 page_length
= PAGE_SIZE
- shmem_page_offset
;
636 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
637 (page_to_phys(page
) & (1 << 17)) != 0;
639 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
640 user_data
, page_do_bit17_swizzling
,
645 mutex_unlock(&dev
->struct_mutex
);
647 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
648 ret
= fault_in_multipages_writeable(user_data
, remain
);
649 /* Userspace is tricking us, but we've already clobbered
650 * its pages with the prefault and promised to write the
651 * data up to the first fault. Hence ignore any errors
652 * and just continue. */
657 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
658 user_data
, page_do_bit17_swizzling
,
661 mutex_lock(&dev
->struct_mutex
);
667 remain
-= page_length
;
668 user_data
+= page_length
;
669 offset
+= page_length
;
673 i915_gem_object_unpin_pages(obj
);
679 * Reads data from the object referenced by handle.
681 * On error, the contents of *data are undefined.
684 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
685 struct drm_file
*file
)
687 struct drm_i915_gem_pread
*args
= data
;
688 struct drm_i915_gem_object
*obj
;
694 if (!access_ok(VERIFY_WRITE
,
695 to_user_ptr(args
->data_ptr
),
699 ret
= i915_mutex_lock_interruptible(dev
);
703 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
704 if (&obj
->base
== NULL
) {
709 /* Bounds check source. */
710 if (args
->offset
> obj
->base
.size
||
711 args
->size
> obj
->base
.size
- args
->offset
) {
716 /* prime objects have no backing filp to GEM pread/pwrite
719 if (!obj
->base
.filp
) {
724 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
726 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
729 drm_gem_object_unreference(&obj
->base
);
731 mutex_unlock(&dev
->struct_mutex
);
735 /* This is the fast write path which cannot handle
736 * page faults in the source data
740 fast_user_write(struct io_mapping
*mapping
,
741 loff_t page_base
, int page_offset
,
742 char __user
*user_data
,
745 void __iomem
*vaddr_atomic
;
747 unsigned long unwritten
;
749 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
750 /* We can use the cpu mem copy function because this is X86. */
751 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
752 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
754 io_mapping_unmap_atomic(vaddr_atomic
);
759 * This is the fast pwrite path, where we copy the data directly from the
760 * user into the GTT, uncached.
763 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
764 struct drm_i915_gem_object
*obj
,
765 struct drm_i915_gem_pwrite
*args
,
766 struct drm_file
*file
)
768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
770 loff_t offset
, page_base
;
771 char __user
*user_data
;
772 int page_offset
, page_length
, ret
;
774 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
778 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
782 ret
= i915_gem_object_put_fence(obj
);
786 user_data
= to_user_ptr(args
->data_ptr
);
789 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
791 intel_fb_obj_invalidate(obj
, ORIGIN_GTT
);
794 /* Operation in this page
796 * page_base = page offset within aperture
797 * page_offset = offset within page
798 * page_length = bytes to copy for this page
800 page_base
= offset
& PAGE_MASK
;
801 page_offset
= offset_in_page(offset
);
802 page_length
= remain
;
803 if ((page_offset
+ remain
) > PAGE_SIZE
)
804 page_length
= PAGE_SIZE
- page_offset
;
806 /* If we get a fault while copying data, then (presumably) our
807 * source page isn't available. Return the error and we'll
808 * retry in the slow path.
810 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
811 page_offset
, user_data
, page_length
)) {
816 remain
-= page_length
;
817 user_data
+= page_length
;
818 offset
+= page_length
;
822 intel_fb_obj_flush(obj
, false, ORIGIN_GTT
);
824 i915_gem_object_ggtt_unpin(obj
);
829 /* Per-page copy function for the shmem pwrite fastpath.
830 * Flushes invalid cachelines before writing to the target if
831 * needs_clflush_before is set and flushes out any written cachelines after
832 * writing if needs_clflush is set. */
834 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
835 char __user
*user_data
,
836 bool page_do_bit17_swizzling
,
837 bool needs_clflush_before
,
838 bool needs_clflush_after
)
843 if (unlikely(page_do_bit17_swizzling
))
846 vaddr
= kmap_atomic(page
);
847 if (needs_clflush_before
)
848 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
850 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
851 user_data
, page_length
);
852 if (needs_clflush_after
)
853 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
855 kunmap_atomic(vaddr
);
857 return ret
? -EFAULT
: 0;
860 /* Only difference to the fast-path function is that this can handle bit17
861 * and uses non-atomic copy and kmap functions. */
863 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
864 char __user
*user_data
,
865 bool page_do_bit17_swizzling
,
866 bool needs_clflush_before
,
867 bool needs_clflush_after
)
873 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
874 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
876 page_do_bit17_swizzling
);
877 if (page_do_bit17_swizzling
)
878 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
882 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
885 if (needs_clflush_after
)
886 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
888 page_do_bit17_swizzling
);
891 return ret
? -EFAULT
: 0;
895 i915_gem_shmem_pwrite(struct drm_device
*dev
,
896 struct drm_i915_gem_object
*obj
,
897 struct drm_i915_gem_pwrite
*args
,
898 struct drm_file
*file
)
902 char __user
*user_data
;
903 int shmem_page_offset
, page_length
, ret
= 0;
904 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
905 int hit_slowpath
= 0;
906 int needs_clflush_after
= 0;
907 int needs_clflush_before
= 0;
908 struct sg_page_iter sg_iter
;
910 user_data
= to_user_ptr(args
->data_ptr
);
913 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
915 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
916 /* If we're not in the cpu write domain, set ourself into the gtt
917 * write domain and manually flush cachelines (if required). This
918 * optimizes for the case when the gpu will use the data
919 * right away and we therefore have to clflush anyway. */
920 needs_clflush_after
= cpu_write_needs_clflush(obj
);
921 ret
= i915_gem_object_wait_rendering(obj
, false);
925 /* Same trick applies to invalidate partially written cachelines read
927 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
928 needs_clflush_before
=
929 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
931 ret
= i915_gem_object_get_pages(obj
);
935 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
937 i915_gem_object_pin_pages(obj
);
939 offset
= args
->offset
;
942 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
943 offset
>> PAGE_SHIFT
) {
944 struct page
*page
= sg_page_iter_page(&sg_iter
);
945 int partial_cacheline_write
;
950 /* Operation in this page
952 * shmem_page_offset = offset within page in shmem file
953 * page_length = bytes to copy for this page
955 shmem_page_offset
= offset_in_page(offset
);
957 page_length
= remain
;
958 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
959 page_length
= PAGE_SIZE
- shmem_page_offset
;
961 /* If we don't overwrite a cacheline completely we need to be
962 * careful to have up-to-date data by first clflushing. Don't
963 * overcomplicate things and flush the entire patch. */
964 partial_cacheline_write
= needs_clflush_before
&&
965 ((shmem_page_offset
| page_length
)
966 & (boot_cpu_data
.x86_clflush_size
- 1));
968 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
969 (page_to_phys(page
) & (1 << 17)) != 0;
971 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
972 user_data
, page_do_bit17_swizzling
,
973 partial_cacheline_write
,
974 needs_clflush_after
);
979 mutex_unlock(&dev
->struct_mutex
);
980 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
981 user_data
, page_do_bit17_swizzling
,
982 partial_cacheline_write
,
983 needs_clflush_after
);
985 mutex_lock(&dev
->struct_mutex
);
991 remain
-= page_length
;
992 user_data
+= page_length
;
993 offset
+= page_length
;
997 i915_gem_object_unpin_pages(obj
);
1001 * Fixup: Flush cpu caches in case we didn't flush the dirty
1002 * cachelines in-line while writing and the object moved
1003 * out of the cpu write domain while we've dropped the lock.
1005 if (!needs_clflush_after
&&
1006 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1007 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
1008 needs_clflush_after
= true;
1012 if (needs_clflush_after
)
1013 i915_gem_chipset_flush(dev
);
1015 obj
->cache_dirty
= true;
1017 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
1022 * Writes data to the object referenced by handle.
1024 * On error, the contents of the buffer that were to be modified are undefined.
1027 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1028 struct drm_file
*file
)
1030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1031 struct drm_i915_gem_pwrite
*args
= data
;
1032 struct drm_i915_gem_object
*obj
;
1035 if (args
->size
== 0)
1038 if (!access_ok(VERIFY_READ
,
1039 to_user_ptr(args
->data_ptr
),
1043 if (likely(!i915
.prefault_disable
)) {
1044 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
1050 intel_runtime_pm_get(dev_priv
);
1052 ret
= i915_mutex_lock_interruptible(dev
);
1056 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1057 if (&obj
->base
== NULL
) {
1062 /* Bounds check destination. */
1063 if (args
->offset
> obj
->base
.size
||
1064 args
->size
> obj
->base
.size
- args
->offset
) {
1069 /* prime objects have no backing filp to GEM pread/pwrite
1072 if (!obj
->base
.filp
) {
1077 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1080 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1081 * it would end up going through the fenced access, and we'll get
1082 * different detiling behavior between reading and writing.
1083 * pread/pwrite currently are reading and writing from the CPU
1084 * perspective, requiring manual detiling by the client.
1086 if (obj
->tiling_mode
== I915_TILING_NONE
&&
1087 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
1088 cpu_write_needs_clflush(obj
)) {
1089 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1090 /* Note that the gtt paths might fail with non-page-backed user
1091 * pointers (e.g. gtt mappings when moving data between
1092 * textures). Fallback to the shmem path in that case. */
1095 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1096 if (obj
->phys_handle
)
1097 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1099 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
1103 drm_gem_object_unreference(&obj
->base
);
1105 mutex_unlock(&dev
->struct_mutex
);
1107 intel_runtime_pm_put(dev_priv
);
1113 i915_gem_check_wedge(struct i915_gpu_error
*error
,
1116 if (i915_reset_in_progress(error
)) {
1117 /* Non-interruptible callers can't handle -EAGAIN, hence return
1118 * -EIO unconditionally for these. */
1122 /* Recovery complete, but the reset failed ... */
1123 if (i915_terminally_wedged(error
))
1127 * Check if GPU Reset is in progress - we need intel_ring_begin
1128 * to work properly to reinit the hw state while the gpu is
1129 * still marked as reset-in-progress. Handle this with a flag.
1131 if (!error
->reload_in_reset
)
1138 static void fake_irq(unsigned long data
)
1140 wake_up_process((struct task_struct
*)data
);
1143 static bool missed_irq(struct drm_i915_private
*dev_priv
,
1144 struct intel_engine_cs
*ring
)
1146 return test_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
1149 static unsigned long local_clock_us(unsigned *cpu
)
1153 /* Cheaply and approximately convert from nanoseconds to microseconds.
1154 * The result and subsequent calculations are also defined in the same
1155 * approximate microseconds units. The principal source of timing
1156 * error here is from the simple truncation.
1158 * Note that local_clock() is only defined wrt to the current CPU;
1159 * the comparisons are no longer valid if we switch CPUs. Instead of
1160 * blocking preemption for the entire busywait, we can detect the CPU
1161 * switch and use that as indicator of system load and a reason to
1162 * stop busywaiting, see busywait_stop().
1165 t
= local_clock() >> 10;
1171 static bool busywait_stop(unsigned long timeout
, unsigned cpu
)
1175 if (time_after(local_clock_us(&this_cpu
), timeout
))
1178 return this_cpu
!= cpu
;
1181 static int __i915_spin_request(struct drm_i915_gem_request
*req
, int state
)
1183 unsigned long timeout
;
1186 /* When waiting for high frequency requests, e.g. during synchronous
1187 * rendering split between the CPU and GPU, the finite amount of time
1188 * required to set up the irq and wait upon it limits the response
1189 * rate. By busywaiting on the request completion for a short while we
1190 * can service the high frequency waits as quick as possible. However,
1191 * if it is a slow request, we want to sleep as quickly as possible.
1192 * The tradeoff between waiting and sleeping is roughly the time it
1193 * takes to sleep on a request, on the order of a microsecond.
1196 if (req
->ring
->irq_refcount
)
1199 /* Only spin if we know the GPU is processing this request */
1200 if (!i915_gem_request_started(req
, true))
1203 timeout
= local_clock_us(&cpu
) + 5;
1204 while (!need_resched()) {
1205 if (i915_gem_request_completed(req
, true))
1208 if (signal_pending_state(state
, current
))
1211 if (busywait_stop(timeout
, cpu
))
1214 cpu_relax_lowlatency();
1217 if (i915_gem_request_completed(req
, false))
1224 * __i915_wait_request - wait until execution of request has finished
1226 * @reset_counter: reset sequence associated with the given request
1227 * @interruptible: do an interruptible wait (normally yes)
1228 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1230 * Note: It is of utmost importance that the passed in seqno and reset_counter
1231 * values have been read by the caller in an smp safe manner. Where read-side
1232 * locks are involved, it is sufficient to read the reset_counter before
1233 * unlocking the lock that protects the seqno. For lockless tricks, the
1234 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1237 * Returns 0 if the request was found within the alloted time. Else returns the
1238 * errno with remaining time filled in timeout argument.
1240 int __i915_wait_request(struct drm_i915_gem_request
*req
,
1241 unsigned reset_counter
,
1244 struct intel_rps_client
*rps
)
1246 struct intel_engine_cs
*ring
= i915_gem_request_get_ring(req
);
1247 struct drm_device
*dev
= ring
->dev
;
1248 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1249 const bool irq_test_in_progress
=
1250 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_ring_flag(ring
);
1251 int state
= interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
;
1253 unsigned long timeout_expire
;
1257 WARN(!intel_irqs_enabled(dev_priv
), "IRQs disabled");
1259 if (list_empty(&req
->list
))
1262 if (i915_gem_request_completed(req
, true))
1267 if (WARN_ON(*timeout
< 0))
1273 timeout_expire
= jiffies
+ nsecs_to_jiffies_timeout(*timeout
);
1276 if (INTEL_INFO(dev_priv
)->gen
>= 6)
1277 gen6_rps_boost(dev_priv
, rps
, req
->emitted_jiffies
);
1279 /* Record current time in case interrupted by signal, or wedged */
1280 trace_i915_gem_request_wait_begin(req
);
1281 before
= ktime_get_raw_ns();
1283 /* Optimistic spin for the next jiffie before touching IRQs */
1284 ret
= __i915_spin_request(req
, state
);
1288 if (!irq_test_in_progress
&& WARN_ON(!ring
->irq_get(ring
))) {
1294 struct timer_list timer
;
1296 prepare_to_wait(&ring
->irq_queue
, &wait
, state
);
1298 /* We need to check whether any gpu reset happened in between
1299 * the caller grabbing the seqno and now ... */
1300 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
)) {
1301 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1302 * is truely gone. */
1303 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1309 if (i915_gem_request_completed(req
, false)) {
1314 if (signal_pending_state(state
, current
)) {
1319 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1324 timer
.function
= NULL
;
1325 if (timeout
|| missed_irq(dev_priv
, ring
)) {
1326 unsigned long expire
;
1328 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1329 expire
= missed_irq(dev_priv
, ring
) ? jiffies
+ 1 : timeout_expire
;
1330 mod_timer(&timer
, expire
);
1335 if (timer
.function
) {
1336 del_singleshot_timer_sync(&timer
);
1337 destroy_timer_on_stack(&timer
);
1340 if (!irq_test_in_progress
)
1341 ring
->irq_put(ring
);
1343 finish_wait(&ring
->irq_queue
, &wait
);
1346 now
= ktime_get_raw_ns();
1347 trace_i915_gem_request_wait_end(req
);
1350 s64 tres
= *timeout
- (now
- before
);
1352 *timeout
= tres
< 0 ? 0 : tres
;
1355 * Apparently ktime isn't accurate enough and occasionally has a
1356 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1357 * things up to make the test happy. We allow up to 1 jiffy.
1359 * This is a regrssion from the timespec->ktime conversion.
1361 if (ret
== -ETIME
&& *timeout
< jiffies_to_usecs(1)*1000)
1368 int i915_gem_request_add_to_client(struct drm_i915_gem_request
*req
,
1369 struct drm_file
*file
)
1371 struct drm_i915_private
*dev_private
;
1372 struct drm_i915_file_private
*file_priv
;
1374 WARN_ON(!req
|| !file
|| req
->file_priv
);
1382 dev_private
= req
->ring
->dev
->dev_private
;
1383 file_priv
= file
->driver_priv
;
1385 spin_lock(&file_priv
->mm
.lock
);
1386 req
->file_priv
= file_priv
;
1387 list_add_tail(&req
->client_list
, &file_priv
->mm
.request_list
);
1388 spin_unlock(&file_priv
->mm
.lock
);
1390 req
->pid
= get_pid(task_pid(current
));
1396 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1398 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1403 spin_lock(&file_priv
->mm
.lock
);
1404 list_del(&request
->client_list
);
1405 request
->file_priv
= NULL
;
1406 spin_unlock(&file_priv
->mm
.lock
);
1408 put_pid(request
->pid
);
1409 request
->pid
= NULL
;
1412 static void i915_gem_request_retire(struct drm_i915_gem_request
*request
)
1414 trace_i915_gem_request_retire(request
);
1416 /* We know the GPU must have read the request to have
1417 * sent us the seqno + interrupt, so use the position
1418 * of tail of the request to update the last known position
1421 * Note this requires that we are always called in request
1424 request
->ringbuf
->last_retired_head
= request
->postfix
;
1426 list_del_init(&request
->list
);
1427 i915_gem_request_remove_from_client(request
);
1429 i915_gem_request_unreference(request
);
1433 __i915_gem_request_retire__upto(struct drm_i915_gem_request
*req
)
1435 struct intel_engine_cs
*engine
= req
->ring
;
1436 struct drm_i915_gem_request
*tmp
;
1438 lockdep_assert_held(&engine
->dev
->struct_mutex
);
1440 if (list_empty(&req
->list
))
1444 tmp
= list_first_entry(&engine
->request_list
,
1445 typeof(*tmp
), list
);
1447 i915_gem_request_retire(tmp
);
1448 } while (tmp
!= req
);
1450 WARN_ON(i915_verify_lists(engine
->dev
));
1454 * Waits for a request to be signaled, and cleans up the
1455 * request and object lists appropriately for that event.
1458 i915_wait_request(struct drm_i915_gem_request
*req
)
1460 struct drm_device
*dev
;
1461 struct drm_i915_private
*dev_priv
;
1465 BUG_ON(req
== NULL
);
1467 dev
= req
->ring
->dev
;
1468 dev_priv
= dev
->dev_private
;
1469 interruptible
= dev_priv
->mm
.interruptible
;
1471 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1473 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1477 ret
= __i915_wait_request(req
,
1478 atomic_read(&dev_priv
->gpu_error
.reset_counter
),
1479 interruptible
, NULL
, NULL
);
1483 __i915_gem_request_retire__upto(req
);
1488 * Ensures that all rendering to the object has completed and the object is
1489 * safe to unbind from the GTT or access from the CPU.
1492 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1501 if (obj
->last_write_req
!= NULL
) {
1502 ret
= i915_wait_request(obj
->last_write_req
);
1506 i
= obj
->last_write_req
->ring
->id
;
1507 if (obj
->last_read_req
[i
] == obj
->last_write_req
)
1508 i915_gem_object_retire__read(obj
, i
);
1510 i915_gem_object_retire__write(obj
);
1513 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1514 if (obj
->last_read_req
[i
] == NULL
)
1517 ret
= i915_wait_request(obj
->last_read_req
[i
]);
1521 i915_gem_object_retire__read(obj
, i
);
1523 RQ_BUG_ON(obj
->active
);
1530 i915_gem_object_retire_request(struct drm_i915_gem_object
*obj
,
1531 struct drm_i915_gem_request
*req
)
1533 int ring
= req
->ring
->id
;
1535 if (obj
->last_read_req
[ring
] == req
)
1536 i915_gem_object_retire__read(obj
, ring
);
1537 else if (obj
->last_write_req
== req
)
1538 i915_gem_object_retire__write(obj
);
1540 __i915_gem_request_retire__upto(req
);
1543 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1544 * as the object state may change during this call.
1546 static __must_check
int
1547 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1548 struct intel_rps_client
*rps
,
1551 struct drm_device
*dev
= obj
->base
.dev
;
1552 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1553 struct drm_i915_gem_request
*requests
[I915_NUM_RINGS
];
1554 unsigned reset_counter
;
1557 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1558 BUG_ON(!dev_priv
->mm
.interruptible
);
1563 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1567 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1570 struct drm_i915_gem_request
*req
;
1572 req
= obj
->last_write_req
;
1576 requests
[n
++] = i915_gem_request_reference(req
);
1578 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1579 struct drm_i915_gem_request
*req
;
1581 req
= obj
->last_read_req
[i
];
1585 requests
[n
++] = i915_gem_request_reference(req
);
1589 mutex_unlock(&dev
->struct_mutex
);
1590 for (i
= 0; ret
== 0 && i
< n
; i
++)
1591 ret
= __i915_wait_request(requests
[i
], reset_counter
, true,
1593 mutex_lock(&dev
->struct_mutex
);
1595 for (i
= 0; i
< n
; i
++) {
1597 i915_gem_object_retire_request(obj
, requests
[i
]);
1598 i915_gem_request_unreference(requests
[i
]);
1604 static struct intel_rps_client
*to_rps_client(struct drm_file
*file
)
1606 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
1611 * Called when user space prepares to use an object with the CPU, either
1612 * through the mmap ioctl's mapping or a GTT mapping.
1615 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1616 struct drm_file
*file
)
1618 struct drm_i915_gem_set_domain
*args
= data
;
1619 struct drm_i915_gem_object
*obj
;
1620 uint32_t read_domains
= args
->read_domains
;
1621 uint32_t write_domain
= args
->write_domain
;
1624 /* Only handle setting domains to types used by the CPU. */
1625 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1628 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1631 /* Having something in the write domain implies it's in the read
1632 * domain, and only that read domain. Enforce that in the request.
1634 if (write_domain
!= 0 && read_domains
!= write_domain
)
1637 ret
= i915_mutex_lock_interruptible(dev
);
1641 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1642 if (&obj
->base
== NULL
) {
1647 /* Try to flush the object off the GPU without holding the lock.
1648 * We will repeat the flush holding the lock in the normal manner
1649 * to catch cases where we are gazumped.
1651 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1652 to_rps_client(file
),
1657 if (read_domains
& I915_GEM_DOMAIN_GTT
)
1658 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1660 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1662 if (write_domain
!= 0)
1663 intel_fb_obj_invalidate(obj
,
1664 write_domain
== I915_GEM_DOMAIN_GTT
?
1665 ORIGIN_GTT
: ORIGIN_CPU
);
1668 drm_gem_object_unreference(&obj
->base
);
1670 mutex_unlock(&dev
->struct_mutex
);
1675 * Called when user space has done writes to this buffer
1678 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1679 struct drm_file
*file
)
1681 struct drm_i915_gem_sw_finish
*args
= data
;
1682 struct drm_i915_gem_object
*obj
;
1685 ret
= i915_mutex_lock_interruptible(dev
);
1689 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1690 if (&obj
->base
== NULL
) {
1695 /* Pinned buffers may be scanout, so flush the cache */
1696 if (obj
->pin_display
)
1697 i915_gem_object_flush_cpu_write_domain(obj
);
1699 drm_gem_object_unreference(&obj
->base
);
1701 mutex_unlock(&dev
->struct_mutex
);
1706 * Maps the contents of an object, returning the address it is mapped
1709 * While the mapping holds a reference on the contents of the object, it doesn't
1710 * imply a ref on the object itself.
1714 * DRM driver writers who look a this function as an example for how to do GEM
1715 * mmap support, please don't implement mmap support like here. The modern way
1716 * to implement DRM mmap support is with an mmap offset ioctl (like
1717 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1718 * That way debug tooling like valgrind will understand what's going on, hiding
1719 * the mmap call in a driver private ioctl will break that. The i915 driver only
1720 * does cpu mmaps this way because we didn't know better.
1723 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1724 struct drm_file
*file
)
1726 struct drm_i915_gem_mmap
*args
= data
;
1727 struct drm_gem_object
*obj
;
1730 if (args
->flags
& ~(I915_MMAP_WC
))
1733 if (args
->flags
& I915_MMAP_WC
&& !cpu_has_pat
)
1736 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1740 /* prime objects have no backing filp to GEM mmap
1744 drm_gem_object_unreference_unlocked(obj
);
1748 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1749 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1751 if (args
->flags
& I915_MMAP_WC
) {
1752 struct mm_struct
*mm
= current
->mm
;
1753 struct vm_area_struct
*vma
;
1755 down_write(&mm
->mmap_sem
);
1756 vma
= find_vma(mm
, addr
);
1759 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1762 up_write(&mm
->mmap_sem
);
1764 drm_gem_object_unreference_unlocked(obj
);
1765 if (IS_ERR((void *)addr
))
1768 args
->addr_ptr
= (uint64_t) addr
;
1774 * i915_gem_fault - fault a page into the GTT
1775 * @vma: VMA in question
1778 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1779 * from userspace. The fault handler takes care of binding the object to
1780 * the GTT (if needed), allocating and programming a fence register (again,
1781 * only if needed based on whether the old reg is still valid or the object
1782 * is tiled) and inserting a new PTE into the faulting process.
1784 * Note that the faulting process may involve evicting existing objects
1785 * from the GTT and/or fence registers to make room. So performance may
1786 * suffer if the GTT working set is large or there are few fence registers
1789 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1791 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1792 struct drm_device
*dev
= obj
->base
.dev
;
1793 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1794 struct i915_ggtt_view view
= i915_ggtt_view_normal
;
1795 pgoff_t page_offset
;
1798 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1800 intel_runtime_pm_get(dev_priv
);
1802 /* We don't use vmf->pgoff since that has the fake offset */
1803 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1806 ret
= i915_mutex_lock_interruptible(dev
);
1810 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1812 /* Try to flush the object off the GPU first without holding the lock.
1813 * Upon reacquiring the lock, we will perform our sanity checks and then
1814 * repeat the flush holding the lock in the normal manner to catch cases
1815 * where we are gazumped.
1817 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
1821 /* Access to snoopable pages through the GTT is incoherent. */
1822 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1827 /* Use a partial view if the object is bigger than the aperture. */
1828 if (obj
->base
.size
>= dev_priv
->gtt
.mappable_end
&&
1829 obj
->tiling_mode
== I915_TILING_NONE
) {
1830 static const unsigned int chunk_size
= 256; // 1 MiB
1832 memset(&view
, 0, sizeof(view
));
1833 view
.type
= I915_GGTT_VIEW_PARTIAL
;
1834 view
.params
.partial
.offset
= rounddown(page_offset
, chunk_size
);
1835 view
.params
.partial
.size
=
1838 (vma
->vm_end
- vma
->vm_start
)/PAGE_SIZE
-
1839 view
.params
.partial
.offset
);
1842 /* Now pin it into the GTT if needed */
1843 ret
= i915_gem_object_ggtt_pin(obj
, &view
, 0, PIN_MAPPABLE
);
1847 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1851 ret
= i915_gem_object_get_fence(obj
);
1855 /* Finally, remap it using the new GTT offset */
1856 pfn
= dev_priv
->gtt
.mappable_base
+
1857 i915_gem_obj_ggtt_offset_view(obj
, &view
);
1860 if (unlikely(view
.type
== I915_GGTT_VIEW_PARTIAL
)) {
1861 /* Overriding existing pages in partial view does not cause
1862 * us any trouble as TLBs are still valid because the fault
1863 * is due to userspace losing part of the mapping or never
1864 * having accessed it before (at this partials' range).
1866 unsigned long base
= vma
->vm_start
+
1867 (view
.params
.partial
.offset
<< PAGE_SHIFT
);
1870 for (i
= 0; i
< view
.params
.partial
.size
; i
++) {
1871 ret
= vm_insert_pfn(vma
, base
+ i
* PAGE_SIZE
, pfn
+ i
);
1876 obj
->fault_mappable
= true;
1878 if (!obj
->fault_mappable
) {
1879 unsigned long size
= min_t(unsigned long,
1880 vma
->vm_end
- vma
->vm_start
,
1884 for (i
= 0; i
< size
>> PAGE_SHIFT
; i
++) {
1885 ret
= vm_insert_pfn(vma
,
1886 (unsigned long)vma
->vm_start
+ i
* PAGE_SIZE
,
1892 obj
->fault_mappable
= true;
1894 ret
= vm_insert_pfn(vma
,
1895 (unsigned long)vmf
->virtual_address
,
1899 i915_gem_object_ggtt_unpin_view(obj
, &view
);
1901 mutex_unlock(&dev
->struct_mutex
);
1906 * We eat errors when the gpu is terminally wedged to avoid
1907 * userspace unduly crashing (gl has no provisions for mmaps to
1908 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1909 * and so needs to be reported.
1911 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1912 ret
= VM_FAULT_SIGBUS
;
1917 * EAGAIN means the gpu is hung and we'll wait for the error
1918 * handler to reset everything when re-faulting in
1919 * i915_mutex_lock_interruptible.
1926 * EBUSY is ok: this just means that another thread
1927 * already did the job.
1929 ret
= VM_FAULT_NOPAGE
;
1936 ret
= VM_FAULT_SIGBUS
;
1939 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1940 ret
= VM_FAULT_SIGBUS
;
1944 intel_runtime_pm_put(dev_priv
);
1949 * i915_gem_release_mmap - remove physical page mappings
1950 * @obj: obj in question
1952 * Preserve the reservation of the mmapping with the DRM core code, but
1953 * relinquish ownership of the pages back to the system.
1955 * It is vital that we remove the page mapping if we have mapped a tiled
1956 * object through the GTT and then lose the fence register due to
1957 * resource pressure. Similarly if the object has been moved out of the
1958 * aperture, than pages mapped into userspace must be revoked. Removing the
1959 * mapping will then trigger a page fault on the next user access, allowing
1960 * fixup by i915_gem_fault().
1963 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1965 if (!obj
->fault_mappable
)
1968 drm_vma_node_unmap(&obj
->base
.vma_node
,
1969 obj
->base
.dev
->anon_inode
->i_mapping
);
1970 obj
->fault_mappable
= false;
1974 i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
1976 struct drm_i915_gem_object
*obj
;
1978 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
1979 i915_gem_release_mmap(obj
);
1983 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1987 if (INTEL_INFO(dev
)->gen
>= 4 ||
1988 tiling_mode
== I915_TILING_NONE
)
1991 /* Previous chips need a power-of-two fence region when tiling */
1992 if (INTEL_INFO(dev
)->gen
== 3)
1993 gtt_size
= 1024*1024;
1995 gtt_size
= 512*1024;
1997 while (gtt_size
< size
)
2004 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
2005 * @obj: object to check
2007 * Return the required GTT alignment for an object, taking into account
2008 * potential fence register mapping.
2011 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2012 int tiling_mode
, bool fenced
)
2015 * Minimum alignment is 4k (GTT page size), but might be greater
2016 * if a fence register is needed for the object.
2018 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
2019 tiling_mode
== I915_TILING_NONE
)
2023 * Previous chips need to be aligned to the size of the smallest
2024 * fence register that can contain the object.
2026 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
2029 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
2031 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2034 if (drm_vma_node_has_offset(&obj
->base
.vma_node
))
2037 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
2039 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2043 /* Badly fragmented mmap space? The only way we can recover
2044 * space is by destroying unwanted objects. We can't randomly release
2045 * mmap_offsets as userspace expects them to be persistent for the
2046 * lifetime of the objects. The closest we can is to release the
2047 * offsets on purgeable objects by truncating it and marking it purged,
2048 * which prevents userspace from ever using that object again.
2050 i915_gem_shrink(dev_priv
,
2051 obj
->base
.size
>> PAGE_SHIFT
,
2053 I915_SHRINK_UNBOUND
|
2054 I915_SHRINK_PURGEABLE
);
2055 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2059 i915_gem_shrink_all(dev_priv
);
2060 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2062 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
2067 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
2069 drm_gem_free_mmap_offset(&obj
->base
);
2073 i915_gem_mmap_gtt(struct drm_file
*file
,
2074 struct drm_device
*dev
,
2078 struct drm_i915_gem_object
*obj
;
2081 ret
= i915_mutex_lock_interruptible(dev
);
2085 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
2086 if (&obj
->base
== NULL
) {
2091 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2092 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2097 ret
= i915_gem_object_create_mmap_offset(obj
);
2101 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
2104 drm_gem_object_unreference(&obj
->base
);
2106 mutex_unlock(&dev
->struct_mutex
);
2111 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2113 * @data: GTT mapping ioctl data
2114 * @file: GEM object info
2116 * Simply returns the fake offset to userspace so it can mmap it.
2117 * The mmap call will end up in drm_gem_mmap(), which will set things
2118 * up so we can get faults in the handler above.
2120 * The fault handler will take care of binding the object into the GTT
2121 * (since it may have been evicted to make room for something), allocating
2122 * a fence register, and mapping the appropriate aperture address into
2126 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2127 struct drm_file
*file
)
2129 struct drm_i915_gem_mmap_gtt
*args
= data
;
2131 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
2134 /* Immediately discard the backing storage */
2136 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
2138 i915_gem_object_free_mmap_offset(obj
);
2140 if (obj
->base
.filp
== NULL
)
2143 /* Our goal here is to return as much of the memory as
2144 * is possible back to the system as we are called from OOM.
2145 * To do this we must instruct the shmfs to drop all of its
2146 * backing pages, *now*.
2148 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
2149 obj
->madv
= __I915_MADV_PURGED
;
2152 /* Try to discard unwanted pages */
2154 i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
2156 struct address_space
*mapping
;
2158 switch (obj
->madv
) {
2159 case I915_MADV_DONTNEED
:
2160 i915_gem_object_truncate(obj
);
2161 case __I915_MADV_PURGED
:
2165 if (obj
->base
.filp
== NULL
)
2168 mapping
= file_inode(obj
->base
.filp
)->i_mapping
,
2169 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
2173 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
2175 struct sg_page_iter sg_iter
;
2178 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
2180 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
2182 /* In the event of a disaster, abandon all caches and
2183 * hope for the best.
2185 WARN_ON(ret
!= -EIO
);
2186 i915_gem_clflush_object(obj
, true);
2187 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2190 i915_gem_gtt_finish_object(obj
);
2192 if (i915_gem_object_needs_bit17_swizzle(obj
))
2193 i915_gem_object_save_bit_17_swizzle(obj
);
2195 if (obj
->madv
== I915_MADV_DONTNEED
)
2198 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
2199 struct page
*page
= sg_page_iter_page(&sg_iter
);
2202 set_page_dirty(page
);
2204 if (obj
->madv
== I915_MADV_WILLNEED
)
2205 mark_page_accessed(page
);
2207 page_cache_release(page
);
2211 sg_free_table(obj
->pages
);
2216 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
2218 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2220 if (obj
->pages
== NULL
)
2223 if (obj
->pages_pin_count
)
2226 BUG_ON(i915_gem_obj_bound_any(obj
));
2228 /* ->put_pages might need to allocate memory for the bit17 swizzle
2229 * array, hence protect them from being reaped by removing them from gtt
2231 list_del(&obj
->global_list
);
2233 ops
->put_pages(obj
);
2236 i915_gem_object_invalidate(obj
);
2242 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2244 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2246 struct address_space
*mapping
;
2247 struct sg_table
*st
;
2248 struct scatterlist
*sg
;
2249 struct sg_page_iter sg_iter
;
2251 unsigned long last_pfn
= 0; /* suppress gcc warning */
2255 /* Assert that the object is not currently in any GPU domain. As it
2256 * wasn't in the GTT, there shouldn't be any way it could have been in
2259 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2260 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2262 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2266 page_count
= obj
->base
.size
/ PAGE_SIZE
;
2267 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2272 /* Get the list of pages out of our struct file. They'll be pinned
2273 * at this point until we release them.
2275 * Fail silently without starting the shrinker
2277 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
2278 gfp
= mapping_gfp_constraint(mapping
, ~(__GFP_IO
| __GFP_RECLAIM
));
2279 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
;
2282 for (i
= 0; i
< page_count
; i
++) {
2283 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2285 i915_gem_shrink(dev_priv
,
2288 I915_SHRINK_UNBOUND
|
2289 I915_SHRINK_PURGEABLE
);
2290 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2293 /* We've tried hard to allocate the memory by reaping
2294 * our own buffer, now let the real VM do its job and
2295 * go down in flames if truly OOM.
2297 i915_gem_shrink_all(dev_priv
);
2298 page
= shmem_read_mapping_page(mapping
, i
);
2300 ret
= PTR_ERR(page
);
2304 #ifdef CONFIG_SWIOTLB
2305 if (swiotlb_nr_tbl()) {
2307 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2312 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
2316 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2318 sg
->length
+= PAGE_SIZE
;
2320 last_pfn
= page_to_pfn(page
);
2322 /* Check that the i965g/gm workaround works. */
2323 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2325 #ifdef CONFIG_SWIOTLB
2326 if (!swiotlb_nr_tbl())
2331 ret
= i915_gem_gtt_prepare_object(obj
);
2335 if (i915_gem_object_needs_bit17_swizzle(obj
))
2336 i915_gem_object_do_bit_17_swizzle(obj
);
2338 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
2339 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2340 i915_gem_object_pin_pages(obj
);
2346 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
2347 page_cache_release(sg_page_iter_page(&sg_iter
));
2351 /* shmemfs first checks if there is enough memory to allocate the page
2352 * and reports ENOSPC should there be insufficient, along with the usual
2353 * ENOMEM for a genuine allocation failure.
2355 * We use ENOSPC in our driver to mean that we have run out of aperture
2356 * space and so want to translate the error from shmemfs back to our
2357 * usual understanding of ENOMEM.
2365 /* Ensure that the associated pages are gathered from the backing storage
2366 * and pinned into our object. i915_gem_object_get_pages() may be called
2367 * multiple times before they are released by a single call to
2368 * i915_gem_object_put_pages() - once the pages are no longer referenced
2369 * either as a result of memory pressure (reaping pages under the shrinker)
2370 * or as the object is itself released.
2373 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2375 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2376 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2382 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2383 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2387 BUG_ON(obj
->pages_pin_count
);
2389 ret
= ops
->get_pages(obj
);
2393 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2395 obj
->get_page
.sg
= obj
->pages
->sgl
;
2396 obj
->get_page
.last
= 0;
2401 void i915_vma_move_to_active(struct i915_vma
*vma
,
2402 struct drm_i915_gem_request
*req
)
2404 struct drm_i915_gem_object
*obj
= vma
->obj
;
2405 struct intel_engine_cs
*ring
;
2407 ring
= i915_gem_request_get_ring(req
);
2409 /* Add a reference if we're newly entering the active list. */
2410 if (obj
->active
== 0)
2411 drm_gem_object_reference(&obj
->base
);
2412 obj
->active
|= intel_ring_flag(ring
);
2414 list_move_tail(&obj
->ring_list
[ring
->id
], &ring
->active_list
);
2415 i915_gem_request_assign(&obj
->last_read_req
[ring
->id
], req
);
2417 list_move_tail(&vma
->mm_list
, &vma
->vm
->active_list
);
2421 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
)
2423 RQ_BUG_ON(obj
->last_write_req
== NULL
);
2424 RQ_BUG_ON(!(obj
->active
& intel_ring_flag(obj
->last_write_req
->ring
)));
2426 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
2427 intel_fb_obj_flush(obj
, true, ORIGIN_CS
);
2431 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
)
2433 struct i915_vma
*vma
;
2435 RQ_BUG_ON(obj
->last_read_req
[ring
] == NULL
);
2436 RQ_BUG_ON(!(obj
->active
& (1 << ring
)));
2438 list_del_init(&obj
->ring_list
[ring
]);
2439 i915_gem_request_assign(&obj
->last_read_req
[ring
], NULL
);
2441 if (obj
->last_write_req
&& obj
->last_write_req
->ring
->id
== ring
)
2442 i915_gem_object_retire__write(obj
);
2444 obj
->active
&= ~(1 << ring
);
2448 /* Bump our place on the bound list to keep it roughly in LRU order
2449 * so that we don't steal from recently used but inactive objects
2450 * (unless we are forced to ofc!)
2452 list_move_tail(&obj
->global_list
,
2453 &to_i915(obj
->base
.dev
)->mm
.bound_list
);
2455 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
2456 if (!list_empty(&vma
->mm_list
))
2457 list_move_tail(&vma
->mm_list
, &vma
->vm
->inactive_list
);
2460 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
2461 drm_gem_object_unreference(&obj
->base
);
2465 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
2467 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2468 struct intel_engine_cs
*ring
;
2471 /* Carefully retire all requests without writing to the rings */
2472 for_each_ring(ring
, dev_priv
, i
) {
2473 ret
= intel_ring_idle(ring
);
2477 i915_gem_retire_requests(dev
);
2479 /* Finally reset hw state */
2480 for_each_ring(ring
, dev_priv
, i
) {
2481 intel_ring_init_seqno(ring
, seqno
);
2483 for (j
= 0; j
< ARRAY_SIZE(ring
->semaphore
.sync_seqno
); j
++)
2484 ring
->semaphore
.sync_seqno
[j
] = 0;
2490 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2492 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2498 /* HWS page needs to be set less than what we
2499 * will inject to ring
2501 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
2505 /* Carefully set the last_seqno value so that wrap
2506 * detection still works
2508 dev_priv
->next_seqno
= seqno
;
2509 dev_priv
->last_seqno
= seqno
- 1;
2510 if (dev_priv
->last_seqno
== 0)
2511 dev_priv
->last_seqno
--;
2517 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
2519 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2521 /* reserve 0 for non-seqno */
2522 if (dev_priv
->next_seqno
== 0) {
2523 int ret
= i915_gem_init_seqno(dev
, 0);
2527 dev_priv
->next_seqno
= 1;
2530 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2535 * NB: This function is not allowed to fail. Doing so would mean the the
2536 * request is not being tracked for completion but the work itself is
2537 * going to happen on the hardware. This would be a Bad Thing(tm).
2539 void __i915_add_request(struct drm_i915_gem_request
*request
,
2540 struct drm_i915_gem_object
*obj
,
2543 struct intel_engine_cs
*ring
;
2544 struct drm_i915_private
*dev_priv
;
2545 struct intel_ringbuffer
*ringbuf
;
2549 if (WARN_ON(request
== NULL
))
2552 ring
= request
->ring
;
2553 dev_priv
= ring
->dev
->dev_private
;
2554 ringbuf
= request
->ringbuf
;
2557 * To ensure that this call will not fail, space for its emissions
2558 * should already have been reserved in the ring buffer. Let the ring
2559 * know that it is time to use that space up.
2561 intel_ring_reserved_space_use(ringbuf
);
2563 request_start
= intel_ring_get_tail(ringbuf
);
2565 * Emit any outstanding flushes - execbuf can fail to emit the flush
2566 * after having emitted the batchbuffer command. Hence we need to fix
2567 * things up similar to emitting the lazy request. The difference here
2568 * is that the flush _must_ happen before the next request, no matter
2572 if (i915
.enable_execlists
)
2573 ret
= logical_ring_flush_all_caches(request
);
2575 ret
= intel_ring_flush_all_caches(request
);
2576 /* Not allowed to fail! */
2577 WARN(ret
, "*_ring_flush_all_caches failed: %d!\n", ret
);
2580 /* Record the position of the start of the request so that
2581 * should we detect the updated seqno part-way through the
2582 * GPU processing the request, we never over-estimate the
2583 * position of the head.
2585 request
->postfix
= intel_ring_get_tail(ringbuf
);
2587 if (i915
.enable_execlists
)
2588 ret
= ring
->emit_request(request
);
2590 ret
= ring
->add_request(request
);
2592 request
->tail
= intel_ring_get_tail(ringbuf
);
2594 /* Not allowed to fail! */
2595 WARN(ret
, "emit|add_request failed: %d!\n", ret
);
2597 request
->head
= request_start
;
2599 /* Whilst this request exists, batch_obj will be on the
2600 * active_list, and so will hold the active reference. Only when this
2601 * request is retired will the the batch_obj be moved onto the
2602 * inactive_list and lose its active reference. Hence we do not need
2603 * to explicitly hold another reference here.
2605 request
->batch_obj
= obj
;
2607 request
->emitted_jiffies
= jiffies
;
2608 request
->previous_seqno
= ring
->last_submitted_seqno
;
2609 ring
->last_submitted_seqno
= request
->seqno
;
2610 list_add_tail(&request
->list
, &ring
->request_list
);
2612 trace_i915_gem_request_add(request
);
2614 i915_queue_hangcheck(ring
->dev
);
2616 queue_delayed_work(dev_priv
->wq
,
2617 &dev_priv
->mm
.retire_work
,
2618 round_jiffies_up_relative(HZ
));
2619 intel_mark_busy(dev_priv
->dev
);
2621 /* Sanity check that the reserved size was large enough. */
2622 intel_ring_reserved_space_end(ringbuf
);
2625 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2626 const struct intel_context
*ctx
)
2628 unsigned long elapsed
;
2630 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2632 if (ctx
->hang_stats
.banned
)
2635 if (ctx
->hang_stats
.ban_period_seconds
&&
2636 elapsed
<= ctx
->hang_stats
.ban_period_seconds
) {
2637 if (!i915_gem_context_is_default(ctx
)) {
2638 DRM_DEBUG("context hanging too fast, banning!\n");
2640 } else if (i915_stop_ring_allow_ban(dev_priv
)) {
2641 if (i915_stop_ring_allow_warn(dev_priv
))
2642 DRM_ERROR("gpu hanging too fast, banning!\n");
2650 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2651 struct intel_context
*ctx
,
2654 struct i915_ctx_hang_stats
*hs
;
2659 hs
= &ctx
->hang_stats
;
2662 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2664 hs
->guilty_ts
= get_seconds();
2666 hs
->batch_pending
++;
2670 void i915_gem_request_free(struct kref
*req_ref
)
2672 struct drm_i915_gem_request
*req
= container_of(req_ref
,
2674 struct intel_context
*ctx
= req
->ctx
;
2677 i915_gem_request_remove_from_client(req
);
2680 if (i915
.enable_execlists
) {
2681 if (ctx
!= req
->ring
->default_context
)
2682 intel_lr_context_unpin(req
);
2685 i915_gem_context_unreference(ctx
);
2688 kmem_cache_free(req
->i915
->requests
, req
);
2691 int i915_gem_request_alloc(struct intel_engine_cs
*ring
,
2692 struct intel_context
*ctx
,
2693 struct drm_i915_gem_request
**req_out
)
2695 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
2696 struct drm_i915_gem_request
*req
;
2704 req
= kmem_cache_zalloc(dev_priv
->requests
, GFP_KERNEL
);
2708 ret
= i915_gem_get_seqno(ring
->dev
, &req
->seqno
);
2712 kref_init(&req
->ref
);
2713 req
->i915
= dev_priv
;
2716 i915_gem_context_reference(req
->ctx
);
2718 if (i915
.enable_execlists
)
2719 ret
= intel_logical_ring_alloc_request_extras(req
);
2721 ret
= intel_ring_alloc_request_extras(req
);
2723 i915_gem_context_unreference(req
->ctx
);
2728 * Reserve space in the ring buffer for all the commands required to
2729 * eventually emit this request. This is to guarantee that the
2730 * i915_add_request() call can't fail. Note that the reserve may need
2731 * to be redone if the request is not actually submitted straight
2732 * away, e.g. because a GPU scheduler has deferred it.
2734 if (i915
.enable_execlists
)
2735 ret
= intel_logical_ring_reserve_space(req
);
2737 ret
= intel_ring_reserve_space(req
);
2740 * At this point, the request is fully allocated even if not
2741 * fully prepared. Thus it can be cleaned up using the proper
2744 i915_gem_request_cancel(req
);
2752 kmem_cache_free(dev_priv
->requests
, req
);
2756 void i915_gem_request_cancel(struct drm_i915_gem_request
*req
)
2758 intel_ring_reserved_space_cancel(req
->ringbuf
);
2760 i915_gem_request_unreference(req
);
2763 struct drm_i915_gem_request
*
2764 i915_gem_find_active_request(struct intel_engine_cs
*ring
)
2766 struct drm_i915_gem_request
*request
;
2768 list_for_each_entry(request
, &ring
->request_list
, list
) {
2769 if (i915_gem_request_completed(request
, false))
2778 static void i915_gem_reset_ring_status(struct drm_i915_private
*dev_priv
,
2779 struct intel_engine_cs
*ring
)
2781 struct drm_i915_gem_request
*request
;
2784 request
= i915_gem_find_active_request(ring
);
2786 if (request
== NULL
)
2789 ring_hung
= ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
2791 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
2793 list_for_each_entry_continue(request
, &ring
->request_list
, list
)
2794 i915_set_reset_status(dev_priv
, request
->ctx
, false);
2797 static void i915_gem_reset_ring_cleanup(struct drm_i915_private
*dev_priv
,
2798 struct intel_engine_cs
*ring
)
2800 struct intel_ringbuffer
*buffer
;
2802 while (!list_empty(&ring
->active_list
)) {
2803 struct drm_i915_gem_object
*obj
;
2805 obj
= list_first_entry(&ring
->active_list
,
2806 struct drm_i915_gem_object
,
2807 ring_list
[ring
->id
]);
2809 i915_gem_object_retire__read(obj
, ring
->id
);
2813 * Clear the execlists queue up before freeing the requests, as those
2814 * are the ones that keep the context and ringbuffer backing objects
2818 if (i915
.enable_execlists
) {
2819 spin_lock_irq(&ring
->execlist_lock
);
2821 /* list_splice_tail_init checks for empty lists */
2822 list_splice_tail_init(&ring
->execlist_queue
,
2823 &ring
->execlist_retired_req_list
);
2825 spin_unlock_irq(&ring
->execlist_lock
);
2826 intel_execlists_retire_requests(ring
);
2830 * We must free the requests after all the corresponding objects have
2831 * been moved off active lists. Which is the same order as the normal
2832 * retire_requests function does. This is important if object hold
2833 * implicit references on things like e.g. ppgtt address spaces through
2836 while (!list_empty(&ring
->request_list
)) {
2837 struct drm_i915_gem_request
*request
;
2839 request
= list_first_entry(&ring
->request_list
,
2840 struct drm_i915_gem_request
,
2843 i915_gem_request_retire(request
);
2846 /* Having flushed all requests from all queues, we know that all
2847 * ringbuffers must now be empty. However, since we do not reclaim
2848 * all space when retiring the request (to prevent HEADs colliding
2849 * with rapid ringbuffer wraparound) the amount of available space
2850 * upon reset is less than when we start. Do one more pass over
2851 * all the ringbuffers to reset last_retired_head.
2853 list_for_each_entry(buffer
, &ring
->buffers
, link
) {
2854 buffer
->last_retired_head
= buffer
->tail
;
2855 intel_ring_update_space(buffer
);
2859 void i915_gem_reset(struct drm_device
*dev
)
2861 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2862 struct intel_engine_cs
*ring
;
2866 * Before we free the objects from the requests, we need to inspect
2867 * them for finding the guilty party. As the requests only borrow
2868 * their reference to the objects, the inspection must be done first.
2870 for_each_ring(ring
, dev_priv
, i
)
2871 i915_gem_reset_ring_status(dev_priv
, ring
);
2873 for_each_ring(ring
, dev_priv
, i
)
2874 i915_gem_reset_ring_cleanup(dev_priv
, ring
);
2876 i915_gem_context_reset(dev
);
2878 i915_gem_restore_fences(dev
);
2880 WARN_ON(i915_verify_lists(dev
));
2884 * This function clears the request list as sequence numbers are passed.
2887 i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
)
2889 WARN_ON(i915_verify_lists(ring
->dev
));
2891 /* Retire requests first as we use it above for the early return.
2892 * If we retire requests last, we may use a later seqno and so clear
2893 * the requests lists without clearing the active list, leading to
2896 while (!list_empty(&ring
->request_list
)) {
2897 struct drm_i915_gem_request
*request
;
2899 request
= list_first_entry(&ring
->request_list
,
2900 struct drm_i915_gem_request
,
2903 if (!i915_gem_request_completed(request
, true))
2906 i915_gem_request_retire(request
);
2909 /* Move any buffers on the active list that are no longer referenced
2910 * by the ringbuffer to the flushing/inactive lists as appropriate,
2911 * before we free the context associated with the requests.
2913 while (!list_empty(&ring
->active_list
)) {
2914 struct drm_i915_gem_object
*obj
;
2916 obj
= list_first_entry(&ring
->active_list
,
2917 struct drm_i915_gem_object
,
2918 ring_list
[ring
->id
]);
2920 if (!list_empty(&obj
->last_read_req
[ring
->id
]->list
))
2923 i915_gem_object_retire__read(obj
, ring
->id
);
2926 if (unlikely(ring
->trace_irq_req
&&
2927 i915_gem_request_completed(ring
->trace_irq_req
, true))) {
2928 ring
->irq_put(ring
);
2929 i915_gem_request_assign(&ring
->trace_irq_req
, NULL
);
2932 WARN_ON(i915_verify_lists(ring
->dev
));
2936 i915_gem_retire_requests(struct drm_device
*dev
)
2938 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2939 struct intel_engine_cs
*ring
;
2943 for_each_ring(ring
, dev_priv
, i
) {
2944 i915_gem_retire_requests_ring(ring
);
2945 idle
&= list_empty(&ring
->request_list
);
2946 if (i915
.enable_execlists
) {
2947 unsigned long flags
;
2949 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
2950 idle
&= list_empty(&ring
->execlist_queue
);
2951 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
2953 intel_execlists_retire_requests(ring
);
2958 mod_delayed_work(dev_priv
->wq
,
2959 &dev_priv
->mm
.idle_work
,
2960 msecs_to_jiffies(100));
2966 i915_gem_retire_work_handler(struct work_struct
*work
)
2968 struct drm_i915_private
*dev_priv
=
2969 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
2970 struct drm_device
*dev
= dev_priv
->dev
;
2973 /* Come back later if the device is busy... */
2975 if (mutex_trylock(&dev
->struct_mutex
)) {
2976 idle
= i915_gem_retire_requests(dev
);
2977 mutex_unlock(&dev
->struct_mutex
);
2980 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2981 round_jiffies_up_relative(HZ
));
2985 i915_gem_idle_work_handler(struct work_struct
*work
)
2987 struct drm_i915_private
*dev_priv
=
2988 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
2989 struct drm_device
*dev
= dev_priv
->dev
;
2990 struct intel_engine_cs
*ring
;
2993 for_each_ring(ring
, dev_priv
, i
)
2994 if (!list_empty(&ring
->request_list
))
2997 /* we probably should sync with hangcheck here, using cancel_work_sync.
2998 * Also locking seems to be fubar here, ring->request_list is protected
2999 * by dev->struct_mutex. */
3001 intel_mark_idle(dev
);
3003 if (mutex_trylock(&dev
->struct_mutex
)) {
3004 struct intel_engine_cs
*ring
;
3007 for_each_ring(ring
, dev_priv
, i
)
3008 i915_gem_batch_pool_fini(&ring
->batch_pool
);
3010 mutex_unlock(&dev
->struct_mutex
);
3015 * Ensures that an object will eventually get non-busy by flushing any required
3016 * write domains, emitting any outstanding lazy request and retiring and
3017 * completed requests.
3020 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
3027 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
3028 struct drm_i915_gem_request
*req
;
3030 req
= obj
->last_read_req
[i
];
3034 if (list_empty(&req
->list
))
3037 if (i915_gem_request_completed(req
, true)) {
3038 __i915_gem_request_retire__upto(req
);
3040 i915_gem_object_retire__read(obj
, i
);
3048 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3049 * @DRM_IOCTL_ARGS: standard ioctl arguments
3051 * Returns 0 if successful, else an error is returned with the remaining time in
3052 * the timeout parameter.
3053 * -ETIME: object is still busy after timeout
3054 * -ERESTARTSYS: signal interrupted the wait
3055 * -ENONENT: object doesn't exist
3056 * Also possible, but rare:
3057 * -EAGAIN: GPU wedged
3059 * -ENODEV: Internal IRQ fail
3060 * -E?: The add request failed
3062 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3063 * non-zero timeout parameter the wait ioctl will wait for the given number of
3064 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3065 * without holding struct_mutex the object may become re-busied before this
3066 * function completes. A similar but shorter * race condition exists in the busy
3070 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
3072 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3073 struct drm_i915_gem_wait
*args
= data
;
3074 struct drm_i915_gem_object
*obj
;
3075 struct drm_i915_gem_request
*req
[I915_NUM_RINGS
];
3076 unsigned reset_counter
;
3080 if (args
->flags
!= 0)
3083 ret
= i915_mutex_lock_interruptible(dev
);
3087 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
3088 if (&obj
->base
== NULL
) {
3089 mutex_unlock(&dev
->struct_mutex
);
3093 /* Need to make sure the object gets inactive eventually. */
3094 ret
= i915_gem_object_flush_active(obj
);
3101 /* Do this after OLR check to make sure we make forward progress polling
3102 * on this IOCTL with a timeout == 0 (like busy ioctl)
3104 if (args
->timeout_ns
== 0) {
3109 drm_gem_object_unreference(&obj
->base
);
3110 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3112 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
3113 if (obj
->last_read_req
[i
] == NULL
)
3116 req
[n
++] = i915_gem_request_reference(obj
->last_read_req
[i
]);
3119 mutex_unlock(&dev
->struct_mutex
);
3121 for (i
= 0; i
< n
; i
++) {
3123 ret
= __i915_wait_request(req
[i
], reset_counter
, true,
3124 args
->timeout_ns
> 0 ? &args
->timeout_ns
: NULL
,
3125 to_rps_client(file
));
3126 i915_gem_request_unreference__unlocked(req
[i
]);
3131 drm_gem_object_unreference(&obj
->base
);
3132 mutex_unlock(&dev
->struct_mutex
);
3137 __i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3138 struct intel_engine_cs
*to
,
3139 struct drm_i915_gem_request
*from_req
,
3140 struct drm_i915_gem_request
**to_req
)
3142 struct intel_engine_cs
*from
;
3145 from
= i915_gem_request_get_ring(from_req
);
3149 if (i915_gem_request_completed(from_req
, true))
3152 if (!i915_semaphore_is_enabled(obj
->base
.dev
)) {
3153 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
3154 ret
= __i915_wait_request(from_req
,
3155 atomic_read(&i915
->gpu_error
.reset_counter
),
3156 i915
->mm
.interruptible
,
3158 &i915
->rps
.semaphores
);
3162 i915_gem_object_retire_request(obj
, from_req
);
3164 int idx
= intel_ring_sync_index(from
, to
);
3165 u32 seqno
= i915_gem_request_get_seqno(from_req
);
3169 if (seqno
<= from
->semaphore
.sync_seqno
[idx
])
3172 if (*to_req
== NULL
) {
3173 ret
= i915_gem_request_alloc(to
, to
->default_context
, to_req
);
3178 trace_i915_gem_ring_sync_to(*to_req
, from
, from_req
);
3179 ret
= to
->semaphore
.sync_to(*to_req
, from
, seqno
);
3183 /* We use last_read_req because sync_to()
3184 * might have just caused seqno wrap under
3187 from
->semaphore
.sync_seqno
[idx
] =
3188 i915_gem_request_get_seqno(obj
->last_read_req
[from
->id
]);
3195 * i915_gem_object_sync - sync an object to a ring.
3197 * @obj: object which may be in use on another ring.
3198 * @to: ring we wish to use the object on. May be NULL.
3199 * @to_req: request we wish to use the object for. See below.
3200 * This will be allocated and returned if a request is
3201 * required but not passed in.
3203 * This code is meant to abstract object synchronization with the GPU.
3204 * Calling with NULL implies synchronizing the object with the CPU
3205 * rather than a particular GPU ring. Conceptually we serialise writes
3206 * between engines inside the GPU. We only allow one engine to write
3207 * into a buffer at any time, but multiple readers. To ensure each has
3208 * a coherent view of memory, we must:
3210 * - If there is an outstanding write request to the object, the new
3211 * request must wait for it to complete (either CPU or in hw, requests
3212 * on the same ring will be naturally ordered).
3214 * - If we are a write request (pending_write_domain is set), the new
3215 * request must wait for outstanding read requests to complete.
3217 * For CPU synchronisation (NULL to) no request is required. For syncing with
3218 * rings to_req must be non-NULL. However, a request does not have to be
3219 * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
3220 * request will be allocated automatically and returned through *to_req. Note
3221 * that it is not guaranteed that commands will be emitted (because the system
3222 * might already be idle). Hence there is no need to create a request that
3223 * might never have any work submitted. Note further that if a request is
3224 * returned in *to_req, it is the responsibility of the caller to submit
3225 * that request (after potentially adding more work to it).
3227 * Returns 0 if successful, else propagates up the lower layer error.
3230 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3231 struct intel_engine_cs
*to
,
3232 struct drm_i915_gem_request
**to_req
)
3234 const bool readonly
= obj
->base
.pending_write_domain
== 0;
3235 struct drm_i915_gem_request
*req
[I915_NUM_RINGS
];
3242 return i915_gem_object_wait_rendering(obj
, readonly
);
3246 if (obj
->last_write_req
)
3247 req
[n
++] = obj
->last_write_req
;
3249 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
3250 if (obj
->last_read_req
[i
])
3251 req
[n
++] = obj
->last_read_req
[i
];
3253 for (i
= 0; i
< n
; i
++) {
3254 ret
= __i915_gem_object_sync(obj
, to
, req
[i
], to_req
);
3262 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
3264 u32 old_write_domain
, old_read_domains
;
3266 /* Force a pagefault for domain tracking on next user access */
3267 i915_gem_release_mmap(obj
);
3269 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3272 /* Wait for any direct GTT access to complete */
3275 old_read_domains
= obj
->base
.read_domains
;
3276 old_write_domain
= obj
->base
.write_domain
;
3278 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
3279 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
3281 trace_i915_gem_object_change_domain(obj
,
3286 static int __i915_vma_unbind(struct i915_vma
*vma
, bool wait
)
3288 struct drm_i915_gem_object
*obj
= vma
->obj
;
3289 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3292 if (list_empty(&vma
->vma_link
))
3295 if (!drm_mm_node_allocated(&vma
->node
)) {
3296 i915_gem_vma_destroy(vma
);
3303 BUG_ON(obj
->pages
== NULL
);
3306 ret
= i915_gem_object_wait_rendering(obj
, false);
3311 if (i915_is_ggtt(vma
->vm
) &&
3312 vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3313 i915_gem_object_finish_gtt(obj
);
3315 /* release the fence reg _after_ flushing */
3316 ret
= i915_gem_object_put_fence(obj
);
3321 trace_i915_vma_unbind(vma
);
3323 vma
->vm
->unbind_vma(vma
);
3326 list_del_init(&vma
->mm_list
);
3327 if (i915_is_ggtt(vma
->vm
)) {
3328 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3329 obj
->map_and_fenceable
= false;
3330 } else if (vma
->ggtt_view
.pages
) {
3331 sg_free_table(vma
->ggtt_view
.pages
);
3332 kfree(vma
->ggtt_view
.pages
);
3334 vma
->ggtt_view
.pages
= NULL
;
3337 drm_mm_remove_node(&vma
->node
);
3338 i915_gem_vma_destroy(vma
);
3340 /* Since the unbound list is global, only move to that list if
3341 * no more VMAs exist. */
3342 if (list_empty(&obj
->vma_list
))
3343 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
3345 /* And finally now the object is completely decoupled from this vma,
3346 * we can drop its hold on the backing storage and allow it to be
3347 * reaped by the shrinker.
3349 i915_gem_object_unpin_pages(obj
);
3354 int i915_vma_unbind(struct i915_vma
*vma
)
3356 return __i915_vma_unbind(vma
, true);
3359 int __i915_vma_unbind_no_wait(struct i915_vma
*vma
)
3361 return __i915_vma_unbind(vma
, false);
3364 int i915_gpu_idle(struct drm_device
*dev
)
3366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3367 struct intel_engine_cs
*ring
;
3370 /* Flush everything onto the inactive list. */
3371 for_each_ring(ring
, dev_priv
, i
) {
3372 if (!i915
.enable_execlists
) {
3373 struct drm_i915_gem_request
*req
;
3375 ret
= i915_gem_request_alloc(ring
, ring
->default_context
, &req
);
3379 ret
= i915_switch_context(req
);
3381 i915_gem_request_cancel(req
);
3385 i915_add_request_no_flush(req
);
3388 ret
= intel_ring_idle(ring
);
3393 WARN_ON(i915_verify_lists(dev
));
3397 static bool i915_gem_valid_gtt_space(struct i915_vma
*vma
,
3398 unsigned long cache_level
)
3400 struct drm_mm_node
*gtt_space
= &vma
->node
;
3401 struct drm_mm_node
*other
;
3404 * On some machines we have to be careful when putting differing types
3405 * of snoopable memory together to avoid the prefetcher crossing memory
3406 * domains and dying. During vm initialisation, we decide whether or not
3407 * these constraints apply and set the drm_mm.color_adjust
3410 if (vma
->vm
->mm
.color_adjust
== NULL
)
3413 if (!drm_mm_node_allocated(gtt_space
))
3416 if (list_empty(>t_space
->node_list
))
3419 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3420 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3423 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3424 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3431 * Finds free space in the GTT aperture and binds the object or a view of it
3434 static struct i915_vma
*
3435 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3436 struct i915_address_space
*vm
,
3437 const struct i915_ggtt_view
*ggtt_view
,
3441 struct drm_device
*dev
= obj
->base
.dev
;
3442 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3443 u32 fence_alignment
, unfenced_alignment
;
3444 u32 search_flag
, alloc_flag
;
3446 u64 size
, fence_size
;
3447 struct i915_vma
*vma
;
3450 if (i915_is_ggtt(vm
)) {
3453 if (WARN_ON(!ggtt_view
))
3454 return ERR_PTR(-EINVAL
);
3456 view_size
= i915_ggtt_view_size(obj
, ggtt_view
);
3458 fence_size
= i915_gem_get_gtt_size(dev
,
3461 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3465 unfenced_alignment
= i915_gem_get_gtt_alignment(dev
,
3469 size
= flags
& PIN_MAPPABLE
? fence_size
: view_size
;
3471 fence_size
= i915_gem_get_gtt_size(dev
,
3474 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3478 unfenced_alignment
=
3479 i915_gem_get_gtt_alignment(dev
,
3483 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3486 start
= flags
& PIN_OFFSET_BIAS
? flags
& PIN_OFFSET_MASK
: 0;
3488 if (flags
& PIN_MAPPABLE
)
3489 end
= min_t(u64
, end
, dev_priv
->gtt
.mappable_end
);
3490 if (flags
& PIN_ZONE_4G
)
3491 end
= min_t(u64
, end
, (1ULL << 32) - PAGE_SIZE
);
3494 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3496 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3497 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3498 ggtt_view
? ggtt_view
->type
: 0,
3500 return ERR_PTR(-EINVAL
);
3503 /* If binding the object/GGTT view requires more space than the entire
3504 * aperture has, reject it early before evicting everything in a vain
3505 * attempt to find space.
3508 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n",
3509 ggtt_view
? ggtt_view
->type
: 0,
3511 flags
& PIN_MAPPABLE
? "mappable" : "total",
3513 return ERR_PTR(-E2BIG
);
3516 ret
= i915_gem_object_get_pages(obj
);
3518 return ERR_PTR(ret
);
3520 i915_gem_object_pin_pages(obj
);
3522 vma
= ggtt_view
? i915_gem_obj_lookup_or_create_ggtt_vma(obj
, ggtt_view
) :
3523 i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3528 if (flags
& PIN_OFFSET_FIXED
) {
3529 uint64_t offset
= flags
& PIN_OFFSET_MASK
;
3531 if (offset
& (alignment
- 1) || offset
+ size
> end
) {
3535 vma
->node
.start
= offset
;
3536 vma
->node
.size
= size
;
3537 vma
->node
.color
= obj
->cache_level
;
3538 ret
= drm_mm_reserve_node(&vm
->mm
, &vma
->node
);
3540 ret
= i915_gem_evict_for_vma(vma
);
3542 ret
= drm_mm_reserve_node(&vm
->mm
, &vma
->node
);
3547 if (flags
& PIN_HIGH
) {
3548 search_flag
= DRM_MM_SEARCH_BELOW
;
3549 alloc_flag
= DRM_MM_CREATE_TOP
;
3551 search_flag
= DRM_MM_SEARCH_DEFAULT
;
3552 alloc_flag
= DRM_MM_CREATE_DEFAULT
;
3556 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3563 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3573 if (WARN_ON(!i915_gem_valid_gtt_space(vma
, obj
->cache_level
))) {
3575 goto err_remove_node
;
3578 trace_i915_vma_bind(vma
, flags
);
3579 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
3581 goto err_remove_node
;
3583 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3584 list_add_tail(&vma
->mm_list
, &vm
->inactive_list
);
3589 drm_mm_remove_node(&vma
->node
);
3591 i915_gem_vma_destroy(vma
);
3594 i915_gem_object_unpin_pages(obj
);
3599 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3602 /* If we don't have a page list set up, then we're not pinned
3603 * to GPU, and we can ignore the cache flush because it'll happen
3604 * again at bind time.
3606 if (obj
->pages
== NULL
)
3610 * Stolen memory is always coherent with the GPU as it is explicitly
3611 * marked as wc by the system, or the system is cache-coherent.
3613 if (obj
->stolen
|| obj
->phys_handle
)
3616 /* If the GPU is snooping the contents of the CPU cache,
3617 * we do not need to manually clear the CPU cache lines. However,
3618 * the caches are only snooped when the render cache is
3619 * flushed/invalidated. As we always have to emit invalidations
3620 * and flushes when moving into and out of the RENDER domain, correct
3621 * snooping behaviour occurs naturally as the result of our domain
3624 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
)) {
3625 obj
->cache_dirty
= true;
3629 trace_i915_gem_object_clflush(obj
);
3630 drm_clflush_sg(obj
->pages
);
3631 obj
->cache_dirty
= false;
3636 /** Flushes the GTT write domain for the object if it's dirty. */
3638 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3640 uint32_t old_write_domain
;
3642 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3645 /* No actual flushing is required for the GTT write domain. Writes
3646 * to it immediately go to main memory as far as we know, so there's
3647 * no chipset flush. It also doesn't land in render cache.
3649 * However, we do have to enforce the order so that all writes through
3650 * the GTT land before any writes to the device, such as updates to
3655 old_write_domain
= obj
->base
.write_domain
;
3656 obj
->base
.write_domain
= 0;
3658 intel_fb_obj_flush(obj
, false, ORIGIN_GTT
);
3660 trace_i915_gem_object_change_domain(obj
,
3661 obj
->base
.read_domains
,
3665 /** Flushes the CPU write domain for the object if it's dirty. */
3667 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3669 uint32_t old_write_domain
;
3671 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3674 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
3675 i915_gem_chipset_flush(obj
->base
.dev
);
3677 old_write_domain
= obj
->base
.write_domain
;
3678 obj
->base
.write_domain
= 0;
3680 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
3682 trace_i915_gem_object_change_domain(obj
,
3683 obj
->base
.read_domains
,
3688 * Moves a single object to the GTT read, and possibly write domain.
3690 * This function returns when the move is complete, including waiting on
3694 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3696 uint32_t old_write_domain
, old_read_domains
;
3697 struct i915_vma
*vma
;
3700 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3703 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3707 /* Flush and acquire obj->pages so that we are coherent through
3708 * direct access in memory with previous cached writes through
3709 * shmemfs and that our cache domain tracking remains valid.
3710 * For example, if the obj->filp was moved to swap without us
3711 * being notified and releasing the pages, we would mistakenly
3712 * continue to assume that the obj remained out of the CPU cached
3715 ret
= i915_gem_object_get_pages(obj
);
3719 i915_gem_object_flush_cpu_write_domain(obj
);
3721 /* Serialise direct access to this object with the barriers for
3722 * coherent writes from the GPU, by effectively invalidating the
3723 * GTT domain upon first access.
3725 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3728 old_write_domain
= obj
->base
.write_domain
;
3729 old_read_domains
= obj
->base
.read_domains
;
3731 /* It should now be out of any other write domains, and we can update
3732 * the domain values for our changes.
3734 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3735 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3737 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3738 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3742 trace_i915_gem_object_change_domain(obj
,
3746 /* And bump the LRU for this access */
3747 vma
= i915_gem_obj_to_ggtt(obj
);
3748 if (vma
&& drm_mm_node_allocated(&vma
->node
) && !obj
->active
)
3749 list_move_tail(&vma
->mm_list
,
3750 &to_i915(obj
->base
.dev
)->gtt
.base
.inactive_list
);
3756 * Changes the cache-level of an object across all VMA.
3758 * After this function returns, the object will be in the new cache-level
3759 * across all GTT and the contents of the backing storage will be coherent,
3760 * with respect to the new cache-level. In order to keep the backing storage
3761 * coherent for all users, we only allow a single cache level to be set
3762 * globally on the object and prevent it from being changed whilst the
3763 * hardware is reading from the object. That is if the object is currently
3764 * on the scanout it will be set to uncached (or equivalent display
3765 * cache coherency) and all non-MOCS GPU access will also be uncached so
3766 * that all direct access to the scanout remains coherent.
3768 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3769 enum i915_cache_level cache_level
)
3771 struct drm_device
*dev
= obj
->base
.dev
;
3772 struct i915_vma
*vma
, *next
;
3776 if (obj
->cache_level
== cache_level
)
3779 /* Inspect the list of currently bound VMA and unbind any that would
3780 * be invalid given the new cache-level. This is principally to
3781 * catch the issue of the CS prefetch crossing page boundaries and
3782 * reading an invalid PTE on older architectures.
3784 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
3785 if (!drm_mm_node_allocated(&vma
->node
))
3788 if (vma
->pin_count
) {
3789 DRM_DEBUG("can not change the cache level of pinned objects\n");
3793 if (!i915_gem_valid_gtt_space(vma
, cache_level
)) {
3794 ret
= i915_vma_unbind(vma
);
3801 /* We can reuse the existing drm_mm nodes but need to change the
3802 * cache-level on the PTE. We could simply unbind them all and
3803 * rebind with the correct cache-level on next use. However since
3804 * we already have a valid slot, dma mapping, pages etc, we may as
3805 * rewrite the PTE in the belief that doing so tramples upon less
3806 * state and so involves less work.
3809 /* Before we change the PTE, the GPU must not be accessing it.
3810 * If we wait upon the object, we know that all the bound
3811 * VMA are no longer active.
3813 ret
= i915_gem_object_wait_rendering(obj
, false);
3817 if (!HAS_LLC(dev
) && cache_level
!= I915_CACHE_NONE
) {
3818 /* Access to snoopable pages through the GTT is
3819 * incoherent and on some machines causes a hard
3820 * lockup. Relinquish the CPU mmaping to force
3821 * userspace to refault in the pages and we can
3822 * then double check if the GTT mapping is still
3823 * valid for that pointer access.
3825 i915_gem_release_mmap(obj
);
3827 /* As we no longer need a fence for GTT access,
3828 * we can relinquish it now (and so prevent having
3829 * to steal a fence from someone else on the next
3830 * fence request). Note GPU activity would have
3831 * dropped the fence as all snoopable access is
3832 * supposed to be linear.
3834 ret
= i915_gem_object_put_fence(obj
);
3838 /* We either have incoherent backing store and
3839 * so no GTT access or the architecture is fully
3840 * coherent. In such cases, existing GTT mmaps
3841 * ignore the cache bit in the PTE and we can
3842 * rewrite it without confusing the GPU or having
3843 * to force userspace to fault back in its mmaps.
3847 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
3848 if (!drm_mm_node_allocated(&vma
->node
))
3851 ret
= i915_vma_bind(vma
, cache_level
, PIN_UPDATE
);
3857 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3858 vma
->node
.color
= cache_level
;
3859 obj
->cache_level
= cache_level
;
3862 /* Flush the dirty CPU caches to the backing storage so that the
3863 * object is now coherent at its new cache level (with respect
3864 * to the access domain).
3866 if (obj
->cache_dirty
&&
3867 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
3868 cpu_write_needs_clflush(obj
)) {
3869 if (i915_gem_clflush_object(obj
, true))
3870 i915_gem_chipset_flush(obj
->base
.dev
);
3876 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3877 struct drm_file
*file
)
3879 struct drm_i915_gem_caching
*args
= data
;
3880 struct drm_i915_gem_object
*obj
;
3882 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3883 if (&obj
->base
== NULL
)
3886 switch (obj
->cache_level
) {
3887 case I915_CACHE_LLC
:
3888 case I915_CACHE_L3_LLC
:
3889 args
->caching
= I915_CACHING_CACHED
;
3893 args
->caching
= I915_CACHING_DISPLAY
;
3897 args
->caching
= I915_CACHING_NONE
;
3901 drm_gem_object_unreference_unlocked(&obj
->base
);
3905 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3906 struct drm_file
*file
)
3908 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3909 struct drm_i915_gem_caching
*args
= data
;
3910 struct drm_i915_gem_object
*obj
;
3911 enum i915_cache_level level
;
3914 switch (args
->caching
) {
3915 case I915_CACHING_NONE
:
3916 level
= I915_CACHE_NONE
;
3918 case I915_CACHING_CACHED
:
3920 * Due to a HW issue on BXT A stepping, GPU stores via a
3921 * snooped mapping may leave stale data in a corresponding CPU
3922 * cacheline, whereas normally such cachelines would get
3925 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
3928 level
= I915_CACHE_LLC
;
3930 case I915_CACHING_DISPLAY
:
3931 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
3937 intel_runtime_pm_get(dev_priv
);
3939 ret
= i915_mutex_lock_interruptible(dev
);
3943 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3944 if (&obj
->base
== NULL
) {
3949 ret
= i915_gem_object_set_cache_level(obj
, level
);
3951 drm_gem_object_unreference(&obj
->base
);
3953 mutex_unlock(&dev
->struct_mutex
);
3955 intel_runtime_pm_put(dev_priv
);
3961 * Prepare buffer for display plane (scanout, cursors, etc).
3962 * Can be called from an uninterruptible phase (modesetting) and allows
3963 * any flushes to be pipelined (for pageflips).
3966 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3968 const struct i915_ggtt_view
*view
)
3970 u32 old_read_domains
, old_write_domain
;
3973 /* Mark the pin_display early so that we account for the
3974 * display coherency whilst setting up the cache domains.
3978 /* The display engine is not coherent with the LLC cache on gen6. As
3979 * a result, we make sure that the pinning that is about to occur is
3980 * done with uncached PTEs. This is lowest common denominator for all
3983 * However for gen6+, we could do better by using the GFDT bit instead
3984 * of uncaching, which would allow us to flush all the LLC-cached data
3985 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3987 ret
= i915_gem_object_set_cache_level(obj
,
3988 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
3990 goto err_unpin_display
;
3992 /* As the user may map the buffer once pinned in the display plane
3993 * (e.g. libkms for the bootup splash), we have to ensure that we
3994 * always use map_and_fenceable for all scanout buffers.
3996 ret
= i915_gem_object_ggtt_pin(obj
, view
, alignment
,
3997 view
->type
== I915_GGTT_VIEW_NORMAL
?
4000 goto err_unpin_display
;
4002 i915_gem_object_flush_cpu_write_domain(obj
);
4004 old_write_domain
= obj
->base
.write_domain
;
4005 old_read_domains
= obj
->base
.read_domains
;
4007 /* It should now be out of any other write domains, and we can update
4008 * the domain values for our changes.
4010 obj
->base
.write_domain
= 0;
4011 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
4013 trace_i915_gem_object_change_domain(obj
,
4025 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
4026 const struct i915_ggtt_view
*view
)
4028 if (WARN_ON(obj
->pin_display
== 0))
4031 i915_gem_object_ggtt_unpin_view(obj
, view
);
4037 * Moves a single object to the CPU read, and possibly write domain.
4039 * This function returns when the move is complete, including waiting on
4043 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
4045 uint32_t old_write_domain
, old_read_domains
;
4048 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
4051 ret
= i915_gem_object_wait_rendering(obj
, !write
);
4055 i915_gem_object_flush_gtt_write_domain(obj
);
4057 old_write_domain
= obj
->base
.write_domain
;
4058 old_read_domains
= obj
->base
.read_domains
;
4060 /* Flush the CPU cache if it's still invalid. */
4061 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
4062 i915_gem_clflush_object(obj
, false);
4064 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
4067 /* It should now be out of any other write domains, and we can update
4068 * the domain values for our changes.
4070 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
4072 /* If we're writing through the CPU, then the GPU read domains will
4073 * need to be invalidated at next use.
4076 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4077 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4080 trace_i915_gem_object_change_domain(obj
,
4087 /* Throttle our rendering by waiting until the ring has completed our requests
4088 * emitted over 20 msec ago.
4090 * Note that if we were to use the current jiffies each time around the loop,
4091 * we wouldn't escape the function with any frames outstanding if the time to
4092 * render a frame was over 20ms.
4094 * This should get us reasonable parallelism between CPU and GPU but also
4095 * relatively low latency when blocking on a particular request to finish.
4098 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
4100 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4101 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4102 unsigned long recent_enough
= jiffies
- DRM_I915_THROTTLE_JIFFIES
;
4103 struct drm_i915_gem_request
*request
, *target
= NULL
;
4104 unsigned reset_counter
;
4107 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
4111 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
4115 spin_lock(&file_priv
->mm
.lock
);
4116 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
4117 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
4121 * Note that the request might not have been submitted yet.
4122 * In which case emitted_jiffies will be zero.
4124 if (!request
->emitted_jiffies
)
4129 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
4131 i915_gem_request_reference(target
);
4132 spin_unlock(&file_priv
->mm
.lock
);
4137 ret
= __i915_wait_request(target
, reset_counter
, true, NULL
, NULL
);
4139 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
4141 i915_gem_request_unreference__unlocked(target
);
4147 i915_vma_misplaced(struct i915_vma
*vma
, uint32_t alignment
, uint64_t flags
)
4149 struct drm_i915_gem_object
*obj
= vma
->obj
;
4152 vma
->node
.start
& (alignment
- 1))
4155 if (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)
4158 if (flags
& PIN_OFFSET_BIAS
&&
4159 vma
->node
.start
< (flags
& PIN_OFFSET_MASK
))
4162 if (flags
& PIN_OFFSET_FIXED
&&
4163 vma
->node
.start
!= (flags
& PIN_OFFSET_MASK
))
4169 void __i915_vma_set_map_and_fenceable(struct i915_vma
*vma
)
4171 struct drm_i915_gem_object
*obj
= vma
->obj
;
4172 bool mappable
, fenceable
;
4173 u32 fence_size
, fence_alignment
;
4175 fence_size
= i915_gem_get_gtt_size(obj
->base
.dev
,
4178 fence_alignment
= i915_gem_get_gtt_alignment(obj
->base
.dev
,
4183 fenceable
= (vma
->node
.size
== fence_size
&&
4184 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
4186 mappable
= (vma
->node
.start
+ fence_size
<=
4187 to_i915(obj
->base
.dev
)->gtt
.mappable_end
);
4189 obj
->map_and_fenceable
= mappable
&& fenceable
;
4193 i915_gem_object_do_pin(struct drm_i915_gem_object
*obj
,
4194 struct i915_address_space
*vm
,
4195 const struct i915_ggtt_view
*ggtt_view
,
4199 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4200 struct i915_vma
*vma
;
4204 if (WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
))
4207 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
4210 if (WARN_ON((flags
& (PIN_MAPPABLE
| PIN_GLOBAL
)) == PIN_MAPPABLE
))
4213 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
4216 vma
= ggtt_view
? i915_gem_obj_to_ggtt_view(obj
, ggtt_view
) :
4217 i915_gem_obj_to_vma(obj
, vm
);
4220 return PTR_ERR(vma
);
4223 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
4226 if (i915_vma_misplaced(vma
, alignment
, flags
)) {
4227 WARN(vma
->pin_count
,
4228 "bo is already pinned in %s with incorrect alignment:"
4229 " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d,"
4230 " obj->map_and_fenceable=%d\n",
4231 ggtt_view
? "ggtt" : "ppgtt",
4232 upper_32_bits(vma
->node
.start
),
4233 lower_32_bits(vma
->node
.start
),
4235 !!(flags
& PIN_MAPPABLE
),
4236 obj
->map_and_fenceable
);
4237 ret
= i915_vma_unbind(vma
);
4245 bound
= vma
? vma
->bound
: 0;
4246 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
4247 vma
= i915_gem_object_bind_to_vm(obj
, vm
, ggtt_view
, alignment
,
4250 return PTR_ERR(vma
);
4252 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
4257 if (ggtt_view
&& ggtt_view
->type
== I915_GGTT_VIEW_NORMAL
&&
4258 (bound
^ vma
->bound
) & GLOBAL_BIND
) {
4259 __i915_vma_set_map_and_fenceable(vma
);
4260 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
4268 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
4269 struct i915_address_space
*vm
,
4273 return i915_gem_object_do_pin(obj
, vm
,
4274 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
,
4279 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
4280 const struct i915_ggtt_view
*view
,
4284 if (WARN_ONCE(!view
, "no view specified"))
4287 return i915_gem_object_do_pin(obj
, i915_obj_to_ggtt(obj
), view
,
4288 alignment
, flags
| PIN_GLOBAL
);
4292 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
4293 const struct i915_ggtt_view
*view
)
4295 struct i915_vma
*vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
4298 WARN_ON(vma
->pin_count
== 0);
4299 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj
, view
));
4305 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4306 struct drm_file
*file
)
4308 struct drm_i915_gem_busy
*args
= data
;
4309 struct drm_i915_gem_object
*obj
;
4312 ret
= i915_mutex_lock_interruptible(dev
);
4316 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4317 if (&obj
->base
== NULL
) {
4322 /* Count all active objects as busy, even if they are currently not used
4323 * by the gpu. Users of this interface expect objects to eventually
4324 * become non-busy without any further actions, therefore emit any
4325 * necessary flushes here.
4327 ret
= i915_gem_object_flush_active(obj
);
4331 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
4332 args
->busy
= obj
->active
<< 16;
4333 if (obj
->last_write_req
)
4334 args
->busy
|= obj
->last_write_req
->ring
->id
;
4337 drm_gem_object_unreference(&obj
->base
);
4339 mutex_unlock(&dev
->struct_mutex
);
4344 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4345 struct drm_file
*file_priv
)
4347 return i915_gem_ring_throttle(dev
, file_priv
);
4351 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4352 struct drm_file
*file_priv
)
4354 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4355 struct drm_i915_gem_madvise
*args
= data
;
4356 struct drm_i915_gem_object
*obj
;
4359 switch (args
->madv
) {
4360 case I915_MADV_DONTNEED
:
4361 case I915_MADV_WILLNEED
:
4367 ret
= i915_mutex_lock_interruptible(dev
);
4371 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
4372 if (&obj
->base
== NULL
) {
4377 if (i915_gem_obj_is_pinned(obj
)) {
4383 obj
->tiling_mode
!= I915_TILING_NONE
&&
4384 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
4385 if (obj
->madv
== I915_MADV_WILLNEED
)
4386 i915_gem_object_unpin_pages(obj
);
4387 if (args
->madv
== I915_MADV_WILLNEED
)
4388 i915_gem_object_pin_pages(obj
);
4391 if (obj
->madv
!= __I915_MADV_PURGED
)
4392 obj
->madv
= args
->madv
;
4394 /* if the object is no longer attached, discard its backing storage */
4395 if (obj
->madv
== I915_MADV_DONTNEED
&& obj
->pages
== NULL
)
4396 i915_gem_object_truncate(obj
);
4398 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4401 drm_gem_object_unreference(&obj
->base
);
4403 mutex_unlock(&dev
->struct_mutex
);
4407 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4408 const struct drm_i915_gem_object_ops
*ops
)
4412 INIT_LIST_HEAD(&obj
->global_list
);
4413 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4414 INIT_LIST_HEAD(&obj
->ring_list
[i
]);
4415 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4416 INIT_LIST_HEAD(&obj
->vma_list
);
4417 INIT_LIST_HEAD(&obj
->batch_pool_link
);
4421 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4422 obj
->madv
= I915_MADV_WILLNEED
;
4424 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4427 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4428 .flags
= I915_GEM_OBJECT_HAS_STRUCT_PAGE
,
4429 .get_pages
= i915_gem_object_get_pages_gtt
,
4430 .put_pages
= i915_gem_object_put_pages_gtt
,
4433 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
4436 struct drm_i915_gem_object
*obj
;
4437 struct address_space
*mapping
;
4440 obj
= i915_gem_object_alloc(dev
);
4444 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4445 i915_gem_object_free(obj
);
4449 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4450 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4451 /* 965gm cannot relocate objects above 4GiB. */
4452 mask
&= ~__GFP_HIGHMEM
;
4453 mask
|= __GFP_DMA32
;
4456 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4457 mapping_set_gfp_mask(mapping
, mask
);
4459 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4461 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4462 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4465 /* On some devices, we can have the GPU use the LLC (the CPU
4466 * cache) for about a 10% performance improvement
4467 * compared to uncached. Graphics requests other than
4468 * display scanout are coherent with the CPU in
4469 * accessing this cache. This means in this mode we
4470 * don't need to clflush on the CPU side, and on the
4471 * GPU side we only need to flush internal caches to
4472 * get data visible to the CPU.
4474 * However, we maintain the display planes as UC, and so
4475 * need to rebind when first used as such.
4477 obj
->cache_level
= I915_CACHE_LLC
;
4479 obj
->cache_level
= I915_CACHE_NONE
;
4481 trace_i915_gem_object_create(obj
);
4486 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4488 /* If we are the last user of the backing storage (be it shmemfs
4489 * pages or stolen etc), we know that the pages are going to be
4490 * immediately released. In this case, we can then skip copying
4491 * back the contents from the GPU.
4494 if (obj
->madv
!= I915_MADV_WILLNEED
)
4497 if (obj
->base
.filp
== NULL
)
4500 /* At first glance, this looks racy, but then again so would be
4501 * userspace racing mmap against close. However, the first external
4502 * reference to the filp can only be obtained through the
4503 * i915_gem_mmap_ioctl() which safeguards us against the user
4504 * acquiring such a reference whilst we are in the middle of
4505 * freeing the object.
4507 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4510 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4512 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4513 struct drm_device
*dev
= obj
->base
.dev
;
4514 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4515 struct i915_vma
*vma
, *next
;
4517 intel_runtime_pm_get(dev_priv
);
4519 trace_i915_gem_object_destroy(obj
);
4521 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4525 ret
= i915_vma_unbind(vma
);
4526 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4527 bool was_interruptible
;
4529 was_interruptible
= dev_priv
->mm
.interruptible
;
4530 dev_priv
->mm
.interruptible
= false;
4532 WARN_ON(i915_vma_unbind(vma
));
4534 dev_priv
->mm
.interruptible
= was_interruptible
;
4538 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4539 * before progressing. */
4541 i915_gem_object_unpin_pages(obj
);
4543 WARN_ON(obj
->frontbuffer_bits
);
4545 if (obj
->pages
&& obj
->madv
== I915_MADV_WILLNEED
&&
4546 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
&&
4547 obj
->tiling_mode
!= I915_TILING_NONE
)
4548 i915_gem_object_unpin_pages(obj
);
4550 if (WARN_ON(obj
->pages_pin_count
))
4551 obj
->pages_pin_count
= 0;
4552 if (discard_backing_storage(obj
))
4553 obj
->madv
= I915_MADV_DONTNEED
;
4554 i915_gem_object_put_pages(obj
);
4555 i915_gem_object_free_mmap_offset(obj
);
4559 if (obj
->base
.import_attach
)
4560 drm_prime_gem_destroy(&obj
->base
, NULL
);
4562 if (obj
->ops
->release
)
4563 obj
->ops
->release(obj
);
4565 drm_gem_object_release(&obj
->base
);
4566 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4569 i915_gem_object_free(obj
);
4571 intel_runtime_pm_put(dev_priv
);
4574 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4575 struct i915_address_space
*vm
)
4577 struct i915_vma
*vma
;
4578 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
4579 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
&&
4586 struct i915_vma
*i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
4587 const struct i915_ggtt_view
*view
)
4589 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
4590 struct i915_vma
*vma
;
4592 if (WARN_ONCE(!view
, "no view specified"))
4593 return ERR_PTR(-EINVAL
);
4595 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4596 if (vma
->vm
== ggtt
&&
4597 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
4602 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4604 struct i915_address_space
*vm
= NULL
;
4605 WARN_ON(vma
->node
.allocated
);
4607 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4608 if (!list_empty(&vma
->exec_list
))
4613 if (!i915_is_ggtt(vm
))
4614 i915_ppgtt_put(i915_vm_to_ppgtt(vm
));
4616 list_del(&vma
->vma_link
);
4618 kmem_cache_free(to_i915(vma
->obj
->base
.dev
)->vmas
, vma
);
4622 i915_gem_stop_ringbuffers(struct drm_device
*dev
)
4624 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4625 struct intel_engine_cs
*ring
;
4628 for_each_ring(ring
, dev_priv
, i
)
4629 dev_priv
->gt
.stop_ring(ring
);
4633 i915_gem_suspend(struct drm_device
*dev
)
4635 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4638 mutex_lock(&dev
->struct_mutex
);
4639 ret
= i915_gpu_idle(dev
);
4643 i915_gem_retire_requests(dev
);
4645 i915_gem_stop_ringbuffers(dev
);
4646 mutex_unlock(&dev
->struct_mutex
);
4648 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
4649 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4650 flush_delayed_work(&dev_priv
->mm
.idle_work
);
4652 /* Assert that we sucessfully flushed all the work and
4653 * reset the GPU back to its idle, low power state.
4655 WARN_ON(dev_priv
->mm
.busy
);
4660 mutex_unlock(&dev
->struct_mutex
);
4664 int i915_gem_l3_remap(struct drm_i915_gem_request
*req
, int slice
)
4666 struct intel_engine_cs
*ring
= req
->ring
;
4667 struct drm_device
*dev
= ring
->dev
;
4668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4669 u32
*remap_info
= dev_priv
->l3_parity
.remap_info
[slice
];
4672 if (!HAS_L3_DPF(dev
) || !remap_info
)
4675 ret
= intel_ring_begin(req
, GEN7_L3LOG_SIZE
/ 4 * 3);
4680 * Note: We do not worry about the concurrent register cacheline hang
4681 * here because no other code should access these registers other than
4682 * at initialization time.
4684 for (i
= 0; i
< GEN7_L3LOG_SIZE
/ 4; i
++) {
4685 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
4686 intel_ring_emit_reg(ring
, GEN7_L3LOG(slice
, i
));
4687 intel_ring_emit(ring
, remap_info
[i
]);
4690 intel_ring_advance(ring
);
4695 void i915_gem_init_swizzling(struct drm_device
*dev
)
4697 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4699 if (INTEL_INFO(dev
)->gen
< 5 ||
4700 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4703 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4704 DISP_TILE_SURFACE_SWIZZLING
);
4709 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4711 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4712 else if (IS_GEN7(dev
))
4713 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4714 else if (IS_GEN8(dev
))
4715 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4720 static void init_unused_ring(struct drm_device
*dev
, u32 base
)
4722 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4724 I915_WRITE(RING_CTL(base
), 0);
4725 I915_WRITE(RING_HEAD(base
), 0);
4726 I915_WRITE(RING_TAIL(base
), 0);
4727 I915_WRITE(RING_START(base
), 0);
4730 static void init_unused_rings(struct drm_device
*dev
)
4733 init_unused_ring(dev
, PRB1_BASE
);
4734 init_unused_ring(dev
, SRB0_BASE
);
4735 init_unused_ring(dev
, SRB1_BASE
);
4736 init_unused_ring(dev
, SRB2_BASE
);
4737 init_unused_ring(dev
, SRB3_BASE
);
4738 } else if (IS_GEN2(dev
)) {
4739 init_unused_ring(dev
, SRB0_BASE
);
4740 init_unused_ring(dev
, SRB1_BASE
);
4741 } else if (IS_GEN3(dev
)) {
4742 init_unused_ring(dev
, PRB1_BASE
);
4743 init_unused_ring(dev
, PRB2_BASE
);
4747 int i915_gem_init_rings(struct drm_device
*dev
)
4749 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4752 ret
= intel_init_render_ring_buffer(dev
);
4757 ret
= intel_init_bsd_ring_buffer(dev
);
4759 goto cleanup_render_ring
;
4763 ret
= intel_init_blt_ring_buffer(dev
);
4765 goto cleanup_bsd_ring
;
4768 if (HAS_VEBOX(dev
)) {
4769 ret
= intel_init_vebox_ring_buffer(dev
);
4771 goto cleanup_blt_ring
;
4774 if (HAS_BSD2(dev
)) {
4775 ret
= intel_init_bsd2_ring_buffer(dev
);
4777 goto cleanup_vebox_ring
;
4783 intel_cleanup_ring_buffer(&dev_priv
->ring
[VECS
]);
4785 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
4787 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
4788 cleanup_render_ring
:
4789 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
4795 i915_gem_init_hw(struct drm_device
*dev
)
4797 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4798 struct intel_engine_cs
*ring
;
4801 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
4804 /* Double layer security blanket, see i915_gem_init() */
4805 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4807 if (dev_priv
->ellc_size
)
4808 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4810 if (IS_HASWELL(dev
))
4811 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
4812 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
4814 if (HAS_PCH_NOP(dev
)) {
4815 if (IS_IVYBRIDGE(dev
)) {
4816 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4817 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4818 I915_WRITE(GEN7_MSG_CTL
, temp
);
4819 } else if (INTEL_INFO(dev
)->gen
>= 7) {
4820 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
4821 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
4822 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
4826 i915_gem_init_swizzling(dev
);
4829 * At least 830 can leave some of the unused rings
4830 * "active" (ie. head != tail) after resume which
4831 * will prevent c3 entry. Makes sure all unused rings
4834 init_unused_rings(dev
);
4836 BUG_ON(!dev_priv
->ring
[RCS
].default_context
);
4838 ret
= i915_ppgtt_init_hw(dev
);
4840 DRM_ERROR("PPGTT enable HW failed %d\n", ret
);
4844 /* Need to do basic initialisation of all rings first: */
4845 for_each_ring(ring
, dev_priv
, i
) {
4846 ret
= ring
->init_hw(ring
);
4851 /* We can't enable contexts until all firmware is loaded */
4852 if (HAS_GUC_UCODE(dev
)) {
4853 ret
= intel_guc_ucode_load(dev
);
4855 DRM_ERROR("Failed to initialize GuC, error %d\n", ret
);
4862 * Increment the next seqno by 0x100 so we have a visible break
4863 * on re-initialisation
4865 ret
= i915_gem_set_seqno(dev
, dev_priv
->next_seqno
+0x100);
4869 /* Now it is safe to go back round and do everything else: */
4870 for_each_ring(ring
, dev_priv
, i
) {
4871 struct drm_i915_gem_request
*req
;
4873 WARN_ON(!ring
->default_context
);
4875 ret
= i915_gem_request_alloc(ring
, ring
->default_context
, &req
);
4877 i915_gem_cleanup_ringbuffer(dev
);
4881 if (ring
->id
== RCS
) {
4882 for (j
= 0; j
< NUM_L3_SLICES(dev
); j
++)
4883 i915_gem_l3_remap(req
, j
);
4886 ret
= i915_ppgtt_init_ring(req
);
4887 if (ret
&& ret
!= -EIO
) {
4888 DRM_ERROR("PPGTT enable ring #%d failed %d\n", i
, ret
);
4889 i915_gem_request_cancel(req
);
4890 i915_gem_cleanup_ringbuffer(dev
);
4894 ret
= i915_gem_context_enable(req
);
4895 if (ret
&& ret
!= -EIO
) {
4896 DRM_ERROR("Context enable ring #%d failed %d\n", i
, ret
);
4897 i915_gem_request_cancel(req
);
4898 i915_gem_cleanup_ringbuffer(dev
);
4902 i915_add_request_no_flush(req
);
4906 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4910 int i915_gem_init(struct drm_device
*dev
)
4912 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4915 i915
.enable_execlists
= intel_sanitize_enable_execlists(dev
,
4916 i915
.enable_execlists
);
4918 mutex_lock(&dev
->struct_mutex
);
4920 if (!i915
.enable_execlists
) {
4921 dev_priv
->gt
.execbuf_submit
= i915_gem_ringbuffer_submission
;
4922 dev_priv
->gt
.init_rings
= i915_gem_init_rings
;
4923 dev_priv
->gt
.cleanup_ring
= intel_cleanup_ring_buffer
;
4924 dev_priv
->gt
.stop_ring
= intel_stop_ring_buffer
;
4926 dev_priv
->gt
.execbuf_submit
= intel_execlists_submission
;
4927 dev_priv
->gt
.init_rings
= intel_logical_rings_init
;
4928 dev_priv
->gt
.cleanup_ring
= intel_logical_ring_cleanup
;
4929 dev_priv
->gt
.stop_ring
= intel_logical_ring_stop
;
4932 /* This is just a security blanket to placate dragons.
4933 * On some systems, we very sporadically observe that the first TLBs
4934 * used by the CS may be stale, despite us poking the TLB reset. If
4935 * we hold the forcewake during initialisation these problems
4936 * just magically go away.
4938 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4940 ret
= i915_gem_init_userptr(dev
);
4944 i915_gem_init_global_gtt(dev
);
4946 ret
= i915_gem_context_init(dev
);
4950 ret
= dev_priv
->gt
.init_rings(dev
);
4954 ret
= i915_gem_init_hw(dev
);
4956 /* Allow ring initialisation to fail by marking the GPU as
4957 * wedged. But we only want to do this where the GPU is angry,
4958 * for all other failure, such as an allocation failure, bail.
4960 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4961 atomic_or(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
4966 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4967 mutex_unlock(&dev
->struct_mutex
);
4973 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4975 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4976 struct intel_engine_cs
*ring
;
4979 for_each_ring(ring
, dev_priv
, i
)
4980 dev_priv
->gt
.cleanup_ring(ring
);
4982 if (i915
.enable_execlists
)
4984 * Neither the BIOS, ourselves or any other kernel
4985 * expects the system to be in execlists mode on startup,
4986 * so we need to reset the GPU back to legacy mode.
4988 intel_gpu_reset(dev
);
4992 init_ring_lists(struct intel_engine_cs
*ring
)
4994 INIT_LIST_HEAD(&ring
->active_list
);
4995 INIT_LIST_HEAD(&ring
->request_list
);
4999 i915_gem_load(struct drm_device
*dev
)
5001 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5005 kmem_cache_create("i915_gem_object",
5006 sizeof(struct drm_i915_gem_object
), 0,
5010 kmem_cache_create("i915_gem_vma",
5011 sizeof(struct i915_vma
), 0,
5014 dev_priv
->requests
=
5015 kmem_cache_create("i915_gem_request",
5016 sizeof(struct drm_i915_gem_request
), 0,
5020 INIT_LIST_HEAD(&dev_priv
->vm_list
);
5021 INIT_LIST_HEAD(&dev_priv
->context_list
);
5022 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
5023 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
5024 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5025 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
5026 init_ring_lists(&dev_priv
->ring
[i
]);
5027 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
5028 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
5029 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
5030 i915_gem_retire_work_handler
);
5031 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
5032 i915_gem_idle_work_handler
);
5033 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
5035 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
5037 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
))
5038 dev_priv
->num_fence_regs
= 32;
5039 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
5040 dev_priv
->num_fence_regs
= 16;
5042 dev_priv
->num_fence_regs
= 8;
5044 if (intel_vgpu_active(dev
))
5045 dev_priv
->num_fence_regs
=
5046 I915_READ(vgtif_reg(avail_rs
.fence_num
));
5049 * Set initial sequence number for requests.
5050 * Using this number allows the wraparound to happen early,
5051 * catching any obvious problems.
5053 dev_priv
->next_seqno
= ((u32
)~0 - 0x1100);
5054 dev_priv
->last_seqno
= ((u32
)~0 - 0x1101);
5056 /* Initialize fence registers to zero */
5057 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5058 i915_gem_restore_fences(dev
);
5060 i915_gem_detect_bit_6_swizzle(dev
);
5061 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
5063 dev_priv
->mm
.interruptible
= true;
5065 i915_gem_shrinker_init(dev_priv
);
5067 mutex_init(&dev_priv
->fb_tracking
.lock
);
5070 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5072 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5074 /* Clean up our request list when the client is going away, so that
5075 * later retire_requests won't dereference our soon-to-be-gone
5078 spin_lock(&file_priv
->mm
.lock
);
5079 while (!list_empty(&file_priv
->mm
.request_list
)) {
5080 struct drm_i915_gem_request
*request
;
5082 request
= list_first_entry(&file_priv
->mm
.request_list
,
5083 struct drm_i915_gem_request
,
5085 list_del(&request
->client_list
);
5086 request
->file_priv
= NULL
;
5088 spin_unlock(&file_priv
->mm
.lock
);
5090 if (!list_empty(&file_priv
->rps
.link
)) {
5091 spin_lock(&to_i915(dev
)->rps
.client_lock
);
5092 list_del(&file_priv
->rps
.link
);
5093 spin_unlock(&to_i915(dev
)->rps
.client_lock
);
5097 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
5099 struct drm_i915_file_private
*file_priv
;
5102 DRM_DEBUG_DRIVER("\n");
5104 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
5108 file
->driver_priv
= file_priv
;
5109 file_priv
->dev_priv
= dev
->dev_private
;
5110 file_priv
->file
= file
;
5111 INIT_LIST_HEAD(&file_priv
->rps
.link
);
5113 spin_lock_init(&file_priv
->mm
.lock
);
5114 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
5116 ret
= i915_gem_context_open(dev
, file
);
5124 * i915_gem_track_fb - update frontbuffer tracking
5125 * @old: current GEM buffer for the frontbuffer slots
5126 * @new: new GEM buffer for the frontbuffer slots
5127 * @frontbuffer_bits: bitmask of frontbuffer slots
5129 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5130 * from @old and setting them in @new. Both @old and @new can be NULL.
5132 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
5133 struct drm_i915_gem_object
*new,
5134 unsigned frontbuffer_bits
)
5137 WARN_ON(!mutex_is_locked(&old
->base
.dev
->struct_mutex
));
5138 WARN_ON(!(old
->frontbuffer_bits
& frontbuffer_bits
));
5139 old
->frontbuffer_bits
&= ~frontbuffer_bits
;
5143 WARN_ON(!mutex_is_locked(&new->base
.dev
->struct_mutex
));
5144 WARN_ON(new->frontbuffer_bits
& frontbuffer_bits
);
5145 new->frontbuffer_bits
|= frontbuffer_bits
;
5149 /* All the new VM stuff */
5150 u64
i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
5151 struct i915_address_space
*vm
)
5153 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5154 struct i915_vma
*vma
;
5156 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5158 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5159 if (i915_is_ggtt(vma
->vm
) &&
5160 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5163 return vma
->node
.start
;
5166 WARN(1, "%s vma for this object not found.\n",
5167 i915_is_ggtt(vm
) ? "global" : "ppgtt");
5171 u64
i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
5172 const struct i915_ggtt_view
*view
)
5174 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5175 struct i915_vma
*vma
;
5177 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5178 if (vma
->vm
== ggtt
&&
5179 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
5180 return vma
->node
.start
;
5182 WARN(1, "global vma for this object not found. (view=%u)\n", view
->type
);
5186 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
5187 struct i915_address_space
*vm
)
5189 struct i915_vma
*vma
;
5191 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5192 if (i915_is_ggtt(vma
->vm
) &&
5193 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5195 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
5202 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
5203 const struct i915_ggtt_view
*view
)
5205 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5206 struct i915_vma
*vma
;
5208 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5209 if (vma
->vm
== ggtt
&&
5210 i915_ggtt_view_equal(&vma
->ggtt_view
, view
) &&
5211 drm_mm_node_allocated(&vma
->node
))
5217 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
5219 struct i915_vma
*vma
;
5221 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5222 if (drm_mm_node_allocated(&vma
->node
))
5228 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
5229 struct i915_address_space
*vm
)
5231 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5232 struct i915_vma
*vma
;
5234 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5236 BUG_ON(list_empty(&o
->vma_list
));
5238 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5239 if (i915_is_ggtt(vma
->vm
) &&
5240 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5243 return vma
->node
.size
;
5248 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
)
5250 struct i915_vma
*vma
;
5251 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
5252 if (vma
->pin_count
> 0)
5258 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
5260 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
, int n
)
5264 /* Only default objects have per-page dirty tracking */
5265 if (WARN_ON((obj
->ops
->flags
& I915_GEM_OBJECT_HAS_STRUCT_PAGE
) == 0))
5268 page
= i915_gem_object_get_page(obj
, n
);
5269 set_page_dirty(page
);
5273 /* Allocate a new GEM object and fill it with the supplied data */
5274 struct drm_i915_gem_object
*
5275 i915_gem_object_create_from_data(struct drm_device
*dev
,
5276 const void *data
, size_t size
)
5278 struct drm_i915_gem_object
*obj
;
5279 struct sg_table
*sg
;
5283 obj
= i915_gem_alloc_object(dev
, round_up(size
, PAGE_SIZE
));
5284 if (IS_ERR_OR_NULL(obj
))
5287 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
5291 ret
= i915_gem_object_get_pages(obj
);
5295 i915_gem_object_pin_pages(obj
);
5297 bytes
= sg_copy_from_buffer(sg
->sgl
, sg
->nents
, (void *)data
, size
);
5298 obj
->dirty
= 1; /* Backing store is now out of date */
5299 i915_gem_object_unpin_pages(obj
);
5301 if (WARN_ON(bytes
!= size
)) {
5302 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes
, size
);
5310 drm_gem_object_unreference(&obj
->base
);
5311 return ERR_PTR(ret
);