2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
38 #include <linux/dma-buf.h>
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
,
43 static __must_check
int
44 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
46 static __must_check
int
47 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
48 struct i915_address_space
*vm
,
50 bool map_and_fenceable
,
52 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
53 struct drm_i915_gem_object
*obj
,
54 struct drm_i915_gem_pwrite
*args
,
55 struct drm_file
*file
);
57 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
58 struct drm_i915_gem_object
*obj
);
59 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
60 struct drm_i915_fence_reg
*fence
,
63 static unsigned long i915_gem_inactive_count(struct shrinker
*shrinker
,
64 struct shrink_control
*sc
);
65 static unsigned long i915_gem_inactive_scan(struct shrinker
*shrinker
,
66 struct shrink_control
*sc
);
67 static unsigned long i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
);
68 static unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
69 static void i915_gem_object_truncate(struct drm_i915_gem_object
*obj
);
71 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
72 enum i915_cache_level level
)
74 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
77 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
79 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
82 return obj
->pin_display
;
85 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
88 i915_gem_release_mmap(obj
);
90 /* As we do not have an associated fence register, we will force
91 * a tiling change if we ever need to acquire one.
93 obj
->fence_dirty
= false;
94 obj
->fence_reg
= I915_FENCE_REG_NONE
;
97 /* some bookkeeping */
98 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
101 spin_lock(&dev_priv
->mm
.object_stat_lock
);
102 dev_priv
->mm
.object_count
++;
103 dev_priv
->mm
.object_memory
+= size
;
104 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
107 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
110 spin_lock(&dev_priv
->mm
.object_stat_lock
);
111 dev_priv
->mm
.object_count
--;
112 dev_priv
->mm
.object_memory
-= size
;
113 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
117 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
121 #define EXIT_COND (!i915_reset_in_progress(error) || \
122 i915_terminally_wedged(error))
127 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
128 * userspace. If it takes that long something really bad is going on and
129 * we should simply try to bail out and fail as gracefully as possible.
131 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
135 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
137 } else if (ret
< 0) {
145 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
147 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
150 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
154 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
158 WARN_ON(i915_verify_lists(dev
));
163 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
165 return i915_gem_obj_bound_any(obj
) && !obj
->active
;
169 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
170 struct drm_file
*file
)
172 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
173 struct drm_i915_gem_init
*args
= data
;
175 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
178 if (args
->gtt_start
>= args
->gtt_end
||
179 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
182 /* GEM with user mode setting was never supported on ilk and later. */
183 if (INTEL_INFO(dev
)->gen
>= 5)
186 mutex_lock(&dev
->struct_mutex
);
187 i915_gem_setup_global_gtt(dev
, args
->gtt_start
, args
->gtt_end
,
189 dev_priv
->gtt
.mappable_end
= args
->gtt_end
;
190 mutex_unlock(&dev
->struct_mutex
);
196 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
197 struct drm_file
*file
)
199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
200 struct drm_i915_gem_get_aperture
*args
= data
;
201 struct drm_i915_gem_object
*obj
;
205 mutex_lock(&dev
->struct_mutex
);
206 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
208 pinned
+= i915_gem_obj_ggtt_size(obj
);
209 mutex_unlock(&dev
->struct_mutex
);
211 args
->aper_size
= dev_priv
->gtt
.base
.total
;
212 args
->aper_available_size
= args
->aper_size
- pinned
;
217 void *i915_gem_object_alloc(struct drm_device
*dev
)
219 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
220 return kmem_cache_zalloc(dev_priv
->slab
, GFP_KERNEL
);
223 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
225 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
226 kmem_cache_free(dev_priv
->slab
, obj
);
230 i915_gem_create(struct drm_file
*file
,
231 struct drm_device
*dev
,
235 struct drm_i915_gem_object
*obj
;
239 size
= roundup(size
, PAGE_SIZE
);
243 /* Allocate the new object */
244 obj
= i915_gem_alloc_object(dev
, size
);
248 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
249 /* drop reference from allocate - handle holds it now */
250 drm_gem_object_unreference_unlocked(&obj
->base
);
259 i915_gem_dumb_create(struct drm_file
*file
,
260 struct drm_device
*dev
,
261 struct drm_mode_create_dumb
*args
)
263 /* have to work out size/pitch and return them */
264 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
265 args
->size
= args
->pitch
* args
->height
;
266 return i915_gem_create(file
, dev
,
267 args
->size
, &args
->handle
);
271 * Creates a new mm object and returns a handle to it.
274 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
275 struct drm_file
*file
)
277 struct drm_i915_gem_create
*args
= data
;
279 return i915_gem_create(file
, dev
,
280 args
->size
, &args
->handle
);
284 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
285 const char *gpu_vaddr
, int gpu_offset
,
288 int ret
, cpu_offset
= 0;
291 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
292 int this_length
= min(cacheline_end
- gpu_offset
, length
);
293 int swizzled_gpu_offset
= gpu_offset
^ 64;
295 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
296 gpu_vaddr
+ swizzled_gpu_offset
,
301 cpu_offset
+= this_length
;
302 gpu_offset
+= this_length
;
303 length
-= this_length
;
310 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
311 const char __user
*cpu_vaddr
,
314 int ret
, cpu_offset
= 0;
317 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
318 int this_length
= min(cacheline_end
- gpu_offset
, length
);
319 int swizzled_gpu_offset
= gpu_offset
^ 64;
321 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
322 cpu_vaddr
+ cpu_offset
,
327 cpu_offset
+= this_length
;
328 gpu_offset
+= this_length
;
329 length
-= this_length
;
335 /* Per-page copy function for the shmem pread fastpath.
336 * Flushes invalid cachelines before reading the target if
337 * needs_clflush is set. */
339 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
340 char __user
*user_data
,
341 bool page_do_bit17_swizzling
, bool needs_clflush
)
346 if (unlikely(page_do_bit17_swizzling
))
349 vaddr
= kmap_atomic(page
);
351 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
353 ret
= __copy_to_user_inatomic(user_data
,
354 vaddr
+ shmem_page_offset
,
356 kunmap_atomic(vaddr
);
358 return ret
? -EFAULT
: 0;
362 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
365 if (unlikely(swizzled
)) {
366 unsigned long start
= (unsigned long) addr
;
367 unsigned long end
= (unsigned long) addr
+ length
;
369 /* For swizzling simply ensure that we always flush both
370 * channels. Lame, but simple and it works. Swizzled
371 * pwrite/pread is far from a hotpath - current userspace
372 * doesn't use it at all. */
373 start
= round_down(start
, 128);
374 end
= round_up(end
, 128);
376 drm_clflush_virt_range((void *)start
, end
- start
);
378 drm_clflush_virt_range(addr
, length
);
383 /* Only difference to the fast-path function is that this can handle bit17
384 * and uses non-atomic copy and kmap functions. */
386 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
387 char __user
*user_data
,
388 bool page_do_bit17_swizzling
, bool needs_clflush
)
395 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
397 page_do_bit17_swizzling
);
399 if (page_do_bit17_swizzling
)
400 ret
= __copy_to_user_swizzled(user_data
,
401 vaddr
, shmem_page_offset
,
404 ret
= __copy_to_user(user_data
,
405 vaddr
+ shmem_page_offset
,
409 return ret
? - EFAULT
: 0;
413 i915_gem_shmem_pread(struct drm_device
*dev
,
414 struct drm_i915_gem_object
*obj
,
415 struct drm_i915_gem_pread
*args
,
416 struct drm_file
*file
)
418 char __user
*user_data
;
421 int shmem_page_offset
, page_length
, ret
= 0;
422 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
424 int needs_clflush
= 0;
425 struct sg_page_iter sg_iter
;
427 user_data
= to_user_ptr(args
->data_ptr
);
430 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
432 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
433 /* If we're not in the cpu read domain, set ourself into the gtt
434 * read domain and manually flush cachelines (if required). This
435 * optimizes for the case when the gpu will dirty the data
436 * anyway again before the next pread happens. */
437 needs_clflush
= !cpu_cache_is_coherent(dev
, obj
->cache_level
);
438 ret
= i915_gem_object_wait_rendering(obj
, true);
443 ret
= i915_gem_object_get_pages(obj
);
447 i915_gem_object_pin_pages(obj
);
449 offset
= args
->offset
;
451 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
452 offset
>> PAGE_SHIFT
) {
453 struct page
*page
= sg_page_iter_page(&sg_iter
);
458 /* Operation in this page
460 * shmem_page_offset = offset within page in shmem file
461 * page_length = bytes to copy for this page
463 shmem_page_offset
= offset_in_page(offset
);
464 page_length
= remain
;
465 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
466 page_length
= PAGE_SIZE
- shmem_page_offset
;
468 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
469 (page_to_phys(page
) & (1 << 17)) != 0;
471 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
472 user_data
, page_do_bit17_swizzling
,
477 mutex_unlock(&dev
->struct_mutex
);
479 if (likely(!i915_prefault_disable
) && !prefaulted
) {
480 ret
= fault_in_multipages_writeable(user_data
, remain
);
481 /* Userspace is tricking us, but we've already clobbered
482 * its pages with the prefault and promised to write the
483 * data up to the first fault. Hence ignore any errors
484 * and just continue. */
489 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
490 user_data
, page_do_bit17_swizzling
,
493 mutex_lock(&dev
->struct_mutex
);
496 mark_page_accessed(page
);
501 remain
-= page_length
;
502 user_data
+= page_length
;
503 offset
+= page_length
;
507 i915_gem_object_unpin_pages(obj
);
513 * Reads data from the object referenced by handle.
515 * On error, the contents of *data are undefined.
518 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
519 struct drm_file
*file
)
521 struct drm_i915_gem_pread
*args
= data
;
522 struct drm_i915_gem_object
*obj
;
528 if (!access_ok(VERIFY_WRITE
,
529 to_user_ptr(args
->data_ptr
),
533 ret
= i915_mutex_lock_interruptible(dev
);
537 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
538 if (&obj
->base
== NULL
) {
543 /* Bounds check source. */
544 if (args
->offset
> obj
->base
.size
||
545 args
->size
> obj
->base
.size
- args
->offset
) {
550 /* prime objects have no backing filp to GEM pread/pwrite
553 if (!obj
->base
.filp
) {
558 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
560 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
563 drm_gem_object_unreference(&obj
->base
);
565 mutex_unlock(&dev
->struct_mutex
);
569 /* This is the fast write path which cannot handle
570 * page faults in the source data
574 fast_user_write(struct io_mapping
*mapping
,
575 loff_t page_base
, int page_offset
,
576 char __user
*user_data
,
579 void __iomem
*vaddr_atomic
;
581 unsigned long unwritten
;
583 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
584 /* We can use the cpu mem copy function because this is X86. */
585 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
586 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
588 io_mapping_unmap_atomic(vaddr_atomic
);
593 * This is the fast pwrite path, where we copy the data directly from the
594 * user into the GTT, uncached.
597 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
598 struct drm_i915_gem_object
*obj
,
599 struct drm_i915_gem_pwrite
*args
,
600 struct drm_file
*file
)
602 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
604 loff_t offset
, page_base
;
605 char __user
*user_data
;
606 int page_offset
, page_length
, ret
;
608 ret
= i915_gem_obj_ggtt_pin(obj
, 0, true, true);
612 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
616 ret
= i915_gem_object_put_fence(obj
);
620 user_data
= to_user_ptr(args
->data_ptr
);
623 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
626 /* Operation in this page
628 * page_base = page offset within aperture
629 * page_offset = offset within page
630 * page_length = bytes to copy for this page
632 page_base
= offset
& PAGE_MASK
;
633 page_offset
= offset_in_page(offset
);
634 page_length
= remain
;
635 if ((page_offset
+ remain
) > PAGE_SIZE
)
636 page_length
= PAGE_SIZE
- page_offset
;
638 /* If we get a fault while copying data, then (presumably) our
639 * source page isn't available. Return the error and we'll
640 * retry in the slow path.
642 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
643 page_offset
, user_data
, page_length
)) {
648 remain
-= page_length
;
649 user_data
+= page_length
;
650 offset
+= page_length
;
654 i915_gem_object_unpin(obj
);
659 /* Per-page copy function for the shmem pwrite fastpath.
660 * Flushes invalid cachelines before writing to the target if
661 * needs_clflush_before is set and flushes out any written cachelines after
662 * writing if needs_clflush is set. */
664 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
665 char __user
*user_data
,
666 bool page_do_bit17_swizzling
,
667 bool needs_clflush_before
,
668 bool needs_clflush_after
)
673 if (unlikely(page_do_bit17_swizzling
))
676 vaddr
= kmap_atomic(page
);
677 if (needs_clflush_before
)
678 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
680 ret
= __copy_from_user_inatomic_nocache(vaddr
+ shmem_page_offset
,
683 if (needs_clflush_after
)
684 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
686 kunmap_atomic(vaddr
);
688 return ret
? -EFAULT
: 0;
691 /* Only difference to the fast-path function is that this can handle bit17
692 * and uses non-atomic copy and kmap functions. */
694 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
695 char __user
*user_data
,
696 bool page_do_bit17_swizzling
,
697 bool needs_clflush_before
,
698 bool needs_clflush_after
)
704 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
705 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
707 page_do_bit17_swizzling
);
708 if (page_do_bit17_swizzling
)
709 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
713 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
716 if (needs_clflush_after
)
717 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
719 page_do_bit17_swizzling
);
722 return ret
? -EFAULT
: 0;
726 i915_gem_shmem_pwrite(struct drm_device
*dev
,
727 struct drm_i915_gem_object
*obj
,
728 struct drm_i915_gem_pwrite
*args
,
729 struct drm_file
*file
)
733 char __user
*user_data
;
734 int shmem_page_offset
, page_length
, ret
= 0;
735 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
736 int hit_slowpath
= 0;
737 int needs_clflush_after
= 0;
738 int needs_clflush_before
= 0;
739 struct sg_page_iter sg_iter
;
741 user_data
= to_user_ptr(args
->data_ptr
);
744 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
746 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
747 /* If we're not in the cpu write domain, set ourself into the gtt
748 * write domain and manually flush cachelines (if required). This
749 * optimizes for the case when the gpu will use the data
750 * right away and we therefore have to clflush anyway. */
751 needs_clflush_after
= cpu_write_needs_clflush(obj
);
752 ret
= i915_gem_object_wait_rendering(obj
, false);
756 /* Same trick applies to invalidate partially written cachelines read
758 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
759 needs_clflush_before
=
760 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
762 ret
= i915_gem_object_get_pages(obj
);
766 i915_gem_object_pin_pages(obj
);
768 offset
= args
->offset
;
771 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
772 offset
>> PAGE_SHIFT
) {
773 struct page
*page
= sg_page_iter_page(&sg_iter
);
774 int partial_cacheline_write
;
779 /* Operation in this page
781 * shmem_page_offset = offset within page in shmem file
782 * page_length = bytes to copy for this page
784 shmem_page_offset
= offset_in_page(offset
);
786 page_length
= remain
;
787 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
788 page_length
= PAGE_SIZE
- shmem_page_offset
;
790 /* If we don't overwrite a cacheline completely we need to be
791 * careful to have up-to-date data by first clflushing. Don't
792 * overcomplicate things and flush the entire patch. */
793 partial_cacheline_write
= needs_clflush_before
&&
794 ((shmem_page_offset
| page_length
)
795 & (boot_cpu_data
.x86_clflush_size
- 1));
797 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
798 (page_to_phys(page
) & (1 << 17)) != 0;
800 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
801 user_data
, page_do_bit17_swizzling
,
802 partial_cacheline_write
,
803 needs_clflush_after
);
808 mutex_unlock(&dev
->struct_mutex
);
809 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
810 user_data
, page_do_bit17_swizzling
,
811 partial_cacheline_write
,
812 needs_clflush_after
);
814 mutex_lock(&dev
->struct_mutex
);
817 set_page_dirty(page
);
818 mark_page_accessed(page
);
823 remain
-= page_length
;
824 user_data
+= page_length
;
825 offset
+= page_length
;
829 i915_gem_object_unpin_pages(obj
);
833 * Fixup: Flush cpu caches in case we didn't flush the dirty
834 * cachelines in-line while writing and the object moved
835 * out of the cpu write domain while we've dropped the lock.
837 if (!needs_clflush_after
&&
838 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
839 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
840 i915_gem_chipset_flush(dev
);
844 if (needs_clflush_after
)
845 i915_gem_chipset_flush(dev
);
851 * Writes data to the object referenced by handle.
853 * On error, the contents of the buffer that were to be modified are undefined.
856 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
857 struct drm_file
*file
)
859 struct drm_i915_gem_pwrite
*args
= data
;
860 struct drm_i915_gem_object
*obj
;
866 if (!access_ok(VERIFY_READ
,
867 to_user_ptr(args
->data_ptr
),
871 if (likely(!i915_prefault_disable
)) {
872 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
878 ret
= i915_mutex_lock_interruptible(dev
);
882 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
883 if (&obj
->base
== NULL
) {
888 /* Bounds check destination. */
889 if (args
->offset
> obj
->base
.size
||
890 args
->size
> obj
->base
.size
- args
->offset
) {
895 /* prime objects have no backing filp to GEM pread/pwrite
898 if (!obj
->base
.filp
) {
903 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
906 /* We can only do the GTT pwrite on untiled buffers, as otherwise
907 * it would end up going through the fenced access, and we'll get
908 * different detiling behavior between reading and writing.
909 * pread/pwrite currently are reading and writing from the CPU
910 * perspective, requiring manual detiling by the client.
913 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
917 if (obj
->tiling_mode
== I915_TILING_NONE
&&
918 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
919 cpu_write_needs_clflush(obj
)) {
920 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
921 /* Note that the gtt paths might fail with non-page-backed user
922 * pointers (e.g. gtt mappings when moving data between
923 * textures). Fallback to the shmem path in that case. */
926 if (ret
== -EFAULT
|| ret
== -ENOSPC
)
927 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
930 drm_gem_object_unreference(&obj
->base
);
932 mutex_unlock(&dev
->struct_mutex
);
937 i915_gem_check_wedge(struct i915_gpu_error
*error
,
940 if (i915_reset_in_progress(error
)) {
941 /* Non-interruptible callers can't handle -EAGAIN, hence return
942 * -EIO unconditionally for these. */
946 /* Recovery complete, but the reset failed ... */
947 if (i915_terminally_wedged(error
))
957 * Compare seqno against outstanding lazy request. Emit a request if they are
961 i915_gem_check_olr(struct intel_ring_buffer
*ring
, u32 seqno
)
965 BUG_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
968 if (seqno
== ring
->outstanding_lazy_seqno
)
969 ret
= i915_add_request(ring
, NULL
);
974 static void fake_irq(unsigned long data
)
976 wake_up_process((struct task_struct
*)data
);
979 static bool missed_irq(struct drm_i915_private
*dev_priv
,
980 struct intel_ring_buffer
*ring
)
982 return test_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
985 static bool can_wait_boost(struct drm_i915_file_private
*file_priv
)
987 if (file_priv
== NULL
)
990 return !atomic_xchg(&file_priv
->rps_wait_boost
, true);
994 * __wait_seqno - wait until execution of seqno has finished
995 * @ring: the ring expected to report seqno
997 * @reset_counter: reset sequence associated with the given seqno
998 * @interruptible: do an interruptible wait (normally yes)
999 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1001 * Note: It is of utmost importance that the passed in seqno and reset_counter
1002 * values have been read by the caller in an smp safe manner. Where read-side
1003 * locks are involved, it is sufficient to read the reset_counter before
1004 * unlocking the lock that protects the seqno. For lockless tricks, the
1005 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1008 * Returns 0 if the seqno was found within the alloted time. Else returns the
1009 * errno with remaining time filled in timeout argument.
1011 static int __wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
,
1012 unsigned reset_counter
,
1014 struct timespec
*timeout
,
1015 struct drm_i915_file_private
*file_priv
)
1017 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1018 const bool irq_test_in_progress
=
1019 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_ring_flag(ring
);
1020 struct timespec before
, now
;
1022 unsigned long timeout_expire
;
1025 WARN(dev_priv
->pc8
.irqs_disabled
, "IRQs disabled\n");
1027 if (i915_seqno_passed(ring
->get_seqno(ring
, true), seqno
))
1030 timeout_expire
= timeout
? jiffies
+ timespec_to_jiffies_timeout(timeout
) : 0;
1032 if (dev_priv
->info
->gen
>= 6 && can_wait_boost(file_priv
)) {
1033 gen6_rps_boost(dev_priv
);
1035 mod_delayed_work(dev_priv
->wq
,
1036 &file_priv
->mm
.idle_work
,
1037 msecs_to_jiffies(100));
1040 if (!irq_test_in_progress
&& WARN_ON(!ring
->irq_get(ring
)))
1043 /* Record current time in case interrupted by signal, or wedged */
1044 trace_i915_gem_request_wait_begin(ring
, seqno
);
1045 getrawmonotonic(&before
);
1047 struct timer_list timer
;
1049 prepare_to_wait(&ring
->irq_queue
, &wait
,
1050 interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
);
1052 /* We need to check whether any gpu reset happened in between
1053 * the caller grabbing the seqno and now ... */
1054 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
)) {
1055 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1056 * is truely gone. */
1057 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1063 if (i915_seqno_passed(ring
->get_seqno(ring
, false), seqno
)) {
1068 if (interruptible
&& signal_pending(current
)) {
1073 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1078 timer
.function
= NULL
;
1079 if (timeout
|| missed_irq(dev_priv
, ring
)) {
1080 unsigned long expire
;
1082 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1083 expire
= missed_irq(dev_priv
, ring
) ? jiffies
+ 1 : timeout_expire
;
1084 mod_timer(&timer
, expire
);
1089 if (timer
.function
) {
1090 del_singleshot_timer_sync(&timer
);
1091 destroy_timer_on_stack(&timer
);
1094 getrawmonotonic(&now
);
1095 trace_i915_gem_request_wait_end(ring
, seqno
);
1097 if (!irq_test_in_progress
)
1098 ring
->irq_put(ring
);
1100 finish_wait(&ring
->irq_queue
, &wait
);
1103 struct timespec sleep_time
= timespec_sub(now
, before
);
1104 *timeout
= timespec_sub(*timeout
, sleep_time
);
1105 if (!timespec_valid(timeout
)) /* i.e. negative time remains */
1106 set_normalized_timespec(timeout
, 0, 0);
1113 * Waits for a sequence number to be signaled, and cleans up the
1114 * request and object lists appropriately for that event.
1117 i915_wait_seqno(struct intel_ring_buffer
*ring
, uint32_t seqno
)
1119 struct drm_device
*dev
= ring
->dev
;
1120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1121 bool interruptible
= dev_priv
->mm
.interruptible
;
1124 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1127 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1131 ret
= i915_gem_check_olr(ring
, seqno
);
1135 return __wait_seqno(ring
, seqno
,
1136 atomic_read(&dev_priv
->gpu_error
.reset_counter
),
1137 interruptible
, NULL
, NULL
);
1141 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object
*obj
,
1142 struct intel_ring_buffer
*ring
)
1144 i915_gem_retire_requests_ring(ring
);
1146 /* Manually manage the write flush as we may have not yet
1147 * retired the buffer.
1149 * Note that the last_write_seqno is always the earlier of
1150 * the two (read/write) seqno, so if we haved successfully waited,
1151 * we know we have passed the last write.
1153 obj
->last_write_seqno
= 0;
1154 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1160 * Ensures that all rendering to the object has completed and the object is
1161 * safe to unbind from the GTT or access from the CPU.
1163 static __must_check
int
1164 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1167 struct intel_ring_buffer
*ring
= obj
->ring
;
1171 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1175 ret
= i915_wait_seqno(ring
, seqno
);
1179 return i915_gem_object_wait_rendering__tail(obj
, ring
);
1182 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1183 * as the object state may change during this call.
1185 static __must_check
int
1186 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1187 struct drm_file
*file
,
1190 struct drm_device
*dev
= obj
->base
.dev
;
1191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1192 struct intel_ring_buffer
*ring
= obj
->ring
;
1193 unsigned reset_counter
;
1197 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1198 BUG_ON(!dev_priv
->mm
.interruptible
);
1200 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1204 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1208 ret
= i915_gem_check_olr(ring
, seqno
);
1212 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1213 mutex_unlock(&dev
->struct_mutex
);
1214 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, NULL
, file
->driver_priv
);
1215 mutex_lock(&dev
->struct_mutex
);
1219 return i915_gem_object_wait_rendering__tail(obj
, ring
);
1223 * Called when user space prepares to use an object with the CPU, either
1224 * through the mmap ioctl's mapping or a GTT mapping.
1227 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1228 struct drm_file
*file
)
1230 struct drm_i915_gem_set_domain
*args
= data
;
1231 struct drm_i915_gem_object
*obj
;
1232 uint32_t read_domains
= args
->read_domains
;
1233 uint32_t write_domain
= args
->write_domain
;
1236 /* Only handle setting domains to types used by the CPU. */
1237 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1240 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1243 /* Having something in the write domain implies it's in the read
1244 * domain, and only that read domain. Enforce that in the request.
1246 if (write_domain
!= 0 && read_domains
!= write_domain
)
1249 ret
= i915_mutex_lock_interruptible(dev
);
1253 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1254 if (&obj
->base
== NULL
) {
1259 /* Try to flush the object off the GPU without holding the lock.
1260 * We will repeat the flush holding the lock in the normal manner
1261 * to catch cases where we are gazumped.
1263 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, file
, !write_domain
);
1267 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1268 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1270 /* Silently promote "you're not bound, there was nothing to do"
1271 * to success, since the client was just asking us to
1272 * make sure everything was done.
1277 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1281 drm_gem_object_unreference(&obj
->base
);
1283 mutex_unlock(&dev
->struct_mutex
);
1288 * Called when user space has done writes to this buffer
1291 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1292 struct drm_file
*file
)
1294 struct drm_i915_gem_sw_finish
*args
= data
;
1295 struct drm_i915_gem_object
*obj
;
1298 ret
= i915_mutex_lock_interruptible(dev
);
1302 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1303 if (&obj
->base
== NULL
) {
1308 /* Pinned buffers may be scanout, so flush the cache */
1309 if (obj
->pin_display
)
1310 i915_gem_object_flush_cpu_write_domain(obj
, true);
1312 drm_gem_object_unreference(&obj
->base
);
1314 mutex_unlock(&dev
->struct_mutex
);
1319 * Maps the contents of an object, returning the address it is mapped
1322 * While the mapping holds a reference on the contents of the object, it doesn't
1323 * imply a ref on the object itself.
1326 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1327 struct drm_file
*file
)
1329 struct drm_i915_gem_mmap
*args
= data
;
1330 struct drm_gem_object
*obj
;
1333 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1337 /* prime objects have no backing filp to GEM mmap
1341 drm_gem_object_unreference_unlocked(obj
);
1345 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1346 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1348 drm_gem_object_unreference_unlocked(obj
);
1349 if (IS_ERR((void *)addr
))
1352 args
->addr_ptr
= (uint64_t) addr
;
1358 * i915_gem_fault - fault a page into the GTT
1359 * vma: VMA in question
1362 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1363 * from userspace. The fault handler takes care of binding the object to
1364 * the GTT (if needed), allocating and programming a fence register (again,
1365 * only if needed based on whether the old reg is still valid or the object
1366 * is tiled) and inserting a new PTE into the faulting process.
1368 * Note that the faulting process may involve evicting existing objects
1369 * from the GTT and/or fence registers to make room. So performance may
1370 * suffer if the GTT working set is large or there are few fence registers
1373 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1375 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1376 struct drm_device
*dev
= obj
->base
.dev
;
1377 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1378 pgoff_t page_offset
;
1381 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1383 intel_runtime_pm_get(dev_priv
);
1385 /* We don't use vmf->pgoff since that has the fake offset */
1386 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1389 ret
= i915_mutex_lock_interruptible(dev
);
1393 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1395 /* Access to snoopable pages through the GTT is incoherent. */
1396 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1401 /* Now bind it into the GTT if needed */
1402 ret
= i915_gem_obj_ggtt_pin(obj
, 0, true, false);
1406 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1410 ret
= i915_gem_object_get_fence(obj
);
1414 obj
->fault_mappable
= true;
1416 pfn
= dev_priv
->gtt
.mappable_base
+ i915_gem_obj_ggtt_offset(obj
);
1420 /* Finally, remap it using the new GTT offset */
1421 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1423 i915_gem_object_unpin(obj
);
1425 mutex_unlock(&dev
->struct_mutex
);
1429 /* If this -EIO is due to a gpu hang, give the reset code a
1430 * chance to clean up the mess. Otherwise return the proper
1432 if (i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1433 ret
= VM_FAULT_SIGBUS
;
1438 * EAGAIN means the gpu is hung and we'll wait for the error
1439 * handler to reset everything when re-faulting in
1440 * i915_mutex_lock_interruptible.
1447 * EBUSY is ok: this just means that another thread
1448 * already did the job.
1450 ret
= VM_FAULT_NOPAGE
;
1456 ret
= VM_FAULT_SIGBUS
;
1459 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1460 ret
= VM_FAULT_SIGBUS
;
1464 intel_runtime_pm_put(dev_priv
);
1469 * i915_gem_release_mmap - remove physical page mappings
1470 * @obj: obj in question
1472 * Preserve the reservation of the mmapping with the DRM core code, but
1473 * relinquish ownership of the pages back to the system.
1475 * It is vital that we remove the page mapping if we have mapped a tiled
1476 * object through the GTT and then lose the fence register due to
1477 * resource pressure. Similarly if the object has been moved out of the
1478 * aperture, than pages mapped into userspace must be revoked. Removing the
1479 * mapping will then trigger a page fault on the next user access, allowing
1480 * fixup by i915_gem_fault().
1483 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1485 if (!obj
->fault_mappable
)
1488 drm_vma_node_unmap(&obj
->base
.vma_node
, obj
->base
.dev
->dev_mapping
);
1489 obj
->fault_mappable
= false;
1493 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1497 if (INTEL_INFO(dev
)->gen
>= 4 ||
1498 tiling_mode
== I915_TILING_NONE
)
1501 /* Previous chips need a power-of-two fence region when tiling */
1502 if (INTEL_INFO(dev
)->gen
== 3)
1503 gtt_size
= 1024*1024;
1505 gtt_size
= 512*1024;
1507 while (gtt_size
< size
)
1514 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1515 * @obj: object to check
1517 * Return the required GTT alignment for an object, taking into account
1518 * potential fence register mapping.
1521 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1522 int tiling_mode
, bool fenced
)
1525 * Minimum alignment is 4k (GTT page size), but might be greater
1526 * if a fence register is needed for the object.
1528 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1529 tiling_mode
== I915_TILING_NONE
)
1533 * Previous chips need to be aligned to the size of the smallest
1534 * fence register that can contain the object.
1536 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1539 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1541 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1544 if (drm_vma_node_has_offset(&obj
->base
.vma_node
))
1547 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1549 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1553 /* Badly fragmented mmap space? The only way we can recover
1554 * space is by destroying unwanted objects. We can't randomly release
1555 * mmap_offsets as userspace expects them to be persistent for the
1556 * lifetime of the objects. The closest we can is to release the
1557 * offsets on purgeable objects by truncating it and marking it purged,
1558 * which prevents userspace from ever using that object again.
1560 i915_gem_purge(dev_priv
, obj
->base
.size
>> PAGE_SHIFT
);
1561 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1565 i915_gem_shrink_all(dev_priv
);
1566 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1568 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
1573 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1575 drm_gem_free_mmap_offset(&obj
->base
);
1579 i915_gem_mmap_gtt(struct drm_file
*file
,
1580 struct drm_device
*dev
,
1584 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1585 struct drm_i915_gem_object
*obj
;
1588 ret
= i915_mutex_lock_interruptible(dev
);
1592 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1593 if (&obj
->base
== NULL
) {
1598 if (obj
->base
.size
> dev_priv
->gtt
.mappable_end
) {
1603 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1604 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1609 ret
= i915_gem_object_create_mmap_offset(obj
);
1613 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
1616 drm_gem_object_unreference(&obj
->base
);
1618 mutex_unlock(&dev
->struct_mutex
);
1623 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1625 * @data: GTT mapping ioctl data
1626 * @file: GEM object info
1628 * Simply returns the fake offset to userspace so it can mmap it.
1629 * The mmap call will end up in drm_gem_mmap(), which will set things
1630 * up so we can get faults in the handler above.
1632 * The fault handler will take care of binding the object into the GTT
1633 * (since it may have been evicted to make room for something), allocating
1634 * a fence register, and mapping the appropriate aperture address into
1638 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1639 struct drm_file
*file
)
1641 struct drm_i915_gem_mmap_gtt
*args
= data
;
1643 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1646 /* Immediately discard the backing storage */
1648 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1650 struct inode
*inode
;
1652 i915_gem_object_free_mmap_offset(obj
);
1654 if (obj
->base
.filp
== NULL
)
1657 /* Our goal here is to return as much of the memory as
1658 * is possible back to the system as we are called from OOM.
1659 * To do this we must instruct the shmfs to drop all of its
1660 * backing pages, *now*.
1662 inode
= file_inode(obj
->base
.filp
);
1663 shmem_truncate_range(inode
, 0, (loff_t
)-1);
1665 obj
->madv
= __I915_MADV_PURGED
;
1669 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1671 return obj
->madv
== I915_MADV_DONTNEED
;
1675 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1677 struct sg_page_iter sg_iter
;
1680 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1682 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1684 /* In the event of a disaster, abandon all caches and
1685 * hope for the best.
1687 WARN_ON(ret
!= -EIO
);
1688 i915_gem_clflush_object(obj
, true);
1689 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
1692 if (i915_gem_object_needs_bit17_swizzle(obj
))
1693 i915_gem_object_save_bit_17_swizzle(obj
);
1695 if (obj
->madv
== I915_MADV_DONTNEED
)
1698 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
1699 struct page
*page
= sg_page_iter_page(&sg_iter
);
1702 set_page_dirty(page
);
1704 if (obj
->madv
== I915_MADV_WILLNEED
)
1705 mark_page_accessed(page
);
1707 page_cache_release(page
);
1711 sg_free_table(obj
->pages
);
1716 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
1718 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1720 if (obj
->pages
== NULL
)
1723 if (obj
->pages_pin_count
)
1726 BUG_ON(i915_gem_obj_bound_any(obj
));
1728 /* ->put_pages might need to allocate memory for the bit17 swizzle
1729 * array, hence protect them from being reaped by removing them from gtt
1731 list_del(&obj
->global_list
);
1733 ops
->put_pages(obj
);
1736 if (i915_gem_object_is_purgeable(obj
))
1737 i915_gem_object_truncate(obj
);
1742 static unsigned long
1743 __i915_gem_shrink(struct drm_i915_private
*dev_priv
, long target
,
1744 bool purgeable_only
)
1746 struct list_head still_bound_list
;
1747 struct drm_i915_gem_object
*obj
, *next
;
1748 unsigned long count
= 0;
1750 list_for_each_entry_safe(obj
, next
,
1751 &dev_priv
->mm
.unbound_list
,
1753 if ((i915_gem_object_is_purgeable(obj
) || !purgeable_only
) &&
1754 i915_gem_object_put_pages(obj
) == 0) {
1755 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1756 if (count
>= target
)
1762 * As we may completely rewrite the bound list whilst unbinding
1763 * (due to retiring requests) we have to strictly process only
1764 * one element of the list at the time, and recheck the list
1765 * on every iteration.
1767 INIT_LIST_HEAD(&still_bound_list
);
1768 while (count
< target
&& !list_empty(&dev_priv
->mm
.bound_list
)) {
1769 struct i915_vma
*vma
, *v
;
1771 obj
= list_first_entry(&dev_priv
->mm
.bound_list
,
1772 typeof(*obj
), global_list
);
1773 list_move_tail(&obj
->global_list
, &still_bound_list
);
1775 if (!i915_gem_object_is_purgeable(obj
) && purgeable_only
)
1779 * Hold a reference whilst we unbind this object, as we may
1780 * end up waiting for and retiring requests. This might
1781 * release the final reference (held by the active list)
1782 * and result in the object being freed from under us.
1783 * in this object being freed.
1785 * Note 1: Shrinking the bound list is special since only active
1786 * (and hence bound objects) can contain such limbo objects, so
1787 * we don't need special tricks for shrinking the unbound list.
1788 * The only other place where we have to be careful with active
1789 * objects suddenly disappearing due to retiring requests is the
1792 * Note 2: Even though the bound list doesn't hold a reference
1793 * to the object we can safely grab one here: The final object
1794 * unreferencing and the bound_list are both protected by the
1795 * dev->struct_mutex and so we won't ever be able to observe an
1796 * object on the bound_list with a reference count equals 0.
1798 drm_gem_object_reference(&obj
->base
);
1800 list_for_each_entry_safe(vma
, v
, &obj
->vma_list
, vma_link
)
1801 if (i915_vma_unbind(vma
))
1804 if (i915_gem_object_put_pages(obj
) == 0)
1805 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1807 drm_gem_object_unreference(&obj
->base
);
1809 list_splice(&still_bound_list
, &dev_priv
->mm
.bound_list
);
1814 static unsigned long
1815 i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
)
1817 return __i915_gem_shrink(dev_priv
, target
, true);
1820 static unsigned long
1821 i915_gem_shrink_all(struct drm_i915_private
*dev_priv
)
1823 struct drm_i915_gem_object
*obj
, *next
;
1826 i915_gem_evict_everything(dev_priv
->dev
);
1828 list_for_each_entry_safe(obj
, next
, &dev_priv
->mm
.unbound_list
,
1830 if (i915_gem_object_put_pages(obj
) == 0)
1831 freed
+= obj
->base
.size
>> PAGE_SHIFT
;
1837 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
1839 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1841 struct address_space
*mapping
;
1842 struct sg_table
*st
;
1843 struct scatterlist
*sg
;
1844 struct sg_page_iter sg_iter
;
1846 unsigned long last_pfn
= 0; /* suppress gcc warning */
1849 /* Assert that the object is not currently in any GPU domain. As it
1850 * wasn't in the GTT, there shouldn't be any way it could have been in
1853 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
1854 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
1856 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
1860 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1861 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
1866 /* Get the list of pages out of our struct file. They'll be pinned
1867 * at this point until we release them.
1869 * Fail silently without starting the shrinker
1871 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
1872 gfp
= mapping_gfp_mask(mapping
);
1873 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1874 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1877 for (i
= 0; i
< page_count
; i
++) {
1878 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1880 i915_gem_purge(dev_priv
, page_count
);
1881 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1884 /* We've tried hard to allocate the memory by reaping
1885 * our own buffer, now let the real VM do its job and
1886 * go down in flames if truly OOM.
1888 gfp
&= ~(__GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
);
1889 gfp
|= __GFP_IO
| __GFP_WAIT
;
1891 i915_gem_shrink_all(dev_priv
);
1892 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1896 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1897 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1899 #ifdef CONFIG_SWIOTLB
1900 if (swiotlb_nr_tbl()) {
1902 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
1907 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
1911 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
1913 sg
->length
+= PAGE_SIZE
;
1915 last_pfn
= page_to_pfn(page
);
1917 /* Check that the i965g/gm workaround works. */
1918 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
1920 #ifdef CONFIG_SWIOTLB
1921 if (!swiotlb_nr_tbl())
1926 if (i915_gem_object_needs_bit17_swizzle(obj
))
1927 i915_gem_object_do_bit_17_swizzle(obj
);
1933 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
1934 page_cache_release(sg_page_iter_page(&sg_iter
));
1937 return PTR_ERR(page
);
1940 /* Ensure that the associated pages are gathered from the backing storage
1941 * and pinned into our object. i915_gem_object_get_pages() may be called
1942 * multiple times before they are released by a single call to
1943 * i915_gem_object_put_pages() - once the pages are no longer referenced
1944 * either as a result of memory pressure (reaping pages under the shrinker)
1945 * or as the object is itself released.
1948 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
1950 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1951 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1957 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1958 DRM_ERROR("Attempting to obtain a purgeable object\n");
1962 BUG_ON(obj
->pages_pin_count
);
1964 ret
= ops
->get_pages(obj
);
1968 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
1973 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1974 struct intel_ring_buffer
*ring
)
1976 struct drm_device
*dev
= obj
->base
.dev
;
1977 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1978 u32 seqno
= intel_ring_get_seqno(ring
);
1980 BUG_ON(ring
== NULL
);
1981 if (obj
->ring
!= ring
&& obj
->last_write_seqno
) {
1982 /* Keep the seqno relative to the current ring */
1983 obj
->last_write_seqno
= seqno
;
1987 /* Add a reference if we're newly entering the active list. */
1989 drm_gem_object_reference(&obj
->base
);
1993 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
1995 obj
->last_read_seqno
= seqno
;
1997 if (obj
->fenced_gpu_access
) {
1998 obj
->last_fenced_seqno
= seqno
;
2000 /* Bump MRU to take account of the delayed flush */
2001 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2002 struct drm_i915_fence_reg
*reg
;
2004 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2005 list_move_tail(®
->lru_list
,
2006 &dev_priv
->mm
.fence_list
);
2011 void i915_vma_move_to_active(struct i915_vma
*vma
,
2012 struct intel_ring_buffer
*ring
)
2014 list_move_tail(&vma
->mm_list
, &vma
->vm
->active_list
);
2015 return i915_gem_object_move_to_active(vma
->obj
, ring
);
2019 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
2021 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2022 struct i915_address_space
*ggtt_vm
= &dev_priv
->gtt
.base
;
2023 struct i915_vma
*vma
= i915_gem_obj_to_vma(obj
, ggtt_vm
);
2025 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
2026 BUG_ON(!obj
->active
);
2028 list_move_tail(&vma
->mm_list
, &ggtt_vm
->inactive_list
);
2030 list_del_init(&obj
->ring_list
);
2033 obj
->last_read_seqno
= 0;
2034 obj
->last_write_seqno
= 0;
2035 obj
->base
.write_domain
= 0;
2037 obj
->last_fenced_seqno
= 0;
2038 obj
->fenced_gpu_access
= false;
2041 drm_gem_object_unreference(&obj
->base
);
2043 WARN_ON(i915_verify_lists(dev
));
2047 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
2049 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2050 struct intel_ring_buffer
*ring
;
2053 /* Carefully retire all requests without writing to the rings */
2054 for_each_ring(ring
, dev_priv
, i
) {
2055 ret
= intel_ring_idle(ring
);
2059 i915_gem_retire_requests(dev
);
2061 /* Finally reset hw state */
2062 for_each_ring(ring
, dev_priv
, i
) {
2063 intel_ring_init_seqno(ring
, seqno
);
2065 for (j
= 0; j
< ARRAY_SIZE(ring
->sync_seqno
); j
++)
2066 ring
->sync_seqno
[j
] = 0;
2072 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2074 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2080 /* HWS page needs to be set less than what we
2081 * will inject to ring
2083 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
2087 /* Carefully set the last_seqno value so that wrap
2088 * detection still works
2090 dev_priv
->next_seqno
= seqno
;
2091 dev_priv
->last_seqno
= seqno
- 1;
2092 if (dev_priv
->last_seqno
== 0)
2093 dev_priv
->last_seqno
--;
2099 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
2101 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2103 /* reserve 0 for non-seqno */
2104 if (dev_priv
->next_seqno
== 0) {
2105 int ret
= i915_gem_init_seqno(dev
, 0);
2109 dev_priv
->next_seqno
= 1;
2112 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2116 int __i915_add_request(struct intel_ring_buffer
*ring
,
2117 struct drm_file
*file
,
2118 struct drm_i915_gem_object
*obj
,
2121 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
2122 struct drm_i915_gem_request
*request
;
2123 u32 request_ring_position
, request_start
;
2127 request_start
= intel_ring_get_tail(ring
);
2129 * Emit any outstanding flushes - execbuf can fail to emit the flush
2130 * after having emitted the batchbuffer command. Hence we need to fix
2131 * things up similar to emitting the lazy request. The difference here
2132 * is that the flush _must_ happen before the next request, no matter
2135 ret
= intel_ring_flush_all_caches(ring
);
2139 request
= ring
->preallocated_lazy_request
;
2140 if (WARN_ON(request
== NULL
))
2143 /* Record the position of the start of the request so that
2144 * should we detect the updated seqno part-way through the
2145 * GPU processing the request, we never over-estimate the
2146 * position of the head.
2148 request_ring_position
= intel_ring_get_tail(ring
);
2150 ret
= ring
->add_request(ring
);
2154 request
->seqno
= intel_ring_get_seqno(ring
);
2155 request
->ring
= ring
;
2156 request
->head
= request_start
;
2157 request
->tail
= request_ring_position
;
2159 /* Whilst this request exists, batch_obj will be on the
2160 * active_list, and so will hold the active reference. Only when this
2161 * request is retired will the the batch_obj be moved onto the
2162 * inactive_list and lose its active reference. Hence we do not need
2163 * to explicitly hold another reference here.
2165 request
->batch_obj
= obj
;
2167 /* Hold a reference to the current context so that we can inspect
2168 * it later in case a hangcheck error event fires.
2170 request
->ctx
= ring
->last_context
;
2172 i915_gem_context_reference(request
->ctx
);
2174 request
->emitted_jiffies
= jiffies
;
2175 was_empty
= list_empty(&ring
->request_list
);
2176 list_add_tail(&request
->list
, &ring
->request_list
);
2177 request
->file_priv
= NULL
;
2180 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2182 spin_lock(&file_priv
->mm
.lock
);
2183 request
->file_priv
= file_priv
;
2184 list_add_tail(&request
->client_list
,
2185 &file_priv
->mm
.request_list
);
2186 spin_unlock(&file_priv
->mm
.lock
);
2189 trace_i915_gem_request_add(ring
, request
->seqno
);
2190 ring
->outstanding_lazy_seqno
= 0;
2191 ring
->preallocated_lazy_request
= NULL
;
2193 if (!dev_priv
->ums
.mm_suspended
) {
2194 i915_queue_hangcheck(ring
->dev
);
2197 cancel_delayed_work_sync(&dev_priv
->mm
.idle_work
);
2198 queue_delayed_work(dev_priv
->wq
,
2199 &dev_priv
->mm
.retire_work
,
2200 round_jiffies_up_relative(HZ
));
2201 intel_mark_busy(dev_priv
->dev
);
2206 *out_seqno
= request
->seqno
;
2211 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2213 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2218 spin_lock(&file_priv
->mm
.lock
);
2219 list_del(&request
->client_list
);
2220 request
->file_priv
= NULL
;
2221 spin_unlock(&file_priv
->mm
.lock
);
2224 static bool i915_head_inside_object(u32 acthd
, struct drm_i915_gem_object
*obj
,
2225 struct i915_address_space
*vm
)
2227 if (acthd
>= i915_gem_obj_offset(obj
, vm
) &&
2228 acthd
< i915_gem_obj_offset(obj
, vm
) + obj
->base
.size
)
2234 static bool i915_head_inside_request(const u32 acthd_unmasked
,
2235 const u32 request_start
,
2236 const u32 request_end
)
2238 const u32 acthd
= acthd_unmasked
& HEAD_ADDR
;
2240 if (request_start
< request_end
) {
2241 if (acthd
>= request_start
&& acthd
< request_end
)
2243 } else if (request_start
> request_end
) {
2244 if (acthd
>= request_start
|| acthd
< request_end
)
2251 static struct i915_address_space
*
2252 request_to_vm(struct drm_i915_gem_request
*request
)
2254 struct drm_i915_private
*dev_priv
= request
->ring
->dev
->dev_private
;
2255 struct i915_address_space
*vm
;
2257 vm
= &dev_priv
->gtt
.base
;
2262 static bool i915_request_guilty(struct drm_i915_gem_request
*request
,
2263 const u32 acthd
, bool *inside
)
2265 /* There is a possibility that unmasked head address
2266 * pointing inside the ring, matches the batch_obj address range.
2267 * However this is extremely unlikely.
2269 if (request
->batch_obj
) {
2270 if (i915_head_inside_object(acthd
, request
->batch_obj
,
2271 request_to_vm(request
))) {
2277 if (i915_head_inside_request(acthd
, request
->head
, request
->tail
)) {
2285 static bool i915_context_is_banned(const struct i915_ctx_hang_stats
*hs
)
2287 const unsigned long elapsed
= get_seconds() - hs
->guilty_ts
;
2292 if (elapsed
<= DRM_I915_CTX_BAN_PERIOD
) {
2293 DRM_ERROR("context hanging too fast, declaring banned!\n");
2300 static void i915_set_reset_status(struct intel_ring_buffer
*ring
,
2301 struct drm_i915_gem_request
*request
,
2304 struct i915_ctx_hang_stats
*hs
= NULL
;
2305 bool inside
, guilty
;
2306 unsigned long offset
= 0;
2308 /* Innocent until proven guilty */
2311 if (request
->batch_obj
)
2312 offset
= i915_gem_obj_offset(request
->batch_obj
,
2313 request_to_vm(request
));
2315 if (ring
->hangcheck
.action
!= HANGCHECK_WAIT
&&
2316 i915_request_guilty(request
, acthd
, &inside
)) {
2317 DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n",
2319 inside
? "inside" : "flushing",
2321 request
->ctx
? request
->ctx
->id
: 0,
2327 /* If contexts are disabled or this is the default context, use
2328 * file_priv->reset_state
2330 if (request
->ctx
&& request
->ctx
->id
!= DEFAULT_CONTEXT_ID
)
2331 hs
= &request
->ctx
->hang_stats
;
2332 else if (request
->file_priv
)
2333 hs
= &request
->file_priv
->hang_stats
;
2337 hs
->banned
= i915_context_is_banned(hs
);
2339 hs
->guilty_ts
= get_seconds();
2341 hs
->batch_pending
++;
2346 static void i915_gem_free_request(struct drm_i915_gem_request
*request
)
2348 list_del(&request
->list
);
2349 i915_gem_request_remove_from_client(request
);
2352 i915_gem_context_unreference(request
->ctx
);
2357 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
2358 struct intel_ring_buffer
*ring
)
2360 u32 completed_seqno
;
2363 acthd
= intel_ring_get_active_head(ring
);
2364 completed_seqno
= ring
->get_seqno(ring
, false);
2366 while (!list_empty(&ring
->request_list
)) {
2367 struct drm_i915_gem_request
*request
;
2369 request
= list_first_entry(&ring
->request_list
,
2370 struct drm_i915_gem_request
,
2373 if (request
->seqno
> completed_seqno
)
2374 i915_set_reset_status(ring
, request
, acthd
);
2376 i915_gem_free_request(request
);
2379 while (!list_empty(&ring
->active_list
)) {
2380 struct drm_i915_gem_object
*obj
;
2382 obj
= list_first_entry(&ring
->active_list
,
2383 struct drm_i915_gem_object
,
2386 i915_gem_object_move_to_inactive(obj
);
2390 void i915_gem_restore_fences(struct drm_device
*dev
)
2392 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2395 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2396 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2399 * Commit delayed tiling changes if we have an object still
2400 * attached to the fence, otherwise just clear the fence.
2403 i915_gem_object_update_fence(reg
->obj
, reg
,
2404 reg
->obj
->tiling_mode
);
2406 i915_gem_write_fence(dev
, i
, NULL
);
2411 void i915_gem_reset(struct drm_device
*dev
)
2413 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2414 struct intel_ring_buffer
*ring
;
2417 for_each_ring(ring
, dev_priv
, i
)
2418 i915_gem_reset_ring_lists(dev_priv
, ring
);
2420 i915_gem_cleanup_ringbuffer(dev
);
2422 i915_gem_restore_fences(dev
);
2426 * This function clears the request list as sequence numbers are passed.
2429 i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
)
2433 if (list_empty(&ring
->request_list
))
2436 WARN_ON(i915_verify_lists(ring
->dev
));
2438 seqno
= ring
->get_seqno(ring
, true);
2440 while (!list_empty(&ring
->request_list
)) {
2441 struct drm_i915_gem_request
*request
;
2443 request
= list_first_entry(&ring
->request_list
,
2444 struct drm_i915_gem_request
,
2447 if (!i915_seqno_passed(seqno
, request
->seqno
))
2450 trace_i915_gem_request_retire(ring
, request
->seqno
);
2451 /* We know the GPU must have read the request to have
2452 * sent us the seqno + interrupt, so use the position
2453 * of tail of the request to update the last known position
2456 ring
->last_retired_head
= request
->tail
;
2458 i915_gem_free_request(request
);
2461 /* Move any buffers on the active list that are no longer referenced
2462 * by the ringbuffer to the flushing/inactive lists as appropriate.
2464 while (!list_empty(&ring
->active_list
)) {
2465 struct drm_i915_gem_object
*obj
;
2467 obj
= list_first_entry(&ring
->active_list
,
2468 struct drm_i915_gem_object
,
2471 if (!i915_seqno_passed(seqno
, obj
->last_read_seqno
))
2474 i915_gem_object_move_to_inactive(obj
);
2477 if (unlikely(ring
->trace_irq_seqno
&&
2478 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
2479 ring
->irq_put(ring
);
2480 ring
->trace_irq_seqno
= 0;
2483 WARN_ON(i915_verify_lists(ring
->dev
));
2487 i915_gem_retire_requests(struct drm_device
*dev
)
2489 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2490 struct intel_ring_buffer
*ring
;
2494 for_each_ring(ring
, dev_priv
, i
) {
2495 i915_gem_retire_requests_ring(ring
);
2496 idle
&= list_empty(&ring
->request_list
);
2500 mod_delayed_work(dev_priv
->wq
,
2501 &dev_priv
->mm
.idle_work
,
2502 msecs_to_jiffies(100));
2508 i915_gem_retire_work_handler(struct work_struct
*work
)
2510 struct drm_i915_private
*dev_priv
=
2511 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
2512 struct drm_device
*dev
= dev_priv
->dev
;
2515 /* Come back later if the device is busy... */
2517 if (mutex_trylock(&dev
->struct_mutex
)) {
2518 idle
= i915_gem_retire_requests(dev
);
2519 mutex_unlock(&dev
->struct_mutex
);
2522 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2523 round_jiffies_up_relative(HZ
));
2527 i915_gem_idle_work_handler(struct work_struct
*work
)
2529 struct drm_i915_private
*dev_priv
=
2530 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
2532 intel_mark_idle(dev_priv
->dev
);
2536 * Ensures that an object will eventually get non-busy by flushing any required
2537 * write domains, emitting any outstanding lazy request and retiring and
2538 * completed requests.
2541 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2546 ret
= i915_gem_check_olr(obj
->ring
, obj
->last_read_seqno
);
2550 i915_gem_retire_requests_ring(obj
->ring
);
2557 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2558 * @DRM_IOCTL_ARGS: standard ioctl arguments
2560 * Returns 0 if successful, else an error is returned with the remaining time in
2561 * the timeout parameter.
2562 * -ETIME: object is still busy after timeout
2563 * -ERESTARTSYS: signal interrupted the wait
2564 * -ENONENT: object doesn't exist
2565 * Also possible, but rare:
2566 * -EAGAIN: GPU wedged
2568 * -ENODEV: Internal IRQ fail
2569 * -E?: The add request failed
2571 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2572 * non-zero timeout parameter the wait ioctl will wait for the given number of
2573 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2574 * without holding struct_mutex the object may become re-busied before this
2575 * function completes. A similar but shorter * race condition exists in the busy
2579 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2581 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2582 struct drm_i915_gem_wait
*args
= data
;
2583 struct drm_i915_gem_object
*obj
;
2584 struct intel_ring_buffer
*ring
= NULL
;
2585 struct timespec timeout_stack
, *timeout
= NULL
;
2586 unsigned reset_counter
;
2590 if (args
->timeout_ns
>= 0) {
2591 timeout_stack
= ns_to_timespec(args
->timeout_ns
);
2592 timeout
= &timeout_stack
;
2595 ret
= i915_mutex_lock_interruptible(dev
);
2599 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2600 if (&obj
->base
== NULL
) {
2601 mutex_unlock(&dev
->struct_mutex
);
2605 /* Need to make sure the object gets inactive eventually. */
2606 ret
= i915_gem_object_flush_active(obj
);
2611 seqno
= obj
->last_read_seqno
;
2618 /* Do this after OLR check to make sure we make forward progress polling
2619 * on this IOCTL with a 0 timeout (like busy ioctl)
2621 if (!args
->timeout_ns
) {
2626 drm_gem_object_unreference(&obj
->base
);
2627 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
2628 mutex_unlock(&dev
->struct_mutex
);
2630 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, timeout
, file
->driver_priv
);
2632 args
->timeout_ns
= timespec_to_ns(timeout
);
2636 drm_gem_object_unreference(&obj
->base
);
2637 mutex_unlock(&dev
->struct_mutex
);
2642 * i915_gem_object_sync - sync an object to a ring.
2644 * @obj: object which may be in use on another ring.
2645 * @to: ring we wish to use the object on. May be NULL.
2647 * This code is meant to abstract object synchronization with the GPU.
2648 * Calling with NULL implies synchronizing the object with the CPU
2649 * rather than a particular GPU ring.
2651 * Returns 0 if successful, else propagates up the lower layer error.
2654 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2655 struct intel_ring_buffer
*to
)
2657 struct intel_ring_buffer
*from
= obj
->ring
;
2661 if (from
== NULL
|| to
== from
)
2664 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2665 return i915_gem_object_wait_rendering(obj
, false);
2667 idx
= intel_ring_sync_index(from
, to
);
2669 seqno
= obj
->last_read_seqno
;
2670 if (seqno
<= from
->sync_seqno
[idx
])
2673 ret
= i915_gem_check_olr(obj
->ring
, seqno
);
2677 trace_i915_gem_ring_sync_to(from
, to
, seqno
);
2678 ret
= to
->sync_to(to
, from
, seqno
);
2680 /* We use last_read_seqno because sync_to()
2681 * might have just caused seqno wrap under
2684 from
->sync_seqno
[idx
] = obj
->last_read_seqno
;
2689 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
2691 u32 old_write_domain
, old_read_domains
;
2693 /* Force a pagefault for domain tracking on next user access */
2694 i915_gem_release_mmap(obj
);
2696 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2699 /* Wait for any direct GTT access to complete */
2702 old_read_domains
= obj
->base
.read_domains
;
2703 old_write_domain
= obj
->base
.write_domain
;
2705 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2706 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2708 trace_i915_gem_object_change_domain(obj
,
2713 int i915_vma_unbind(struct i915_vma
*vma
)
2715 struct drm_i915_gem_object
*obj
= vma
->obj
;
2716 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2719 /* For now we only ever use 1 vma per object */
2720 WARN_ON(!list_is_singular(&obj
->vma_list
));
2722 if (list_empty(&vma
->vma_link
))
2725 if (!drm_mm_node_allocated(&vma
->node
)) {
2726 i915_gem_vma_destroy(vma
);
2734 BUG_ON(obj
->pages
== NULL
);
2736 ret
= i915_gem_object_finish_gpu(obj
);
2739 /* Continue on if we fail due to EIO, the GPU is hung so we
2740 * should be safe and we need to cleanup or else we might
2741 * cause memory corruption through use-after-free.
2744 i915_gem_object_finish_gtt(obj
);
2746 /* release the fence reg _after_ flushing */
2747 ret
= i915_gem_object_put_fence(obj
);
2751 trace_i915_vma_unbind(vma
);
2753 if (obj
->has_global_gtt_mapping
)
2754 i915_gem_gtt_unbind_object(obj
);
2755 if (obj
->has_aliasing_ppgtt_mapping
) {
2756 i915_ppgtt_unbind_object(dev_priv
->mm
.aliasing_ppgtt
, obj
);
2757 obj
->has_aliasing_ppgtt_mapping
= 0;
2759 i915_gem_gtt_finish_object(obj
);
2761 list_del(&vma
->mm_list
);
2762 /* Avoid an unnecessary call to unbind on rebind. */
2763 if (i915_is_ggtt(vma
->vm
))
2764 obj
->map_and_fenceable
= true;
2766 drm_mm_remove_node(&vma
->node
);
2767 i915_gem_vma_destroy(vma
);
2769 /* Since the unbound list is global, only move to that list if
2770 * no more VMAs exist. */
2771 if (list_empty(&obj
->vma_list
))
2772 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2774 /* And finally now the object is completely decoupled from this vma,
2775 * we can drop its hold on the backing storage and allow it to be
2776 * reaped by the shrinker.
2778 i915_gem_object_unpin_pages(obj
);
2784 * Unbinds an object from the global GTT aperture.
2787 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
2789 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2790 struct i915_address_space
*ggtt
= &dev_priv
->gtt
.base
;
2792 if (!i915_gem_obj_ggtt_bound(obj
))
2798 BUG_ON(obj
->pages
== NULL
);
2800 return i915_vma_unbind(i915_gem_obj_to_vma(obj
, ggtt
));
2803 int i915_gpu_idle(struct drm_device
*dev
)
2805 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2806 struct intel_ring_buffer
*ring
;
2809 /* Flush everything onto the inactive list. */
2810 for_each_ring(ring
, dev_priv
, i
) {
2811 ret
= i915_switch_context(ring
, NULL
, DEFAULT_CONTEXT_ID
);
2815 ret
= intel_ring_idle(ring
);
2823 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
2824 struct drm_i915_gem_object
*obj
)
2826 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2828 int fence_pitch_shift
;
2830 if (INTEL_INFO(dev
)->gen
>= 6) {
2831 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
2832 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2834 fence_reg
= FENCE_REG_965_0
;
2835 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
2838 fence_reg
+= reg
* 8;
2840 /* To w/a incoherency with non-atomic 64-bit register updates,
2841 * we split the 64-bit update into two 32-bit writes. In order
2842 * for a partial fence not to be evaluated between writes, we
2843 * precede the update with write to turn off the fence register,
2844 * and only enable the fence as the last step.
2846 * For extra levels of paranoia, we make sure each step lands
2847 * before applying the next step.
2849 I915_WRITE(fence_reg
, 0);
2850 POSTING_READ(fence_reg
);
2853 u32 size
= i915_gem_obj_ggtt_size(obj
);
2856 val
= (uint64_t)((i915_gem_obj_ggtt_offset(obj
) + size
- 4096) &
2858 val
|= i915_gem_obj_ggtt_offset(obj
) & 0xfffff000;
2859 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
2860 if (obj
->tiling_mode
== I915_TILING_Y
)
2861 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2862 val
|= I965_FENCE_REG_VALID
;
2864 I915_WRITE(fence_reg
+ 4, val
>> 32);
2865 POSTING_READ(fence_reg
+ 4);
2867 I915_WRITE(fence_reg
+ 0, val
);
2868 POSTING_READ(fence_reg
);
2870 I915_WRITE(fence_reg
+ 4, 0);
2871 POSTING_READ(fence_reg
+ 4);
2875 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
2876 struct drm_i915_gem_object
*obj
)
2878 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2882 u32 size
= i915_gem_obj_ggtt_size(obj
);
2886 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I915_FENCE_START_MASK
) ||
2887 (size
& -size
) != size
||
2888 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
2889 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2890 i915_gem_obj_ggtt_offset(obj
), obj
->map_and_fenceable
, size
);
2892 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2897 /* Note: pitch better be a power of two tile widths */
2898 pitch_val
= obj
->stride
/ tile_width
;
2899 pitch_val
= ffs(pitch_val
) - 1;
2901 val
= i915_gem_obj_ggtt_offset(obj
);
2902 if (obj
->tiling_mode
== I915_TILING_Y
)
2903 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2904 val
|= I915_FENCE_SIZE_BITS(size
);
2905 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2906 val
|= I830_FENCE_REG_VALID
;
2911 reg
= FENCE_REG_830_0
+ reg
* 4;
2913 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
2915 I915_WRITE(reg
, val
);
2919 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
2920 struct drm_i915_gem_object
*obj
)
2922 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2926 u32 size
= i915_gem_obj_ggtt_size(obj
);
2929 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I830_FENCE_START_MASK
) ||
2930 (size
& -size
) != size
||
2931 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
2932 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2933 i915_gem_obj_ggtt_offset(obj
), size
);
2935 pitch_val
= obj
->stride
/ 128;
2936 pitch_val
= ffs(pitch_val
) - 1;
2938 val
= i915_gem_obj_ggtt_offset(obj
);
2939 if (obj
->tiling_mode
== I915_TILING_Y
)
2940 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2941 val
|= I830_FENCE_SIZE_BITS(size
);
2942 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2943 val
|= I830_FENCE_REG_VALID
;
2947 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
2948 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
2951 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
2953 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
2956 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
2957 struct drm_i915_gem_object
*obj
)
2959 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2961 /* Ensure that all CPU reads are completed before installing a fence
2962 * and all writes before removing the fence.
2964 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
2967 WARN(obj
&& (!obj
->stride
|| !obj
->tiling_mode
),
2968 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
2969 obj
->stride
, obj
->tiling_mode
);
2971 switch (INTEL_INFO(dev
)->gen
) {
2976 case 4: i965_write_fence_reg(dev
, reg
, obj
); break;
2977 case 3: i915_write_fence_reg(dev
, reg
, obj
); break;
2978 case 2: i830_write_fence_reg(dev
, reg
, obj
); break;
2982 /* And similarly be paranoid that no direct access to this region
2983 * is reordered to before the fence is installed.
2985 if (i915_gem_object_needs_mb(obj
))
2989 static inline int fence_number(struct drm_i915_private
*dev_priv
,
2990 struct drm_i915_fence_reg
*fence
)
2992 return fence
- dev_priv
->fence_regs
;
2995 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
2996 struct drm_i915_fence_reg
*fence
,
2999 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3000 int reg
= fence_number(dev_priv
, fence
);
3002 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
3005 obj
->fence_reg
= reg
;
3007 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
3009 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3011 list_del_init(&fence
->lru_list
);
3013 obj
->fence_dirty
= false;
3017 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
3019 if (obj
->last_fenced_seqno
) {
3020 int ret
= i915_wait_seqno(obj
->ring
, obj
->last_fenced_seqno
);
3024 obj
->last_fenced_seqno
= 0;
3027 obj
->fenced_gpu_access
= false;
3032 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
3034 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3035 struct drm_i915_fence_reg
*fence
;
3038 ret
= i915_gem_object_wait_fence(obj
);
3042 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
3045 fence
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3047 i915_gem_object_fence_lost(obj
);
3048 i915_gem_object_update_fence(obj
, fence
, false);
3053 static struct drm_i915_fence_reg
*
3054 i915_find_fence_reg(struct drm_device
*dev
)
3056 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3057 struct drm_i915_fence_reg
*reg
, *avail
;
3060 /* First try to find a free reg */
3062 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
3063 reg
= &dev_priv
->fence_regs
[i
];
3067 if (!reg
->pin_count
)
3074 /* None available, try to steal one or wait for a user to finish */
3075 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
3086 * i915_gem_object_get_fence - set up fencing for an object
3087 * @obj: object to map through a fence reg
3089 * When mapping objects through the GTT, userspace wants to be able to write
3090 * to them without having to worry about swizzling if the object is tiled.
3091 * This function walks the fence regs looking for a free one for @obj,
3092 * stealing one if it can't find any.
3094 * It then sets up the reg based on the object's properties: address, pitch
3095 * and tiling format.
3097 * For an untiled surface, this removes any existing fence.
3100 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
3102 struct drm_device
*dev
= obj
->base
.dev
;
3103 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3104 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
3105 struct drm_i915_fence_reg
*reg
;
3108 /* Have we updated the tiling parameters upon the object and so
3109 * will need to serialise the write to the associated fence register?
3111 if (obj
->fence_dirty
) {
3112 ret
= i915_gem_object_wait_fence(obj
);
3117 /* Just update our place in the LRU if our fence is getting reused. */
3118 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
3119 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3120 if (!obj
->fence_dirty
) {
3121 list_move_tail(®
->lru_list
,
3122 &dev_priv
->mm
.fence_list
);
3125 } else if (enable
) {
3126 reg
= i915_find_fence_reg(dev
);
3131 struct drm_i915_gem_object
*old
= reg
->obj
;
3133 ret
= i915_gem_object_wait_fence(old
);
3137 i915_gem_object_fence_lost(old
);
3142 i915_gem_object_update_fence(obj
, reg
, enable
);
3147 static bool i915_gem_valid_gtt_space(struct drm_device
*dev
,
3148 struct drm_mm_node
*gtt_space
,
3149 unsigned long cache_level
)
3151 struct drm_mm_node
*other
;
3153 /* On non-LLC machines we have to be careful when putting differing
3154 * types of snoopable memory together to avoid the prefetcher
3155 * crossing memory domains and dying.
3160 if (!drm_mm_node_allocated(gtt_space
))
3163 if (list_empty(>t_space
->node_list
))
3166 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3167 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3170 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3171 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3177 static void i915_gem_verify_gtt(struct drm_device
*dev
)
3180 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3181 struct drm_i915_gem_object
*obj
;
3184 list_for_each_entry(obj
, &dev_priv
->mm
.gtt_list
, global_list
) {
3185 if (obj
->gtt_space
== NULL
) {
3186 printk(KERN_ERR
"object found on GTT list with no space reserved\n");
3191 if (obj
->cache_level
!= obj
->gtt_space
->color
) {
3192 printk(KERN_ERR
"object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3193 i915_gem_obj_ggtt_offset(obj
),
3194 i915_gem_obj_ggtt_offset(obj
) + i915_gem_obj_ggtt_size(obj
),
3196 obj
->gtt_space
->color
);
3201 if (!i915_gem_valid_gtt_space(dev
,
3203 obj
->cache_level
)) {
3204 printk(KERN_ERR
"invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3205 i915_gem_obj_ggtt_offset(obj
),
3206 i915_gem_obj_ggtt_offset(obj
) + i915_gem_obj_ggtt_size(obj
),
3218 * Finds free space in the GTT aperture and binds the object there.
3221 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3222 struct i915_address_space
*vm
,
3224 bool map_and_fenceable
,
3227 struct drm_device
*dev
= obj
->base
.dev
;
3228 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3229 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
3231 map_and_fenceable
? dev_priv
->gtt
.mappable_end
: vm
->total
;
3232 struct i915_vma
*vma
;
3235 fence_size
= i915_gem_get_gtt_size(dev
,
3238 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3240 obj
->tiling_mode
, true);
3241 unfenced_alignment
=
3242 i915_gem_get_gtt_alignment(dev
,
3244 obj
->tiling_mode
, false);
3247 alignment
= map_and_fenceable
? fence_alignment
:
3249 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
3250 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
3254 size
= map_and_fenceable
? fence_size
: obj
->base
.size
;
3256 /* If the object is bigger than the entire aperture, reject it early
3257 * before evicting everything in a vain attempt to find space.
3259 if (obj
->base
.size
> gtt_max
) {
3260 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3262 map_and_fenceable
? "mappable" : "total",
3267 ret
= i915_gem_object_get_pages(obj
);
3271 i915_gem_object_pin_pages(obj
);
3273 BUG_ON(!i915_is_ggtt(vm
));
3275 vma
= i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3281 /* For now we only ever use 1 vma per object */
3282 WARN_ON(!list_is_singular(&obj
->vma_list
));
3285 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3287 obj
->cache_level
, 0, gtt_max
,
3288 DRM_MM_SEARCH_DEFAULT
);
3290 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3299 if (WARN_ON(!i915_gem_valid_gtt_space(dev
, &vma
->node
,
3300 obj
->cache_level
))) {
3302 goto err_remove_node
;
3305 ret
= i915_gem_gtt_prepare_object(obj
);
3307 goto err_remove_node
;
3309 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3310 list_add_tail(&vma
->mm_list
, &vm
->inactive_list
);
3312 if (i915_is_ggtt(vm
)) {
3313 bool mappable
, fenceable
;
3315 fenceable
= (vma
->node
.size
== fence_size
&&
3316 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
3318 mappable
= (vma
->node
.start
+ obj
->base
.size
<=
3319 dev_priv
->gtt
.mappable_end
);
3321 obj
->map_and_fenceable
= mappable
&& fenceable
;
3324 WARN_ON(map_and_fenceable
&& !obj
->map_and_fenceable
);
3326 trace_i915_vma_bind(vma
, map_and_fenceable
);
3327 i915_gem_verify_gtt(dev
);
3331 drm_mm_remove_node(&vma
->node
);
3333 i915_gem_vma_destroy(vma
);
3335 i915_gem_object_unpin_pages(obj
);
3340 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3343 /* If we don't have a page list set up, then we're not pinned
3344 * to GPU, and we can ignore the cache flush because it'll happen
3345 * again at bind time.
3347 if (obj
->pages
== NULL
)
3351 * Stolen memory is always coherent with the GPU as it is explicitly
3352 * marked as wc by the system, or the system is cache-coherent.
3357 /* If the GPU is snooping the contents of the CPU cache,
3358 * we do not need to manually clear the CPU cache lines. However,
3359 * the caches are only snooped when the render cache is
3360 * flushed/invalidated. As we always have to emit invalidations
3361 * and flushes when moving into and out of the RENDER domain, correct
3362 * snooping behaviour occurs naturally as the result of our domain
3365 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
3368 trace_i915_gem_object_clflush(obj
);
3369 drm_clflush_sg(obj
->pages
);
3374 /** Flushes the GTT write domain for the object if it's dirty. */
3376 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3378 uint32_t old_write_domain
;
3380 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3383 /* No actual flushing is required for the GTT write domain. Writes
3384 * to it immediately go to main memory as far as we know, so there's
3385 * no chipset flush. It also doesn't land in render cache.
3387 * However, we do have to enforce the order so that all writes through
3388 * the GTT land before any writes to the device, such as updates to
3393 old_write_domain
= obj
->base
.write_domain
;
3394 obj
->base
.write_domain
= 0;
3396 trace_i915_gem_object_change_domain(obj
,
3397 obj
->base
.read_domains
,
3401 /** Flushes the CPU write domain for the object if it's dirty. */
3403 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
,
3406 uint32_t old_write_domain
;
3408 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3411 if (i915_gem_clflush_object(obj
, force
))
3412 i915_gem_chipset_flush(obj
->base
.dev
);
3414 old_write_domain
= obj
->base
.write_domain
;
3415 obj
->base
.write_domain
= 0;
3417 trace_i915_gem_object_change_domain(obj
,
3418 obj
->base
.read_domains
,
3423 * Moves a single object to the GTT read, and possibly write domain.
3425 * This function returns when the move is complete, including waiting on
3429 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3431 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
3432 uint32_t old_write_domain
, old_read_domains
;
3435 /* Not valid to be called on unbound objects. */
3436 if (!i915_gem_obj_bound_any(obj
))
3439 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3442 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3446 i915_gem_object_flush_cpu_write_domain(obj
, false);
3448 /* Serialise direct access to this object with the barriers for
3449 * coherent writes from the GPU, by effectively invalidating the
3450 * GTT domain upon first access.
3452 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3455 old_write_domain
= obj
->base
.write_domain
;
3456 old_read_domains
= obj
->base
.read_domains
;
3458 /* It should now be out of any other write domains, and we can update
3459 * the domain values for our changes.
3461 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3462 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3464 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3465 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3469 trace_i915_gem_object_change_domain(obj
,
3473 /* And bump the LRU for this access */
3474 if (i915_gem_object_is_inactive(obj
)) {
3475 struct i915_vma
*vma
= i915_gem_obj_to_ggtt(obj
);
3477 list_move_tail(&vma
->mm_list
,
3478 &dev_priv
->gtt
.base
.inactive_list
);
3485 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3486 enum i915_cache_level cache_level
)
3488 struct drm_device
*dev
= obj
->base
.dev
;
3489 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3490 struct i915_vma
*vma
;
3493 if (obj
->cache_level
== cache_level
)
3496 if (obj
->pin_count
) {
3497 DRM_DEBUG("can not change the cache level of pinned objects\n");
3501 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
3502 if (!i915_gem_valid_gtt_space(dev
, &vma
->node
, cache_level
)) {
3503 ret
= i915_vma_unbind(vma
);
3511 if (i915_gem_obj_bound_any(obj
)) {
3512 ret
= i915_gem_object_finish_gpu(obj
);
3516 i915_gem_object_finish_gtt(obj
);
3518 /* Before SandyBridge, you could not use tiling or fence
3519 * registers with snooped memory, so relinquish any fences
3520 * currently pointing to our region in the aperture.
3522 if (INTEL_INFO(dev
)->gen
< 6) {
3523 ret
= i915_gem_object_put_fence(obj
);
3528 if (obj
->has_global_gtt_mapping
)
3529 i915_gem_gtt_bind_object(obj
, cache_level
);
3530 if (obj
->has_aliasing_ppgtt_mapping
)
3531 i915_ppgtt_bind_object(dev_priv
->mm
.aliasing_ppgtt
,
3535 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3536 vma
->node
.color
= cache_level
;
3537 obj
->cache_level
= cache_level
;
3539 if (cpu_write_needs_clflush(obj
)) {
3540 u32 old_read_domains
, old_write_domain
;
3542 /* If we're coming from LLC cached, then we haven't
3543 * actually been tracking whether the data is in the
3544 * CPU cache or not, since we only allow one bit set
3545 * in obj->write_domain and have been skipping the clflushes.
3546 * Just set it to the CPU cache for now.
3548 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
3550 old_read_domains
= obj
->base
.read_domains
;
3551 old_write_domain
= obj
->base
.write_domain
;
3553 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3554 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3556 trace_i915_gem_object_change_domain(obj
,
3561 i915_gem_verify_gtt(dev
);
3565 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3566 struct drm_file
*file
)
3568 struct drm_i915_gem_caching
*args
= data
;
3569 struct drm_i915_gem_object
*obj
;
3572 ret
= i915_mutex_lock_interruptible(dev
);
3576 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3577 if (&obj
->base
== NULL
) {
3582 switch (obj
->cache_level
) {
3583 case I915_CACHE_LLC
:
3584 case I915_CACHE_L3_LLC
:
3585 args
->caching
= I915_CACHING_CACHED
;
3589 args
->caching
= I915_CACHING_DISPLAY
;
3593 args
->caching
= I915_CACHING_NONE
;
3597 drm_gem_object_unreference(&obj
->base
);
3599 mutex_unlock(&dev
->struct_mutex
);
3603 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3604 struct drm_file
*file
)
3606 struct drm_i915_gem_caching
*args
= data
;
3607 struct drm_i915_gem_object
*obj
;
3608 enum i915_cache_level level
;
3611 switch (args
->caching
) {
3612 case I915_CACHING_NONE
:
3613 level
= I915_CACHE_NONE
;
3615 case I915_CACHING_CACHED
:
3616 level
= I915_CACHE_LLC
;
3618 case I915_CACHING_DISPLAY
:
3619 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
3625 ret
= i915_mutex_lock_interruptible(dev
);
3629 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3630 if (&obj
->base
== NULL
) {
3635 ret
= i915_gem_object_set_cache_level(obj
, level
);
3637 drm_gem_object_unreference(&obj
->base
);
3639 mutex_unlock(&dev
->struct_mutex
);
3643 static bool is_pin_display(struct drm_i915_gem_object
*obj
)
3645 /* There are 3 sources that pin objects:
3646 * 1. The display engine (scanouts, sprites, cursors);
3647 * 2. Reservations for execbuffer;
3650 * We can ignore reservations as we hold the struct_mutex and
3651 * are only called outside of the reservation path. The user
3652 * can only increment pin_count once, and so if after
3653 * subtracting the potential reference by the user, any pin_count
3654 * remains, it must be due to another use by the display engine.
3656 return obj
->pin_count
- !!obj
->user_pin_count
;
3660 * Prepare buffer for display plane (scanout, cursors, etc).
3661 * Can be called from an uninterruptible phase (modesetting) and allows
3662 * any flushes to be pipelined (for pageflips).
3665 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3667 struct intel_ring_buffer
*pipelined
)
3669 u32 old_read_domains
, old_write_domain
;
3672 if (pipelined
!= obj
->ring
) {
3673 ret
= i915_gem_object_sync(obj
, pipelined
);
3678 /* Mark the pin_display early so that we account for the
3679 * display coherency whilst setting up the cache domains.
3681 obj
->pin_display
= true;
3683 /* The display engine is not coherent with the LLC cache on gen6. As
3684 * a result, we make sure that the pinning that is about to occur is
3685 * done with uncached PTEs. This is lowest common denominator for all
3688 * However for gen6+, we could do better by using the GFDT bit instead
3689 * of uncaching, which would allow us to flush all the LLC-cached data
3690 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3692 ret
= i915_gem_object_set_cache_level(obj
,
3693 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
3695 goto err_unpin_display
;
3697 /* As the user may map the buffer once pinned in the display plane
3698 * (e.g. libkms for the bootup splash), we have to ensure that we
3699 * always use map_and_fenceable for all scanout buffers.
3701 ret
= i915_gem_obj_ggtt_pin(obj
, alignment
, true, false);
3703 goto err_unpin_display
;
3705 i915_gem_object_flush_cpu_write_domain(obj
, true);
3707 old_write_domain
= obj
->base
.write_domain
;
3708 old_read_domains
= obj
->base
.read_domains
;
3710 /* It should now be out of any other write domains, and we can update
3711 * the domain values for our changes.
3713 obj
->base
.write_domain
= 0;
3714 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3716 trace_i915_gem_object_change_domain(obj
,
3723 obj
->pin_display
= is_pin_display(obj
);
3728 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
)
3730 i915_gem_object_unpin(obj
);
3731 obj
->pin_display
= is_pin_display(obj
);
3735 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
3739 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
3742 ret
= i915_gem_object_wait_rendering(obj
, false);
3746 /* Ensure that we invalidate the GPU's caches and TLBs. */
3747 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
3752 * Moves a single object to the CPU read, and possibly write domain.
3754 * This function returns when the move is complete, including waiting on
3758 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3760 uint32_t old_write_domain
, old_read_domains
;
3763 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3766 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3770 i915_gem_object_flush_gtt_write_domain(obj
);
3772 old_write_domain
= obj
->base
.write_domain
;
3773 old_read_domains
= obj
->base
.read_domains
;
3775 /* Flush the CPU cache if it's still invalid. */
3776 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3777 i915_gem_clflush_object(obj
, false);
3779 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3782 /* It should now be out of any other write domains, and we can update
3783 * the domain values for our changes.
3785 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3787 /* If we're writing through the CPU, then the GPU read domains will
3788 * need to be invalidated at next use.
3791 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3792 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3795 trace_i915_gem_object_change_domain(obj
,
3802 /* Throttle our rendering by waiting until the ring has completed our requests
3803 * emitted over 20 msec ago.
3805 * Note that if we were to use the current jiffies each time around the loop,
3806 * we wouldn't escape the function with any frames outstanding if the time to
3807 * render a frame was over 20ms.
3809 * This should get us reasonable parallelism between CPU and GPU but also
3810 * relatively low latency when blocking on a particular request to finish.
3813 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3815 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3816 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3817 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3818 struct drm_i915_gem_request
*request
;
3819 struct intel_ring_buffer
*ring
= NULL
;
3820 unsigned reset_counter
;
3824 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
3828 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
3832 spin_lock(&file_priv
->mm
.lock
);
3833 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3834 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3837 ring
= request
->ring
;
3838 seqno
= request
->seqno
;
3840 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3841 spin_unlock(&file_priv
->mm
.lock
);
3846 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, NULL
, NULL
);
3848 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3854 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3855 struct i915_address_space
*vm
,
3857 bool map_and_fenceable
,
3860 struct i915_vma
*vma
;
3863 if (WARN_ON(obj
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
3866 WARN_ON(map_and_fenceable
&& !i915_is_ggtt(vm
));
3868 vma
= i915_gem_obj_to_vma(obj
, vm
);
3872 vma
->node
.start
& (alignment
- 1)) ||
3873 (map_and_fenceable
&& !obj
->map_and_fenceable
)) {
3874 WARN(obj
->pin_count
,
3875 "bo is already pinned with incorrect alignment:"
3876 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3877 " obj->map_and_fenceable=%d\n",
3878 i915_gem_obj_offset(obj
, vm
), alignment
,
3880 obj
->map_and_fenceable
);
3881 ret
= i915_vma_unbind(vma
);
3887 if (!i915_gem_obj_bound(obj
, vm
)) {
3888 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3890 ret
= i915_gem_object_bind_to_vm(obj
, vm
, alignment
,
3896 if (!dev_priv
->mm
.aliasing_ppgtt
)
3897 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3900 if (!obj
->has_global_gtt_mapping
&& map_and_fenceable
)
3901 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3904 obj
->pin_mappable
|= map_and_fenceable
;
3910 i915_gem_object_unpin(struct drm_i915_gem_object
*obj
)
3912 BUG_ON(obj
->pin_count
== 0);
3913 BUG_ON(!i915_gem_obj_bound_any(obj
));
3915 if (--obj
->pin_count
== 0)
3916 obj
->pin_mappable
= false;
3920 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3921 struct drm_file
*file
)
3923 struct drm_i915_gem_pin
*args
= data
;
3924 struct drm_i915_gem_object
*obj
;
3927 ret
= i915_mutex_lock_interruptible(dev
);
3931 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3932 if (&obj
->base
== NULL
) {
3937 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3938 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3943 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3944 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3950 if (obj
->user_pin_count
== ULONG_MAX
) {
3955 if (obj
->user_pin_count
== 0) {
3956 ret
= i915_gem_obj_ggtt_pin(obj
, args
->alignment
, true, false);
3961 obj
->user_pin_count
++;
3962 obj
->pin_filp
= file
;
3964 args
->offset
= i915_gem_obj_ggtt_offset(obj
);
3966 drm_gem_object_unreference(&obj
->base
);
3968 mutex_unlock(&dev
->struct_mutex
);
3973 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3974 struct drm_file
*file
)
3976 struct drm_i915_gem_pin
*args
= data
;
3977 struct drm_i915_gem_object
*obj
;
3980 ret
= i915_mutex_lock_interruptible(dev
);
3984 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3985 if (&obj
->base
== NULL
) {
3990 if (obj
->pin_filp
!= file
) {
3991 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3996 obj
->user_pin_count
--;
3997 if (obj
->user_pin_count
== 0) {
3998 obj
->pin_filp
= NULL
;
3999 i915_gem_object_unpin(obj
);
4003 drm_gem_object_unreference(&obj
->base
);
4005 mutex_unlock(&dev
->struct_mutex
);
4010 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4011 struct drm_file
*file
)
4013 struct drm_i915_gem_busy
*args
= data
;
4014 struct drm_i915_gem_object
*obj
;
4017 ret
= i915_mutex_lock_interruptible(dev
);
4021 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4022 if (&obj
->base
== NULL
) {
4027 /* Count all active objects as busy, even if they are currently not used
4028 * by the gpu. Users of this interface expect objects to eventually
4029 * become non-busy without any further actions, therefore emit any
4030 * necessary flushes here.
4032 ret
= i915_gem_object_flush_active(obj
);
4034 args
->busy
= obj
->active
;
4036 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
4037 args
->busy
|= intel_ring_flag(obj
->ring
) << 16;
4040 drm_gem_object_unreference(&obj
->base
);
4042 mutex_unlock(&dev
->struct_mutex
);
4047 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4048 struct drm_file
*file_priv
)
4050 return i915_gem_ring_throttle(dev
, file_priv
);
4054 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4055 struct drm_file
*file_priv
)
4057 struct drm_i915_gem_madvise
*args
= data
;
4058 struct drm_i915_gem_object
*obj
;
4061 switch (args
->madv
) {
4062 case I915_MADV_DONTNEED
:
4063 case I915_MADV_WILLNEED
:
4069 ret
= i915_mutex_lock_interruptible(dev
);
4073 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
4074 if (&obj
->base
== NULL
) {
4079 if (obj
->pin_count
) {
4084 if (obj
->madv
!= __I915_MADV_PURGED
)
4085 obj
->madv
= args
->madv
;
4087 /* if the object is no longer attached, discard its backing storage */
4088 if (i915_gem_object_is_purgeable(obj
) && obj
->pages
== NULL
)
4089 i915_gem_object_truncate(obj
);
4091 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4094 drm_gem_object_unreference(&obj
->base
);
4096 mutex_unlock(&dev
->struct_mutex
);
4100 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4101 const struct drm_i915_gem_object_ops
*ops
)
4103 INIT_LIST_HEAD(&obj
->global_list
);
4104 INIT_LIST_HEAD(&obj
->ring_list
);
4105 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4106 INIT_LIST_HEAD(&obj
->vma_list
);
4110 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4111 obj
->madv
= I915_MADV_WILLNEED
;
4112 /* Avoid an unnecessary call to unbind on the first bind. */
4113 obj
->map_and_fenceable
= true;
4115 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4118 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4119 .get_pages
= i915_gem_object_get_pages_gtt
,
4120 .put_pages
= i915_gem_object_put_pages_gtt
,
4123 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
4126 struct drm_i915_gem_object
*obj
;
4127 struct address_space
*mapping
;
4130 obj
= i915_gem_object_alloc(dev
);
4134 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4135 i915_gem_object_free(obj
);
4139 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4140 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4141 /* 965gm cannot relocate objects above 4GiB. */
4142 mask
&= ~__GFP_HIGHMEM
;
4143 mask
|= __GFP_DMA32
;
4146 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4147 mapping_set_gfp_mask(mapping
, mask
);
4149 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4151 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4152 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4155 /* On some devices, we can have the GPU use the LLC (the CPU
4156 * cache) for about a 10% performance improvement
4157 * compared to uncached. Graphics requests other than
4158 * display scanout are coherent with the CPU in
4159 * accessing this cache. This means in this mode we
4160 * don't need to clflush on the CPU side, and on the
4161 * GPU side we only need to flush internal caches to
4162 * get data visible to the CPU.
4164 * However, we maintain the display planes as UC, and so
4165 * need to rebind when first used as such.
4167 obj
->cache_level
= I915_CACHE_LLC
;
4169 obj
->cache_level
= I915_CACHE_NONE
;
4171 trace_i915_gem_object_create(obj
);
4176 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4178 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4179 struct drm_device
*dev
= obj
->base
.dev
;
4180 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4181 struct i915_vma
*vma
, *next
;
4183 intel_runtime_pm_get(dev_priv
);
4185 trace_i915_gem_object_destroy(obj
);
4188 i915_gem_detach_phys_object(dev
, obj
);
4191 /* NB: 0 or 1 elements */
4192 WARN_ON(!list_empty(&obj
->vma_list
) &&
4193 !list_is_singular(&obj
->vma_list
));
4194 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4195 int ret
= i915_vma_unbind(vma
);
4196 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4197 bool was_interruptible
;
4199 was_interruptible
= dev_priv
->mm
.interruptible
;
4200 dev_priv
->mm
.interruptible
= false;
4202 WARN_ON(i915_vma_unbind(vma
));
4204 dev_priv
->mm
.interruptible
= was_interruptible
;
4208 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4209 * before progressing. */
4211 i915_gem_object_unpin_pages(obj
);
4213 if (WARN_ON(obj
->pages_pin_count
))
4214 obj
->pages_pin_count
= 0;
4215 i915_gem_object_put_pages(obj
);
4216 i915_gem_object_free_mmap_offset(obj
);
4217 i915_gem_object_release_stolen(obj
);
4221 if (obj
->base
.import_attach
)
4222 drm_prime_gem_destroy(&obj
->base
, NULL
);
4224 drm_gem_object_release(&obj
->base
);
4225 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4228 i915_gem_object_free(obj
);
4230 intel_runtime_pm_put(dev_priv
);
4233 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4234 struct i915_address_space
*vm
)
4236 struct i915_vma
*vma
;
4237 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4244 static struct i915_vma
*__i915_gem_vma_create(struct drm_i915_gem_object
*obj
,
4245 struct i915_address_space
*vm
)
4247 struct i915_vma
*vma
= kzalloc(sizeof(*vma
), GFP_KERNEL
);
4249 return ERR_PTR(-ENOMEM
);
4251 INIT_LIST_HEAD(&vma
->vma_link
);
4252 INIT_LIST_HEAD(&vma
->mm_list
);
4253 INIT_LIST_HEAD(&vma
->exec_list
);
4257 /* Keep GGTT vmas first to make debug easier */
4258 if (i915_is_ggtt(vm
))
4259 list_add(&vma
->vma_link
, &obj
->vma_list
);
4261 list_add_tail(&vma
->vma_link
, &obj
->vma_list
);
4267 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
4268 struct i915_address_space
*vm
)
4270 struct i915_vma
*vma
;
4272 vma
= i915_gem_obj_to_vma(obj
, vm
);
4274 vma
= __i915_gem_vma_create(obj
, vm
);
4279 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4281 WARN_ON(vma
->node
.allocated
);
4283 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4284 if (!list_empty(&vma
->exec_list
))
4287 list_del(&vma
->vma_link
);
4293 i915_gem_suspend(struct drm_device
*dev
)
4295 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4298 mutex_lock(&dev
->struct_mutex
);
4299 if (dev_priv
->ums
.mm_suspended
)
4302 ret
= i915_gpu_idle(dev
);
4306 i915_gem_retire_requests(dev
);
4308 /* Under UMS, be paranoid and evict. */
4309 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4310 i915_gem_evict_everything(dev
);
4312 i915_kernel_lost_context(dev
);
4313 i915_gem_cleanup_ringbuffer(dev
);
4315 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4316 * We need to replace this with a semaphore, or something.
4317 * And not confound ums.mm_suspended!
4319 dev_priv
->ums
.mm_suspended
= !drm_core_check_feature(dev
,
4321 mutex_unlock(&dev
->struct_mutex
);
4323 del_timer_sync(&dev_priv
->gpu_error
.hangcheck_timer
);
4324 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4325 cancel_delayed_work_sync(&dev_priv
->mm
.idle_work
);
4330 mutex_unlock(&dev
->struct_mutex
);
4334 int i915_gem_l3_remap(struct intel_ring_buffer
*ring
, int slice
)
4336 struct drm_device
*dev
= ring
->dev
;
4337 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4338 u32 reg_base
= GEN7_L3LOG_BASE
+ (slice
* 0x200);
4339 u32
*remap_info
= dev_priv
->l3_parity
.remap_info
[slice
];
4342 if (!HAS_L3_DPF(dev
) || !remap_info
)
4345 ret
= intel_ring_begin(ring
, GEN7_L3LOG_SIZE
/ 4 * 3);
4350 * Note: We do not worry about the concurrent register cacheline hang
4351 * here because no other code should access these registers other than
4352 * at initialization time.
4354 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
4355 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
4356 intel_ring_emit(ring
, reg_base
+ i
);
4357 intel_ring_emit(ring
, remap_info
[i
/4]);
4360 intel_ring_advance(ring
);
4365 void i915_gem_init_swizzling(struct drm_device
*dev
)
4367 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4369 if (INTEL_INFO(dev
)->gen
< 5 ||
4370 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4373 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4374 DISP_TILE_SURFACE_SWIZZLING
);
4379 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4381 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4382 else if (IS_GEN7(dev
))
4383 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4384 else if (IS_GEN8(dev
))
4385 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4391 intel_enable_blt(struct drm_device
*dev
)
4396 /* The blitter was dysfunctional on early prototypes */
4397 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
4398 DRM_INFO("BLT not supported on this pre-production hardware;"
4399 " graphics performance will be degraded.\n");
4406 static int i915_gem_init_rings(struct drm_device
*dev
)
4408 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4411 ret
= intel_init_render_ring_buffer(dev
);
4416 ret
= intel_init_bsd_ring_buffer(dev
);
4418 goto cleanup_render_ring
;
4421 if (intel_enable_blt(dev
)) {
4422 ret
= intel_init_blt_ring_buffer(dev
);
4424 goto cleanup_bsd_ring
;
4427 if (HAS_VEBOX(dev
)) {
4428 ret
= intel_init_vebox_ring_buffer(dev
);
4430 goto cleanup_blt_ring
;
4434 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
4436 goto cleanup_vebox_ring
;
4441 intel_cleanup_ring_buffer(&dev_priv
->ring
[VECS
]);
4443 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
4445 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
4446 cleanup_render_ring
:
4447 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
4453 i915_gem_init_hw(struct drm_device
*dev
)
4455 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4458 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
4461 if (dev_priv
->ellc_size
)
4462 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4464 if (IS_HASWELL(dev
))
4465 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
4466 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
4468 if (HAS_PCH_NOP(dev
)) {
4469 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4470 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4471 I915_WRITE(GEN7_MSG_CTL
, temp
);
4474 i915_gem_init_swizzling(dev
);
4476 ret
= i915_gem_init_rings(dev
);
4480 for (i
= 0; i
< NUM_L3_SLICES(dev
); i
++)
4481 i915_gem_l3_remap(&dev_priv
->ring
[RCS
], i
);
4484 * XXX: There was some w/a described somewhere suggesting loading
4485 * contexts before PPGTT.
4487 ret
= i915_gem_context_init(dev
);
4489 i915_gem_cleanup_ringbuffer(dev
);
4490 DRM_ERROR("Context initialization failed %d\n", ret
);
4494 if (dev_priv
->mm
.aliasing_ppgtt
) {
4495 ret
= dev_priv
->mm
.aliasing_ppgtt
->enable(dev
);
4497 i915_gem_cleanup_aliasing_ppgtt(dev
);
4498 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4505 int i915_gem_init(struct drm_device
*dev
)
4507 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4510 mutex_lock(&dev
->struct_mutex
);
4512 if (IS_VALLEYVIEW(dev
)) {
4513 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4514 I915_WRITE(VLV_GTLC_WAKE_CTRL
, 1);
4515 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS
) & 1) == 1, 10))
4516 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4519 i915_gem_init_global_gtt(dev
);
4521 ret
= i915_gem_init_hw(dev
);
4522 mutex_unlock(&dev
->struct_mutex
);
4524 i915_gem_cleanup_aliasing_ppgtt(dev
);
4528 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4529 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4530 dev_priv
->dri1
.allow_batchbuffer
= 1;
4535 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4537 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4538 struct intel_ring_buffer
*ring
;
4541 for_each_ring(ring
, dev_priv
, i
)
4542 intel_cleanup_ring_buffer(ring
);
4546 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4547 struct drm_file
*file_priv
)
4549 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4552 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4555 if (i915_reset_in_progress(&dev_priv
->gpu_error
)) {
4556 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4557 atomic_set(&dev_priv
->gpu_error
.reset_counter
, 0);
4560 mutex_lock(&dev
->struct_mutex
);
4561 dev_priv
->ums
.mm_suspended
= 0;
4563 ret
= i915_gem_init_hw(dev
);
4565 mutex_unlock(&dev
->struct_mutex
);
4569 BUG_ON(!list_empty(&dev_priv
->gtt
.base
.active_list
));
4570 mutex_unlock(&dev
->struct_mutex
);
4572 ret
= drm_irq_install(dev
);
4574 goto cleanup_ringbuffer
;
4579 mutex_lock(&dev
->struct_mutex
);
4580 i915_gem_cleanup_ringbuffer(dev
);
4581 dev_priv
->ums
.mm_suspended
= 1;
4582 mutex_unlock(&dev
->struct_mutex
);
4588 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4589 struct drm_file
*file_priv
)
4591 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4594 drm_irq_uninstall(dev
);
4596 return i915_gem_suspend(dev
);
4600 i915_gem_lastclose(struct drm_device
*dev
)
4604 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4607 ret
= i915_gem_suspend(dev
);
4609 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4613 init_ring_lists(struct intel_ring_buffer
*ring
)
4615 INIT_LIST_HEAD(&ring
->active_list
);
4616 INIT_LIST_HEAD(&ring
->request_list
);
4619 static void i915_init_vm(struct drm_i915_private
*dev_priv
,
4620 struct i915_address_space
*vm
)
4622 vm
->dev
= dev_priv
->dev
;
4623 INIT_LIST_HEAD(&vm
->active_list
);
4624 INIT_LIST_HEAD(&vm
->inactive_list
);
4625 INIT_LIST_HEAD(&vm
->global_link
);
4626 list_add(&vm
->global_link
, &dev_priv
->vm_list
);
4630 i915_gem_load(struct drm_device
*dev
)
4632 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4636 kmem_cache_create("i915_gem_object",
4637 sizeof(struct drm_i915_gem_object
), 0,
4641 INIT_LIST_HEAD(&dev_priv
->vm_list
);
4642 i915_init_vm(dev_priv
, &dev_priv
->gtt
.base
);
4644 INIT_LIST_HEAD(&dev_priv
->context_list
);
4645 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4646 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4647 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4648 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4649 init_ring_lists(&dev_priv
->ring
[i
]);
4650 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
4651 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4652 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4653 i915_gem_retire_work_handler
);
4654 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
4655 i915_gem_idle_work_handler
);
4656 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
4658 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4660 I915_WRITE(MI_ARB_STATE
,
4661 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
4664 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4666 /* Old X drivers will take 0-2 for front, back, depth buffers */
4667 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4668 dev_priv
->fence_reg_start
= 3;
4670 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
))
4671 dev_priv
->num_fence_regs
= 32;
4672 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4673 dev_priv
->num_fence_regs
= 16;
4675 dev_priv
->num_fence_regs
= 8;
4677 /* Initialize fence registers to zero */
4678 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4679 i915_gem_restore_fences(dev
);
4681 i915_gem_detect_bit_6_swizzle(dev
);
4682 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4684 dev_priv
->mm
.interruptible
= true;
4686 dev_priv
->mm
.inactive_shrinker
.scan_objects
= i915_gem_inactive_scan
;
4687 dev_priv
->mm
.inactive_shrinker
.count_objects
= i915_gem_inactive_count
;
4688 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
4689 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
4693 * Create a physically contiguous memory object for this object
4694 * e.g. for cursor + overlay regs
4696 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4697 int id
, int size
, int align
)
4699 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4700 struct drm_i915_gem_phys_object
*phys_obj
;
4703 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4706 phys_obj
= kzalloc(sizeof(*phys_obj
), GFP_KERNEL
);
4712 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4713 if (!phys_obj
->handle
) {
4718 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4721 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4729 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4731 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4732 struct drm_i915_gem_phys_object
*phys_obj
;
4734 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4737 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4738 if (phys_obj
->cur_obj
) {
4739 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4743 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4745 drm_pci_free(dev
, phys_obj
->handle
);
4747 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4750 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4754 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4755 i915_gem_free_phys_object(dev
, i
);
4758 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4759 struct drm_i915_gem_object
*obj
)
4761 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4768 vaddr
= obj
->phys_obj
->handle
->vaddr
;
4770 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4771 for (i
= 0; i
< page_count
; i
++) {
4772 struct page
*page
= shmem_read_mapping_page(mapping
, i
);
4773 if (!IS_ERR(page
)) {
4774 char *dst
= kmap_atomic(page
);
4775 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
4778 drm_clflush_pages(&page
, 1);
4780 set_page_dirty(page
);
4781 mark_page_accessed(page
);
4782 page_cache_release(page
);
4785 i915_gem_chipset_flush(dev
);
4787 obj
->phys_obj
->cur_obj
= NULL
;
4788 obj
->phys_obj
= NULL
;
4792 i915_gem_attach_phys_object(struct drm_device
*dev
,
4793 struct drm_i915_gem_object
*obj
,
4797 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4798 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4803 if (id
> I915_MAX_PHYS_OBJECT
)
4806 if (obj
->phys_obj
) {
4807 if (obj
->phys_obj
->id
== id
)
4809 i915_gem_detach_phys_object(dev
, obj
);
4812 /* create a new object */
4813 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4814 ret
= i915_gem_init_phys_object(dev
, id
,
4815 obj
->base
.size
, align
);
4817 DRM_ERROR("failed to init phys object %d size: %zu\n",
4818 id
, obj
->base
.size
);
4823 /* bind to the object */
4824 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4825 obj
->phys_obj
->cur_obj
= obj
;
4827 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4829 for (i
= 0; i
< page_count
; i
++) {
4833 page
= shmem_read_mapping_page(mapping
, i
);
4835 return PTR_ERR(page
);
4837 src
= kmap_atomic(page
);
4838 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4839 memcpy(dst
, src
, PAGE_SIZE
);
4842 mark_page_accessed(page
);
4843 page_cache_release(page
);
4850 i915_gem_phys_pwrite(struct drm_device
*dev
,
4851 struct drm_i915_gem_object
*obj
,
4852 struct drm_i915_gem_pwrite
*args
,
4853 struct drm_file
*file_priv
)
4855 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
4856 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
4858 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
4859 unsigned long unwritten
;
4861 /* The physical object once assigned is fixed for the lifetime
4862 * of the obj, so we can safely drop the lock and continue
4865 mutex_unlock(&dev
->struct_mutex
);
4866 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
4867 mutex_lock(&dev
->struct_mutex
);
4872 i915_gem_chipset_flush(dev
);
4876 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4878 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4880 cancel_delayed_work_sync(&file_priv
->mm
.idle_work
);
4882 /* Clean up our request list when the client is going away, so that
4883 * later retire_requests won't dereference our soon-to-be-gone
4886 spin_lock(&file_priv
->mm
.lock
);
4887 while (!list_empty(&file_priv
->mm
.request_list
)) {
4888 struct drm_i915_gem_request
*request
;
4890 request
= list_first_entry(&file_priv
->mm
.request_list
,
4891 struct drm_i915_gem_request
,
4893 list_del(&request
->client_list
);
4894 request
->file_priv
= NULL
;
4896 spin_unlock(&file_priv
->mm
.lock
);
4900 i915_gem_file_idle_work_handler(struct work_struct
*work
)
4902 struct drm_i915_file_private
*file_priv
=
4903 container_of(work
, typeof(*file_priv
), mm
.idle_work
.work
);
4905 atomic_set(&file_priv
->rps_wait_boost
, false);
4908 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
4910 struct drm_i915_file_private
*file_priv
;
4912 DRM_DEBUG_DRIVER("\n");
4914 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
4918 file
->driver_priv
= file_priv
;
4919 file_priv
->dev_priv
= dev
->dev_private
;
4921 spin_lock_init(&file_priv
->mm
.lock
);
4922 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
4923 INIT_DELAYED_WORK(&file_priv
->mm
.idle_work
,
4924 i915_gem_file_idle_work_handler
);
4926 idr_init(&file_priv
->context_idr
);
4931 static bool mutex_is_locked_by(struct mutex
*mutex
, struct task_struct
*task
)
4933 if (!mutex_is_locked(mutex
))
4936 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4937 return mutex
->owner
== task
;
4939 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4944 static unsigned long
4945 i915_gem_inactive_count(struct shrinker
*shrinker
, struct shrink_control
*sc
)
4947 struct drm_i915_private
*dev_priv
=
4948 container_of(shrinker
,
4949 struct drm_i915_private
,
4950 mm
.inactive_shrinker
);
4951 struct drm_device
*dev
= dev_priv
->dev
;
4952 struct drm_i915_gem_object
*obj
;
4954 unsigned long count
;
4956 if (!mutex_trylock(&dev
->struct_mutex
)) {
4957 if (!mutex_is_locked_by(&dev
->struct_mutex
, current
))
4960 if (dev_priv
->mm
.shrinker_no_lock_stealing
)
4967 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
)
4968 if (obj
->pages_pin_count
== 0)
4969 count
+= obj
->base
.size
>> PAGE_SHIFT
;
4971 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
4975 if (obj
->pin_count
== 0 && obj
->pages_pin_count
== 0)
4976 count
+= obj
->base
.size
>> PAGE_SHIFT
;
4980 mutex_unlock(&dev
->struct_mutex
);
4985 /* All the new VM stuff */
4986 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
4987 struct i915_address_space
*vm
)
4989 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
4990 struct i915_vma
*vma
;
4992 if (vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
)
4993 vm
= &dev_priv
->gtt
.base
;
4995 BUG_ON(list_empty(&o
->vma_list
));
4996 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
4998 return vma
->node
.start
;
5004 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
5005 struct i915_address_space
*vm
)
5007 struct i915_vma
*vma
;
5009 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5010 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
5016 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
5018 struct i915_vma
*vma
;
5020 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5021 if (drm_mm_node_allocated(&vma
->node
))
5027 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
5028 struct i915_address_space
*vm
)
5030 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5031 struct i915_vma
*vma
;
5033 if (vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
)
5034 vm
= &dev_priv
->gtt
.base
;
5036 BUG_ON(list_empty(&o
->vma_list
));
5038 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5040 return vma
->node
.size
;
5045 static unsigned long
5046 i915_gem_inactive_scan(struct shrinker
*shrinker
, struct shrink_control
*sc
)
5048 struct drm_i915_private
*dev_priv
=
5049 container_of(shrinker
,
5050 struct drm_i915_private
,
5051 mm
.inactive_shrinker
);
5052 struct drm_device
*dev
= dev_priv
->dev
;
5053 unsigned long freed
;
5056 if (!mutex_trylock(&dev
->struct_mutex
)) {
5057 if (!mutex_is_locked_by(&dev
->struct_mutex
, current
))
5060 if (dev_priv
->mm
.shrinker_no_lock_stealing
)
5066 freed
= i915_gem_purge(dev_priv
, sc
->nr_to_scan
);
5067 if (freed
< sc
->nr_to_scan
)
5068 freed
+= __i915_gem_shrink(dev_priv
,
5069 sc
->nr_to_scan
- freed
,
5071 if (freed
< sc
->nr_to_scan
)
5072 freed
+= i915_gem_shrink_all(dev_priv
);
5075 mutex_unlock(&dev
->struct_mutex
);
5080 struct i915_vma
*i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
)
5082 struct i915_vma
*vma
;
5084 if (WARN_ON(list_empty(&obj
->vma_list
)))
5087 vma
= list_first_entry(&obj
->vma_list
, typeof(*vma
), vma_link
);
5088 if (WARN_ON(vma
->vm
!= obj_to_ggtt(obj
)))