2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 #define RQ_BUG_ON(expr)
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
46 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
);
48 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
);
49 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
50 struct drm_i915_gem_object
*obj
);
51 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
52 struct drm_i915_fence_reg
*fence
,
55 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
56 enum i915_cache_level level
)
58 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
61 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
63 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
66 return obj
->pin_display
;
69 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
72 i915_gem_release_mmap(obj
);
74 /* As we do not have an associated fence register, we will force
75 * a tiling change if we ever need to acquire one.
77 obj
->fence_dirty
= false;
78 obj
->fence_reg
= I915_FENCE_REG_NONE
;
81 /* some bookkeeping */
82 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
85 spin_lock(&dev_priv
->mm
.object_stat_lock
);
86 dev_priv
->mm
.object_count
++;
87 dev_priv
->mm
.object_memory
+= size
;
88 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
91 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
94 spin_lock(&dev_priv
->mm
.object_stat_lock
);
95 dev_priv
->mm
.object_count
--;
96 dev_priv
->mm
.object_memory
-= size
;
97 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
101 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
105 #define EXIT_COND (!i915_reset_in_progress(error) || \
106 i915_terminally_wedged(error))
111 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
112 * userspace. If it takes that long something really bad is going on and
113 * we should simply try to bail out and fail as gracefully as possible.
115 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
119 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
121 } else if (ret
< 0) {
129 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
134 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
138 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
142 WARN_ON(i915_verify_lists(dev
));
147 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
148 struct drm_file
*file
)
150 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
151 struct drm_i915_gem_get_aperture
*args
= data
;
152 struct i915_gtt
*ggtt
= &dev_priv
->gtt
;
153 struct i915_vma
*vma
;
157 mutex_lock(&dev
->struct_mutex
);
158 list_for_each_entry(vma
, &ggtt
->base
.active_list
, mm_list
)
160 pinned
+= vma
->node
.size
;
161 list_for_each_entry(vma
, &ggtt
->base
.inactive_list
, mm_list
)
163 pinned
+= vma
->node
.size
;
164 mutex_unlock(&dev
->struct_mutex
);
166 args
->aper_size
= dev_priv
->gtt
.base
.total
;
167 args
->aper_available_size
= args
->aper_size
- pinned
;
173 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
175 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
176 char *vaddr
= obj
->phys_handle
->vaddr
;
178 struct scatterlist
*sg
;
181 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
184 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
188 page
= shmem_read_mapping_page(mapping
, i
);
190 return PTR_ERR(page
);
192 src
= kmap_atomic(page
);
193 memcpy(vaddr
, src
, PAGE_SIZE
);
194 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
197 page_cache_release(page
);
201 i915_gem_chipset_flush(obj
->base
.dev
);
203 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
207 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
214 sg
->length
= obj
->base
.size
;
216 sg_dma_address(sg
) = obj
->phys_handle
->busaddr
;
217 sg_dma_len(sg
) = obj
->base
.size
;
220 obj
->has_dma_mapping
= true;
225 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
)
229 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
231 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
233 /* In the event of a disaster, abandon all caches and
236 WARN_ON(ret
!= -EIO
);
237 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
240 if (obj
->madv
== I915_MADV_DONTNEED
)
244 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
245 char *vaddr
= obj
->phys_handle
->vaddr
;
248 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
252 page
= shmem_read_mapping_page(mapping
, i
);
256 dst
= kmap_atomic(page
);
257 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
258 memcpy(dst
, vaddr
, PAGE_SIZE
);
261 set_page_dirty(page
);
262 if (obj
->madv
== I915_MADV_WILLNEED
)
263 mark_page_accessed(page
);
264 page_cache_release(page
);
270 sg_free_table(obj
->pages
);
273 obj
->has_dma_mapping
= false;
277 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
279 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
282 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
283 .get_pages
= i915_gem_object_get_pages_phys
,
284 .put_pages
= i915_gem_object_put_pages_phys
,
285 .release
= i915_gem_object_release_phys
,
289 drop_pages(struct drm_i915_gem_object
*obj
)
291 struct i915_vma
*vma
, *next
;
294 drm_gem_object_reference(&obj
->base
);
295 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
)
296 if (i915_vma_unbind(vma
))
299 ret
= i915_gem_object_put_pages(obj
);
300 drm_gem_object_unreference(&obj
->base
);
306 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
309 drm_dma_handle_t
*phys
;
312 if (obj
->phys_handle
) {
313 if ((unsigned long)obj
->phys_handle
->vaddr
& (align
-1))
319 if (obj
->madv
!= I915_MADV_WILLNEED
)
322 if (obj
->base
.filp
== NULL
)
325 ret
= drop_pages(obj
);
329 /* create a new object */
330 phys
= drm_pci_alloc(obj
->base
.dev
, obj
->base
.size
, align
);
334 obj
->phys_handle
= phys
;
335 obj
->ops
= &i915_gem_phys_ops
;
337 return i915_gem_object_get_pages(obj
);
341 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
342 struct drm_i915_gem_pwrite
*args
,
343 struct drm_file
*file_priv
)
345 struct drm_device
*dev
= obj
->base
.dev
;
346 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
347 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
350 /* We manually control the domain here and pretend that it
351 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
353 ret
= i915_gem_object_wait_rendering(obj
, false);
357 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
358 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
359 unsigned long unwritten
;
361 /* The physical object once assigned is fixed for the lifetime
362 * of the obj, so we can safely drop the lock and continue
365 mutex_unlock(&dev
->struct_mutex
);
366 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
367 mutex_lock(&dev
->struct_mutex
);
374 drm_clflush_virt_range(vaddr
, args
->size
);
375 i915_gem_chipset_flush(dev
);
378 intel_fb_obj_flush(obj
, false);
382 void *i915_gem_object_alloc(struct drm_device
*dev
)
384 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
385 return kmem_cache_zalloc(dev_priv
->objects
, GFP_KERNEL
);
388 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
390 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
391 kmem_cache_free(dev_priv
->objects
, obj
);
395 i915_gem_create(struct drm_file
*file
,
396 struct drm_device
*dev
,
400 struct drm_i915_gem_object
*obj
;
404 size
= roundup(size
, PAGE_SIZE
);
408 /* Allocate the new object */
409 obj
= i915_gem_alloc_object(dev
, size
);
413 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
414 /* drop reference from allocate - handle holds it now */
415 drm_gem_object_unreference_unlocked(&obj
->base
);
424 i915_gem_dumb_create(struct drm_file
*file
,
425 struct drm_device
*dev
,
426 struct drm_mode_create_dumb
*args
)
428 /* have to work out size/pitch and return them */
429 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
430 args
->size
= args
->pitch
* args
->height
;
431 return i915_gem_create(file
, dev
,
432 args
->size
, &args
->handle
);
436 * Creates a new mm object and returns a handle to it.
439 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
440 struct drm_file
*file
)
442 struct drm_i915_gem_create
*args
= data
;
444 return i915_gem_create(file
, dev
,
445 args
->size
, &args
->handle
);
449 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
450 const char *gpu_vaddr
, int gpu_offset
,
453 int ret
, cpu_offset
= 0;
456 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
457 int this_length
= min(cacheline_end
- gpu_offset
, length
);
458 int swizzled_gpu_offset
= gpu_offset
^ 64;
460 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
461 gpu_vaddr
+ swizzled_gpu_offset
,
466 cpu_offset
+= this_length
;
467 gpu_offset
+= this_length
;
468 length
-= this_length
;
475 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
476 const char __user
*cpu_vaddr
,
479 int ret
, cpu_offset
= 0;
482 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
483 int this_length
= min(cacheline_end
- gpu_offset
, length
);
484 int swizzled_gpu_offset
= gpu_offset
^ 64;
486 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
487 cpu_vaddr
+ cpu_offset
,
492 cpu_offset
+= this_length
;
493 gpu_offset
+= this_length
;
494 length
-= this_length
;
501 * Pins the specified object's pages and synchronizes the object with
502 * GPU accesses. Sets needs_clflush to non-zero if the caller should
503 * flush the object from the CPU cache.
505 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
515 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
516 /* If we're not in the cpu read domain, set ourself into the gtt
517 * read domain and manually flush cachelines (if required). This
518 * optimizes for the case when the gpu will dirty the data
519 * anyway again before the next pread happens. */
520 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
522 ret
= i915_gem_object_wait_rendering(obj
, true);
527 ret
= i915_gem_object_get_pages(obj
);
531 i915_gem_object_pin_pages(obj
);
536 /* Per-page copy function for the shmem pread fastpath.
537 * Flushes invalid cachelines before reading the target if
538 * needs_clflush is set. */
540 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
541 char __user
*user_data
,
542 bool page_do_bit17_swizzling
, bool needs_clflush
)
547 if (unlikely(page_do_bit17_swizzling
))
550 vaddr
= kmap_atomic(page
);
552 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
554 ret
= __copy_to_user_inatomic(user_data
,
555 vaddr
+ shmem_page_offset
,
557 kunmap_atomic(vaddr
);
559 return ret
? -EFAULT
: 0;
563 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
566 if (unlikely(swizzled
)) {
567 unsigned long start
= (unsigned long) addr
;
568 unsigned long end
= (unsigned long) addr
+ length
;
570 /* For swizzling simply ensure that we always flush both
571 * channels. Lame, but simple and it works. Swizzled
572 * pwrite/pread is far from a hotpath - current userspace
573 * doesn't use it at all. */
574 start
= round_down(start
, 128);
575 end
= round_up(end
, 128);
577 drm_clflush_virt_range((void *)start
, end
- start
);
579 drm_clflush_virt_range(addr
, length
);
584 /* Only difference to the fast-path function is that this can handle bit17
585 * and uses non-atomic copy and kmap functions. */
587 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
588 char __user
*user_data
,
589 bool page_do_bit17_swizzling
, bool needs_clflush
)
596 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
598 page_do_bit17_swizzling
);
600 if (page_do_bit17_swizzling
)
601 ret
= __copy_to_user_swizzled(user_data
,
602 vaddr
, shmem_page_offset
,
605 ret
= __copy_to_user(user_data
,
606 vaddr
+ shmem_page_offset
,
610 return ret
? - EFAULT
: 0;
614 i915_gem_shmem_pread(struct drm_device
*dev
,
615 struct drm_i915_gem_object
*obj
,
616 struct drm_i915_gem_pread
*args
,
617 struct drm_file
*file
)
619 char __user
*user_data
;
622 int shmem_page_offset
, page_length
, ret
= 0;
623 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
625 int needs_clflush
= 0;
626 struct sg_page_iter sg_iter
;
628 user_data
= to_user_ptr(args
->data_ptr
);
631 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
633 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
637 offset
= args
->offset
;
639 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
640 offset
>> PAGE_SHIFT
) {
641 struct page
*page
= sg_page_iter_page(&sg_iter
);
646 /* Operation in this page
648 * shmem_page_offset = offset within page in shmem file
649 * page_length = bytes to copy for this page
651 shmem_page_offset
= offset_in_page(offset
);
652 page_length
= remain
;
653 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
654 page_length
= PAGE_SIZE
- shmem_page_offset
;
656 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
657 (page_to_phys(page
) & (1 << 17)) != 0;
659 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
660 user_data
, page_do_bit17_swizzling
,
665 mutex_unlock(&dev
->struct_mutex
);
667 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
668 ret
= fault_in_multipages_writeable(user_data
, remain
);
669 /* Userspace is tricking us, but we've already clobbered
670 * its pages with the prefault and promised to write the
671 * data up to the first fault. Hence ignore any errors
672 * and just continue. */
677 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
678 user_data
, page_do_bit17_swizzling
,
681 mutex_lock(&dev
->struct_mutex
);
687 remain
-= page_length
;
688 user_data
+= page_length
;
689 offset
+= page_length
;
693 i915_gem_object_unpin_pages(obj
);
699 * Reads data from the object referenced by handle.
701 * On error, the contents of *data are undefined.
704 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
705 struct drm_file
*file
)
707 struct drm_i915_gem_pread
*args
= data
;
708 struct drm_i915_gem_object
*obj
;
714 if (!access_ok(VERIFY_WRITE
,
715 to_user_ptr(args
->data_ptr
),
719 ret
= i915_mutex_lock_interruptible(dev
);
723 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
724 if (&obj
->base
== NULL
) {
729 /* Bounds check source. */
730 if (args
->offset
> obj
->base
.size
||
731 args
->size
> obj
->base
.size
- args
->offset
) {
736 /* prime objects have no backing filp to GEM pread/pwrite
739 if (!obj
->base
.filp
) {
744 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
746 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
749 drm_gem_object_unreference(&obj
->base
);
751 mutex_unlock(&dev
->struct_mutex
);
755 /* This is the fast write path which cannot handle
756 * page faults in the source data
760 fast_user_write(struct io_mapping
*mapping
,
761 loff_t page_base
, int page_offset
,
762 char __user
*user_data
,
765 void __iomem
*vaddr_atomic
;
767 unsigned long unwritten
;
769 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
770 /* We can use the cpu mem copy function because this is X86. */
771 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
772 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
774 io_mapping_unmap_atomic(vaddr_atomic
);
779 * This is the fast pwrite path, where we copy the data directly from the
780 * user into the GTT, uncached.
783 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
784 struct drm_i915_gem_object
*obj
,
785 struct drm_i915_gem_pwrite
*args
,
786 struct drm_file
*file
)
788 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
790 loff_t offset
, page_base
;
791 char __user
*user_data
;
792 int page_offset
, page_length
, ret
;
794 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
798 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
802 ret
= i915_gem_object_put_fence(obj
);
806 user_data
= to_user_ptr(args
->data_ptr
);
809 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
811 intel_fb_obj_invalidate(obj
, ORIGIN_GTT
);
814 /* Operation in this page
816 * page_base = page offset within aperture
817 * page_offset = offset within page
818 * page_length = bytes to copy for this page
820 page_base
= offset
& PAGE_MASK
;
821 page_offset
= offset_in_page(offset
);
822 page_length
= remain
;
823 if ((page_offset
+ remain
) > PAGE_SIZE
)
824 page_length
= PAGE_SIZE
- page_offset
;
826 /* If we get a fault while copying data, then (presumably) our
827 * source page isn't available. Return the error and we'll
828 * retry in the slow path.
830 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
831 page_offset
, user_data
, page_length
)) {
836 remain
-= page_length
;
837 user_data
+= page_length
;
838 offset
+= page_length
;
842 intel_fb_obj_flush(obj
, false);
844 i915_gem_object_ggtt_unpin(obj
);
849 /* Per-page copy function for the shmem pwrite fastpath.
850 * Flushes invalid cachelines before writing to the target if
851 * needs_clflush_before is set and flushes out any written cachelines after
852 * writing if needs_clflush is set. */
854 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
855 char __user
*user_data
,
856 bool page_do_bit17_swizzling
,
857 bool needs_clflush_before
,
858 bool needs_clflush_after
)
863 if (unlikely(page_do_bit17_swizzling
))
866 vaddr
= kmap_atomic(page
);
867 if (needs_clflush_before
)
868 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
870 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
871 user_data
, page_length
);
872 if (needs_clflush_after
)
873 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
875 kunmap_atomic(vaddr
);
877 return ret
? -EFAULT
: 0;
880 /* Only difference to the fast-path function is that this can handle bit17
881 * and uses non-atomic copy and kmap functions. */
883 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
884 char __user
*user_data
,
885 bool page_do_bit17_swizzling
,
886 bool needs_clflush_before
,
887 bool needs_clflush_after
)
893 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
894 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
896 page_do_bit17_swizzling
);
897 if (page_do_bit17_swizzling
)
898 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
902 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
905 if (needs_clflush_after
)
906 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
908 page_do_bit17_swizzling
);
911 return ret
? -EFAULT
: 0;
915 i915_gem_shmem_pwrite(struct drm_device
*dev
,
916 struct drm_i915_gem_object
*obj
,
917 struct drm_i915_gem_pwrite
*args
,
918 struct drm_file
*file
)
922 char __user
*user_data
;
923 int shmem_page_offset
, page_length
, ret
= 0;
924 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
925 int hit_slowpath
= 0;
926 int needs_clflush_after
= 0;
927 int needs_clflush_before
= 0;
928 struct sg_page_iter sg_iter
;
930 user_data
= to_user_ptr(args
->data_ptr
);
933 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
935 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
936 /* If we're not in the cpu write domain, set ourself into the gtt
937 * write domain and manually flush cachelines (if required). This
938 * optimizes for the case when the gpu will use the data
939 * right away and we therefore have to clflush anyway. */
940 needs_clflush_after
= cpu_write_needs_clflush(obj
);
941 ret
= i915_gem_object_wait_rendering(obj
, false);
945 /* Same trick applies to invalidate partially written cachelines read
947 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
948 needs_clflush_before
=
949 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
951 ret
= i915_gem_object_get_pages(obj
);
955 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
957 i915_gem_object_pin_pages(obj
);
959 offset
= args
->offset
;
962 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
963 offset
>> PAGE_SHIFT
) {
964 struct page
*page
= sg_page_iter_page(&sg_iter
);
965 int partial_cacheline_write
;
970 /* Operation in this page
972 * shmem_page_offset = offset within page in shmem file
973 * page_length = bytes to copy for this page
975 shmem_page_offset
= offset_in_page(offset
);
977 page_length
= remain
;
978 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
979 page_length
= PAGE_SIZE
- shmem_page_offset
;
981 /* If we don't overwrite a cacheline completely we need to be
982 * careful to have up-to-date data by first clflushing. Don't
983 * overcomplicate things and flush the entire patch. */
984 partial_cacheline_write
= needs_clflush_before
&&
985 ((shmem_page_offset
| page_length
)
986 & (boot_cpu_data
.x86_clflush_size
- 1));
988 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
989 (page_to_phys(page
) & (1 << 17)) != 0;
991 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
992 user_data
, page_do_bit17_swizzling
,
993 partial_cacheline_write
,
994 needs_clflush_after
);
999 mutex_unlock(&dev
->struct_mutex
);
1000 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
1001 user_data
, page_do_bit17_swizzling
,
1002 partial_cacheline_write
,
1003 needs_clflush_after
);
1005 mutex_lock(&dev
->struct_mutex
);
1011 remain
-= page_length
;
1012 user_data
+= page_length
;
1013 offset
+= page_length
;
1017 i915_gem_object_unpin_pages(obj
);
1021 * Fixup: Flush cpu caches in case we didn't flush the dirty
1022 * cachelines in-line while writing and the object moved
1023 * out of the cpu write domain while we've dropped the lock.
1025 if (!needs_clflush_after
&&
1026 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1027 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
1028 i915_gem_chipset_flush(dev
);
1032 if (needs_clflush_after
)
1033 i915_gem_chipset_flush(dev
);
1035 intel_fb_obj_flush(obj
, false);
1040 * Writes data to the object referenced by handle.
1042 * On error, the contents of the buffer that were to be modified are undefined.
1045 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1046 struct drm_file
*file
)
1048 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1049 struct drm_i915_gem_pwrite
*args
= data
;
1050 struct drm_i915_gem_object
*obj
;
1053 if (args
->size
== 0)
1056 if (!access_ok(VERIFY_READ
,
1057 to_user_ptr(args
->data_ptr
),
1061 if (likely(!i915
.prefault_disable
)) {
1062 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
1068 intel_runtime_pm_get(dev_priv
);
1070 ret
= i915_mutex_lock_interruptible(dev
);
1074 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1075 if (&obj
->base
== NULL
) {
1080 /* Bounds check destination. */
1081 if (args
->offset
> obj
->base
.size
||
1082 args
->size
> obj
->base
.size
- args
->offset
) {
1087 /* prime objects have no backing filp to GEM pread/pwrite
1090 if (!obj
->base
.filp
) {
1095 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1098 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1099 * it would end up going through the fenced access, and we'll get
1100 * different detiling behavior between reading and writing.
1101 * pread/pwrite currently are reading and writing from the CPU
1102 * perspective, requiring manual detiling by the client.
1104 if (obj
->tiling_mode
== I915_TILING_NONE
&&
1105 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
1106 cpu_write_needs_clflush(obj
)) {
1107 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1108 /* Note that the gtt paths might fail with non-page-backed user
1109 * pointers (e.g. gtt mappings when moving data between
1110 * textures). Fallback to the shmem path in that case. */
1113 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1114 if (obj
->phys_handle
)
1115 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1117 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
1121 drm_gem_object_unreference(&obj
->base
);
1123 mutex_unlock(&dev
->struct_mutex
);
1125 intel_runtime_pm_put(dev_priv
);
1131 i915_gem_check_wedge(struct i915_gpu_error
*error
,
1134 if (i915_reset_in_progress(error
)) {
1135 /* Non-interruptible callers can't handle -EAGAIN, hence return
1136 * -EIO unconditionally for these. */
1140 /* Recovery complete, but the reset failed ... */
1141 if (i915_terminally_wedged(error
))
1145 * Check if GPU Reset is in progress - we need intel_ring_begin
1146 * to work properly to reinit the hw state while the gpu is
1147 * still marked as reset-in-progress. Handle this with a flag.
1149 if (!error
->reload_in_reset
)
1156 static void fake_irq(unsigned long data
)
1158 wake_up_process((struct task_struct
*)data
);
1161 static bool missed_irq(struct drm_i915_private
*dev_priv
,
1162 struct intel_engine_cs
*ring
)
1164 return test_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
1167 static int __i915_spin_request(struct drm_i915_gem_request
*req
)
1169 unsigned long timeout
;
1171 if (i915_gem_request_get_ring(req
)->irq_refcount
)
1174 timeout
= jiffies
+ 1;
1175 while (!need_resched()) {
1176 if (i915_gem_request_completed(req
, true))
1179 if (time_after_eq(jiffies
, timeout
))
1182 cpu_relax_lowlatency();
1184 if (i915_gem_request_completed(req
, false))
1191 * __i915_wait_request - wait until execution of request has finished
1193 * @reset_counter: reset sequence associated with the given request
1194 * @interruptible: do an interruptible wait (normally yes)
1195 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1197 * Note: It is of utmost importance that the passed in seqno and reset_counter
1198 * values have been read by the caller in an smp safe manner. Where read-side
1199 * locks are involved, it is sufficient to read the reset_counter before
1200 * unlocking the lock that protects the seqno. For lockless tricks, the
1201 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1204 * Returns 0 if the request was found within the alloted time. Else returns the
1205 * errno with remaining time filled in timeout argument.
1207 int __i915_wait_request(struct drm_i915_gem_request
*req
,
1208 unsigned reset_counter
,
1211 struct intel_rps_client
*rps
)
1213 struct intel_engine_cs
*ring
= i915_gem_request_get_ring(req
);
1214 struct drm_device
*dev
= ring
->dev
;
1215 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1216 const bool irq_test_in_progress
=
1217 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_ring_flag(ring
);
1219 unsigned long timeout_expire
;
1223 WARN(!intel_irqs_enabled(dev_priv
), "IRQs disabled");
1225 if (list_empty(&req
->list
))
1228 if (i915_gem_request_completed(req
, true))
1231 timeout_expire
= timeout
?
1232 jiffies
+ nsecs_to_jiffies_timeout((u64
)*timeout
) : 0;
1234 if (INTEL_INFO(dev_priv
)->gen
>= 6)
1235 gen6_rps_boost(dev_priv
, rps
, req
->emitted_jiffies
);
1237 /* Record current time in case interrupted by signal, or wedged */
1238 trace_i915_gem_request_wait_begin(req
);
1239 before
= ktime_get_raw_ns();
1241 /* Optimistic spin for the next jiffie before touching IRQs */
1242 ret
= __i915_spin_request(req
);
1246 if (!irq_test_in_progress
&& WARN_ON(!ring
->irq_get(ring
))) {
1252 struct timer_list timer
;
1254 prepare_to_wait(&ring
->irq_queue
, &wait
,
1255 interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
);
1257 /* We need to check whether any gpu reset happened in between
1258 * the caller grabbing the seqno and now ... */
1259 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
)) {
1260 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1261 * is truely gone. */
1262 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1268 if (i915_gem_request_completed(req
, false)) {
1273 if (interruptible
&& signal_pending(current
)) {
1278 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1283 timer
.function
= NULL
;
1284 if (timeout
|| missed_irq(dev_priv
, ring
)) {
1285 unsigned long expire
;
1287 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1288 expire
= missed_irq(dev_priv
, ring
) ? jiffies
+ 1 : timeout_expire
;
1289 mod_timer(&timer
, expire
);
1294 if (timer
.function
) {
1295 del_singleshot_timer_sync(&timer
);
1296 destroy_timer_on_stack(&timer
);
1299 if (!irq_test_in_progress
)
1300 ring
->irq_put(ring
);
1302 finish_wait(&ring
->irq_queue
, &wait
);
1305 now
= ktime_get_raw_ns();
1306 trace_i915_gem_request_wait_end(req
);
1309 s64 tres
= *timeout
- (now
- before
);
1311 *timeout
= tres
< 0 ? 0 : tres
;
1314 * Apparently ktime isn't accurate enough and occasionally has a
1315 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1316 * things up to make the test happy. We allow up to 1 jiffy.
1318 * This is a regrssion from the timespec->ktime conversion.
1320 if (ret
== -ETIME
&& *timeout
< jiffies_to_usecs(1)*1000)
1327 int i915_gem_request_add_to_client(struct drm_i915_gem_request
*req
,
1328 struct drm_file
*file
)
1330 struct drm_i915_private
*dev_private
;
1331 struct drm_i915_file_private
*file_priv
;
1333 WARN_ON(!req
|| !file
|| req
->file_priv
);
1341 dev_private
= req
->ring
->dev
->dev_private
;
1342 file_priv
= file
->driver_priv
;
1344 spin_lock(&file_priv
->mm
.lock
);
1345 req
->file_priv
= file_priv
;
1346 list_add_tail(&req
->client_list
, &file_priv
->mm
.request_list
);
1347 spin_unlock(&file_priv
->mm
.lock
);
1349 req
->pid
= get_pid(task_pid(current
));
1355 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1357 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1362 spin_lock(&file_priv
->mm
.lock
);
1363 list_del(&request
->client_list
);
1364 request
->file_priv
= NULL
;
1365 spin_unlock(&file_priv
->mm
.lock
);
1367 put_pid(request
->pid
);
1368 request
->pid
= NULL
;
1371 static void i915_gem_request_retire(struct drm_i915_gem_request
*request
)
1373 trace_i915_gem_request_retire(request
);
1375 /* We know the GPU must have read the request to have
1376 * sent us the seqno + interrupt, so use the position
1377 * of tail of the request to update the last known position
1380 * Note this requires that we are always called in request
1383 request
->ringbuf
->last_retired_head
= request
->postfix
;
1385 list_del_init(&request
->list
);
1386 i915_gem_request_remove_from_client(request
);
1388 i915_gem_request_unreference(request
);
1392 __i915_gem_request_retire__upto(struct drm_i915_gem_request
*req
)
1394 struct intel_engine_cs
*engine
= req
->ring
;
1395 struct drm_i915_gem_request
*tmp
;
1397 lockdep_assert_held(&engine
->dev
->struct_mutex
);
1399 if (list_empty(&req
->list
))
1403 tmp
= list_first_entry(&engine
->request_list
,
1404 typeof(*tmp
), list
);
1406 i915_gem_request_retire(tmp
);
1407 } while (tmp
!= req
);
1409 WARN_ON(i915_verify_lists(engine
->dev
));
1413 * Waits for a request to be signaled, and cleans up the
1414 * request and object lists appropriately for that event.
1417 i915_wait_request(struct drm_i915_gem_request
*req
)
1419 struct drm_device
*dev
;
1420 struct drm_i915_private
*dev_priv
;
1424 BUG_ON(req
== NULL
);
1426 dev
= req
->ring
->dev
;
1427 dev_priv
= dev
->dev_private
;
1428 interruptible
= dev_priv
->mm
.interruptible
;
1430 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1432 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1436 ret
= __i915_wait_request(req
,
1437 atomic_read(&dev_priv
->gpu_error
.reset_counter
),
1438 interruptible
, NULL
, NULL
);
1442 __i915_gem_request_retire__upto(req
);
1447 * Ensures that all rendering to the object has completed and the object is
1448 * safe to unbind from the GTT or access from the CPU.
1451 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1460 if (obj
->last_write_req
!= NULL
) {
1461 ret
= i915_wait_request(obj
->last_write_req
);
1465 i
= obj
->last_write_req
->ring
->id
;
1466 if (obj
->last_read_req
[i
] == obj
->last_write_req
)
1467 i915_gem_object_retire__read(obj
, i
);
1469 i915_gem_object_retire__write(obj
);
1472 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1473 if (obj
->last_read_req
[i
] == NULL
)
1476 ret
= i915_wait_request(obj
->last_read_req
[i
]);
1480 i915_gem_object_retire__read(obj
, i
);
1482 RQ_BUG_ON(obj
->active
);
1489 i915_gem_object_retire_request(struct drm_i915_gem_object
*obj
,
1490 struct drm_i915_gem_request
*req
)
1492 int ring
= req
->ring
->id
;
1494 if (obj
->last_read_req
[ring
] == req
)
1495 i915_gem_object_retire__read(obj
, ring
);
1496 else if (obj
->last_write_req
== req
)
1497 i915_gem_object_retire__write(obj
);
1499 __i915_gem_request_retire__upto(req
);
1502 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1503 * as the object state may change during this call.
1505 static __must_check
int
1506 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1507 struct intel_rps_client
*rps
,
1510 struct drm_device
*dev
= obj
->base
.dev
;
1511 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1512 struct drm_i915_gem_request
*requests
[I915_NUM_RINGS
];
1513 unsigned reset_counter
;
1516 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1517 BUG_ON(!dev_priv
->mm
.interruptible
);
1522 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1526 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1529 struct drm_i915_gem_request
*req
;
1531 req
= obj
->last_write_req
;
1535 requests
[n
++] = i915_gem_request_reference(req
);
1537 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1538 struct drm_i915_gem_request
*req
;
1540 req
= obj
->last_read_req
[i
];
1544 requests
[n
++] = i915_gem_request_reference(req
);
1548 mutex_unlock(&dev
->struct_mutex
);
1549 for (i
= 0; ret
== 0 && i
< n
; i
++)
1550 ret
= __i915_wait_request(requests
[i
], reset_counter
, true,
1552 mutex_lock(&dev
->struct_mutex
);
1554 for (i
= 0; i
< n
; i
++) {
1556 i915_gem_object_retire_request(obj
, requests
[i
]);
1557 i915_gem_request_unreference(requests
[i
]);
1563 static struct intel_rps_client
*to_rps_client(struct drm_file
*file
)
1565 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
1570 * Called when user space prepares to use an object with the CPU, either
1571 * through the mmap ioctl's mapping or a GTT mapping.
1574 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1575 struct drm_file
*file
)
1577 struct drm_i915_gem_set_domain
*args
= data
;
1578 struct drm_i915_gem_object
*obj
;
1579 uint32_t read_domains
= args
->read_domains
;
1580 uint32_t write_domain
= args
->write_domain
;
1583 /* Only handle setting domains to types used by the CPU. */
1584 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1587 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1590 /* Having something in the write domain implies it's in the read
1591 * domain, and only that read domain. Enforce that in the request.
1593 if (write_domain
!= 0 && read_domains
!= write_domain
)
1596 ret
= i915_mutex_lock_interruptible(dev
);
1600 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1601 if (&obj
->base
== NULL
) {
1606 /* Try to flush the object off the GPU without holding the lock.
1607 * We will repeat the flush holding the lock in the normal manner
1608 * to catch cases where we are gazumped.
1610 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1611 to_rps_client(file
),
1616 if (read_domains
& I915_GEM_DOMAIN_GTT
)
1617 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1619 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1621 if (write_domain
!= 0)
1622 intel_fb_obj_invalidate(obj
,
1623 write_domain
== I915_GEM_DOMAIN_GTT
?
1624 ORIGIN_GTT
: ORIGIN_CPU
);
1627 drm_gem_object_unreference(&obj
->base
);
1629 mutex_unlock(&dev
->struct_mutex
);
1634 * Called when user space has done writes to this buffer
1637 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1638 struct drm_file
*file
)
1640 struct drm_i915_gem_sw_finish
*args
= data
;
1641 struct drm_i915_gem_object
*obj
;
1644 ret
= i915_mutex_lock_interruptible(dev
);
1648 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1649 if (&obj
->base
== NULL
) {
1654 /* Pinned buffers may be scanout, so flush the cache */
1655 if (obj
->pin_display
)
1656 i915_gem_object_flush_cpu_write_domain(obj
);
1658 drm_gem_object_unreference(&obj
->base
);
1660 mutex_unlock(&dev
->struct_mutex
);
1665 * Maps the contents of an object, returning the address it is mapped
1668 * While the mapping holds a reference on the contents of the object, it doesn't
1669 * imply a ref on the object itself.
1673 * DRM driver writers who look a this function as an example for how to do GEM
1674 * mmap support, please don't implement mmap support like here. The modern way
1675 * to implement DRM mmap support is with an mmap offset ioctl (like
1676 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1677 * That way debug tooling like valgrind will understand what's going on, hiding
1678 * the mmap call in a driver private ioctl will break that. The i915 driver only
1679 * does cpu mmaps this way because we didn't know better.
1682 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1683 struct drm_file
*file
)
1685 struct drm_i915_gem_mmap
*args
= data
;
1686 struct drm_gem_object
*obj
;
1689 if (args
->flags
& ~(I915_MMAP_WC
))
1692 if (args
->flags
& I915_MMAP_WC
&& !cpu_has_pat
)
1695 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1699 /* prime objects have no backing filp to GEM mmap
1703 drm_gem_object_unreference_unlocked(obj
);
1707 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1708 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1710 if (args
->flags
& I915_MMAP_WC
) {
1711 struct mm_struct
*mm
= current
->mm
;
1712 struct vm_area_struct
*vma
;
1714 down_write(&mm
->mmap_sem
);
1715 vma
= find_vma(mm
, addr
);
1718 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1721 up_write(&mm
->mmap_sem
);
1723 drm_gem_object_unreference_unlocked(obj
);
1724 if (IS_ERR((void *)addr
))
1727 args
->addr_ptr
= (uint64_t) addr
;
1733 * i915_gem_fault - fault a page into the GTT
1734 * vma: VMA in question
1737 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1738 * from userspace. The fault handler takes care of binding the object to
1739 * the GTT (if needed), allocating and programming a fence register (again,
1740 * only if needed based on whether the old reg is still valid or the object
1741 * is tiled) and inserting a new PTE into the faulting process.
1743 * Note that the faulting process may involve evicting existing objects
1744 * from the GTT and/or fence registers to make room. So performance may
1745 * suffer if the GTT working set is large or there are few fence registers
1748 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1750 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1751 struct drm_device
*dev
= obj
->base
.dev
;
1752 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1753 struct i915_ggtt_view view
= i915_ggtt_view_normal
;
1754 pgoff_t page_offset
;
1757 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1759 intel_runtime_pm_get(dev_priv
);
1761 /* We don't use vmf->pgoff since that has the fake offset */
1762 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1765 ret
= i915_mutex_lock_interruptible(dev
);
1769 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1771 /* Try to flush the object off the GPU first without holding the lock.
1772 * Upon reacquiring the lock, we will perform our sanity checks and then
1773 * repeat the flush holding the lock in the normal manner to catch cases
1774 * where we are gazumped.
1776 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
1780 /* Access to snoopable pages through the GTT is incoherent. */
1781 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1786 /* Use a partial view if the object is bigger than the aperture. */
1787 if (obj
->base
.size
>= dev_priv
->gtt
.mappable_end
&&
1788 obj
->tiling_mode
== I915_TILING_NONE
) {
1789 static const unsigned int chunk_size
= 256; // 1 MiB
1791 memset(&view
, 0, sizeof(view
));
1792 view
.type
= I915_GGTT_VIEW_PARTIAL
;
1793 view
.params
.partial
.offset
= rounddown(page_offset
, chunk_size
);
1794 view
.params
.partial
.size
=
1797 (vma
->vm_end
- vma
->vm_start
)/PAGE_SIZE
-
1798 view
.params
.partial
.offset
);
1801 /* Now pin it into the GTT if needed */
1802 ret
= i915_gem_object_ggtt_pin(obj
, &view
, 0, PIN_MAPPABLE
);
1806 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1810 ret
= i915_gem_object_get_fence(obj
);
1814 /* Finally, remap it using the new GTT offset */
1815 pfn
= dev_priv
->gtt
.mappable_base
+
1816 i915_gem_obj_ggtt_offset_view(obj
, &view
);
1819 if (unlikely(view
.type
== I915_GGTT_VIEW_PARTIAL
)) {
1820 /* Overriding existing pages in partial view does not cause
1821 * us any trouble as TLBs are still valid because the fault
1822 * is due to userspace losing part of the mapping or never
1823 * having accessed it before (at this partials' range).
1825 unsigned long base
= vma
->vm_start
+
1826 (view
.params
.partial
.offset
<< PAGE_SHIFT
);
1829 for (i
= 0; i
< view
.params
.partial
.size
; i
++) {
1830 ret
= vm_insert_pfn(vma
, base
+ i
* PAGE_SIZE
, pfn
+ i
);
1835 obj
->fault_mappable
= true;
1837 if (!obj
->fault_mappable
) {
1838 unsigned long size
= min_t(unsigned long,
1839 vma
->vm_end
- vma
->vm_start
,
1843 for (i
= 0; i
< size
>> PAGE_SHIFT
; i
++) {
1844 ret
= vm_insert_pfn(vma
,
1845 (unsigned long)vma
->vm_start
+ i
* PAGE_SIZE
,
1851 obj
->fault_mappable
= true;
1853 ret
= vm_insert_pfn(vma
,
1854 (unsigned long)vmf
->virtual_address
,
1858 i915_gem_object_ggtt_unpin_view(obj
, &view
);
1860 mutex_unlock(&dev
->struct_mutex
);
1865 * We eat errors when the gpu is terminally wedged to avoid
1866 * userspace unduly crashing (gl has no provisions for mmaps to
1867 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1868 * and so needs to be reported.
1870 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1871 ret
= VM_FAULT_SIGBUS
;
1876 * EAGAIN means the gpu is hung and we'll wait for the error
1877 * handler to reset everything when re-faulting in
1878 * i915_mutex_lock_interruptible.
1885 * EBUSY is ok: this just means that another thread
1886 * already did the job.
1888 ret
= VM_FAULT_NOPAGE
;
1895 ret
= VM_FAULT_SIGBUS
;
1898 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1899 ret
= VM_FAULT_SIGBUS
;
1903 intel_runtime_pm_put(dev_priv
);
1908 * i915_gem_release_mmap - remove physical page mappings
1909 * @obj: obj in question
1911 * Preserve the reservation of the mmapping with the DRM core code, but
1912 * relinquish ownership of the pages back to the system.
1914 * It is vital that we remove the page mapping if we have mapped a tiled
1915 * object through the GTT and then lose the fence register due to
1916 * resource pressure. Similarly if the object has been moved out of the
1917 * aperture, than pages mapped into userspace must be revoked. Removing the
1918 * mapping will then trigger a page fault on the next user access, allowing
1919 * fixup by i915_gem_fault().
1922 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1924 if (!obj
->fault_mappable
)
1927 drm_vma_node_unmap(&obj
->base
.vma_node
,
1928 obj
->base
.dev
->anon_inode
->i_mapping
);
1929 obj
->fault_mappable
= false;
1933 i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
1935 struct drm_i915_gem_object
*obj
;
1937 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
1938 i915_gem_release_mmap(obj
);
1942 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1946 if (INTEL_INFO(dev
)->gen
>= 4 ||
1947 tiling_mode
== I915_TILING_NONE
)
1950 /* Previous chips need a power-of-two fence region when tiling */
1951 if (INTEL_INFO(dev
)->gen
== 3)
1952 gtt_size
= 1024*1024;
1954 gtt_size
= 512*1024;
1956 while (gtt_size
< size
)
1963 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1964 * @obj: object to check
1966 * Return the required GTT alignment for an object, taking into account
1967 * potential fence register mapping.
1970 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1971 int tiling_mode
, bool fenced
)
1974 * Minimum alignment is 4k (GTT page size), but might be greater
1975 * if a fence register is needed for the object.
1977 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1978 tiling_mode
== I915_TILING_NONE
)
1982 * Previous chips need to be aligned to the size of the smallest
1983 * fence register that can contain the object.
1985 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1988 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1990 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1993 if (drm_vma_node_has_offset(&obj
->base
.vma_node
))
1996 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1998 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2002 /* Badly fragmented mmap space? The only way we can recover
2003 * space is by destroying unwanted objects. We can't randomly release
2004 * mmap_offsets as userspace expects them to be persistent for the
2005 * lifetime of the objects. The closest we can is to release the
2006 * offsets on purgeable objects by truncating it and marking it purged,
2007 * which prevents userspace from ever using that object again.
2009 i915_gem_shrink(dev_priv
,
2010 obj
->base
.size
>> PAGE_SHIFT
,
2012 I915_SHRINK_UNBOUND
|
2013 I915_SHRINK_PURGEABLE
);
2014 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2018 i915_gem_shrink_all(dev_priv
);
2019 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2021 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
2026 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
2028 drm_gem_free_mmap_offset(&obj
->base
);
2032 i915_gem_mmap_gtt(struct drm_file
*file
,
2033 struct drm_device
*dev
,
2037 struct drm_i915_gem_object
*obj
;
2040 ret
= i915_mutex_lock_interruptible(dev
);
2044 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
2045 if (&obj
->base
== NULL
) {
2050 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2051 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2056 ret
= i915_gem_object_create_mmap_offset(obj
);
2060 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
2063 drm_gem_object_unreference(&obj
->base
);
2065 mutex_unlock(&dev
->struct_mutex
);
2070 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2072 * @data: GTT mapping ioctl data
2073 * @file: GEM object info
2075 * Simply returns the fake offset to userspace so it can mmap it.
2076 * The mmap call will end up in drm_gem_mmap(), which will set things
2077 * up so we can get faults in the handler above.
2079 * The fault handler will take care of binding the object into the GTT
2080 * (since it may have been evicted to make room for something), allocating
2081 * a fence register, and mapping the appropriate aperture address into
2085 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2086 struct drm_file
*file
)
2088 struct drm_i915_gem_mmap_gtt
*args
= data
;
2090 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
2093 /* Immediately discard the backing storage */
2095 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
2097 i915_gem_object_free_mmap_offset(obj
);
2099 if (obj
->base
.filp
== NULL
)
2102 /* Our goal here is to return as much of the memory as
2103 * is possible back to the system as we are called from OOM.
2104 * To do this we must instruct the shmfs to drop all of its
2105 * backing pages, *now*.
2107 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
2108 obj
->madv
= __I915_MADV_PURGED
;
2111 /* Try to discard unwanted pages */
2113 i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
2115 struct address_space
*mapping
;
2117 switch (obj
->madv
) {
2118 case I915_MADV_DONTNEED
:
2119 i915_gem_object_truncate(obj
);
2120 case __I915_MADV_PURGED
:
2124 if (obj
->base
.filp
== NULL
)
2127 mapping
= file_inode(obj
->base
.filp
)->i_mapping
,
2128 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
2132 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
2134 struct sg_page_iter sg_iter
;
2137 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
2139 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
2141 /* In the event of a disaster, abandon all caches and
2142 * hope for the best.
2144 WARN_ON(ret
!= -EIO
);
2145 i915_gem_clflush_object(obj
, true);
2146 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2149 if (i915_gem_object_needs_bit17_swizzle(obj
))
2150 i915_gem_object_save_bit_17_swizzle(obj
);
2152 if (obj
->madv
== I915_MADV_DONTNEED
)
2155 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
2156 struct page
*page
= sg_page_iter_page(&sg_iter
);
2159 set_page_dirty(page
);
2161 if (obj
->madv
== I915_MADV_WILLNEED
)
2162 mark_page_accessed(page
);
2164 page_cache_release(page
);
2168 sg_free_table(obj
->pages
);
2173 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
2175 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2177 if (obj
->pages
== NULL
)
2180 if (obj
->pages_pin_count
)
2183 BUG_ON(i915_gem_obj_bound_any(obj
));
2185 /* ->put_pages might need to allocate memory for the bit17 swizzle
2186 * array, hence protect them from being reaped by removing them from gtt
2188 list_del(&obj
->global_list
);
2190 ops
->put_pages(obj
);
2193 i915_gem_object_invalidate(obj
);
2199 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2201 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2203 struct address_space
*mapping
;
2204 struct sg_table
*st
;
2205 struct scatterlist
*sg
;
2206 struct sg_page_iter sg_iter
;
2208 unsigned long last_pfn
= 0; /* suppress gcc warning */
2211 /* Assert that the object is not currently in any GPU domain. As it
2212 * wasn't in the GTT, there shouldn't be any way it could have been in
2215 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2216 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2218 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2222 page_count
= obj
->base
.size
/ PAGE_SIZE
;
2223 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2228 /* Get the list of pages out of our struct file. They'll be pinned
2229 * at this point until we release them.
2231 * Fail silently without starting the shrinker
2233 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
2234 gfp
= mapping_gfp_mask(mapping
);
2235 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
2236 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
2239 for (i
= 0; i
< page_count
; i
++) {
2240 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2242 i915_gem_shrink(dev_priv
,
2245 I915_SHRINK_UNBOUND
|
2246 I915_SHRINK_PURGEABLE
);
2247 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2250 /* We've tried hard to allocate the memory by reaping
2251 * our own buffer, now let the real VM do its job and
2252 * go down in flames if truly OOM.
2254 i915_gem_shrink_all(dev_priv
);
2255 page
= shmem_read_mapping_page(mapping
, i
);
2259 #ifdef CONFIG_SWIOTLB
2260 if (swiotlb_nr_tbl()) {
2262 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2267 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
2271 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2273 sg
->length
+= PAGE_SIZE
;
2275 last_pfn
= page_to_pfn(page
);
2277 /* Check that the i965g/gm workaround works. */
2278 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2280 #ifdef CONFIG_SWIOTLB
2281 if (!swiotlb_nr_tbl())
2286 if (i915_gem_object_needs_bit17_swizzle(obj
))
2287 i915_gem_object_do_bit_17_swizzle(obj
);
2289 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
2290 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2291 i915_gem_object_pin_pages(obj
);
2297 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
2298 page_cache_release(sg_page_iter_page(&sg_iter
));
2302 /* shmemfs first checks if there is enough memory to allocate the page
2303 * and reports ENOSPC should there be insufficient, along with the usual
2304 * ENOMEM for a genuine allocation failure.
2306 * We use ENOSPC in our driver to mean that we have run out of aperture
2307 * space and so want to translate the error from shmemfs back to our
2308 * usual understanding of ENOMEM.
2310 if (PTR_ERR(page
) == -ENOSPC
)
2313 return PTR_ERR(page
);
2316 /* Ensure that the associated pages are gathered from the backing storage
2317 * and pinned into our object. i915_gem_object_get_pages() may be called
2318 * multiple times before they are released by a single call to
2319 * i915_gem_object_put_pages() - once the pages are no longer referenced
2320 * either as a result of memory pressure (reaping pages under the shrinker)
2321 * or as the object is itself released.
2324 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2326 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2327 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2333 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2334 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2338 BUG_ON(obj
->pages_pin_count
);
2340 ret
= ops
->get_pages(obj
);
2344 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2346 obj
->get_page
.sg
= obj
->pages
->sgl
;
2347 obj
->get_page
.last
= 0;
2352 void i915_vma_move_to_active(struct i915_vma
*vma
,
2353 struct drm_i915_gem_request
*req
)
2355 struct drm_i915_gem_object
*obj
= vma
->obj
;
2356 struct intel_engine_cs
*ring
;
2358 ring
= i915_gem_request_get_ring(req
);
2360 /* Add a reference if we're newly entering the active list. */
2361 if (obj
->active
== 0)
2362 drm_gem_object_reference(&obj
->base
);
2363 obj
->active
|= intel_ring_flag(ring
);
2365 list_move_tail(&obj
->ring_list
[ring
->id
], &ring
->active_list
);
2366 i915_gem_request_assign(&obj
->last_read_req
[ring
->id
], req
);
2368 list_move_tail(&vma
->mm_list
, &vma
->vm
->active_list
);
2372 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
)
2374 RQ_BUG_ON(obj
->last_write_req
== NULL
);
2375 RQ_BUG_ON(!(obj
->active
& intel_ring_flag(obj
->last_write_req
->ring
)));
2377 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
2378 intel_fb_obj_flush(obj
, true);
2382 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
)
2384 struct i915_vma
*vma
;
2386 RQ_BUG_ON(obj
->last_read_req
[ring
] == NULL
);
2387 RQ_BUG_ON(!(obj
->active
& (1 << ring
)));
2389 list_del_init(&obj
->ring_list
[ring
]);
2390 i915_gem_request_assign(&obj
->last_read_req
[ring
], NULL
);
2392 if (obj
->last_write_req
&& obj
->last_write_req
->ring
->id
== ring
)
2393 i915_gem_object_retire__write(obj
);
2395 obj
->active
&= ~(1 << ring
);
2399 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
2400 if (!list_empty(&vma
->mm_list
))
2401 list_move_tail(&vma
->mm_list
, &vma
->vm
->inactive_list
);
2404 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
2405 drm_gem_object_unreference(&obj
->base
);
2409 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
2411 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2412 struct intel_engine_cs
*ring
;
2415 /* Carefully retire all requests without writing to the rings */
2416 for_each_ring(ring
, dev_priv
, i
) {
2417 ret
= intel_ring_idle(ring
);
2421 i915_gem_retire_requests(dev
);
2423 /* Finally reset hw state */
2424 for_each_ring(ring
, dev_priv
, i
) {
2425 intel_ring_init_seqno(ring
, seqno
);
2427 for (j
= 0; j
< ARRAY_SIZE(ring
->semaphore
.sync_seqno
); j
++)
2428 ring
->semaphore
.sync_seqno
[j
] = 0;
2434 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2436 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2442 /* HWS page needs to be set less than what we
2443 * will inject to ring
2445 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
2449 /* Carefully set the last_seqno value so that wrap
2450 * detection still works
2452 dev_priv
->next_seqno
= seqno
;
2453 dev_priv
->last_seqno
= seqno
- 1;
2454 if (dev_priv
->last_seqno
== 0)
2455 dev_priv
->last_seqno
--;
2461 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
2463 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2465 /* reserve 0 for non-seqno */
2466 if (dev_priv
->next_seqno
== 0) {
2467 int ret
= i915_gem_init_seqno(dev
, 0);
2471 dev_priv
->next_seqno
= 1;
2474 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2479 * NB: This function is not allowed to fail. Doing so would mean the the
2480 * request is not being tracked for completion but the work itself is
2481 * going to happen on the hardware. This would be a Bad Thing(tm).
2483 void __i915_add_request(struct drm_i915_gem_request
*request
,
2484 struct drm_i915_gem_object
*obj
,
2487 struct intel_engine_cs
*ring
;
2488 struct drm_i915_private
*dev_priv
;
2489 struct intel_ringbuffer
*ringbuf
;
2493 if (WARN_ON(request
== NULL
))
2496 ring
= request
->ring
;
2497 dev_priv
= ring
->dev
->dev_private
;
2498 ringbuf
= request
->ringbuf
;
2501 * To ensure that this call will not fail, space for its emissions
2502 * should already have been reserved in the ring buffer. Let the ring
2503 * know that it is time to use that space up.
2505 intel_ring_reserved_space_use(ringbuf
);
2507 request_start
= intel_ring_get_tail(ringbuf
);
2509 * Emit any outstanding flushes - execbuf can fail to emit the flush
2510 * after having emitted the batchbuffer command. Hence we need to fix
2511 * things up similar to emitting the lazy request. The difference here
2512 * is that the flush _must_ happen before the next request, no matter
2516 if (i915
.enable_execlists
)
2517 ret
= logical_ring_flush_all_caches(request
);
2519 ret
= intel_ring_flush_all_caches(request
);
2520 /* Not allowed to fail! */
2521 WARN(ret
, "*_ring_flush_all_caches failed: %d!\n", ret
);
2524 /* Record the position of the start of the request so that
2525 * should we detect the updated seqno part-way through the
2526 * GPU processing the request, we never over-estimate the
2527 * position of the head.
2529 request
->postfix
= intel_ring_get_tail(ringbuf
);
2531 if (i915
.enable_execlists
)
2532 ret
= ring
->emit_request(request
);
2534 ret
= ring
->add_request(request
);
2536 request
->tail
= intel_ring_get_tail(ringbuf
);
2538 /* Not allowed to fail! */
2539 WARN(ret
, "emit|add_request failed: %d!\n", ret
);
2541 request
->head
= request_start
;
2543 /* Whilst this request exists, batch_obj will be on the
2544 * active_list, and so will hold the active reference. Only when this
2545 * request is retired will the the batch_obj be moved onto the
2546 * inactive_list and lose its active reference. Hence we do not need
2547 * to explicitly hold another reference here.
2549 request
->batch_obj
= obj
;
2551 request
->emitted_jiffies
= jiffies
;
2552 list_add_tail(&request
->list
, &ring
->request_list
);
2554 trace_i915_gem_request_add(request
);
2556 i915_queue_hangcheck(ring
->dev
);
2558 queue_delayed_work(dev_priv
->wq
,
2559 &dev_priv
->mm
.retire_work
,
2560 round_jiffies_up_relative(HZ
));
2561 intel_mark_busy(dev_priv
->dev
);
2563 /* Sanity check that the reserved size was large enough. */
2564 intel_ring_reserved_space_end(ringbuf
);
2567 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2568 const struct intel_context
*ctx
)
2570 unsigned long elapsed
;
2572 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2574 if (ctx
->hang_stats
.banned
)
2577 if (ctx
->hang_stats
.ban_period_seconds
&&
2578 elapsed
<= ctx
->hang_stats
.ban_period_seconds
) {
2579 if (!i915_gem_context_is_default(ctx
)) {
2580 DRM_DEBUG("context hanging too fast, banning!\n");
2582 } else if (i915_stop_ring_allow_ban(dev_priv
)) {
2583 if (i915_stop_ring_allow_warn(dev_priv
))
2584 DRM_ERROR("gpu hanging too fast, banning!\n");
2592 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2593 struct intel_context
*ctx
,
2596 struct i915_ctx_hang_stats
*hs
;
2601 hs
= &ctx
->hang_stats
;
2604 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2606 hs
->guilty_ts
= get_seconds();
2608 hs
->batch_pending
++;
2612 void i915_gem_request_free(struct kref
*req_ref
)
2614 struct drm_i915_gem_request
*req
= container_of(req_ref
,
2616 struct intel_context
*ctx
= req
->ctx
;
2619 i915_gem_request_remove_from_client(req
);
2622 if (i915
.enable_execlists
) {
2623 struct intel_engine_cs
*ring
= req
->ring
;
2625 if (ctx
!= ring
->default_context
)
2626 intel_lr_context_unpin(ring
, ctx
);
2629 i915_gem_context_unreference(ctx
);
2632 kmem_cache_free(req
->i915
->requests
, req
);
2635 int i915_gem_request_alloc(struct intel_engine_cs
*ring
,
2636 struct intel_context
*ctx
,
2637 struct drm_i915_gem_request
**req_out
)
2639 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
2640 struct drm_i915_gem_request
*req
;
2648 req
= kmem_cache_zalloc(dev_priv
->requests
, GFP_KERNEL
);
2652 ret
= i915_gem_get_seqno(ring
->dev
, &req
->seqno
);
2656 kref_init(&req
->ref
);
2657 req
->i915
= dev_priv
;
2660 i915_gem_context_reference(req
->ctx
);
2662 if (i915
.enable_execlists
)
2663 ret
= intel_logical_ring_alloc_request_extras(req
);
2665 ret
= intel_ring_alloc_request_extras(req
);
2667 i915_gem_context_unreference(req
->ctx
);
2672 * Reserve space in the ring buffer for all the commands required to
2673 * eventually emit this request. This is to guarantee that the
2674 * i915_add_request() call can't fail. Note that the reserve may need
2675 * to be redone if the request is not actually submitted straight
2676 * away, e.g. because a GPU scheduler has deferred it.
2678 if (i915
.enable_execlists
)
2679 ret
= intel_logical_ring_reserve_space(req
);
2681 ret
= intel_ring_reserve_space(req
);
2684 * At this point, the request is fully allocated even if not
2685 * fully prepared. Thus it can be cleaned up using the proper
2688 i915_gem_request_cancel(req
);
2696 kmem_cache_free(dev_priv
->requests
, req
);
2700 void i915_gem_request_cancel(struct drm_i915_gem_request
*req
)
2702 intel_ring_reserved_space_cancel(req
->ringbuf
);
2704 i915_gem_request_unreference(req
);
2707 struct drm_i915_gem_request
*
2708 i915_gem_find_active_request(struct intel_engine_cs
*ring
)
2710 struct drm_i915_gem_request
*request
;
2712 list_for_each_entry(request
, &ring
->request_list
, list
) {
2713 if (i915_gem_request_completed(request
, false))
2722 static void i915_gem_reset_ring_status(struct drm_i915_private
*dev_priv
,
2723 struct intel_engine_cs
*ring
)
2725 struct drm_i915_gem_request
*request
;
2728 request
= i915_gem_find_active_request(ring
);
2730 if (request
== NULL
)
2733 ring_hung
= ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
2735 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
2737 list_for_each_entry_continue(request
, &ring
->request_list
, list
)
2738 i915_set_reset_status(dev_priv
, request
->ctx
, false);
2741 static void i915_gem_reset_ring_cleanup(struct drm_i915_private
*dev_priv
,
2742 struct intel_engine_cs
*ring
)
2744 while (!list_empty(&ring
->active_list
)) {
2745 struct drm_i915_gem_object
*obj
;
2747 obj
= list_first_entry(&ring
->active_list
,
2748 struct drm_i915_gem_object
,
2749 ring_list
[ring
->id
]);
2751 i915_gem_object_retire__read(obj
, ring
->id
);
2755 * Clear the execlists queue up before freeing the requests, as those
2756 * are the ones that keep the context and ringbuffer backing objects
2759 while (!list_empty(&ring
->execlist_queue
)) {
2760 struct drm_i915_gem_request
*submit_req
;
2762 submit_req
= list_first_entry(&ring
->execlist_queue
,
2763 struct drm_i915_gem_request
,
2765 list_del(&submit_req
->execlist_link
);
2767 if (submit_req
->ctx
!= ring
->default_context
)
2768 intel_lr_context_unpin(ring
, submit_req
->ctx
);
2770 i915_gem_request_unreference(submit_req
);
2774 * We must free the requests after all the corresponding objects have
2775 * been moved off active lists. Which is the same order as the normal
2776 * retire_requests function does. This is important if object hold
2777 * implicit references on things like e.g. ppgtt address spaces through
2780 while (!list_empty(&ring
->request_list
)) {
2781 struct drm_i915_gem_request
*request
;
2783 request
= list_first_entry(&ring
->request_list
,
2784 struct drm_i915_gem_request
,
2787 i915_gem_request_retire(request
);
2791 void i915_gem_restore_fences(struct drm_device
*dev
)
2793 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2796 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2797 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2800 * Commit delayed tiling changes if we have an object still
2801 * attached to the fence, otherwise just clear the fence.
2804 i915_gem_object_update_fence(reg
->obj
, reg
,
2805 reg
->obj
->tiling_mode
);
2807 i915_gem_write_fence(dev
, i
, NULL
);
2812 void i915_gem_reset(struct drm_device
*dev
)
2814 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2815 struct intel_engine_cs
*ring
;
2819 * Before we free the objects from the requests, we need to inspect
2820 * them for finding the guilty party. As the requests only borrow
2821 * their reference to the objects, the inspection must be done first.
2823 for_each_ring(ring
, dev_priv
, i
)
2824 i915_gem_reset_ring_status(dev_priv
, ring
);
2826 for_each_ring(ring
, dev_priv
, i
)
2827 i915_gem_reset_ring_cleanup(dev_priv
, ring
);
2829 i915_gem_context_reset(dev
);
2831 i915_gem_restore_fences(dev
);
2833 WARN_ON(i915_verify_lists(dev
));
2837 * This function clears the request list as sequence numbers are passed.
2840 i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
)
2842 WARN_ON(i915_verify_lists(ring
->dev
));
2844 /* Retire requests first as we use it above for the early return.
2845 * If we retire requests last, we may use a later seqno and so clear
2846 * the requests lists without clearing the active list, leading to
2849 while (!list_empty(&ring
->request_list
)) {
2850 struct drm_i915_gem_request
*request
;
2852 request
= list_first_entry(&ring
->request_list
,
2853 struct drm_i915_gem_request
,
2856 if (!i915_gem_request_completed(request
, true))
2859 i915_gem_request_retire(request
);
2862 /* Move any buffers on the active list that are no longer referenced
2863 * by the ringbuffer to the flushing/inactive lists as appropriate,
2864 * before we free the context associated with the requests.
2866 while (!list_empty(&ring
->active_list
)) {
2867 struct drm_i915_gem_object
*obj
;
2869 obj
= list_first_entry(&ring
->active_list
,
2870 struct drm_i915_gem_object
,
2871 ring_list
[ring
->id
]);
2873 if (!list_empty(&obj
->last_read_req
[ring
->id
]->list
))
2876 i915_gem_object_retire__read(obj
, ring
->id
);
2879 if (unlikely(ring
->trace_irq_req
&&
2880 i915_gem_request_completed(ring
->trace_irq_req
, true))) {
2881 ring
->irq_put(ring
);
2882 i915_gem_request_assign(&ring
->trace_irq_req
, NULL
);
2885 WARN_ON(i915_verify_lists(ring
->dev
));
2889 i915_gem_retire_requests(struct drm_device
*dev
)
2891 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2892 struct intel_engine_cs
*ring
;
2896 for_each_ring(ring
, dev_priv
, i
) {
2897 i915_gem_retire_requests_ring(ring
);
2898 idle
&= list_empty(&ring
->request_list
);
2899 if (i915
.enable_execlists
) {
2900 unsigned long flags
;
2902 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
2903 idle
&= list_empty(&ring
->execlist_queue
);
2904 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
2906 intel_execlists_retire_requests(ring
);
2911 mod_delayed_work(dev_priv
->wq
,
2912 &dev_priv
->mm
.idle_work
,
2913 msecs_to_jiffies(100));
2919 i915_gem_retire_work_handler(struct work_struct
*work
)
2921 struct drm_i915_private
*dev_priv
=
2922 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
2923 struct drm_device
*dev
= dev_priv
->dev
;
2926 /* Come back later if the device is busy... */
2928 if (mutex_trylock(&dev
->struct_mutex
)) {
2929 idle
= i915_gem_retire_requests(dev
);
2930 mutex_unlock(&dev
->struct_mutex
);
2933 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2934 round_jiffies_up_relative(HZ
));
2938 i915_gem_idle_work_handler(struct work_struct
*work
)
2940 struct drm_i915_private
*dev_priv
=
2941 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
2942 struct drm_device
*dev
= dev_priv
->dev
;
2943 struct intel_engine_cs
*ring
;
2946 for_each_ring(ring
, dev_priv
, i
)
2947 if (!list_empty(&ring
->request_list
))
2950 intel_mark_idle(dev
);
2952 if (mutex_trylock(&dev
->struct_mutex
)) {
2953 struct intel_engine_cs
*ring
;
2956 for_each_ring(ring
, dev_priv
, i
)
2957 i915_gem_batch_pool_fini(&ring
->batch_pool
);
2959 mutex_unlock(&dev
->struct_mutex
);
2964 * Ensures that an object will eventually get non-busy by flushing any required
2965 * write domains, emitting any outstanding lazy request and retiring and
2966 * completed requests.
2969 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2976 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
2977 struct drm_i915_gem_request
*req
;
2979 req
= obj
->last_read_req
[i
];
2983 if (list_empty(&req
->list
))
2986 if (i915_gem_request_completed(req
, true)) {
2987 __i915_gem_request_retire__upto(req
);
2989 i915_gem_object_retire__read(obj
, i
);
2997 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2998 * @DRM_IOCTL_ARGS: standard ioctl arguments
3000 * Returns 0 if successful, else an error is returned with the remaining time in
3001 * the timeout parameter.
3002 * -ETIME: object is still busy after timeout
3003 * -ERESTARTSYS: signal interrupted the wait
3004 * -ENONENT: object doesn't exist
3005 * Also possible, but rare:
3006 * -EAGAIN: GPU wedged
3008 * -ENODEV: Internal IRQ fail
3009 * -E?: The add request failed
3011 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3012 * non-zero timeout parameter the wait ioctl will wait for the given number of
3013 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3014 * without holding struct_mutex the object may become re-busied before this
3015 * function completes. A similar but shorter * race condition exists in the busy
3019 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
3021 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3022 struct drm_i915_gem_wait
*args
= data
;
3023 struct drm_i915_gem_object
*obj
;
3024 struct drm_i915_gem_request
*req
[I915_NUM_RINGS
];
3025 unsigned reset_counter
;
3029 if (args
->flags
!= 0)
3032 ret
= i915_mutex_lock_interruptible(dev
);
3036 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
3037 if (&obj
->base
== NULL
) {
3038 mutex_unlock(&dev
->struct_mutex
);
3042 /* Need to make sure the object gets inactive eventually. */
3043 ret
= i915_gem_object_flush_active(obj
);
3050 /* Do this after OLR check to make sure we make forward progress polling
3051 * on this IOCTL with a timeout == 0 (like busy ioctl)
3053 if (args
->timeout_ns
== 0) {
3058 drm_gem_object_unreference(&obj
->base
);
3059 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3061 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
3062 if (obj
->last_read_req
[i
] == NULL
)
3065 req
[n
++] = i915_gem_request_reference(obj
->last_read_req
[i
]);
3068 mutex_unlock(&dev
->struct_mutex
);
3070 for (i
= 0; i
< n
; i
++) {
3072 ret
= __i915_wait_request(req
[i
], reset_counter
, true,
3073 args
->timeout_ns
> 0 ? &args
->timeout_ns
: NULL
,
3075 i915_gem_request_unreference__unlocked(req
[i
]);
3080 drm_gem_object_unreference(&obj
->base
);
3081 mutex_unlock(&dev
->struct_mutex
);
3086 __i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3087 struct intel_engine_cs
*to
,
3088 struct drm_i915_gem_request
*from_req
,
3089 struct drm_i915_gem_request
**to_req
)
3091 struct intel_engine_cs
*from
;
3094 from
= i915_gem_request_get_ring(from_req
);
3098 if (i915_gem_request_completed(from_req
, true))
3101 if (!i915_semaphore_is_enabled(obj
->base
.dev
)) {
3102 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
3103 ret
= __i915_wait_request(from_req
,
3104 atomic_read(&i915
->gpu_error
.reset_counter
),
3105 i915
->mm
.interruptible
,
3107 &i915
->rps
.semaphores
);
3111 i915_gem_object_retire_request(obj
, from_req
);
3113 int idx
= intel_ring_sync_index(from
, to
);
3114 u32 seqno
= i915_gem_request_get_seqno(from_req
);
3118 if (seqno
<= from
->semaphore
.sync_seqno
[idx
])
3121 if (*to_req
== NULL
) {
3122 ret
= i915_gem_request_alloc(to
, to
->default_context
, to_req
);
3127 trace_i915_gem_ring_sync_to(*to_req
, from
, from_req
);
3128 ret
= to
->semaphore
.sync_to(*to_req
, from
, seqno
);
3132 /* We use last_read_req because sync_to()
3133 * might have just caused seqno wrap under
3136 from
->semaphore
.sync_seqno
[idx
] =
3137 i915_gem_request_get_seqno(obj
->last_read_req
[from
->id
]);
3144 * i915_gem_object_sync - sync an object to a ring.
3146 * @obj: object which may be in use on another ring.
3147 * @to: ring we wish to use the object on. May be NULL.
3148 * @to_req: request we wish to use the object for. See below.
3149 * This will be allocated and returned if a request is
3150 * required but not passed in.
3152 * This code is meant to abstract object synchronization with the GPU.
3153 * Calling with NULL implies synchronizing the object with the CPU
3154 * rather than a particular GPU ring. Conceptually we serialise writes
3155 * between engines inside the GPU. We only allow one engine to write
3156 * into a buffer at any time, but multiple readers. To ensure each has
3157 * a coherent view of memory, we must:
3159 * - If there is an outstanding write request to the object, the new
3160 * request must wait for it to complete (either CPU or in hw, requests
3161 * on the same ring will be naturally ordered).
3163 * - If we are a write request (pending_write_domain is set), the new
3164 * request must wait for outstanding read requests to complete.
3166 * For CPU synchronisation (NULL to) no request is required. For syncing with
3167 * rings to_req must be non-NULL. However, a request does not have to be
3168 * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
3169 * request will be allocated automatically and returned through *to_req. Note
3170 * that it is not guaranteed that commands will be emitted (because the system
3171 * might already be idle). Hence there is no need to create a request that
3172 * might never have any work submitted. Note further that if a request is
3173 * returned in *to_req, it is the responsibility of the caller to submit
3174 * that request (after potentially adding more work to it).
3176 * Returns 0 if successful, else propagates up the lower layer error.
3179 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3180 struct intel_engine_cs
*to
,
3181 struct drm_i915_gem_request
**to_req
)
3183 const bool readonly
= obj
->base
.pending_write_domain
== 0;
3184 struct drm_i915_gem_request
*req
[I915_NUM_RINGS
];
3191 return i915_gem_object_wait_rendering(obj
, readonly
);
3195 if (obj
->last_write_req
)
3196 req
[n
++] = obj
->last_write_req
;
3198 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
3199 if (obj
->last_read_req
[i
])
3200 req
[n
++] = obj
->last_read_req
[i
];
3202 for (i
= 0; i
< n
; i
++) {
3203 ret
= __i915_gem_object_sync(obj
, to
, req
[i
], to_req
);
3211 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
3213 u32 old_write_domain
, old_read_domains
;
3215 /* Force a pagefault for domain tracking on next user access */
3216 i915_gem_release_mmap(obj
);
3218 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3221 /* Wait for any direct GTT access to complete */
3224 old_read_domains
= obj
->base
.read_domains
;
3225 old_write_domain
= obj
->base
.write_domain
;
3227 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
3228 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
3230 trace_i915_gem_object_change_domain(obj
,
3235 int i915_vma_unbind(struct i915_vma
*vma
)
3237 struct drm_i915_gem_object
*obj
= vma
->obj
;
3238 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3241 if (list_empty(&vma
->vma_link
))
3244 if (!drm_mm_node_allocated(&vma
->node
)) {
3245 i915_gem_vma_destroy(vma
);
3252 BUG_ON(obj
->pages
== NULL
);
3254 ret
= i915_gem_object_wait_rendering(obj
, false);
3257 /* Continue on if we fail due to EIO, the GPU is hung so we
3258 * should be safe and we need to cleanup or else we might
3259 * cause memory corruption through use-after-free.
3262 if (i915_is_ggtt(vma
->vm
) &&
3263 vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3264 i915_gem_object_finish_gtt(obj
);
3266 /* release the fence reg _after_ flushing */
3267 ret
= i915_gem_object_put_fence(obj
);
3272 trace_i915_vma_unbind(vma
);
3274 vma
->vm
->unbind_vma(vma
);
3277 list_del_init(&vma
->mm_list
);
3278 if (i915_is_ggtt(vma
->vm
)) {
3279 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3280 obj
->map_and_fenceable
= false;
3281 } else if (vma
->ggtt_view
.pages
) {
3282 sg_free_table(vma
->ggtt_view
.pages
);
3283 kfree(vma
->ggtt_view
.pages
);
3284 vma
->ggtt_view
.pages
= NULL
;
3288 drm_mm_remove_node(&vma
->node
);
3289 i915_gem_vma_destroy(vma
);
3291 /* Since the unbound list is global, only move to that list if
3292 * no more VMAs exist. */
3293 if (list_empty(&obj
->vma_list
)) {
3294 i915_gem_gtt_finish_object(obj
);
3295 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
3298 /* And finally now the object is completely decoupled from this vma,
3299 * we can drop its hold on the backing storage and allow it to be
3300 * reaped by the shrinker.
3302 i915_gem_object_unpin_pages(obj
);
3307 int i915_gpu_idle(struct drm_device
*dev
)
3309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3310 struct intel_engine_cs
*ring
;
3313 /* Flush everything onto the inactive list. */
3314 for_each_ring(ring
, dev_priv
, i
) {
3315 if (!i915
.enable_execlists
) {
3316 struct drm_i915_gem_request
*req
;
3318 ret
= i915_gem_request_alloc(ring
, ring
->default_context
, &req
);
3322 ret
= i915_switch_context(req
);
3324 i915_gem_request_cancel(req
);
3328 i915_add_request_no_flush(req
);
3331 ret
= intel_ring_idle(ring
);
3336 WARN_ON(i915_verify_lists(dev
));
3340 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
3341 struct drm_i915_gem_object
*obj
)
3343 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3345 int fence_pitch_shift
;
3347 if (INTEL_INFO(dev
)->gen
>= 6) {
3348 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
3349 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
3351 fence_reg
= FENCE_REG_965_0
;
3352 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
3355 fence_reg
+= reg
* 8;
3357 /* To w/a incoherency with non-atomic 64-bit register updates,
3358 * we split the 64-bit update into two 32-bit writes. In order
3359 * for a partial fence not to be evaluated between writes, we
3360 * precede the update with write to turn off the fence register,
3361 * and only enable the fence as the last step.
3363 * For extra levels of paranoia, we make sure each step lands
3364 * before applying the next step.
3366 I915_WRITE(fence_reg
, 0);
3367 POSTING_READ(fence_reg
);
3370 u32 size
= i915_gem_obj_ggtt_size(obj
);
3373 /* Adjust fence size to match tiled area */
3374 if (obj
->tiling_mode
!= I915_TILING_NONE
) {
3375 uint32_t row_size
= obj
->stride
*
3376 (obj
->tiling_mode
== I915_TILING_Y
? 32 : 8);
3377 size
= (size
/ row_size
) * row_size
;
3380 val
= (uint64_t)((i915_gem_obj_ggtt_offset(obj
) + size
- 4096) &
3382 val
|= i915_gem_obj_ggtt_offset(obj
) & 0xfffff000;
3383 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
3384 if (obj
->tiling_mode
== I915_TILING_Y
)
3385 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
3386 val
|= I965_FENCE_REG_VALID
;
3388 I915_WRITE(fence_reg
+ 4, val
>> 32);
3389 POSTING_READ(fence_reg
+ 4);
3391 I915_WRITE(fence_reg
+ 0, val
);
3392 POSTING_READ(fence_reg
);
3394 I915_WRITE(fence_reg
+ 4, 0);
3395 POSTING_READ(fence_reg
+ 4);
3399 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
3400 struct drm_i915_gem_object
*obj
)
3402 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3406 u32 size
= i915_gem_obj_ggtt_size(obj
);
3410 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I915_FENCE_START_MASK
) ||
3411 (size
& -size
) != size
||
3412 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3413 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3414 i915_gem_obj_ggtt_offset(obj
), obj
->map_and_fenceable
, size
);
3416 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
3421 /* Note: pitch better be a power of two tile widths */
3422 pitch_val
= obj
->stride
/ tile_width
;
3423 pitch_val
= ffs(pitch_val
) - 1;
3425 val
= i915_gem_obj_ggtt_offset(obj
);
3426 if (obj
->tiling_mode
== I915_TILING_Y
)
3427 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3428 val
|= I915_FENCE_SIZE_BITS(size
);
3429 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3430 val
|= I830_FENCE_REG_VALID
;
3435 reg
= FENCE_REG_830_0
+ reg
* 4;
3437 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
3439 I915_WRITE(reg
, val
);
3443 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
3444 struct drm_i915_gem_object
*obj
)
3446 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3450 u32 size
= i915_gem_obj_ggtt_size(obj
);
3453 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I830_FENCE_START_MASK
) ||
3454 (size
& -size
) != size
||
3455 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3456 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3457 i915_gem_obj_ggtt_offset(obj
), size
);
3459 pitch_val
= obj
->stride
/ 128;
3460 pitch_val
= ffs(pitch_val
) - 1;
3462 val
= i915_gem_obj_ggtt_offset(obj
);
3463 if (obj
->tiling_mode
== I915_TILING_Y
)
3464 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3465 val
|= I830_FENCE_SIZE_BITS(size
);
3466 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3467 val
|= I830_FENCE_REG_VALID
;
3471 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
3472 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
3475 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
3477 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
3480 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
3481 struct drm_i915_gem_object
*obj
)
3483 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3485 /* Ensure that all CPU reads are completed before installing a fence
3486 * and all writes before removing the fence.
3488 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
3491 WARN(obj
&& (!obj
->stride
|| !obj
->tiling_mode
),
3492 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3493 obj
->stride
, obj
->tiling_mode
);
3496 i830_write_fence_reg(dev
, reg
, obj
);
3497 else if (IS_GEN3(dev
))
3498 i915_write_fence_reg(dev
, reg
, obj
);
3499 else if (INTEL_INFO(dev
)->gen
>= 4)
3500 i965_write_fence_reg(dev
, reg
, obj
);
3502 /* And similarly be paranoid that no direct access to this region
3503 * is reordered to before the fence is installed.
3505 if (i915_gem_object_needs_mb(obj
))
3509 static inline int fence_number(struct drm_i915_private
*dev_priv
,
3510 struct drm_i915_fence_reg
*fence
)
3512 return fence
- dev_priv
->fence_regs
;
3515 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
3516 struct drm_i915_fence_reg
*fence
,
3519 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3520 int reg
= fence_number(dev_priv
, fence
);
3522 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
3525 obj
->fence_reg
= reg
;
3527 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
3529 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3531 list_del_init(&fence
->lru_list
);
3533 obj
->fence_dirty
= false;
3537 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
3539 if (obj
->last_fenced_req
) {
3540 int ret
= i915_wait_request(obj
->last_fenced_req
);
3544 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
3551 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
3553 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3554 struct drm_i915_fence_reg
*fence
;
3557 ret
= i915_gem_object_wait_fence(obj
);
3561 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
3564 fence
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3566 if (WARN_ON(fence
->pin_count
))
3569 i915_gem_object_fence_lost(obj
);
3570 i915_gem_object_update_fence(obj
, fence
, false);
3575 static struct drm_i915_fence_reg
*
3576 i915_find_fence_reg(struct drm_device
*dev
)
3578 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3579 struct drm_i915_fence_reg
*reg
, *avail
;
3582 /* First try to find a free reg */
3584 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
3585 reg
= &dev_priv
->fence_regs
[i
];
3589 if (!reg
->pin_count
)
3596 /* None available, try to steal one or wait for a user to finish */
3597 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
3605 /* Wait for completion of pending flips which consume fences */
3606 if (intel_has_pending_fb_unpin(dev
))
3607 return ERR_PTR(-EAGAIN
);
3609 return ERR_PTR(-EDEADLK
);
3613 * i915_gem_object_get_fence - set up fencing for an object
3614 * @obj: object to map through a fence reg
3616 * When mapping objects through the GTT, userspace wants to be able to write
3617 * to them without having to worry about swizzling if the object is tiled.
3618 * This function walks the fence regs looking for a free one for @obj,
3619 * stealing one if it can't find any.
3621 * It then sets up the reg based on the object's properties: address, pitch
3622 * and tiling format.
3624 * For an untiled surface, this removes any existing fence.
3627 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
3629 struct drm_device
*dev
= obj
->base
.dev
;
3630 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3631 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
3632 struct drm_i915_fence_reg
*reg
;
3635 /* Have we updated the tiling parameters upon the object and so
3636 * will need to serialise the write to the associated fence register?
3638 if (obj
->fence_dirty
) {
3639 ret
= i915_gem_object_wait_fence(obj
);
3644 /* Just update our place in the LRU if our fence is getting reused. */
3645 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
3646 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3647 if (!obj
->fence_dirty
) {
3648 list_move_tail(®
->lru_list
,
3649 &dev_priv
->mm
.fence_list
);
3652 } else if (enable
) {
3653 if (WARN_ON(!obj
->map_and_fenceable
))
3656 reg
= i915_find_fence_reg(dev
);
3658 return PTR_ERR(reg
);
3661 struct drm_i915_gem_object
*old
= reg
->obj
;
3663 ret
= i915_gem_object_wait_fence(old
);
3667 i915_gem_object_fence_lost(old
);
3672 i915_gem_object_update_fence(obj
, reg
, enable
);
3677 static bool i915_gem_valid_gtt_space(struct i915_vma
*vma
,
3678 unsigned long cache_level
)
3680 struct drm_mm_node
*gtt_space
= &vma
->node
;
3681 struct drm_mm_node
*other
;
3684 * On some machines we have to be careful when putting differing types
3685 * of snoopable memory together to avoid the prefetcher crossing memory
3686 * domains and dying. During vm initialisation, we decide whether or not
3687 * these constraints apply and set the drm_mm.color_adjust
3690 if (vma
->vm
->mm
.color_adjust
== NULL
)
3693 if (!drm_mm_node_allocated(gtt_space
))
3696 if (list_empty(>t_space
->node_list
))
3699 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3700 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3703 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3704 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3711 * Finds free space in the GTT aperture and binds the object or a view of it
3714 static struct i915_vma
*
3715 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3716 struct i915_address_space
*vm
,
3717 const struct i915_ggtt_view
*ggtt_view
,
3721 struct drm_device
*dev
= obj
->base
.dev
;
3722 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3723 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
3725 flags
& PIN_OFFSET_BIAS
? flags
& PIN_OFFSET_MASK
: 0;
3727 flags
& PIN_MAPPABLE
? dev_priv
->gtt
.mappable_end
: vm
->total
;
3728 struct i915_vma
*vma
;
3731 if (i915_is_ggtt(vm
)) {
3734 if (WARN_ON(!ggtt_view
))
3735 return ERR_PTR(-EINVAL
);
3737 view_size
= i915_ggtt_view_size(obj
, ggtt_view
);
3739 fence_size
= i915_gem_get_gtt_size(dev
,
3742 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3746 unfenced_alignment
= i915_gem_get_gtt_alignment(dev
,
3750 size
= flags
& PIN_MAPPABLE
? fence_size
: view_size
;
3752 fence_size
= i915_gem_get_gtt_size(dev
,
3755 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3759 unfenced_alignment
=
3760 i915_gem_get_gtt_alignment(dev
,
3764 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3768 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3770 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3771 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3772 ggtt_view
? ggtt_view
->type
: 0,
3774 return ERR_PTR(-EINVAL
);
3777 /* If binding the object/GGTT view requires more space than the entire
3778 * aperture has, reject it early before evicting everything in a vain
3779 * attempt to find space.
3782 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%u > %s aperture=%llu\n",
3783 ggtt_view
? ggtt_view
->type
: 0,
3785 flags
& PIN_MAPPABLE
? "mappable" : "total",
3787 return ERR_PTR(-E2BIG
);
3790 ret
= i915_gem_object_get_pages(obj
);
3792 return ERR_PTR(ret
);
3794 i915_gem_object_pin_pages(obj
);
3796 vma
= ggtt_view
? i915_gem_obj_lookup_or_create_ggtt_vma(obj
, ggtt_view
) :
3797 i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3803 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3807 DRM_MM_SEARCH_DEFAULT
,
3808 DRM_MM_CREATE_DEFAULT
);
3810 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3819 if (WARN_ON(!i915_gem_valid_gtt_space(vma
, obj
->cache_level
))) {
3821 goto err_remove_node
;
3824 ret
= i915_gem_gtt_prepare_object(obj
);
3826 goto err_remove_node
;
3828 trace_i915_vma_bind(vma
, flags
);
3829 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
3831 goto err_finish_gtt
;
3833 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3834 list_add_tail(&vma
->mm_list
, &vm
->inactive_list
);
3839 i915_gem_gtt_finish_object(obj
);
3841 drm_mm_remove_node(&vma
->node
);
3843 i915_gem_vma_destroy(vma
);
3846 i915_gem_object_unpin_pages(obj
);
3851 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3854 /* If we don't have a page list set up, then we're not pinned
3855 * to GPU, and we can ignore the cache flush because it'll happen
3856 * again at bind time.
3858 if (obj
->pages
== NULL
)
3862 * Stolen memory is always coherent with the GPU as it is explicitly
3863 * marked as wc by the system, or the system is cache-coherent.
3865 if (obj
->stolen
|| obj
->phys_handle
)
3868 /* If the GPU is snooping the contents of the CPU cache,
3869 * we do not need to manually clear the CPU cache lines. However,
3870 * the caches are only snooped when the render cache is
3871 * flushed/invalidated. As we always have to emit invalidations
3872 * and flushes when moving into and out of the RENDER domain, correct
3873 * snooping behaviour occurs naturally as the result of our domain
3876 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
)) {
3877 obj
->cache_dirty
= true;
3881 trace_i915_gem_object_clflush(obj
);
3882 drm_clflush_sg(obj
->pages
);
3883 obj
->cache_dirty
= false;
3888 /** Flushes the GTT write domain for the object if it's dirty. */
3890 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3892 uint32_t old_write_domain
;
3894 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3897 /* No actual flushing is required for the GTT write domain. Writes
3898 * to it immediately go to main memory as far as we know, so there's
3899 * no chipset flush. It also doesn't land in render cache.
3901 * However, we do have to enforce the order so that all writes through
3902 * the GTT land before any writes to the device, such as updates to
3907 old_write_domain
= obj
->base
.write_domain
;
3908 obj
->base
.write_domain
= 0;
3910 intel_fb_obj_flush(obj
, false);
3912 trace_i915_gem_object_change_domain(obj
,
3913 obj
->base
.read_domains
,
3917 /** Flushes the CPU write domain for the object if it's dirty. */
3919 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3921 uint32_t old_write_domain
;
3923 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3926 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
3927 i915_gem_chipset_flush(obj
->base
.dev
);
3929 old_write_domain
= obj
->base
.write_domain
;
3930 obj
->base
.write_domain
= 0;
3932 intel_fb_obj_flush(obj
, false);
3934 trace_i915_gem_object_change_domain(obj
,
3935 obj
->base
.read_domains
,
3940 * Moves a single object to the GTT read, and possibly write domain.
3942 * This function returns when the move is complete, including waiting on
3946 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3948 uint32_t old_write_domain
, old_read_domains
;
3949 struct i915_vma
*vma
;
3952 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3955 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3959 /* Flush and acquire obj->pages so that we are coherent through
3960 * direct access in memory with previous cached writes through
3961 * shmemfs and that our cache domain tracking remains valid.
3962 * For example, if the obj->filp was moved to swap without us
3963 * being notified and releasing the pages, we would mistakenly
3964 * continue to assume that the obj remained out of the CPU cached
3967 ret
= i915_gem_object_get_pages(obj
);
3971 i915_gem_object_flush_cpu_write_domain(obj
);
3973 /* Serialise direct access to this object with the barriers for
3974 * coherent writes from the GPU, by effectively invalidating the
3975 * GTT domain upon first access.
3977 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3980 old_write_domain
= obj
->base
.write_domain
;
3981 old_read_domains
= obj
->base
.read_domains
;
3983 /* It should now be out of any other write domains, and we can update
3984 * the domain values for our changes.
3986 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3987 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3989 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3990 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3994 trace_i915_gem_object_change_domain(obj
,
3998 /* And bump the LRU for this access */
3999 vma
= i915_gem_obj_to_ggtt(obj
);
4000 if (vma
&& drm_mm_node_allocated(&vma
->node
) && !obj
->active
)
4001 list_move_tail(&vma
->mm_list
,
4002 &to_i915(obj
->base
.dev
)->gtt
.base
.inactive_list
);
4007 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
4008 enum i915_cache_level cache_level
)
4010 struct drm_device
*dev
= obj
->base
.dev
;
4011 struct i915_vma
*vma
, *next
;
4014 if (obj
->cache_level
== cache_level
)
4017 if (i915_gem_obj_is_pinned(obj
)) {
4018 DRM_DEBUG("can not change the cache level of pinned objects\n");
4022 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4023 if (!i915_gem_valid_gtt_space(vma
, cache_level
)) {
4024 ret
= i915_vma_unbind(vma
);
4030 if (i915_gem_obj_bound_any(obj
)) {
4031 ret
= i915_gem_object_wait_rendering(obj
, false);
4035 i915_gem_object_finish_gtt(obj
);
4037 /* Before SandyBridge, you could not use tiling or fence
4038 * registers with snooped memory, so relinquish any fences
4039 * currently pointing to our region in the aperture.
4041 if (INTEL_INFO(dev
)->gen
< 6) {
4042 ret
= i915_gem_object_put_fence(obj
);
4047 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4048 if (drm_mm_node_allocated(&vma
->node
)) {
4049 ret
= i915_vma_bind(vma
, cache_level
,
4056 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4057 vma
->node
.color
= cache_level
;
4058 obj
->cache_level
= cache_level
;
4060 if (obj
->cache_dirty
&&
4061 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
4062 cpu_write_needs_clflush(obj
)) {
4063 if (i915_gem_clflush_object(obj
, true))
4064 i915_gem_chipset_flush(obj
->base
.dev
);
4070 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
4071 struct drm_file
*file
)
4073 struct drm_i915_gem_caching
*args
= data
;
4074 struct drm_i915_gem_object
*obj
;
4076 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4077 if (&obj
->base
== NULL
)
4080 switch (obj
->cache_level
) {
4081 case I915_CACHE_LLC
:
4082 case I915_CACHE_L3_LLC
:
4083 args
->caching
= I915_CACHING_CACHED
;
4087 args
->caching
= I915_CACHING_DISPLAY
;
4091 args
->caching
= I915_CACHING_NONE
;
4095 drm_gem_object_unreference_unlocked(&obj
->base
);
4099 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
4100 struct drm_file
*file
)
4102 struct drm_i915_gem_caching
*args
= data
;
4103 struct drm_i915_gem_object
*obj
;
4104 enum i915_cache_level level
;
4107 switch (args
->caching
) {
4108 case I915_CACHING_NONE
:
4109 level
= I915_CACHE_NONE
;
4111 case I915_CACHING_CACHED
:
4112 level
= I915_CACHE_LLC
;
4114 case I915_CACHING_DISPLAY
:
4115 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
4121 ret
= i915_mutex_lock_interruptible(dev
);
4125 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4126 if (&obj
->base
== NULL
) {
4131 ret
= i915_gem_object_set_cache_level(obj
, level
);
4133 drm_gem_object_unreference(&obj
->base
);
4135 mutex_unlock(&dev
->struct_mutex
);
4140 * Prepare buffer for display plane (scanout, cursors, etc).
4141 * Can be called from an uninterruptible phase (modesetting) and allows
4142 * any flushes to be pipelined (for pageflips).
4145 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
4147 struct intel_engine_cs
*pipelined
,
4148 struct drm_i915_gem_request
**pipelined_request
,
4149 const struct i915_ggtt_view
*view
)
4151 u32 old_read_domains
, old_write_domain
;
4154 ret
= i915_gem_object_sync(obj
, pipelined
, pipelined_request
);
4158 /* Mark the pin_display early so that we account for the
4159 * display coherency whilst setting up the cache domains.
4163 /* The display engine is not coherent with the LLC cache on gen6. As
4164 * a result, we make sure that the pinning that is about to occur is
4165 * done with uncached PTEs. This is lowest common denominator for all
4168 * However for gen6+, we could do better by using the GFDT bit instead
4169 * of uncaching, which would allow us to flush all the LLC-cached data
4170 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4172 ret
= i915_gem_object_set_cache_level(obj
,
4173 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
4175 goto err_unpin_display
;
4177 /* As the user may map the buffer once pinned in the display plane
4178 * (e.g. libkms for the bootup splash), we have to ensure that we
4179 * always use map_and_fenceable for all scanout buffers.
4181 ret
= i915_gem_object_ggtt_pin(obj
, view
, alignment
,
4182 view
->type
== I915_GGTT_VIEW_NORMAL
?
4185 goto err_unpin_display
;
4187 i915_gem_object_flush_cpu_write_domain(obj
);
4189 old_write_domain
= obj
->base
.write_domain
;
4190 old_read_domains
= obj
->base
.read_domains
;
4192 /* It should now be out of any other write domains, and we can update
4193 * the domain values for our changes.
4195 obj
->base
.write_domain
= 0;
4196 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
4198 trace_i915_gem_object_change_domain(obj
,
4210 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
4211 const struct i915_ggtt_view
*view
)
4213 if (WARN_ON(obj
->pin_display
== 0))
4216 i915_gem_object_ggtt_unpin_view(obj
, view
);
4222 * Moves a single object to the CPU read, and possibly write domain.
4224 * This function returns when the move is complete, including waiting on
4228 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
4230 uint32_t old_write_domain
, old_read_domains
;
4233 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
4236 ret
= i915_gem_object_wait_rendering(obj
, !write
);
4240 i915_gem_object_flush_gtt_write_domain(obj
);
4242 old_write_domain
= obj
->base
.write_domain
;
4243 old_read_domains
= obj
->base
.read_domains
;
4245 /* Flush the CPU cache if it's still invalid. */
4246 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
4247 i915_gem_clflush_object(obj
, false);
4249 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
4252 /* It should now be out of any other write domains, and we can update
4253 * the domain values for our changes.
4255 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
4257 /* If we're writing through the CPU, then the GPU read domains will
4258 * need to be invalidated at next use.
4261 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4262 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4265 trace_i915_gem_object_change_domain(obj
,
4272 /* Throttle our rendering by waiting until the ring has completed our requests
4273 * emitted over 20 msec ago.
4275 * Note that if we were to use the current jiffies each time around the loop,
4276 * we wouldn't escape the function with any frames outstanding if the time to
4277 * render a frame was over 20ms.
4279 * This should get us reasonable parallelism between CPU and GPU but also
4280 * relatively low latency when blocking on a particular request to finish.
4283 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
4285 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4286 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4287 unsigned long recent_enough
= jiffies
- DRM_I915_THROTTLE_JIFFIES
;
4288 struct drm_i915_gem_request
*request
, *target
= NULL
;
4289 unsigned reset_counter
;
4292 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
4296 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
4300 spin_lock(&file_priv
->mm
.lock
);
4301 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
4302 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
4306 * Note that the request might not have been submitted yet.
4307 * In which case emitted_jiffies will be zero.
4309 if (!request
->emitted_jiffies
)
4314 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
4316 i915_gem_request_reference(target
);
4317 spin_unlock(&file_priv
->mm
.lock
);
4322 ret
= __i915_wait_request(target
, reset_counter
, true, NULL
, NULL
);
4324 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
4326 i915_gem_request_unreference__unlocked(target
);
4332 i915_vma_misplaced(struct i915_vma
*vma
, uint32_t alignment
, uint64_t flags
)
4334 struct drm_i915_gem_object
*obj
= vma
->obj
;
4337 vma
->node
.start
& (alignment
- 1))
4340 if (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)
4343 if (flags
& PIN_OFFSET_BIAS
&&
4344 vma
->node
.start
< (flags
& PIN_OFFSET_MASK
))
4351 i915_gem_object_do_pin(struct drm_i915_gem_object
*obj
,
4352 struct i915_address_space
*vm
,
4353 const struct i915_ggtt_view
*ggtt_view
,
4357 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4358 struct i915_vma
*vma
;
4362 if (WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
))
4365 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
4368 if (WARN_ON((flags
& (PIN_MAPPABLE
| PIN_GLOBAL
)) == PIN_MAPPABLE
))
4371 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
4374 vma
= ggtt_view
? i915_gem_obj_to_ggtt_view(obj
, ggtt_view
) :
4375 i915_gem_obj_to_vma(obj
, vm
);
4378 return PTR_ERR(vma
);
4381 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
4384 if (i915_vma_misplaced(vma
, alignment
, flags
)) {
4385 unsigned long offset
;
4386 offset
= ggtt_view
? i915_gem_obj_ggtt_offset_view(obj
, ggtt_view
) :
4387 i915_gem_obj_offset(obj
, vm
);
4388 WARN(vma
->pin_count
,
4389 "bo is already pinned in %s with incorrect alignment:"
4390 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4391 " obj->map_and_fenceable=%d\n",
4392 ggtt_view
? "ggtt" : "ppgtt",
4395 !!(flags
& PIN_MAPPABLE
),
4396 obj
->map_and_fenceable
);
4397 ret
= i915_vma_unbind(vma
);
4405 bound
= vma
? vma
->bound
: 0;
4406 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
4407 vma
= i915_gem_object_bind_to_vm(obj
, vm
, ggtt_view
, alignment
,
4410 return PTR_ERR(vma
);
4412 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
4417 if (ggtt_view
&& ggtt_view
->type
== I915_GGTT_VIEW_NORMAL
&&
4418 (bound
^ vma
->bound
) & GLOBAL_BIND
) {
4419 bool mappable
, fenceable
;
4420 u32 fence_size
, fence_alignment
;
4422 fence_size
= i915_gem_get_gtt_size(obj
->base
.dev
,
4425 fence_alignment
= i915_gem_get_gtt_alignment(obj
->base
.dev
,
4430 fenceable
= (vma
->node
.size
== fence_size
&&
4431 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
4433 mappable
= (vma
->node
.start
+ fence_size
<=
4434 dev_priv
->gtt
.mappable_end
);
4436 obj
->map_and_fenceable
= mappable
&& fenceable
;
4438 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
4446 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
4447 struct i915_address_space
*vm
,
4451 return i915_gem_object_do_pin(obj
, vm
,
4452 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
,
4457 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
4458 const struct i915_ggtt_view
*view
,
4462 if (WARN_ONCE(!view
, "no view specified"))
4465 return i915_gem_object_do_pin(obj
, i915_obj_to_ggtt(obj
), view
,
4466 alignment
, flags
| PIN_GLOBAL
);
4470 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
4471 const struct i915_ggtt_view
*view
)
4473 struct i915_vma
*vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
4476 WARN_ON(vma
->pin_count
== 0);
4477 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj
, view
));
4483 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
4485 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4486 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4487 struct i915_vma
*ggtt_vma
= i915_gem_obj_to_ggtt(obj
);
4489 WARN_ON(!ggtt_vma
||
4490 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
>
4491 ggtt_vma
->pin_count
);
4492 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
4499 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
4501 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4502 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4503 WARN_ON(dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
<= 0);
4504 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
4509 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4510 struct drm_file
*file
)
4512 struct drm_i915_gem_busy
*args
= data
;
4513 struct drm_i915_gem_object
*obj
;
4516 ret
= i915_mutex_lock_interruptible(dev
);
4520 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4521 if (&obj
->base
== NULL
) {
4526 /* Count all active objects as busy, even if they are currently not used
4527 * by the gpu. Users of this interface expect objects to eventually
4528 * become non-busy without any further actions, therefore emit any
4529 * necessary flushes here.
4531 ret
= i915_gem_object_flush_active(obj
);
4535 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
4536 args
->busy
= obj
->active
<< 16;
4537 if (obj
->last_write_req
)
4538 args
->busy
|= obj
->last_write_req
->ring
->id
;
4541 drm_gem_object_unreference(&obj
->base
);
4543 mutex_unlock(&dev
->struct_mutex
);
4548 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4549 struct drm_file
*file_priv
)
4551 return i915_gem_ring_throttle(dev
, file_priv
);
4555 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4556 struct drm_file
*file_priv
)
4558 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4559 struct drm_i915_gem_madvise
*args
= data
;
4560 struct drm_i915_gem_object
*obj
;
4563 switch (args
->madv
) {
4564 case I915_MADV_DONTNEED
:
4565 case I915_MADV_WILLNEED
:
4571 ret
= i915_mutex_lock_interruptible(dev
);
4575 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
4576 if (&obj
->base
== NULL
) {
4581 if (i915_gem_obj_is_pinned(obj
)) {
4587 obj
->tiling_mode
!= I915_TILING_NONE
&&
4588 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
4589 if (obj
->madv
== I915_MADV_WILLNEED
)
4590 i915_gem_object_unpin_pages(obj
);
4591 if (args
->madv
== I915_MADV_WILLNEED
)
4592 i915_gem_object_pin_pages(obj
);
4595 if (obj
->madv
!= __I915_MADV_PURGED
)
4596 obj
->madv
= args
->madv
;
4598 /* if the object is no longer attached, discard its backing storage */
4599 if (obj
->madv
== I915_MADV_DONTNEED
&& obj
->pages
== NULL
)
4600 i915_gem_object_truncate(obj
);
4602 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4605 drm_gem_object_unreference(&obj
->base
);
4607 mutex_unlock(&dev
->struct_mutex
);
4611 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4612 const struct drm_i915_gem_object_ops
*ops
)
4616 INIT_LIST_HEAD(&obj
->global_list
);
4617 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4618 INIT_LIST_HEAD(&obj
->ring_list
[i
]);
4619 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4620 INIT_LIST_HEAD(&obj
->vma_list
);
4621 INIT_LIST_HEAD(&obj
->batch_pool_link
);
4625 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4626 obj
->madv
= I915_MADV_WILLNEED
;
4628 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4631 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4632 .get_pages
= i915_gem_object_get_pages_gtt
,
4633 .put_pages
= i915_gem_object_put_pages_gtt
,
4636 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
4639 struct drm_i915_gem_object
*obj
;
4640 struct address_space
*mapping
;
4643 obj
= i915_gem_object_alloc(dev
);
4647 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4648 i915_gem_object_free(obj
);
4652 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4653 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4654 /* 965gm cannot relocate objects above 4GiB. */
4655 mask
&= ~__GFP_HIGHMEM
;
4656 mask
|= __GFP_DMA32
;
4659 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4660 mapping_set_gfp_mask(mapping
, mask
);
4662 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4664 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4665 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4668 /* On some devices, we can have the GPU use the LLC (the CPU
4669 * cache) for about a 10% performance improvement
4670 * compared to uncached. Graphics requests other than
4671 * display scanout are coherent with the CPU in
4672 * accessing this cache. This means in this mode we
4673 * don't need to clflush on the CPU side, and on the
4674 * GPU side we only need to flush internal caches to
4675 * get data visible to the CPU.
4677 * However, we maintain the display planes as UC, and so
4678 * need to rebind when first used as such.
4680 obj
->cache_level
= I915_CACHE_LLC
;
4682 obj
->cache_level
= I915_CACHE_NONE
;
4684 trace_i915_gem_object_create(obj
);
4689 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4691 /* If we are the last user of the backing storage (be it shmemfs
4692 * pages or stolen etc), we know that the pages are going to be
4693 * immediately released. In this case, we can then skip copying
4694 * back the contents from the GPU.
4697 if (obj
->madv
!= I915_MADV_WILLNEED
)
4700 if (obj
->base
.filp
== NULL
)
4703 /* At first glance, this looks racy, but then again so would be
4704 * userspace racing mmap against close. However, the first external
4705 * reference to the filp can only be obtained through the
4706 * i915_gem_mmap_ioctl() which safeguards us against the user
4707 * acquiring such a reference whilst we are in the middle of
4708 * freeing the object.
4710 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4713 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4715 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4716 struct drm_device
*dev
= obj
->base
.dev
;
4717 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4718 struct i915_vma
*vma
, *next
;
4720 intel_runtime_pm_get(dev_priv
);
4722 trace_i915_gem_object_destroy(obj
);
4724 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4728 ret
= i915_vma_unbind(vma
);
4729 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4730 bool was_interruptible
;
4732 was_interruptible
= dev_priv
->mm
.interruptible
;
4733 dev_priv
->mm
.interruptible
= false;
4735 WARN_ON(i915_vma_unbind(vma
));
4737 dev_priv
->mm
.interruptible
= was_interruptible
;
4741 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4742 * before progressing. */
4744 i915_gem_object_unpin_pages(obj
);
4746 WARN_ON(obj
->frontbuffer_bits
);
4748 if (obj
->pages
&& obj
->madv
== I915_MADV_WILLNEED
&&
4749 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
&&
4750 obj
->tiling_mode
!= I915_TILING_NONE
)
4751 i915_gem_object_unpin_pages(obj
);
4753 if (WARN_ON(obj
->pages_pin_count
))
4754 obj
->pages_pin_count
= 0;
4755 if (discard_backing_storage(obj
))
4756 obj
->madv
= I915_MADV_DONTNEED
;
4757 i915_gem_object_put_pages(obj
);
4758 i915_gem_object_free_mmap_offset(obj
);
4762 if (obj
->base
.import_attach
)
4763 drm_prime_gem_destroy(&obj
->base
, NULL
);
4765 if (obj
->ops
->release
)
4766 obj
->ops
->release(obj
);
4768 drm_gem_object_release(&obj
->base
);
4769 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4772 i915_gem_object_free(obj
);
4774 intel_runtime_pm_put(dev_priv
);
4777 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4778 struct i915_address_space
*vm
)
4780 struct i915_vma
*vma
;
4781 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
4782 if (i915_is_ggtt(vma
->vm
) &&
4783 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
4791 struct i915_vma
*i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
4792 const struct i915_ggtt_view
*view
)
4794 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
4795 struct i915_vma
*vma
;
4797 if (WARN_ONCE(!view
, "no view specified"))
4798 return ERR_PTR(-EINVAL
);
4800 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4801 if (vma
->vm
== ggtt
&&
4802 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
4807 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4809 struct i915_address_space
*vm
= NULL
;
4810 WARN_ON(vma
->node
.allocated
);
4812 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4813 if (!list_empty(&vma
->exec_list
))
4818 if (!i915_is_ggtt(vm
))
4819 i915_ppgtt_put(i915_vm_to_ppgtt(vm
));
4821 list_del(&vma
->vma_link
);
4823 kmem_cache_free(to_i915(vma
->obj
->base
.dev
)->vmas
, vma
);
4827 i915_gem_stop_ringbuffers(struct drm_device
*dev
)
4829 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4830 struct intel_engine_cs
*ring
;
4833 for_each_ring(ring
, dev_priv
, i
)
4834 dev_priv
->gt
.stop_ring(ring
);
4838 i915_gem_suspend(struct drm_device
*dev
)
4840 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4843 mutex_lock(&dev
->struct_mutex
);
4844 ret
= i915_gpu_idle(dev
);
4848 i915_gem_retire_requests(dev
);
4850 i915_gem_stop_ringbuffers(dev
);
4851 mutex_unlock(&dev
->struct_mutex
);
4853 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
4854 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4855 flush_delayed_work(&dev_priv
->mm
.idle_work
);
4857 /* Assert that we sucessfully flushed all the work and
4858 * reset the GPU back to its idle, low power state.
4860 WARN_ON(dev_priv
->mm
.busy
);
4865 mutex_unlock(&dev
->struct_mutex
);
4869 int i915_gem_l3_remap(struct drm_i915_gem_request
*req
, int slice
)
4871 struct intel_engine_cs
*ring
= req
->ring
;
4872 struct drm_device
*dev
= ring
->dev
;
4873 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4874 u32 reg_base
= GEN7_L3LOG_BASE
+ (slice
* 0x200);
4875 u32
*remap_info
= dev_priv
->l3_parity
.remap_info
[slice
];
4878 if (!HAS_L3_DPF(dev
) || !remap_info
)
4881 ret
= intel_ring_begin(req
, GEN7_L3LOG_SIZE
/ 4 * 3);
4886 * Note: We do not worry about the concurrent register cacheline hang
4887 * here because no other code should access these registers other than
4888 * at initialization time.
4890 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
4891 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
4892 intel_ring_emit(ring
, reg_base
+ i
);
4893 intel_ring_emit(ring
, remap_info
[i
/4]);
4896 intel_ring_advance(ring
);
4901 void i915_gem_init_swizzling(struct drm_device
*dev
)
4903 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4905 if (INTEL_INFO(dev
)->gen
< 5 ||
4906 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4909 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4910 DISP_TILE_SURFACE_SWIZZLING
);
4915 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4917 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4918 else if (IS_GEN7(dev
))
4919 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4920 else if (IS_GEN8(dev
))
4921 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4927 intel_enable_blt(struct drm_device
*dev
)
4932 /* The blitter was dysfunctional on early prototypes */
4933 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
4934 DRM_INFO("BLT not supported on this pre-production hardware;"
4935 " graphics performance will be degraded.\n");
4942 static void init_unused_ring(struct drm_device
*dev
, u32 base
)
4944 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4946 I915_WRITE(RING_CTL(base
), 0);
4947 I915_WRITE(RING_HEAD(base
), 0);
4948 I915_WRITE(RING_TAIL(base
), 0);
4949 I915_WRITE(RING_START(base
), 0);
4952 static void init_unused_rings(struct drm_device
*dev
)
4955 init_unused_ring(dev
, PRB1_BASE
);
4956 init_unused_ring(dev
, SRB0_BASE
);
4957 init_unused_ring(dev
, SRB1_BASE
);
4958 init_unused_ring(dev
, SRB2_BASE
);
4959 init_unused_ring(dev
, SRB3_BASE
);
4960 } else if (IS_GEN2(dev
)) {
4961 init_unused_ring(dev
, SRB0_BASE
);
4962 init_unused_ring(dev
, SRB1_BASE
);
4963 } else if (IS_GEN3(dev
)) {
4964 init_unused_ring(dev
, PRB1_BASE
);
4965 init_unused_ring(dev
, PRB2_BASE
);
4969 int i915_gem_init_rings(struct drm_device
*dev
)
4971 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4974 ret
= intel_init_render_ring_buffer(dev
);
4979 ret
= intel_init_bsd_ring_buffer(dev
);
4981 goto cleanup_render_ring
;
4984 if (intel_enable_blt(dev
)) {
4985 ret
= intel_init_blt_ring_buffer(dev
);
4987 goto cleanup_bsd_ring
;
4990 if (HAS_VEBOX(dev
)) {
4991 ret
= intel_init_vebox_ring_buffer(dev
);
4993 goto cleanup_blt_ring
;
4996 if (HAS_BSD2(dev
)) {
4997 ret
= intel_init_bsd2_ring_buffer(dev
);
4999 goto cleanup_vebox_ring
;
5002 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
5004 goto cleanup_bsd2_ring
;
5009 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS2
]);
5011 intel_cleanup_ring_buffer(&dev_priv
->ring
[VECS
]);
5013 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
5015 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
5016 cleanup_render_ring
:
5017 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
5023 i915_gem_init_hw(struct drm_device
*dev
)
5025 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5026 struct intel_engine_cs
*ring
;
5029 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
5032 /* Double layer security blanket, see i915_gem_init() */
5033 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5035 if (dev_priv
->ellc_size
)
5036 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
5038 if (IS_HASWELL(dev
))
5039 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
5040 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
5042 if (HAS_PCH_NOP(dev
)) {
5043 if (IS_IVYBRIDGE(dev
)) {
5044 u32 temp
= I915_READ(GEN7_MSG_CTL
);
5045 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
5046 I915_WRITE(GEN7_MSG_CTL
, temp
);
5047 } else if (INTEL_INFO(dev
)->gen
>= 7) {
5048 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
5049 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
5050 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
5054 i915_gem_init_swizzling(dev
);
5057 * At least 830 can leave some of the unused rings
5058 * "active" (ie. head != tail) after resume which
5059 * will prevent c3 entry. Makes sure all unused rings
5062 init_unused_rings(dev
);
5064 BUG_ON(!dev_priv
->ring
[RCS
].default_context
);
5066 ret
= i915_ppgtt_init_hw(dev
);
5068 DRM_ERROR("PPGTT enable HW failed %d\n", ret
);
5072 /* Need to do basic initialisation of all rings first: */
5073 for_each_ring(ring
, dev_priv
, i
) {
5074 ret
= ring
->init_hw(ring
);
5079 /* Now it is safe to go back round and do everything else: */
5080 for_each_ring(ring
, dev_priv
, i
) {
5081 struct drm_i915_gem_request
*req
;
5083 WARN_ON(!ring
->default_context
);
5085 ret
= i915_gem_request_alloc(ring
, ring
->default_context
, &req
);
5087 i915_gem_cleanup_ringbuffer(dev
);
5091 if (ring
->id
== RCS
) {
5092 for (j
= 0; j
< NUM_L3_SLICES(dev
); j
++)
5093 i915_gem_l3_remap(req
, j
);
5096 ret
= i915_ppgtt_init_ring(req
);
5097 if (ret
&& ret
!= -EIO
) {
5098 DRM_ERROR("PPGTT enable ring #%d failed %d\n", i
, ret
);
5099 i915_gem_request_cancel(req
);
5100 i915_gem_cleanup_ringbuffer(dev
);
5104 ret
= i915_gem_context_enable(req
);
5105 if (ret
&& ret
!= -EIO
) {
5106 DRM_ERROR("Context enable ring #%d failed %d\n", i
, ret
);
5107 i915_gem_request_cancel(req
);
5108 i915_gem_cleanup_ringbuffer(dev
);
5112 i915_add_request_no_flush(req
);
5116 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5120 int i915_gem_init(struct drm_device
*dev
)
5122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5125 i915
.enable_execlists
= intel_sanitize_enable_execlists(dev
,
5126 i915
.enable_execlists
);
5128 mutex_lock(&dev
->struct_mutex
);
5130 if (IS_VALLEYVIEW(dev
)) {
5131 /* VLVA0 (potential hack), BIOS isn't actually waking us */
5132 I915_WRITE(VLV_GTLC_WAKE_CTRL
, VLV_GTLC_ALLOWWAKEREQ
);
5133 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS
) &
5134 VLV_GTLC_ALLOWWAKEACK
), 10))
5135 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
5138 if (!i915
.enable_execlists
) {
5139 dev_priv
->gt
.execbuf_submit
= i915_gem_ringbuffer_submission
;
5140 dev_priv
->gt
.init_rings
= i915_gem_init_rings
;
5141 dev_priv
->gt
.cleanup_ring
= intel_cleanup_ring_buffer
;
5142 dev_priv
->gt
.stop_ring
= intel_stop_ring_buffer
;
5144 dev_priv
->gt
.execbuf_submit
= intel_execlists_submission
;
5145 dev_priv
->gt
.init_rings
= intel_logical_rings_init
;
5146 dev_priv
->gt
.cleanup_ring
= intel_logical_ring_cleanup
;
5147 dev_priv
->gt
.stop_ring
= intel_logical_ring_stop
;
5150 /* This is just a security blanket to placate dragons.
5151 * On some systems, we very sporadically observe that the first TLBs
5152 * used by the CS may be stale, despite us poking the TLB reset. If
5153 * we hold the forcewake during initialisation these problems
5154 * just magically go away.
5156 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5158 ret
= i915_gem_init_userptr(dev
);
5162 i915_gem_init_global_gtt(dev
);
5164 ret
= i915_gem_context_init(dev
);
5168 ret
= dev_priv
->gt
.init_rings(dev
);
5172 ret
= i915_gem_init_hw(dev
);
5174 /* Allow ring initialisation to fail by marking the GPU as
5175 * wedged. But we only want to do this where the GPU is angry,
5176 * for all other failure, such as an allocation failure, bail.
5178 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
5179 atomic_set_mask(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
5184 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5185 mutex_unlock(&dev
->struct_mutex
);
5191 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
5193 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5194 struct intel_engine_cs
*ring
;
5197 for_each_ring(ring
, dev_priv
, i
)
5198 dev_priv
->gt
.cleanup_ring(ring
);
5200 if (i915
.enable_execlists
)
5202 * Neither the BIOS, ourselves or any other kernel
5203 * expects the system to be in execlists mode on startup,
5204 * so we need to reset the GPU back to legacy mode.
5206 intel_gpu_reset(dev
);
5210 init_ring_lists(struct intel_engine_cs
*ring
)
5212 INIT_LIST_HEAD(&ring
->active_list
);
5213 INIT_LIST_HEAD(&ring
->request_list
);
5216 void i915_init_vm(struct drm_i915_private
*dev_priv
,
5217 struct i915_address_space
*vm
)
5219 if (!i915_is_ggtt(vm
))
5220 drm_mm_init(&vm
->mm
, vm
->start
, vm
->total
);
5221 vm
->dev
= dev_priv
->dev
;
5222 INIT_LIST_HEAD(&vm
->active_list
);
5223 INIT_LIST_HEAD(&vm
->inactive_list
);
5224 INIT_LIST_HEAD(&vm
->global_link
);
5225 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
5229 i915_gem_load(struct drm_device
*dev
)
5231 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5235 kmem_cache_create("i915_gem_object",
5236 sizeof(struct drm_i915_gem_object
), 0,
5240 kmem_cache_create("i915_gem_vma",
5241 sizeof(struct i915_vma
), 0,
5244 dev_priv
->requests
=
5245 kmem_cache_create("i915_gem_request",
5246 sizeof(struct drm_i915_gem_request
), 0,
5250 INIT_LIST_HEAD(&dev_priv
->vm_list
);
5251 i915_init_vm(dev_priv
, &dev_priv
->gtt
.base
);
5253 INIT_LIST_HEAD(&dev_priv
->context_list
);
5254 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
5255 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
5256 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5257 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
5258 init_ring_lists(&dev_priv
->ring
[i
]);
5259 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
5260 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
5261 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
5262 i915_gem_retire_work_handler
);
5263 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
5264 i915_gem_idle_work_handler
);
5265 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
5267 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
5269 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
))
5270 dev_priv
->num_fence_regs
= 32;
5271 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
5272 dev_priv
->num_fence_regs
= 16;
5274 dev_priv
->num_fence_regs
= 8;
5276 if (intel_vgpu_active(dev
))
5277 dev_priv
->num_fence_regs
=
5278 I915_READ(vgtif_reg(avail_rs
.fence_num
));
5280 /* Initialize fence registers to zero */
5281 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5282 i915_gem_restore_fences(dev
);
5284 i915_gem_detect_bit_6_swizzle(dev
);
5285 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
5287 dev_priv
->mm
.interruptible
= true;
5289 i915_gem_shrinker_init(dev_priv
);
5291 mutex_init(&dev_priv
->fb_tracking
.lock
);
5294 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5296 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5298 /* Clean up our request list when the client is going away, so that
5299 * later retire_requests won't dereference our soon-to-be-gone
5302 spin_lock(&file_priv
->mm
.lock
);
5303 while (!list_empty(&file_priv
->mm
.request_list
)) {
5304 struct drm_i915_gem_request
*request
;
5306 request
= list_first_entry(&file_priv
->mm
.request_list
,
5307 struct drm_i915_gem_request
,
5309 list_del(&request
->client_list
);
5310 request
->file_priv
= NULL
;
5312 spin_unlock(&file_priv
->mm
.lock
);
5314 if (!list_empty(&file_priv
->rps
.link
)) {
5315 spin_lock(&to_i915(dev
)->rps
.client_lock
);
5316 list_del(&file_priv
->rps
.link
);
5317 spin_unlock(&to_i915(dev
)->rps
.client_lock
);
5321 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
5323 struct drm_i915_file_private
*file_priv
;
5326 DRM_DEBUG_DRIVER("\n");
5328 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
5332 file
->driver_priv
= file_priv
;
5333 file_priv
->dev_priv
= dev
->dev_private
;
5334 file_priv
->file
= file
;
5335 INIT_LIST_HEAD(&file_priv
->rps
.link
);
5337 spin_lock_init(&file_priv
->mm
.lock
);
5338 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
5340 ret
= i915_gem_context_open(dev
, file
);
5348 * i915_gem_track_fb - update frontbuffer tracking
5349 * old: current GEM buffer for the frontbuffer slots
5350 * new: new GEM buffer for the frontbuffer slots
5351 * frontbuffer_bits: bitmask of frontbuffer slots
5353 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5354 * from @old and setting them in @new. Both @old and @new can be NULL.
5356 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
5357 struct drm_i915_gem_object
*new,
5358 unsigned frontbuffer_bits
)
5361 WARN_ON(!mutex_is_locked(&old
->base
.dev
->struct_mutex
));
5362 WARN_ON(!(old
->frontbuffer_bits
& frontbuffer_bits
));
5363 old
->frontbuffer_bits
&= ~frontbuffer_bits
;
5367 WARN_ON(!mutex_is_locked(&new->base
.dev
->struct_mutex
));
5368 WARN_ON(new->frontbuffer_bits
& frontbuffer_bits
);
5369 new->frontbuffer_bits
|= frontbuffer_bits
;
5373 /* All the new VM stuff */
5375 i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
5376 struct i915_address_space
*vm
)
5378 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5379 struct i915_vma
*vma
;
5381 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5383 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5384 if (i915_is_ggtt(vma
->vm
) &&
5385 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5388 return vma
->node
.start
;
5391 WARN(1, "%s vma for this object not found.\n",
5392 i915_is_ggtt(vm
) ? "global" : "ppgtt");
5397 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
5398 const struct i915_ggtt_view
*view
)
5400 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5401 struct i915_vma
*vma
;
5403 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5404 if (vma
->vm
== ggtt
&&
5405 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
5406 return vma
->node
.start
;
5408 WARN(1, "global vma for this object not found. (view=%u)\n", view
->type
);
5412 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
5413 struct i915_address_space
*vm
)
5415 struct i915_vma
*vma
;
5417 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5418 if (i915_is_ggtt(vma
->vm
) &&
5419 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5421 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
5428 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
5429 const struct i915_ggtt_view
*view
)
5431 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5432 struct i915_vma
*vma
;
5434 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5435 if (vma
->vm
== ggtt
&&
5436 i915_ggtt_view_equal(&vma
->ggtt_view
, view
) &&
5437 drm_mm_node_allocated(&vma
->node
))
5443 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
5445 struct i915_vma
*vma
;
5447 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5448 if (drm_mm_node_allocated(&vma
->node
))
5454 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
5455 struct i915_address_space
*vm
)
5457 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5458 struct i915_vma
*vma
;
5460 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5462 BUG_ON(list_empty(&o
->vma_list
));
5464 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5465 if (i915_is_ggtt(vma
->vm
) &&
5466 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5469 return vma
->node
.size
;
5474 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
)
5476 struct i915_vma
*vma
;
5477 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
5478 if (vma
->pin_count
> 0)