2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 #define RQ_BUG_ON(expr)
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
46 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
);
48 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
);
49 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
50 struct drm_i915_gem_object
*obj
);
51 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
52 struct drm_i915_fence_reg
*fence
,
55 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
56 enum i915_cache_level level
)
58 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
61 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
63 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
66 return obj
->pin_display
;
69 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
72 i915_gem_release_mmap(obj
);
74 /* As we do not have an associated fence register, we will force
75 * a tiling change if we ever need to acquire one.
77 obj
->fence_dirty
= false;
78 obj
->fence_reg
= I915_FENCE_REG_NONE
;
81 /* some bookkeeping */
82 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
85 spin_lock(&dev_priv
->mm
.object_stat_lock
);
86 dev_priv
->mm
.object_count
++;
87 dev_priv
->mm
.object_memory
+= size
;
88 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
91 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
94 spin_lock(&dev_priv
->mm
.object_stat_lock
);
95 dev_priv
->mm
.object_count
--;
96 dev_priv
->mm
.object_memory
-= size
;
97 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
101 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
105 #define EXIT_COND (!i915_reset_in_progress(error) || \
106 i915_terminally_wedged(error))
111 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
112 * userspace. If it takes that long something really bad is going on and
113 * we should simply try to bail out and fail as gracefully as possible.
115 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
119 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
121 } else if (ret
< 0) {
129 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
134 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
138 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
142 WARN_ON(i915_verify_lists(dev
));
147 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
148 struct drm_file
*file
)
150 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
151 struct drm_i915_gem_get_aperture
*args
= data
;
152 struct drm_i915_gem_object
*obj
;
156 mutex_lock(&dev
->struct_mutex
);
157 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
158 if (i915_gem_obj_is_pinned(obj
))
159 pinned
+= i915_gem_obj_ggtt_size(obj
);
160 mutex_unlock(&dev
->struct_mutex
);
162 args
->aper_size
= dev_priv
->gtt
.base
.total
;
163 args
->aper_available_size
= args
->aper_size
- pinned
;
169 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
171 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
172 char *vaddr
= obj
->phys_handle
->vaddr
;
174 struct scatterlist
*sg
;
177 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
180 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
184 page
= shmem_read_mapping_page(mapping
, i
);
186 return PTR_ERR(page
);
188 src
= kmap_atomic(page
);
189 memcpy(vaddr
, src
, PAGE_SIZE
);
190 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
193 page_cache_release(page
);
197 i915_gem_chipset_flush(obj
->base
.dev
);
199 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
203 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
210 sg
->length
= obj
->base
.size
;
212 sg_dma_address(sg
) = obj
->phys_handle
->busaddr
;
213 sg_dma_len(sg
) = obj
->base
.size
;
216 obj
->has_dma_mapping
= true;
221 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
)
225 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
227 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
229 /* In the event of a disaster, abandon all caches and
232 WARN_ON(ret
!= -EIO
);
233 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
236 if (obj
->madv
== I915_MADV_DONTNEED
)
240 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
241 char *vaddr
= obj
->phys_handle
->vaddr
;
244 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
248 page
= shmem_read_mapping_page(mapping
, i
);
252 dst
= kmap_atomic(page
);
253 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
254 memcpy(dst
, vaddr
, PAGE_SIZE
);
257 set_page_dirty(page
);
258 if (obj
->madv
== I915_MADV_WILLNEED
)
259 mark_page_accessed(page
);
260 page_cache_release(page
);
266 sg_free_table(obj
->pages
);
269 obj
->has_dma_mapping
= false;
273 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
275 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
278 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
279 .get_pages
= i915_gem_object_get_pages_phys
,
280 .put_pages
= i915_gem_object_put_pages_phys
,
281 .release
= i915_gem_object_release_phys
,
285 drop_pages(struct drm_i915_gem_object
*obj
)
287 struct i915_vma
*vma
, *next
;
290 drm_gem_object_reference(&obj
->base
);
291 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
)
292 if (i915_vma_unbind(vma
))
295 ret
= i915_gem_object_put_pages(obj
);
296 drm_gem_object_unreference(&obj
->base
);
302 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
305 drm_dma_handle_t
*phys
;
308 if (obj
->phys_handle
) {
309 if ((unsigned long)obj
->phys_handle
->vaddr
& (align
-1))
315 if (obj
->madv
!= I915_MADV_WILLNEED
)
318 if (obj
->base
.filp
== NULL
)
321 ret
= drop_pages(obj
);
325 /* create a new object */
326 phys
= drm_pci_alloc(obj
->base
.dev
, obj
->base
.size
, align
);
330 obj
->phys_handle
= phys
;
331 obj
->ops
= &i915_gem_phys_ops
;
333 return i915_gem_object_get_pages(obj
);
337 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
338 struct drm_i915_gem_pwrite
*args
,
339 struct drm_file
*file_priv
)
341 struct drm_device
*dev
= obj
->base
.dev
;
342 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
343 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
346 /* We manually control the domain here and pretend that it
347 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
349 ret
= i915_gem_object_wait_rendering(obj
, false);
353 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_CPU
);
354 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
355 unsigned long unwritten
;
357 /* The physical object once assigned is fixed for the lifetime
358 * of the obj, so we can safely drop the lock and continue
361 mutex_unlock(&dev
->struct_mutex
);
362 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
363 mutex_lock(&dev
->struct_mutex
);
370 drm_clflush_virt_range(vaddr
, args
->size
);
371 i915_gem_chipset_flush(dev
);
374 intel_fb_obj_flush(obj
, false);
378 void *i915_gem_object_alloc(struct drm_device
*dev
)
380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
381 return kmem_cache_zalloc(dev_priv
->objects
, GFP_KERNEL
);
384 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
386 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
387 kmem_cache_free(dev_priv
->objects
, obj
);
391 i915_gem_create(struct drm_file
*file
,
392 struct drm_device
*dev
,
396 struct drm_i915_gem_object
*obj
;
400 size
= roundup(size
, PAGE_SIZE
);
404 /* Allocate the new object */
405 obj
= i915_gem_alloc_object(dev
, size
);
409 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
410 /* drop reference from allocate - handle holds it now */
411 drm_gem_object_unreference_unlocked(&obj
->base
);
420 i915_gem_dumb_create(struct drm_file
*file
,
421 struct drm_device
*dev
,
422 struct drm_mode_create_dumb
*args
)
424 /* have to work out size/pitch and return them */
425 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
426 args
->size
= args
->pitch
* args
->height
;
427 return i915_gem_create(file
, dev
,
428 args
->size
, &args
->handle
);
432 * Creates a new mm object and returns a handle to it.
435 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
436 struct drm_file
*file
)
438 struct drm_i915_gem_create
*args
= data
;
440 return i915_gem_create(file
, dev
,
441 args
->size
, &args
->handle
);
445 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
446 const char *gpu_vaddr
, int gpu_offset
,
449 int ret
, cpu_offset
= 0;
452 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
453 int this_length
= min(cacheline_end
- gpu_offset
, length
);
454 int swizzled_gpu_offset
= gpu_offset
^ 64;
456 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
457 gpu_vaddr
+ swizzled_gpu_offset
,
462 cpu_offset
+= this_length
;
463 gpu_offset
+= this_length
;
464 length
-= this_length
;
471 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
472 const char __user
*cpu_vaddr
,
475 int ret
, cpu_offset
= 0;
478 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
479 int this_length
= min(cacheline_end
- gpu_offset
, length
);
480 int swizzled_gpu_offset
= gpu_offset
^ 64;
482 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
483 cpu_vaddr
+ cpu_offset
,
488 cpu_offset
+= this_length
;
489 gpu_offset
+= this_length
;
490 length
-= this_length
;
497 * Pins the specified object's pages and synchronizes the object with
498 * GPU accesses. Sets needs_clflush to non-zero if the caller should
499 * flush the object from the CPU cache.
501 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
511 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
512 /* If we're not in the cpu read domain, set ourself into the gtt
513 * read domain and manually flush cachelines (if required). This
514 * optimizes for the case when the gpu will dirty the data
515 * anyway again before the next pread happens. */
516 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
518 ret
= i915_gem_object_wait_rendering(obj
, true);
523 ret
= i915_gem_object_get_pages(obj
);
527 i915_gem_object_pin_pages(obj
);
532 /* Per-page copy function for the shmem pread fastpath.
533 * Flushes invalid cachelines before reading the target if
534 * needs_clflush is set. */
536 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
537 char __user
*user_data
,
538 bool page_do_bit17_swizzling
, bool needs_clflush
)
543 if (unlikely(page_do_bit17_swizzling
))
546 vaddr
= kmap_atomic(page
);
548 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
550 ret
= __copy_to_user_inatomic(user_data
,
551 vaddr
+ shmem_page_offset
,
553 kunmap_atomic(vaddr
);
555 return ret
? -EFAULT
: 0;
559 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
562 if (unlikely(swizzled
)) {
563 unsigned long start
= (unsigned long) addr
;
564 unsigned long end
= (unsigned long) addr
+ length
;
566 /* For swizzling simply ensure that we always flush both
567 * channels. Lame, but simple and it works. Swizzled
568 * pwrite/pread is far from a hotpath - current userspace
569 * doesn't use it at all. */
570 start
= round_down(start
, 128);
571 end
= round_up(end
, 128);
573 drm_clflush_virt_range((void *)start
, end
- start
);
575 drm_clflush_virt_range(addr
, length
);
580 /* Only difference to the fast-path function is that this can handle bit17
581 * and uses non-atomic copy and kmap functions. */
583 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
584 char __user
*user_data
,
585 bool page_do_bit17_swizzling
, bool needs_clflush
)
592 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
594 page_do_bit17_swizzling
);
596 if (page_do_bit17_swizzling
)
597 ret
= __copy_to_user_swizzled(user_data
,
598 vaddr
, shmem_page_offset
,
601 ret
= __copy_to_user(user_data
,
602 vaddr
+ shmem_page_offset
,
606 return ret
? - EFAULT
: 0;
610 i915_gem_shmem_pread(struct drm_device
*dev
,
611 struct drm_i915_gem_object
*obj
,
612 struct drm_i915_gem_pread
*args
,
613 struct drm_file
*file
)
615 char __user
*user_data
;
618 int shmem_page_offset
, page_length
, ret
= 0;
619 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
621 int needs_clflush
= 0;
622 struct sg_page_iter sg_iter
;
624 user_data
= to_user_ptr(args
->data_ptr
);
627 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
629 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
633 offset
= args
->offset
;
635 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
636 offset
>> PAGE_SHIFT
) {
637 struct page
*page
= sg_page_iter_page(&sg_iter
);
642 /* Operation in this page
644 * shmem_page_offset = offset within page in shmem file
645 * page_length = bytes to copy for this page
647 shmem_page_offset
= offset_in_page(offset
);
648 page_length
= remain
;
649 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
650 page_length
= PAGE_SIZE
- shmem_page_offset
;
652 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
653 (page_to_phys(page
) & (1 << 17)) != 0;
655 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
656 user_data
, page_do_bit17_swizzling
,
661 mutex_unlock(&dev
->struct_mutex
);
663 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
664 ret
= fault_in_multipages_writeable(user_data
, remain
);
665 /* Userspace is tricking us, but we've already clobbered
666 * its pages with the prefault and promised to write the
667 * data up to the first fault. Hence ignore any errors
668 * and just continue. */
673 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
674 user_data
, page_do_bit17_swizzling
,
677 mutex_lock(&dev
->struct_mutex
);
683 remain
-= page_length
;
684 user_data
+= page_length
;
685 offset
+= page_length
;
689 i915_gem_object_unpin_pages(obj
);
695 * Reads data from the object referenced by handle.
697 * On error, the contents of *data are undefined.
700 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
701 struct drm_file
*file
)
703 struct drm_i915_gem_pread
*args
= data
;
704 struct drm_i915_gem_object
*obj
;
710 if (!access_ok(VERIFY_WRITE
,
711 to_user_ptr(args
->data_ptr
),
715 ret
= i915_mutex_lock_interruptible(dev
);
719 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
720 if (&obj
->base
== NULL
) {
725 /* Bounds check source. */
726 if (args
->offset
> obj
->base
.size
||
727 args
->size
> obj
->base
.size
- args
->offset
) {
732 /* prime objects have no backing filp to GEM pread/pwrite
735 if (!obj
->base
.filp
) {
740 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
742 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
745 drm_gem_object_unreference(&obj
->base
);
747 mutex_unlock(&dev
->struct_mutex
);
751 /* This is the fast write path which cannot handle
752 * page faults in the source data
756 fast_user_write(struct io_mapping
*mapping
,
757 loff_t page_base
, int page_offset
,
758 char __user
*user_data
,
761 void __iomem
*vaddr_atomic
;
763 unsigned long unwritten
;
765 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
766 /* We can use the cpu mem copy function because this is X86. */
767 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
768 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
770 io_mapping_unmap_atomic(vaddr_atomic
);
775 * This is the fast pwrite path, where we copy the data directly from the
776 * user into the GTT, uncached.
779 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
780 struct drm_i915_gem_object
*obj
,
781 struct drm_i915_gem_pwrite
*args
,
782 struct drm_file
*file
)
784 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
786 loff_t offset
, page_base
;
787 char __user
*user_data
;
788 int page_offset
, page_length
, ret
;
790 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
794 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
798 ret
= i915_gem_object_put_fence(obj
);
802 user_data
= to_user_ptr(args
->data_ptr
);
805 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
807 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_GTT
);
810 /* Operation in this page
812 * page_base = page offset within aperture
813 * page_offset = offset within page
814 * page_length = bytes to copy for this page
816 page_base
= offset
& PAGE_MASK
;
817 page_offset
= offset_in_page(offset
);
818 page_length
= remain
;
819 if ((page_offset
+ remain
) > PAGE_SIZE
)
820 page_length
= PAGE_SIZE
- page_offset
;
822 /* If we get a fault while copying data, then (presumably) our
823 * source page isn't available. Return the error and we'll
824 * retry in the slow path.
826 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
827 page_offset
, user_data
, page_length
)) {
832 remain
-= page_length
;
833 user_data
+= page_length
;
834 offset
+= page_length
;
838 intel_fb_obj_flush(obj
, false);
840 i915_gem_object_ggtt_unpin(obj
);
845 /* Per-page copy function for the shmem pwrite fastpath.
846 * Flushes invalid cachelines before writing to the target if
847 * needs_clflush_before is set and flushes out any written cachelines after
848 * writing if needs_clflush is set. */
850 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
851 char __user
*user_data
,
852 bool page_do_bit17_swizzling
,
853 bool needs_clflush_before
,
854 bool needs_clflush_after
)
859 if (unlikely(page_do_bit17_swizzling
))
862 vaddr
= kmap_atomic(page
);
863 if (needs_clflush_before
)
864 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
866 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
867 user_data
, page_length
);
868 if (needs_clflush_after
)
869 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
871 kunmap_atomic(vaddr
);
873 return ret
? -EFAULT
: 0;
876 /* Only difference to the fast-path function is that this can handle bit17
877 * and uses non-atomic copy and kmap functions. */
879 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
880 char __user
*user_data
,
881 bool page_do_bit17_swizzling
,
882 bool needs_clflush_before
,
883 bool needs_clflush_after
)
889 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
890 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
892 page_do_bit17_swizzling
);
893 if (page_do_bit17_swizzling
)
894 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
898 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
901 if (needs_clflush_after
)
902 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
904 page_do_bit17_swizzling
);
907 return ret
? -EFAULT
: 0;
911 i915_gem_shmem_pwrite(struct drm_device
*dev
,
912 struct drm_i915_gem_object
*obj
,
913 struct drm_i915_gem_pwrite
*args
,
914 struct drm_file
*file
)
918 char __user
*user_data
;
919 int shmem_page_offset
, page_length
, ret
= 0;
920 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
921 int hit_slowpath
= 0;
922 int needs_clflush_after
= 0;
923 int needs_clflush_before
= 0;
924 struct sg_page_iter sg_iter
;
926 user_data
= to_user_ptr(args
->data_ptr
);
929 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
931 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
932 /* If we're not in the cpu write domain, set ourself into the gtt
933 * write domain and manually flush cachelines (if required). This
934 * optimizes for the case when the gpu will use the data
935 * right away and we therefore have to clflush anyway. */
936 needs_clflush_after
= cpu_write_needs_clflush(obj
);
937 ret
= i915_gem_object_wait_rendering(obj
, false);
941 /* Same trick applies to invalidate partially written cachelines read
943 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
944 needs_clflush_before
=
945 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
947 ret
= i915_gem_object_get_pages(obj
);
951 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_CPU
);
953 i915_gem_object_pin_pages(obj
);
955 offset
= args
->offset
;
958 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
959 offset
>> PAGE_SHIFT
) {
960 struct page
*page
= sg_page_iter_page(&sg_iter
);
961 int partial_cacheline_write
;
966 /* Operation in this page
968 * shmem_page_offset = offset within page in shmem file
969 * page_length = bytes to copy for this page
971 shmem_page_offset
= offset_in_page(offset
);
973 page_length
= remain
;
974 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
975 page_length
= PAGE_SIZE
- shmem_page_offset
;
977 /* If we don't overwrite a cacheline completely we need to be
978 * careful to have up-to-date data by first clflushing. Don't
979 * overcomplicate things and flush the entire patch. */
980 partial_cacheline_write
= needs_clflush_before
&&
981 ((shmem_page_offset
| page_length
)
982 & (boot_cpu_data
.x86_clflush_size
- 1));
984 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
985 (page_to_phys(page
) & (1 << 17)) != 0;
987 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
988 user_data
, page_do_bit17_swizzling
,
989 partial_cacheline_write
,
990 needs_clflush_after
);
995 mutex_unlock(&dev
->struct_mutex
);
996 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
997 user_data
, page_do_bit17_swizzling
,
998 partial_cacheline_write
,
999 needs_clflush_after
);
1001 mutex_lock(&dev
->struct_mutex
);
1007 remain
-= page_length
;
1008 user_data
+= page_length
;
1009 offset
+= page_length
;
1013 i915_gem_object_unpin_pages(obj
);
1017 * Fixup: Flush cpu caches in case we didn't flush the dirty
1018 * cachelines in-line while writing and the object moved
1019 * out of the cpu write domain while we've dropped the lock.
1021 if (!needs_clflush_after
&&
1022 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1023 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
1024 i915_gem_chipset_flush(dev
);
1028 if (needs_clflush_after
)
1029 i915_gem_chipset_flush(dev
);
1031 intel_fb_obj_flush(obj
, false);
1036 * Writes data to the object referenced by handle.
1038 * On error, the contents of the buffer that were to be modified are undefined.
1041 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1042 struct drm_file
*file
)
1044 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1045 struct drm_i915_gem_pwrite
*args
= data
;
1046 struct drm_i915_gem_object
*obj
;
1049 if (args
->size
== 0)
1052 if (!access_ok(VERIFY_READ
,
1053 to_user_ptr(args
->data_ptr
),
1057 if (likely(!i915
.prefault_disable
)) {
1058 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
1064 intel_runtime_pm_get(dev_priv
);
1066 ret
= i915_mutex_lock_interruptible(dev
);
1070 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1071 if (&obj
->base
== NULL
) {
1076 /* Bounds check destination. */
1077 if (args
->offset
> obj
->base
.size
||
1078 args
->size
> obj
->base
.size
- args
->offset
) {
1083 /* prime objects have no backing filp to GEM pread/pwrite
1086 if (!obj
->base
.filp
) {
1091 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1094 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1095 * it would end up going through the fenced access, and we'll get
1096 * different detiling behavior between reading and writing.
1097 * pread/pwrite currently are reading and writing from the CPU
1098 * perspective, requiring manual detiling by the client.
1100 if (obj
->tiling_mode
== I915_TILING_NONE
&&
1101 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
1102 cpu_write_needs_clflush(obj
)) {
1103 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1104 /* Note that the gtt paths might fail with non-page-backed user
1105 * pointers (e.g. gtt mappings when moving data between
1106 * textures). Fallback to the shmem path in that case. */
1109 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1110 if (obj
->phys_handle
)
1111 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1113 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
1117 drm_gem_object_unreference(&obj
->base
);
1119 mutex_unlock(&dev
->struct_mutex
);
1121 intel_runtime_pm_put(dev_priv
);
1127 i915_gem_check_wedge(struct i915_gpu_error
*error
,
1130 if (i915_reset_in_progress(error
)) {
1131 /* Non-interruptible callers can't handle -EAGAIN, hence return
1132 * -EIO unconditionally for these. */
1136 /* Recovery complete, but the reset failed ... */
1137 if (i915_terminally_wedged(error
))
1141 * Check if GPU Reset is in progress - we need intel_ring_begin
1142 * to work properly to reinit the hw state while the gpu is
1143 * still marked as reset-in-progress. Handle this with a flag.
1145 if (!error
->reload_in_reset
)
1153 * Compare arbitrary request against outstanding lazy request. Emit on match.
1156 i915_gem_check_olr(struct drm_i915_gem_request
*req
)
1160 WARN_ON(!mutex_is_locked(&req
->ring
->dev
->struct_mutex
));
1163 if (req
== req
->ring
->outstanding_lazy_request
)
1164 ret
= i915_add_request(req
->ring
);
1169 static void fake_irq(unsigned long data
)
1171 wake_up_process((struct task_struct
*)data
);
1174 static bool missed_irq(struct drm_i915_private
*dev_priv
,
1175 struct intel_engine_cs
*ring
)
1177 return test_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
1180 static int __i915_spin_request(struct drm_i915_gem_request
*req
)
1182 unsigned long timeout
;
1184 if (i915_gem_request_get_ring(req
)->irq_refcount
)
1187 timeout
= jiffies
+ 1;
1188 while (!need_resched()) {
1189 if (i915_gem_request_completed(req
, true))
1192 if (time_after_eq(jiffies
, timeout
))
1195 cpu_relax_lowlatency();
1197 if (i915_gem_request_completed(req
, false))
1204 * __i915_wait_request - wait until execution of request has finished
1206 * @reset_counter: reset sequence associated with the given request
1207 * @interruptible: do an interruptible wait (normally yes)
1208 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1210 * Note: It is of utmost importance that the passed in seqno and reset_counter
1211 * values have been read by the caller in an smp safe manner. Where read-side
1212 * locks are involved, it is sufficient to read the reset_counter before
1213 * unlocking the lock that protects the seqno. For lockless tricks, the
1214 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1217 * Returns 0 if the request was found within the alloted time. Else returns the
1218 * errno with remaining time filled in timeout argument.
1220 int __i915_wait_request(struct drm_i915_gem_request
*req
,
1221 unsigned reset_counter
,
1224 struct drm_i915_file_private
*file_priv
)
1226 struct intel_engine_cs
*ring
= i915_gem_request_get_ring(req
);
1227 struct drm_device
*dev
= ring
->dev
;
1228 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1229 const bool irq_test_in_progress
=
1230 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_ring_flag(ring
);
1232 unsigned long timeout_expire
;
1236 WARN(!intel_irqs_enabled(dev_priv
), "IRQs disabled");
1238 if (list_empty(&req
->list
))
1241 if (i915_gem_request_completed(req
, true))
1244 timeout_expire
= timeout
?
1245 jiffies
+ nsecs_to_jiffies_timeout((u64
)*timeout
) : 0;
1247 if (INTEL_INFO(dev
)->gen
>= 6)
1248 gen6_rps_boost(dev_priv
, file_priv
);
1250 /* Record current time in case interrupted by signal, or wedged */
1251 trace_i915_gem_request_wait_begin(req
);
1252 before
= ktime_get_raw_ns();
1254 /* Optimistic spin for the next jiffie before touching IRQs */
1255 ret
= __i915_spin_request(req
);
1259 if (!irq_test_in_progress
&& WARN_ON(!ring
->irq_get(ring
))) {
1265 struct timer_list timer
;
1267 prepare_to_wait(&ring
->irq_queue
, &wait
,
1268 interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
);
1270 /* We need to check whether any gpu reset happened in between
1271 * the caller grabbing the seqno and now ... */
1272 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
)) {
1273 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1274 * is truely gone. */
1275 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1281 if (i915_gem_request_completed(req
, false)) {
1286 if (interruptible
&& signal_pending(current
)) {
1291 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1296 timer
.function
= NULL
;
1297 if (timeout
|| missed_irq(dev_priv
, ring
)) {
1298 unsigned long expire
;
1300 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1301 expire
= missed_irq(dev_priv
, ring
) ? jiffies
+ 1 : timeout_expire
;
1302 mod_timer(&timer
, expire
);
1307 if (timer
.function
) {
1308 del_singleshot_timer_sync(&timer
);
1309 destroy_timer_on_stack(&timer
);
1312 if (!irq_test_in_progress
)
1313 ring
->irq_put(ring
);
1315 finish_wait(&ring
->irq_queue
, &wait
);
1318 now
= ktime_get_raw_ns();
1319 trace_i915_gem_request_wait_end(req
);
1322 s64 tres
= *timeout
- (now
- before
);
1324 *timeout
= tres
< 0 ? 0 : tres
;
1327 * Apparently ktime isn't accurate enough and occasionally has a
1328 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1329 * things up to make the test happy. We allow up to 1 jiffy.
1331 * This is a regrssion from the timespec->ktime conversion.
1333 if (ret
== -ETIME
&& *timeout
< jiffies_to_usecs(1)*1000)
1341 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1343 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1348 spin_lock(&file_priv
->mm
.lock
);
1349 list_del(&request
->client_list
);
1350 request
->file_priv
= NULL
;
1351 spin_unlock(&file_priv
->mm
.lock
);
1354 static void i915_gem_request_retire(struct drm_i915_gem_request
*request
)
1356 trace_i915_gem_request_retire(request
);
1358 /* We know the GPU must have read the request to have
1359 * sent us the seqno + interrupt, so use the position
1360 * of tail of the request to update the last known position
1363 * Note this requires that we are always called in request
1366 request
->ringbuf
->last_retired_head
= request
->postfix
;
1368 list_del_init(&request
->list
);
1369 i915_gem_request_remove_from_client(request
);
1371 put_pid(request
->pid
);
1373 i915_gem_request_unreference(request
);
1377 __i915_gem_request_retire__upto(struct drm_i915_gem_request
*req
)
1379 struct intel_engine_cs
*engine
= req
->ring
;
1380 struct drm_i915_gem_request
*tmp
;
1382 lockdep_assert_held(&engine
->dev
->struct_mutex
);
1384 if (list_empty(&req
->list
))
1388 tmp
= list_first_entry(&engine
->request_list
,
1389 typeof(*tmp
), list
);
1391 i915_gem_request_retire(tmp
);
1392 } while (tmp
!= req
);
1394 WARN_ON(i915_verify_lists(engine
->dev
));
1398 * Waits for a request to be signaled, and cleans up the
1399 * request and object lists appropriately for that event.
1402 i915_wait_request(struct drm_i915_gem_request
*req
)
1404 struct drm_device
*dev
;
1405 struct drm_i915_private
*dev_priv
;
1409 BUG_ON(req
== NULL
);
1411 dev
= req
->ring
->dev
;
1412 dev_priv
= dev
->dev_private
;
1413 interruptible
= dev_priv
->mm
.interruptible
;
1415 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1417 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1421 ret
= i915_gem_check_olr(req
);
1425 ret
= __i915_wait_request(req
,
1426 atomic_read(&dev_priv
->gpu_error
.reset_counter
),
1427 interruptible
, NULL
, NULL
);
1431 __i915_gem_request_retire__upto(req
);
1436 * Ensures that all rendering to the object has completed and the object is
1437 * safe to unbind from the GTT or access from the CPU.
1440 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1449 if (obj
->last_write_req
!= NULL
) {
1450 ret
= i915_wait_request(obj
->last_write_req
);
1454 i
= obj
->last_write_req
->ring
->id
;
1455 if (obj
->last_read_req
[i
] == obj
->last_write_req
)
1456 i915_gem_object_retire__read(obj
, i
);
1458 i915_gem_object_retire__write(obj
);
1461 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1462 if (obj
->last_read_req
[i
] == NULL
)
1465 ret
= i915_wait_request(obj
->last_read_req
[i
]);
1469 i915_gem_object_retire__read(obj
, i
);
1471 RQ_BUG_ON(obj
->active
);
1478 i915_gem_object_retire_request(struct drm_i915_gem_object
*obj
,
1479 struct drm_i915_gem_request
*req
)
1481 int ring
= req
->ring
->id
;
1483 if (obj
->last_read_req
[ring
] == req
)
1484 i915_gem_object_retire__read(obj
, ring
);
1485 else if (obj
->last_write_req
== req
)
1486 i915_gem_object_retire__write(obj
);
1488 __i915_gem_request_retire__upto(req
);
1491 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1492 * as the object state may change during this call.
1494 static __must_check
int
1495 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1496 struct drm_i915_file_private
*file_priv
,
1499 struct drm_device
*dev
= obj
->base
.dev
;
1500 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1501 struct drm_i915_gem_request
*requests
[I915_NUM_RINGS
];
1502 unsigned reset_counter
;
1505 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1506 BUG_ON(!dev_priv
->mm
.interruptible
);
1511 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1515 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1518 struct drm_i915_gem_request
*req
;
1520 req
= obj
->last_write_req
;
1524 ret
= i915_gem_check_olr(req
);
1528 requests
[n
++] = i915_gem_request_reference(req
);
1530 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1531 struct drm_i915_gem_request
*req
;
1533 req
= obj
->last_read_req
[i
];
1537 ret
= i915_gem_check_olr(req
);
1541 requests
[n
++] = i915_gem_request_reference(req
);
1545 mutex_unlock(&dev
->struct_mutex
);
1546 for (i
= 0; ret
== 0 && i
< n
; i
++)
1547 ret
= __i915_wait_request(requests
[i
], reset_counter
, true,
1549 mutex_lock(&dev
->struct_mutex
);
1552 for (i
= 0; i
< n
; i
++) {
1554 i915_gem_object_retire_request(obj
, requests
[i
]);
1555 i915_gem_request_unreference(requests
[i
]);
1562 * Called when user space prepares to use an object with the CPU, either
1563 * through the mmap ioctl's mapping or a GTT mapping.
1566 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1567 struct drm_file
*file
)
1569 struct drm_i915_gem_set_domain
*args
= data
;
1570 struct drm_i915_gem_object
*obj
;
1571 uint32_t read_domains
= args
->read_domains
;
1572 uint32_t write_domain
= args
->write_domain
;
1575 /* Only handle setting domains to types used by the CPU. */
1576 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1579 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1582 /* Having something in the write domain implies it's in the read
1583 * domain, and only that read domain. Enforce that in the request.
1585 if (write_domain
!= 0 && read_domains
!= write_domain
)
1588 ret
= i915_mutex_lock_interruptible(dev
);
1592 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1593 if (&obj
->base
== NULL
) {
1598 /* Try to flush the object off the GPU without holding the lock.
1599 * We will repeat the flush holding the lock in the normal manner
1600 * to catch cases where we are gazumped.
1602 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1608 if (read_domains
& I915_GEM_DOMAIN_GTT
)
1609 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1611 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1614 drm_gem_object_unreference(&obj
->base
);
1616 mutex_unlock(&dev
->struct_mutex
);
1621 * Called when user space has done writes to this buffer
1624 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1625 struct drm_file
*file
)
1627 struct drm_i915_gem_sw_finish
*args
= data
;
1628 struct drm_i915_gem_object
*obj
;
1631 ret
= i915_mutex_lock_interruptible(dev
);
1635 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1636 if (&obj
->base
== NULL
) {
1641 /* Pinned buffers may be scanout, so flush the cache */
1642 if (obj
->pin_display
)
1643 i915_gem_object_flush_cpu_write_domain(obj
);
1645 drm_gem_object_unreference(&obj
->base
);
1647 mutex_unlock(&dev
->struct_mutex
);
1652 * Maps the contents of an object, returning the address it is mapped
1655 * While the mapping holds a reference on the contents of the object, it doesn't
1656 * imply a ref on the object itself.
1660 * DRM driver writers who look a this function as an example for how to do GEM
1661 * mmap support, please don't implement mmap support like here. The modern way
1662 * to implement DRM mmap support is with an mmap offset ioctl (like
1663 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1664 * That way debug tooling like valgrind will understand what's going on, hiding
1665 * the mmap call in a driver private ioctl will break that. The i915 driver only
1666 * does cpu mmaps this way because we didn't know better.
1669 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1670 struct drm_file
*file
)
1672 struct drm_i915_gem_mmap
*args
= data
;
1673 struct drm_gem_object
*obj
;
1676 if (args
->flags
& ~(I915_MMAP_WC
))
1679 if (args
->flags
& I915_MMAP_WC
&& !cpu_has_pat
)
1682 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1686 /* prime objects have no backing filp to GEM mmap
1690 drm_gem_object_unreference_unlocked(obj
);
1694 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1695 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1697 if (args
->flags
& I915_MMAP_WC
) {
1698 struct mm_struct
*mm
= current
->mm
;
1699 struct vm_area_struct
*vma
;
1701 down_write(&mm
->mmap_sem
);
1702 vma
= find_vma(mm
, addr
);
1705 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1708 up_write(&mm
->mmap_sem
);
1710 drm_gem_object_unreference_unlocked(obj
);
1711 if (IS_ERR((void *)addr
))
1714 args
->addr_ptr
= (uint64_t) addr
;
1720 * i915_gem_fault - fault a page into the GTT
1721 * vma: VMA in question
1724 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1725 * from userspace. The fault handler takes care of binding the object to
1726 * the GTT (if needed), allocating and programming a fence register (again,
1727 * only if needed based on whether the old reg is still valid or the object
1728 * is tiled) and inserting a new PTE into the faulting process.
1730 * Note that the faulting process may involve evicting existing objects
1731 * from the GTT and/or fence registers to make room. So performance may
1732 * suffer if the GTT working set is large or there are few fence registers
1735 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1737 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1738 struct drm_device
*dev
= obj
->base
.dev
;
1739 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1740 struct i915_ggtt_view view
= i915_ggtt_view_normal
;
1741 pgoff_t page_offset
;
1744 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1746 intel_runtime_pm_get(dev_priv
);
1748 /* We don't use vmf->pgoff since that has the fake offset */
1749 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1752 ret
= i915_mutex_lock_interruptible(dev
);
1756 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1758 /* Try to flush the object off the GPU first without holding the lock.
1759 * Upon reacquiring the lock, we will perform our sanity checks and then
1760 * repeat the flush holding the lock in the normal manner to catch cases
1761 * where we are gazumped.
1763 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
1767 /* Access to snoopable pages through the GTT is incoherent. */
1768 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1773 /* Use a partial view if the object is bigger than the aperture. */
1774 if (obj
->base
.size
>= dev_priv
->gtt
.mappable_end
&&
1775 obj
->tiling_mode
== I915_TILING_NONE
) {
1776 static const unsigned int chunk_size
= 256; // 1 MiB
1778 memset(&view
, 0, sizeof(view
));
1779 view
.type
= I915_GGTT_VIEW_PARTIAL
;
1780 view
.params
.partial
.offset
= rounddown(page_offset
, chunk_size
);
1781 view
.params
.partial
.size
=
1784 (vma
->vm_end
- vma
->vm_start
)/PAGE_SIZE
-
1785 view
.params
.partial
.offset
);
1788 /* Now pin it into the GTT if needed */
1789 ret
= i915_gem_object_ggtt_pin(obj
, &view
, 0, PIN_MAPPABLE
);
1793 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1797 ret
= i915_gem_object_get_fence(obj
);
1801 /* Finally, remap it using the new GTT offset */
1802 pfn
= dev_priv
->gtt
.mappable_base
+
1803 i915_gem_obj_ggtt_offset_view(obj
, &view
);
1806 if (unlikely(view
.type
== I915_GGTT_VIEW_PARTIAL
)) {
1807 /* Overriding existing pages in partial view does not cause
1808 * us any trouble as TLBs are still valid because the fault
1809 * is due to userspace losing part of the mapping or never
1810 * having accessed it before (at this partials' range).
1812 unsigned long base
= vma
->vm_start
+
1813 (view
.params
.partial
.offset
<< PAGE_SHIFT
);
1816 for (i
= 0; i
< view
.params
.partial
.size
; i
++) {
1817 ret
= vm_insert_pfn(vma
, base
+ i
* PAGE_SIZE
, pfn
+ i
);
1822 obj
->fault_mappable
= true;
1824 if (!obj
->fault_mappable
) {
1825 unsigned long size
= min_t(unsigned long,
1826 vma
->vm_end
- vma
->vm_start
,
1830 for (i
= 0; i
< size
>> PAGE_SHIFT
; i
++) {
1831 ret
= vm_insert_pfn(vma
,
1832 (unsigned long)vma
->vm_start
+ i
* PAGE_SIZE
,
1838 obj
->fault_mappable
= true;
1840 ret
= vm_insert_pfn(vma
,
1841 (unsigned long)vmf
->virtual_address
,
1845 i915_gem_object_ggtt_unpin_view(obj
, &view
);
1847 mutex_unlock(&dev
->struct_mutex
);
1852 * We eat errors when the gpu is terminally wedged to avoid
1853 * userspace unduly crashing (gl has no provisions for mmaps to
1854 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1855 * and so needs to be reported.
1857 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1858 ret
= VM_FAULT_SIGBUS
;
1863 * EAGAIN means the gpu is hung and we'll wait for the error
1864 * handler to reset everything when re-faulting in
1865 * i915_mutex_lock_interruptible.
1872 * EBUSY is ok: this just means that another thread
1873 * already did the job.
1875 ret
= VM_FAULT_NOPAGE
;
1882 ret
= VM_FAULT_SIGBUS
;
1885 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1886 ret
= VM_FAULT_SIGBUS
;
1890 intel_runtime_pm_put(dev_priv
);
1895 * i915_gem_release_mmap - remove physical page mappings
1896 * @obj: obj in question
1898 * Preserve the reservation of the mmapping with the DRM core code, but
1899 * relinquish ownership of the pages back to the system.
1901 * It is vital that we remove the page mapping if we have mapped a tiled
1902 * object through the GTT and then lose the fence register due to
1903 * resource pressure. Similarly if the object has been moved out of the
1904 * aperture, than pages mapped into userspace must be revoked. Removing the
1905 * mapping will then trigger a page fault on the next user access, allowing
1906 * fixup by i915_gem_fault().
1909 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1911 if (!obj
->fault_mappable
)
1914 drm_vma_node_unmap(&obj
->base
.vma_node
,
1915 obj
->base
.dev
->anon_inode
->i_mapping
);
1916 obj
->fault_mappable
= false;
1920 i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
1922 struct drm_i915_gem_object
*obj
;
1924 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
1925 i915_gem_release_mmap(obj
);
1929 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1933 if (INTEL_INFO(dev
)->gen
>= 4 ||
1934 tiling_mode
== I915_TILING_NONE
)
1937 /* Previous chips need a power-of-two fence region when tiling */
1938 if (INTEL_INFO(dev
)->gen
== 3)
1939 gtt_size
= 1024*1024;
1941 gtt_size
= 512*1024;
1943 while (gtt_size
< size
)
1950 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1951 * @obj: object to check
1953 * Return the required GTT alignment for an object, taking into account
1954 * potential fence register mapping.
1957 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1958 int tiling_mode
, bool fenced
)
1961 * Minimum alignment is 4k (GTT page size), but might be greater
1962 * if a fence register is needed for the object.
1964 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1965 tiling_mode
== I915_TILING_NONE
)
1969 * Previous chips need to be aligned to the size of the smallest
1970 * fence register that can contain the object.
1972 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1975 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1977 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1980 if (drm_vma_node_has_offset(&obj
->base
.vma_node
))
1983 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1985 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1989 /* Badly fragmented mmap space? The only way we can recover
1990 * space is by destroying unwanted objects. We can't randomly release
1991 * mmap_offsets as userspace expects them to be persistent for the
1992 * lifetime of the objects. The closest we can is to release the
1993 * offsets on purgeable objects by truncating it and marking it purged,
1994 * which prevents userspace from ever using that object again.
1996 i915_gem_shrink(dev_priv
,
1997 obj
->base
.size
>> PAGE_SHIFT
,
1999 I915_SHRINK_UNBOUND
|
2000 I915_SHRINK_PURGEABLE
);
2001 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2005 i915_gem_shrink_all(dev_priv
);
2006 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2008 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
2013 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
2015 drm_gem_free_mmap_offset(&obj
->base
);
2019 i915_gem_mmap_gtt(struct drm_file
*file
,
2020 struct drm_device
*dev
,
2024 struct drm_i915_gem_object
*obj
;
2027 ret
= i915_mutex_lock_interruptible(dev
);
2031 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
2032 if (&obj
->base
== NULL
) {
2037 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2038 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2043 ret
= i915_gem_object_create_mmap_offset(obj
);
2047 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
2050 drm_gem_object_unreference(&obj
->base
);
2052 mutex_unlock(&dev
->struct_mutex
);
2057 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2059 * @data: GTT mapping ioctl data
2060 * @file: GEM object info
2062 * Simply returns the fake offset to userspace so it can mmap it.
2063 * The mmap call will end up in drm_gem_mmap(), which will set things
2064 * up so we can get faults in the handler above.
2066 * The fault handler will take care of binding the object into the GTT
2067 * (since it may have been evicted to make room for something), allocating
2068 * a fence register, and mapping the appropriate aperture address into
2072 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2073 struct drm_file
*file
)
2075 struct drm_i915_gem_mmap_gtt
*args
= data
;
2077 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
2080 /* Immediately discard the backing storage */
2082 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
2084 i915_gem_object_free_mmap_offset(obj
);
2086 if (obj
->base
.filp
== NULL
)
2089 /* Our goal here is to return as much of the memory as
2090 * is possible back to the system as we are called from OOM.
2091 * To do this we must instruct the shmfs to drop all of its
2092 * backing pages, *now*.
2094 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
2095 obj
->madv
= __I915_MADV_PURGED
;
2098 /* Try to discard unwanted pages */
2100 i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
2102 struct address_space
*mapping
;
2104 switch (obj
->madv
) {
2105 case I915_MADV_DONTNEED
:
2106 i915_gem_object_truncate(obj
);
2107 case __I915_MADV_PURGED
:
2111 if (obj
->base
.filp
== NULL
)
2114 mapping
= file_inode(obj
->base
.filp
)->i_mapping
,
2115 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
2119 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
2121 struct sg_page_iter sg_iter
;
2124 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
2126 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
2128 /* In the event of a disaster, abandon all caches and
2129 * hope for the best.
2131 WARN_ON(ret
!= -EIO
);
2132 i915_gem_clflush_object(obj
, true);
2133 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2136 if (i915_gem_object_needs_bit17_swizzle(obj
))
2137 i915_gem_object_save_bit_17_swizzle(obj
);
2139 if (obj
->madv
== I915_MADV_DONTNEED
)
2142 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
2143 struct page
*page
= sg_page_iter_page(&sg_iter
);
2146 set_page_dirty(page
);
2148 if (obj
->madv
== I915_MADV_WILLNEED
)
2149 mark_page_accessed(page
);
2151 page_cache_release(page
);
2155 sg_free_table(obj
->pages
);
2160 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
2162 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2164 if (obj
->pages
== NULL
)
2167 if (obj
->pages_pin_count
)
2170 BUG_ON(i915_gem_obj_bound_any(obj
));
2172 /* ->put_pages might need to allocate memory for the bit17 swizzle
2173 * array, hence protect them from being reaped by removing them from gtt
2175 list_del(&obj
->global_list
);
2177 ops
->put_pages(obj
);
2180 i915_gem_object_invalidate(obj
);
2186 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2188 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2190 struct address_space
*mapping
;
2191 struct sg_table
*st
;
2192 struct scatterlist
*sg
;
2193 struct sg_page_iter sg_iter
;
2195 unsigned long last_pfn
= 0; /* suppress gcc warning */
2198 /* Assert that the object is not currently in any GPU domain. As it
2199 * wasn't in the GTT, there shouldn't be any way it could have been in
2202 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2203 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2205 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2209 page_count
= obj
->base
.size
/ PAGE_SIZE
;
2210 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2215 /* Get the list of pages out of our struct file. They'll be pinned
2216 * at this point until we release them.
2218 * Fail silently without starting the shrinker
2220 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
2221 gfp
= mapping_gfp_mask(mapping
);
2222 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
2223 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
2226 for (i
= 0; i
< page_count
; i
++) {
2227 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2229 i915_gem_shrink(dev_priv
,
2232 I915_SHRINK_UNBOUND
|
2233 I915_SHRINK_PURGEABLE
);
2234 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2237 /* We've tried hard to allocate the memory by reaping
2238 * our own buffer, now let the real VM do its job and
2239 * go down in flames if truly OOM.
2241 i915_gem_shrink_all(dev_priv
);
2242 page
= shmem_read_mapping_page(mapping
, i
);
2246 #ifdef CONFIG_SWIOTLB
2247 if (swiotlb_nr_tbl()) {
2249 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2254 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
2258 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2260 sg
->length
+= PAGE_SIZE
;
2262 last_pfn
= page_to_pfn(page
);
2264 /* Check that the i965g/gm workaround works. */
2265 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2267 #ifdef CONFIG_SWIOTLB
2268 if (!swiotlb_nr_tbl())
2273 if (i915_gem_object_needs_bit17_swizzle(obj
))
2274 i915_gem_object_do_bit_17_swizzle(obj
);
2276 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
2277 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2278 i915_gem_object_pin_pages(obj
);
2284 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
2285 page_cache_release(sg_page_iter_page(&sg_iter
));
2289 /* shmemfs first checks if there is enough memory to allocate the page
2290 * and reports ENOSPC should there be insufficient, along with the usual
2291 * ENOMEM for a genuine allocation failure.
2293 * We use ENOSPC in our driver to mean that we have run out of aperture
2294 * space and so want to translate the error from shmemfs back to our
2295 * usual understanding of ENOMEM.
2297 if (PTR_ERR(page
) == -ENOSPC
)
2300 return PTR_ERR(page
);
2303 /* Ensure that the associated pages are gathered from the backing storage
2304 * and pinned into our object. i915_gem_object_get_pages() may be called
2305 * multiple times before they are released by a single call to
2306 * i915_gem_object_put_pages() - once the pages are no longer referenced
2307 * either as a result of memory pressure (reaping pages under the shrinker)
2308 * or as the object is itself released.
2311 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2313 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2314 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2320 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2321 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2325 BUG_ON(obj
->pages_pin_count
);
2327 ret
= ops
->get_pages(obj
);
2331 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2333 obj
->get_page
.sg
= obj
->pages
->sgl
;
2334 obj
->get_page
.last
= 0;
2339 void i915_vma_move_to_active(struct i915_vma
*vma
,
2340 struct intel_engine_cs
*ring
)
2342 struct drm_i915_gem_object
*obj
= vma
->obj
;
2344 /* Add a reference if we're newly entering the active list. */
2345 if (obj
->active
== 0)
2346 drm_gem_object_reference(&obj
->base
);
2347 obj
->active
|= intel_ring_flag(ring
);
2349 list_move_tail(&obj
->ring_list
[ring
->id
], &ring
->active_list
);
2350 i915_gem_request_assign(&obj
->last_read_req
[ring
->id
],
2351 intel_ring_get_request(ring
));
2353 list_move_tail(&vma
->mm_list
, &vma
->vm
->active_list
);
2357 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
)
2359 RQ_BUG_ON(obj
->last_write_req
== NULL
);
2360 RQ_BUG_ON(!(obj
->active
& intel_ring_flag(obj
->last_write_req
->ring
)));
2362 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
2363 intel_fb_obj_flush(obj
, true);
2367 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
)
2369 struct i915_vma
*vma
;
2371 RQ_BUG_ON(obj
->last_read_req
[ring
] == NULL
);
2372 RQ_BUG_ON(!(obj
->active
& (1 << ring
)));
2374 list_del_init(&obj
->ring_list
[ring
]);
2375 i915_gem_request_assign(&obj
->last_read_req
[ring
], NULL
);
2377 if (obj
->last_write_req
&& obj
->last_write_req
->ring
->id
== ring
)
2378 i915_gem_object_retire__write(obj
);
2380 obj
->active
&= ~(1 << ring
);
2384 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
2385 if (!list_empty(&vma
->mm_list
))
2386 list_move_tail(&vma
->mm_list
, &vma
->vm
->inactive_list
);
2389 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
2390 drm_gem_object_unreference(&obj
->base
);
2394 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
2396 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2397 struct intel_engine_cs
*ring
;
2400 /* Carefully retire all requests without writing to the rings */
2401 for_each_ring(ring
, dev_priv
, i
) {
2402 ret
= intel_ring_idle(ring
);
2406 i915_gem_retire_requests(dev
);
2408 /* Finally reset hw state */
2409 for_each_ring(ring
, dev_priv
, i
) {
2410 intel_ring_init_seqno(ring
, seqno
);
2412 for (j
= 0; j
< ARRAY_SIZE(ring
->semaphore
.sync_seqno
); j
++)
2413 ring
->semaphore
.sync_seqno
[j
] = 0;
2419 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2421 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2427 /* HWS page needs to be set less than what we
2428 * will inject to ring
2430 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
2434 /* Carefully set the last_seqno value so that wrap
2435 * detection still works
2437 dev_priv
->next_seqno
= seqno
;
2438 dev_priv
->last_seqno
= seqno
- 1;
2439 if (dev_priv
->last_seqno
== 0)
2440 dev_priv
->last_seqno
--;
2446 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
2448 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2450 /* reserve 0 for non-seqno */
2451 if (dev_priv
->next_seqno
== 0) {
2452 int ret
= i915_gem_init_seqno(dev
, 0);
2456 dev_priv
->next_seqno
= 1;
2459 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2463 int __i915_add_request(struct intel_engine_cs
*ring
,
2464 struct drm_file
*file
,
2465 struct drm_i915_gem_object
*obj
)
2467 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2468 struct drm_i915_gem_request
*request
;
2469 struct intel_ringbuffer
*ringbuf
;
2473 request
= ring
->outstanding_lazy_request
;
2474 if (WARN_ON(request
== NULL
))
2477 if (i915
.enable_execlists
) {
2478 ringbuf
= request
->ctx
->engine
[ring
->id
].ringbuf
;
2480 ringbuf
= ring
->buffer
;
2482 request_start
= intel_ring_get_tail(ringbuf
);
2484 * Emit any outstanding flushes - execbuf can fail to emit the flush
2485 * after having emitted the batchbuffer command. Hence we need to fix
2486 * things up similar to emitting the lazy request. The difference here
2487 * is that the flush _must_ happen before the next request, no matter
2490 if (i915
.enable_execlists
) {
2491 ret
= logical_ring_flush_all_caches(ringbuf
, request
->ctx
);
2495 ret
= intel_ring_flush_all_caches(ring
);
2500 /* Record the position of the start of the request so that
2501 * should we detect the updated seqno part-way through the
2502 * GPU processing the request, we never over-estimate the
2503 * position of the head.
2505 request
->postfix
= intel_ring_get_tail(ringbuf
);
2507 if (i915
.enable_execlists
) {
2508 ret
= ring
->emit_request(ringbuf
, request
);
2512 ret
= ring
->add_request(ring
);
2516 request
->tail
= intel_ring_get_tail(ringbuf
);
2519 request
->head
= request_start
;
2521 /* Whilst this request exists, batch_obj will be on the
2522 * active_list, and so will hold the active reference. Only when this
2523 * request is retired will the the batch_obj be moved onto the
2524 * inactive_list and lose its active reference. Hence we do not need
2525 * to explicitly hold another reference here.
2527 request
->batch_obj
= obj
;
2529 if (!i915
.enable_execlists
) {
2530 /* Hold a reference to the current context so that we can inspect
2531 * it later in case a hangcheck error event fires.
2533 request
->ctx
= ring
->last_context
;
2535 i915_gem_context_reference(request
->ctx
);
2538 request
->emitted_jiffies
= jiffies
;
2539 list_add_tail(&request
->list
, &ring
->request_list
);
2540 request
->file_priv
= NULL
;
2543 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2545 spin_lock(&file_priv
->mm
.lock
);
2546 request
->file_priv
= file_priv
;
2547 list_add_tail(&request
->client_list
,
2548 &file_priv
->mm
.request_list
);
2549 spin_unlock(&file_priv
->mm
.lock
);
2551 request
->pid
= get_pid(task_pid(current
));
2554 trace_i915_gem_request_add(request
);
2555 ring
->outstanding_lazy_request
= NULL
;
2557 i915_queue_hangcheck(ring
->dev
);
2559 queue_delayed_work(dev_priv
->wq
,
2560 &dev_priv
->mm
.retire_work
,
2561 round_jiffies_up_relative(HZ
));
2562 intel_mark_busy(dev_priv
->dev
);
2567 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2568 const struct intel_context
*ctx
)
2570 unsigned long elapsed
;
2572 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2574 if (ctx
->hang_stats
.banned
)
2577 if (ctx
->hang_stats
.ban_period_seconds
&&
2578 elapsed
<= ctx
->hang_stats
.ban_period_seconds
) {
2579 if (!i915_gem_context_is_default(ctx
)) {
2580 DRM_DEBUG("context hanging too fast, banning!\n");
2582 } else if (i915_stop_ring_allow_ban(dev_priv
)) {
2583 if (i915_stop_ring_allow_warn(dev_priv
))
2584 DRM_ERROR("gpu hanging too fast, banning!\n");
2592 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2593 struct intel_context
*ctx
,
2596 struct i915_ctx_hang_stats
*hs
;
2601 hs
= &ctx
->hang_stats
;
2604 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2606 hs
->guilty_ts
= get_seconds();
2608 hs
->batch_pending
++;
2612 void i915_gem_request_free(struct kref
*req_ref
)
2614 struct drm_i915_gem_request
*req
= container_of(req_ref
,
2616 struct intel_context
*ctx
= req
->ctx
;
2619 if (i915
.enable_execlists
) {
2620 struct intel_engine_cs
*ring
= req
->ring
;
2622 if (ctx
!= ring
->default_context
)
2623 intel_lr_context_unpin(ring
, ctx
);
2626 i915_gem_context_unreference(ctx
);
2629 kmem_cache_free(req
->i915
->requests
, req
);
2632 int i915_gem_request_alloc(struct intel_engine_cs
*ring
,
2633 struct intel_context
*ctx
)
2635 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
2636 struct drm_i915_gem_request
*req
;
2639 if (ring
->outstanding_lazy_request
)
2642 req
= kmem_cache_zalloc(dev_priv
->requests
, GFP_KERNEL
);
2646 kref_init(&req
->ref
);
2647 req
->i915
= dev_priv
;
2649 ret
= i915_gem_get_seqno(ring
->dev
, &req
->seqno
);
2657 if (i915
.enable_execlists
)
2658 ret
= intel_logical_ring_alloc_request_extras(req
, ctx
);
2660 ret
= intel_ring_alloc_request_extras(req
);
2666 ring
->outstanding_lazy_request
= req
;
2670 struct drm_i915_gem_request
*
2671 i915_gem_find_active_request(struct intel_engine_cs
*ring
)
2673 struct drm_i915_gem_request
*request
;
2675 list_for_each_entry(request
, &ring
->request_list
, list
) {
2676 if (i915_gem_request_completed(request
, false))
2685 static void i915_gem_reset_ring_status(struct drm_i915_private
*dev_priv
,
2686 struct intel_engine_cs
*ring
)
2688 struct drm_i915_gem_request
*request
;
2691 request
= i915_gem_find_active_request(ring
);
2693 if (request
== NULL
)
2696 ring_hung
= ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
2698 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
2700 list_for_each_entry_continue(request
, &ring
->request_list
, list
)
2701 i915_set_reset_status(dev_priv
, request
->ctx
, false);
2704 static void i915_gem_reset_ring_cleanup(struct drm_i915_private
*dev_priv
,
2705 struct intel_engine_cs
*ring
)
2707 while (!list_empty(&ring
->active_list
)) {
2708 struct drm_i915_gem_object
*obj
;
2710 obj
= list_first_entry(&ring
->active_list
,
2711 struct drm_i915_gem_object
,
2712 ring_list
[ring
->id
]);
2714 i915_gem_object_retire__read(obj
, ring
->id
);
2718 * Clear the execlists queue up before freeing the requests, as those
2719 * are the ones that keep the context and ringbuffer backing objects
2722 while (!list_empty(&ring
->execlist_queue
)) {
2723 struct drm_i915_gem_request
*submit_req
;
2725 submit_req
= list_first_entry(&ring
->execlist_queue
,
2726 struct drm_i915_gem_request
,
2728 list_del(&submit_req
->execlist_link
);
2730 if (submit_req
->ctx
!= ring
->default_context
)
2731 intel_lr_context_unpin(ring
, submit_req
->ctx
);
2733 i915_gem_request_unreference(submit_req
);
2737 * We must free the requests after all the corresponding objects have
2738 * been moved off active lists. Which is the same order as the normal
2739 * retire_requests function does. This is important if object hold
2740 * implicit references on things like e.g. ppgtt address spaces through
2743 while (!list_empty(&ring
->request_list
)) {
2744 struct drm_i915_gem_request
*request
;
2746 request
= list_first_entry(&ring
->request_list
,
2747 struct drm_i915_gem_request
,
2750 i915_gem_request_retire(request
);
2753 /* This may not have been flushed before the reset, so clean it now */
2754 i915_gem_request_assign(&ring
->outstanding_lazy_request
, NULL
);
2757 void i915_gem_restore_fences(struct drm_device
*dev
)
2759 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2762 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2763 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2766 * Commit delayed tiling changes if we have an object still
2767 * attached to the fence, otherwise just clear the fence.
2770 i915_gem_object_update_fence(reg
->obj
, reg
,
2771 reg
->obj
->tiling_mode
);
2773 i915_gem_write_fence(dev
, i
, NULL
);
2778 void i915_gem_reset(struct drm_device
*dev
)
2780 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2781 struct intel_engine_cs
*ring
;
2785 * Before we free the objects from the requests, we need to inspect
2786 * them for finding the guilty party. As the requests only borrow
2787 * their reference to the objects, the inspection must be done first.
2789 for_each_ring(ring
, dev_priv
, i
)
2790 i915_gem_reset_ring_status(dev_priv
, ring
);
2792 for_each_ring(ring
, dev_priv
, i
)
2793 i915_gem_reset_ring_cleanup(dev_priv
, ring
);
2795 i915_gem_context_reset(dev
);
2797 i915_gem_restore_fences(dev
);
2799 WARN_ON(i915_verify_lists(dev
));
2803 * This function clears the request list as sequence numbers are passed.
2806 i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
)
2808 WARN_ON(i915_verify_lists(ring
->dev
));
2810 if (list_empty(&ring
->active_list
))
2813 /* Retire requests first as we use it above for the early return.
2814 * If we retire requests last, we may use a later seqno and so clear
2815 * the requests lists without clearing the active list, leading to
2818 while (!list_empty(&ring
->request_list
)) {
2819 struct drm_i915_gem_request
*request
;
2821 request
= list_first_entry(&ring
->request_list
,
2822 struct drm_i915_gem_request
,
2825 if (!i915_gem_request_completed(request
, true))
2828 i915_gem_request_retire(request
);
2831 /* Move any buffers on the active list that are no longer referenced
2832 * by the ringbuffer to the flushing/inactive lists as appropriate,
2833 * before we free the context associated with the requests.
2835 while (!list_empty(&ring
->active_list
)) {
2836 struct drm_i915_gem_object
*obj
;
2838 obj
= list_first_entry(&ring
->active_list
,
2839 struct drm_i915_gem_object
,
2840 ring_list
[ring
->id
]);
2842 if (!list_empty(&obj
->last_read_req
[ring
->id
]->list
))
2845 i915_gem_object_retire__read(obj
, ring
->id
);
2848 if (unlikely(ring
->trace_irq_req
&&
2849 i915_gem_request_completed(ring
->trace_irq_req
, true))) {
2850 ring
->irq_put(ring
);
2851 i915_gem_request_assign(&ring
->trace_irq_req
, NULL
);
2854 WARN_ON(i915_verify_lists(ring
->dev
));
2858 i915_gem_retire_requests(struct drm_device
*dev
)
2860 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2861 struct intel_engine_cs
*ring
;
2865 for_each_ring(ring
, dev_priv
, i
) {
2866 i915_gem_retire_requests_ring(ring
);
2867 idle
&= list_empty(&ring
->request_list
);
2868 if (i915
.enable_execlists
) {
2869 unsigned long flags
;
2871 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
2872 idle
&= list_empty(&ring
->execlist_queue
);
2873 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
2875 intel_execlists_retire_requests(ring
);
2880 mod_delayed_work(dev_priv
->wq
,
2881 &dev_priv
->mm
.idle_work
,
2882 msecs_to_jiffies(100));
2888 i915_gem_retire_work_handler(struct work_struct
*work
)
2890 struct drm_i915_private
*dev_priv
=
2891 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
2892 struct drm_device
*dev
= dev_priv
->dev
;
2895 /* Come back later if the device is busy... */
2897 if (mutex_trylock(&dev
->struct_mutex
)) {
2898 idle
= i915_gem_retire_requests(dev
);
2899 mutex_unlock(&dev
->struct_mutex
);
2902 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2903 round_jiffies_up_relative(HZ
));
2907 i915_gem_idle_work_handler(struct work_struct
*work
)
2909 struct drm_i915_private
*dev_priv
=
2910 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
2911 struct drm_device
*dev
= dev_priv
->dev
;
2912 struct intel_engine_cs
*ring
;
2915 for_each_ring(ring
, dev_priv
, i
)
2916 if (!list_empty(&ring
->request_list
))
2919 intel_mark_idle(dev
);
2921 if (mutex_trylock(&dev
->struct_mutex
)) {
2922 struct intel_engine_cs
*ring
;
2925 for_each_ring(ring
, dev_priv
, i
)
2926 i915_gem_batch_pool_fini(&ring
->batch_pool
);
2928 mutex_unlock(&dev
->struct_mutex
);
2933 * Ensures that an object will eventually get non-busy by flushing any required
2934 * write domains, emitting any outstanding lazy request and retiring and
2935 * completed requests.
2938 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2945 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
2946 struct drm_i915_gem_request
*req
;
2948 req
= obj
->last_read_req
[i
];
2952 if (list_empty(&req
->list
))
2955 ret
= i915_gem_check_olr(req
);
2959 if (i915_gem_request_completed(req
, true)) {
2960 __i915_gem_request_retire__upto(req
);
2962 i915_gem_object_retire__read(obj
, i
);
2970 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2971 * @DRM_IOCTL_ARGS: standard ioctl arguments
2973 * Returns 0 if successful, else an error is returned with the remaining time in
2974 * the timeout parameter.
2975 * -ETIME: object is still busy after timeout
2976 * -ERESTARTSYS: signal interrupted the wait
2977 * -ENONENT: object doesn't exist
2978 * Also possible, but rare:
2979 * -EAGAIN: GPU wedged
2981 * -ENODEV: Internal IRQ fail
2982 * -E?: The add request failed
2984 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2985 * non-zero timeout parameter the wait ioctl will wait for the given number of
2986 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2987 * without holding struct_mutex the object may become re-busied before this
2988 * function completes. A similar but shorter * race condition exists in the busy
2992 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2994 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2995 struct drm_i915_gem_wait
*args
= data
;
2996 struct drm_i915_gem_object
*obj
;
2997 struct drm_i915_gem_request
*req
[I915_NUM_RINGS
];
2998 unsigned reset_counter
;
3002 if (args
->flags
!= 0)
3005 ret
= i915_mutex_lock_interruptible(dev
);
3009 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
3010 if (&obj
->base
== NULL
) {
3011 mutex_unlock(&dev
->struct_mutex
);
3015 /* Need to make sure the object gets inactive eventually. */
3016 ret
= i915_gem_object_flush_active(obj
);
3023 /* Do this after OLR check to make sure we make forward progress polling
3024 * on this IOCTL with a timeout == 0 (like busy ioctl)
3026 if (args
->timeout_ns
== 0) {
3031 drm_gem_object_unreference(&obj
->base
);
3032 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3034 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
3035 if (obj
->last_read_req
[i
] == NULL
)
3038 req
[n
++] = i915_gem_request_reference(obj
->last_read_req
[i
]);
3041 mutex_unlock(&dev
->struct_mutex
);
3043 for (i
= 0; i
< n
; i
++) {
3045 ret
= __i915_wait_request(req
[i
], reset_counter
, true,
3046 args
->timeout_ns
> 0 ? &args
->timeout_ns
: NULL
,
3048 i915_gem_request_unreference__unlocked(req
[i
]);
3053 drm_gem_object_unreference(&obj
->base
);
3054 mutex_unlock(&dev
->struct_mutex
);
3059 __i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3060 struct intel_engine_cs
*to
,
3061 struct drm_i915_gem_request
*req
)
3063 struct intel_engine_cs
*from
;
3066 from
= i915_gem_request_get_ring(req
);
3070 if (i915_gem_request_completed(req
, true))
3073 ret
= i915_gem_check_olr(req
);
3077 if (!i915_semaphore_is_enabled(obj
->base
.dev
)) {
3078 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
3079 ret
= __i915_wait_request(req
,
3080 atomic_read(&i915
->gpu_error
.reset_counter
),
3081 i915
->mm
.interruptible
,
3083 &i915
->rps
.semaphores
);
3087 i915_gem_object_retire_request(obj
, req
);
3089 int idx
= intel_ring_sync_index(from
, to
);
3090 u32 seqno
= i915_gem_request_get_seqno(req
);
3092 if (seqno
<= from
->semaphore
.sync_seqno
[idx
])
3095 trace_i915_gem_ring_sync_to(from
, to
, req
);
3096 ret
= to
->semaphore
.sync_to(to
, from
, seqno
);
3100 /* We use last_read_req because sync_to()
3101 * might have just caused seqno wrap under
3104 from
->semaphore
.sync_seqno
[idx
] =
3105 i915_gem_request_get_seqno(obj
->last_read_req
[from
->id
]);
3112 * i915_gem_object_sync - sync an object to a ring.
3114 * @obj: object which may be in use on another ring.
3115 * @to: ring we wish to use the object on. May be NULL.
3117 * This code is meant to abstract object synchronization with the GPU.
3118 * Calling with NULL implies synchronizing the object with the CPU
3119 * rather than a particular GPU ring. Conceptually we serialise writes
3120 * between engines inside the GPU. We only allow on engine to write
3121 * into a buffer at any time, but multiple readers. To ensure each has
3122 * a coherent view of memory, we must:
3124 * - If there is an outstanding write request to the object, the new
3125 * request must wait for it to complete (either CPU or in hw, requests
3126 * on the same ring will be naturally ordered).
3128 * - If we are a write request (pending_write_domain is set), the new
3129 * request must wait for outstanding read requests to complete.
3131 * Returns 0 if successful, else propagates up the lower layer error.
3134 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3135 struct intel_engine_cs
*to
)
3137 const bool readonly
= obj
->base
.pending_write_domain
== 0;
3138 struct drm_i915_gem_request
*req
[I915_NUM_RINGS
];
3145 return i915_gem_object_wait_rendering(obj
, readonly
);
3149 if (obj
->last_write_req
)
3150 req
[n
++] = obj
->last_write_req
;
3152 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
3153 if (obj
->last_read_req
[i
])
3154 req
[n
++] = obj
->last_read_req
[i
];
3156 for (i
= 0; i
< n
; i
++) {
3157 ret
= __i915_gem_object_sync(obj
, to
, req
[i
]);
3165 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
3167 u32 old_write_domain
, old_read_domains
;
3169 /* Force a pagefault for domain tracking on next user access */
3170 i915_gem_release_mmap(obj
);
3172 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3175 /* Wait for any direct GTT access to complete */
3178 old_read_domains
= obj
->base
.read_domains
;
3179 old_write_domain
= obj
->base
.write_domain
;
3181 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
3182 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
3184 trace_i915_gem_object_change_domain(obj
,
3189 int i915_vma_unbind(struct i915_vma
*vma
)
3191 struct drm_i915_gem_object
*obj
= vma
->obj
;
3192 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3195 if (list_empty(&vma
->vma_link
))
3198 if (!drm_mm_node_allocated(&vma
->node
)) {
3199 i915_gem_vma_destroy(vma
);
3206 BUG_ON(obj
->pages
== NULL
);
3208 ret
= i915_gem_object_wait_rendering(obj
, false);
3211 /* Continue on if we fail due to EIO, the GPU is hung so we
3212 * should be safe and we need to cleanup or else we might
3213 * cause memory corruption through use-after-free.
3216 if (i915_is_ggtt(vma
->vm
) &&
3217 vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3218 i915_gem_object_finish_gtt(obj
);
3220 /* release the fence reg _after_ flushing */
3221 ret
= i915_gem_object_put_fence(obj
);
3226 trace_i915_vma_unbind(vma
);
3228 vma
->vm
->unbind_vma(vma
);
3231 list_del_init(&vma
->mm_list
);
3232 if (i915_is_ggtt(vma
->vm
)) {
3233 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3234 obj
->map_and_fenceable
= false;
3235 } else if (vma
->ggtt_view
.pages
) {
3236 sg_free_table(vma
->ggtt_view
.pages
);
3237 kfree(vma
->ggtt_view
.pages
);
3238 vma
->ggtt_view
.pages
= NULL
;
3242 drm_mm_remove_node(&vma
->node
);
3243 i915_gem_vma_destroy(vma
);
3245 /* Since the unbound list is global, only move to that list if
3246 * no more VMAs exist. */
3247 if (list_empty(&obj
->vma_list
)) {
3248 i915_gem_gtt_finish_object(obj
);
3249 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
3252 /* And finally now the object is completely decoupled from this vma,
3253 * we can drop its hold on the backing storage and allow it to be
3254 * reaped by the shrinker.
3256 i915_gem_object_unpin_pages(obj
);
3261 int i915_gpu_idle(struct drm_device
*dev
)
3263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3264 struct intel_engine_cs
*ring
;
3267 /* Flush everything onto the inactive list. */
3268 for_each_ring(ring
, dev_priv
, i
) {
3269 if (!i915
.enable_execlists
) {
3270 ret
= i915_switch_context(ring
, ring
->default_context
);
3275 ret
= intel_ring_idle(ring
);
3280 WARN_ON(i915_verify_lists(dev
));
3284 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
3285 struct drm_i915_gem_object
*obj
)
3287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3289 int fence_pitch_shift
;
3291 if (INTEL_INFO(dev
)->gen
>= 6) {
3292 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
3293 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
3295 fence_reg
= FENCE_REG_965_0
;
3296 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
3299 fence_reg
+= reg
* 8;
3301 /* To w/a incoherency with non-atomic 64-bit register updates,
3302 * we split the 64-bit update into two 32-bit writes. In order
3303 * for a partial fence not to be evaluated between writes, we
3304 * precede the update with write to turn off the fence register,
3305 * and only enable the fence as the last step.
3307 * For extra levels of paranoia, we make sure each step lands
3308 * before applying the next step.
3310 I915_WRITE(fence_reg
, 0);
3311 POSTING_READ(fence_reg
);
3314 u32 size
= i915_gem_obj_ggtt_size(obj
);
3317 /* Adjust fence size to match tiled area */
3318 if (obj
->tiling_mode
!= I915_TILING_NONE
) {
3319 uint32_t row_size
= obj
->stride
*
3320 (obj
->tiling_mode
== I915_TILING_Y
? 32 : 8);
3321 size
= (size
/ row_size
) * row_size
;
3324 val
= (uint64_t)((i915_gem_obj_ggtt_offset(obj
) + size
- 4096) &
3326 val
|= i915_gem_obj_ggtt_offset(obj
) & 0xfffff000;
3327 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
3328 if (obj
->tiling_mode
== I915_TILING_Y
)
3329 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
3330 val
|= I965_FENCE_REG_VALID
;
3332 I915_WRITE(fence_reg
+ 4, val
>> 32);
3333 POSTING_READ(fence_reg
+ 4);
3335 I915_WRITE(fence_reg
+ 0, val
);
3336 POSTING_READ(fence_reg
);
3338 I915_WRITE(fence_reg
+ 4, 0);
3339 POSTING_READ(fence_reg
+ 4);
3343 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
3344 struct drm_i915_gem_object
*obj
)
3346 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3350 u32 size
= i915_gem_obj_ggtt_size(obj
);
3354 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I915_FENCE_START_MASK
) ||
3355 (size
& -size
) != size
||
3356 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3357 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3358 i915_gem_obj_ggtt_offset(obj
), obj
->map_and_fenceable
, size
);
3360 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
3365 /* Note: pitch better be a power of two tile widths */
3366 pitch_val
= obj
->stride
/ tile_width
;
3367 pitch_val
= ffs(pitch_val
) - 1;
3369 val
= i915_gem_obj_ggtt_offset(obj
);
3370 if (obj
->tiling_mode
== I915_TILING_Y
)
3371 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3372 val
|= I915_FENCE_SIZE_BITS(size
);
3373 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3374 val
|= I830_FENCE_REG_VALID
;
3379 reg
= FENCE_REG_830_0
+ reg
* 4;
3381 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
3383 I915_WRITE(reg
, val
);
3387 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
3388 struct drm_i915_gem_object
*obj
)
3390 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3394 u32 size
= i915_gem_obj_ggtt_size(obj
);
3397 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I830_FENCE_START_MASK
) ||
3398 (size
& -size
) != size
||
3399 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3400 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3401 i915_gem_obj_ggtt_offset(obj
), size
);
3403 pitch_val
= obj
->stride
/ 128;
3404 pitch_val
= ffs(pitch_val
) - 1;
3406 val
= i915_gem_obj_ggtt_offset(obj
);
3407 if (obj
->tiling_mode
== I915_TILING_Y
)
3408 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3409 val
|= I830_FENCE_SIZE_BITS(size
);
3410 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3411 val
|= I830_FENCE_REG_VALID
;
3415 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
3416 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
3419 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
3421 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
3424 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
3425 struct drm_i915_gem_object
*obj
)
3427 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3429 /* Ensure that all CPU reads are completed before installing a fence
3430 * and all writes before removing the fence.
3432 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
3435 WARN(obj
&& (!obj
->stride
|| !obj
->tiling_mode
),
3436 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3437 obj
->stride
, obj
->tiling_mode
);
3440 i830_write_fence_reg(dev
, reg
, obj
);
3441 else if (IS_GEN3(dev
))
3442 i915_write_fence_reg(dev
, reg
, obj
);
3443 else if (INTEL_INFO(dev
)->gen
>= 4)
3444 i965_write_fence_reg(dev
, reg
, obj
);
3446 /* And similarly be paranoid that no direct access to this region
3447 * is reordered to before the fence is installed.
3449 if (i915_gem_object_needs_mb(obj
))
3453 static inline int fence_number(struct drm_i915_private
*dev_priv
,
3454 struct drm_i915_fence_reg
*fence
)
3456 return fence
- dev_priv
->fence_regs
;
3459 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
3460 struct drm_i915_fence_reg
*fence
,
3463 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3464 int reg
= fence_number(dev_priv
, fence
);
3466 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
3469 obj
->fence_reg
= reg
;
3471 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
3473 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3475 list_del_init(&fence
->lru_list
);
3477 obj
->fence_dirty
= false;
3481 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
3483 if (obj
->last_fenced_req
) {
3484 int ret
= i915_wait_request(obj
->last_fenced_req
);
3488 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
3495 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
3497 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3498 struct drm_i915_fence_reg
*fence
;
3501 ret
= i915_gem_object_wait_fence(obj
);
3505 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
3508 fence
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3510 if (WARN_ON(fence
->pin_count
))
3513 i915_gem_object_fence_lost(obj
);
3514 i915_gem_object_update_fence(obj
, fence
, false);
3519 static struct drm_i915_fence_reg
*
3520 i915_find_fence_reg(struct drm_device
*dev
)
3522 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3523 struct drm_i915_fence_reg
*reg
, *avail
;
3526 /* First try to find a free reg */
3528 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
3529 reg
= &dev_priv
->fence_regs
[i
];
3533 if (!reg
->pin_count
)
3540 /* None available, try to steal one or wait for a user to finish */
3541 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
3549 /* Wait for completion of pending flips which consume fences */
3550 if (intel_has_pending_fb_unpin(dev
))
3551 return ERR_PTR(-EAGAIN
);
3553 return ERR_PTR(-EDEADLK
);
3557 * i915_gem_object_get_fence - set up fencing for an object
3558 * @obj: object to map through a fence reg
3560 * When mapping objects through the GTT, userspace wants to be able to write
3561 * to them without having to worry about swizzling if the object is tiled.
3562 * This function walks the fence regs looking for a free one for @obj,
3563 * stealing one if it can't find any.
3565 * It then sets up the reg based on the object's properties: address, pitch
3566 * and tiling format.
3568 * For an untiled surface, this removes any existing fence.
3571 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
3573 struct drm_device
*dev
= obj
->base
.dev
;
3574 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3575 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
3576 struct drm_i915_fence_reg
*reg
;
3579 /* Have we updated the tiling parameters upon the object and so
3580 * will need to serialise the write to the associated fence register?
3582 if (obj
->fence_dirty
) {
3583 ret
= i915_gem_object_wait_fence(obj
);
3588 /* Just update our place in the LRU if our fence is getting reused. */
3589 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
3590 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3591 if (!obj
->fence_dirty
) {
3592 list_move_tail(®
->lru_list
,
3593 &dev_priv
->mm
.fence_list
);
3596 } else if (enable
) {
3597 if (WARN_ON(!obj
->map_and_fenceable
))
3600 reg
= i915_find_fence_reg(dev
);
3602 return PTR_ERR(reg
);
3605 struct drm_i915_gem_object
*old
= reg
->obj
;
3607 ret
= i915_gem_object_wait_fence(old
);
3611 i915_gem_object_fence_lost(old
);
3616 i915_gem_object_update_fence(obj
, reg
, enable
);
3621 static bool i915_gem_valid_gtt_space(struct i915_vma
*vma
,
3622 unsigned long cache_level
)
3624 struct drm_mm_node
*gtt_space
= &vma
->node
;
3625 struct drm_mm_node
*other
;
3628 * On some machines we have to be careful when putting differing types
3629 * of snoopable memory together to avoid the prefetcher crossing memory
3630 * domains and dying. During vm initialisation, we decide whether or not
3631 * these constraints apply and set the drm_mm.color_adjust
3634 if (vma
->vm
->mm
.color_adjust
== NULL
)
3637 if (!drm_mm_node_allocated(gtt_space
))
3640 if (list_empty(>t_space
->node_list
))
3643 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3644 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3647 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3648 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3655 * Finds free space in the GTT aperture and binds the object or a view of it
3658 static struct i915_vma
*
3659 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3660 struct i915_address_space
*vm
,
3661 const struct i915_ggtt_view
*ggtt_view
,
3665 struct drm_device
*dev
= obj
->base
.dev
;
3666 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3667 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
3668 unsigned long start
=
3669 flags
& PIN_OFFSET_BIAS
? flags
& PIN_OFFSET_MASK
: 0;
3671 flags
& PIN_MAPPABLE
? dev_priv
->gtt
.mappable_end
: vm
->total
;
3672 struct i915_vma
*vma
;
3675 if (i915_is_ggtt(vm
)) {
3678 if (WARN_ON(!ggtt_view
))
3679 return ERR_PTR(-EINVAL
);
3681 view_size
= i915_ggtt_view_size(obj
, ggtt_view
);
3683 fence_size
= i915_gem_get_gtt_size(dev
,
3686 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3690 unfenced_alignment
= i915_gem_get_gtt_alignment(dev
,
3694 size
= flags
& PIN_MAPPABLE
? fence_size
: view_size
;
3696 fence_size
= i915_gem_get_gtt_size(dev
,
3699 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3703 unfenced_alignment
=
3704 i915_gem_get_gtt_alignment(dev
,
3708 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3712 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3714 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3715 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3716 ggtt_view
? ggtt_view
->type
: 0,
3718 return ERR_PTR(-EINVAL
);
3721 /* If binding the object/GGTT view requires more space than the entire
3722 * aperture has, reject it early before evicting everything in a vain
3723 * attempt to find space.
3726 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%u > %s aperture=%lu\n",
3727 ggtt_view
? ggtt_view
->type
: 0,
3729 flags
& PIN_MAPPABLE
? "mappable" : "total",
3731 return ERR_PTR(-E2BIG
);
3734 ret
= i915_gem_object_get_pages(obj
);
3736 return ERR_PTR(ret
);
3738 i915_gem_object_pin_pages(obj
);
3740 vma
= ggtt_view
? i915_gem_obj_lookup_or_create_ggtt_vma(obj
, ggtt_view
) :
3741 i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3747 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3751 DRM_MM_SEARCH_DEFAULT
,
3752 DRM_MM_CREATE_DEFAULT
);
3754 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3763 if (WARN_ON(!i915_gem_valid_gtt_space(vma
, obj
->cache_level
))) {
3765 goto err_remove_node
;
3768 ret
= i915_gem_gtt_prepare_object(obj
);
3770 goto err_remove_node
;
3772 trace_i915_vma_bind(vma
, flags
);
3773 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
3775 goto err_finish_gtt
;
3777 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3778 list_add_tail(&vma
->mm_list
, &vm
->inactive_list
);
3783 i915_gem_gtt_finish_object(obj
);
3785 drm_mm_remove_node(&vma
->node
);
3787 i915_gem_vma_destroy(vma
);
3790 i915_gem_object_unpin_pages(obj
);
3795 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3798 /* If we don't have a page list set up, then we're not pinned
3799 * to GPU, and we can ignore the cache flush because it'll happen
3800 * again at bind time.
3802 if (obj
->pages
== NULL
)
3806 * Stolen memory is always coherent with the GPU as it is explicitly
3807 * marked as wc by the system, or the system is cache-coherent.
3809 if (obj
->stolen
|| obj
->phys_handle
)
3812 /* If the GPU is snooping the contents of the CPU cache,
3813 * we do not need to manually clear the CPU cache lines. However,
3814 * the caches are only snooped when the render cache is
3815 * flushed/invalidated. As we always have to emit invalidations
3816 * and flushes when moving into and out of the RENDER domain, correct
3817 * snooping behaviour occurs naturally as the result of our domain
3820 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
)) {
3821 obj
->cache_dirty
= true;
3825 trace_i915_gem_object_clflush(obj
);
3826 drm_clflush_sg(obj
->pages
);
3827 obj
->cache_dirty
= false;
3832 /** Flushes the GTT write domain for the object if it's dirty. */
3834 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3836 uint32_t old_write_domain
;
3838 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3841 /* No actual flushing is required for the GTT write domain. Writes
3842 * to it immediately go to main memory as far as we know, so there's
3843 * no chipset flush. It also doesn't land in render cache.
3845 * However, we do have to enforce the order so that all writes through
3846 * the GTT land before any writes to the device, such as updates to
3851 old_write_domain
= obj
->base
.write_domain
;
3852 obj
->base
.write_domain
= 0;
3854 intel_fb_obj_flush(obj
, false);
3856 trace_i915_gem_object_change_domain(obj
,
3857 obj
->base
.read_domains
,
3861 /** Flushes the CPU write domain for the object if it's dirty. */
3863 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3865 uint32_t old_write_domain
;
3867 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3870 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
3871 i915_gem_chipset_flush(obj
->base
.dev
);
3873 old_write_domain
= obj
->base
.write_domain
;
3874 obj
->base
.write_domain
= 0;
3876 intel_fb_obj_flush(obj
, false);
3878 trace_i915_gem_object_change_domain(obj
,
3879 obj
->base
.read_domains
,
3884 * Moves a single object to the GTT read, and possibly write domain.
3886 * This function returns when the move is complete, including waiting on
3890 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3892 uint32_t old_write_domain
, old_read_domains
;
3893 struct i915_vma
*vma
;
3896 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3899 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3903 /* Flush and acquire obj->pages so that we are coherent through
3904 * direct access in memory with previous cached writes through
3905 * shmemfs and that our cache domain tracking remains valid.
3906 * For example, if the obj->filp was moved to swap without us
3907 * being notified and releasing the pages, we would mistakenly
3908 * continue to assume that the obj remained out of the CPU cached
3911 ret
= i915_gem_object_get_pages(obj
);
3915 i915_gem_object_flush_cpu_write_domain(obj
);
3917 /* Serialise direct access to this object with the barriers for
3918 * coherent writes from the GPU, by effectively invalidating the
3919 * GTT domain upon first access.
3921 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3924 old_write_domain
= obj
->base
.write_domain
;
3925 old_read_domains
= obj
->base
.read_domains
;
3927 /* It should now be out of any other write domains, and we can update
3928 * the domain values for our changes.
3930 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3931 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3933 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3934 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3939 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_GTT
);
3941 trace_i915_gem_object_change_domain(obj
,
3945 /* And bump the LRU for this access */
3946 vma
= i915_gem_obj_to_ggtt(obj
);
3947 if (vma
&& drm_mm_node_allocated(&vma
->node
) && !obj
->active
)
3948 list_move_tail(&vma
->mm_list
,
3949 &to_i915(obj
->base
.dev
)->gtt
.base
.inactive_list
);
3954 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3955 enum i915_cache_level cache_level
)
3957 struct drm_device
*dev
= obj
->base
.dev
;
3958 struct i915_vma
*vma
, *next
;
3961 if (obj
->cache_level
== cache_level
)
3964 if (i915_gem_obj_is_pinned(obj
)) {
3965 DRM_DEBUG("can not change the cache level of pinned objects\n");
3969 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
3970 if (!i915_gem_valid_gtt_space(vma
, cache_level
)) {
3971 ret
= i915_vma_unbind(vma
);
3977 if (i915_gem_obj_bound_any(obj
)) {
3978 ret
= i915_gem_object_wait_rendering(obj
, false);
3982 i915_gem_object_finish_gtt(obj
);
3984 /* Before SandyBridge, you could not use tiling or fence
3985 * registers with snooped memory, so relinquish any fences
3986 * currently pointing to our region in the aperture.
3988 if (INTEL_INFO(dev
)->gen
< 6) {
3989 ret
= i915_gem_object_put_fence(obj
);
3994 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3995 if (drm_mm_node_allocated(&vma
->node
)) {
3996 ret
= i915_vma_bind(vma
, cache_level
,
4003 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4004 vma
->node
.color
= cache_level
;
4005 obj
->cache_level
= cache_level
;
4007 if (obj
->cache_dirty
&&
4008 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
4009 cpu_write_needs_clflush(obj
)) {
4010 if (i915_gem_clflush_object(obj
, true))
4011 i915_gem_chipset_flush(obj
->base
.dev
);
4017 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
4018 struct drm_file
*file
)
4020 struct drm_i915_gem_caching
*args
= data
;
4021 struct drm_i915_gem_object
*obj
;
4023 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4024 if (&obj
->base
== NULL
)
4027 switch (obj
->cache_level
) {
4028 case I915_CACHE_LLC
:
4029 case I915_CACHE_L3_LLC
:
4030 args
->caching
= I915_CACHING_CACHED
;
4034 args
->caching
= I915_CACHING_DISPLAY
;
4038 args
->caching
= I915_CACHING_NONE
;
4042 drm_gem_object_unreference_unlocked(&obj
->base
);
4046 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
4047 struct drm_file
*file
)
4049 struct drm_i915_gem_caching
*args
= data
;
4050 struct drm_i915_gem_object
*obj
;
4051 enum i915_cache_level level
;
4054 switch (args
->caching
) {
4055 case I915_CACHING_NONE
:
4056 level
= I915_CACHE_NONE
;
4058 case I915_CACHING_CACHED
:
4059 level
= I915_CACHE_LLC
;
4061 case I915_CACHING_DISPLAY
:
4062 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
4068 ret
= i915_mutex_lock_interruptible(dev
);
4072 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4073 if (&obj
->base
== NULL
) {
4078 ret
= i915_gem_object_set_cache_level(obj
, level
);
4080 drm_gem_object_unreference(&obj
->base
);
4082 mutex_unlock(&dev
->struct_mutex
);
4087 * Prepare buffer for display plane (scanout, cursors, etc).
4088 * Can be called from an uninterruptible phase (modesetting) and allows
4089 * any flushes to be pipelined (for pageflips).
4092 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
4094 struct intel_engine_cs
*pipelined
,
4095 const struct i915_ggtt_view
*view
)
4097 u32 old_read_domains
, old_write_domain
;
4100 ret
= i915_gem_object_sync(obj
, pipelined
);
4104 /* Mark the pin_display early so that we account for the
4105 * display coherency whilst setting up the cache domains.
4109 /* The display engine is not coherent with the LLC cache on gen6. As
4110 * a result, we make sure that the pinning that is about to occur is
4111 * done with uncached PTEs. This is lowest common denominator for all
4114 * However for gen6+, we could do better by using the GFDT bit instead
4115 * of uncaching, which would allow us to flush all the LLC-cached data
4116 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4118 ret
= i915_gem_object_set_cache_level(obj
,
4119 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
4121 goto err_unpin_display
;
4123 /* As the user may map the buffer once pinned in the display plane
4124 * (e.g. libkms for the bootup splash), we have to ensure that we
4125 * always use map_and_fenceable for all scanout buffers.
4127 ret
= i915_gem_object_ggtt_pin(obj
, view
, alignment
,
4128 view
->type
== I915_GGTT_VIEW_NORMAL
?
4131 goto err_unpin_display
;
4133 i915_gem_object_flush_cpu_write_domain(obj
);
4135 old_write_domain
= obj
->base
.write_domain
;
4136 old_read_domains
= obj
->base
.read_domains
;
4138 /* It should now be out of any other write domains, and we can update
4139 * the domain values for our changes.
4141 obj
->base
.write_domain
= 0;
4142 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
4144 trace_i915_gem_object_change_domain(obj
,
4156 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
4157 const struct i915_ggtt_view
*view
)
4159 if (WARN_ON(obj
->pin_display
== 0))
4162 i915_gem_object_ggtt_unpin_view(obj
, view
);
4168 * Moves a single object to the CPU read, and possibly write domain.
4170 * This function returns when the move is complete, including waiting on
4174 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
4176 uint32_t old_write_domain
, old_read_domains
;
4179 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
4182 ret
= i915_gem_object_wait_rendering(obj
, !write
);
4186 i915_gem_object_flush_gtt_write_domain(obj
);
4188 old_write_domain
= obj
->base
.write_domain
;
4189 old_read_domains
= obj
->base
.read_domains
;
4191 /* Flush the CPU cache if it's still invalid. */
4192 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
4193 i915_gem_clflush_object(obj
, false);
4195 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
4198 /* It should now be out of any other write domains, and we can update
4199 * the domain values for our changes.
4201 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
4203 /* If we're writing through the CPU, then the GPU read domains will
4204 * need to be invalidated at next use.
4207 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4208 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4212 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_CPU
);
4214 trace_i915_gem_object_change_domain(obj
,
4221 /* Throttle our rendering by waiting until the ring has completed our requests
4222 * emitted over 20 msec ago.
4224 * Note that if we were to use the current jiffies each time around the loop,
4225 * we wouldn't escape the function with any frames outstanding if the time to
4226 * render a frame was over 20ms.
4228 * This should get us reasonable parallelism between CPU and GPU but also
4229 * relatively low latency when blocking on a particular request to finish.
4232 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
4234 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4235 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4236 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
4237 struct drm_i915_gem_request
*request
, *target
= NULL
;
4238 unsigned reset_counter
;
4241 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
4245 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
4249 spin_lock(&file_priv
->mm
.lock
);
4250 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
4251 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
4256 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
4258 i915_gem_request_reference(target
);
4259 spin_unlock(&file_priv
->mm
.lock
);
4264 ret
= __i915_wait_request(target
, reset_counter
, true, NULL
, NULL
);
4266 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
4268 i915_gem_request_unreference__unlocked(target
);
4274 i915_vma_misplaced(struct i915_vma
*vma
, uint32_t alignment
, uint64_t flags
)
4276 struct drm_i915_gem_object
*obj
= vma
->obj
;
4279 vma
->node
.start
& (alignment
- 1))
4282 if (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)
4285 if (flags
& PIN_OFFSET_BIAS
&&
4286 vma
->node
.start
< (flags
& PIN_OFFSET_MASK
))
4293 i915_gem_object_do_pin(struct drm_i915_gem_object
*obj
,
4294 struct i915_address_space
*vm
,
4295 const struct i915_ggtt_view
*ggtt_view
,
4299 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4300 struct i915_vma
*vma
;
4304 if (WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
))
4307 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
4310 if (WARN_ON((flags
& (PIN_MAPPABLE
| PIN_GLOBAL
)) == PIN_MAPPABLE
))
4313 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
4316 vma
= ggtt_view
? i915_gem_obj_to_ggtt_view(obj
, ggtt_view
) :
4317 i915_gem_obj_to_vma(obj
, vm
);
4320 return PTR_ERR(vma
);
4323 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
4326 if (i915_vma_misplaced(vma
, alignment
, flags
)) {
4327 unsigned long offset
;
4328 offset
= ggtt_view
? i915_gem_obj_ggtt_offset_view(obj
, ggtt_view
) :
4329 i915_gem_obj_offset(obj
, vm
);
4330 WARN(vma
->pin_count
,
4331 "bo is already pinned in %s with incorrect alignment:"
4332 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4333 " obj->map_and_fenceable=%d\n",
4334 ggtt_view
? "ggtt" : "ppgtt",
4337 !!(flags
& PIN_MAPPABLE
),
4338 obj
->map_and_fenceable
);
4339 ret
= i915_vma_unbind(vma
);
4347 bound
= vma
? vma
->bound
: 0;
4348 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
4349 vma
= i915_gem_object_bind_to_vm(obj
, vm
, ggtt_view
, alignment
,
4352 return PTR_ERR(vma
);
4354 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
4359 if (ggtt_view
&& ggtt_view
->type
== I915_GGTT_VIEW_NORMAL
&&
4360 (bound
^ vma
->bound
) & GLOBAL_BIND
) {
4361 bool mappable
, fenceable
;
4362 u32 fence_size
, fence_alignment
;
4364 fence_size
= i915_gem_get_gtt_size(obj
->base
.dev
,
4367 fence_alignment
= i915_gem_get_gtt_alignment(obj
->base
.dev
,
4372 fenceable
= (vma
->node
.size
== fence_size
&&
4373 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
4375 mappable
= (vma
->node
.start
+ fence_size
<=
4376 dev_priv
->gtt
.mappable_end
);
4378 obj
->map_and_fenceable
= mappable
&& fenceable
;
4380 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
4388 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
4389 struct i915_address_space
*vm
,
4393 return i915_gem_object_do_pin(obj
, vm
,
4394 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
,
4399 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
4400 const struct i915_ggtt_view
*view
,
4404 if (WARN_ONCE(!view
, "no view specified"))
4407 return i915_gem_object_do_pin(obj
, i915_obj_to_ggtt(obj
), view
,
4408 alignment
, flags
| PIN_GLOBAL
);
4412 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
4413 const struct i915_ggtt_view
*view
)
4415 struct i915_vma
*vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
4418 WARN_ON(vma
->pin_count
== 0);
4419 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj
, view
));
4425 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
4427 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4428 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4429 struct i915_vma
*ggtt_vma
= i915_gem_obj_to_ggtt(obj
);
4431 WARN_ON(!ggtt_vma
||
4432 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
>
4433 ggtt_vma
->pin_count
);
4434 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
4441 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
4443 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4444 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4445 WARN_ON(dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
<= 0);
4446 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
4451 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4452 struct drm_file
*file
)
4454 struct drm_i915_gem_busy
*args
= data
;
4455 struct drm_i915_gem_object
*obj
;
4458 ret
= i915_mutex_lock_interruptible(dev
);
4462 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4463 if (&obj
->base
== NULL
) {
4468 /* Count all active objects as busy, even if they are currently not used
4469 * by the gpu. Users of this interface expect objects to eventually
4470 * become non-busy without any further actions, therefore emit any
4471 * necessary flushes here.
4473 ret
= i915_gem_object_flush_active(obj
);
4477 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
4478 args
->busy
= obj
->active
<< 16;
4479 if (obj
->last_write_req
)
4480 args
->busy
|= obj
->last_write_req
->ring
->id
;
4483 drm_gem_object_unreference(&obj
->base
);
4485 mutex_unlock(&dev
->struct_mutex
);
4490 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4491 struct drm_file
*file_priv
)
4493 return i915_gem_ring_throttle(dev
, file_priv
);
4497 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4498 struct drm_file
*file_priv
)
4500 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4501 struct drm_i915_gem_madvise
*args
= data
;
4502 struct drm_i915_gem_object
*obj
;
4505 switch (args
->madv
) {
4506 case I915_MADV_DONTNEED
:
4507 case I915_MADV_WILLNEED
:
4513 ret
= i915_mutex_lock_interruptible(dev
);
4517 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
4518 if (&obj
->base
== NULL
) {
4523 if (i915_gem_obj_is_pinned(obj
)) {
4529 obj
->tiling_mode
!= I915_TILING_NONE
&&
4530 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
4531 if (obj
->madv
== I915_MADV_WILLNEED
)
4532 i915_gem_object_unpin_pages(obj
);
4533 if (args
->madv
== I915_MADV_WILLNEED
)
4534 i915_gem_object_pin_pages(obj
);
4537 if (obj
->madv
!= __I915_MADV_PURGED
)
4538 obj
->madv
= args
->madv
;
4540 /* if the object is no longer attached, discard its backing storage */
4541 if (obj
->madv
== I915_MADV_DONTNEED
&& obj
->pages
== NULL
)
4542 i915_gem_object_truncate(obj
);
4544 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4547 drm_gem_object_unreference(&obj
->base
);
4549 mutex_unlock(&dev
->struct_mutex
);
4553 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4554 const struct drm_i915_gem_object_ops
*ops
)
4558 INIT_LIST_HEAD(&obj
->global_list
);
4559 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4560 INIT_LIST_HEAD(&obj
->ring_list
[i
]);
4561 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4562 INIT_LIST_HEAD(&obj
->vma_list
);
4563 INIT_LIST_HEAD(&obj
->batch_pool_link
);
4567 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4568 obj
->madv
= I915_MADV_WILLNEED
;
4570 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4573 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4574 .get_pages
= i915_gem_object_get_pages_gtt
,
4575 .put_pages
= i915_gem_object_put_pages_gtt
,
4578 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
4581 struct drm_i915_gem_object
*obj
;
4582 struct address_space
*mapping
;
4585 obj
= i915_gem_object_alloc(dev
);
4589 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4590 i915_gem_object_free(obj
);
4594 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4595 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4596 /* 965gm cannot relocate objects above 4GiB. */
4597 mask
&= ~__GFP_HIGHMEM
;
4598 mask
|= __GFP_DMA32
;
4601 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4602 mapping_set_gfp_mask(mapping
, mask
);
4604 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4606 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4607 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4610 /* On some devices, we can have the GPU use the LLC (the CPU
4611 * cache) for about a 10% performance improvement
4612 * compared to uncached. Graphics requests other than
4613 * display scanout are coherent with the CPU in
4614 * accessing this cache. This means in this mode we
4615 * don't need to clflush on the CPU side, and on the
4616 * GPU side we only need to flush internal caches to
4617 * get data visible to the CPU.
4619 * However, we maintain the display planes as UC, and so
4620 * need to rebind when first used as such.
4622 obj
->cache_level
= I915_CACHE_LLC
;
4624 obj
->cache_level
= I915_CACHE_NONE
;
4626 trace_i915_gem_object_create(obj
);
4631 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4633 /* If we are the last user of the backing storage (be it shmemfs
4634 * pages or stolen etc), we know that the pages are going to be
4635 * immediately released. In this case, we can then skip copying
4636 * back the contents from the GPU.
4639 if (obj
->madv
!= I915_MADV_WILLNEED
)
4642 if (obj
->base
.filp
== NULL
)
4645 /* At first glance, this looks racy, but then again so would be
4646 * userspace racing mmap against close. However, the first external
4647 * reference to the filp can only be obtained through the
4648 * i915_gem_mmap_ioctl() which safeguards us against the user
4649 * acquiring such a reference whilst we are in the middle of
4650 * freeing the object.
4652 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4655 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4657 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4658 struct drm_device
*dev
= obj
->base
.dev
;
4659 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4660 struct i915_vma
*vma
, *next
;
4662 intel_runtime_pm_get(dev_priv
);
4664 trace_i915_gem_object_destroy(obj
);
4666 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4670 ret
= i915_vma_unbind(vma
);
4671 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4672 bool was_interruptible
;
4674 was_interruptible
= dev_priv
->mm
.interruptible
;
4675 dev_priv
->mm
.interruptible
= false;
4677 WARN_ON(i915_vma_unbind(vma
));
4679 dev_priv
->mm
.interruptible
= was_interruptible
;
4683 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4684 * before progressing. */
4686 i915_gem_object_unpin_pages(obj
);
4688 WARN_ON(obj
->frontbuffer_bits
);
4690 if (obj
->pages
&& obj
->madv
== I915_MADV_WILLNEED
&&
4691 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
&&
4692 obj
->tiling_mode
!= I915_TILING_NONE
)
4693 i915_gem_object_unpin_pages(obj
);
4695 if (WARN_ON(obj
->pages_pin_count
))
4696 obj
->pages_pin_count
= 0;
4697 if (discard_backing_storage(obj
))
4698 obj
->madv
= I915_MADV_DONTNEED
;
4699 i915_gem_object_put_pages(obj
);
4700 i915_gem_object_free_mmap_offset(obj
);
4704 if (obj
->base
.import_attach
)
4705 drm_prime_gem_destroy(&obj
->base
, NULL
);
4707 if (obj
->ops
->release
)
4708 obj
->ops
->release(obj
);
4710 drm_gem_object_release(&obj
->base
);
4711 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4714 i915_gem_object_free(obj
);
4716 intel_runtime_pm_put(dev_priv
);
4719 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4720 struct i915_address_space
*vm
)
4722 struct i915_vma
*vma
;
4723 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
4724 if (i915_is_ggtt(vma
->vm
) &&
4725 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
4733 struct i915_vma
*i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
4734 const struct i915_ggtt_view
*view
)
4736 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
4737 struct i915_vma
*vma
;
4739 if (WARN_ONCE(!view
, "no view specified"))
4740 return ERR_PTR(-EINVAL
);
4742 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4743 if (vma
->vm
== ggtt
&&
4744 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
4749 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4751 struct i915_address_space
*vm
= NULL
;
4752 WARN_ON(vma
->node
.allocated
);
4754 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4755 if (!list_empty(&vma
->exec_list
))
4760 if (!i915_is_ggtt(vm
))
4761 i915_ppgtt_put(i915_vm_to_ppgtt(vm
));
4763 list_del(&vma
->vma_link
);
4765 kmem_cache_free(to_i915(vma
->obj
->base
.dev
)->vmas
, vma
);
4769 i915_gem_stop_ringbuffers(struct drm_device
*dev
)
4771 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4772 struct intel_engine_cs
*ring
;
4775 for_each_ring(ring
, dev_priv
, i
)
4776 dev_priv
->gt
.stop_ring(ring
);
4780 i915_gem_suspend(struct drm_device
*dev
)
4782 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4785 mutex_lock(&dev
->struct_mutex
);
4786 ret
= i915_gpu_idle(dev
);
4790 i915_gem_retire_requests(dev
);
4792 i915_gem_stop_ringbuffers(dev
);
4793 mutex_unlock(&dev
->struct_mutex
);
4795 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
4796 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4797 flush_delayed_work(&dev_priv
->mm
.idle_work
);
4799 /* Assert that we sucessfully flushed all the work and
4800 * reset the GPU back to its idle, low power state.
4802 WARN_ON(dev_priv
->mm
.busy
);
4807 mutex_unlock(&dev
->struct_mutex
);
4811 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
)
4813 struct drm_device
*dev
= ring
->dev
;
4814 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4815 u32 reg_base
= GEN7_L3LOG_BASE
+ (slice
* 0x200);
4816 u32
*remap_info
= dev_priv
->l3_parity
.remap_info
[slice
];
4819 if (!HAS_L3_DPF(dev
) || !remap_info
)
4822 ret
= intel_ring_begin(ring
, GEN7_L3LOG_SIZE
/ 4 * 3);
4827 * Note: We do not worry about the concurrent register cacheline hang
4828 * here because no other code should access these registers other than
4829 * at initialization time.
4831 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
4832 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
4833 intel_ring_emit(ring
, reg_base
+ i
);
4834 intel_ring_emit(ring
, remap_info
[i
/4]);
4837 intel_ring_advance(ring
);
4842 void i915_gem_init_swizzling(struct drm_device
*dev
)
4844 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4846 if (INTEL_INFO(dev
)->gen
< 5 ||
4847 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4850 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4851 DISP_TILE_SURFACE_SWIZZLING
);
4856 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4858 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4859 else if (IS_GEN7(dev
))
4860 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4861 else if (IS_GEN8(dev
))
4862 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4868 intel_enable_blt(struct drm_device
*dev
)
4873 /* The blitter was dysfunctional on early prototypes */
4874 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
4875 DRM_INFO("BLT not supported on this pre-production hardware;"
4876 " graphics performance will be degraded.\n");
4883 static void init_unused_ring(struct drm_device
*dev
, u32 base
)
4885 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4887 I915_WRITE(RING_CTL(base
), 0);
4888 I915_WRITE(RING_HEAD(base
), 0);
4889 I915_WRITE(RING_TAIL(base
), 0);
4890 I915_WRITE(RING_START(base
), 0);
4893 static void init_unused_rings(struct drm_device
*dev
)
4896 init_unused_ring(dev
, PRB1_BASE
);
4897 init_unused_ring(dev
, SRB0_BASE
);
4898 init_unused_ring(dev
, SRB1_BASE
);
4899 init_unused_ring(dev
, SRB2_BASE
);
4900 init_unused_ring(dev
, SRB3_BASE
);
4901 } else if (IS_GEN2(dev
)) {
4902 init_unused_ring(dev
, SRB0_BASE
);
4903 init_unused_ring(dev
, SRB1_BASE
);
4904 } else if (IS_GEN3(dev
)) {
4905 init_unused_ring(dev
, PRB1_BASE
);
4906 init_unused_ring(dev
, PRB2_BASE
);
4910 int i915_gem_init_rings(struct drm_device
*dev
)
4912 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4915 ret
= intel_init_render_ring_buffer(dev
);
4920 ret
= intel_init_bsd_ring_buffer(dev
);
4922 goto cleanup_render_ring
;
4925 if (intel_enable_blt(dev
)) {
4926 ret
= intel_init_blt_ring_buffer(dev
);
4928 goto cleanup_bsd_ring
;
4931 if (HAS_VEBOX(dev
)) {
4932 ret
= intel_init_vebox_ring_buffer(dev
);
4934 goto cleanup_blt_ring
;
4937 if (HAS_BSD2(dev
)) {
4938 ret
= intel_init_bsd2_ring_buffer(dev
);
4940 goto cleanup_vebox_ring
;
4943 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
4945 goto cleanup_bsd2_ring
;
4950 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS2
]);
4952 intel_cleanup_ring_buffer(&dev_priv
->ring
[VECS
]);
4954 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
4956 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
4957 cleanup_render_ring
:
4958 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
4964 i915_gem_init_hw(struct drm_device
*dev
)
4966 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4967 struct intel_engine_cs
*ring
;
4970 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
4973 /* Double layer security blanket, see i915_gem_init() */
4974 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4976 if (dev_priv
->ellc_size
)
4977 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4979 if (IS_HASWELL(dev
))
4980 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
4981 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
4983 if (HAS_PCH_NOP(dev
)) {
4984 if (IS_IVYBRIDGE(dev
)) {
4985 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4986 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4987 I915_WRITE(GEN7_MSG_CTL
, temp
);
4988 } else if (INTEL_INFO(dev
)->gen
>= 7) {
4989 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
4990 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
4991 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
4995 i915_gem_init_swizzling(dev
);
4998 * At least 830 can leave some of the unused rings
4999 * "active" (ie. head != tail) after resume which
5000 * will prevent c3 entry. Makes sure all unused rings
5003 init_unused_rings(dev
);
5005 for_each_ring(ring
, dev_priv
, i
) {
5006 ret
= ring
->init_hw(ring
);
5011 for (i
= 0; i
< NUM_L3_SLICES(dev
); i
++)
5012 i915_gem_l3_remap(&dev_priv
->ring
[RCS
], i
);
5014 ret
= i915_ppgtt_init_hw(dev
);
5015 if (ret
&& ret
!= -EIO
) {
5016 DRM_ERROR("PPGTT enable failed %d\n", ret
);
5017 i915_gem_cleanup_ringbuffer(dev
);
5020 ret
= i915_gem_context_enable(dev_priv
);
5021 if (ret
&& ret
!= -EIO
) {
5022 DRM_ERROR("Context enable failed %d\n", ret
);
5023 i915_gem_cleanup_ringbuffer(dev
);
5029 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5033 int i915_gem_init(struct drm_device
*dev
)
5035 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5038 i915
.enable_execlists
= intel_sanitize_enable_execlists(dev
,
5039 i915
.enable_execlists
);
5041 mutex_lock(&dev
->struct_mutex
);
5043 if (IS_VALLEYVIEW(dev
)) {
5044 /* VLVA0 (potential hack), BIOS isn't actually waking us */
5045 I915_WRITE(VLV_GTLC_WAKE_CTRL
, VLV_GTLC_ALLOWWAKEREQ
);
5046 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS
) &
5047 VLV_GTLC_ALLOWWAKEACK
), 10))
5048 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
5051 if (!i915
.enable_execlists
) {
5052 dev_priv
->gt
.execbuf_submit
= i915_gem_ringbuffer_submission
;
5053 dev_priv
->gt
.init_rings
= i915_gem_init_rings
;
5054 dev_priv
->gt
.cleanup_ring
= intel_cleanup_ring_buffer
;
5055 dev_priv
->gt
.stop_ring
= intel_stop_ring_buffer
;
5057 dev_priv
->gt
.execbuf_submit
= intel_execlists_submission
;
5058 dev_priv
->gt
.init_rings
= intel_logical_rings_init
;
5059 dev_priv
->gt
.cleanup_ring
= intel_logical_ring_cleanup
;
5060 dev_priv
->gt
.stop_ring
= intel_logical_ring_stop
;
5063 /* This is just a security blanket to placate dragons.
5064 * On some systems, we very sporadically observe that the first TLBs
5065 * used by the CS may be stale, despite us poking the TLB reset. If
5066 * we hold the forcewake during initialisation these problems
5067 * just magically go away.
5069 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5071 ret
= i915_gem_init_userptr(dev
);
5075 i915_gem_init_global_gtt(dev
);
5077 ret
= i915_gem_context_init(dev
);
5081 ret
= dev_priv
->gt
.init_rings(dev
);
5085 ret
= i915_gem_init_hw(dev
);
5087 /* Allow ring initialisation to fail by marking the GPU as
5088 * wedged. But we only want to do this where the GPU is angry,
5089 * for all other failure, such as an allocation failure, bail.
5091 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
5092 atomic_set_mask(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
5097 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5098 mutex_unlock(&dev
->struct_mutex
);
5104 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
5106 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5107 struct intel_engine_cs
*ring
;
5110 for_each_ring(ring
, dev_priv
, i
)
5111 dev_priv
->gt
.cleanup_ring(ring
);
5115 init_ring_lists(struct intel_engine_cs
*ring
)
5117 INIT_LIST_HEAD(&ring
->active_list
);
5118 INIT_LIST_HEAD(&ring
->request_list
);
5121 void i915_init_vm(struct drm_i915_private
*dev_priv
,
5122 struct i915_address_space
*vm
)
5124 if (!i915_is_ggtt(vm
))
5125 drm_mm_init(&vm
->mm
, vm
->start
, vm
->total
);
5126 vm
->dev
= dev_priv
->dev
;
5127 INIT_LIST_HEAD(&vm
->active_list
);
5128 INIT_LIST_HEAD(&vm
->inactive_list
);
5129 INIT_LIST_HEAD(&vm
->global_link
);
5130 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
5134 i915_gem_load(struct drm_device
*dev
)
5136 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5140 kmem_cache_create("i915_gem_object",
5141 sizeof(struct drm_i915_gem_object
), 0,
5145 kmem_cache_create("i915_gem_vma",
5146 sizeof(struct i915_vma
), 0,
5149 dev_priv
->requests
=
5150 kmem_cache_create("i915_gem_request",
5151 sizeof(struct drm_i915_gem_request
), 0,
5155 INIT_LIST_HEAD(&dev_priv
->vm_list
);
5156 i915_init_vm(dev_priv
, &dev_priv
->gtt
.base
);
5158 INIT_LIST_HEAD(&dev_priv
->context_list
);
5159 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
5160 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
5161 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5162 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
5163 init_ring_lists(&dev_priv
->ring
[i
]);
5164 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
5165 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
5166 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
5167 i915_gem_retire_work_handler
);
5168 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
5169 i915_gem_idle_work_handler
);
5170 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
5172 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
5174 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
))
5175 dev_priv
->num_fence_regs
= 32;
5176 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
5177 dev_priv
->num_fence_regs
= 16;
5179 dev_priv
->num_fence_regs
= 8;
5181 if (intel_vgpu_active(dev
))
5182 dev_priv
->num_fence_regs
=
5183 I915_READ(vgtif_reg(avail_rs
.fence_num
));
5185 /* Initialize fence registers to zero */
5186 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5187 i915_gem_restore_fences(dev
);
5189 i915_gem_detect_bit_6_swizzle(dev
);
5190 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
5192 dev_priv
->mm
.interruptible
= true;
5194 i915_gem_shrinker_init(dev_priv
);
5196 mutex_init(&dev_priv
->fb_tracking
.lock
);
5199 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5201 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5203 /* Clean up our request list when the client is going away, so that
5204 * later retire_requests won't dereference our soon-to-be-gone
5207 spin_lock(&file_priv
->mm
.lock
);
5208 while (!list_empty(&file_priv
->mm
.request_list
)) {
5209 struct drm_i915_gem_request
*request
;
5211 request
= list_first_entry(&file_priv
->mm
.request_list
,
5212 struct drm_i915_gem_request
,
5214 list_del(&request
->client_list
);
5215 request
->file_priv
= NULL
;
5217 spin_unlock(&file_priv
->mm
.lock
);
5219 if (!list_empty(&file_priv
->rps_boost
)) {
5220 mutex_lock(&to_i915(dev
)->rps
.hw_lock
);
5221 list_del(&file_priv
->rps_boost
);
5222 mutex_unlock(&to_i915(dev
)->rps
.hw_lock
);
5226 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
5228 struct drm_i915_file_private
*file_priv
;
5231 DRM_DEBUG_DRIVER("\n");
5233 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
5237 file
->driver_priv
= file_priv
;
5238 file_priv
->dev_priv
= dev
->dev_private
;
5239 file_priv
->file
= file
;
5240 INIT_LIST_HEAD(&file_priv
->rps_boost
);
5242 spin_lock_init(&file_priv
->mm
.lock
);
5243 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
5245 ret
= i915_gem_context_open(dev
, file
);
5253 * i915_gem_track_fb - update frontbuffer tracking
5254 * old: current GEM buffer for the frontbuffer slots
5255 * new: new GEM buffer for the frontbuffer slots
5256 * frontbuffer_bits: bitmask of frontbuffer slots
5258 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5259 * from @old and setting them in @new. Both @old and @new can be NULL.
5261 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
5262 struct drm_i915_gem_object
*new,
5263 unsigned frontbuffer_bits
)
5266 WARN_ON(!mutex_is_locked(&old
->base
.dev
->struct_mutex
));
5267 WARN_ON(!(old
->frontbuffer_bits
& frontbuffer_bits
));
5268 old
->frontbuffer_bits
&= ~frontbuffer_bits
;
5272 WARN_ON(!mutex_is_locked(&new->base
.dev
->struct_mutex
));
5273 WARN_ON(new->frontbuffer_bits
& frontbuffer_bits
);
5274 new->frontbuffer_bits
|= frontbuffer_bits
;
5278 /* All the new VM stuff */
5280 i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
5281 struct i915_address_space
*vm
)
5283 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5284 struct i915_vma
*vma
;
5286 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5288 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5289 if (i915_is_ggtt(vma
->vm
) &&
5290 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5293 return vma
->node
.start
;
5296 WARN(1, "%s vma for this object not found.\n",
5297 i915_is_ggtt(vm
) ? "global" : "ppgtt");
5302 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
5303 const struct i915_ggtt_view
*view
)
5305 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5306 struct i915_vma
*vma
;
5308 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5309 if (vma
->vm
== ggtt
&&
5310 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
5311 return vma
->node
.start
;
5313 WARN(1, "global vma for this object not found. (view=%u)\n", view
->type
);
5317 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
5318 struct i915_address_space
*vm
)
5320 struct i915_vma
*vma
;
5322 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5323 if (i915_is_ggtt(vma
->vm
) &&
5324 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5326 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
5333 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
5334 const struct i915_ggtt_view
*view
)
5336 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5337 struct i915_vma
*vma
;
5339 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5340 if (vma
->vm
== ggtt
&&
5341 i915_ggtt_view_equal(&vma
->ggtt_view
, view
) &&
5342 drm_mm_node_allocated(&vma
->node
))
5348 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
5350 struct i915_vma
*vma
;
5352 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5353 if (drm_mm_node_allocated(&vma
->node
))
5359 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
5360 struct i915_address_space
*vm
)
5362 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5363 struct i915_vma
*vma
;
5365 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5367 BUG_ON(list_empty(&o
->vma_list
));
5369 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5370 if (i915_is_ggtt(vma
->vm
) &&
5371 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5374 return vma
->node
.size
;
5379 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
)
5381 struct i915_vma
*vma
;
5382 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
5383 if (vma
->pin_count
> 0)