2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
38 #include <linux/dma-buf.h>
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
,
43 static __must_check
int
44 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
46 static __must_check
int
47 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
48 struct i915_address_space
*vm
,
50 bool map_and_fenceable
,
52 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
53 struct drm_i915_gem_object
*obj
,
54 struct drm_i915_gem_pwrite
*args
,
55 struct drm_file
*file
);
57 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
58 struct drm_i915_gem_object
*obj
);
59 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
60 struct drm_i915_fence_reg
*fence
,
63 static unsigned long i915_gem_inactive_count(struct shrinker
*shrinker
,
64 struct shrink_control
*sc
);
65 static unsigned long i915_gem_inactive_scan(struct shrinker
*shrinker
,
66 struct shrink_control
*sc
);
67 static unsigned long i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
);
68 static unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
69 static void i915_gem_object_truncate(struct drm_i915_gem_object
*obj
);
71 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
72 enum i915_cache_level level
)
74 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
77 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
79 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
82 return obj
->pin_display
;
85 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
88 i915_gem_release_mmap(obj
);
90 /* As we do not have an associated fence register, we will force
91 * a tiling change if we ever need to acquire one.
93 obj
->fence_dirty
= false;
94 obj
->fence_reg
= I915_FENCE_REG_NONE
;
97 /* some bookkeeping */
98 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
101 spin_lock(&dev_priv
->mm
.object_stat_lock
);
102 dev_priv
->mm
.object_count
++;
103 dev_priv
->mm
.object_memory
+= size
;
104 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
107 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
110 spin_lock(&dev_priv
->mm
.object_stat_lock
);
111 dev_priv
->mm
.object_count
--;
112 dev_priv
->mm
.object_memory
-= size
;
113 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
117 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
121 #define EXIT_COND (!i915_reset_in_progress(error) || \
122 i915_terminally_wedged(error))
127 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
128 * userspace. If it takes that long something really bad is going on and
129 * we should simply try to bail out and fail as gracefully as possible.
131 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
135 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
137 } else if (ret
< 0) {
145 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
147 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
150 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
154 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
158 WARN_ON(i915_verify_lists(dev
));
163 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
165 return i915_gem_obj_bound_any(obj
) && !obj
->active
;
169 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
170 struct drm_file
*file
)
172 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
173 struct drm_i915_gem_init
*args
= data
;
175 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
178 if (args
->gtt_start
>= args
->gtt_end
||
179 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
182 /* GEM with user mode setting was never supported on ilk and later. */
183 if (INTEL_INFO(dev
)->gen
>= 5)
186 mutex_lock(&dev
->struct_mutex
);
187 i915_gem_setup_global_gtt(dev
, args
->gtt_start
, args
->gtt_end
,
189 dev_priv
->gtt
.mappable_end
= args
->gtt_end
;
190 mutex_unlock(&dev
->struct_mutex
);
196 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
197 struct drm_file
*file
)
199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
200 struct drm_i915_gem_get_aperture
*args
= data
;
201 struct drm_i915_gem_object
*obj
;
205 mutex_lock(&dev
->struct_mutex
);
206 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
207 if (i915_gem_obj_is_pinned(obj
))
208 pinned
+= i915_gem_obj_ggtt_size(obj
);
209 mutex_unlock(&dev
->struct_mutex
);
211 args
->aper_size
= dev_priv
->gtt
.base
.total
;
212 args
->aper_available_size
= args
->aper_size
- pinned
;
217 void *i915_gem_object_alloc(struct drm_device
*dev
)
219 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
220 return kmem_cache_zalloc(dev_priv
->slab
, GFP_KERNEL
);
223 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
225 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
226 kmem_cache_free(dev_priv
->slab
, obj
);
230 i915_gem_create(struct drm_file
*file
,
231 struct drm_device
*dev
,
235 struct drm_i915_gem_object
*obj
;
239 size
= roundup(size
, PAGE_SIZE
);
243 /* Allocate the new object */
244 obj
= i915_gem_alloc_object(dev
, size
);
248 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
249 /* drop reference from allocate - handle holds it now */
250 drm_gem_object_unreference_unlocked(&obj
->base
);
259 i915_gem_dumb_create(struct drm_file
*file
,
260 struct drm_device
*dev
,
261 struct drm_mode_create_dumb
*args
)
263 /* have to work out size/pitch and return them */
264 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
265 args
->size
= args
->pitch
* args
->height
;
266 return i915_gem_create(file
, dev
,
267 args
->size
, &args
->handle
);
271 * Creates a new mm object and returns a handle to it.
274 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
275 struct drm_file
*file
)
277 struct drm_i915_gem_create
*args
= data
;
279 return i915_gem_create(file
, dev
,
280 args
->size
, &args
->handle
);
284 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
285 const char *gpu_vaddr
, int gpu_offset
,
288 int ret
, cpu_offset
= 0;
291 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
292 int this_length
= min(cacheline_end
- gpu_offset
, length
);
293 int swizzled_gpu_offset
= gpu_offset
^ 64;
295 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
296 gpu_vaddr
+ swizzled_gpu_offset
,
301 cpu_offset
+= this_length
;
302 gpu_offset
+= this_length
;
303 length
-= this_length
;
310 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
311 const char __user
*cpu_vaddr
,
314 int ret
, cpu_offset
= 0;
317 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
318 int this_length
= min(cacheline_end
- gpu_offset
, length
);
319 int swizzled_gpu_offset
= gpu_offset
^ 64;
321 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
322 cpu_vaddr
+ cpu_offset
,
327 cpu_offset
+= this_length
;
328 gpu_offset
+= this_length
;
329 length
-= this_length
;
335 /* Per-page copy function for the shmem pread fastpath.
336 * Flushes invalid cachelines before reading the target if
337 * needs_clflush is set. */
339 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
340 char __user
*user_data
,
341 bool page_do_bit17_swizzling
, bool needs_clflush
)
346 if (unlikely(page_do_bit17_swizzling
))
349 vaddr
= kmap_atomic(page
);
351 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
353 ret
= __copy_to_user_inatomic(user_data
,
354 vaddr
+ shmem_page_offset
,
356 kunmap_atomic(vaddr
);
358 return ret
? -EFAULT
: 0;
362 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
365 if (unlikely(swizzled
)) {
366 unsigned long start
= (unsigned long) addr
;
367 unsigned long end
= (unsigned long) addr
+ length
;
369 /* For swizzling simply ensure that we always flush both
370 * channels. Lame, but simple and it works. Swizzled
371 * pwrite/pread is far from a hotpath - current userspace
372 * doesn't use it at all. */
373 start
= round_down(start
, 128);
374 end
= round_up(end
, 128);
376 drm_clflush_virt_range((void *)start
, end
- start
);
378 drm_clflush_virt_range(addr
, length
);
383 /* Only difference to the fast-path function is that this can handle bit17
384 * and uses non-atomic copy and kmap functions. */
386 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
387 char __user
*user_data
,
388 bool page_do_bit17_swizzling
, bool needs_clflush
)
395 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
397 page_do_bit17_swizzling
);
399 if (page_do_bit17_swizzling
)
400 ret
= __copy_to_user_swizzled(user_data
,
401 vaddr
, shmem_page_offset
,
404 ret
= __copy_to_user(user_data
,
405 vaddr
+ shmem_page_offset
,
409 return ret
? - EFAULT
: 0;
413 i915_gem_shmem_pread(struct drm_device
*dev
,
414 struct drm_i915_gem_object
*obj
,
415 struct drm_i915_gem_pread
*args
,
416 struct drm_file
*file
)
418 char __user
*user_data
;
421 int shmem_page_offset
, page_length
, ret
= 0;
422 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
424 int needs_clflush
= 0;
425 struct sg_page_iter sg_iter
;
427 user_data
= to_user_ptr(args
->data_ptr
);
430 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
432 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
433 /* If we're not in the cpu read domain, set ourself into the gtt
434 * read domain and manually flush cachelines (if required). This
435 * optimizes for the case when the gpu will dirty the data
436 * anyway again before the next pread happens. */
437 needs_clflush
= !cpu_cache_is_coherent(dev
, obj
->cache_level
);
438 ret
= i915_gem_object_wait_rendering(obj
, true);
443 ret
= i915_gem_object_get_pages(obj
);
447 i915_gem_object_pin_pages(obj
);
449 offset
= args
->offset
;
451 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
452 offset
>> PAGE_SHIFT
) {
453 struct page
*page
= sg_page_iter_page(&sg_iter
);
458 /* Operation in this page
460 * shmem_page_offset = offset within page in shmem file
461 * page_length = bytes to copy for this page
463 shmem_page_offset
= offset_in_page(offset
);
464 page_length
= remain
;
465 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
466 page_length
= PAGE_SIZE
- shmem_page_offset
;
468 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
469 (page_to_phys(page
) & (1 << 17)) != 0;
471 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
472 user_data
, page_do_bit17_swizzling
,
477 mutex_unlock(&dev
->struct_mutex
);
479 if (likely(!i915_prefault_disable
) && !prefaulted
) {
480 ret
= fault_in_multipages_writeable(user_data
, remain
);
481 /* Userspace is tricking us, but we've already clobbered
482 * its pages with the prefault and promised to write the
483 * data up to the first fault. Hence ignore any errors
484 * and just continue. */
489 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
490 user_data
, page_do_bit17_swizzling
,
493 mutex_lock(&dev
->struct_mutex
);
496 mark_page_accessed(page
);
501 remain
-= page_length
;
502 user_data
+= page_length
;
503 offset
+= page_length
;
507 i915_gem_object_unpin_pages(obj
);
513 * Reads data from the object referenced by handle.
515 * On error, the contents of *data are undefined.
518 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
519 struct drm_file
*file
)
521 struct drm_i915_gem_pread
*args
= data
;
522 struct drm_i915_gem_object
*obj
;
528 if (!access_ok(VERIFY_WRITE
,
529 to_user_ptr(args
->data_ptr
),
533 ret
= i915_mutex_lock_interruptible(dev
);
537 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
538 if (&obj
->base
== NULL
) {
543 /* Bounds check source. */
544 if (args
->offset
> obj
->base
.size
||
545 args
->size
> obj
->base
.size
- args
->offset
) {
550 /* prime objects have no backing filp to GEM pread/pwrite
553 if (!obj
->base
.filp
) {
558 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
560 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
563 drm_gem_object_unreference(&obj
->base
);
565 mutex_unlock(&dev
->struct_mutex
);
569 /* This is the fast write path which cannot handle
570 * page faults in the source data
574 fast_user_write(struct io_mapping
*mapping
,
575 loff_t page_base
, int page_offset
,
576 char __user
*user_data
,
579 void __iomem
*vaddr_atomic
;
581 unsigned long unwritten
;
583 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
584 /* We can use the cpu mem copy function because this is X86. */
585 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
586 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
588 io_mapping_unmap_atomic(vaddr_atomic
);
593 * This is the fast pwrite path, where we copy the data directly from the
594 * user into the GTT, uncached.
597 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
598 struct drm_i915_gem_object
*obj
,
599 struct drm_i915_gem_pwrite
*args
,
600 struct drm_file
*file
)
602 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
604 loff_t offset
, page_base
;
605 char __user
*user_data
;
606 int page_offset
, page_length
, ret
;
608 ret
= i915_gem_obj_ggtt_pin(obj
, 0, true, true);
612 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
616 ret
= i915_gem_object_put_fence(obj
);
620 user_data
= to_user_ptr(args
->data_ptr
);
623 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
626 /* Operation in this page
628 * page_base = page offset within aperture
629 * page_offset = offset within page
630 * page_length = bytes to copy for this page
632 page_base
= offset
& PAGE_MASK
;
633 page_offset
= offset_in_page(offset
);
634 page_length
= remain
;
635 if ((page_offset
+ remain
) > PAGE_SIZE
)
636 page_length
= PAGE_SIZE
- page_offset
;
638 /* If we get a fault while copying data, then (presumably) our
639 * source page isn't available. Return the error and we'll
640 * retry in the slow path.
642 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
643 page_offset
, user_data
, page_length
)) {
648 remain
-= page_length
;
649 user_data
+= page_length
;
650 offset
+= page_length
;
654 i915_gem_object_ggtt_unpin(obj
);
659 /* Per-page copy function for the shmem pwrite fastpath.
660 * Flushes invalid cachelines before writing to the target if
661 * needs_clflush_before is set and flushes out any written cachelines after
662 * writing if needs_clflush is set. */
664 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
665 char __user
*user_data
,
666 bool page_do_bit17_swizzling
,
667 bool needs_clflush_before
,
668 bool needs_clflush_after
)
673 if (unlikely(page_do_bit17_swizzling
))
676 vaddr
= kmap_atomic(page
);
677 if (needs_clflush_before
)
678 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
680 ret
= __copy_from_user_inatomic_nocache(vaddr
+ shmem_page_offset
,
683 if (needs_clflush_after
)
684 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
686 kunmap_atomic(vaddr
);
688 return ret
? -EFAULT
: 0;
691 /* Only difference to the fast-path function is that this can handle bit17
692 * and uses non-atomic copy and kmap functions. */
694 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
695 char __user
*user_data
,
696 bool page_do_bit17_swizzling
,
697 bool needs_clflush_before
,
698 bool needs_clflush_after
)
704 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
705 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
707 page_do_bit17_swizzling
);
708 if (page_do_bit17_swizzling
)
709 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
713 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
716 if (needs_clflush_after
)
717 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
719 page_do_bit17_swizzling
);
722 return ret
? -EFAULT
: 0;
726 i915_gem_shmem_pwrite(struct drm_device
*dev
,
727 struct drm_i915_gem_object
*obj
,
728 struct drm_i915_gem_pwrite
*args
,
729 struct drm_file
*file
)
733 char __user
*user_data
;
734 int shmem_page_offset
, page_length
, ret
= 0;
735 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
736 int hit_slowpath
= 0;
737 int needs_clflush_after
= 0;
738 int needs_clflush_before
= 0;
739 struct sg_page_iter sg_iter
;
741 user_data
= to_user_ptr(args
->data_ptr
);
744 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
746 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
747 /* If we're not in the cpu write domain, set ourself into the gtt
748 * write domain and manually flush cachelines (if required). This
749 * optimizes for the case when the gpu will use the data
750 * right away and we therefore have to clflush anyway. */
751 needs_clflush_after
= cpu_write_needs_clflush(obj
);
752 ret
= i915_gem_object_wait_rendering(obj
, false);
756 /* Same trick applies to invalidate partially written cachelines read
758 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
759 needs_clflush_before
=
760 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
762 ret
= i915_gem_object_get_pages(obj
);
766 i915_gem_object_pin_pages(obj
);
768 offset
= args
->offset
;
771 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
772 offset
>> PAGE_SHIFT
) {
773 struct page
*page
= sg_page_iter_page(&sg_iter
);
774 int partial_cacheline_write
;
779 /* Operation in this page
781 * shmem_page_offset = offset within page in shmem file
782 * page_length = bytes to copy for this page
784 shmem_page_offset
= offset_in_page(offset
);
786 page_length
= remain
;
787 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
788 page_length
= PAGE_SIZE
- shmem_page_offset
;
790 /* If we don't overwrite a cacheline completely we need to be
791 * careful to have up-to-date data by first clflushing. Don't
792 * overcomplicate things and flush the entire patch. */
793 partial_cacheline_write
= needs_clflush_before
&&
794 ((shmem_page_offset
| page_length
)
795 & (boot_cpu_data
.x86_clflush_size
- 1));
797 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
798 (page_to_phys(page
) & (1 << 17)) != 0;
800 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
801 user_data
, page_do_bit17_swizzling
,
802 partial_cacheline_write
,
803 needs_clflush_after
);
808 mutex_unlock(&dev
->struct_mutex
);
809 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
810 user_data
, page_do_bit17_swizzling
,
811 partial_cacheline_write
,
812 needs_clflush_after
);
814 mutex_lock(&dev
->struct_mutex
);
817 set_page_dirty(page
);
818 mark_page_accessed(page
);
823 remain
-= page_length
;
824 user_data
+= page_length
;
825 offset
+= page_length
;
829 i915_gem_object_unpin_pages(obj
);
833 * Fixup: Flush cpu caches in case we didn't flush the dirty
834 * cachelines in-line while writing and the object moved
835 * out of the cpu write domain while we've dropped the lock.
837 if (!needs_clflush_after
&&
838 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
839 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
840 i915_gem_chipset_flush(dev
);
844 if (needs_clflush_after
)
845 i915_gem_chipset_flush(dev
);
851 * Writes data to the object referenced by handle.
853 * On error, the contents of the buffer that were to be modified are undefined.
856 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
857 struct drm_file
*file
)
859 struct drm_i915_gem_pwrite
*args
= data
;
860 struct drm_i915_gem_object
*obj
;
866 if (!access_ok(VERIFY_READ
,
867 to_user_ptr(args
->data_ptr
),
871 if (likely(!i915_prefault_disable
)) {
872 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
878 ret
= i915_mutex_lock_interruptible(dev
);
882 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
883 if (&obj
->base
== NULL
) {
888 /* Bounds check destination. */
889 if (args
->offset
> obj
->base
.size
||
890 args
->size
> obj
->base
.size
- args
->offset
) {
895 /* prime objects have no backing filp to GEM pread/pwrite
898 if (!obj
->base
.filp
) {
903 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
906 /* We can only do the GTT pwrite on untiled buffers, as otherwise
907 * it would end up going through the fenced access, and we'll get
908 * different detiling behavior between reading and writing.
909 * pread/pwrite currently are reading and writing from the CPU
910 * perspective, requiring manual detiling by the client.
913 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
917 if (obj
->tiling_mode
== I915_TILING_NONE
&&
918 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
919 cpu_write_needs_clflush(obj
)) {
920 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
921 /* Note that the gtt paths might fail with non-page-backed user
922 * pointers (e.g. gtt mappings when moving data between
923 * textures). Fallback to the shmem path in that case. */
926 if (ret
== -EFAULT
|| ret
== -ENOSPC
)
927 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
930 drm_gem_object_unreference(&obj
->base
);
932 mutex_unlock(&dev
->struct_mutex
);
937 i915_gem_check_wedge(struct i915_gpu_error
*error
,
940 if (i915_reset_in_progress(error
)) {
941 /* Non-interruptible callers can't handle -EAGAIN, hence return
942 * -EIO unconditionally for these. */
946 /* Recovery complete, but the reset failed ... */
947 if (i915_terminally_wedged(error
))
957 * Compare seqno against outstanding lazy request. Emit a request if they are
961 i915_gem_check_olr(struct intel_ring_buffer
*ring
, u32 seqno
)
965 BUG_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
968 if (seqno
== ring
->outstanding_lazy_seqno
)
969 ret
= i915_add_request(ring
, NULL
);
974 static void fake_irq(unsigned long data
)
976 wake_up_process((struct task_struct
*)data
);
979 static bool missed_irq(struct drm_i915_private
*dev_priv
,
980 struct intel_ring_buffer
*ring
)
982 return test_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
985 static bool can_wait_boost(struct drm_i915_file_private
*file_priv
)
987 if (file_priv
== NULL
)
990 return !atomic_xchg(&file_priv
->rps_wait_boost
, true);
994 * __wait_seqno - wait until execution of seqno has finished
995 * @ring: the ring expected to report seqno
997 * @reset_counter: reset sequence associated with the given seqno
998 * @interruptible: do an interruptible wait (normally yes)
999 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1001 * Note: It is of utmost importance that the passed in seqno and reset_counter
1002 * values have been read by the caller in an smp safe manner. Where read-side
1003 * locks are involved, it is sufficient to read the reset_counter before
1004 * unlocking the lock that protects the seqno. For lockless tricks, the
1005 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1008 * Returns 0 if the seqno was found within the alloted time. Else returns the
1009 * errno with remaining time filled in timeout argument.
1011 static int __wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
,
1012 unsigned reset_counter
,
1014 struct timespec
*timeout
,
1015 struct drm_i915_file_private
*file_priv
)
1017 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1018 struct timespec before
, now
;
1020 long timeout_jiffies
;
1023 WARN(dev_priv
->pc8
.irqs_disabled
, "IRQs disabled\n");
1025 if (i915_seqno_passed(ring
->get_seqno(ring
, true), seqno
))
1028 timeout_jiffies
= timeout
? timespec_to_jiffies_timeout(timeout
) : 1;
1030 if (dev_priv
->info
->gen
>= 6 && can_wait_boost(file_priv
)) {
1031 gen6_rps_boost(dev_priv
);
1033 mod_delayed_work(dev_priv
->wq
,
1034 &file_priv
->mm
.idle_work
,
1035 msecs_to_jiffies(100));
1038 if (!(dev_priv
->gpu_error
.test_irq_rings
& intel_ring_flag(ring
)) &&
1039 WARN_ON(!ring
->irq_get(ring
)))
1042 /* Record current time in case interrupted by signal, or wedged */
1043 trace_i915_gem_request_wait_begin(ring
, seqno
);
1044 getrawmonotonic(&before
);
1046 struct timer_list timer
;
1047 unsigned long expire
;
1049 prepare_to_wait(&ring
->irq_queue
, &wait
,
1050 interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
);
1052 /* We need to check whether any gpu reset happened in between
1053 * the caller grabbing the seqno and now ... */
1054 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
)) {
1055 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1056 * is truely gone. */
1057 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1063 if (i915_seqno_passed(ring
->get_seqno(ring
, false), seqno
)) {
1068 if (interruptible
&& signal_pending(current
)) {
1073 if (timeout_jiffies
<= 0) {
1078 timer
.function
= NULL
;
1079 if (timeout
|| missed_irq(dev_priv
, ring
)) {
1080 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1081 expire
= jiffies
+ (missed_irq(dev_priv
, ring
) ? 1: timeout_jiffies
);
1082 mod_timer(&timer
, expire
);
1088 timeout_jiffies
= expire
- jiffies
;
1090 if (timer
.function
) {
1091 del_singleshot_timer_sync(&timer
);
1092 destroy_timer_on_stack(&timer
);
1095 getrawmonotonic(&now
);
1096 trace_i915_gem_request_wait_end(ring
, seqno
);
1098 ring
->irq_put(ring
);
1100 finish_wait(&ring
->irq_queue
, &wait
);
1103 struct timespec sleep_time
= timespec_sub(now
, before
);
1104 *timeout
= timespec_sub(*timeout
, sleep_time
);
1105 if (!timespec_valid(timeout
)) /* i.e. negative time remains */
1106 set_normalized_timespec(timeout
, 0, 0);
1113 * Waits for a sequence number to be signaled, and cleans up the
1114 * request and object lists appropriately for that event.
1117 i915_wait_seqno(struct intel_ring_buffer
*ring
, uint32_t seqno
)
1119 struct drm_device
*dev
= ring
->dev
;
1120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1121 bool interruptible
= dev_priv
->mm
.interruptible
;
1124 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1127 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1131 ret
= i915_gem_check_olr(ring
, seqno
);
1135 return __wait_seqno(ring
, seqno
,
1136 atomic_read(&dev_priv
->gpu_error
.reset_counter
),
1137 interruptible
, NULL
, NULL
);
1141 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object
*obj
,
1142 struct intel_ring_buffer
*ring
)
1144 i915_gem_retire_requests_ring(ring
);
1146 /* Manually manage the write flush as we may have not yet
1147 * retired the buffer.
1149 * Note that the last_write_seqno is always the earlier of
1150 * the two (read/write) seqno, so if we haved successfully waited,
1151 * we know we have passed the last write.
1153 obj
->last_write_seqno
= 0;
1154 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1160 * Ensures that all rendering to the object has completed and the object is
1161 * safe to unbind from the GTT or access from the CPU.
1163 static __must_check
int
1164 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1167 struct intel_ring_buffer
*ring
= obj
->ring
;
1171 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1175 ret
= i915_wait_seqno(ring
, seqno
);
1179 return i915_gem_object_wait_rendering__tail(obj
, ring
);
1182 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1183 * as the object state may change during this call.
1185 static __must_check
int
1186 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1187 struct drm_file
*file
,
1190 struct drm_device
*dev
= obj
->base
.dev
;
1191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1192 struct intel_ring_buffer
*ring
= obj
->ring
;
1193 unsigned reset_counter
;
1197 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1198 BUG_ON(!dev_priv
->mm
.interruptible
);
1200 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1204 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1208 ret
= i915_gem_check_olr(ring
, seqno
);
1212 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1213 mutex_unlock(&dev
->struct_mutex
);
1214 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, NULL
, file
->driver_priv
);
1215 mutex_lock(&dev
->struct_mutex
);
1219 return i915_gem_object_wait_rendering__tail(obj
, ring
);
1223 * Called when user space prepares to use an object with the CPU, either
1224 * through the mmap ioctl's mapping or a GTT mapping.
1227 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1228 struct drm_file
*file
)
1230 struct drm_i915_gem_set_domain
*args
= data
;
1231 struct drm_i915_gem_object
*obj
;
1232 uint32_t read_domains
= args
->read_domains
;
1233 uint32_t write_domain
= args
->write_domain
;
1236 /* Only handle setting domains to types used by the CPU. */
1237 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1240 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1243 /* Having something in the write domain implies it's in the read
1244 * domain, and only that read domain. Enforce that in the request.
1246 if (write_domain
!= 0 && read_domains
!= write_domain
)
1249 ret
= i915_mutex_lock_interruptible(dev
);
1253 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1254 if (&obj
->base
== NULL
) {
1259 /* Try to flush the object off the GPU without holding the lock.
1260 * We will repeat the flush holding the lock in the normal manner
1261 * to catch cases where we are gazumped.
1263 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, file
, !write_domain
);
1267 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1268 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1270 /* Silently promote "you're not bound, there was nothing to do"
1271 * to success, since the client was just asking us to
1272 * make sure everything was done.
1277 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1281 drm_gem_object_unreference(&obj
->base
);
1283 mutex_unlock(&dev
->struct_mutex
);
1288 * Called when user space has done writes to this buffer
1291 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1292 struct drm_file
*file
)
1294 struct drm_i915_gem_sw_finish
*args
= data
;
1295 struct drm_i915_gem_object
*obj
;
1298 ret
= i915_mutex_lock_interruptible(dev
);
1302 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1303 if (&obj
->base
== NULL
) {
1308 /* Pinned buffers may be scanout, so flush the cache */
1309 if (obj
->pin_display
)
1310 i915_gem_object_flush_cpu_write_domain(obj
, true);
1312 drm_gem_object_unreference(&obj
->base
);
1314 mutex_unlock(&dev
->struct_mutex
);
1319 * Maps the contents of an object, returning the address it is mapped
1322 * While the mapping holds a reference on the contents of the object, it doesn't
1323 * imply a ref on the object itself.
1326 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1327 struct drm_file
*file
)
1329 struct drm_i915_gem_mmap
*args
= data
;
1330 struct drm_gem_object
*obj
;
1333 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1337 /* prime objects have no backing filp to GEM mmap
1341 drm_gem_object_unreference_unlocked(obj
);
1345 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1346 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1348 drm_gem_object_unreference_unlocked(obj
);
1349 if (IS_ERR((void *)addr
))
1352 args
->addr_ptr
= (uint64_t) addr
;
1358 * i915_gem_fault - fault a page into the GTT
1359 * vma: VMA in question
1362 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1363 * from userspace. The fault handler takes care of binding the object to
1364 * the GTT (if needed), allocating and programming a fence register (again,
1365 * only if needed based on whether the old reg is still valid or the object
1366 * is tiled) and inserting a new PTE into the faulting process.
1368 * Note that the faulting process may involve evicting existing objects
1369 * from the GTT and/or fence registers to make room. So performance may
1370 * suffer if the GTT working set is large or there are few fence registers
1373 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1375 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1376 struct drm_device
*dev
= obj
->base
.dev
;
1377 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1378 pgoff_t page_offset
;
1381 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1383 /* We don't use vmf->pgoff since that has the fake offset */
1384 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1387 ret
= i915_mutex_lock_interruptible(dev
);
1391 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1393 /* Access to snoopable pages through the GTT is incoherent. */
1394 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1399 /* Now bind it into the GTT if needed */
1400 ret
= i915_gem_obj_ggtt_pin(obj
, 0, true, false);
1404 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1408 ret
= i915_gem_object_get_fence(obj
);
1412 obj
->fault_mappable
= true;
1414 pfn
= dev_priv
->gtt
.mappable_base
+ i915_gem_obj_ggtt_offset(obj
);
1418 /* Finally, remap it using the new GTT offset */
1419 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1421 i915_gem_object_ggtt_unpin(obj
);
1423 mutex_unlock(&dev
->struct_mutex
);
1427 /* If this -EIO is due to a gpu hang, give the reset code a
1428 * chance to clean up the mess. Otherwise return the proper
1430 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
1431 return VM_FAULT_SIGBUS
;
1434 * EAGAIN means the gpu is hung and we'll wait for the error
1435 * handler to reset everything when re-faulting in
1436 * i915_mutex_lock_interruptible.
1443 * EBUSY is ok: this just means that another thread
1444 * already did the job.
1446 return VM_FAULT_NOPAGE
;
1448 return VM_FAULT_OOM
;
1450 return VM_FAULT_SIGBUS
;
1452 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1453 return VM_FAULT_SIGBUS
;
1458 * i915_gem_release_mmap - remove physical page mappings
1459 * @obj: obj in question
1461 * Preserve the reservation of the mmapping with the DRM core code, but
1462 * relinquish ownership of the pages back to the system.
1464 * It is vital that we remove the page mapping if we have mapped a tiled
1465 * object through the GTT and then lose the fence register due to
1466 * resource pressure. Similarly if the object has been moved out of the
1467 * aperture, than pages mapped into userspace must be revoked. Removing the
1468 * mapping will then trigger a page fault on the next user access, allowing
1469 * fixup by i915_gem_fault().
1472 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1474 if (!obj
->fault_mappable
)
1477 drm_vma_node_unmap(&obj
->base
.vma_node
, obj
->base
.dev
->dev_mapping
);
1478 obj
->fault_mappable
= false;
1482 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1486 if (INTEL_INFO(dev
)->gen
>= 4 ||
1487 tiling_mode
== I915_TILING_NONE
)
1490 /* Previous chips need a power-of-two fence region when tiling */
1491 if (INTEL_INFO(dev
)->gen
== 3)
1492 gtt_size
= 1024*1024;
1494 gtt_size
= 512*1024;
1496 while (gtt_size
< size
)
1503 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1504 * @obj: object to check
1506 * Return the required GTT alignment for an object, taking into account
1507 * potential fence register mapping.
1510 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1511 int tiling_mode
, bool fenced
)
1514 * Minimum alignment is 4k (GTT page size), but might be greater
1515 * if a fence register is needed for the object.
1517 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1518 tiling_mode
== I915_TILING_NONE
)
1522 * Previous chips need to be aligned to the size of the smallest
1523 * fence register that can contain the object.
1525 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1528 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1530 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1533 if (drm_vma_node_has_offset(&obj
->base
.vma_node
))
1536 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1538 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1542 /* Badly fragmented mmap space? The only way we can recover
1543 * space is by destroying unwanted objects. We can't randomly release
1544 * mmap_offsets as userspace expects them to be persistent for the
1545 * lifetime of the objects. The closest we can is to release the
1546 * offsets on purgeable objects by truncating it and marking it purged,
1547 * which prevents userspace from ever using that object again.
1549 i915_gem_purge(dev_priv
, obj
->base
.size
>> PAGE_SHIFT
);
1550 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1554 i915_gem_shrink_all(dev_priv
);
1555 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1557 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
1562 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1564 drm_gem_free_mmap_offset(&obj
->base
);
1568 i915_gem_mmap_gtt(struct drm_file
*file
,
1569 struct drm_device
*dev
,
1573 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1574 struct drm_i915_gem_object
*obj
;
1577 ret
= i915_mutex_lock_interruptible(dev
);
1581 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1582 if (&obj
->base
== NULL
) {
1587 if (obj
->base
.size
> dev_priv
->gtt
.mappable_end
) {
1592 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1593 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1598 ret
= i915_gem_object_create_mmap_offset(obj
);
1602 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
1605 drm_gem_object_unreference(&obj
->base
);
1607 mutex_unlock(&dev
->struct_mutex
);
1612 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1614 * @data: GTT mapping ioctl data
1615 * @file: GEM object info
1617 * Simply returns the fake offset to userspace so it can mmap it.
1618 * The mmap call will end up in drm_gem_mmap(), which will set things
1619 * up so we can get faults in the handler above.
1621 * The fault handler will take care of binding the object into the GTT
1622 * (since it may have been evicted to make room for something), allocating
1623 * a fence register, and mapping the appropriate aperture address into
1627 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1628 struct drm_file
*file
)
1630 struct drm_i915_gem_mmap_gtt
*args
= data
;
1632 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1635 /* Immediately discard the backing storage */
1637 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1639 struct inode
*inode
;
1641 i915_gem_object_free_mmap_offset(obj
);
1643 if (obj
->base
.filp
== NULL
)
1646 /* Our goal here is to return as much of the memory as
1647 * is possible back to the system as we are called from OOM.
1648 * To do this we must instruct the shmfs to drop all of its
1649 * backing pages, *now*.
1651 inode
= file_inode(obj
->base
.filp
);
1652 shmem_truncate_range(inode
, 0, (loff_t
)-1);
1654 obj
->madv
= __I915_MADV_PURGED
;
1658 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1660 return obj
->madv
== I915_MADV_DONTNEED
;
1664 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1666 struct sg_page_iter sg_iter
;
1669 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1671 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1673 /* In the event of a disaster, abandon all caches and
1674 * hope for the best.
1676 WARN_ON(ret
!= -EIO
);
1677 i915_gem_clflush_object(obj
, true);
1678 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
1681 if (i915_gem_object_needs_bit17_swizzle(obj
))
1682 i915_gem_object_save_bit_17_swizzle(obj
);
1684 if (obj
->madv
== I915_MADV_DONTNEED
)
1687 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
1688 struct page
*page
= sg_page_iter_page(&sg_iter
);
1691 set_page_dirty(page
);
1693 if (obj
->madv
== I915_MADV_WILLNEED
)
1694 mark_page_accessed(page
);
1696 page_cache_release(page
);
1700 sg_free_table(obj
->pages
);
1705 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
1707 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1709 if (obj
->pages
== NULL
)
1712 if (obj
->pages_pin_count
)
1715 BUG_ON(i915_gem_obj_bound_any(obj
));
1717 /* ->put_pages might need to allocate memory for the bit17 swizzle
1718 * array, hence protect them from being reaped by removing them from gtt
1720 list_del(&obj
->global_list
);
1722 ops
->put_pages(obj
);
1725 if (i915_gem_object_is_purgeable(obj
))
1726 i915_gem_object_truncate(obj
);
1731 static unsigned long
1732 __i915_gem_shrink(struct drm_i915_private
*dev_priv
, long target
,
1733 bool purgeable_only
)
1735 struct list_head still_bound_list
;
1736 struct drm_i915_gem_object
*obj
, *next
;
1737 unsigned long count
= 0;
1739 list_for_each_entry_safe(obj
, next
,
1740 &dev_priv
->mm
.unbound_list
,
1742 if ((i915_gem_object_is_purgeable(obj
) || !purgeable_only
) &&
1743 i915_gem_object_put_pages(obj
) == 0) {
1744 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1745 if (count
>= target
)
1751 * As we may completely rewrite the bound list whilst unbinding
1752 * (due to retiring requests) we have to strictly process only
1753 * one element of the list at the time, and recheck the list
1754 * on every iteration.
1756 INIT_LIST_HEAD(&still_bound_list
);
1757 while (count
< target
&& !list_empty(&dev_priv
->mm
.bound_list
)) {
1758 struct i915_vma
*vma
, *v
;
1760 obj
= list_first_entry(&dev_priv
->mm
.bound_list
,
1761 typeof(*obj
), global_list
);
1762 list_move_tail(&obj
->global_list
, &still_bound_list
);
1764 if (!i915_gem_object_is_purgeable(obj
) && purgeable_only
)
1768 * Hold a reference whilst we unbind this object, as we may
1769 * end up waiting for and retiring requests. This might
1770 * release the final reference (held by the active list)
1771 * and result in the object being freed from under us.
1772 * in this object being freed.
1774 * Note 1: Shrinking the bound list is special since only active
1775 * (and hence bound objects) can contain such limbo objects, so
1776 * we don't need special tricks for shrinking the unbound list.
1777 * The only other place where we have to be careful with active
1778 * objects suddenly disappearing due to retiring requests is the
1781 * Note 2: Even though the bound list doesn't hold a reference
1782 * to the object we can safely grab one here: The final object
1783 * unreferencing and the bound_list are both protected by the
1784 * dev->struct_mutex and so we won't ever be able to observe an
1785 * object on the bound_list with a reference count equals 0.
1787 drm_gem_object_reference(&obj
->base
);
1789 list_for_each_entry_safe(vma
, v
, &obj
->vma_list
, vma_link
)
1790 if (i915_vma_unbind(vma
))
1793 if (i915_gem_object_put_pages(obj
) == 0)
1794 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1796 drm_gem_object_unreference(&obj
->base
);
1798 list_splice(&still_bound_list
, &dev_priv
->mm
.bound_list
);
1803 static unsigned long
1804 i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
)
1806 return __i915_gem_shrink(dev_priv
, target
, true);
1809 static unsigned long
1810 i915_gem_shrink_all(struct drm_i915_private
*dev_priv
)
1812 struct drm_i915_gem_object
*obj
, *next
;
1815 i915_gem_evict_everything(dev_priv
->dev
);
1817 list_for_each_entry_safe(obj
, next
, &dev_priv
->mm
.unbound_list
,
1819 if (i915_gem_object_put_pages(obj
) == 0)
1820 freed
+= obj
->base
.size
>> PAGE_SHIFT
;
1826 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
1828 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1830 struct address_space
*mapping
;
1831 struct sg_table
*st
;
1832 struct scatterlist
*sg
;
1833 struct sg_page_iter sg_iter
;
1835 unsigned long last_pfn
= 0; /* suppress gcc warning */
1838 /* Assert that the object is not currently in any GPU domain. As it
1839 * wasn't in the GTT, there shouldn't be any way it could have been in
1842 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
1843 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
1845 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
1849 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1850 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
1855 /* Get the list of pages out of our struct file. They'll be pinned
1856 * at this point until we release them.
1858 * Fail silently without starting the shrinker
1860 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
1861 gfp
= mapping_gfp_mask(mapping
);
1862 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1863 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1866 for (i
= 0; i
< page_count
; i
++) {
1867 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1869 i915_gem_purge(dev_priv
, page_count
);
1870 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1873 /* We've tried hard to allocate the memory by reaping
1874 * our own buffer, now let the real VM do its job and
1875 * go down in flames if truly OOM.
1877 gfp
&= ~(__GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
);
1878 gfp
|= __GFP_IO
| __GFP_WAIT
;
1880 i915_gem_shrink_all(dev_priv
);
1881 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1885 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1886 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1888 #ifdef CONFIG_SWIOTLB
1889 if (swiotlb_nr_tbl()) {
1891 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
1896 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
1900 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
1902 sg
->length
+= PAGE_SIZE
;
1904 last_pfn
= page_to_pfn(page
);
1906 /* Check that the i965g/gm workaround works. */
1907 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
1909 #ifdef CONFIG_SWIOTLB
1910 if (!swiotlb_nr_tbl())
1915 if (i915_gem_object_needs_bit17_swizzle(obj
))
1916 i915_gem_object_do_bit_17_swizzle(obj
);
1922 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
1923 page_cache_release(sg_page_iter_page(&sg_iter
));
1926 return PTR_ERR(page
);
1929 /* Ensure that the associated pages are gathered from the backing storage
1930 * and pinned into our object. i915_gem_object_get_pages() may be called
1931 * multiple times before they are released by a single call to
1932 * i915_gem_object_put_pages() - once the pages are no longer referenced
1933 * either as a result of memory pressure (reaping pages under the shrinker)
1934 * or as the object is itself released.
1937 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
1939 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1940 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1946 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1947 DRM_ERROR("Attempting to obtain a purgeable object\n");
1951 BUG_ON(obj
->pages_pin_count
);
1953 ret
= ops
->get_pages(obj
);
1957 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
1962 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1963 struct intel_ring_buffer
*ring
)
1965 struct drm_device
*dev
= obj
->base
.dev
;
1966 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1967 u32 seqno
= intel_ring_get_seqno(ring
);
1969 BUG_ON(ring
== NULL
);
1970 if (obj
->ring
!= ring
&& obj
->last_write_seqno
) {
1971 /* Keep the seqno relative to the current ring */
1972 obj
->last_write_seqno
= seqno
;
1976 /* Add a reference if we're newly entering the active list. */
1978 drm_gem_object_reference(&obj
->base
);
1982 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
1984 obj
->last_read_seqno
= seqno
;
1986 if (obj
->fenced_gpu_access
) {
1987 obj
->last_fenced_seqno
= seqno
;
1989 /* Bump MRU to take account of the delayed flush */
1990 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1991 struct drm_i915_fence_reg
*reg
;
1993 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
1994 list_move_tail(®
->lru_list
,
1995 &dev_priv
->mm
.fence_list
);
2000 void i915_vma_move_to_active(struct i915_vma
*vma
,
2001 struct intel_ring_buffer
*ring
)
2003 list_move_tail(&vma
->mm_list
, &vma
->vm
->active_list
);
2004 return i915_gem_object_move_to_active(vma
->obj
, ring
);
2008 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
2010 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2011 struct i915_address_space
*vm
;
2012 struct i915_vma
*vma
;
2014 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
2015 BUG_ON(!obj
->active
);
2017 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
2018 vma
= i915_gem_obj_to_vma(obj
, vm
);
2019 if (vma
&& !list_empty(&vma
->mm_list
))
2020 list_move_tail(&vma
->mm_list
, &vm
->inactive_list
);
2023 list_del_init(&obj
->ring_list
);
2026 obj
->last_read_seqno
= 0;
2027 obj
->last_write_seqno
= 0;
2028 obj
->base
.write_domain
= 0;
2030 obj
->last_fenced_seqno
= 0;
2031 obj
->fenced_gpu_access
= false;
2034 drm_gem_object_unreference(&obj
->base
);
2036 WARN_ON(i915_verify_lists(dev
));
2040 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
2042 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2043 struct intel_ring_buffer
*ring
;
2046 /* Carefully retire all requests without writing to the rings */
2047 for_each_ring(ring
, dev_priv
, i
) {
2048 ret
= intel_ring_idle(ring
);
2052 i915_gem_retire_requests(dev
);
2054 /* Finally reset hw state */
2055 for_each_ring(ring
, dev_priv
, i
) {
2056 intel_ring_init_seqno(ring
, seqno
);
2058 for (j
= 0; j
< ARRAY_SIZE(ring
->sync_seqno
); j
++)
2059 ring
->sync_seqno
[j
] = 0;
2065 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2067 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2073 /* HWS page needs to be set less than what we
2074 * will inject to ring
2076 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
2080 /* Carefully set the last_seqno value so that wrap
2081 * detection still works
2083 dev_priv
->next_seqno
= seqno
;
2084 dev_priv
->last_seqno
= seqno
- 1;
2085 if (dev_priv
->last_seqno
== 0)
2086 dev_priv
->last_seqno
--;
2092 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
2094 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2096 /* reserve 0 for non-seqno */
2097 if (dev_priv
->next_seqno
== 0) {
2098 int ret
= i915_gem_init_seqno(dev
, 0);
2102 dev_priv
->next_seqno
= 1;
2105 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2109 int __i915_add_request(struct intel_ring_buffer
*ring
,
2110 struct drm_file
*file
,
2111 struct drm_i915_gem_object
*obj
,
2114 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
2115 struct drm_i915_gem_request
*request
;
2116 u32 request_ring_position
, request_start
;
2120 request_start
= intel_ring_get_tail(ring
);
2122 * Emit any outstanding flushes - execbuf can fail to emit the flush
2123 * after having emitted the batchbuffer command. Hence we need to fix
2124 * things up similar to emitting the lazy request. The difference here
2125 * is that the flush _must_ happen before the next request, no matter
2128 ret
= intel_ring_flush_all_caches(ring
);
2132 request
= ring
->preallocated_lazy_request
;
2133 if (WARN_ON(request
== NULL
))
2136 /* Record the position of the start of the request so that
2137 * should we detect the updated seqno part-way through the
2138 * GPU processing the request, we never over-estimate the
2139 * position of the head.
2141 request_ring_position
= intel_ring_get_tail(ring
);
2143 ret
= ring
->add_request(ring
);
2147 request
->seqno
= intel_ring_get_seqno(ring
);
2148 request
->ring
= ring
;
2149 request
->head
= request_start
;
2150 request
->tail
= request_ring_position
;
2152 /* Whilst this request exists, batch_obj will be on the
2153 * active_list, and so will hold the active reference. Only when this
2154 * request is retired will the the batch_obj be moved onto the
2155 * inactive_list and lose its active reference. Hence we do not need
2156 * to explicitly hold another reference here.
2158 request
->batch_obj
= obj
;
2160 /* Hold a reference to the current context so that we can inspect
2161 * it later in case a hangcheck error event fires.
2163 request
->ctx
= ring
->last_context
;
2165 i915_gem_context_reference(request
->ctx
);
2167 request
->emitted_jiffies
= jiffies
;
2168 was_empty
= list_empty(&ring
->request_list
);
2169 list_add_tail(&request
->list
, &ring
->request_list
);
2170 request
->file_priv
= NULL
;
2173 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2175 spin_lock(&file_priv
->mm
.lock
);
2176 request
->file_priv
= file_priv
;
2177 list_add_tail(&request
->client_list
,
2178 &file_priv
->mm
.request_list
);
2179 spin_unlock(&file_priv
->mm
.lock
);
2182 trace_i915_gem_request_add(ring
, request
->seqno
);
2183 ring
->outstanding_lazy_seqno
= 0;
2184 ring
->preallocated_lazy_request
= NULL
;
2186 if (!dev_priv
->ums
.mm_suspended
) {
2187 i915_queue_hangcheck(ring
->dev
);
2190 cancel_delayed_work_sync(&dev_priv
->mm
.idle_work
);
2191 queue_delayed_work(dev_priv
->wq
,
2192 &dev_priv
->mm
.retire_work
,
2193 round_jiffies_up_relative(HZ
));
2194 intel_mark_busy(dev_priv
->dev
);
2199 *out_seqno
= request
->seqno
;
2204 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2206 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2211 spin_lock(&file_priv
->mm
.lock
);
2212 list_del(&request
->client_list
);
2213 request
->file_priv
= NULL
;
2214 spin_unlock(&file_priv
->mm
.lock
);
2217 static bool i915_head_inside_object(u32 acthd
, struct drm_i915_gem_object
*obj
,
2218 struct i915_address_space
*vm
)
2220 if (acthd
>= i915_gem_obj_offset(obj
, vm
) &&
2221 acthd
< i915_gem_obj_offset(obj
, vm
) + obj
->base
.size
)
2227 static bool i915_head_inside_request(const u32 acthd_unmasked
,
2228 const u32 request_start
,
2229 const u32 request_end
)
2231 const u32 acthd
= acthd_unmasked
& HEAD_ADDR
;
2233 if (request_start
< request_end
) {
2234 if (acthd
>= request_start
&& acthd
< request_end
)
2236 } else if (request_start
> request_end
) {
2237 if (acthd
>= request_start
|| acthd
< request_end
)
2244 static struct i915_address_space
*
2245 request_to_vm(struct drm_i915_gem_request
*request
)
2247 struct drm_i915_private
*dev_priv
= request
->ring
->dev
->dev_private
;
2248 struct i915_address_space
*vm
;
2250 vm
= &dev_priv
->gtt
.base
;
2255 static bool i915_request_guilty(struct drm_i915_gem_request
*request
,
2256 const u32 acthd
, bool *inside
)
2258 /* There is a possibility that unmasked head address
2259 * pointing inside the ring, matches the batch_obj address range.
2260 * However this is extremely unlikely.
2262 if (request
->batch_obj
) {
2263 if (i915_head_inside_object(acthd
, request
->batch_obj
,
2264 request_to_vm(request
))) {
2270 if (i915_head_inside_request(acthd
, request
->head
, request
->tail
)) {
2278 static bool i915_context_is_banned(const struct i915_ctx_hang_stats
*hs
)
2280 const unsigned long elapsed
= get_seconds() - hs
->guilty_ts
;
2285 if (elapsed
<= DRM_I915_CTX_BAN_PERIOD
) {
2286 DRM_ERROR("context hanging too fast, declaring banned!\n");
2293 static void i915_set_reset_status(struct intel_ring_buffer
*ring
,
2294 struct drm_i915_gem_request
*request
,
2297 struct i915_ctx_hang_stats
*hs
= NULL
;
2298 bool inside
, guilty
;
2299 unsigned long offset
= 0;
2301 /* Innocent until proven guilty */
2304 if (request
->batch_obj
)
2305 offset
= i915_gem_obj_offset(request
->batch_obj
,
2306 request_to_vm(request
));
2308 if (ring
->hangcheck
.action
!= HANGCHECK_WAIT
&&
2309 i915_request_guilty(request
, acthd
, &inside
)) {
2310 DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n",
2312 inside
? "inside" : "flushing",
2314 request
->ctx
? request
->ctx
->id
: 0,
2320 /* If contexts are disabled or this is the default context, use
2321 * file_priv->reset_state
2323 if (request
->ctx
&& request
->ctx
->id
!= DEFAULT_CONTEXT_ID
)
2324 hs
= &request
->ctx
->hang_stats
;
2325 else if (request
->file_priv
)
2326 hs
= &request
->file_priv
->private_default_ctx
->hang_stats
;
2330 hs
->banned
= i915_context_is_banned(hs
);
2332 hs
->guilty_ts
= get_seconds();
2334 hs
->batch_pending
++;
2339 static void i915_gem_free_request(struct drm_i915_gem_request
*request
)
2341 list_del(&request
->list
);
2342 i915_gem_request_remove_from_client(request
);
2345 i915_gem_context_unreference(request
->ctx
);
2350 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
2351 struct intel_ring_buffer
*ring
)
2353 u32 completed_seqno
;
2356 acthd
= intel_ring_get_active_head(ring
);
2357 completed_seqno
= ring
->get_seqno(ring
, false);
2359 while (!list_empty(&ring
->request_list
)) {
2360 struct drm_i915_gem_request
*request
;
2362 request
= list_first_entry(&ring
->request_list
,
2363 struct drm_i915_gem_request
,
2366 if (request
->seqno
> completed_seqno
)
2367 i915_set_reset_status(ring
, request
, acthd
);
2369 i915_gem_free_request(request
);
2372 while (!list_empty(&ring
->active_list
)) {
2373 struct drm_i915_gem_object
*obj
;
2375 obj
= list_first_entry(&ring
->active_list
,
2376 struct drm_i915_gem_object
,
2379 i915_gem_object_move_to_inactive(obj
);
2383 void i915_gem_restore_fences(struct drm_device
*dev
)
2385 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2388 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2389 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2392 * Commit delayed tiling changes if we have an object still
2393 * attached to the fence, otherwise just clear the fence.
2396 i915_gem_object_update_fence(reg
->obj
, reg
,
2397 reg
->obj
->tiling_mode
);
2399 i915_gem_write_fence(dev
, i
, NULL
);
2404 void i915_gem_reset(struct drm_device
*dev
)
2406 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2407 struct intel_ring_buffer
*ring
;
2410 for_each_ring(ring
, dev_priv
, i
)
2411 i915_gem_reset_ring_lists(dev_priv
, ring
);
2413 i915_gem_cleanup_ringbuffer(dev
);
2415 i915_gem_context_reset(dev
);
2417 i915_gem_restore_fences(dev
);
2421 * This function clears the request list as sequence numbers are passed.
2424 i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
)
2428 if (list_empty(&ring
->request_list
))
2431 WARN_ON(i915_verify_lists(ring
->dev
));
2433 seqno
= ring
->get_seqno(ring
, true);
2435 while (!list_empty(&ring
->request_list
)) {
2436 struct drm_i915_gem_request
*request
;
2438 request
= list_first_entry(&ring
->request_list
,
2439 struct drm_i915_gem_request
,
2442 if (!i915_seqno_passed(seqno
, request
->seqno
))
2445 trace_i915_gem_request_retire(ring
, request
->seqno
);
2446 /* We know the GPU must have read the request to have
2447 * sent us the seqno + interrupt, so use the position
2448 * of tail of the request to update the last known position
2451 ring
->last_retired_head
= request
->tail
;
2453 i915_gem_free_request(request
);
2456 /* Move any buffers on the active list that are no longer referenced
2457 * by the ringbuffer to the flushing/inactive lists as appropriate.
2459 while (!list_empty(&ring
->active_list
)) {
2460 struct drm_i915_gem_object
*obj
;
2462 obj
= list_first_entry(&ring
->active_list
,
2463 struct drm_i915_gem_object
,
2466 if (!i915_seqno_passed(seqno
, obj
->last_read_seqno
))
2469 i915_gem_object_move_to_inactive(obj
);
2472 if (unlikely(ring
->trace_irq_seqno
&&
2473 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
2474 ring
->irq_put(ring
);
2475 ring
->trace_irq_seqno
= 0;
2478 WARN_ON(i915_verify_lists(ring
->dev
));
2482 i915_gem_retire_requests(struct drm_device
*dev
)
2484 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2485 struct intel_ring_buffer
*ring
;
2489 for_each_ring(ring
, dev_priv
, i
) {
2490 i915_gem_retire_requests_ring(ring
);
2491 idle
&= list_empty(&ring
->request_list
);
2495 mod_delayed_work(dev_priv
->wq
,
2496 &dev_priv
->mm
.idle_work
,
2497 msecs_to_jiffies(100));
2503 i915_gem_retire_work_handler(struct work_struct
*work
)
2505 struct drm_i915_private
*dev_priv
=
2506 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
2507 struct drm_device
*dev
= dev_priv
->dev
;
2510 /* Come back later if the device is busy... */
2512 if (mutex_trylock(&dev
->struct_mutex
)) {
2513 idle
= i915_gem_retire_requests(dev
);
2514 mutex_unlock(&dev
->struct_mutex
);
2517 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2518 round_jiffies_up_relative(HZ
));
2522 i915_gem_idle_work_handler(struct work_struct
*work
)
2524 struct drm_i915_private
*dev_priv
=
2525 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
2527 intel_mark_idle(dev_priv
->dev
);
2531 * Ensures that an object will eventually get non-busy by flushing any required
2532 * write domains, emitting any outstanding lazy request and retiring and
2533 * completed requests.
2536 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2541 ret
= i915_gem_check_olr(obj
->ring
, obj
->last_read_seqno
);
2545 i915_gem_retire_requests_ring(obj
->ring
);
2552 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2553 * @DRM_IOCTL_ARGS: standard ioctl arguments
2555 * Returns 0 if successful, else an error is returned with the remaining time in
2556 * the timeout parameter.
2557 * -ETIME: object is still busy after timeout
2558 * -ERESTARTSYS: signal interrupted the wait
2559 * -ENONENT: object doesn't exist
2560 * Also possible, but rare:
2561 * -EAGAIN: GPU wedged
2563 * -ENODEV: Internal IRQ fail
2564 * -E?: The add request failed
2566 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2567 * non-zero timeout parameter the wait ioctl will wait for the given number of
2568 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2569 * without holding struct_mutex the object may become re-busied before this
2570 * function completes. A similar but shorter * race condition exists in the busy
2574 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2576 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2577 struct drm_i915_gem_wait
*args
= data
;
2578 struct drm_i915_gem_object
*obj
;
2579 struct intel_ring_buffer
*ring
= NULL
;
2580 struct timespec timeout_stack
, *timeout
= NULL
;
2581 unsigned reset_counter
;
2585 if (args
->timeout_ns
>= 0) {
2586 timeout_stack
= ns_to_timespec(args
->timeout_ns
);
2587 timeout
= &timeout_stack
;
2590 ret
= i915_mutex_lock_interruptible(dev
);
2594 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2595 if (&obj
->base
== NULL
) {
2596 mutex_unlock(&dev
->struct_mutex
);
2600 /* Need to make sure the object gets inactive eventually. */
2601 ret
= i915_gem_object_flush_active(obj
);
2606 seqno
= obj
->last_read_seqno
;
2613 /* Do this after OLR check to make sure we make forward progress polling
2614 * on this IOCTL with a 0 timeout (like busy ioctl)
2616 if (!args
->timeout_ns
) {
2621 drm_gem_object_unreference(&obj
->base
);
2622 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
2623 mutex_unlock(&dev
->struct_mutex
);
2625 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, timeout
, file
->driver_priv
);
2627 args
->timeout_ns
= timespec_to_ns(timeout
);
2631 drm_gem_object_unreference(&obj
->base
);
2632 mutex_unlock(&dev
->struct_mutex
);
2637 * i915_gem_object_sync - sync an object to a ring.
2639 * @obj: object which may be in use on another ring.
2640 * @to: ring we wish to use the object on. May be NULL.
2642 * This code is meant to abstract object synchronization with the GPU.
2643 * Calling with NULL implies synchronizing the object with the CPU
2644 * rather than a particular GPU ring.
2646 * Returns 0 if successful, else propagates up the lower layer error.
2649 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2650 struct intel_ring_buffer
*to
)
2652 struct intel_ring_buffer
*from
= obj
->ring
;
2656 if (from
== NULL
|| to
== from
)
2659 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2660 return i915_gem_object_wait_rendering(obj
, false);
2662 idx
= intel_ring_sync_index(from
, to
);
2664 seqno
= obj
->last_read_seqno
;
2665 if (seqno
<= from
->sync_seqno
[idx
])
2668 ret
= i915_gem_check_olr(obj
->ring
, seqno
);
2672 trace_i915_gem_ring_sync_to(from
, to
, seqno
);
2673 ret
= to
->sync_to(to
, from
, seqno
);
2675 /* We use last_read_seqno because sync_to()
2676 * might have just caused seqno wrap under
2679 from
->sync_seqno
[idx
] = obj
->last_read_seqno
;
2684 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
2686 u32 old_write_domain
, old_read_domains
;
2688 /* Force a pagefault for domain tracking on next user access */
2689 i915_gem_release_mmap(obj
);
2691 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2694 /* Wait for any direct GTT access to complete */
2697 old_read_domains
= obj
->base
.read_domains
;
2698 old_write_domain
= obj
->base
.write_domain
;
2700 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2701 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2703 trace_i915_gem_object_change_domain(obj
,
2708 int i915_vma_unbind(struct i915_vma
*vma
)
2710 struct drm_i915_gem_object
*obj
= vma
->obj
;
2711 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2714 /* For now we only ever use 1 vma per object */
2715 WARN_ON(!list_is_singular(&obj
->vma_list
));
2717 if (list_empty(&vma
->vma_link
))
2720 if (!drm_mm_node_allocated(&vma
->node
)) {
2721 i915_gem_vma_destroy(vma
);
2729 BUG_ON(obj
->pages
== NULL
);
2731 ret
= i915_gem_object_finish_gpu(obj
);
2734 /* Continue on if we fail due to EIO, the GPU is hung so we
2735 * should be safe and we need to cleanup or else we might
2736 * cause memory corruption through use-after-free.
2739 i915_gem_object_finish_gtt(obj
);
2741 /* release the fence reg _after_ flushing */
2742 ret
= i915_gem_object_put_fence(obj
);
2746 trace_i915_vma_unbind(vma
);
2748 vma
->unbind_vma(vma
);
2750 i915_gem_gtt_finish_object(obj
);
2752 list_del(&vma
->mm_list
);
2753 /* Avoid an unnecessary call to unbind on rebind. */
2754 if (i915_is_ggtt(vma
->vm
))
2755 obj
->map_and_fenceable
= true;
2757 drm_mm_remove_node(&vma
->node
);
2758 i915_gem_vma_destroy(vma
);
2760 /* Since the unbound list is global, only move to that list if
2761 * no more VMAs exist. */
2762 if (list_empty(&obj
->vma_list
))
2763 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2765 /* And finally now the object is completely decoupled from this vma,
2766 * we can drop its hold on the backing storage and allow it to be
2767 * reaped by the shrinker.
2769 i915_gem_object_unpin_pages(obj
);
2775 * Unbinds an object from the global GTT aperture.
2778 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
2780 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2781 struct i915_address_space
*ggtt
= &dev_priv
->gtt
.base
;
2783 if (!i915_gem_obj_ggtt_bound(obj
))
2786 if (i915_gem_obj_to_ggtt(obj
)->pin_count
)
2789 BUG_ON(obj
->pages
== NULL
);
2791 return i915_vma_unbind(i915_gem_obj_to_vma(obj
, ggtt
));
2794 int i915_gpu_idle(struct drm_device
*dev
)
2796 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2797 struct intel_ring_buffer
*ring
;
2800 /* Flush everything onto the inactive list. */
2801 for_each_ring(ring
, dev_priv
, i
) {
2802 ret
= i915_switch_context(ring
, NULL
, DEFAULT_CONTEXT_ID
);
2806 ret
= intel_ring_idle(ring
);
2814 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
2815 struct drm_i915_gem_object
*obj
)
2817 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2819 int fence_pitch_shift
;
2821 if (INTEL_INFO(dev
)->gen
>= 6) {
2822 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
2823 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2825 fence_reg
= FENCE_REG_965_0
;
2826 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
2829 fence_reg
+= reg
* 8;
2831 /* To w/a incoherency with non-atomic 64-bit register updates,
2832 * we split the 64-bit update into two 32-bit writes. In order
2833 * for a partial fence not to be evaluated between writes, we
2834 * precede the update with write to turn off the fence register,
2835 * and only enable the fence as the last step.
2837 * For extra levels of paranoia, we make sure each step lands
2838 * before applying the next step.
2840 I915_WRITE(fence_reg
, 0);
2841 POSTING_READ(fence_reg
);
2844 u32 size
= i915_gem_obj_ggtt_size(obj
);
2847 val
= (uint64_t)((i915_gem_obj_ggtt_offset(obj
) + size
- 4096) &
2849 val
|= i915_gem_obj_ggtt_offset(obj
) & 0xfffff000;
2850 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
2851 if (obj
->tiling_mode
== I915_TILING_Y
)
2852 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2853 val
|= I965_FENCE_REG_VALID
;
2855 I915_WRITE(fence_reg
+ 4, val
>> 32);
2856 POSTING_READ(fence_reg
+ 4);
2858 I915_WRITE(fence_reg
+ 0, val
);
2859 POSTING_READ(fence_reg
);
2861 I915_WRITE(fence_reg
+ 4, 0);
2862 POSTING_READ(fence_reg
+ 4);
2866 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
2867 struct drm_i915_gem_object
*obj
)
2869 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2873 u32 size
= i915_gem_obj_ggtt_size(obj
);
2877 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I915_FENCE_START_MASK
) ||
2878 (size
& -size
) != size
||
2879 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
2880 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2881 i915_gem_obj_ggtt_offset(obj
), obj
->map_and_fenceable
, size
);
2883 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2888 /* Note: pitch better be a power of two tile widths */
2889 pitch_val
= obj
->stride
/ tile_width
;
2890 pitch_val
= ffs(pitch_val
) - 1;
2892 val
= i915_gem_obj_ggtt_offset(obj
);
2893 if (obj
->tiling_mode
== I915_TILING_Y
)
2894 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2895 val
|= I915_FENCE_SIZE_BITS(size
);
2896 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2897 val
|= I830_FENCE_REG_VALID
;
2902 reg
= FENCE_REG_830_0
+ reg
* 4;
2904 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
2906 I915_WRITE(reg
, val
);
2910 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
2911 struct drm_i915_gem_object
*obj
)
2913 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2917 u32 size
= i915_gem_obj_ggtt_size(obj
);
2920 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I830_FENCE_START_MASK
) ||
2921 (size
& -size
) != size
||
2922 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
2923 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2924 i915_gem_obj_ggtt_offset(obj
), size
);
2926 pitch_val
= obj
->stride
/ 128;
2927 pitch_val
= ffs(pitch_val
) - 1;
2929 val
= i915_gem_obj_ggtt_offset(obj
);
2930 if (obj
->tiling_mode
== I915_TILING_Y
)
2931 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2932 val
|= I830_FENCE_SIZE_BITS(size
);
2933 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2934 val
|= I830_FENCE_REG_VALID
;
2938 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
2939 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
2942 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
2944 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
2947 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
2948 struct drm_i915_gem_object
*obj
)
2950 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2952 /* Ensure that all CPU reads are completed before installing a fence
2953 * and all writes before removing the fence.
2955 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
2958 WARN(obj
&& (!obj
->stride
|| !obj
->tiling_mode
),
2959 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
2960 obj
->stride
, obj
->tiling_mode
);
2962 switch (INTEL_INFO(dev
)->gen
) {
2967 case 4: i965_write_fence_reg(dev
, reg
, obj
); break;
2968 case 3: i915_write_fence_reg(dev
, reg
, obj
); break;
2969 case 2: i830_write_fence_reg(dev
, reg
, obj
); break;
2973 /* And similarly be paranoid that no direct access to this region
2974 * is reordered to before the fence is installed.
2976 if (i915_gem_object_needs_mb(obj
))
2980 static inline int fence_number(struct drm_i915_private
*dev_priv
,
2981 struct drm_i915_fence_reg
*fence
)
2983 return fence
- dev_priv
->fence_regs
;
2986 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
2987 struct drm_i915_fence_reg
*fence
,
2990 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2991 int reg
= fence_number(dev_priv
, fence
);
2993 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
2996 obj
->fence_reg
= reg
;
2998 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
3000 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3002 list_del_init(&fence
->lru_list
);
3004 obj
->fence_dirty
= false;
3008 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
3010 if (obj
->last_fenced_seqno
) {
3011 int ret
= i915_wait_seqno(obj
->ring
, obj
->last_fenced_seqno
);
3015 obj
->last_fenced_seqno
= 0;
3018 obj
->fenced_gpu_access
= false;
3023 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
3025 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3026 struct drm_i915_fence_reg
*fence
;
3029 ret
= i915_gem_object_wait_fence(obj
);
3033 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
3036 fence
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3038 i915_gem_object_fence_lost(obj
);
3039 i915_gem_object_update_fence(obj
, fence
, false);
3044 static struct drm_i915_fence_reg
*
3045 i915_find_fence_reg(struct drm_device
*dev
)
3047 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3048 struct drm_i915_fence_reg
*reg
, *avail
;
3051 /* First try to find a free reg */
3053 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
3054 reg
= &dev_priv
->fence_regs
[i
];
3058 if (!reg
->pin_count
)
3065 /* None available, try to steal one or wait for a user to finish */
3066 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
3077 * i915_gem_object_get_fence - set up fencing for an object
3078 * @obj: object to map through a fence reg
3080 * When mapping objects through the GTT, userspace wants to be able to write
3081 * to them without having to worry about swizzling if the object is tiled.
3082 * This function walks the fence regs looking for a free one for @obj,
3083 * stealing one if it can't find any.
3085 * It then sets up the reg based on the object's properties: address, pitch
3086 * and tiling format.
3088 * For an untiled surface, this removes any existing fence.
3091 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
3093 struct drm_device
*dev
= obj
->base
.dev
;
3094 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3095 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
3096 struct drm_i915_fence_reg
*reg
;
3099 /* Have we updated the tiling parameters upon the object and so
3100 * will need to serialise the write to the associated fence register?
3102 if (obj
->fence_dirty
) {
3103 ret
= i915_gem_object_wait_fence(obj
);
3108 /* Just update our place in the LRU if our fence is getting reused. */
3109 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
3110 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3111 if (!obj
->fence_dirty
) {
3112 list_move_tail(®
->lru_list
,
3113 &dev_priv
->mm
.fence_list
);
3116 } else if (enable
) {
3117 reg
= i915_find_fence_reg(dev
);
3122 struct drm_i915_gem_object
*old
= reg
->obj
;
3124 ret
= i915_gem_object_wait_fence(old
);
3128 i915_gem_object_fence_lost(old
);
3133 i915_gem_object_update_fence(obj
, reg
, enable
);
3138 static bool i915_gem_valid_gtt_space(struct drm_device
*dev
,
3139 struct drm_mm_node
*gtt_space
,
3140 unsigned long cache_level
)
3142 struct drm_mm_node
*other
;
3144 /* On non-LLC machines we have to be careful when putting differing
3145 * types of snoopable memory together to avoid the prefetcher
3146 * crossing memory domains and dying.
3151 if (!drm_mm_node_allocated(gtt_space
))
3154 if (list_empty(>t_space
->node_list
))
3157 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3158 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3161 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3162 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3168 static void i915_gem_verify_gtt(struct drm_device
*dev
)
3171 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3172 struct drm_i915_gem_object
*obj
;
3175 list_for_each_entry(obj
, &dev_priv
->mm
.gtt_list
, global_list
) {
3176 if (obj
->gtt_space
== NULL
) {
3177 printk(KERN_ERR
"object found on GTT list with no space reserved\n");
3182 if (obj
->cache_level
!= obj
->gtt_space
->color
) {
3183 printk(KERN_ERR
"object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3184 i915_gem_obj_ggtt_offset(obj
),
3185 i915_gem_obj_ggtt_offset(obj
) + i915_gem_obj_ggtt_size(obj
),
3187 obj
->gtt_space
->color
);
3192 if (!i915_gem_valid_gtt_space(dev
,
3194 obj
->cache_level
)) {
3195 printk(KERN_ERR
"invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3196 i915_gem_obj_ggtt_offset(obj
),
3197 i915_gem_obj_ggtt_offset(obj
) + i915_gem_obj_ggtt_size(obj
),
3209 * Finds free space in the GTT aperture and binds the object there.
3212 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3213 struct i915_address_space
*vm
,
3215 bool map_and_fenceable
,
3218 struct drm_device
*dev
= obj
->base
.dev
;
3219 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3220 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
3222 map_and_fenceable
? dev_priv
->gtt
.mappable_end
: vm
->total
;
3223 struct i915_vma
*vma
;
3226 fence_size
= i915_gem_get_gtt_size(dev
,
3229 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3231 obj
->tiling_mode
, true);
3232 unfenced_alignment
=
3233 i915_gem_get_gtt_alignment(dev
,
3235 obj
->tiling_mode
, false);
3238 alignment
= map_and_fenceable
? fence_alignment
:
3240 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
3241 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
3245 size
= map_and_fenceable
? fence_size
: obj
->base
.size
;
3247 /* If the object is bigger than the entire aperture, reject it early
3248 * before evicting everything in a vain attempt to find space.
3250 if (obj
->base
.size
> gtt_max
) {
3251 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3253 map_and_fenceable
? "mappable" : "total",
3258 ret
= i915_gem_object_get_pages(obj
);
3262 i915_gem_object_pin_pages(obj
);
3264 BUG_ON(!i915_is_ggtt(vm
));
3266 vma
= i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3272 /* For now we only ever use 1 vma per object */
3273 WARN_ON(!list_is_singular(&obj
->vma_list
));
3276 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3278 obj
->cache_level
, 0, gtt_max
,
3279 DRM_MM_SEARCH_DEFAULT
);
3281 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3290 if (WARN_ON(!i915_gem_valid_gtt_space(dev
, &vma
->node
,
3291 obj
->cache_level
))) {
3293 goto err_remove_node
;
3296 ret
= i915_gem_gtt_prepare_object(obj
);
3298 goto err_remove_node
;
3300 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3301 list_add_tail(&vma
->mm_list
, &vm
->inactive_list
);
3303 if (i915_is_ggtt(vm
)) {
3304 bool mappable
, fenceable
;
3306 fenceable
= (vma
->node
.size
== fence_size
&&
3307 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
3309 mappable
= (vma
->node
.start
+ obj
->base
.size
<=
3310 dev_priv
->gtt
.mappable_end
);
3312 obj
->map_and_fenceable
= mappable
&& fenceable
;
3315 WARN_ON(map_and_fenceable
&& !obj
->map_and_fenceable
);
3317 trace_i915_vma_bind(vma
, map_and_fenceable
);
3318 i915_gem_verify_gtt(dev
);
3322 drm_mm_remove_node(&vma
->node
);
3324 i915_gem_vma_destroy(vma
);
3326 i915_gem_object_unpin_pages(obj
);
3331 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3334 /* If we don't have a page list set up, then we're not pinned
3335 * to GPU, and we can ignore the cache flush because it'll happen
3336 * again at bind time.
3338 if (obj
->pages
== NULL
)
3342 * Stolen memory is always coherent with the GPU as it is explicitly
3343 * marked as wc by the system, or the system is cache-coherent.
3348 /* If the GPU is snooping the contents of the CPU cache,
3349 * we do not need to manually clear the CPU cache lines. However,
3350 * the caches are only snooped when the render cache is
3351 * flushed/invalidated. As we always have to emit invalidations
3352 * and flushes when moving into and out of the RENDER domain, correct
3353 * snooping behaviour occurs naturally as the result of our domain
3356 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
3359 trace_i915_gem_object_clflush(obj
);
3360 drm_clflush_sg(obj
->pages
);
3365 /** Flushes the GTT write domain for the object if it's dirty. */
3367 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3369 uint32_t old_write_domain
;
3371 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3374 /* No actual flushing is required for the GTT write domain. Writes
3375 * to it immediately go to main memory as far as we know, so there's
3376 * no chipset flush. It also doesn't land in render cache.
3378 * However, we do have to enforce the order so that all writes through
3379 * the GTT land before any writes to the device, such as updates to
3384 old_write_domain
= obj
->base
.write_domain
;
3385 obj
->base
.write_domain
= 0;
3387 trace_i915_gem_object_change_domain(obj
,
3388 obj
->base
.read_domains
,
3392 /** Flushes the CPU write domain for the object if it's dirty. */
3394 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
,
3397 uint32_t old_write_domain
;
3399 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3402 if (i915_gem_clflush_object(obj
, force
))
3403 i915_gem_chipset_flush(obj
->base
.dev
);
3405 old_write_domain
= obj
->base
.write_domain
;
3406 obj
->base
.write_domain
= 0;
3408 trace_i915_gem_object_change_domain(obj
,
3409 obj
->base
.read_domains
,
3414 * Moves a single object to the GTT read, and possibly write domain.
3416 * This function returns when the move is complete, including waiting on
3420 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3422 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
3423 uint32_t old_write_domain
, old_read_domains
;
3426 /* Not valid to be called on unbound objects. */
3427 if (!i915_gem_obj_bound_any(obj
))
3430 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3433 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3437 i915_gem_object_flush_cpu_write_domain(obj
, false);
3439 /* Serialise direct access to this object with the barriers for
3440 * coherent writes from the GPU, by effectively invalidating the
3441 * GTT domain upon first access.
3443 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3446 old_write_domain
= obj
->base
.write_domain
;
3447 old_read_domains
= obj
->base
.read_domains
;
3449 /* It should now be out of any other write domains, and we can update
3450 * the domain values for our changes.
3452 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3453 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3455 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3456 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3460 trace_i915_gem_object_change_domain(obj
,
3464 /* And bump the LRU for this access */
3465 if (i915_gem_object_is_inactive(obj
)) {
3466 struct i915_vma
*vma
= i915_gem_obj_to_ggtt(obj
);
3468 list_move_tail(&vma
->mm_list
,
3469 &dev_priv
->gtt
.base
.inactive_list
);
3476 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3477 enum i915_cache_level cache_level
)
3479 struct drm_device
*dev
= obj
->base
.dev
;
3480 struct i915_vma
*vma
;
3483 if (obj
->cache_level
== cache_level
)
3486 if (i915_gem_obj_is_pinned(obj
)) {
3487 DRM_DEBUG("can not change the cache level of pinned objects\n");
3491 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
3492 if (!i915_gem_valid_gtt_space(dev
, &vma
->node
, cache_level
)) {
3493 ret
= i915_vma_unbind(vma
);
3501 if (i915_gem_obj_bound_any(obj
)) {
3502 ret
= i915_gem_object_finish_gpu(obj
);
3506 i915_gem_object_finish_gtt(obj
);
3508 /* Before SandyBridge, you could not use tiling or fence
3509 * registers with snooped memory, so relinquish any fences
3510 * currently pointing to our region in the aperture.
3512 if (INTEL_INFO(dev
)->gen
< 6) {
3513 ret
= i915_gem_object_put_fence(obj
);
3518 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3519 vma
->bind_vma(vma
, cache_level
, 0);
3522 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3523 vma
->node
.color
= cache_level
;
3524 obj
->cache_level
= cache_level
;
3526 if (cpu_write_needs_clflush(obj
)) {
3527 u32 old_read_domains
, old_write_domain
;
3529 /* If we're coming from LLC cached, then we haven't
3530 * actually been tracking whether the data is in the
3531 * CPU cache or not, since we only allow one bit set
3532 * in obj->write_domain and have been skipping the clflushes.
3533 * Just set it to the CPU cache for now.
3535 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
3537 old_read_domains
= obj
->base
.read_domains
;
3538 old_write_domain
= obj
->base
.write_domain
;
3540 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3541 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3543 trace_i915_gem_object_change_domain(obj
,
3548 i915_gem_verify_gtt(dev
);
3552 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3553 struct drm_file
*file
)
3555 struct drm_i915_gem_caching
*args
= data
;
3556 struct drm_i915_gem_object
*obj
;
3559 ret
= i915_mutex_lock_interruptible(dev
);
3563 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3564 if (&obj
->base
== NULL
) {
3569 switch (obj
->cache_level
) {
3570 case I915_CACHE_LLC
:
3571 case I915_CACHE_L3_LLC
:
3572 args
->caching
= I915_CACHING_CACHED
;
3576 args
->caching
= I915_CACHING_DISPLAY
;
3580 args
->caching
= I915_CACHING_NONE
;
3584 drm_gem_object_unreference(&obj
->base
);
3586 mutex_unlock(&dev
->struct_mutex
);
3590 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3591 struct drm_file
*file
)
3593 struct drm_i915_gem_caching
*args
= data
;
3594 struct drm_i915_gem_object
*obj
;
3595 enum i915_cache_level level
;
3598 switch (args
->caching
) {
3599 case I915_CACHING_NONE
:
3600 level
= I915_CACHE_NONE
;
3602 case I915_CACHING_CACHED
:
3603 level
= I915_CACHE_LLC
;
3605 case I915_CACHING_DISPLAY
:
3606 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
3612 ret
= i915_mutex_lock_interruptible(dev
);
3616 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3617 if (&obj
->base
== NULL
) {
3622 ret
= i915_gem_object_set_cache_level(obj
, level
);
3624 drm_gem_object_unreference(&obj
->base
);
3626 mutex_unlock(&dev
->struct_mutex
);
3630 static bool is_pin_display(struct drm_i915_gem_object
*obj
)
3632 /* There are 3 sources that pin objects:
3633 * 1. The display engine (scanouts, sprites, cursors);
3634 * 2. Reservations for execbuffer;
3637 * We can ignore reservations as we hold the struct_mutex and
3638 * are only called outside of the reservation path. The user
3639 * can only increment pin_count once, and so if after
3640 * subtracting the potential reference by the user, any pin_count
3641 * remains, it must be due to another use by the display engine.
3643 return i915_gem_obj_to_ggtt(obj
)->pin_count
- !!obj
->user_pin_count
;
3647 * Prepare buffer for display plane (scanout, cursors, etc).
3648 * Can be called from an uninterruptible phase (modesetting) and allows
3649 * any flushes to be pipelined (for pageflips).
3652 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3654 struct intel_ring_buffer
*pipelined
)
3656 u32 old_read_domains
, old_write_domain
;
3659 if (pipelined
!= obj
->ring
) {
3660 ret
= i915_gem_object_sync(obj
, pipelined
);
3665 /* Mark the pin_display early so that we account for the
3666 * display coherency whilst setting up the cache domains.
3668 obj
->pin_display
= true;
3670 /* The display engine is not coherent with the LLC cache on gen6. As
3671 * a result, we make sure that the pinning that is about to occur is
3672 * done with uncached PTEs. This is lowest common denominator for all
3675 * However for gen6+, we could do better by using the GFDT bit instead
3676 * of uncaching, which would allow us to flush all the LLC-cached data
3677 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3679 ret
= i915_gem_object_set_cache_level(obj
,
3680 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
3682 goto err_unpin_display
;
3684 /* As the user may map the buffer once pinned in the display plane
3685 * (e.g. libkms for the bootup splash), we have to ensure that we
3686 * always use map_and_fenceable for all scanout buffers.
3688 ret
= i915_gem_obj_ggtt_pin(obj
, alignment
, true, false);
3690 goto err_unpin_display
;
3692 i915_gem_object_flush_cpu_write_domain(obj
, true);
3694 old_write_domain
= obj
->base
.write_domain
;
3695 old_read_domains
= obj
->base
.read_domains
;
3697 /* It should now be out of any other write domains, and we can update
3698 * the domain values for our changes.
3700 obj
->base
.write_domain
= 0;
3701 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3703 trace_i915_gem_object_change_domain(obj
,
3710 obj
->pin_display
= is_pin_display(obj
);
3715 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
)
3717 i915_gem_object_ggtt_unpin(obj
);
3718 obj
->pin_display
= is_pin_display(obj
);
3722 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
3726 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
3729 ret
= i915_gem_object_wait_rendering(obj
, false);
3733 /* Ensure that we invalidate the GPU's caches and TLBs. */
3734 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
3739 * Moves a single object to the CPU read, and possibly write domain.
3741 * This function returns when the move is complete, including waiting on
3745 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3747 uint32_t old_write_domain
, old_read_domains
;
3750 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3753 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3757 i915_gem_object_flush_gtt_write_domain(obj
);
3759 old_write_domain
= obj
->base
.write_domain
;
3760 old_read_domains
= obj
->base
.read_domains
;
3762 /* Flush the CPU cache if it's still invalid. */
3763 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3764 i915_gem_clflush_object(obj
, false);
3766 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3769 /* It should now be out of any other write domains, and we can update
3770 * the domain values for our changes.
3772 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3774 /* If we're writing through the CPU, then the GPU read domains will
3775 * need to be invalidated at next use.
3778 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3779 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3782 trace_i915_gem_object_change_domain(obj
,
3789 /* Throttle our rendering by waiting until the ring has completed our requests
3790 * emitted over 20 msec ago.
3792 * Note that if we were to use the current jiffies each time around the loop,
3793 * we wouldn't escape the function with any frames outstanding if the time to
3794 * render a frame was over 20ms.
3796 * This should get us reasonable parallelism between CPU and GPU but also
3797 * relatively low latency when blocking on a particular request to finish.
3800 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3802 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3803 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3804 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3805 struct drm_i915_gem_request
*request
;
3806 struct intel_ring_buffer
*ring
= NULL
;
3807 unsigned reset_counter
;
3811 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
3815 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
3819 spin_lock(&file_priv
->mm
.lock
);
3820 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3821 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3824 ring
= request
->ring
;
3825 seqno
= request
->seqno
;
3827 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3828 spin_unlock(&file_priv
->mm
.lock
);
3833 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, NULL
, NULL
);
3835 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3841 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3842 struct i915_address_space
*vm
,
3844 bool map_and_fenceable
,
3847 const u32 flags
= map_and_fenceable
? GLOBAL_BIND
: 0;
3848 struct i915_vma
*vma
;
3851 WARN_ON(map_and_fenceable
&& !i915_is_ggtt(vm
));
3853 vma
= i915_gem_obj_to_vma(obj
, vm
);
3856 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
3860 vma
->node
.start
& (alignment
- 1)) ||
3861 (map_and_fenceable
&& !obj
->map_and_fenceable
)) {
3862 WARN(vma
->pin_count
,
3863 "bo is already pinned with incorrect alignment:"
3864 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3865 " obj->map_and_fenceable=%d\n",
3866 i915_gem_obj_offset(obj
, vm
), alignment
,
3868 obj
->map_and_fenceable
);
3869 ret
= i915_vma_unbind(vma
);
3875 if (!i915_gem_obj_bound(obj
, vm
)) {
3876 ret
= i915_gem_object_bind_to_vm(obj
, vm
, alignment
,
3884 vma
= i915_gem_obj_to_vma(obj
, vm
);
3886 vma
->bind_vma(vma
, obj
->cache_level
, flags
);
3888 i915_gem_obj_to_vma(obj
, vm
)->pin_count
++;
3889 obj
->pin_mappable
|= map_and_fenceable
;
3895 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
)
3897 struct i915_vma
*vma
= i915_gem_obj_to_ggtt(obj
);
3900 BUG_ON(vma
->pin_count
== 0);
3901 BUG_ON(!i915_gem_obj_ggtt_bound(obj
));
3903 if (--vma
->pin_count
== 0)
3904 obj
->pin_mappable
= false;
3908 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3909 struct drm_file
*file
)
3911 struct drm_i915_gem_pin
*args
= data
;
3912 struct drm_i915_gem_object
*obj
;
3915 ret
= i915_mutex_lock_interruptible(dev
);
3919 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3920 if (&obj
->base
== NULL
) {
3925 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3926 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3931 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3932 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3938 if (obj
->user_pin_count
== ULONG_MAX
) {
3943 if (obj
->user_pin_count
== 0) {
3944 ret
= i915_gem_obj_ggtt_pin(obj
, args
->alignment
, true, false);
3949 obj
->user_pin_count
++;
3950 obj
->pin_filp
= file
;
3952 args
->offset
= i915_gem_obj_ggtt_offset(obj
);
3954 drm_gem_object_unreference(&obj
->base
);
3956 mutex_unlock(&dev
->struct_mutex
);
3961 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3962 struct drm_file
*file
)
3964 struct drm_i915_gem_pin
*args
= data
;
3965 struct drm_i915_gem_object
*obj
;
3968 ret
= i915_mutex_lock_interruptible(dev
);
3972 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3973 if (&obj
->base
== NULL
) {
3978 if (obj
->pin_filp
!= file
) {
3979 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3984 obj
->user_pin_count
--;
3985 if (obj
->user_pin_count
== 0) {
3986 obj
->pin_filp
= NULL
;
3987 i915_gem_object_ggtt_unpin(obj
);
3991 drm_gem_object_unreference(&obj
->base
);
3993 mutex_unlock(&dev
->struct_mutex
);
3998 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3999 struct drm_file
*file
)
4001 struct drm_i915_gem_busy
*args
= data
;
4002 struct drm_i915_gem_object
*obj
;
4005 ret
= i915_mutex_lock_interruptible(dev
);
4009 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4010 if (&obj
->base
== NULL
) {
4015 /* Count all active objects as busy, even if they are currently not used
4016 * by the gpu. Users of this interface expect objects to eventually
4017 * become non-busy without any further actions, therefore emit any
4018 * necessary flushes here.
4020 ret
= i915_gem_object_flush_active(obj
);
4022 args
->busy
= obj
->active
;
4024 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
4025 args
->busy
|= intel_ring_flag(obj
->ring
) << 16;
4028 drm_gem_object_unreference(&obj
->base
);
4030 mutex_unlock(&dev
->struct_mutex
);
4035 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4036 struct drm_file
*file_priv
)
4038 return i915_gem_ring_throttle(dev
, file_priv
);
4042 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4043 struct drm_file
*file_priv
)
4045 struct drm_i915_gem_madvise
*args
= data
;
4046 struct drm_i915_gem_object
*obj
;
4049 switch (args
->madv
) {
4050 case I915_MADV_DONTNEED
:
4051 case I915_MADV_WILLNEED
:
4057 ret
= i915_mutex_lock_interruptible(dev
);
4061 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
4062 if (&obj
->base
== NULL
) {
4067 if (i915_gem_obj_is_pinned(obj
)) {
4072 if (obj
->madv
!= __I915_MADV_PURGED
)
4073 obj
->madv
= args
->madv
;
4075 /* if the object is no longer attached, discard its backing storage */
4076 if (i915_gem_object_is_purgeable(obj
) && obj
->pages
== NULL
)
4077 i915_gem_object_truncate(obj
);
4079 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4082 drm_gem_object_unreference(&obj
->base
);
4084 mutex_unlock(&dev
->struct_mutex
);
4088 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4089 const struct drm_i915_gem_object_ops
*ops
)
4091 INIT_LIST_HEAD(&obj
->global_list
);
4092 INIT_LIST_HEAD(&obj
->ring_list
);
4093 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4094 INIT_LIST_HEAD(&obj
->vma_list
);
4098 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4099 obj
->madv
= I915_MADV_WILLNEED
;
4100 /* Avoid an unnecessary call to unbind on the first bind. */
4101 obj
->map_and_fenceable
= true;
4103 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4106 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4107 .get_pages
= i915_gem_object_get_pages_gtt
,
4108 .put_pages
= i915_gem_object_put_pages_gtt
,
4111 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
4114 struct drm_i915_gem_object
*obj
;
4115 struct address_space
*mapping
;
4118 obj
= i915_gem_object_alloc(dev
);
4122 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4123 i915_gem_object_free(obj
);
4127 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4128 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4129 /* 965gm cannot relocate objects above 4GiB. */
4130 mask
&= ~__GFP_HIGHMEM
;
4131 mask
|= __GFP_DMA32
;
4134 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4135 mapping_set_gfp_mask(mapping
, mask
);
4137 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4139 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4140 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4143 /* On some devices, we can have the GPU use the LLC (the CPU
4144 * cache) for about a 10% performance improvement
4145 * compared to uncached. Graphics requests other than
4146 * display scanout are coherent with the CPU in
4147 * accessing this cache. This means in this mode we
4148 * don't need to clflush on the CPU side, and on the
4149 * GPU side we only need to flush internal caches to
4150 * get data visible to the CPU.
4152 * However, we maintain the display planes as UC, and so
4153 * need to rebind when first used as such.
4155 obj
->cache_level
= I915_CACHE_LLC
;
4157 obj
->cache_level
= I915_CACHE_NONE
;
4159 trace_i915_gem_object_create(obj
);
4164 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4166 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4167 struct drm_device
*dev
= obj
->base
.dev
;
4168 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4169 struct i915_vma
*vma
, *next
;
4171 trace_i915_gem_object_destroy(obj
);
4174 i915_gem_detach_phys_object(dev
, obj
);
4176 /* NB: 0 or 1 elements */
4177 WARN_ON(!list_empty(&obj
->vma_list
) &&
4178 !list_is_singular(&obj
->vma_list
));
4179 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4183 ret
= i915_vma_unbind(vma
);
4184 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4185 bool was_interruptible
;
4187 was_interruptible
= dev_priv
->mm
.interruptible
;
4188 dev_priv
->mm
.interruptible
= false;
4190 WARN_ON(i915_vma_unbind(vma
));
4192 dev_priv
->mm
.interruptible
= was_interruptible
;
4196 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4197 * before progressing. */
4199 i915_gem_object_unpin_pages(obj
);
4201 if (WARN_ON(obj
->pages_pin_count
))
4202 obj
->pages_pin_count
= 0;
4203 i915_gem_object_put_pages(obj
);
4204 i915_gem_object_free_mmap_offset(obj
);
4205 i915_gem_object_release_stolen(obj
);
4209 if (obj
->base
.import_attach
)
4210 drm_prime_gem_destroy(&obj
->base
, NULL
);
4212 drm_gem_object_release(&obj
->base
);
4213 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4216 i915_gem_object_free(obj
);
4219 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4220 struct i915_address_space
*vm
)
4222 struct i915_vma
*vma
;
4223 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4230 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4232 WARN_ON(vma
->node
.allocated
);
4234 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4235 if (!list_empty(&vma
->exec_list
))
4238 list_del(&vma
->vma_link
);
4244 i915_gem_suspend(struct drm_device
*dev
)
4246 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4249 mutex_lock(&dev
->struct_mutex
);
4250 if (dev_priv
->ums
.mm_suspended
)
4253 ret
= i915_gpu_idle(dev
);
4257 i915_gem_retire_requests(dev
);
4259 /* Under UMS, be paranoid and evict. */
4260 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4261 i915_gem_evict_everything(dev
);
4263 i915_kernel_lost_context(dev
);
4264 i915_gem_cleanup_ringbuffer(dev
);
4266 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4267 * We need to replace this with a semaphore, or something.
4268 * And not confound ums.mm_suspended!
4270 dev_priv
->ums
.mm_suspended
= !drm_core_check_feature(dev
,
4272 mutex_unlock(&dev
->struct_mutex
);
4274 del_timer_sync(&dev_priv
->gpu_error
.hangcheck_timer
);
4275 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4276 cancel_delayed_work_sync(&dev_priv
->mm
.idle_work
);
4281 mutex_unlock(&dev
->struct_mutex
);
4285 int i915_gem_l3_remap(struct intel_ring_buffer
*ring
, int slice
)
4287 struct drm_device
*dev
= ring
->dev
;
4288 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4289 u32 reg_base
= GEN7_L3LOG_BASE
+ (slice
* 0x200);
4290 u32
*remap_info
= dev_priv
->l3_parity
.remap_info
[slice
];
4293 if (!HAS_L3_DPF(dev
) || !remap_info
)
4296 ret
= intel_ring_begin(ring
, GEN7_L3LOG_SIZE
/ 4 * 3);
4301 * Note: We do not worry about the concurrent register cacheline hang
4302 * here because no other code should access these registers other than
4303 * at initialization time.
4305 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
4306 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
4307 intel_ring_emit(ring
, reg_base
+ i
);
4308 intel_ring_emit(ring
, remap_info
[i
/4]);
4311 intel_ring_advance(ring
);
4316 void i915_gem_init_swizzling(struct drm_device
*dev
)
4318 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4320 if (INTEL_INFO(dev
)->gen
< 5 ||
4321 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4324 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4325 DISP_TILE_SURFACE_SWIZZLING
);
4330 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4332 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4333 else if (IS_GEN7(dev
))
4334 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4335 else if (IS_GEN8(dev
))
4336 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4342 intel_enable_blt(struct drm_device
*dev
)
4347 /* The blitter was dysfunctional on early prototypes */
4348 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
4349 DRM_INFO("BLT not supported on this pre-production hardware;"
4350 " graphics performance will be degraded.\n");
4357 static int i915_gem_init_rings(struct drm_device
*dev
)
4359 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4362 ret
= intel_init_render_ring_buffer(dev
);
4367 ret
= intel_init_bsd_ring_buffer(dev
);
4369 goto cleanup_render_ring
;
4372 if (intel_enable_blt(dev
)) {
4373 ret
= intel_init_blt_ring_buffer(dev
);
4375 goto cleanup_bsd_ring
;
4378 if (HAS_VEBOX(dev
)) {
4379 ret
= intel_init_vebox_ring_buffer(dev
);
4381 goto cleanup_blt_ring
;
4385 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
4387 goto cleanup_vebox_ring
;
4392 intel_cleanup_ring_buffer(&dev_priv
->ring
[VECS
]);
4394 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
4396 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
4397 cleanup_render_ring
:
4398 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
4404 i915_gem_init_hw(struct drm_device
*dev
)
4406 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4409 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
4412 if (dev_priv
->ellc_size
)
4413 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4415 if (IS_HSW_GT3(dev
))
4416 I915_WRITE(MI_PREDICATE_RESULT_2
, LOWER_SLICE_ENABLED
);
4418 I915_WRITE(MI_PREDICATE_RESULT_2
, LOWER_SLICE_DISABLED
);
4420 if (HAS_PCH_NOP(dev
)) {
4421 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4422 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4423 I915_WRITE(GEN7_MSG_CTL
, temp
);
4426 i915_gem_init_swizzling(dev
);
4428 ret
= i915_gem_init_rings(dev
);
4432 for (i
= 0; i
< NUM_L3_SLICES(dev
); i
++)
4433 i915_gem_l3_remap(&dev_priv
->ring
[RCS
], i
);
4436 * XXX: Contexts should only be initialized once. Doing a switch to the
4437 * default context switch however is something we'd like to do after
4438 * reset or thaw (the latter may not actually be necessary for HW, but
4439 * goes with our code better). Context switching requires rings (for
4440 * the do_switch), but before enabling PPGTT. So don't move this.
4442 ret
= i915_gem_context_enable(dev_priv
);
4444 DRM_ERROR("Context enable failed %d\n", ret
);
4451 i915_gem_cleanup_ringbuffer(dev
);
4455 int i915_gem_init(struct drm_device
*dev
)
4457 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4460 mutex_lock(&dev
->struct_mutex
);
4462 if (IS_VALLEYVIEW(dev
)) {
4463 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4464 I915_WRITE(VLV_GTLC_WAKE_CTRL
, 1);
4465 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS
) & 1) == 1, 10))
4466 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4469 i915_gem_init_global_gtt(dev
);
4471 ret
= i915_gem_context_init(dev
);
4475 ret
= i915_gem_init_hw(dev
);
4476 mutex_unlock(&dev
->struct_mutex
);
4478 WARN_ON(dev_priv
->mm
.aliasing_ppgtt
);
4479 i915_gem_context_fini(dev
);
4480 drm_mm_takedown(&dev_priv
->gtt
.base
.mm
);
4484 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4485 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4486 dev_priv
->dri1
.allow_batchbuffer
= 1;
4491 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4493 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4494 struct intel_ring_buffer
*ring
;
4497 for_each_ring(ring
, dev_priv
, i
)
4498 intel_cleanup_ring_buffer(ring
);
4502 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4503 struct drm_file
*file_priv
)
4505 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4508 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4511 if (i915_reset_in_progress(&dev_priv
->gpu_error
)) {
4512 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4513 atomic_set(&dev_priv
->gpu_error
.reset_counter
, 0);
4516 mutex_lock(&dev
->struct_mutex
);
4517 dev_priv
->ums
.mm_suspended
= 0;
4519 ret
= i915_gem_init_hw(dev
);
4521 mutex_unlock(&dev
->struct_mutex
);
4525 BUG_ON(!list_empty(&dev_priv
->gtt
.base
.active_list
));
4526 mutex_unlock(&dev
->struct_mutex
);
4528 ret
= drm_irq_install(dev
);
4530 goto cleanup_ringbuffer
;
4535 mutex_lock(&dev
->struct_mutex
);
4536 i915_gem_cleanup_ringbuffer(dev
);
4537 dev_priv
->ums
.mm_suspended
= 1;
4538 mutex_unlock(&dev
->struct_mutex
);
4544 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4545 struct drm_file
*file_priv
)
4547 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4550 drm_irq_uninstall(dev
);
4552 return i915_gem_suspend(dev
);
4556 i915_gem_lastclose(struct drm_device
*dev
)
4560 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4563 ret
= i915_gem_suspend(dev
);
4565 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4569 init_ring_lists(struct intel_ring_buffer
*ring
)
4571 INIT_LIST_HEAD(&ring
->active_list
);
4572 INIT_LIST_HEAD(&ring
->request_list
);
4575 static void i915_init_vm(struct drm_i915_private
*dev_priv
,
4576 struct i915_address_space
*vm
)
4578 vm
->dev
= dev_priv
->dev
;
4579 INIT_LIST_HEAD(&vm
->active_list
);
4580 INIT_LIST_HEAD(&vm
->inactive_list
);
4581 INIT_LIST_HEAD(&vm
->global_link
);
4582 list_add(&vm
->global_link
, &dev_priv
->vm_list
);
4586 i915_gem_load(struct drm_device
*dev
)
4588 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4592 kmem_cache_create("i915_gem_object",
4593 sizeof(struct drm_i915_gem_object
), 0,
4597 INIT_LIST_HEAD(&dev_priv
->vm_list
);
4598 i915_init_vm(dev_priv
, &dev_priv
->gtt
.base
);
4600 INIT_LIST_HEAD(&dev_priv
->context_list
);
4601 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4602 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4603 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4604 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4605 init_ring_lists(&dev_priv
->ring
[i
]);
4606 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
4607 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4608 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4609 i915_gem_retire_work_handler
);
4610 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
4611 i915_gem_idle_work_handler
);
4612 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
4614 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4616 I915_WRITE(MI_ARB_STATE
,
4617 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
4620 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4622 /* Old X drivers will take 0-2 for front, back, depth buffers */
4623 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4624 dev_priv
->fence_reg_start
= 3;
4626 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
))
4627 dev_priv
->num_fence_regs
= 32;
4628 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4629 dev_priv
->num_fence_regs
= 16;
4631 dev_priv
->num_fence_regs
= 8;
4633 /* Initialize fence registers to zero */
4634 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4635 i915_gem_restore_fences(dev
);
4637 i915_gem_detect_bit_6_swizzle(dev
);
4638 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4640 dev_priv
->mm
.interruptible
= true;
4642 dev_priv
->mm
.inactive_shrinker
.scan_objects
= i915_gem_inactive_scan
;
4643 dev_priv
->mm
.inactive_shrinker
.count_objects
= i915_gem_inactive_count
;
4644 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
4645 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
4649 * Create a physically contiguous memory object for this object
4650 * e.g. for cursor + overlay regs
4652 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4653 int id
, int size
, int align
)
4655 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4656 struct drm_i915_gem_phys_object
*phys_obj
;
4659 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4662 phys_obj
= kzalloc(sizeof(*phys_obj
), GFP_KERNEL
);
4668 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4669 if (!phys_obj
->handle
) {
4674 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4677 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4685 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4687 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4688 struct drm_i915_gem_phys_object
*phys_obj
;
4690 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4693 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4694 if (phys_obj
->cur_obj
) {
4695 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4699 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4701 drm_pci_free(dev
, phys_obj
->handle
);
4703 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4706 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4710 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4711 i915_gem_free_phys_object(dev
, i
);
4714 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4715 struct drm_i915_gem_object
*obj
)
4717 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4724 vaddr
= obj
->phys_obj
->handle
->vaddr
;
4726 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4727 for (i
= 0; i
< page_count
; i
++) {
4728 struct page
*page
= shmem_read_mapping_page(mapping
, i
);
4729 if (!IS_ERR(page
)) {
4730 char *dst
= kmap_atomic(page
);
4731 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
4734 drm_clflush_pages(&page
, 1);
4736 set_page_dirty(page
);
4737 mark_page_accessed(page
);
4738 page_cache_release(page
);
4741 i915_gem_chipset_flush(dev
);
4743 obj
->phys_obj
->cur_obj
= NULL
;
4744 obj
->phys_obj
= NULL
;
4748 i915_gem_attach_phys_object(struct drm_device
*dev
,
4749 struct drm_i915_gem_object
*obj
,
4753 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4754 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4759 if (id
> I915_MAX_PHYS_OBJECT
)
4762 if (obj
->phys_obj
) {
4763 if (obj
->phys_obj
->id
== id
)
4765 i915_gem_detach_phys_object(dev
, obj
);
4768 /* create a new object */
4769 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4770 ret
= i915_gem_init_phys_object(dev
, id
,
4771 obj
->base
.size
, align
);
4773 DRM_ERROR("failed to init phys object %d size: %zu\n",
4774 id
, obj
->base
.size
);
4779 /* bind to the object */
4780 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4781 obj
->phys_obj
->cur_obj
= obj
;
4783 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4785 for (i
= 0; i
< page_count
; i
++) {
4789 page
= shmem_read_mapping_page(mapping
, i
);
4791 return PTR_ERR(page
);
4793 src
= kmap_atomic(page
);
4794 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4795 memcpy(dst
, src
, PAGE_SIZE
);
4798 mark_page_accessed(page
);
4799 page_cache_release(page
);
4806 i915_gem_phys_pwrite(struct drm_device
*dev
,
4807 struct drm_i915_gem_object
*obj
,
4808 struct drm_i915_gem_pwrite
*args
,
4809 struct drm_file
*file_priv
)
4811 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
4812 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
4814 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
4815 unsigned long unwritten
;
4817 /* The physical object once assigned is fixed for the lifetime
4818 * of the obj, so we can safely drop the lock and continue
4821 mutex_unlock(&dev
->struct_mutex
);
4822 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
4823 mutex_lock(&dev
->struct_mutex
);
4828 i915_gem_chipset_flush(dev
);
4832 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4834 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4836 cancel_delayed_work_sync(&file_priv
->mm
.idle_work
);
4838 /* Clean up our request list when the client is going away, so that
4839 * later retire_requests won't dereference our soon-to-be-gone
4842 spin_lock(&file_priv
->mm
.lock
);
4843 while (!list_empty(&file_priv
->mm
.request_list
)) {
4844 struct drm_i915_gem_request
*request
;
4846 request
= list_first_entry(&file_priv
->mm
.request_list
,
4847 struct drm_i915_gem_request
,
4849 list_del(&request
->client_list
);
4850 request
->file_priv
= NULL
;
4852 spin_unlock(&file_priv
->mm
.lock
);
4856 i915_gem_file_idle_work_handler(struct work_struct
*work
)
4858 struct drm_i915_file_private
*file_priv
=
4859 container_of(work
, typeof(*file_priv
), mm
.idle_work
.work
);
4861 atomic_set(&file_priv
->rps_wait_boost
, false);
4864 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
4866 struct drm_i915_file_private
*file_priv
;
4869 DRM_DEBUG_DRIVER("\n");
4871 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
4875 file
->driver_priv
= file_priv
;
4876 file_priv
->dev_priv
= dev
->dev_private
;
4878 spin_lock_init(&file_priv
->mm
.lock
);
4879 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
4880 INIT_DELAYED_WORK(&file_priv
->mm
.idle_work
,
4881 i915_gem_file_idle_work_handler
);
4883 ret
= i915_gem_context_open(dev
, file
);
4890 static bool mutex_is_locked_by(struct mutex
*mutex
, struct task_struct
*task
)
4892 if (!mutex_is_locked(mutex
))
4895 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4896 return mutex
->owner
== task
;
4898 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4903 static unsigned long
4904 i915_gem_inactive_count(struct shrinker
*shrinker
, struct shrink_control
*sc
)
4906 struct drm_i915_private
*dev_priv
=
4907 container_of(shrinker
,
4908 struct drm_i915_private
,
4909 mm
.inactive_shrinker
);
4910 struct drm_device
*dev
= dev_priv
->dev
;
4911 struct drm_i915_gem_object
*obj
;
4913 unsigned long count
;
4915 if (!mutex_trylock(&dev
->struct_mutex
)) {
4916 if (!mutex_is_locked_by(&dev
->struct_mutex
, current
))
4919 if (dev_priv
->mm
.shrinker_no_lock_stealing
)
4926 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
)
4927 if (obj
->pages_pin_count
== 0)
4928 count
+= obj
->base
.size
>> PAGE_SHIFT
;
4930 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
4934 if (!i915_gem_obj_is_pinned(obj
) && obj
->pages_pin_count
== 0)
4935 count
+= obj
->base
.size
>> PAGE_SHIFT
;
4939 mutex_unlock(&dev
->struct_mutex
);
4944 /* All the new VM stuff */
4945 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
4946 struct i915_address_space
*vm
)
4948 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
4949 struct i915_vma
*vma
;
4951 if (!dev_priv
->mm
.aliasing_ppgtt
||
4952 vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
)
4953 vm
= &dev_priv
->gtt
.base
;
4955 BUG_ON(list_empty(&o
->vma_list
));
4956 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
4958 return vma
->node
.start
;
4964 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
4965 struct i915_address_space
*vm
)
4967 struct i915_vma
*vma
;
4969 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
4970 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
4976 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
4978 struct i915_vma
*vma
;
4980 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
4981 if (drm_mm_node_allocated(&vma
->node
))
4987 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
4988 struct i915_address_space
*vm
)
4990 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
4991 struct i915_vma
*vma
;
4993 if (!dev_priv
->mm
.aliasing_ppgtt
||
4994 vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
)
4995 vm
= &dev_priv
->gtt
.base
;
4997 BUG_ON(list_empty(&o
->vma_list
));
4999 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5001 return vma
->node
.size
;
5006 static unsigned long
5007 i915_gem_inactive_scan(struct shrinker
*shrinker
, struct shrink_control
*sc
)
5009 struct drm_i915_private
*dev_priv
=
5010 container_of(shrinker
,
5011 struct drm_i915_private
,
5012 mm
.inactive_shrinker
);
5013 struct drm_device
*dev
= dev_priv
->dev
;
5014 unsigned long freed
;
5017 if (!mutex_trylock(&dev
->struct_mutex
)) {
5018 if (!mutex_is_locked_by(&dev
->struct_mutex
, current
))
5021 if (dev_priv
->mm
.shrinker_no_lock_stealing
)
5027 freed
= i915_gem_purge(dev_priv
, sc
->nr_to_scan
);
5028 if (freed
< sc
->nr_to_scan
)
5029 freed
+= __i915_gem_shrink(dev_priv
,
5030 sc
->nr_to_scan
- freed
,
5032 if (freed
< sc
->nr_to_scan
)
5033 freed
+= i915_gem_shrink_all(dev_priv
);
5036 mutex_unlock(&dev
->struct_mutex
);
5041 struct i915_vma
*i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
)
5043 struct i915_vma
*vma
;
5045 if (WARN_ON(list_empty(&obj
->vma_list
)))
5048 vma
= list_first_entry(&obj
->vma_list
, typeof(*vma
), vma_link
);
5049 if (vma
->vm
!= obj_to_ggtt(obj
))