2 * Copyright © 2011-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded its state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
89 #include <drm/i915_drm.h>
91 #include "i915_trace.h"
93 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
95 /* This is a HW constraint. The value below is the largest known requirement
96 * I've seen in a spec to date, and that was a workaround for a non-shipping
97 * part. It should be safe to decrease this, but it's more future proof as is.
99 #define GEN6_CONTEXT_ALIGN (64<<10)
100 #define GEN7_CONTEXT_ALIGN 4096
102 static size_t get_context_alignment(struct drm_i915_private
*dev_priv
)
104 if (IS_GEN6(dev_priv
))
105 return GEN6_CONTEXT_ALIGN
;
107 return GEN7_CONTEXT_ALIGN
;
110 static int get_context_size(struct drm_i915_private
*dev_priv
)
115 switch (INTEL_GEN(dev_priv
)) {
117 reg
= I915_READ(CXT_SIZE
);
118 ret
= GEN6_CXT_TOTAL_SIZE(reg
) * 64;
121 reg
= I915_READ(GEN7_CXT_SIZE
);
122 if (IS_HASWELL(dev_priv
))
123 ret
= HSW_CXT_TOTAL_SIZE
;
125 ret
= GEN7_CXT_TOTAL_SIZE(reg
) * 64;
128 ret
= GEN8_CXT_TOTAL_SIZE
;
137 void i915_gem_context_free(struct kref
*ctx_ref
)
139 struct i915_gem_context
*ctx
= container_of(ctx_ref
, typeof(*ctx
), ref
);
142 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
143 trace_i915_context_free(ctx
);
144 GEM_BUG_ON(!ctx
->closed
);
146 i915_ppgtt_put(ctx
->ppgtt
);
148 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
149 struct intel_context
*ce
= &ctx
->engine
[i
];
154 WARN_ON(ce
->pin_count
);
156 intel_ring_free(ce
->ring
);
158 i915_vma_put(ce
->state
);
162 list_del(&ctx
->link
);
164 ida_simple_remove(&ctx
->i915
->context_hw_ida
, ctx
->hw_id
);
168 struct drm_i915_gem_object
*
169 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
)
171 struct drm_i915_gem_object
*obj
;
174 lockdep_assert_held(&dev
->struct_mutex
);
176 obj
= i915_gem_object_create(dev
, size
);
181 * Try to make the context utilize L3 as well as LLC.
183 * On VLV we don't have L3 controls in the PTEs so we
184 * shouldn't touch the cache level, especially as that
185 * would make the object snooped which might have a
186 * negative performance impact.
188 * Snooping is required on non-llc platforms in execlist
189 * mode, but since all GGTT accesses use PAT entry 0 we
190 * get snooping anyway regardless of cache_level.
192 * This is only applicable for Ivy Bridge devices since
193 * later platforms don't have L3 control bits in the PTE.
195 if (IS_IVYBRIDGE(dev
)) {
196 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_L3_LLC
);
197 /* Failure shouldn't ever happen this early */
199 i915_gem_object_put(obj
);
207 static void i915_ppgtt_close(struct i915_address_space
*vm
)
209 struct list_head
*phases
[] = {
216 GEM_BUG_ON(vm
->closed
);
219 for (phase
= phases
; *phase
; phase
++) {
220 struct i915_vma
*vma
, *vn
;
222 list_for_each_entry_safe(vma
, vn
, *phase
, vm_link
)
223 if (!i915_vma_is_closed(vma
))
228 static void context_close(struct i915_gem_context
*ctx
)
230 GEM_BUG_ON(ctx
->closed
);
233 i915_ppgtt_close(&ctx
->ppgtt
->base
);
234 ctx
->file_priv
= ERR_PTR(-EBADF
);
235 i915_gem_context_put(ctx
);
238 static int assign_hw_id(struct drm_i915_private
*dev_priv
, unsigned *out
)
242 ret
= ida_simple_get(&dev_priv
->context_hw_ida
,
243 0, MAX_CONTEXT_HW_ID
, GFP_KERNEL
);
245 /* Contexts are only released when no longer active.
246 * Flush any pending retires to hopefully release some
247 * stale contexts and try again.
249 i915_gem_retire_requests(dev_priv
);
250 ret
= ida_simple_get(&dev_priv
->context_hw_ida
,
251 0, MAX_CONTEXT_HW_ID
, GFP_KERNEL
);
260 static struct i915_gem_context
*
261 __create_hw_context(struct drm_device
*dev
,
262 struct drm_i915_file_private
*file_priv
)
264 struct drm_i915_private
*dev_priv
= to_i915(dev
);
265 struct i915_gem_context
*ctx
;
268 ctx
= kzalloc(sizeof(*ctx
), GFP_KERNEL
);
270 return ERR_PTR(-ENOMEM
);
272 ret
= assign_hw_id(dev_priv
, &ctx
->hw_id
);
278 kref_init(&ctx
->ref
);
279 list_add_tail(&ctx
->link
, &dev_priv
->context_list
);
280 ctx
->i915
= dev_priv
;
282 ctx
->ggtt_alignment
= get_context_alignment(dev_priv
);
284 if (dev_priv
->hw_context_size
) {
285 struct drm_i915_gem_object
*obj
;
286 struct i915_vma
*vma
;
288 obj
= i915_gem_alloc_context_obj(dev
,
289 dev_priv
->hw_context_size
);
295 vma
= i915_vma_create(obj
, &dev_priv
->ggtt
.base
, NULL
);
297 i915_gem_object_put(obj
);
302 ctx
->engine
[RCS
].state
= vma
;
305 /* Default context will never have a file_priv */
306 if (file_priv
!= NULL
) {
307 ret
= idr_alloc(&file_priv
->context_idr
, ctx
,
308 DEFAULT_CONTEXT_HANDLE
, 0, GFP_KERNEL
);
312 ret
= DEFAULT_CONTEXT_HANDLE
;
314 ctx
->file_priv
= file_priv
;
316 ctx
->pid
= get_task_pid(current
, PIDTYPE_PID
);
318 ctx
->user_handle
= ret
;
319 /* NB: Mark all slices as needing a remap so that when the context first
320 * loads it will restore whatever remap state already exists. If there
321 * is no remap info, it will be a NOP. */
322 ctx
->remap_slice
= ALL_L3_SLICES(dev_priv
);
324 ctx
->hang_stats
.ban_period_seconds
= DRM_I915_CTX_BAN_PERIOD
;
325 ctx
->ring_size
= 4 * PAGE_SIZE
;
326 ctx
->desc_template
= GEN8_CTX_ADDRESSING_MODE(dev_priv
) <<
327 GEN8_CTX_ADDRESSING_MODE_SHIFT
;
328 ATOMIC_INIT_NOTIFIER_HEAD(&ctx
->status_notifier
);
338 * The default context needs to exist per ring that uses contexts. It stores the
339 * context state of the GPU for applications that don't utilize HW contexts, as
340 * well as an idle case.
342 static struct i915_gem_context
*
343 i915_gem_create_context(struct drm_device
*dev
,
344 struct drm_i915_file_private
*file_priv
)
346 struct i915_gem_context
*ctx
;
348 lockdep_assert_held(&dev
->struct_mutex
);
350 ctx
= __create_hw_context(dev
, file_priv
);
354 if (USES_FULL_PPGTT(dev
)) {
355 struct i915_hw_ppgtt
*ppgtt
=
356 i915_ppgtt_create(to_i915(dev
), file_priv
);
359 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
361 idr_remove(&file_priv
->context_idr
, ctx
->user_handle
);
363 return ERR_CAST(ppgtt
);
369 trace_i915_context_create(ctx
);
375 * i915_gem_context_create_gvt - create a GVT GEM context
378 * This function is used to create a GVT specific GEM context.
381 * pointer to i915_gem_context on success, error pointer if failed
384 struct i915_gem_context
*
385 i915_gem_context_create_gvt(struct drm_device
*dev
)
387 struct i915_gem_context
*ctx
;
390 if (!IS_ENABLED(CONFIG_DRM_I915_GVT
))
391 return ERR_PTR(-ENODEV
);
393 ret
= i915_mutex_lock_interruptible(dev
);
397 ctx
= i915_gem_create_context(dev
, NULL
);
401 ctx
->execlists_force_single_submission
= true;
402 ctx
->ring_size
= 512 * PAGE_SIZE
; /* Max ring buffer size */
404 mutex_unlock(&dev
->struct_mutex
);
408 static void i915_gem_context_unpin(struct i915_gem_context
*ctx
,
409 struct intel_engine_cs
*engine
)
411 if (i915
.enable_execlists
) {
412 intel_lr_context_unpin(ctx
, engine
);
414 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
417 i915_vma_unpin(ce
->state
);
419 i915_gem_context_put(ctx
);
423 int i915_gem_context_init(struct drm_device
*dev
)
425 struct drm_i915_private
*dev_priv
= to_i915(dev
);
426 struct i915_gem_context
*ctx
;
428 /* Init should only be called once per module load. Eventually the
429 * restriction on the context_disabled check can be loosened. */
430 if (WARN_ON(dev_priv
->kernel_context
))
433 if (intel_vgpu_active(dev_priv
) &&
434 HAS_LOGICAL_RING_CONTEXTS(dev_priv
)) {
435 if (!i915
.enable_execlists
) {
436 DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
441 /* Using the simple ida interface, the max is limited by sizeof(int) */
442 BUILD_BUG_ON(MAX_CONTEXT_HW_ID
> INT_MAX
);
443 ida_init(&dev_priv
->context_hw_ida
);
445 if (i915
.enable_execlists
) {
446 /* NB: intentionally left blank. We will allocate our own
447 * backing objects as we need them, thank you very much */
448 dev_priv
->hw_context_size
= 0;
449 } else if (HAS_HW_CONTEXTS(dev_priv
)) {
450 dev_priv
->hw_context_size
=
451 round_up(get_context_size(dev_priv
), 4096);
452 if (dev_priv
->hw_context_size
> (1<<20)) {
453 DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
454 dev_priv
->hw_context_size
);
455 dev_priv
->hw_context_size
= 0;
459 ctx
= i915_gem_create_context(dev
, NULL
);
461 DRM_ERROR("Failed to create default global context (error %ld)\n",
466 dev_priv
->kernel_context
= ctx
;
468 DRM_DEBUG_DRIVER("%s context support initialized\n",
469 i915
.enable_execlists
? "LR" :
470 dev_priv
->hw_context_size
? "HW" : "fake");
474 void i915_gem_context_lost(struct drm_i915_private
*dev_priv
)
476 struct intel_engine_cs
*engine
;
478 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
480 for_each_engine(engine
, dev_priv
) {
481 if (engine
->last_context
) {
482 i915_gem_context_unpin(engine
->last_context
, engine
);
483 engine
->last_context
= NULL
;
487 /* Force the GPU state to be restored on enabling */
488 if (!i915
.enable_execlists
) {
489 struct i915_gem_context
*ctx
;
491 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
492 if (!i915_gem_context_is_default(ctx
))
495 for_each_engine(engine
, dev_priv
)
496 ctx
->engine
[engine
->id
].initialised
= false;
498 ctx
->remap_slice
= ALL_L3_SLICES(dev_priv
);
501 for_each_engine(engine
, dev_priv
) {
502 struct intel_context
*kce
=
503 &dev_priv
->kernel_context
->engine
[engine
->id
];
505 kce
->initialised
= true;
510 void i915_gem_context_fini(struct drm_device
*dev
)
512 struct drm_i915_private
*dev_priv
= to_i915(dev
);
513 struct i915_gem_context
*dctx
= dev_priv
->kernel_context
;
515 lockdep_assert_held(&dev
->struct_mutex
);
518 dev_priv
->kernel_context
= NULL
;
520 ida_destroy(&dev_priv
->context_hw_ida
);
523 static int context_idr_cleanup(int id
, void *p
, void *data
)
525 struct i915_gem_context
*ctx
= p
;
531 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
)
533 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
534 struct i915_gem_context
*ctx
;
536 idr_init(&file_priv
->context_idr
);
538 mutex_lock(&dev
->struct_mutex
);
539 ctx
= i915_gem_create_context(dev
, file_priv
);
540 mutex_unlock(&dev
->struct_mutex
);
543 idr_destroy(&file_priv
->context_idr
);
550 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
)
552 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
554 lockdep_assert_held(&dev
->struct_mutex
);
556 idr_for_each(&file_priv
->context_idr
, context_idr_cleanup
, NULL
);
557 idr_destroy(&file_priv
->context_idr
);
561 mi_set_context(struct drm_i915_gem_request
*req
, u32 hw_flags
)
563 struct drm_i915_private
*dev_priv
= req
->i915
;
564 struct intel_ring
*ring
= req
->ring
;
565 struct intel_engine_cs
*engine
= req
->engine
;
566 u32 flags
= hw_flags
| MI_MM_SPACE_GTT
;
567 const int num_rings
=
568 /* Use an extended w/a on ivb+ if signalling from other rings */
570 INTEL_INFO(dev_priv
)->num_rings
- 1 :
574 /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
575 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
576 * explicitly, so we rely on the value at ring init, stored in
577 * itlb_before_ctx_switch.
579 if (IS_GEN6(dev_priv
)) {
580 ret
= engine
->emit_flush(req
, EMIT_INVALIDATE
);
585 /* These flags are for resource streamer on HSW+ */
586 if (IS_HASWELL(dev_priv
) || INTEL_GEN(dev_priv
) >= 8)
587 flags
|= (HSW_MI_RS_SAVE_STATE_EN
| HSW_MI_RS_RESTORE_STATE_EN
);
588 else if (INTEL_GEN(dev_priv
) < 8)
589 flags
|= (MI_SAVE_EXT_STATE_EN
| MI_RESTORE_EXT_STATE_EN
);
593 if (INTEL_GEN(dev_priv
) >= 7)
594 len
+= 2 + (num_rings
? 4*num_rings
+ 6 : 0);
596 ret
= intel_ring_begin(req
, len
);
600 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
601 if (INTEL_GEN(dev_priv
) >= 7) {
602 intel_ring_emit(ring
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
604 struct intel_engine_cs
*signaller
;
606 intel_ring_emit(ring
,
607 MI_LOAD_REGISTER_IMM(num_rings
));
608 for_each_engine(signaller
, dev_priv
) {
609 if (signaller
== engine
)
612 intel_ring_emit_reg(ring
,
613 RING_PSMI_CTL(signaller
->mmio_base
));
614 intel_ring_emit(ring
,
615 _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE
));
620 intel_ring_emit(ring
, MI_NOOP
);
621 intel_ring_emit(ring
, MI_SET_CONTEXT
);
622 intel_ring_emit(ring
,
623 i915_ggtt_offset(req
->ctx
->engine
[RCS
].state
) | flags
);
625 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
626 * WaMiSetContext_Hang:snb,ivb,vlv
628 intel_ring_emit(ring
, MI_NOOP
);
630 if (INTEL_GEN(dev_priv
) >= 7) {
632 struct intel_engine_cs
*signaller
;
633 i915_reg_t last_reg
= {}; /* keep gcc quiet */
635 intel_ring_emit(ring
,
636 MI_LOAD_REGISTER_IMM(num_rings
));
637 for_each_engine(signaller
, dev_priv
) {
638 if (signaller
== engine
)
641 last_reg
= RING_PSMI_CTL(signaller
->mmio_base
);
642 intel_ring_emit_reg(ring
, last_reg
);
643 intel_ring_emit(ring
,
644 _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE
));
647 /* Insert a delay before the next switch! */
648 intel_ring_emit(ring
,
649 MI_STORE_REGISTER_MEM
|
650 MI_SRM_LRM_GLOBAL_GTT
);
651 intel_ring_emit_reg(ring
, last_reg
);
652 intel_ring_emit(ring
,
653 i915_ggtt_offset(engine
->scratch
));
654 intel_ring_emit(ring
, MI_NOOP
);
656 intel_ring_emit(ring
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
659 intel_ring_advance(ring
);
664 static int remap_l3(struct drm_i915_gem_request
*req
, int slice
)
666 u32
*remap_info
= req
->i915
->l3_parity
.remap_info
[slice
];
667 struct intel_ring
*ring
= req
->ring
;
673 ret
= intel_ring_begin(req
, GEN7_L3LOG_SIZE
/4 * 2 + 2);
678 * Note: We do not worry about the concurrent register cacheline hang
679 * here because no other code should access these registers other than
680 * at initialization time.
682 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE
/4));
683 for (i
= 0; i
< GEN7_L3LOG_SIZE
/4; i
++) {
684 intel_ring_emit_reg(ring
, GEN7_L3LOG(slice
, i
));
685 intel_ring_emit(ring
, remap_info
[i
]);
687 intel_ring_emit(ring
, MI_NOOP
);
688 intel_ring_advance(ring
);
693 static inline bool skip_rcs_switch(struct i915_hw_ppgtt
*ppgtt
,
694 struct intel_engine_cs
*engine
,
695 struct i915_gem_context
*to
)
700 if (!to
->engine
[RCS
].initialised
)
703 if (ppgtt
&& (intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
))
706 return to
== engine
->last_context
;
710 needs_pd_load_pre(struct i915_hw_ppgtt
*ppgtt
,
711 struct intel_engine_cs
*engine
,
712 struct i915_gem_context
*to
)
717 /* Always load the ppgtt on first use */
718 if (!engine
->last_context
)
721 /* Same context without new entries, skip */
722 if (engine
->last_context
== to
&&
723 !(intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
))
726 if (engine
->id
!= RCS
)
729 if (INTEL_GEN(engine
->i915
) < 8)
736 needs_pd_load_post(struct i915_hw_ppgtt
*ppgtt
,
737 struct i915_gem_context
*to
,
743 if (!IS_GEN8(to
->i915
))
746 if (hw_flags
& MI_RESTORE_INHIBIT
)
752 static int do_rcs_switch(struct drm_i915_gem_request
*req
)
754 struct i915_gem_context
*to
= req
->ctx
;
755 struct intel_engine_cs
*engine
= req
->engine
;
756 struct i915_hw_ppgtt
*ppgtt
= to
->ppgtt
?: req
->i915
->mm
.aliasing_ppgtt
;
757 struct i915_vma
*vma
= to
->engine
[RCS
].state
;
758 struct i915_gem_context
*from
;
762 if (skip_rcs_switch(ppgtt
, engine
, to
))
765 /* Clear this page out of any CPU caches for coherent swap-in/out. */
766 if (!(vma
->flags
& I915_VMA_GLOBAL_BIND
)) {
767 ret
= i915_gem_object_set_to_gtt_domain(vma
->obj
, false);
772 /* Trying to pin first makes error handling easier. */
773 ret
= i915_vma_pin(vma
, 0, to
->ggtt_alignment
, PIN_GLOBAL
);
778 * Pin can switch back to the default context if we end up calling into
779 * evict_everything - as a last ditch gtt defrag effort that also
780 * switches to the default context. Hence we need to reload from here.
782 * XXX: Doing so is painfully broken!
784 from
= engine
->last_context
;
786 if (needs_pd_load_pre(ppgtt
, engine
, to
)) {
787 /* Older GENs and non render rings still want the load first,
788 * "PP_DCLV followed by PP_DIR_BASE register through Load
789 * Register Immediate commands in Ring Buffer before submitting
791 trace_switch_mm(engine
, to
);
792 ret
= ppgtt
->switch_mm(ppgtt
, req
);
797 if (!to
->engine
[RCS
].initialised
|| i915_gem_context_is_default(to
))
798 /* NB: If we inhibit the restore, the context is not allowed to
799 * die because future work may end up depending on valid address
800 * space. This means we must enforce that a page table load
801 * occur when this occurs. */
802 hw_flags
= MI_RESTORE_INHIBIT
;
803 else if (ppgtt
&& intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
)
804 hw_flags
= MI_FORCE_RESTORE
;
808 if (to
!= from
|| (hw_flags
& MI_FORCE_RESTORE
)) {
809 ret
= mi_set_context(req
, hw_flags
);
814 /* The backing object for the context is done after switching to the
815 * *next* context. Therefore we cannot retire the previous context until
816 * the next context has already started running. In fact, the below code
817 * is a bit suboptimal because the retiring can occur simply after the
818 * MI_SET_CONTEXT instead of when the next seqno has completed.
821 /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
822 * whole damn pipeline, we don't need to explicitly mark the
823 * object dirty. The only exception is that the context must be
824 * correct in case the object gets swapped out. Ideally we'd be
825 * able to defer doing this until we know the object would be
826 * swapped, but there is no way to do that yet.
828 i915_vma_move_to_active(from
->engine
[RCS
].state
, req
, 0);
829 /* state is kept alive until the next request */
830 i915_vma_unpin(from
->engine
[RCS
].state
);
831 i915_gem_context_put(from
);
833 engine
->last_context
= i915_gem_context_get(to
);
835 /* GEN8 does *not* require an explicit reload if the PDPs have been
836 * setup, and we do not wish to move them.
838 if (needs_pd_load_post(ppgtt
, to
, hw_flags
)) {
839 trace_switch_mm(engine
, to
);
840 ret
= ppgtt
->switch_mm(ppgtt
, req
);
841 /* The hardware context switch is emitted, but we haven't
842 * actually changed the state - so it's probably safe to bail
843 * here. Still, let the user know something dangerous has
851 ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(engine
);
853 for (i
= 0; i
< MAX_L3_SLICES
; i
++) {
854 if (!(to
->remap_slice
& (1<<i
)))
857 ret
= remap_l3(req
, i
);
861 to
->remap_slice
&= ~(1<<i
);
864 if (!to
->engine
[RCS
].initialised
) {
865 if (engine
->init_context
) {
866 ret
= engine
->init_context(req
);
870 to
->engine
[RCS
].initialised
= true;
881 * i915_switch_context() - perform a GPU context switch.
882 * @req: request for which we'll execute the context switch
884 * The context life cycle is simple. The context refcount is incremented and
885 * decremented by 1 and create and destroy. If the context is in use by the GPU,
886 * it will have a refcount > 1. This allows us to destroy the context abstract
887 * object while letting the normal object tracking destroy the backing BO.
889 * This function should not be used in execlists mode. Instead the context is
890 * switched by writing to the ELSP and requests keep a reference to their
893 int i915_switch_context(struct drm_i915_gem_request
*req
)
895 struct intel_engine_cs
*engine
= req
->engine
;
897 lockdep_assert_held(&req
->i915
->drm
.struct_mutex
);
898 if (i915
.enable_execlists
)
901 if (!req
->ctx
->engine
[engine
->id
].state
) {
902 struct i915_gem_context
*to
= req
->ctx
;
903 struct i915_hw_ppgtt
*ppgtt
=
904 to
->ppgtt
?: req
->i915
->mm
.aliasing_ppgtt
;
906 if (needs_pd_load_pre(ppgtt
, engine
, to
)) {
909 trace_switch_mm(engine
, to
);
910 ret
= ppgtt
->switch_mm(ppgtt
, req
);
914 ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(engine
);
917 if (to
!= engine
->last_context
) {
918 if (engine
->last_context
)
919 i915_gem_context_put(engine
->last_context
);
920 engine
->last_context
= i915_gem_context_get(to
);
926 return do_rcs_switch(req
);
929 int i915_gem_switch_to_kernel_context(struct drm_i915_private
*dev_priv
)
931 struct intel_engine_cs
*engine
;
933 for_each_engine(engine
, dev_priv
) {
934 struct drm_i915_gem_request
*req
;
937 if (engine
->last_context
== NULL
)
940 if (engine
->last_context
== dev_priv
->kernel_context
)
943 req
= i915_gem_request_alloc(engine
, dev_priv
->kernel_context
);
947 ret
= i915_switch_context(req
);
948 i915_add_request_no_flush(req
);
956 static bool contexts_enabled(struct drm_device
*dev
)
958 return i915
.enable_execlists
|| to_i915(dev
)->hw_context_size
;
961 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
962 struct drm_file
*file
)
964 struct drm_i915_gem_context_create
*args
= data
;
965 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
966 struct i915_gem_context
*ctx
;
969 if (!contexts_enabled(dev
))
975 ret
= i915_mutex_lock_interruptible(dev
);
979 ctx
= i915_gem_create_context(dev
, file_priv
);
980 mutex_unlock(&dev
->struct_mutex
);
984 args
->ctx_id
= ctx
->user_handle
;
985 DRM_DEBUG_DRIVER("HW context %d created\n", args
->ctx_id
);
990 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
991 struct drm_file
*file
)
993 struct drm_i915_gem_context_destroy
*args
= data
;
994 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
995 struct i915_gem_context
*ctx
;
1001 if (args
->ctx_id
== DEFAULT_CONTEXT_HANDLE
)
1004 ret
= i915_mutex_lock_interruptible(dev
);
1008 ctx
= i915_gem_context_lookup(file_priv
, args
->ctx_id
);
1010 mutex_unlock(&dev
->struct_mutex
);
1011 return PTR_ERR(ctx
);
1014 idr_remove(&file_priv
->context_idr
, ctx
->user_handle
);
1016 mutex_unlock(&dev
->struct_mutex
);
1018 DRM_DEBUG_DRIVER("HW context %d destroyed\n", args
->ctx_id
);
1022 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
1023 struct drm_file
*file
)
1025 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1026 struct drm_i915_gem_context_param
*args
= data
;
1027 struct i915_gem_context
*ctx
;
1030 ret
= i915_mutex_lock_interruptible(dev
);
1034 ctx
= i915_gem_context_lookup(file_priv
, args
->ctx_id
);
1036 mutex_unlock(&dev
->struct_mutex
);
1037 return PTR_ERR(ctx
);
1041 switch (args
->param
) {
1042 case I915_CONTEXT_PARAM_BAN_PERIOD
:
1043 args
->value
= ctx
->hang_stats
.ban_period_seconds
;
1045 case I915_CONTEXT_PARAM_NO_ZEROMAP
:
1046 args
->value
= ctx
->flags
& CONTEXT_NO_ZEROMAP
;
1048 case I915_CONTEXT_PARAM_GTT_SIZE
:
1050 args
->value
= ctx
->ppgtt
->base
.total
;
1051 else if (to_i915(dev
)->mm
.aliasing_ppgtt
)
1052 args
->value
= to_i915(dev
)->mm
.aliasing_ppgtt
->base
.total
;
1054 args
->value
= to_i915(dev
)->ggtt
.base
.total
;
1056 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE
:
1057 args
->value
= !!(ctx
->flags
& CONTEXT_NO_ERROR_CAPTURE
);
1063 mutex_unlock(&dev
->struct_mutex
);
1068 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
1069 struct drm_file
*file
)
1071 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1072 struct drm_i915_gem_context_param
*args
= data
;
1073 struct i915_gem_context
*ctx
;
1076 ret
= i915_mutex_lock_interruptible(dev
);
1080 ctx
= i915_gem_context_lookup(file_priv
, args
->ctx_id
);
1082 mutex_unlock(&dev
->struct_mutex
);
1083 return PTR_ERR(ctx
);
1086 switch (args
->param
) {
1087 case I915_CONTEXT_PARAM_BAN_PERIOD
:
1090 else if (args
->value
< ctx
->hang_stats
.ban_period_seconds
&&
1091 !capable(CAP_SYS_ADMIN
))
1094 ctx
->hang_stats
.ban_period_seconds
= args
->value
;
1096 case I915_CONTEXT_PARAM_NO_ZEROMAP
:
1100 ctx
->flags
&= ~CONTEXT_NO_ZEROMAP
;
1101 ctx
->flags
|= args
->value
? CONTEXT_NO_ZEROMAP
: 0;
1104 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE
:
1109 ctx
->flags
|= CONTEXT_NO_ERROR_CAPTURE
;
1111 ctx
->flags
&= ~CONTEXT_NO_ERROR_CAPTURE
;
1118 mutex_unlock(&dev
->struct_mutex
);
1123 int i915_gem_context_reset_stats_ioctl(struct drm_device
*dev
,
1124 void *data
, struct drm_file
*file
)
1126 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1127 struct drm_i915_reset_stats
*args
= data
;
1128 struct i915_ctx_hang_stats
*hs
;
1129 struct i915_gem_context
*ctx
;
1132 if (args
->flags
|| args
->pad
)
1135 if (args
->ctx_id
== DEFAULT_CONTEXT_HANDLE
&& !capable(CAP_SYS_ADMIN
))
1138 ret
= i915_mutex_lock_interruptible(dev
);
1142 ctx
= i915_gem_context_lookup(file
->driver_priv
, args
->ctx_id
);
1144 mutex_unlock(&dev
->struct_mutex
);
1145 return PTR_ERR(ctx
);
1147 hs
= &ctx
->hang_stats
;
1149 if (capable(CAP_SYS_ADMIN
))
1150 args
->reset_count
= i915_reset_count(&dev_priv
->gpu_error
);
1152 args
->reset_count
= 0;
1154 args
->batch_active
= hs
->batch_active
;
1155 args
->batch_pending
= hs
->batch_pending
;
1157 mutex_unlock(&dev
->struct_mutex
);