2 * Copyright © 2011-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded its state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
89 #include <drm/i915_drm.h>
91 #include "i915_trace.h"
93 /* This is a HW constraint. The value below is the largest known requirement
94 * I've seen in a spec to date, and that was a workaround for a non-shipping
95 * part. It should be safe to decrease this, but it's more future proof as is.
97 #define GEN6_CONTEXT_ALIGN (64<<10)
98 #define GEN7_CONTEXT_ALIGN 4096
100 static size_t get_context_alignment(struct drm_device
*dev
)
103 return GEN6_CONTEXT_ALIGN
;
105 return GEN7_CONTEXT_ALIGN
;
108 static int get_context_size(struct drm_device
*dev
)
110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
114 switch (INTEL_INFO(dev
)->gen
) {
116 reg
= I915_READ(CXT_SIZE
);
117 ret
= GEN6_CXT_TOTAL_SIZE(reg
) * 64;
120 reg
= I915_READ(GEN7_CXT_SIZE
);
122 ret
= HSW_CXT_TOTAL_SIZE
;
124 ret
= GEN7_CXT_TOTAL_SIZE(reg
) * 64;
127 ret
= GEN8_CXT_TOTAL_SIZE
;
136 void i915_gem_context_free(struct kref
*ctx_ref
)
138 struct intel_context
*ctx
= container_of(ctx_ref
,
141 trace_i915_context_free(ctx
);
143 if (i915
.enable_execlists
)
144 intel_lr_context_free(ctx
);
146 i915_ppgtt_put(ctx
->ppgtt
);
148 if (ctx
->legacy_hw_ctx
.rcs_state
)
149 drm_gem_object_unreference(&ctx
->legacy_hw_ctx
.rcs_state
->base
);
150 list_del(&ctx
->link
);
154 struct drm_i915_gem_object
*
155 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
)
157 struct drm_i915_gem_object
*obj
;
160 obj
= i915_gem_alloc_object(dev
, size
);
162 return ERR_PTR(-ENOMEM
);
165 * Try to make the context utilize L3 as well as LLC.
167 * On VLV we don't have L3 controls in the PTEs so we
168 * shouldn't touch the cache level, especially as that
169 * would make the object snooped which might have a
170 * negative performance impact.
172 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
)) {
173 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_L3_LLC
);
174 /* Failure shouldn't ever happen this early */
176 drm_gem_object_unreference(&obj
->base
);
184 static struct intel_context
*
185 __create_hw_context(struct drm_device
*dev
,
186 struct drm_i915_file_private
*file_priv
)
188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
189 struct intel_context
*ctx
;
192 ctx
= kzalloc(sizeof(*ctx
), GFP_KERNEL
);
194 return ERR_PTR(-ENOMEM
);
196 kref_init(&ctx
->ref
);
197 list_add_tail(&ctx
->link
, &dev_priv
->context_list
);
199 if (dev_priv
->hw_context_size
) {
200 struct drm_i915_gem_object
*obj
=
201 i915_gem_alloc_context_obj(dev
, dev_priv
->hw_context_size
);
206 ctx
->legacy_hw_ctx
.rcs_state
= obj
;
209 /* Default context will never have a file_priv */
210 if (file_priv
!= NULL
) {
211 ret
= idr_alloc(&file_priv
->context_idr
, ctx
,
212 DEFAULT_CONTEXT_HANDLE
, 0, GFP_KERNEL
);
216 ret
= DEFAULT_CONTEXT_HANDLE
;
218 ctx
->file_priv
= file_priv
;
219 ctx
->user_handle
= ret
;
220 /* NB: Mark all slices as needing a remap so that when the context first
221 * loads it will restore whatever remap state already exists. If there
222 * is no remap info, it will be a NOP. */
223 ctx
->remap_slice
= (1 << NUM_L3_SLICES(dev
)) - 1;
225 ctx
->hang_stats
.ban_period_seconds
= DRM_I915_CTX_BAN_PERIOD
;
230 i915_gem_context_unreference(ctx
);
235 * The default context needs to exist per ring that uses contexts. It stores the
236 * context state of the GPU for applications that don't utilize HW contexts, as
237 * well as an idle case.
239 static struct intel_context
*
240 i915_gem_create_context(struct drm_device
*dev
,
241 struct drm_i915_file_private
*file_priv
)
243 const bool is_global_default_ctx
= file_priv
== NULL
;
244 struct intel_context
*ctx
;
247 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
249 ctx
= __create_hw_context(dev
, file_priv
);
253 if (is_global_default_ctx
&& ctx
->legacy_hw_ctx
.rcs_state
) {
254 /* We may need to do things with the shrinker which
255 * require us to immediately switch back to the default
256 * context. This can cause a problem as pinning the
257 * default context also requires GTT space which may not
258 * be available. To avoid this we always pin the default
261 ret
= i915_gem_obj_ggtt_pin(ctx
->legacy_hw_ctx
.rcs_state
,
262 get_context_alignment(dev
), 0);
264 DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret
);
269 if (USES_FULL_PPGTT(dev
)) {
270 struct i915_hw_ppgtt
*ppgtt
= i915_ppgtt_create(dev
, file_priv
);
272 if (IS_ERR_OR_NULL(ppgtt
)) {
273 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
275 ret
= PTR_ERR(ppgtt
);
282 trace_i915_context_create(ctx
);
287 if (is_global_default_ctx
&& ctx
->legacy_hw_ctx
.rcs_state
)
288 i915_gem_object_ggtt_unpin(ctx
->legacy_hw_ctx
.rcs_state
);
290 i915_gem_context_unreference(ctx
);
294 void i915_gem_context_reset(struct drm_device
*dev
)
296 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
299 if (i915
.enable_execlists
) {
300 struct intel_context
*ctx
;
302 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
303 intel_lr_context_reset(dev
, ctx
);
309 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
310 struct intel_engine_cs
*ring
= &dev_priv
->ring
[i
];
311 struct intel_context
*lctx
= ring
->last_context
;
314 if (lctx
->legacy_hw_ctx
.rcs_state
&& i
== RCS
)
315 i915_gem_object_ggtt_unpin(lctx
->legacy_hw_ctx
.rcs_state
);
317 i915_gem_context_unreference(lctx
);
318 ring
->last_context
= NULL
;
323 int i915_gem_context_init(struct drm_device
*dev
)
325 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
326 struct intel_context
*ctx
;
329 /* Init should only be called once per module load. Eventually the
330 * restriction on the context_disabled check can be loosened. */
331 if (WARN_ON(dev_priv
->ring
[RCS
].default_context
))
334 if (i915
.enable_execlists
) {
335 /* NB: intentionally left blank. We will allocate our own
336 * backing objects as we need them, thank you very much */
337 dev_priv
->hw_context_size
= 0;
338 } else if (HAS_HW_CONTEXTS(dev
)) {
339 dev_priv
->hw_context_size
= round_up(get_context_size(dev
), 4096);
340 if (dev_priv
->hw_context_size
> (1<<20)) {
341 DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
342 dev_priv
->hw_context_size
);
343 dev_priv
->hw_context_size
= 0;
347 ctx
= i915_gem_create_context(dev
, NULL
);
349 DRM_ERROR("Failed to create default global context (error %ld)\n",
354 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
355 struct intel_engine_cs
*ring
= &dev_priv
->ring
[i
];
357 /* NB: RCS will hold a ref for all rings */
358 ring
->default_context
= ctx
;
361 DRM_DEBUG_DRIVER("%s context support initialized\n",
362 i915
.enable_execlists
? "LR" :
363 dev_priv
->hw_context_size
? "HW" : "fake");
367 void i915_gem_context_fini(struct drm_device
*dev
)
369 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
370 struct intel_context
*dctx
= dev_priv
->ring
[RCS
].default_context
;
373 if (dctx
->legacy_hw_ctx
.rcs_state
) {
374 /* The only known way to stop the gpu from accessing the hw context is
375 * to reset it. Do this as the very last operation to avoid confusing
376 * other code, leading to spurious errors. */
377 intel_gpu_reset(dev
);
379 /* When default context is created and switched to, base object refcount
380 * will be 2 (+1 from object creation and +1 from do_switch()).
381 * i915_gem_context_fini() will be called after gpu_idle() has switched
382 * to default context. So we need to unreference the base object once
383 * to offset the do_switch part, so that i915_gem_context_unreference()
384 * can then free the base object correctly. */
385 WARN_ON(!dev_priv
->ring
[RCS
].last_context
);
386 if (dev_priv
->ring
[RCS
].last_context
== dctx
) {
387 /* Fake switch to NULL context */
388 WARN_ON(dctx
->legacy_hw_ctx
.rcs_state
->active
);
389 i915_gem_object_ggtt_unpin(dctx
->legacy_hw_ctx
.rcs_state
);
390 i915_gem_context_unreference(dctx
);
391 dev_priv
->ring
[RCS
].last_context
= NULL
;
394 i915_gem_object_ggtt_unpin(dctx
->legacy_hw_ctx
.rcs_state
);
397 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
398 struct intel_engine_cs
*ring
= &dev_priv
->ring
[i
];
400 if (ring
->last_context
)
401 i915_gem_context_unreference(ring
->last_context
);
403 ring
->default_context
= NULL
;
404 ring
->last_context
= NULL
;
407 i915_gem_context_unreference(dctx
);
410 int i915_gem_context_enable(struct drm_i915_private
*dev_priv
)
412 struct intel_engine_cs
*ring
;
415 BUG_ON(!dev_priv
->ring
[RCS
].default_context
);
417 if (i915
.enable_execlists
) {
418 for_each_ring(ring
, dev_priv
, i
) {
419 if (ring
->init_context
) {
420 ret
= ring
->init_context(ring
,
421 ring
->default_context
);
423 DRM_ERROR("ring init context: %d\n",
431 for_each_ring(ring
, dev_priv
, i
) {
432 ret
= i915_switch_context(ring
, ring
->default_context
);
440 static int context_idr_cleanup(int id
, void *p
, void *data
)
442 struct intel_context
*ctx
= p
;
444 i915_gem_context_unreference(ctx
);
448 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
)
450 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
451 struct intel_context
*ctx
;
453 idr_init(&file_priv
->context_idr
);
455 mutex_lock(&dev
->struct_mutex
);
456 ctx
= i915_gem_create_context(dev
, file_priv
);
457 mutex_unlock(&dev
->struct_mutex
);
460 idr_destroy(&file_priv
->context_idr
);
467 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
)
469 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
471 idr_for_each(&file_priv
->context_idr
, context_idr_cleanup
, NULL
);
472 idr_destroy(&file_priv
->context_idr
);
475 struct intel_context
*
476 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
)
478 struct intel_context
*ctx
;
480 ctx
= (struct intel_context
*)idr_find(&file_priv
->context_idr
, id
);
482 return ERR_PTR(-ENOENT
);
488 mi_set_context(struct intel_engine_cs
*ring
,
489 struct intel_context
*new_context
,
492 u32 flags
= hw_flags
| MI_MM_SPACE_GTT
;
493 const int num_rings
=
494 /* Use an extended w/a on ivb+ if signalling from other rings */
495 i915_semaphore_is_enabled(ring
->dev
) ?
496 hweight32(INTEL_INFO(ring
->dev
)->ring_mask
) - 1 :
500 /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
501 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
502 * explicitly, so we rely on the value at ring init, stored in
503 * itlb_before_ctx_switch.
505 if (IS_GEN6(ring
->dev
)) {
506 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, 0);
511 /* These flags are for resource streamer on HSW+ */
512 if (!IS_HASWELL(ring
->dev
) && INTEL_INFO(ring
->dev
)->gen
< 8)
513 flags
|= (MI_SAVE_EXT_STATE_EN
| MI_RESTORE_EXT_STATE_EN
);
517 if (INTEL_INFO(ring
->dev
)->gen
>= 7)
518 len
+= 2 + (num_rings
? 4*num_rings
+ 2 : 0);
520 ret
= intel_ring_begin(ring
, len
);
524 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
525 if (INTEL_INFO(ring
->dev
)->gen
>= 7) {
526 intel_ring_emit(ring
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
528 struct intel_engine_cs
*signaller
;
530 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(num_rings
));
531 for_each_ring(signaller
, to_i915(ring
->dev
), i
) {
532 if (signaller
== ring
)
535 intel_ring_emit(ring
, RING_PSMI_CTL(signaller
->mmio_base
));
536 intel_ring_emit(ring
, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE
));
541 intel_ring_emit(ring
, MI_NOOP
);
542 intel_ring_emit(ring
, MI_SET_CONTEXT
);
543 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(new_context
->legacy_hw_ctx
.rcs_state
) |
546 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
547 * WaMiSetContext_Hang:snb,ivb,vlv
549 intel_ring_emit(ring
, MI_NOOP
);
551 if (INTEL_INFO(ring
->dev
)->gen
>= 7) {
553 struct intel_engine_cs
*signaller
;
555 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(num_rings
));
556 for_each_ring(signaller
, to_i915(ring
->dev
), i
) {
557 if (signaller
== ring
)
560 intel_ring_emit(ring
, RING_PSMI_CTL(signaller
->mmio_base
));
561 intel_ring_emit(ring
, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE
));
564 intel_ring_emit(ring
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
567 intel_ring_advance(ring
);
572 static inline bool should_skip_switch(struct intel_engine_cs
*ring
,
573 struct intel_context
*from
,
574 struct intel_context
*to
)
576 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
582 if (from
== to
&& !test_bit(ring
->id
,
583 &to
->ppgtt
->pd_dirty_rings
))
585 } else if (dev_priv
->mm
.aliasing_ppgtt
) {
586 if (from
== to
&& !test_bit(ring
->id
,
587 &dev_priv
->mm
.aliasing_ppgtt
->pd_dirty_rings
))
595 needs_pd_load_pre(struct intel_engine_cs
*ring
, struct intel_context
*to
)
597 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
602 if (INTEL_INFO(ring
->dev
)->gen
< 8)
605 if (ring
!= &dev_priv
->ring
[RCS
])
612 needs_pd_load_post(struct intel_engine_cs
*ring
, struct intel_context
*to
,
615 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
620 if (!IS_GEN8(ring
->dev
))
623 if (ring
!= &dev_priv
->ring
[RCS
])
626 if (hw_flags
& MI_RESTORE_INHIBIT
)
632 static int do_switch(struct intel_engine_cs
*ring
,
633 struct intel_context
*to
)
635 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
636 struct intel_context
*from
= ring
->last_context
;
638 bool uninitialized
= false;
639 struct i915_vma
*vma
;
642 if (from
!= NULL
&& ring
== &dev_priv
->ring
[RCS
]) {
643 BUG_ON(from
->legacy_hw_ctx
.rcs_state
== NULL
);
644 BUG_ON(!i915_gem_obj_is_pinned(from
->legacy_hw_ctx
.rcs_state
));
647 if (should_skip_switch(ring
, from
, to
))
650 /* Trying to pin first makes error handling easier. */
651 if (ring
== &dev_priv
->ring
[RCS
]) {
652 ret
= i915_gem_obj_ggtt_pin(to
->legacy_hw_ctx
.rcs_state
,
653 get_context_alignment(ring
->dev
), 0);
659 * Pin can switch back to the default context if we end up calling into
660 * evict_everything - as a last ditch gtt defrag effort that also
661 * switches to the default context. Hence we need to reload from here.
663 from
= ring
->last_context
;
665 if (needs_pd_load_pre(ring
, to
)) {
666 /* Older GENs and non render rings still want the load first,
667 * "PP_DCLV followed by PP_DIR_BASE register through Load
668 * Register Immediate commands in Ring Buffer before submitting
670 trace_switch_mm(ring
, to
);
671 ret
= to
->ppgtt
->switch_mm(to
->ppgtt
, ring
);
675 /* Doing a PD load always reloads the page dirs */
676 clear_bit(ring
->id
, &to
->ppgtt
->pd_dirty_rings
);
679 if (ring
!= &dev_priv
->ring
[RCS
]) {
681 i915_gem_context_unreference(from
);
686 * Clear this page out of any CPU caches for coherent swap-in/out. Note
687 * that thanks to write = false in this call and us not setting any gpu
688 * write domains when putting a context object onto the active list
689 * (when switching away from it), this won't block.
691 * XXX: We need a real interface to do this instead of trickery.
693 ret
= i915_gem_object_set_to_gtt_domain(to
->legacy_hw_ctx
.rcs_state
, false);
697 vma
= i915_gem_obj_to_ggtt(to
->legacy_hw_ctx
.rcs_state
);
698 if (!(vma
->bound
& GLOBAL_BIND
)) {
699 ret
= i915_vma_bind(vma
,
700 to
->legacy_hw_ctx
.rcs_state
->cache_level
,
702 /* This shouldn't ever fail. */
703 if (WARN_ONCE(ret
, "GGTT context bind failed!"))
707 if (!to
->legacy_hw_ctx
.initialized
) {
708 hw_flags
|= MI_RESTORE_INHIBIT
;
709 /* NB: If we inhibit the restore, the context is not allowed to
710 * die because future work may end up depending on valid address
711 * space. This means we must enforce that a page table load
712 * occur when this occurs. */
713 } else if (to
->ppgtt
&&
714 test_and_clear_bit(ring
->id
, &to
->ppgtt
->pd_dirty_rings
))
715 hw_flags
|= MI_FORCE_RESTORE
;
717 /* We should never emit switch_mm more than once */
718 WARN_ON(needs_pd_load_pre(ring
, to
) &&
719 needs_pd_load_post(ring
, to
, hw_flags
));
721 ret
= mi_set_context(ring
, to
, hw_flags
);
725 /* GEN8 does *not* require an explicit reload if the PDPs have been
726 * setup, and we do not wish to move them.
728 if (needs_pd_load_post(ring
, to
, hw_flags
)) {
729 trace_switch_mm(ring
, to
);
730 ret
= to
->ppgtt
->switch_mm(to
->ppgtt
, ring
);
731 /* The hardware context switch is emitted, but we haven't
732 * actually changed the state - so it's probably safe to bail
733 * here. Still, let the user know something dangerous has
737 DRM_ERROR("Failed to change address space on context switch\n");
742 for (i
= 0; i
< MAX_L3_SLICES
; i
++) {
743 if (!(to
->remap_slice
& (1<<i
)))
746 ret
= i915_gem_l3_remap(ring
, i
);
747 /* If it failed, try again next round */
749 DRM_DEBUG_DRIVER("L3 remapping failed\n");
751 to
->remap_slice
&= ~(1<<i
);
754 /* The backing object for the context is done after switching to the
755 * *next* context. Therefore we cannot retire the previous context until
756 * the next context has already started running. In fact, the below code
757 * is a bit suboptimal because the retiring can occur simply after the
758 * MI_SET_CONTEXT instead of when the next seqno has completed.
761 from
->legacy_hw_ctx
.rcs_state
->base
.read_domains
= I915_GEM_DOMAIN_INSTRUCTION
;
762 i915_vma_move_to_active(i915_gem_obj_to_ggtt(from
->legacy_hw_ctx
.rcs_state
), ring
);
763 /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
764 * whole damn pipeline, we don't need to explicitly mark the
765 * object dirty. The only exception is that the context must be
766 * correct in case the object gets swapped out. Ideally we'd be
767 * able to defer doing this until we know the object would be
768 * swapped, but there is no way to do that yet.
770 from
->legacy_hw_ctx
.rcs_state
->dirty
= 1;
771 BUG_ON(i915_gem_request_get_ring(
772 from
->legacy_hw_ctx
.rcs_state
->last_read_req
) != ring
);
774 /* obj is kept alive until the next request by its active ref */
775 i915_gem_object_ggtt_unpin(from
->legacy_hw_ctx
.rcs_state
);
776 i915_gem_context_unreference(from
);
779 uninitialized
= !to
->legacy_hw_ctx
.initialized
;
780 to
->legacy_hw_ctx
.initialized
= true;
783 i915_gem_context_reference(to
);
784 ring
->last_context
= to
;
787 if (ring
->init_context
) {
788 ret
= ring
->init_context(ring
, to
);
790 DRM_ERROR("ring init context: %d\n", ret
);
798 i915_gem_object_ggtt_unpin(to
->legacy_hw_ctx
.rcs_state
);
803 * i915_switch_context() - perform a GPU context switch.
804 * @ring: ring for which we'll execute the context switch
805 * @to: the context to switch to
807 * The context life cycle is simple. The context refcount is incremented and
808 * decremented by 1 and create and destroy. If the context is in use by the GPU,
809 * it will have a refcount > 1. This allows us to destroy the context abstract
810 * object while letting the normal object tracking destroy the backing BO.
812 * This function should not be used in execlists mode. Instead the context is
813 * switched by writing to the ELSP and requests keep a reference to their
816 int i915_switch_context(struct intel_engine_cs
*ring
,
817 struct intel_context
*to
)
819 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
821 WARN_ON(i915
.enable_execlists
);
822 WARN_ON(!mutex_is_locked(&dev_priv
->dev
->struct_mutex
));
824 if (to
->legacy_hw_ctx
.rcs_state
== NULL
) { /* We have the fake context */
825 if (to
!= ring
->last_context
) {
826 i915_gem_context_reference(to
);
827 if (ring
->last_context
)
828 i915_gem_context_unreference(ring
->last_context
);
829 ring
->last_context
= to
;
834 return do_switch(ring
, to
);
837 static bool contexts_enabled(struct drm_device
*dev
)
839 return i915
.enable_execlists
|| to_i915(dev
)->hw_context_size
;
842 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
843 struct drm_file
*file
)
845 struct drm_i915_gem_context_create
*args
= data
;
846 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
847 struct intel_context
*ctx
;
850 if (!contexts_enabled(dev
))
853 ret
= i915_mutex_lock_interruptible(dev
);
857 ctx
= i915_gem_create_context(dev
, file_priv
);
858 mutex_unlock(&dev
->struct_mutex
);
862 args
->ctx_id
= ctx
->user_handle
;
863 DRM_DEBUG_DRIVER("HW context %d created\n", args
->ctx_id
);
868 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
869 struct drm_file
*file
)
871 struct drm_i915_gem_context_destroy
*args
= data
;
872 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
873 struct intel_context
*ctx
;
876 if (args
->ctx_id
== DEFAULT_CONTEXT_HANDLE
)
879 ret
= i915_mutex_lock_interruptible(dev
);
883 ctx
= i915_gem_context_get(file_priv
, args
->ctx_id
);
885 mutex_unlock(&dev
->struct_mutex
);
889 idr_remove(&ctx
->file_priv
->context_idr
, ctx
->user_handle
);
890 i915_gem_context_unreference(ctx
);
891 mutex_unlock(&dev
->struct_mutex
);
893 DRM_DEBUG_DRIVER("HW context %d destroyed\n", args
->ctx_id
);
897 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
898 struct drm_file
*file
)
900 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
901 struct drm_i915_gem_context_param
*args
= data
;
902 struct intel_context
*ctx
;
905 ret
= i915_mutex_lock_interruptible(dev
);
909 ctx
= i915_gem_context_get(file_priv
, args
->ctx_id
);
911 mutex_unlock(&dev
->struct_mutex
);
916 switch (args
->param
) {
917 case I915_CONTEXT_PARAM_BAN_PERIOD
:
918 args
->value
= ctx
->hang_stats
.ban_period_seconds
;
924 mutex_unlock(&dev
->struct_mutex
);
929 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
930 struct drm_file
*file
)
932 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
933 struct drm_i915_gem_context_param
*args
= data
;
934 struct intel_context
*ctx
;
937 ret
= i915_mutex_lock_interruptible(dev
);
941 ctx
= i915_gem_context_get(file_priv
, args
->ctx_id
);
943 mutex_unlock(&dev
->struct_mutex
);
947 switch (args
->param
) {
948 case I915_CONTEXT_PARAM_BAN_PERIOD
:
951 else if (args
->value
< ctx
->hang_stats
.ban_period_seconds
&&
952 !capable(CAP_SYS_ADMIN
))
955 ctx
->hang_stats
.ban_period_seconds
= args
->value
;
961 mutex_unlock(&dev
->struct_mutex
);