2 * Copyright © 2011-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded its state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
89 #include <drm/i915_drm.h>
91 #include "i915_trace.h"
93 /* This is a HW constraint. The value below is the largest known requirement
94 * I've seen in a spec to date, and that was a workaround for a non-shipping
95 * part. It should be safe to decrease this, but it's more future proof as is.
97 #define GEN6_CONTEXT_ALIGN (64<<10)
98 #define GEN7_CONTEXT_ALIGN 4096
100 static size_t get_context_alignment(struct drm_device
*dev
)
103 return GEN6_CONTEXT_ALIGN
;
105 return GEN7_CONTEXT_ALIGN
;
108 static int get_context_size(struct drm_device
*dev
)
110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
114 switch (INTEL_INFO(dev
)->gen
) {
116 reg
= I915_READ(CXT_SIZE
);
117 ret
= GEN6_CXT_TOTAL_SIZE(reg
) * 64;
120 reg
= I915_READ(GEN7_CXT_SIZE
);
122 ret
= HSW_CXT_TOTAL_SIZE
;
124 ret
= GEN7_CXT_TOTAL_SIZE(reg
) * 64;
127 ret
= GEN8_CXT_TOTAL_SIZE
;
136 void i915_gem_context_free(struct kref
*ctx_ref
)
138 struct intel_context
*ctx
= container_of(ctx_ref
,
141 trace_i915_context_free(ctx
);
143 if (i915
.enable_execlists
)
144 intel_lr_context_free(ctx
);
146 i915_ppgtt_put(ctx
->ppgtt
);
148 if (ctx
->legacy_hw_ctx
.rcs_state
)
149 drm_gem_object_unreference(&ctx
->legacy_hw_ctx
.rcs_state
->base
);
150 list_del(&ctx
->link
);
154 struct drm_i915_gem_object
*
155 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
)
157 struct drm_i915_gem_object
*obj
;
160 obj
= i915_gem_object_create_stolen(dev
, size
);
162 obj
= i915_gem_alloc_object(dev
, size
);
164 return ERR_PTR(-ENOMEM
);
167 * Try to make the context utilize L3 as well as LLC.
169 * On VLV we don't have L3 controls in the PTEs so we
170 * shouldn't touch the cache level, especially as that
171 * would make the object snooped which might have a
172 * negative performance impact.
174 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
)) {
175 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_L3_LLC
);
176 /* Failure shouldn't ever happen this early */
178 drm_gem_object_unreference(&obj
->base
);
186 static struct intel_context
*
187 __create_hw_context(struct drm_device
*dev
,
188 struct drm_i915_file_private
*file_priv
)
190 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
191 struct intel_context
*ctx
;
194 ctx
= kzalloc(sizeof(*ctx
), GFP_KERNEL
);
196 return ERR_PTR(-ENOMEM
);
198 kref_init(&ctx
->ref
);
199 list_add_tail(&ctx
->link
, &dev_priv
->context_list
);
201 if (dev_priv
->hw_context_size
) {
202 struct drm_i915_gem_object
*obj
=
203 i915_gem_alloc_context_obj(dev
, dev_priv
->hw_context_size
);
208 ctx
->legacy_hw_ctx
.rcs_state
= obj
;
211 /* Default context will never have a file_priv */
212 if (file_priv
!= NULL
) {
213 ret
= idr_alloc(&file_priv
->context_idr
, ctx
,
214 DEFAULT_CONTEXT_HANDLE
, 0, GFP_KERNEL
);
218 ret
= DEFAULT_CONTEXT_HANDLE
;
220 ctx
->file_priv
= file_priv
;
221 ctx
->user_handle
= ret
;
222 /* NB: Mark all slices as needing a remap so that when the context first
223 * loads it will restore whatever remap state already exists. If there
224 * is no remap info, it will be a NOP. */
225 ctx
->remap_slice
= (1 << NUM_L3_SLICES(dev
)) - 1;
227 ctx
->hang_stats
.ban_period_seconds
= DRM_I915_CTX_BAN_PERIOD
;
232 i915_gem_context_unreference(ctx
);
237 * The default context needs to exist per ring that uses contexts. It stores the
238 * context state of the GPU for applications that don't utilize HW contexts, as
239 * well as an idle case.
241 static struct intel_context
*
242 i915_gem_create_context(struct drm_device
*dev
,
243 struct drm_i915_file_private
*file_priv
)
245 const bool is_global_default_ctx
= file_priv
== NULL
;
246 struct intel_context
*ctx
;
249 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
251 ctx
= __create_hw_context(dev
, file_priv
);
255 if (is_global_default_ctx
&& ctx
->legacy_hw_ctx
.rcs_state
) {
256 /* We may need to do things with the shrinker which
257 * require us to immediately switch back to the default
258 * context. This can cause a problem as pinning the
259 * default context also requires GTT space which may not
260 * be available. To avoid this we always pin the default
263 ret
= i915_gem_obj_ggtt_pin(ctx
->legacy_hw_ctx
.rcs_state
,
264 get_context_alignment(dev
), 0);
266 DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret
);
271 if (USES_FULL_PPGTT(dev
)) {
272 struct i915_hw_ppgtt
*ppgtt
= i915_ppgtt_create(dev
, file_priv
);
274 if (IS_ERR_OR_NULL(ppgtt
)) {
275 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
277 ret
= PTR_ERR(ppgtt
);
284 trace_i915_context_create(ctx
);
289 if (is_global_default_ctx
&& ctx
->legacy_hw_ctx
.rcs_state
)
290 i915_gem_object_ggtt_unpin(ctx
->legacy_hw_ctx
.rcs_state
);
292 i915_gem_context_unreference(ctx
);
296 void i915_gem_context_reset(struct drm_device
*dev
)
298 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
301 if (i915
.enable_execlists
) {
302 struct intel_context
*ctx
;
304 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
305 intel_lr_context_reset(dev
, ctx
);
311 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
312 struct intel_engine_cs
*ring
= &dev_priv
->ring
[i
];
313 struct intel_context
*lctx
= ring
->last_context
;
316 if (lctx
->legacy_hw_ctx
.rcs_state
&& i
== RCS
)
317 i915_gem_object_ggtt_unpin(lctx
->legacy_hw_ctx
.rcs_state
);
319 i915_gem_context_unreference(lctx
);
320 ring
->last_context
= NULL
;
325 int i915_gem_context_init(struct drm_device
*dev
)
327 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
328 struct intel_context
*ctx
;
331 /* Init should only be called once per module load. Eventually the
332 * restriction on the context_disabled check can be loosened. */
333 if (WARN_ON(dev_priv
->ring
[RCS
].default_context
))
336 if (i915
.enable_execlists
) {
337 /* NB: intentionally left blank. We will allocate our own
338 * backing objects as we need them, thank you very much */
339 dev_priv
->hw_context_size
= 0;
340 } else if (HAS_HW_CONTEXTS(dev
)) {
341 dev_priv
->hw_context_size
= round_up(get_context_size(dev
), 4096);
342 if (dev_priv
->hw_context_size
> (1<<20)) {
343 DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
344 dev_priv
->hw_context_size
);
345 dev_priv
->hw_context_size
= 0;
349 ctx
= i915_gem_create_context(dev
, NULL
);
351 DRM_ERROR("Failed to create default global context (error %ld)\n",
356 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
357 struct intel_engine_cs
*ring
= &dev_priv
->ring
[i
];
359 /* NB: RCS will hold a ref for all rings */
360 ring
->default_context
= ctx
;
363 DRM_DEBUG_DRIVER("%s context support initialized\n",
364 i915
.enable_execlists
? "LR" :
365 dev_priv
->hw_context_size
? "HW" : "fake");
369 void i915_gem_context_fini(struct drm_device
*dev
)
371 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
372 struct intel_context
*dctx
= dev_priv
->ring
[RCS
].default_context
;
375 if (dctx
->legacy_hw_ctx
.rcs_state
) {
376 /* The only known way to stop the gpu from accessing the hw context is
377 * to reset it. Do this as the very last operation to avoid confusing
378 * other code, leading to spurious errors. */
379 intel_gpu_reset(dev
);
381 /* When default context is created and switched to, base object refcount
382 * will be 2 (+1 from object creation and +1 from do_switch()).
383 * i915_gem_context_fini() will be called after gpu_idle() has switched
384 * to default context. So we need to unreference the base object once
385 * to offset the do_switch part, so that i915_gem_context_unreference()
386 * can then free the base object correctly. */
387 WARN_ON(!dev_priv
->ring
[RCS
].last_context
);
388 if (dev_priv
->ring
[RCS
].last_context
== dctx
) {
389 /* Fake switch to NULL context */
390 WARN_ON(dctx
->legacy_hw_ctx
.rcs_state
->active
);
391 i915_gem_object_ggtt_unpin(dctx
->legacy_hw_ctx
.rcs_state
);
392 i915_gem_context_unreference(dctx
);
393 dev_priv
->ring
[RCS
].last_context
= NULL
;
396 i915_gem_object_ggtt_unpin(dctx
->legacy_hw_ctx
.rcs_state
);
399 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
400 struct intel_engine_cs
*ring
= &dev_priv
->ring
[i
];
402 if (ring
->last_context
)
403 i915_gem_context_unreference(ring
->last_context
);
405 ring
->default_context
= NULL
;
406 ring
->last_context
= NULL
;
409 i915_gem_context_unreference(dctx
);
412 int i915_gem_context_enable(struct drm_i915_private
*dev_priv
)
414 struct intel_engine_cs
*ring
;
417 BUG_ON(!dev_priv
->ring
[RCS
].default_context
);
419 if (i915
.enable_execlists
) {
420 for_each_ring(ring
, dev_priv
, i
) {
421 if (ring
->init_context
) {
422 ret
= ring
->init_context(ring
,
423 ring
->default_context
);
425 DRM_ERROR("ring init context: %d\n",
433 for_each_ring(ring
, dev_priv
, i
) {
434 ret
= i915_switch_context(ring
, ring
->default_context
);
442 static int context_idr_cleanup(int id
, void *p
, void *data
)
444 struct intel_context
*ctx
= p
;
446 i915_gem_context_unreference(ctx
);
450 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
)
452 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
453 struct intel_context
*ctx
;
455 idr_init(&file_priv
->context_idr
);
457 mutex_lock(&dev
->struct_mutex
);
458 ctx
= i915_gem_create_context(dev
, file_priv
);
459 mutex_unlock(&dev
->struct_mutex
);
462 idr_destroy(&file_priv
->context_idr
);
469 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
)
471 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
473 idr_for_each(&file_priv
->context_idr
, context_idr_cleanup
, NULL
);
474 idr_destroy(&file_priv
->context_idr
);
477 struct intel_context
*
478 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
)
480 struct intel_context
*ctx
;
482 ctx
= (struct intel_context
*)idr_find(&file_priv
->context_idr
, id
);
484 return ERR_PTR(-ENOENT
);
490 mi_set_context(struct intel_engine_cs
*ring
,
491 struct intel_context
*new_context
,
494 u32 flags
= hw_flags
| MI_MM_SPACE_GTT
;
495 const int num_rings
=
496 /* Use an extended w/a on ivb+ if signalling from other rings */
497 i915_semaphore_is_enabled(ring
->dev
) ?
498 hweight32(INTEL_INFO(ring
->dev
)->ring_mask
) - 1 :
502 /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
503 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
504 * explicitly, so we rely on the value at ring init, stored in
505 * itlb_before_ctx_switch.
507 if (IS_GEN6(ring
->dev
)) {
508 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, 0);
513 /* These flags are for resource streamer on HSW+ */
514 if (!IS_HASWELL(ring
->dev
) && INTEL_INFO(ring
->dev
)->gen
< 8)
515 flags
|= (MI_SAVE_EXT_STATE_EN
| MI_RESTORE_EXT_STATE_EN
);
519 if (INTEL_INFO(ring
->dev
)->gen
>= 7)
520 len
+= 2 + (num_rings
? 4*num_rings
+ 2 : 0);
522 ret
= intel_ring_begin(ring
, len
);
526 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
527 if (INTEL_INFO(ring
->dev
)->gen
>= 7) {
528 intel_ring_emit(ring
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
530 struct intel_engine_cs
*signaller
;
532 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(num_rings
));
533 for_each_ring(signaller
, to_i915(ring
->dev
), i
) {
534 if (signaller
== ring
)
537 intel_ring_emit(ring
, RING_PSMI_CTL(signaller
->mmio_base
));
538 intel_ring_emit(ring
, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE
));
543 intel_ring_emit(ring
, MI_NOOP
);
544 intel_ring_emit(ring
, MI_SET_CONTEXT
);
545 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(new_context
->legacy_hw_ctx
.rcs_state
) |
548 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
549 * WaMiSetContext_Hang:snb,ivb,vlv
551 intel_ring_emit(ring
, MI_NOOP
);
553 if (INTEL_INFO(ring
->dev
)->gen
>= 7) {
555 struct intel_engine_cs
*signaller
;
557 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(num_rings
));
558 for_each_ring(signaller
, to_i915(ring
->dev
), i
) {
559 if (signaller
== ring
)
562 intel_ring_emit(ring
, RING_PSMI_CTL(signaller
->mmio_base
));
563 intel_ring_emit(ring
, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE
));
566 intel_ring_emit(ring
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
569 intel_ring_advance(ring
);
574 static inline bool should_skip_switch(struct intel_engine_cs
*ring
,
575 struct intel_context
*from
,
576 struct intel_context
*to
)
581 if (to
->ppgtt
&& from
== to
&&
582 !(intel_ring_flag(ring
) & to
->ppgtt
->pd_dirty_rings
))
589 needs_pd_load_pre(struct intel_engine_cs
*ring
, struct intel_context
*to
)
591 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
596 if (INTEL_INFO(ring
->dev
)->gen
< 8)
599 if (ring
!= &dev_priv
->ring
[RCS
])
606 needs_pd_load_post(struct intel_engine_cs
*ring
, struct intel_context
*to
,
609 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
614 if (!IS_GEN8(ring
->dev
))
617 if (ring
!= &dev_priv
->ring
[RCS
])
620 if (hw_flags
& MI_RESTORE_INHIBIT
)
626 static int do_switch(struct intel_engine_cs
*ring
,
627 struct intel_context
*to
)
629 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
630 struct intel_context
*from
= ring
->last_context
;
632 bool uninitialized
= false;
635 if (from
!= NULL
&& ring
== &dev_priv
->ring
[RCS
]) {
636 BUG_ON(from
->legacy_hw_ctx
.rcs_state
== NULL
);
637 BUG_ON(!i915_gem_obj_is_pinned(from
->legacy_hw_ctx
.rcs_state
));
640 if (should_skip_switch(ring
, from
, to
))
643 /* Trying to pin first makes error handling easier. */
644 if (ring
== &dev_priv
->ring
[RCS
]) {
645 ret
= i915_gem_obj_ggtt_pin(to
->legacy_hw_ctx
.rcs_state
,
646 get_context_alignment(ring
->dev
), 0);
652 * Pin can switch back to the default context if we end up calling into
653 * evict_everything - as a last ditch gtt defrag effort that also
654 * switches to the default context. Hence we need to reload from here.
656 from
= ring
->last_context
;
658 if (needs_pd_load_pre(ring
, to
)) {
659 /* Older GENs and non render rings still want the load first,
660 * "PP_DCLV followed by PP_DIR_BASE register through Load
661 * Register Immediate commands in Ring Buffer before submitting
663 trace_switch_mm(ring
, to
);
664 ret
= to
->ppgtt
->switch_mm(to
->ppgtt
, ring
);
668 /* Doing a PD load always reloads the page dirs */
669 to
->ppgtt
->pd_dirty_rings
&= ~intel_ring_flag(ring
);
672 if (ring
!= &dev_priv
->ring
[RCS
]) {
674 i915_gem_context_unreference(from
);
679 * Clear this page out of any CPU caches for coherent swap-in/out. Note
680 * that thanks to write = false in this call and us not setting any gpu
681 * write domains when putting a context object onto the active list
682 * (when switching away from it), this won't block.
684 * XXX: We need a real interface to do this instead of trickery.
686 ret
= i915_gem_object_set_to_gtt_domain(to
->legacy_hw_ctx
.rcs_state
, false);
690 if (!to
->legacy_hw_ctx
.initialized
) {
691 hw_flags
|= MI_RESTORE_INHIBIT
;
692 /* NB: If we inhibit the restore, the context is not allowed to
693 * die because future work may end up depending on valid address
694 * space. This means we must enforce that a page table load
695 * occur when this occurs. */
696 } else if (to
->ppgtt
&&
697 (intel_ring_flag(ring
) & to
->ppgtt
->pd_dirty_rings
)) {
698 hw_flags
|= MI_FORCE_RESTORE
;
699 to
->ppgtt
->pd_dirty_rings
&= ~intel_ring_flag(ring
);
702 /* We should never emit switch_mm more than once */
703 WARN_ON(needs_pd_load_pre(ring
, to
) &&
704 needs_pd_load_post(ring
, to
, hw_flags
));
706 ret
= mi_set_context(ring
, to
, hw_flags
);
710 /* GEN8 does *not* require an explicit reload if the PDPs have been
711 * setup, and we do not wish to move them.
713 if (needs_pd_load_post(ring
, to
, hw_flags
)) {
714 trace_switch_mm(ring
, to
);
715 ret
= to
->ppgtt
->switch_mm(to
->ppgtt
, ring
);
716 /* The hardware context switch is emitted, but we haven't
717 * actually changed the state - so it's probably safe to bail
718 * here. Still, let the user know something dangerous has
722 DRM_ERROR("Failed to change address space on context switch\n");
727 for (i
= 0; i
< MAX_L3_SLICES
; i
++) {
728 if (!(to
->remap_slice
& (1<<i
)))
731 ret
= i915_gem_l3_remap(ring
, i
);
732 /* If it failed, try again next round */
734 DRM_DEBUG_DRIVER("L3 remapping failed\n");
736 to
->remap_slice
&= ~(1<<i
);
739 /* The backing object for the context is done after switching to the
740 * *next* context. Therefore we cannot retire the previous context until
741 * the next context has already started running. In fact, the below code
742 * is a bit suboptimal because the retiring can occur simply after the
743 * MI_SET_CONTEXT instead of when the next seqno has completed.
746 from
->legacy_hw_ctx
.rcs_state
->base
.read_domains
= I915_GEM_DOMAIN_INSTRUCTION
;
747 i915_vma_move_to_active(i915_gem_obj_to_ggtt(from
->legacy_hw_ctx
.rcs_state
), ring
);
748 /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
749 * whole damn pipeline, we don't need to explicitly mark the
750 * object dirty. The only exception is that the context must be
751 * correct in case the object gets swapped out. Ideally we'd be
752 * able to defer doing this until we know the object would be
753 * swapped, but there is no way to do that yet.
755 from
->legacy_hw_ctx
.rcs_state
->dirty
= 1;
756 BUG_ON(i915_gem_request_get_ring(
757 from
->legacy_hw_ctx
.rcs_state
->last_read_req
) != ring
);
759 /* obj is kept alive until the next request by its active ref */
760 i915_gem_object_ggtt_unpin(from
->legacy_hw_ctx
.rcs_state
);
761 i915_gem_context_unreference(from
);
764 uninitialized
= !to
->legacy_hw_ctx
.initialized
;
765 to
->legacy_hw_ctx
.initialized
= true;
768 i915_gem_context_reference(to
);
769 ring
->last_context
= to
;
772 if (ring
->init_context
) {
773 ret
= ring
->init_context(ring
, to
);
775 DRM_ERROR("ring init context: %d\n", ret
);
783 i915_gem_object_ggtt_unpin(to
->legacy_hw_ctx
.rcs_state
);
788 * i915_switch_context() - perform a GPU context switch.
789 * @ring: ring for which we'll execute the context switch
790 * @to: the context to switch to
792 * The context life cycle is simple. The context refcount is incremented and
793 * decremented by 1 and create and destroy. If the context is in use by the GPU,
794 * it will have a refcount > 1. This allows us to destroy the context abstract
795 * object while letting the normal object tracking destroy the backing BO.
797 * This function should not be used in execlists mode. Instead the context is
798 * switched by writing to the ELSP and requests keep a reference to their
801 int i915_switch_context(struct intel_engine_cs
*ring
,
802 struct intel_context
*to
)
804 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
806 WARN_ON(i915
.enable_execlists
);
807 WARN_ON(!mutex_is_locked(&dev_priv
->dev
->struct_mutex
));
809 if (to
->legacy_hw_ctx
.rcs_state
== NULL
) { /* We have the fake context */
810 if (to
!= ring
->last_context
) {
811 i915_gem_context_reference(to
);
812 if (ring
->last_context
)
813 i915_gem_context_unreference(ring
->last_context
);
814 ring
->last_context
= to
;
819 return do_switch(ring
, to
);
822 static bool contexts_enabled(struct drm_device
*dev
)
824 return i915
.enable_execlists
|| to_i915(dev
)->hw_context_size
;
827 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
828 struct drm_file
*file
)
830 struct drm_i915_gem_context_create
*args
= data
;
831 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
832 struct intel_context
*ctx
;
835 if (!contexts_enabled(dev
))
838 ret
= i915_mutex_lock_interruptible(dev
);
842 ctx
= i915_gem_create_context(dev
, file_priv
);
843 mutex_unlock(&dev
->struct_mutex
);
847 args
->ctx_id
= ctx
->user_handle
;
848 DRM_DEBUG_DRIVER("HW context %d created\n", args
->ctx_id
);
853 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
854 struct drm_file
*file
)
856 struct drm_i915_gem_context_destroy
*args
= data
;
857 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
858 struct intel_context
*ctx
;
861 if (args
->ctx_id
== DEFAULT_CONTEXT_HANDLE
)
864 ret
= i915_mutex_lock_interruptible(dev
);
868 ctx
= i915_gem_context_get(file_priv
, args
->ctx_id
);
870 mutex_unlock(&dev
->struct_mutex
);
874 idr_remove(&ctx
->file_priv
->context_idr
, ctx
->user_handle
);
875 i915_gem_context_unreference(ctx
);
876 mutex_unlock(&dev
->struct_mutex
);
878 DRM_DEBUG_DRIVER("HW context %d destroyed\n", args
->ctx_id
);
882 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
883 struct drm_file
*file
)
885 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
886 struct drm_i915_gem_context_param
*args
= data
;
887 struct intel_context
*ctx
;
890 ret
= i915_mutex_lock_interruptible(dev
);
894 ctx
= i915_gem_context_get(file_priv
, args
->ctx_id
);
896 mutex_unlock(&dev
->struct_mutex
);
901 switch (args
->param
) {
902 case I915_CONTEXT_PARAM_BAN_PERIOD
:
903 args
->value
= ctx
->hang_stats
.ban_period_seconds
;
909 mutex_unlock(&dev
->struct_mutex
);
914 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
915 struct drm_file
*file
)
917 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
918 struct drm_i915_gem_context_param
*args
= data
;
919 struct intel_context
*ctx
;
922 ret
= i915_mutex_lock_interruptible(dev
);
926 ctx
= i915_gem_context_get(file_priv
, args
->ctx_id
);
928 mutex_unlock(&dev
->struct_mutex
);
932 switch (args
->param
) {
933 case I915_CONTEXT_PARAM_BAN_PERIOD
:
936 else if (args
->value
< ctx
->hang_stats
.ban_period_seconds
&&
937 !capable(CAP_SYS_ADMIN
))
940 ctx
->hang_stats
.ban_period_seconds
= args
->value
;
946 mutex_unlock(&dev
->struct_mutex
);