2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/dma_remapping.h>
39 struct hlist_head buckets
[0];
42 static struct eb_objects
*
45 struct eb_objects
*eb
;
46 int count
= PAGE_SIZE
/ sizeof(struct hlist_head
) / 2;
49 eb
= kzalloc(count
*sizeof(struct hlist_head
) +
50 sizeof(struct eb_objects
),
60 eb_reset(struct eb_objects
*eb
)
62 memset(eb
->buckets
, 0, (eb
->and+1)*sizeof(struct hlist_head
));
66 eb_add_object(struct eb_objects
*eb
, struct drm_i915_gem_object
*obj
)
68 hlist_add_head(&obj
->exec_node
,
69 &eb
->buckets
[obj
->exec_handle
& eb
->and]);
72 static struct drm_i915_gem_object
*
73 eb_get_object(struct eb_objects
*eb
, unsigned long handle
)
75 struct hlist_head
*head
;
76 struct hlist_node
*node
;
77 struct drm_i915_gem_object
*obj
;
79 head
= &eb
->buckets
[handle
& eb
->and];
80 hlist_for_each(node
, head
) {
81 obj
= hlist_entry(node
, struct drm_i915_gem_object
, exec_node
);
82 if (obj
->exec_handle
== handle
)
90 eb_destroy(struct eb_objects
*eb
)
95 static inline int use_cpu_reloc(struct drm_i915_gem_object
*obj
)
97 return (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
||
98 !obj
->map_and_fenceable
||
99 obj
->cache_level
!= I915_CACHE_NONE
);
103 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object
*obj
,
104 struct eb_objects
*eb
,
105 struct drm_i915_gem_relocation_entry
*reloc
)
107 struct drm_device
*dev
= obj
->base
.dev
;
108 struct drm_gem_object
*target_obj
;
109 struct drm_i915_gem_object
*target_i915_obj
;
110 uint32_t target_offset
;
113 /* we've already hold a reference to all valid objects */
114 target_obj
= &eb_get_object(eb
, reloc
->target_handle
)->base
;
115 if (unlikely(target_obj
== NULL
))
118 target_i915_obj
= to_intel_bo(target_obj
);
119 target_offset
= target_i915_obj
->gtt_offset
;
121 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
122 * pipe_control writes because the gpu doesn't properly redirect them
123 * through the ppgtt for non_secure batchbuffers. */
124 if (unlikely(IS_GEN6(dev
) &&
125 reloc
->write_domain
== I915_GEM_DOMAIN_INSTRUCTION
&&
126 !target_i915_obj
->has_global_gtt_mapping
)) {
127 i915_gem_gtt_bind_object(target_i915_obj
,
128 target_i915_obj
->cache_level
);
131 /* The target buffer should have appeared before us in the
132 * exec_object list, so it should have a GTT space bound by now.
134 if (unlikely(target_offset
== 0)) {
135 DRM_DEBUG("No GTT space found for object %d\n",
136 reloc
->target_handle
);
140 /* Validate that the target is in a valid r/w GPU domain */
141 if (unlikely(reloc
->write_domain
& (reloc
->write_domain
- 1))) {
142 DRM_DEBUG("reloc with multiple write domains: "
143 "obj %p target %d offset %d "
144 "read %08x write %08x",
145 obj
, reloc
->target_handle
,
148 reloc
->write_domain
);
151 if (unlikely((reloc
->write_domain
| reloc
->read_domains
)
152 & ~I915_GEM_GPU_DOMAINS
)) {
153 DRM_DEBUG("reloc with read/write non-GPU domains: "
154 "obj %p target %d offset %d "
155 "read %08x write %08x",
156 obj
, reloc
->target_handle
,
159 reloc
->write_domain
);
162 if (unlikely(reloc
->write_domain
&& target_obj
->pending_write_domain
&&
163 reloc
->write_domain
!= target_obj
->pending_write_domain
)) {
164 DRM_DEBUG("Write domain conflict: "
165 "obj %p target %d offset %d "
166 "new %08x old %08x\n",
167 obj
, reloc
->target_handle
,
170 target_obj
->pending_write_domain
);
174 target_obj
->pending_read_domains
|= reloc
->read_domains
;
175 target_obj
->pending_write_domain
|= reloc
->write_domain
;
177 /* If the relocation already has the right value in it, no
178 * more work needs to be done.
180 if (target_offset
== reloc
->presumed_offset
)
183 /* Check that the relocation address is valid... */
184 if (unlikely(reloc
->offset
> obj
->base
.size
- 4)) {
185 DRM_DEBUG("Relocation beyond object bounds: "
186 "obj %p target %d offset %d size %d.\n",
187 obj
, reloc
->target_handle
,
189 (int) obj
->base
.size
);
192 if (unlikely(reloc
->offset
& 3)) {
193 DRM_DEBUG("Relocation not 4-byte aligned: "
194 "obj %p target %d offset %d.\n",
195 obj
, reloc
->target_handle
,
196 (int) reloc
->offset
);
200 /* We can't wait for rendering with pagefaults disabled */
201 if (obj
->active
&& in_atomic())
204 reloc
->delta
+= target_offset
;
205 if (use_cpu_reloc(obj
)) {
206 uint32_t page_offset
= reloc
->offset
& ~PAGE_MASK
;
209 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
213 vaddr
= kmap_atomic(i915_gem_object_get_page(obj
,
214 reloc
->offset
>> PAGE_SHIFT
));
215 *(uint32_t *)(vaddr
+ page_offset
) = reloc
->delta
;
216 kunmap_atomic(vaddr
);
218 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
219 uint32_t __iomem
*reloc_entry
;
220 void __iomem
*reloc_page
;
222 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
226 ret
= i915_gem_object_put_fence(obj
);
230 /* Map the page containing the relocation we're going to perform. */
231 reloc
->offset
+= obj
->gtt_offset
;
232 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
233 reloc
->offset
& PAGE_MASK
);
234 reloc_entry
= (uint32_t __iomem
*)
235 (reloc_page
+ (reloc
->offset
& ~PAGE_MASK
));
236 iowrite32(reloc
->delta
, reloc_entry
);
237 io_mapping_unmap_atomic(reloc_page
);
240 /* and update the user's relocation entry */
241 reloc
->presumed_offset
= target_offset
;
247 i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object
*obj
,
248 struct eb_objects
*eb
)
250 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
251 struct drm_i915_gem_relocation_entry stack_reloc
[N_RELOC(512)];
252 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
253 struct drm_i915_gem_exec_object2
*entry
= obj
->exec_entry
;
256 user_relocs
= (void __user
*)(uintptr_t)entry
->relocs_ptr
;
258 remain
= entry
->relocation_count
;
260 struct drm_i915_gem_relocation_entry
*r
= stack_reloc
;
262 if (count
> ARRAY_SIZE(stack_reloc
))
263 count
= ARRAY_SIZE(stack_reloc
);
266 if (__copy_from_user_inatomic(r
, user_relocs
, count
*sizeof(r
[0])))
270 u64 offset
= r
->presumed_offset
;
272 ret
= i915_gem_execbuffer_relocate_entry(obj
, eb
, r
);
276 if (r
->presumed_offset
!= offset
&&
277 __copy_to_user_inatomic(&user_relocs
->presumed_offset
,
279 sizeof(r
->presumed_offset
))) {
293 i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object
*obj
,
294 struct eb_objects
*eb
,
295 struct drm_i915_gem_relocation_entry
*relocs
)
297 const struct drm_i915_gem_exec_object2
*entry
= obj
->exec_entry
;
300 for (i
= 0; i
< entry
->relocation_count
; i
++) {
301 ret
= i915_gem_execbuffer_relocate_entry(obj
, eb
, &relocs
[i
]);
310 i915_gem_execbuffer_relocate(struct drm_device
*dev
,
311 struct eb_objects
*eb
,
312 struct list_head
*objects
)
314 struct drm_i915_gem_object
*obj
;
317 /* This is the fast path and we cannot handle a pagefault whilst
318 * holding the struct mutex lest the user pass in the relocations
319 * contained within a mmaped bo. For in such a case we, the page
320 * fault handler would call i915_gem_fault() and we would try to
321 * acquire the struct mutex again. Obviously this is bad and so
322 * lockdep complains vehemently.
325 list_for_each_entry(obj
, objects
, exec_list
) {
326 ret
= i915_gem_execbuffer_relocate_object(obj
, eb
);
335 #define __EXEC_OBJECT_HAS_PIN (1<<31)
336 #define __EXEC_OBJECT_HAS_FENCE (1<<30)
339 need_reloc_mappable(struct drm_i915_gem_object
*obj
)
341 struct drm_i915_gem_exec_object2
*entry
= obj
->exec_entry
;
342 return entry
->relocation_count
&& !use_cpu_reloc(obj
);
346 i915_gem_execbuffer_reserve_object(struct drm_i915_gem_object
*obj
,
347 struct intel_ring_buffer
*ring
)
349 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
350 struct drm_i915_gem_exec_object2
*entry
= obj
->exec_entry
;
351 bool has_fenced_gpu_access
= INTEL_INFO(ring
->dev
)->gen
< 4;
352 bool need_fence
, need_mappable
;
356 has_fenced_gpu_access
&&
357 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
358 obj
->tiling_mode
!= I915_TILING_NONE
;
359 need_mappable
= need_fence
|| need_reloc_mappable(obj
);
361 ret
= i915_gem_object_pin(obj
, entry
->alignment
, need_mappable
, false);
365 entry
->flags
|= __EXEC_OBJECT_HAS_PIN
;
367 if (has_fenced_gpu_access
) {
368 if (entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
) {
369 ret
= i915_gem_object_get_fence(obj
);
373 if (i915_gem_object_pin_fence(obj
))
374 entry
->flags
|= __EXEC_OBJECT_HAS_FENCE
;
376 obj
->pending_fenced_gpu_access
= true;
380 /* Ensure ppgtt mapping exists if needed */
381 if (dev_priv
->mm
.aliasing_ppgtt
&& !obj
->has_aliasing_ppgtt_mapping
) {
382 i915_ppgtt_bind_object(dev_priv
->mm
.aliasing_ppgtt
,
383 obj
, obj
->cache_level
);
385 obj
->has_aliasing_ppgtt_mapping
= 1;
388 entry
->offset
= obj
->gtt_offset
;
393 i915_gem_execbuffer_unreserve_object(struct drm_i915_gem_object
*obj
)
395 struct drm_i915_gem_exec_object2
*entry
;
400 entry
= obj
->exec_entry
;
402 if (entry
->flags
& __EXEC_OBJECT_HAS_FENCE
)
403 i915_gem_object_unpin_fence(obj
);
405 if (entry
->flags
& __EXEC_OBJECT_HAS_PIN
)
406 i915_gem_object_unpin(obj
);
408 entry
->flags
&= ~(__EXEC_OBJECT_HAS_FENCE
| __EXEC_OBJECT_HAS_PIN
);
412 i915_gem_execbuffer_reserve(struct intel_ring_buffer
*ring
,
413 struct drm_file
*file
,
414 struct list_head
*objects
)
416 struct drm_i915_gem_object
*obj
;
417 struct list_head ordered_objects
;
418 bool has_fenced_gpu_access
= INTEL_INFO(ring
->dev
)->gen
< 4;
421 INIT_LIST_HEAD(&ordered_objects
);
422 while (!list_empty(objects
)) {
423 struct drm_i915_gem_exec_object2
*entry
;
424 bool need_fence
, need_mappable
;
426 obj
= list_first_entry(objects
,
427 struct drm_i915_gem_object
,
429 entry
= obj
->exec_entry
;
432 has_fenced_gpu_access
&&
433 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
434 obj
->tiling_mode
!= I915_TILING_NONE
;
435 need_mappable
= need_fence
|| need_reloc_mappable(obj
);
438 list_move(&obj
->exec_list
, &ordered_objects
);
440 list_move_tail(&obj
->exec_list
, &ordered_objects
);
442 obj
->base
.pending_read_domains
= 0;
443 obj
->base
.pending_write_domain
= 0;
444 obj
->pending_fenced_gpu_access
= false;
446 list_splice(&ordered_objects
, objects
);
448 /* Attempt to pin all of the buffers into the GTT.
449 * This is done in 3 phases:
451 * 1a. Unbind all objects that do not match the GTT constraints for
452 * the execbuffer (fenceable, mappable, alignment etc).
453 * 1b. Increment pin count for already bound objects.
454 * 2. Bind new objects.
455 * 3. Decrement pin count.
457 * This avoid unnecessary unbinding of later objects in order to make
458 * room for the earlier objects *unless* we need to defragment.
464 /* Unbind any ill-fitting objects or pin. */
465 list_for_each_entry(obj
, objects
, exec_list
) {
466 struct drm_i915_gem_exec_object2
*entry
= obj
->exec_entry
;
467 bool need_fence
, need_mappable
;
473 has_fenced_gpu_access
&&
474 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
475 obj
->tiling_mode
!= I915_TILING_NONE
;
476 need_mappable
= need_fence
|| need_reloc_mappable(obj
);
478 if ((entry
->alignment
&& obj
->gtt_offset
& (entry
->alignment
- 1)) ||
479 (need_mappable
&& !obj
->map_and_fenceable
))
480 ret
= i915_gem_object_unbind(obj
);
482 ret
= i915_gem_execbuffer_reserve_object(obj
, ring
);
487 /* Bind fresh objects */
488 list_for_each_entry(obj
, objects
, exec_list
) {
492 ret
= i915_gem_execbuffer_reserve_object(obj
, ring
);
497 err
: /* Decrement pin count for bound objects */
498 list_for_each_entry(obj
, objects
, exec_list
)
499 i915_gem_execbuffer_unreserve_object(obj
);
501 if (ret
!= -ENOSPC
|| retry
++)
504 ret
= i915_gem_evict_everything(ring
->dev
);
511 i915_gem_execbuffer_relocate_slow(struct drm_device
*dev
,
512 struct drm_file
*file
,
513 struct intel_ring_buffer
*ring
,
514 struct list_head
*objects
,
515 struct eb_objects
*eb
,
516 struct drm_i915_gem_exec_object2
*exec
,
519 struct drm_i915_gem_relocation_entry
*reloc
;
520 struct drm_i915_gem_object
*obj
;
524 /* We may process another execbuffer during the unlock... */
525 while (!list_empty(objects
)) {
526 obj
= list_first_entry(objects
,
527 struct drm_i915_gem_object
,
529 list_del_init(&obj
->exec_list
);
530 drm_gem_object_unreference(&obj
->base
);
533 mutex_unlock(&dev
->struct_mutex
);
536 for (i
= 0; i
< count
; i
++)
537 total
+= exec
[i
].relocation_count
;
539 reloc_offset
= drm_malloc_ab(count
, sizeof(*reloc_offset
));
540 reloc
= drm_malloc_ab(total
, sizeof(*reloc
));
541 if (reloc
== NULL
|| reloc_offset
== NULL
) {
542 drm_free_large(reloc
);
543 drm_free_large(reloc_offset
);
544 mutex_lock(&dev
->struct_mutex
);
549 for (i
= 0; i
< count
; i
++) {
550 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
552 user_relocs
= (void __user
*)(uintptr_t)exec
[i
].relocs_ptr
;
554 if (copy_from_user(reloc
+total
, user_relocs
,
555 exec
[i
].relocation_count
* sizeof(*reloc
))) {
557 mutex_lock(&dev
->struct_mutex
);
561 reloc_offset
[i
] = total
;
562 total
+= exec
[i
].relocation_count
;
565 ret
= i915_mutex_lock_interruptible(dev
);
567 mutex_lock(&dev
->struct_mutex
);
571 /* reacquire the objects */
573 for (i
= 0; i
< count
; i
++) {
574 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
,
576 if (&obj
->base
== NULL
) {
577 DRM_DEBUG("Invalid object handle %d at index %d\n",
583 list_add_tail(&obj
->exec_list
, objects
);
584 obj
->exec_handle
= exec
[i
].handle
;
585 obj
->exec_entry
= &exec
[i
];
586 eb_add_object(eb
, obj
);
589 ret
= i915_gem_execbuffer_reserve(ring
, file
, objects
);
593 list_for_each_entry(obj
, objects
, exec_list
) {
594 int offset
= obj
->exec_entry
- exec
;
595 ret
= i915_gem_execbuffer_relocate_object_slow(obj
, eb
,
596 reloc
+ reloc_offset
[offset
]);
601 /* Leave the user relocations as are, this is the painfully slow path,
602 * and we want to avoid the complication of dropping the lock whilst
603 * having buffers reserved in the aperture and so causing spurious
604 * ENOSPC for random operations.
608 drm_free_large(reloc
);
609 drm_free_large(reloc_offset
);
614 i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer
*ring
, u32 flips
)
616 u32 plane
, flip_mask
;
619 /* Check for any pending flips. As we only maintain a flip queue depth
620 * of 1, we can simply insert a WAIT for the next display flip prior
621 * to executing the batch and avoid stalling the CPU.
624 for (plane
= 0; flips
>> plane
; plane
++) {
625 if (((flips
>> plane
) & 1) == 0)
629 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
631 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
633 ret
= intel_ring_begin(ring
, 2);
637 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
638 intel_ring_emit(ring
, MI_NOOP
);
639 intel_ring_advance(ring
);
646 i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer
*ring
,
647 struct list_head
*objects
)
649 struct drm_i915_gem_object
*obj
;
650 uint32_t flush_domains
= 0;
654 list_for_each_entry(obj
, objects
, exec_list
) {
655 ret
= i915_gem_object_sync(obj
, ring
);
659 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
660 i915_gem_clflush_object(obj
);
662 if (obj
->base
.pending_write_domain
)
663 flips
|= atomic_read(&obj
->pending_flip
);
665 flush_domains
|= obj
->base
.write_domain
;
669 ret
= i915_gem_execbuffer_wait_for_flips(ring
, flips
);
674 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
675 intel_gtt_chipset_flush();
677 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
680 /* Unconditionally invalidate gpu caches and ensure that we do flush
681 * any residual writes from the previous batch.
683 return intel_ring_invalidate_all_caches(ring
);
687 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2
*exec
)
689 return ((exec
->batch_start_offset
| exec
->batch_len
) & 0x7) == 0;
693 validate_exec_list(struct drm_i915_gem_exec_object2
*exec
,
698 for (i
= 0; i
< count
; i
++) {
699 char __user
*ptr
= (char __user
*)(uintptr_t)exec
[i
].relocs_ptr
;
700 int length
; /* limited by fault_in_pages_readable() */
702 /* First check for malicious input causing overflow */
703 if (exec
[i
].relocation_count
>
704 INT_MAX
/ sizeof(struct drm_i915_gem_relocation_entry
))
707 length
= exec
[i
].relocation_count
*
708 sizeof(struct drm_i915_gem_relocation_entry
);
709 if (!access_ok(VERIFY_READ
, ptr
, length
))
712 /* we may also need to update the presumed offsets */
713 if (!access_ok(VERIFY_WRITE
, ptr
, length
))
716 if (fault_in_multipages_readable(ptr
, length
))
724 i915_gem_execbuffer_move_to_active(struct list_head
*objects
,
725 struct intel_ring_buffer
*ring
,
728 struct drm_i915_gem_object
*obj
;
730 list_for_each_entry(obj
, objects
, exec_list
) {
731 u32 old_read
= obj
->base
.read_domains
;
732 u32 old_write
= obj
->base
.write_domain
;
734 obj
->base
.read_domains
= obj
->base
.pending_read_domains
;
735 obj
->base
.write_domain
= obj
->base
.pending_write_domain
;
736 obj
->fenced_gpu_access
= obj
->pending_fenced_gpu_access
;
738 i915_gem_object_move_to_active(obj
, ring
, seqno
);
739 if (obj
->base
.write_domain
) {
741 obj
->last_write_seqno
= seqno
;
742 if (obj
->pin_count
) /* check for potential scanout */
743 intel_mark_fb_busy(obj
);
746 trace_i915_gem_object_change_domain(obj
, old_read
, old_write
);
751 i915_gem_execbuffer_retire_commands(struct drm_device
*dev
,
752 struct drm_file
*file
,
753 struct intel_ring_buffer
*ring
)
755 /* Unconditionally force add_request to emit a full flush. */
756 ring
->gpu_caches_dirty
= true;
758 /* Add a breadcrumb for the completion of the batch buffer */
759 (void)i915_add_request(ring
, file
, NULL
);
763 i915_reset_gen7_sol_offsets(struct drm_device
*dev
,
764 struct intel_ring_buffer
*ring
)
766 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
769 if (!IS_GEN7(dev
) || ring
!= &dev_priv
->ring
[RCS
])
772 ret
= intel_ring_begin(ring
, 4 * 3);
776 for (i
= 0; i
< 4; i
++) {
777 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
778 intel_ring_emit(ring
, GEN7_SO_WRITE_OFFSET(i
));
779 intel_ring_emit(ring
, 0);
782 intel_ring_advance(ring
);
788 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
789 struct drm_file
*file
,
790 struct drm_i915_gem_execbuffer2
*args
,
791 struct drm_i915_gem_exec_object2
*exec
)
793 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
794 struct list_head objects
;
795 struct eb_objects
*eb
;
796 struct drm_i915_gem_object
*batch_obj
;
797 struct drm_clip_rect
*cliprects
= NULL
;
798 struct intel_ring_buffer
*ring
;
799 u32 ctx_id
= i915_execbuffer2_get_context_id(*args
);
800 u32 exec_start
, exec_len
;
805 if (!i915_gem_check_execbuffer(args
)) {
806 DRM_DEBUG("execbuf with invalid offset/length\n");
810 ret
= validate_exec_list(exec
, args
->buffer_count
);
814 switch (args
->flags
& I915_EXEC_RING_MASK
) {
815 case I915_EXEC_DEFAULT
:
816 case I915_EXEC_RENDER
:
817 ring
= &dev_priv
->ring
[RCS
];
820 ring
= &dev_priv
->ring
[VCS
];
822 DRM_DEBUG("Ring %s doesn't support contexts\n",
828 ring
= &dev_priv
->ring
[BCS
];
830 DRM_DEBUG("Ring %s doesn't support contexts\n",
836 DRM_DEBUG("execbuf with unknown ring: %d\n",
837 (int)(args
->flags
& I915_EXEC_RING_MASK
));
840 if (!intel_ring_initialized(ring
)) {
841 DRM_DEBUG("execbuf with invalid ring: %d\n",
842 (int)(args
->flags
& I915_EXEC_RING_MASK
));
846 mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
847 mask
= I915_EXEC_CONSTANTS_MASK
;
849 case I915_EXEC_CONSTANTS_REL_GENERAL
:
850 case I915_EXEC_CONSTANTS_ABSOLUTE
:
851 case I915_EXEC_CONSTANTS_REL_SURFACE
:
852 if (ring
== &dev_priv
->ring
[RCS
] &&
853 mode
!= dev_priv
->relative_constants_mode
) {
854 if (INTEL_INFO(dev
)->gen
< 4)
857 if (INTEL_INFO(dev
)->gen
> 5 &&
858 mode
== I915_EXEC_CONSTANTS_REL_SURFACE
)
861 /* The HW changed the meaning on this bit on gen6 */
862 if (INTEL_INFO(dev
)->gen
>= 6)
863 mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
867 DRM_DEBUG("execbuf with unknown constants: %d\n", mode
);
871 if (args
->buffer_count
< 1) {
872 DRM_DEBUG("execbuf with %d buffers\n", args
->buffer_count
);
876 if (args
->num_cliprects
!= 0) {
877 if (ring
!= &dev_priv
->ring
[RCS
]) {
878 DRM_DEBUG("clip rectangles are only valid with the render ring\n");
882 if (INTEL_INFO(dev
)->gen
>= 5) {
883 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
887 if (args
->num_cliprects
> UINT_MAX
/ sizeof(*cliprects
)) {
888 DRM_DEBUG("execbuf with %u cliprects\n",
889 args
->num_cliprects
);
893 cliprects
= kmalloc(args
->num_cliprects
* sizeof(*cliprects
),
895 if (cliprects
== NULL
) {
900 if (copy_from_user(cliprects
,
901 (struct drm_clip_rect __user
*)(uintptr_t)
903 sizeof(*cliprects
)*args
->num_cliprects
)) {
909 ret
= i915_mutex_lock_interruptible(dev
);
913 if (dev_priv
->mm
.suspended
) {
914 mutex_unlock(&dev
->struct_mutex
);
919 eb
= eb_create(args
->buffer_count
);
921 mutex_unlock(&dev
->struct_mutex
);
926 /* Look up object handles */
927 INIT_LIST_HEAD(&objects
);
928 for (i
= 0; i
< args
->buffer_count
; i
++) {
929 struct drm_i915_gem_object
*obj
;
931 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
,
933 if (&obj
->base
== NULL
) {
934 DRM_DEBUG("Invalid object handle %d at index %d\n",
936 /* prevent error path from reading uninitialized data */
941 if (!list_empty(&obj
->exec_list
)) {
942 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
943 obj
, exec
[i
].handle
, i
);
948 list_add_tail(&obj
->exec_list
, &objects
);
949 obj
->exec_handle
= exec
[i
].handle
;
950 obj
->exec_entry
= &exec
[i
];
951 eb_add_object(eb
, obj
);
954 /* take note of the batch buffer before we might reorder the lists */
955 batch_obj
= list_entry(objects
.prev
,
956 struct drm_i915_gem_object
,
959 /* Move the objects en-masse into the GTT, evicting if necessary. */
960 ret
= i915_gem_execbuffer_reserve(ring
, file
, &objects
);
964 /* The objects are in their final locations, apply the relocations. */
965 ret
= i915_gem_execbuffer_relocate(dev
, eb
, &objects
);
967 if (ret
== -EFAULT
) {
968 ret
= i915_gem_execbuffer_relocate_slow(dev
, file
, ring
,
972 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
978 /* Set the pending read domains for the batch buffer to COMMAND */
979 if (batch_obj
->base
.pending_write_domain
) {
980 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
984 batch_obj
->base
.pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
986 ret
= i915_gem_execbuffer_move_to_gpu(ring
, &objects
);
990 seqno
= i915_gem_next_request_seqno(ring
);
991 for (i
= 0; i
< ARRAY_SIZE(ring
->sync_seqno
); i
++) {
992 if (seqno
< ring
->sync_seqno
[i
]) {
993 /* The GPU can not handle its semaphore value wrapping,
994 * so every billion or so execbuffers, we need to stall
995 * the GPU in order to reset the counters.
997 ret
= i915_gpu_idle(dev
);
1000 i915_gem_retire_requests(dev
);
1002 BUG_ON(ring
->sync_seqno
[i
]);
1006 ret
= i915_switch_context(ring
, file
, ctx_id
);
1010 if (ring
== &dev_priv
->ring
[RCS
] &&
1011 mode
!= dev_priv
->relative_constants_mode
) {
1012 ret
= intel_ring_begin(ring
, 4);
1016 intel_ring_emit(ring
, MI_NOOP
);
1017 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
1018 intel_ring_emit(ring
, INSTPM
);
1019 intel_ring_emit(ring
, mask
<< 16 | mode
);
1020 intel_ring_advance(ring
);
1022 dev_priv
->relative_constants_mode
= mode
;
1025 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
1026 ret
= i915_reset_gen7_sol_offsets(dev
, ring
);
1031 trace_i915_gem_ring_dispatch(ring
, seqno
);
1033 exec_start
= batch_obj
->gtt_offset
+ args
->batch_start_offset
;
1034 exec_len
= args
->batch_len
;
1036 for (i
= 0; i
< args
->num_cliprects
; i
++) {
1037 ret
= i915_emit_box(dev
, &cliprects
[i
],
1038 args
->DR1
, args
->DR4
);
1042 ret
= ring
->dispatch_execbuffer(ring
,
1043 exec_start
, exec_len
);
1048 ret
= ring
->dispatch_execbuffer(ring
, exec_start
, exec_len
);
1053 i915_gem_execbuffer_move_to_active(&objects
, ring
, seqno
);
1054 i915_gem_execbuffer_retire_commands(dev
, file
, ring
);
1058 while (!list_empty(&objects
)) {
1059 struct drm_i915_gem_object
*obj
;
1061 obj
= list_first_entry(&objects
,
1062 struct drm_i915_gem_object
,
1064 list_del_init(&obj
->exec_list
);
1065 drm_gem_object_unreference(&obj
->base
);
1068 mutex_unlock(&dev
->struct_mutex
);
1076 * Legacy execbuffer just creates an exec2 list from the original exec object
1077 * list array and passes it to the real function.
1080 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1081 struct drm_file
*file
)
1083 struct drm_i915_gem_execbuffer
*args
= data
;
1084 struct drm_i915_gem_execbuffer2 exec2
;
1085 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
1086 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
1089 if (args
->buffer_count
< 1) {
1090 DRM_DEBUG("execbuf with %d buffers\n", args
->buffer_count
);
1094 /* Copy in the exec list from userland */
1095 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
1096 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
1097 if (exec_list
== NULL
|| exec2_list
== NULL
) {
1098 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1099 args
->buffer_count
);
1100 drm_free_large(exec_list
);
1101 drm_free_large(exec2_list
);
1104 ret
= copy_from_user(exec_list
,
1105 (void __user
*)(uintptr_t)args
->buffers_ptr
,
1106 sizeof(*exec_list
) * args
->buffer_count
);
1108 DRM_DEBUG("copy %d exec entries failed %d\n",
1109 args
->buffer_count
, ret
);
1110 drm_free_large(exec_list
);
1111 drm_free_large(exec2_list
);
1115 for (i
= 0; i
< args
->buffer_count
; i
++) {
1116 exec2_list
[i
].handle
= exec_list
[i
].handle
;
1117 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
1118 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
1119 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
1120 exec2_list
[i
].offset
= exec_list
[i
].offset
;
1121 if (INTEL_INFO(dev
)->gen
< 4)
1122 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
1124 exec2_list
[i
].flags
= 0;
1127 exec2
.buffers_ptr
= args
->buffers_ptr
;
1128 exec2
.buffer_count
= args
->buffer_count
;
1129 exec2
.batch_start_offset
= args
->batch_start_offset
;
1130 exec2
.batch_len
= args
->batch_len
;
1131 exec2
.DR1
= args
->DR1
;
1132 exec2
.DR4
= args
->DR4
;
1133 exec2
.num_cliprects
= args
->num_cliprects
;
1134 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
1135 exec2
.flags
= I915_EXEC_RENDER
;
1136 i915_execbuffer2_set_context_id(exec2
, 0);
1138 ret
= i915_gem_do_execbuffer(dev
, data
, file
, &exec2
, exec2_list
);
1140 /* Copy the new buffer offsets back to the user's exec list. */
1141 for (i
= 0; i
< args
->buffer_count
; i
++)
1142 exec_list
[i
].offset
= exec2_list
[i
].offset
;
1143 /* ... and back out to userspace */
1144 ret
= copy_to_user((void __user
*)(uintptr_t)args
->buffers_ptr
,
1146 sizeof(*exec_list
) * args
->buffer_count
);
1149 DRM_DEBUG("failed to copy %d exec entries "
1150 "back to user (%d)\n",
1151 args
->buffer_count
, ret
);
1155 drm_free_large(exec_list
);
1156 drm_free_large(exec2_list
);
1161 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1162 struct drm_file
*file
)
1164 struct drm_i915_gem_execbuffer2
*args
= data
;
1165 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
1168 if (args
->buffer_count
< 1 ||
1169 args
->buffer_count
> UINT_MAX
/ sizeof(*exec2_list
)) {
1170 DRM_DEBUG("execbuf2 with %d buffers\n", args
->buffer_count
);
1174 exec2_list
= kmalloc(sizeof(*exec2_list
)*args
->buffer_count
,
1175 GFP_KERNEL
| __GFP_NOWARN
| __GFP_NORETRY
);
1176 if (exec2_list
== NULL
)
1177 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
),
1178 args
->buffer_count
);
1179 if (exec2_list
== NULL
) {
1180 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1181 args
->buffer_count
);
1184 ret
= copy_from_user(exec2_list
,
1185 (struct drm_i915_relocation_entry __user
*)
1186 (uintptr_t) args
->buffers_ptr
,
1187 sizeof(*exec2_list
) * args
->buffer_count
);
1189 DRM_DEBUG("copy %d exec entries failed %d\n",
1190 args
->buffer_count
, ret
);
1191 drm_free_large(exec2_list
);
1195 ret
= i915_gem_do_execbuffer(dev
, data
, file
, args
, exec2_list
);
1197 /* Copy the new buffer offsets back to the user's exec list. */
1198 ret
= copy_to_user((void __user
*)(uintptr_t)args
->buffers_ptr
,
1200 sizeof(*exec2_list
) * args
->buffer_count
);
1203 DRM_DEBUG("failed to copy %d exec entries "
1204 "back to user (%d)\n",
1205 args
->buffer_count
, ret
);
1209 drm_free_large(exec2_list
);