2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/dma_remapping.h>
35 #include <linux/uaccess.h>
37 #define __EXEC_OBJECT_HAS_PIN (1<<31)
38 #define __EXEC_OBJECT_HAS_FENCE (1<<30)
39 #define __EXEC_OBJECT_NEEDS_MAP (1<<29)
40 #define __EXEC_OBJECT_NEEDS_BIAS (1<<28)
42 #define BATCH_OFFSET_BIAS (256*1024)
45 struct list_head vmas
;
48 struct i915_vma
*lut
[0];
49 struct hlist_head buckets
[0];
53 static struct eb_vmas
*
54 eb_create(struct drm_i915_gem_execbuffer2
*args
)
56 struct eb_vmas
*eb
= NULL
;
58 if (args
->flags
& I915_EXEC_HANDLE_LUT
) {
59 unsigned size
= args
->buffer_count
;
60 size
*= sizeof(struct i915_vma
*);
61 size
+= sizeof(struct eb_vmas
);
62 eb
= kmalloc(size
, GFP_TEMPORARY
| __GFP_NOWARN
| __GFP_NORETRY
);
66 unsigned size
= args
->buffer_count
;
67 unsigned count
= PAGE_SIZE
/ sizeof(struct hlist_head
) / 2;
68 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE
/ sizeof(struct hlist_head
));
69 while (count
> 2*size
)
71 eb
= kzalloc(count
*sizeof(struct hlist_head
) +
72 sizeof(struct eb_vmas
),
79 eb
->and = -args
->buffer_count
;
81 INIT_LIST_HEAD(&eb
->vmas
);
86 eb_reset(struct eb_vmas
*eb
)
89 memset(eb
->buckets
, 0, (eb
->and+1)*sizeof(struct hlist_head
));
93 eb_lookup_vmas(struct eb_vmas
*eb
,
94 struct drm_i915_gem_exec_object2
*exec
,
95 const struct drm_i915_gem_execbuffer2
*args
,
96 struct i915_address_space
*vm
,
97 struct drm_file
*file
)
99 struct drm_i915_gem_object
*obj
;
100 struct list_head objects
;
103 INIT_LIST_HEAD(&objects
);
104 spin_lock(&file
->table_lock
);
105 /* Grab a reference to the object and release the lock so we can lookup
106 * or create the VMA without using GFP_ATOMIC */
107 for (i
= 0; i
< args
->buffer_count
; i
++) {
108 obj
= to_intel_bo(idr_find(&file
->object_idr
, exec
[i
].handle
));
110 spin_unlock(&file
->table_lock
);
111 DRM_DEBUG("Invalid object handle %d at index %d\n",
117 if (!list_empty(&obj
->obj_exec_link
)) {
118 spin_unlock(&file
->table_lock
);
119 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
120 obj
, exec
[i
].handle
, i
);
125 drm_gem_object_reference(&obj
->base
);
126 list_add_tail(&obj
->obj_exec_link
, &objects
);
128 spin_unlock(&file
->table_lock
);
131 while (!list_empty(&objects
)) {
132 struct i915_vma
*vma
;
134 obj
= list_first_entry(&objects
,
135 struct drm_i915_gem_object
,
139 * NOTE: We can leak any vmas created here when something fails
140 * later on. But that's no issue since vma_unbind can deal with
141 * vmas which are not actually bound. And since only
142 * lookup_or_create exists as an interface to get at the vma
143 * from the (obj, vm) we don't run the risk of creating
144 * duplicated vmas for the same vm.
146 vma
= i915_gem_obj_lookup_or_create_vma(obj
, vm
);
148 DRM_DEBUG("Failed to lookup VMA\n");
153 /* Transfer ownership from the objects list to the vmas list. */
154 list_add_tail(&vma
->exec_list
, &eb
->vmas
);
155 list_del_init(&obj
->obj_exec_link
);
157 vma
->exec_entry
= &exec
[i
];
161 uint32_t handle
= args
->flags
& I915_EXEC_HANDLE_LUT
? i
: exec
[i
].handle
;
162 vma
->exec_handle
= handle
;
163 hlist_add_head(&vma
->exec_node
,
164 &eb
->buckets
[handle
& eb
->and]);
173 while (!list_empty(&objects
)) {
174 obj
= list_first_entry(&objects
,
175 struct drm_i915_gem_object
,
177 list_del_init(&obj
->obj_exec_link
);
178 drm_gem_object_unreference(&obj
->base
);
181 * Objects already transfered to the vmas list will be unreferenced by
188 static struct i915_vma
*eb_get_vma(struct eb_vmas
*eb
, unsigned long handle
)
191 if (handle
>= -eb
->and)
193 return eb
->lut
[handle
];
195 struct hlist_head
*head
;
196 struct i915_vma
*vma
;
198 head
= &eb
->buckets
[handle
& eb
->and];
199 hlist_for_each_entry(vma
, head
, exec_node
) {
200 if (vma
->exec_handle
== handle
)
208 i915_gem_execbuffer_unreserve_vma(struct i915_vma
*vma
)
210 struct drm_i915_gem_exec_object2
*entry
;
211 struct drm_i915_gem_object
*obj
= vma
->obj
;
213 if (!drm_mm_node_allocated(&vma
->node
))
216 entry
= vma
->exec_entry
;
218 if (entry
->flags
& __EXEC_OBJECT_HAS_FENCE
)
219 i915_gem_object_unpin_fence(obj
);
221 if (entry
->flags
& __EXEC_OBJECT_HAS_PIN
)
224 entry
->flags
&= ~(__EXEC_OBJECT_HAS_FENCE
| __EXEC_OBJECT_HAS_PIN
);
227 static void eb_destroy(struct eb_vmas
*eb
)
229 while (!list_empty(&eb
->vmas
)) {
230 struct i915_vma
*vma
;
232 vma
= list_first_entry(&eb
->vmas
,
235 list_del_init(&vma
->exec_list
);
236 i915_gem_execbuffer_unreserve_vma(vma
);
237 drm_gem_object_unreference(&vma
->obj
->base
);
242 static inline int use_cpu_reloc(struct drm_i915_gem_object
*obj
)
244 return (HAS_LLC(obj
->base
.dev
) ||
245 obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
||
246 obj
->cache_level
!= I915_CACHE_NONE
);
249 /* Used to convert any address to canonical form.
250 * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
251 * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
252 * addresses to be in a canonical form:
253 * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
254 * canonical form [63:48] == [47]."
256 #define GEN8_HIGH_ADDRESS_BIT 47
257 static inline uint64_t gen8_canonical_addr(uint64_t address
)
259 return sign_extend64(address
, GEN8_HIGH_ADDRESS_BIT
);
262 static inline uint64_t gen8_noncanonical_addr(uint64_t address
)
264 return address
& ((1ULL << (GEN8_HIGH_ADDRESS_BIT
+ 1)) - 1);
267 static inline uint64_t
268 relocation_target(struct drm_i915_gem_relocation_entry
*reloc
,
269 uint64_t target_offset
)
271 return gen8_canonical_addr((int)reloc
->delta
+ target_offset
);
275 relocate_entry_cpu(struct drm_i915_gem_object
*obj
,
276 struct drm_i915_gem_relocation_entry
*reloc
,
277 uint64_t target_offset
)
279 struct drm_device
*dev
= obj
->base
.dev
;
280 uint32_t page_offset
= offset_in_page(reloc
->offset
);
281 uint64_t delta
= relocation_target(reloc
, target_offset
);
285 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
289 vaddr
= kmap_atomic(i915_gem_object_get_dirty_page(obj
,
290 reloc
->offset
>> PAGE_SHIFT
));
291 *(uint32_t *)(vaddr
+ page_offset
) = lower_32_bits(delta
);
293 if (INTEL_INFO(dev
)->gen
>= 8) {
294 page_offset
= offset_in_page(page_offset
+ sizeof(uint32_t));
296 if (page_offset
== 0) {
297 kunmap_atomic(vaddr
);
298 vaddr
= kmap_atomic(i915_gem_object_get_dirty_page(obj
,
299 (reloc
->offset
+ sizeof(uint32_t)) >> PAGE_SHIFT
));
302 *(uint32_t *)(vaddr
+ page_offset
) = upper_32_bits(delta
);
305 kunmap_atomic(vaddr
);
311 relocate_entry_gtt(struct drm_i915_gem_object
*obj
,
312 struct drm_i915_gem_relocation_entry
*reloc
,
313 uint64_t target_offset
)
315 struct drm_device
*dev
= obj
->base
.dev
;
316 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
317 uint64_t delta
= relocation_target(reloc
, target_offset
);
319 void __iomem
*reloc_page
;
322 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
326 ret
= i915_gem_object_put_fence(obj
);
330 /* Map the page containing the relocation we're going to perform. */
331 offset
= i915_gem_obj_ggtt_offset(obj
);
332 offset
+= reloc
->offset
;
333 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->gtt
.mappable
,
335 iowrite32(lower_32_bits(delta
), reloc_page
+ offset_in_page(offset
));
337 if (INTEL_INFO(dev
)->gen
>= 8) {
338 offset
+= sizeof(uint32_t);
340 if (offset_in_page(offset
) == 0) {
341 io_mapping_unmap_atomic(reloc_page
);
343 io_mapping_map_atomic_wc(dev_priv
->gtt
.mappable
,
347 iowrite32(upper_32_bits(delta
),
348 reloc_page
+ offset_in_page(offset
));
351 io_mapping_unmap_atomic(reloc_page
);
357 clflush_write32(void *addr
, uint32_t value
)
359 /* This is not a fast path, so KISS. */
360 drm_clflush_virt_range(addr
, sizeof(uint32_t));
361 *(uint32_t *)addr
= value
;
362 drm_clflush_virt_range(addr
, sizeof(uint32_t));
366 relocate_entry_clflush(struct drm_i915_gem_object
*obj
,
367 struct drm_i915_gem_relocation_entry
*reloc
,
368 uint64_t target_offset
)
370 struct drm_device
*dev
= obj
->base
.dev
;
371 uint32_t page_offset
= offset_in_page(reloc
->offset
);
372 uint64_t delta
= relocation_target(reloc
, target_offset
);
376 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
380 vaddr
= kmap_atomic(i915_gem_object_get_dirty_page(obj
,
381 reloc
->offset
>> PAGE_SHIFT
));
382 clflush_write32(vaddr
+ page_offset
, lower_32_bits(delta
));
384 if (INTEL_INFO(dev
)->gen
>= 8) {
385 page_offset
= offset_in_page(page_offset
+ sizeof(uint32_t));
387 if (page_offset
== 0) {
388 kunmap_atomic(vaddr
);
389 vaddr
= kmap_atomic(i915_gem_object_get_dirty_page(obj
,
390 (reloc
->offset
+ sizeof(uint32_t)) >> PAGE_SHIFT
));
393 clflush_write32(vaddr
+ page_offset
, upper_32_bits(delta
));
396 kunmap_atomic(vaddr
);
402 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object
*obj
,
404 struct drm_i915_gem_relocation_entry
*reloc
)
406 struct drm_device
*dev
= obj
->base
.dev
;
407 struct drm_gem_object
*target_obj
;
408 struct drm_i915_gem_object
*target_i915_obj
;
409 struct i915_vma
*target_vma
;
410 uint64_t target_offset
;
413 /* we've already hold a reference to all valid objects */
414 target_vma
= eb_get_vma(eb
, reloc
->target_handle
);
415 if (unlikely(target_vma
== NULL
))
417 target_i915_obj
= target_vma
->obj
;
418 target_obj
= &target_vma
->obj
->base
;
420 target_offset
= gen8_canonical_addr(target_vma
->node
.start
);
422 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
423 * pipe_control writes because the gpu doesn't properly redirect them
424 * through the ppgtt for non_secure batchbuffers. */
425 if (unlikely(IS_GEN6(dev
) &&
426 reloc
->write_domain
== I915_GEM_DOMAIN_INSTRUCTION
)) {
427 ret
= i915_vma_bind(target_vma
, target_i915_obj
->cache_level
,
429 if (WARN_ONCE(ret
, "Unexpected failure to bind target VMA!"))
433 /* Validate that the target is in a valid r/w GPU domain */
434 if (unlikely(reloc
->write_domain
& (reloc
->write_domain
- 1))) {
435 DRM_DEBUG("reloc with multiple write domains: "
436 "obj %p target %d offset %d "
437 "read %08x write %08x",
438 obj
, reloc
->target_handle
,
441 reloc
->write_domain
);
444 if (unlikely((reloc
->write_domain
| reloc
->read_domains
)
445 & ~I915_GEM_GPU_DOMAINS
)) {
446 DRM_DEBUG("reloc with read/write non-GPU domains: "
447 "obj %p target %d offset %d "
448 "read %08x write %08x",
449 obj
, reloc
->target_handle
,
452 reloc
->write_domain
);
456 target_obj
->pending_read_domains
|= reloc
->read_domains
;
457 target_obj
->pending_write_domain
|= reloc
->write_domain
;
459 /* If the relocation already has the right value in it, no
460 * more work needs to be done.
462 if (target_offset
== reloc
->presumed_offset
)
465 /* Check that the relocation address is valid... */
466 if (unlikely(reloc
->offset
>
467 obj
->base
.size
- (INTEL_INFO(dev
)->gen
>= 8 ? 8 : 4))) {
468 DRM_DEBUG("Relocation beyond object bounds: "
469 "obj %p target %d offset %d size %d.\n",
470 obj
, reloc
->target_handle
,
472 (int) obj
->base
.size
);
475 if (unlikely(reloc
->offset
& 3)) {
476 DRM_DEBUG("Relocation not 4-byte aligned: "
477 "obj %p target %d offset %d.\n",
478 obj
, reloc
->target_handle
,
479 (int) reloc
->offset
);
483 /* We can't wait for rendering with pagefaults disabled */
484 if (obj
->active
&& pagefault_disabled())
487 if (use_cpu_reloc(obj
))
488 ret
= relocate_entry_cpu(obj
, reloc
, target_offset
);
489 else if (obj
->map_and_fenceable
)
490 ret
= relocate_entry_gtt(obj
, reloc
, target_offset
);
491 else if (cpu_has_clflush
)
492 ret
= relocate_entry_clflush(obj
, reloc
, target_offset
);
494 WARN_ONCE(1, "Impossible case in relocation handling\n");
501 /* and update the user's relocation entry */
502 reloc
->presumed_offset
= target_offset
;
508 i915_gem_execbuffer_relocate_vma(struct i915_vma
*vma
,
511 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
512 struct drm_i915_gem_relocation_entry stack_reloc
[N_RELOC(512)];
513 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
514 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
517 user_relocs
= to_user_ptr(entry
->relocs_ptr
);
519 remain
= entry
->relocation_count
;
521 struct drm_i915_gem_relocation_entry
*r
= stack_reloc
;
523 if (count
> ARRAY_SIZE(stack_reloc
))
524 count
= ARRAY_SIZE(stack_reloc
);
527 if (__copy_from_user_inatomic(r
, user_relocs
, count
*sizeof(r
[0])))
531 u64 offset
= r
->presumed_offset
;
533 ret
= i915_gem_execbuffer_relocate_entry(vma
->obj
, eb
, r
);
537 if (r
->presumed_offset
!= offset
&&
538 __copy_to_user_inatomic(&user_relocs
->presumed_offset
,
540 sizeof(r
->presumed_offset
))) {
554 i915_gem_execbuffer_relocate_vma_slow(struct i915_vma
*vma
,
556 struct drm_i915_gem_relocation_entry
*relocs
)
558 const struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
561 for (i
= 0; i
< entry
->relocation_count
; i
++) {
562 ret
= i915_gem_execbuffer_relocate_entry(vma
->obj
, eb
, &relocs
[i
]);
571 i915_gem_execbuffer_relocate(struct eb_vmas
*eb
)
573 struct i915_vma
*vma
;
576 /* This is the fast path and we cannot handle a pagefault whilst
577 * holding the struct mutex lest the user pass in the relocations
578 * contained within a mmaped bo. For in such a case we, the page
579 * fault handler would call i915_gem_fault() and we would try to
580 * acquire the struct mutex again. Obviously this is bad and so
581 * lockdep complains vehemently.
584 list_for_each_entry(vma
, &eb
->vmas
, exec_list
) {
585 ret
= i915_gem_execbuffer_relocate_vma(vma
, eb
);
594 static bool only_mappable_for_reloc(unsigned int flags
)
596 return (flags
& (EXEC_OBJECT_NEEDS_FENCE
| __EXEC_OBJECT_NEEDS_MAP
)) ==
597 __EXEC_OBJECT_NEEDS_MAP
;
601 i915_gem_execbuffer_reserve_vma(struct i915_vma
*vma
,
602 struct intel_engine_cs
*engine
,
605 struct drm_i915_gem_object
*obj
= vma
->obj
;
606 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
611 if (entry
->flags
& EXEC_OBJECT_NEEDS_GTT
)
614 if (!drm_mm_node_allocated(&vma
->node
)) {
615 /* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
616 * limit address to the first 4GBs for unflagged objects.
618 if ((entry
->flags
& EXEC_OBJECT_SUPPORTS_48B_ADDRESS
) == 0)
619 flags
|= PIN_ZONE_4G
;
620 if (entry
->flags
& __EXEC_OBJECT_NEEDS_MAP
)
621 flags
|= PIN_GLOBAL
| PIN_MAPPABLE
;
622 if (entry
->flags
& __EXEC_OBJECT_NEEDS_BIAS
)
623 flags
|= BATCH_OFFSET_BIAS
| PIN_OFFSET_BIAS
;
624 if (entry
->flags
& EXEC_OBJECT_PINNED
)
625 flags
|= entry
->offset
| PIN_OFFSET_FIXED
;
626 if ((flags
& PIN_MAPPABLE
) == 0)
630 ret
= i915_gem_object_pin(obj
, vma
->vm
, entry
->alignment
, flags
);
631 if ((ret
== -ENOSPC
|| ret
== -E2BIG
) &&
632 only_mappable_for_reloc(entry
->flags
))
633 ret
= i915_gem_object_pin(obj
, vma
->vm
,
635 flags
& ~PIN_MAPPABLE
);
639 entry
->flags
|= __EXEC_OBJECT_HAS_PIN
;
641 if (entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
) {
642 ret
= i915_gem_object_get_fence(obj
);
646 if (i915_gem_object_pin_fence(obj
))
647 entry
->flags
|= __EXEC_OBJECT_HAS_FENCE
;
650 if (entry
->offset
!= vma
->node
.start
) {
651 entry
->offset
= vma
->node
.start
;
655 if (entry
->flags
& EXEC_OBJECT_WRITE
) {
656 obj
->base
.pending_read_domains
= I915_GEM_DOMAIN_RENDER
;
657 obj
->base
.pending_write_domain
= I915_GEM_DOMAIN_RENDER
;
664 need_reloc_mappable(struct i915_vma
*vma
)
666 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
668 if (entry
->relocation_count
== 0)
674 /* See also use_cpu_reloc() */
675 if (HAS_LLC(vma
->obj
->base
.dev
))
678 if (vma
->obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
685 eb_vma_misplaced(struct i915_vma
*vma
)
687 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
688 struct drm_i915_gem_object
*obj
= vma
->obj
;
690 WARN_ON(entry
->flags
& __EXEC_OBJECT_NEEDS_MAP
&& !vma
->is_ggtt
);
692 if (entry
->alignment
&&
693 vma
->node
.start
& (entry
->alignment
- 1))
696 if (entry
->flags
& EXEC_OBJECT_PINNED
&&
697 vma
->node
.start
!= entry
->offset
)
700 if (entry
->flags
& __EXEC_OBJECT_NEEDS_BIAS
&&
701 vma
->node
.start
< BATCH_OFFSET_BIAS
)
704 /* avoid costly ping-pong once a batch bo ended up non-mappable */
705 if (entry
->flags
& __EXEC_OBJECT_NEEDS_MAP
&& !obj
->map_and_fenceable
)
706 return !only_mappable_for_reloc(entry
->flags
);
708 if ((entry
->flags
& EXEC_OBJECT_SUPPORTS_48B_ADDRESS
) == 0 &&
709 (vma
->node
.start
+ vma
->node
.size
- 1) >> 32)
716 i915_gem_execbuffer_reserve(struct intel_engine_cs
*engine
,
717 struct list_head
*vmas
,
718 struct intel_context
*ctx
,
721 struct drm_i915_gem_object
*obj
;
722 struct i915_vma
*vma
;
723 struct i915_address_space
*vm
;
724 struct list_head ordered_vmas
;
725 struct list_head pinned_vmas
;
726 bool has_fenced_gpu_access
= INTEL_INFO(engine
->dev
)->gen
< 4;
729 i915_gem_retire_requests_ring(engine
);
731 vm
= list_first_entry(vmas
, struct i915_vma
, exec_list
)->vm
;
733 INIT_LIST_HEAD(&ordered_vmas
);
734 INIT_LIST_HEAD(&pinned_vmas
);
735 while (!list_empty(vmas
)) {
736 struct drm_i915_gem_exec_object2
*entry
;
737 bool need_fence
, need_mappable
;
739 vma
= list_first_entry(vmas
, struct i915_vma
, exec_list
);
741 entry
= vma
->exec_entry
;
743 if (ctx
->flags
& CONTEXT_NO_ZEROMAP
)
744 entry
->flags
|= __EXEC_OBJECT_NEEDS_BIAS
;
746 if (!has_fenced_gpu_access
)
747 entry
->flags
&= ~EXEC_OBJECT_NEEDS_FENCE
;
749 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
750 obj
->tiling_mode
!= I915_TILING_NONE
;
751 need_mappable
= need_fence
|| need_reloc_mappable(vma
);
753 if (entry
->flags
& EXEC_OBJECT_PINNED
)
754 list_move_tail(&vma
->exec_list
, &pinned_vmas
);
755 else if (need_mappable
) {
756 entry
->flags
|= __EXEC_OBJECT_NEEDS_MAP
;
757 list_move(&vma
->exec_list
, &ordered_vmas
);
759 list_move_tail(&vma
->exec_list
, &ordered_vmas
);
761 obj
->base
.pending_read_domains
= I915_GEM_GPU_DOMAINS
& ~I915_GEM_DOMAIN_COMMAND
;
762 obj
->base
.pending_write_domain
= 0;
764 list_splice(&ordered_vmas
, vmas
);
765 list_splice(&pinned_vmas
, vmas
);
767 /* Attempt to pin all of the buffers into the GTT.
768 * This is done in 3 phases:
770 * 1a. Unbind all objects that do not match the GTT constraints for
771 * the execbuffer (fenceable, mappable, alignment etc).
772 * 1b. Increment pin count for already bound objects.
773 * 2. Bind new objects.
774 * 3. Decrement pin count.
776 * This avoid unnecessary unbinding of later objects in order to make
777 * room for the earlier objects *unless* we need to defragment.
783 /* Unbind any ill-fitting objects or pin. */
784 list_for_each_entry(vma
, vmas
, exec_list
) {
785 if (!drm_mm_node_allocated(&vma
->node
))
788 if (eb_vma_misplaced(vma
))
789 ret
= i915_vma_unbind(vma
);
791 ret
= i915_gem_execbuffer_reserve_vma(vma
,
798 /* Bind fresh objects */
799 list_for_each_entry(vma
, vmas
, exec_list
) {
800 if (drm_mm_node_allocated(&vma
->node
))
803 ret
= i915_gem_execbuffer_reserve_vma(vma
, engine
,
810 if (ret
!= -ENOSPC
|| retry
++)
813 /* Decrement pin count for bound objects */
814 list_for_each_entry(vma
, vmas
, exec_list
)
815 i915_gem_execbuffer_unreserve_vma(vma
);
817 ret
= i915_gem_evict_vm(vm
, true);
824 i915_gem_execbuffer_relocate_slow(struct drm_device
*dev
,
825 struct drm_i915_gem_execbuffer2
*args
,
826 struct drm_file
*file
,
827 struct intel_engine_cs
*engine
,
829 struct drm_i915_gem_exec_object2
*exec
,
830 struct intel_context
*ctx
)
832 struct drm_i915_gem_relocation_entry
*reloc
;
833 struct i915_address_space
*vm
;
834 struct i915_vma
*vma
;
838 unsigned count
= args
->buffer_count
;
840 vm
= list_first_entry(&eb
->vmas
, struct i915_vma
, exec_list
)->vm
;
842 /* We may process another execbuffer during the unlock... */
843 while (!list_empty(&eb
->vmas
)) {
844 vma
= list_first_entry(&eb
->vmas
, struct i915_vma
, exec_list
);
845 list_del_init(&vma
->exec_list
);
846 i915_gem_execbuffer_unreserve_vma(vma
);
847 drm_gem_object_unreference(&vma
->obj
->base
);
850 mutex_unlock(&dev
->struct_mutex
);
853 for (i
= 0; i
< count
; i
++)
854 total
+= exec
[i
].relocation_count
;
856 reloc_offset
= drm_malloc_ab(count
, sizeof(*reloc_offset
));
857 reloc
= drm_malloc_ab(total
, sizeof(*reloc
));
858 if (reloc
== NULL
|| reloc_offset
== NULL
) {
859 drm_free_large(reloc
);
860 drm_free_large(reloc_offset
);
861 mutex_lock(&dev
->struct_mutex
);
866 for (i
= 0; i
< count
; i
++) {
867 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
868 u64 invalid_offset
= (u64
)-1;
871 user_relocs
= to_user_ptr(exec
[i
].relocs_ptr
);
873 if (copy_from_user(reloc
+total
, user_relocs
,
874 exec
[i
].relocation_count
* sizeof(*reloc
))) {
876 mutex_lock(&dev
->struct_mutex
);
880 /* As we do not update the known relocation offsets after
881 * relocating (due to the complexities in lock handling),
882 * we need to mark them as invalid now so that we force the
883 * relocation processing next time. Just in case the target
884 * object is evicted and then rebound into its old
885 * presumed_offset before the next execbuffer - if that
886 * happened we would make the mistake of assuming that the
887 * relocations were valid.
889 for (j
= 0; j
< exec
[i
].relocation_count
; j
++) {
890 if (__copy_to_user(&user_relocs
[j
].presumed_offset
,
892 sizeof(invalid_offset
))) {
894 mutex_lock(&dev
->struct_mutex
);
899 reloc_offset
[i
] = total
;
900 total
+= exec
[i
].relocation_count
;
903 ret
= i915_mutex_lock_interruptible(dev
);
905 mutex_lock(&dev
->struct_mutex
);
909 /* reacquire the objects */
911 ret
= eb_lookup_vmas(eb
, exec
, args
, vm
, file
);
915 need_relocs
= (args
->flags
& I915_EXEC_NO_RELOC
) == 0;
916 ret
= i915_gem_execbuffer_reserve(engine
, &eb
->vmas
, ctx
,
921 list_for_each_entry(vma
, &eb
->vmas
, exec_list
) {
922 int offset
= vma
->exec_entry
- exec
;
923 ret
= i915_gem_execbuffer_relocate_vma_slow(vma
, eb
,
924 reloc
+ reloc_offset
[offset
]);
929 /* Leave the user relocations as are, this is the painfully slow path,
930 * and we want to avoid the complication of dropping the lock whilst
931 * having buffers reserved in the aperture and so causing spurious
932 * ENOSPC for random operations.
936 drm_free_large(reloc
);
937 drm_free_large(reloc_offset
);
942 i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request
*req
,
943 struct list_head
*vmas
)
945 const unsigned other_rings
= ~intel_ring_flag(req
->engine
);
946 struct i915_vma
*vma
;
947 uint32_t flush_domains
= 0;
948 bool flush_chipset
= false;
951 list_for_each_entry(vma
, vmas
, exec_list
) {
952 struct drm_i915_gem_object
*obj
= vma
->obj
;
954 if (obj
->active
& other_rings
) {
955 ret
= i915_gem_object_sync(obj
, req
->engine
, &req
);
960 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
961 flush_chipset
|= i915_gem_clflush_object(obj
, false);
963 flush_domains
|= obj
->base
.write_domain
;
967 i915_gem_chipset_flush(req
->engine
->dev
);
969 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
972 /* Unconditionally invalidate gpu caches and ensure that we do flush
973 * any residual writes from the previous batch.
975 return intel_ring_invalidate_all_caches(req
);
979 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2
*exec
)
981 if (exec
->flags
& __I915_EXEC_UNKNOWN_FLAGS
)
984 /* Kernel clipping was a DRI1 misfeature */
985 if (exec
->num_cliprects
|| exec
->cliprects_ptr
)
988 if (exec
->DR4
== 0xffffffff) {
989 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
992 if (exec
->DR1
|| exec
->DR4
)
995 if ((exec
->batch_start_offset
| exec
->batch_len
) & 0x7)
1002 validate_exec_list(struct drm_device
*dev
,
1003 struct drm_i915_gem_exec_object2
*exec
,
1006 unsigned relocs_total
= 0;
1007 unsigned relocs_max
= UINT_MAX
/ sizeof(struct drm_i915_gem_relocation_entry
);
1008 unsigned invalid_flags
;
1011 invalid_flags
= __EXEC_OBJECT_UNKNOWN_FLAGS
;
1012 if (USES_FULL_PPGTT(dev
))
1013 invalid_flags
|= EXEC_OBJECT_NEEDS_GTT
;
1015 for (i
= 0; i
< count
; i
++) {
1016 char __user
*ptr
= to_user_ptr(exec
[i
].relocs_ptr
);
1017 int length
; /* limited by fault_in_pages_readable() */
1019 if (exec
[i
].flags
& invalid_flags
)
1022 /* Offset can be used as input (EXEC_OBJECT_PINNED), reject
1023 * any non-page-aligned or non-canonical addresses.
1025 if (exec
[i
].flags
& EXEC_OBJECT_PINNED
) {
1026 if (exec
[i
].offset
!=
1027 gen8_canonical_addr(exec
[i
].offset
& PAGE_MASK
))
1030 /* From drm_mm perspective address space is continuous,
1031 * so from this point we're always using non-canonical
1034 exec
[i
].offset
= gen8_noncanonical_addr(exec
[i
].offset
);
1037 if (exec
[i
].alignment
&& !is_power_of_2(exec
[i
].alignment
))
1040 /* First check for malicious input causing overflow in
1041 * the worst case where we need to allocate the entire
1042 * relocation tree as a single array.
1044 if (exec
[i
].relocation_count
> relocs_max
- relocs_total
)
1046 relocs_total
+= exec
[i
].relocation_count
;
1048 length
= exec
[i
].relocation_count
*
1049 sizeof(struct drm_i915_gem_relocation_entry
);
1051 * We must check that the entire relocation array is safe
1052 * to read, but since we may need to update the presumed
1053 * offsets during execution, check for full write access.
1055 if (!access_ok(VERIFY_WRITE
, ptr
, length
))
1058 if (likely(!i915
.prefault_disable
)) {
1059 if (fault_in_multipages_readable(ptr
, length
))
1067 static struct intel_context
*
1068 i915_gem_validate_context(struct drm_device
*dev
, struct drm_file
*file
,
1069 struct intel_engine_cs
*engine
, const u32 ctx_id
)
1071 struct intel_context
*ctx
= NULL
;
1072 struct i915_ctx_hang_stats
*hs
;
1074 if (engine
->id
!= RCS
&& ctx_id
!= DEFAULT_CONTEXT_HANDLE
)
1075 return ERR_PTR(-EINVAL
);
1077 ctx
= i915_gem_context_get(file
->driver_priv
, ctx_id
);
1081 hs
= &ctx
->hang_stats
;
1083 DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id
);
1084 return ERR_PTR(-EIO
);
1087 if (i915
.enable_execlists
&& !ctx
->engine
[engine
->id
].state
) {
1088 int ret
= intel_lr_context_deferred_alloc(ctx
, engine
);
1090 DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id
, ret
);
1091 return ERR_PTR(ret
);
1099 i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
1100 struct drm_i915_gem_request
*req
)
1102 struct intel_engine_cs
*engine
= i915_gem_request_get_ring(req
);
1103 struct i915_vma
*vma
;
1105 list_for_each_entry(vma
, vmas
, exec_list
) {
1106 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
1107 struct drm_i915_gem_object
*obj
= vma
->obj
;
1108 u32 old_read
= obj
->base
.read_domains
;
1109 u32 old_write
= obj
->base
.write_domain
;
1111 obj
->dirty
= 1; /* be paranoid */
1112 obj
->base
.write_domain
= obj
->base
.pending_write_domain
;
1113 if (obj
->base
.write_domain
== 0)
1114 obj
->base
.pending_read_domains
|= obj
->base
.read_domains
;
1115 obj
->base
.read_domains
= obj
->base
.pending_read_domains
;
1117 i915_vma_move_to_active(vma
, req
);
1118 if (obj
->base
.write_domain
) {
1119 i915_gem_request_assign(&obj
->last_write_req
, req
);
1121 intel_fb_obj_invalidate(obj
, ORIGIN_CS
);
1123 /* update for the implicit flush after a batch */
1124 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1126 if (entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
) {
1127 i915_gem_request_assign(&obj
->last_fenced_req
, req
);
1128 if (entry
->flags
& __EXEC_OBJECT_HAS_FENCE
) {
1129 struct drm_i915_private
*dev_priv
= to_i915(engine
->dev
);
1130 list_move_tail(&dev_priv
->fence_regs
[obj
->fence_reg
].lru_list
,
1131 &dev_priv
->mm
.fence_list
);
1135 trace_i915_gem_object_change_domain(obj
, old_read
, old_write
);
1140 i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params
*params
)
1142 /* Unconditionally force add_request to emit a full flush. */
1143 params
->engine
->gpu_caches_dirty
= true;
1145 /* Add a breadcrumb for the completion of the batch buffer */
1146 __i915_add_request(params
->request
, params
->batch_obj
, true);
1150 i915_reset_gen7_sol_offsets(struct drm_device
*dev
,
1151 struct drm_i915_gem_request
*req
)
1153 struct intel_engine_cs
*engine
= req
->engine
;
1154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1157 if (!IS_GEN7(dev
) || engine
!= &dev_priv
->engine
[RCS
]) {
1158 DRM_DEBUG("sol reset is gen7/rcs only\n");
1162 ret
= intel_ring_begin(req
, 4 * 3);
1166 for (i
= 0; i
< 4; i
++) {
1167 intel_ring_emit(engine
, MI_LOAD_REGISTER_IMM(1));
1168 intel_ring_emit_reg(engine
, GEN7_SO_WRITE_OFFSET(i
));
1169 intel_ring_emit(engine
, 0);
1172 intel_ring_advance(engine
);
1177 static struct drm_i915_gem_object
*
1178 i915_gem_execbuffer_parse(struct intel_engine_cs
*engine
,
1179 struct drm_i915_gem_exec_object2
*shadow_exec_entry
,
1181 struct drm_i915_gem_object
*batch_obj
,
1182 u32 batch_start_offset
,
1186 struct drm_i915_gem_object
*shadow_batch_obj
;
1187 struct i915_vma
*vma
;
1190 shadow_batch_obj
= i915_gem_batch_pool_get(&engine
->batch_pool
,
1191 PAGE_ALIGN(batch_len
));
1192 if (IS_ERR(shadow_batch_obj
))
1193 return shadow_batch_obj
;
1195 ret
= i915_parse_cmds(engine
,
1204 ret
= i915_gem_obj_ggtt_pin(shadow_batch_obj
, 0, 0);
1208 i915_gem_object_unpin_pages(shadow_batch_obj
);
1210 memset(shadow_exec_entry
, 0, sizeof(*shadow_exec_entry
));
1212 vma
= i915_gem_obj_to_ggtt(shadow_batch_obj
);
1213 vma
->exec_entry
= shadow_exec_entry
;
1214 vma
->exec_entry
->flags
= __EXEC_OBJECT_HAS_PIN
;
1215 drm_gem_object_reference(&shadow_batch_obj
->base
);
1216 list_add_tail(&vma
->exec_list
, &eb
->vmas
);
1218 shadow_batch_obj
->base
.pending_read_domains
= I915_GEM_DOMAIN_COMMAND
;
1220 return shadow_batch_obj
;
1223 i915_gem_object_unpin_pages(shadow_batch_obj
);
1224 if (ret
== -EACCES
) /* unhandled chained batch */
1227 return ERR_PTR(ret
);
1231 i915_gem_ringbuffer_submission(struct i915_execbuffer_params
*params
,
1232 struct drm_i915_gem_execbuffer2
*args
,
1233 struct list_head
*vmas
)
1235 struct drm_device
*dev
= params
->dev
;
1236 struct intel_engine_cs
*engine
= params
->engine
;
1237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1238 u64 exec_start
, exec_len
;
1243 ret
= i915_gem_execbuffer_move_to_gpu(params
->request
, vmas
);
1247 ret
= i915_switch_context(params
->request
);
1251 WARN(params
->ctx
->ppgtt
&& params
->ctx
->ppgtt
->pd_dirty_rings
& (1<<engine
->id
),
1252 "%s didn't clear reload\n", engine
->name
);
1254 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
1255 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
1256 switch (instp_mode
) {
1257 case I915_EXEC_CONSTANTS_REL_GENERAL
:
1258 case I915_EXEC_CONSTANTS_ABSOLUTE
:
1259 case I915_EXEC_CONSTANTS_REL_SURFACE
:
1260 if (instp_mode
!= 0 && engine
!= &dev_priv
->engine
[RCS
]) {
1261 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
1265 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
1266 if (INTEL_INFO(dev
)->gen
< 4) {
1267 DRM_DEBUG("no rel constants on pre-gen4\n");
1271 if (INTEL_INFO(dev
)->gen
> 5 &&
1272 instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
1273 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
1277 /* The HW changed the meaning on this bit on gen6 */
1278 if (INTEL_INFO(dev
)->gen
>= 6)
1279 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
1283 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
1287 if (engine
== &dev_priv
->engine
[RCS
] &&
1288 instp_mode
!= dev_priv
->relative_constants_mode
) {
1289 ret
= intel_ring_begin(params
->request
, 4);
1293 intel_ring_emit(engine
, MI_NOOP
);
1294 intel_ring_emit(engine
, MI_LOAD_REGISTER_IMM(1));
1295 intel_ring_emit_reg(engine
, INSTPM
);
1296 intel_ring_emit(engine
, instp_mask
<< 16 | instp_mode
);
1297 intel_ring_advance(engine
);
1299 dev_priv
->relative_constants_mode
= instp_mode
;
1302 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
1303 ret
= i915_reset_gen7_sol_offsets(dev
, params
->request
);
1308 exec_len
= args
->batch_len
;
1309 exec_start
= params
->batch_obj_vm_offset
+
1310 params
->args_batch_start_offset
;
1313 exec_len
= params
->batch_obj
->base
.size
;
1315 ret
= engine
->dispatch_execbuffer(params
->request
,
1316 exec_start
, exec_len
,
1317 params
->dispatch_flags
);
1321 trace_i915_gem_ring_dispatch(params
->request
, params
->dispatch_flags
);
1323 i915_gem_execbuffer_move_to_active(vmas
, params
->request
);
1324 i915_gem_execbuffer_retire_commands(params
);
1330 * Find one BSD ring to dispatch the corresponding BSD command.
1331 * The ring index is returned.
1334 gen8_dispatch_bsd_ring(struct drm_i915_private
*dev_priv
, struct drm_file
*file
)
1336 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1338 /* Check whether the file_priv has already selected one ring. */
1339 if ((int)file_priv
->bsd_ring
< 0) {
1340 /* If not, use the ping-pong mechanism to select one. */
1341 mutex_lock(&dev_priv
->dev
->struct_mutex
);
1342 file_priv
->bsd_ring
= dev_priv
->mm
.bsd_ring_dispatch_index
;
1343 dev_priv
->mm
.bsd_ring_dispatch_index
^= 1;
1344 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
1347 return file_priv
->bsd_ring
;
1350 static struct drm_i915_gem_object
*
1351 eb_get_batch(struct eb_vmas
*eb
)
1353 struct i915_vma
*vma
= list_entry(eb
->vmas
.prev
, typeof(*vma
), exec_list
);
1356 * SNA is doing fancy tricks with compressing batch buffers, which leads
1357 * to negative relocation deltas. Usually that works out ok since the
1358 * relocate address is still positive, except when the batch is placed
1359 * very low in the GTT. Ensure this doesn't happen.
1361 * Note that actual hangs have only been observed on gen7, but for
1362 * paranoia do it everywhere.
1364 if ((vma
->exec_entry
->flags
& EXEC_OBJECT_PINNED
) == 0)
1365 vma
->exec_entry
->flags
|= __EXEC_OBJECT_NEEDS_BIAS
;
1370 #define I915_USER_RINGS (4)
1372 static const enum intel_ring_id user_ring_map
[I915_USER_RINGS
+ 1] = {
1373 [I915_EXEC_DEFAULT
] = RCS
,
1374 [I915_EXEC_RENDER
] = RCS
,
1375 [I915_EXEC_BLT
] = BCS
,
1376 [I915_EXEC_BSD
] = VCS
,
1377 [I915_EXEC_VEBOX
] = VECS
1381 eb_select_ring(struct drm_i915_private
*dev_priv
,
1382 struct drm_file
*file
,
1383 struct drm_i915_gem_execbuffer2
*args
,
1384 struct intel_engine_cs
**ring
)
1386 unsigned int user_ring_id
= args
->flags
& I915_EXEC_RING_MASK
;
1388 if (user_ring_id
> I915_USER_RINGS
) {
1389 DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id
);
1393 if ((user_ring_id
!= I915_EXEC_BSD
) &&
1394 ((args
->flags
& I915_EXEC_BSD_MASK
) != 0)) {
1395 DRM_DEBUG("execbuf with non bsd ring but with invalid "
1396 "bsd dispatch flags: %d\n", (int)(args
->flags
));
1400 if (user_ring_id
== I915_EXEC_BSD
&& HAS_BSD2(dev_priv
)) {
1401 unsigned int bsd_idx
= args
->flags
& I915_EXEC_BSD_MASK
;
1403 if (bsd_idx
== I915_EXEC_BSD_DEFAULT
) {
1404 bsd_idx
= gen8_dispatch_bsd_ring(dev_priv
, file
);
1405 } else if (bsd_idx
>= I915_EXEC_BSD_RING1
&&
1406 bsd_idx
<= I915_EXEC_BSD_RING2
) {
1407 bsd_idx
>>= I915_EXEC_BSD_SHIFT
;
1410 DRM_DEBUG("execbuf with unknown bsd ring: %u\n",
1415 *ring
= &dev_priv
->engine
[_VCS(bsd_idx
)];
1417 *ring
= &dev_priv
->engine
[user_ring_map
[user_ring_id
]];
1420 if (!intel_ring_initialized(*ring
)) {
1421 DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id
);
1429 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
1430 struct drm_file
*file
,
1431 struct drm_i915_gem_execbuffer2
*args
,
1432 struct drm_i915_gem_exec_object2
*exec
)
1434 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1435 struct drm_i915_gem_request
*req
= NULL
;
1437 struct drm_i915_gem_object
*batch_obj
;
1438 struct drm_i915_gem_exec_object2 shadow_exec_entry
;
1439 struct intel_engine_cs
*engine
;
1440 struct intel_context
*ctx
;
1441 struct i915_address_space
*vm
;
1442 struct i915_execbuffer_params params_master
; /* XXX: will be removed later */
1443 struct i915_execbuffer_params
*params
= ¶ms_master
;
1444 const u32 ctx_id
= i915_execbuffer2_get_context_id(*args
);
1449 if (!i915_gem_check_execbuffer(args
))
1452 ret
= validate_exec_list(dev
, exec
, args
->buffer_count
);
1457 if (args
->flags
& I915_EXEC_SECURE
) {
1458 if (!file
->is_master
|| !capable(CAP_SYS_ADMIN
))
1461 dispatch_flags
|= I915_DISPATCH_SECURE
;
1463 if (args
->flags
& I915_EXEC_IS_PINNED
)
1464 dispatch_flags
|= I915_DISPATCH_PINNED
;
1466 ret
= eb_select_ring(dev_priv
, file
, args
, &engine
);
1470 if (args
->buffer_count
< 1) {
1471 DRM_DEBUG("execbuf with %d buffers\n", args
->buffer_count
);
1475 if (args
->flags
& I915_EXEC_RESOURCE_STREAMER
) {
1476 if (!HAS_RESOURCE_STREAMER(dev
)) {
1477 DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
1480 if (engine
->id
!= RCS
) {
1481 DRM_DEBUG("RS is not available on %s\n",
1486 dispatch_flags
|= I915_DISPATCH_RS
;
1489 intel_runtime_pm_get(dev_priv
);
1491 ret
= i915_mutex_lock_interruptible(dev
);
1495 ctx
= i915_gem_validate_context(dev
, file
, engine
, ctx_id
);
1497 mutex_unlock(&dev
->struct_mutex
);
1502 i915_gem_context_reference(ctx
);
1505 vm
= &ctx
->ppgtt
->base
;
1507 vm
= &dev_priv
->gtt
.base
;
1509 memset(¶ms_master
, 0x00, sizeof(params_master
));
1511 eb
= eb_create(args
);
1513 i915_gem_context_unreference(ctx
);
1514 mutex_unlock(&dev
->struct_mutex
);
1519 /* Look up object handles */
1520 ret
= eb_lookup_vmas(eb
, exec
, args
, vm
, file
);
1524 /* take note of the batch buffer before we might reorder the lists */
1525 batch_obj
= eb_get_batch(eb
);
1527 /* Move the objects en-masse into the GTT, evicting if necessary. */
1528 need_relocs
= (args
->flags
& I915_EXEC_NO_RELOC
) == 0;
1529 ret
= i915_gem_execbuffer_reserve(engine
, &eb
->vmas
, ctx
,
1534 /* The objects are in their final locations, apply the relocations. */
1536 ret
= i915_gem_execbuffer_relocate(eb
);
1538 if (ret
== -EFAULT
) {
1539 ret
= i915_gem_execbuffer_relocate_slow(dev
, args
, file
,
1542 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1548 /* Set the pending read domains for the batch buffer to COMMAND */
1549 if (batch_obj
->base
.pending_write_domain
) {
1550 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1555 params
->args_batch_start_offset
= args
->batch_start_offset
;
1556 if (i915_needs_cmd_parser(engine
) && args
->batch_len
) {
1557 struct drm_i915_gem_object
*parsed_batch_obj
;
1559 parsed_batch_obj
= i915_gem_execbuffer_parse(engine
,
1563 args
->batch_start_offset
,
1566 if (IS_ERR(parsed_batch_obj
)) {
1567 ret
= PTR_ERR(parsed_batch_obj
);
1572 * parsed_batch_obj == batch_obj means batch not fully parsed:
1573 * Accept, but don't promote to secure.
1576 if (parsed_batch_obj
!= batch_obj
) {
1578 * Batch parsed and accepted:
1580 * Set the DISPATCH_SECURE bit to remove the NON_SECURE
1581 * bit from MI_BATCH_BUFFER_START commands issued in
1582 * the dispatch_execbuffer implementations. We
1583 * specifically don't want that set on batches the
1584 * command parser has accepted.
1586 dispatch_flags
|= I915_DISPATCH_SECURE
;
1587 params
->args_batch_start_offset
= 0;
1588 batch_obj
= parsed_batch_obj
;
1592 batch_obj
->base
.pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
1594 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1595 * batch" bit. Hence we need to pin secure batches into the global gtt.
1596 * hsw should have this fixed, but bdw mucks it up again. */
1597 if (dispatch_flags
& I915_DISPATCH_SECURE
) {
1599 * So on first glance it looks freaky that we pin the batch here
1600 * outside of the reservation loop. But:
1601 * - The batch is already pinned into the relevant ppgtt, so we
1602 * already have the backing storage fully allocated.
1603 * - No other BO uses the global gtt (well contexts, but meh),
1604 * so we don't really have issues with multiple objects not
1605 * fitting due to fragmentation.
1606 * So this is actually safe.
1608 ret
= i915_gem_obj_ggtt_pin(batch_obj
, 0, 0);
1612 params
->batch_obj_vm_offset
= i915_gem_obj_ggtt_offset(batch_obj
);
1614 params
->batch_obj_vm_offset
= i915_gem_obj_offset(batch_obj
, vm
);
1616 /* Allocate a request for this batch buffer nice and early. */
1617 req
= i915_gem_request_alloc(engine
, ctx
);
1620 goto err_batch_unpin
;
1623 ret
= i915_gem_request_add_to_client(req
, file
);
1625 goto err_batch_unpin
;
1628 * Save assorted stuff away to pass through to *_submission().
1629 * NB: This data should be 'persistent' and not local as it will
1630 * kept around beyond the duration of the IOCTL once the GPU
1631 * scheduler arrives.
1634 params
->file
= file
;
1635 params
->engine
= engine
;
1636 params
->dispatch_flags
= dispatch_flags
;
1637 params
->batch_obj
= batch_obj
;
1639 params
->request
= req
;
1641 ret
= dev_priv
->gt
.execbuf_submit(params
, args
, &eb
->vmas
);
1645 * FIXME: We crucially rely upon the active tracking for the (ppgtt)
1646 * batch vma for correctness. For less ugly and less fragility this
1647 * needs to be adjusted to also track the ggtt batch vma properly as
1650 if (dispatch_flags
& I915_DISPATCH_SECURE
)
1651 i915_gem_object_ggtt_unpin(batch_obj
);
1654 /* the request owns the ref now */
1655 i915_gem_context_unreference(ctx
);
1659 * If the request was created but not successfully submitted then it
1660 * must be freed again. If it was submitted then it is being tracked
1661 * on the active request list and no clean up is required here.
1663 if (ret
&& !IS_ERR_OR_NULL(req
))
1664 i915_gem_request_cancel(req
);
1666 mutex_unlock(&dev
->struct_mutex
);
1669 /* intel_gpu_busy should also get a ref, so it will free when the device
1670 * is really idle. */
1671 intel_runtime_pm_put(dev_priv
);
1676 * Legacy execbuffer just creates an exec2 list from the original exec object
1677 * list array and passes it to the real function.
1680 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1681 struct drm_file
*file
)
1683 struct drm_i915_gem_execbuffer
*args
= data
;
1684 struct drm_i915_gem_execbuffer2 exec2
;
1685 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
1686 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
1689 if (args
->buffer_count
< 1) {
1690 DRM_DEBUG("execbuf with %d buffers\n", args
->buffer_count
);
1694 /* Copy in the exec list from userland */
1695 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
1696 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
1697 if (exec_list
== NULL
|| exec2_list
== NULL
) {
1698 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1699 args
->buffer_count
);
1700 drm_free_large(exec_list
);
1701 drm_free_large(exec2_list
);
1704 ret
= copy_from_user(exec_list
,
1705 to_user_ptr(args
->buffers_ptr
),
1706 sizeof(*exec_list
) * args
->buffer_count
);
1708 DRM_DEBUG("copy %d exec entries failed %d\n",
1709 args
->buffer_count
, ret
);
1710 drm_free_large(exec_list
);
1711 drm_free_large(exec2_list
);
1715 for (i
= 0; i
< args
->buffer_count
; i
++) {
1716 exec2_list
[i
].handle
= exec_list
[i
].handle
;
1717 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
1718 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
1719 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
1720 exec2_list
[i
].offset
= exec_list
[i
].offset
;
1721 if (INTEL_INFO(dev
)->gen
< 4)
1722 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
1724 exec2_list
[i
].flags
= 0;
1727 exec2
.buffers_ptr
= args
->buffers_ptr
;
1728 exec2
.buffer_count
= args
->buffer_count
;
1729 exec2
.batch_start_offset
= args
->batch_start_offset
;
1730 exec2
.batch_len
= args
->batch_len
;
1731 exec2
.DR1
= args
->DR1
;
1732 exec2
.DR4
= args
->DR4
;
1733 exec2
.num_cliprects
= args
->num_cliprects
;
1734 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
1735 exec2
.flags
= I915_EXEC_RENDER
;
1736 i915_execbuffer2_set_context_id(exec2
, 0);
1738 ret
= i915_gem_do_execbuffer(dev
, data
, file
, &exec2
, exec2_list
);
1740 struct drm_i915_gem_exec_object __user
*user_exec_list
=
1741 to_user_ptr(args
->buffers_ptr
);
1743 /* Copy the new buffer offsets back to the user's exec list. */
1744 for (i
= 0; i
< args
->buffer_count
; i
++) {
1745 exec2_list
[i
].offset
=
1746 gen8_canonical_addr(exec2_list
[i
].offset
);
1747 ret
= __copy_to_user(&user_exec_list
[i
].offset
,
1748 &exec2_list
[i
].offset
,
1749 sizeof(user_exec_list
[i
].offset
));
1752 DRM_DEBUG("failed to copy %d exec entries "
1753 "back to user (%d)\n",
1754 args
->buffer_count
, ret
);
1760 drm_free_large(exec_list
);
1761 drm_free_large(exec2_list
);
1766 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1767 struct drm_file
*file
)
1769 struct drm_i915_gem_execbuffer2
*args
= data
;
1770 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
1773 if (args
->buffer_count
< 1 ||
1774 args
->buffer_count
> UINT_MAX
/ sizeof(*exec2_list
)) {
1775 DRM_DEBUG("execbuf2 with %d buffers\n", args
->buffer_count
);
1779 if (args
->rsvd2
!= 0) {
1780 DRM_DEBUG("dirty rvsd2 field\n");
1784 exec2_list
= kmalloc(sizeof(*exec2_list
)*args
->buffer_count
,
1785 GFP_TEMPORARY
| __GFP_NOWARN
| __GFP_NORETRY
);
1786 if (exec2_list
== NULL
)
1787 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
),
1788 args
->buffer_count
);
1789 if (exec2_list
== NULL
) {
1790 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1791 args
->buffer_count
);
1794 ret
= copy_from_user(exec2_list
,
1795 to_user_ptr(args
->buffers_ptr
),
1796 sizeof(*exec2_list
) * args
->buffer_count
);
1798 DRM_DEBUG("copy %d exec entries failed %d\n",
1799 args
->buffer_count
, ret
);
1800 drm_free_large(exec2_list
);
1804 ret
= i915_gem_do_execbuffer(dev
, data
, file
, args
, exec2_list
);
1806 /* Copy the new buffer offsets back to the user's exec list. */
1807 struct drm_i915_gem_exec_object2 __user
*user_exec_list
=
1808 to_user_ptr(args
->buffers_ptr
);
1811 for (i
= 0; i
< args
->buffer_count
; i
++) {
1812 exec2_list
[i
].offset
=
1813 gen8_canonical_addr(exec2_list
[i
].offset
);
1814 ret
= __copy_to_user(&user_exec_list
[i
].offset
,
1815 &exec2_list
[i
].offset
,
1816 sizeof(user_exec_list
[i
].offset
));
1819 DRM_DEBUG("failed to copy %d exec entries "
1821 args
->buffer_count
);
1827 drm_free_large(exec2_list
);