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drm/i915/bdw: Reorganize PPGTT init
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c
1 /*
2 * Copyright © 2010 Daniel Vetter
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #include <linux/seq_file.h>
26 #include <drm/drmP.h>
27 #include <drm/i915_drm.h>
28 #include "i915_drv.h"
29 #include "i915_trace.h"
30 #include "intel_drv.h"
31
32 #define GEN6_PPGTT_PD_ENTRIES 512
33 #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
34 typedef uint64_t gen8_gtt_pte_t;
35 typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
36
37 /* PPGTT stuff */
38 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
39 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
40
41 #define GEN6_PDE_VALID (1 << 0)
42 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
43 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
44
45 #define GEN6_PTE_VALID (1 << 0)
46 #define GEN6_PTE_UNCACHED (1 << 1)
47 #define HSW_PTE_UNCACHED (0)
48 #define GEN6_PTE_CACHE_LLC (2 << 1)
49 #define GEN7_PTE_CACHE_L3_LLC (3 << 1)
50 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
51 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
52
53 /* Cacheability Control is a 4-bit value. The low three bits are stored in *
54 * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
55 */
56 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
57 (((bits) & 0x8) << (11 - 3)))
58 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
59 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
60 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
61 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
62 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
63 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
64
65 #define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t))
66 #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t))
67 #define GEN8_LEGACY_PDPS 4
68
69 #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD)
70 #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */
71 #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */
72 #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */
73
74 static void ppgtt_bind_vma(struct i915_vma *vma,
75 enum i915_cache_level cache_level,
76 u32 flags);
77 static void ppgtt_unbind_vma(struct i915_vma *vma);
78 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt);
79
80 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
81 enum i915_cache_level level,
82 bool valid)
83 {
84 gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
85 pte |= addr;
86 if (level != I915_CACHE_NONE)
87 pte |= PPAT_CACHED_INDEX;
88 else
89 pte |= PPAT_UNCACHED_INDEX;
90 return pte;
91 }
92
93 static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
94 dma_addr_t addr,
95 enum i915_cache_level level)
96 {
97 gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
98 pde |= addr;
99 if (level != I915_CACHE_NONE)
100 pde |= PPAT_CACHED_PDE_INDEX;
101 else
102 pde |= PPAT_UNCACHED_INDEX;
103 return pde;
104 }
105
106 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
107 enum i915_cache_level level,
108 bool valid)
109 {
110 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
111 pte |= GEN6_PTE_ADDR_ENCODE(addr);
112
113 switch (level) {
114 case I915_CACHE_L3_LLC:
115 case I915_CACHE_LLC:
116 pte |= GEN6_PTE_CACHE_LLC;
117 break;
118 case I915_CACHE_NONE:
119 pte |= GEN6_PTE_UNCACHED;
120 break;
121 default:
122 WARN_ON(1);
123 }
124
125 return pte;
126 }
127
128 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
129 enum i915_cache_level level,
130 bool valid)
131 {
132 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
133 pte |= GEN6_PTE_ADDR_ENCODE(addr);
134
135 switch (level) {
136 case I915_CACHE_L3_LLC:
137 pte |= GEN7_PTE_CACHE_L3_LLC;
138 break;
139 case I915_CACHE_LLC:
140 pte |= GEN6_PTE_CACHE_LLC;
141 break;
142 case I915_CACHE_NONE:
143 pte |= GEN6_PTE_UNCACHED;
144 break;
145 default:
146 WARN_ON(1);
147 }
148
149 return pte;
150 }
151
152 #define BYT_PTE_WRITEABLE (1 << 1)
153 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
154
155 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
156 enum i915_cache_level level,
157 bool valid)
158 {
159 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
160 pte |= GEN6_PTE_ADDR_ENCODE(addr);
161
162 /* Mark the page as writeable. Other platforms don't have a
163 * setting for read-only/writable, so this matches that behavior.
164 */
165 pte |= BYT_PTE_WRITEABLE;
166
167 if (level != I915_CACHE_NONE)
168 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
169
170 return pte;
171 }
172
173 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
174 enum i915_cache_level level,
175 bool valid)
176 {
177 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
178 pte |= HSW_PTE_ADDR_ENCODE(addr);
179
180 if (level != I915_CACHE_NONE)
181 pte |= HSW_WB_LLC_AGE3;
182
183 return pte;
184 }
185
186 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
187 enum i915_cache_level level,
188 bool valid)
189 {
190 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
191 pte |= HSW_PTE_ADDR_ENCODE(addr);
192
193 switch (level) {
194 case I915_CACHE_NONE:
195 break;
196 case I915_CACHE_WT:
197 pte |= HSW_WT_ELLC_LLC_AGE3;
198 break;
199 default:
200 pte |= HSW_WB_ELLC_LLC_AGE3;
201 break;
202 }
203
204 return pte;
205 }
206
207 /* Broadwell Page Directory Pointer Descriptors */
208 static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry,
209 uint64_t val, bool synchronous)
210 {
211 struct drm_i915_private *dev_priv = ring->dev->dev_private;
212 int ret;
213
214 BUG_ON(entry >= 4);
215
216 if (synchronous) {
217 I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32);
218 I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val);
219 return 0;
220 }
221
222 ret = intel_ring_begin(ring, 6);
223 if (ret)
224 return ret;
225
226 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
227 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
228 intel_ring_emit(ring, (u32)(val >> 32));
229 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
230 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
231 intel_ring_emit(ring, (u32)(val));
232 intel_ring_advance(ring);
233
234 return 0;
235 }
236
237 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
238 struct intel_ring_buffer *ring,
239 bool synchronous)
240 {
241 int i, ret;
242
243 /* bit of a hack to find the actual last used pd */
244 int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
245
246 for (i = used_pd - 1; i >= 0; i--) {
247 dma_addr_t addr = ppgtt->pd_dma_addr[i];
248 ret = gen8_write_pdp(ring, i, addr, synchronous);
249 if (ret)
250 return ret;
251 }
252
253 return 0;
254 }
255
256 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
257 unsigned first_entry,
258 unsigned num_entries,
259 bool use_scratch)
260 {
261 struct i915_hw_ppgtt *ppgtt =
262 container_of(vm, struct i915_hw_ppgtt, base);
263 gen8_gtt_pte_t *pt_vaddr, scratch_pte;
264 unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE;
265 unsigned first_pte = first_entry % GEN8_PTES_PER_PAGE;
266 unsigned last_pte, i;
267
268 scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
269 I915_CACHE_LLC, use_scratch);
270
271 while (num_entries) {
272 struct page *page_table = &ppgtt->gen8_pt_pages[act_pt];
273
274 last_pte = first_pte + num_entries;
275 if (last_pte > GEN8_PTES_PER_PAGE)
276 last_pte = GEN8_PTES_PER_PAGE;
277
278 pt_vaddr = kmap_atomic(page_table);
279
280 for (i = first_pte; i < last_pte; i++)
281 pt_vaddr[i] = scratch_pte;
282
283 kunmap_atomic(pt_vaddr);
284
285 num_entries -= last_pte - first_pte;
286 first_pte = 0;
287 act_pt++;
288 }
289 }
290
291 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
292 struct sg_table *pages,
293 unsigned first_entry,
294 enum i915_cache_level cache_level)
295 {
296 struct i915_hw_ppgtt *ppgtt =
297 container_of(vm, struct i915_hw_ppgtt, base);
298 gen8_gtt_pte_t *pt_vaddr;
299 unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE;
300 unsigned act_pte = first_entry % GEN8_PTES_PER_PAGE;
301 struct sg_page_iter sg_iter;
302
303 pt_vaddr = NULL;
304 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
305 if (pt_vaddr == NULL)
306 pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]);
307
308 pt_vaddr[act_pte] =
309 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
310 cache_level, true);
311 if (++act_pte == GEN8_PTES_PER_PAGE) {
312 kunmap_atomic(pt_vaddr);
313 pt_vaddr = NULL;
314 act_pt++;
315 act_pte = 0;
316 }
317 }
318 if (pt_vaddr)
319 kunmap_atomic(pt_vaddr);
320 }
321
322 static void gen8_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
323 {
324 int i;
325
326 for (i = 0; i < ppgtt->num_pd_pages ; i++)
327 kfree(ppgtt->gen8_pt_dma_addr[i]);
328
329 __free_pages(ppgtt->gen8_pt_pages, get_order(ppgtt->num_pt_pages << PAGE_SHIFT));
330 __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
331 }
332
333 static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
334 {
335 struct pci_dev *hwdev = ppgtt->base.dev->pdev;
336 int i, j;
337
338 for (i = 0; i < ppgtt->num_pd_pages; i++) {
339 /* TODO: In the future we'll support sparse mappings, so this
340 * will have to change. */
341 if (!ppgtt->pd_dma_addr[i])
342 continue;
343
344 pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE,
345 PCI_DMA_BIDIRECTIONAL);
346
347 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
348 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
349 if (addr)
350 pci_unmap_page(hwdev, addr, PAGE_SIZE,
351 PCI_DMA_BIDIRECTIONAL);
352 }
353 }
354 }
355
356 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
357 {
358 struct i915_hw_ppgtt *ppgtt =
359 container_of(vm, struct i915_hw_ppgtt, base);
360
361 list_del(&vm->global_link);
362 drm_mm_takedown(&vm->mm);
363
364 gen8_ppgtt_unmap_pages(ppgtt);
365 gen8_ppgtt_free(ppgtt);
366 }
367
368 /**
369 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
370 * with a net effect resembling a 2-level page table in normal x86 terms. Each
371 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
372 * space.
373 *
374 * FIXME: split allocation into smaller pieces. For now we only ever do this
375 * once, but with full PPGTT, the multiple contiguous allocations will be bad.
376 * TODO: Do something with the size parameter
377 */
378 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
379 {
380 struct page *pt_pages;
381 const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
382 const int num_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
383 struct pci_dev *hwdev = ppgtt->base.dev->pdev;
384 int i, j, ret;
385
386 if (size % (1<<30))
387 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
388
389 /* 1. Do all our allocations for page directories and page tables */
390 ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
391 if (!ppgtt->pd_pages)
392 return -ENOMEM;
393
394 pt_pages = alloc_pages(GFP_KERNEL, get_order(num_pt_pages << PAGE_SHIFT));
395 if (!pt_pages) {
396 __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
397 return -ENOMEM;
398 }
399
400 ppgtt->gen8_pt_pages = pt_pages;
401 ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
402 ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT);
403 ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
404 BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
405
406 for (i = 0; i < max_pdp; i++) {
407 ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE,
408 sizeof(dma_addr_t),
409 GFP_KERNEL);
410 if (!ppgtt->gen8_pt_dma_addr[i]) {
411 ret = -ENOMEM;
412 goto bail;
413 }
414 }
415
416 /*
417 * 2. Create all the DMA mappings for the page directories and page
418 * tables
419 */
420 for (i = 0; i < max_pdp; i++) {
421 dma_addr_t pd_addr, pt_addr;
422
423 /* Get the page directory mappings */
424 pd_addr = pci_map_page(hwdev, &ppgtt->pd_pages[i], 0,
425 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
426 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr);
427 if (ret)
428 goto bail;
429
430 ppgtt->pd_dma_addr[i] = pd_addr;
431
432 /* And the page table mappings per page directory */
433 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
434 struct page *p = &pt_pages[i * GEN8_PDES_PER_PAGE + j];
435
436 pt_addr = pci_map_page(hwdev, p, 0, PAGE_SIZE,
437 PCI_DMA_BIDIRECTIONAL);
438 ret = pci_dma_mapping_error(hwdev, pt_addr);
439 if (ret)
440 goto bail;
441
442 ppgtt->gen8_pt_dma_addr[i][j] = pt_addr;
443 }
444 }
445
446 /*
447 * 3. Map all the page directory entires to point to the page tables
448 * we've allocated.
449 *
450 * For now, the PPGTT helper functions all require that the PDEs are
451 * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
452 * will never need to touch the PDEs again.
453 */
454 for (i = 0; i < max_pdp; i++) {
455 gen8_ppgtt_pde_t *pd_vaddr;
456 pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
457 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
458 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
459 pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
460 I915_CACHE_LLC);
461 }
462 kunmap_atomic(pd_vaddr);
463 }
464
465 ppgtt->enable = gen8_ppgtt_enable;
466 ppgtt->switch_mm = gen8_mm_switch;
467 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
468 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
469 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
470 ppgtt->base.start = 0;
471 ppgtt->base.total = ppgtt->num_pt_pages * GEN8_PTES_PER_PAGE * PAGE_SIZE;
472
473 ppgtt->base.clear_range(&ppgtt->base, 0,
474 ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE,
475 true);
476
477 DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
478 ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
479 DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
480 ppgtt->num_pt_pages,
481 (ppgtt->num_pt_pages - num_pt_pages) +
482 size % (1<<30));
483 return 0;
484
485 bail:
486 gen8_ppgtt_unmap_pages(ppgtt);
487 gen8_ppgtt_free(ppgtt);
488 return ret;
489 }
490
491 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
492 {
493 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
494 struct i915_address_space *vm = &ppgtt->base;
495 gen6_gtt_pte_t __iomem *pd_addr;
496 gen6_gtt_pte_t scratch_pte;
497 uint32_t pd_entry;
498 int pte, pde;
499
500 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
501
502 pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm +
503 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
504
505 seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm,
506 ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries);
507 for (pde = 0; pde < ppgtt->num_pd_entries; pde++) {
508 u32 expected;
509 gen6_gtt_pte_t *pt_vaddr;
510 dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde];
511 pd_entry = readl(pd_addr + pde);
512 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
513
514 if (pd_entry != expected)
515 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
516 pde,
517 pd_entry,
518 expected);
519 seq_printf(m, "\tPDE: %x\n", pd_entry);
520
521 pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]);
522 for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) {
523 unsigned long va =
524 (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) +
525 (pte * PAGE_SIZE);
526 int i;
527 bool found = false;
528 for (i = 0; i < 4; i++)
529 if (pt_vaddr[pte + i] != scratch_pte)
530 found = true;
531 if (!found)
532 continue;
533
534 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
535 for (i = 0; i < 4; i++) {
536 if (pt_vaddr[pte + i] != scratch_pte)
537 seq_printf(m, " %08x", pt_vaddr[pte + i]);
538 else
539 seq_puts(m, " SCRATCH ");
540 }
541 seq_puts(m, "\n");
542 }
543 kunmap_atomic(pt_vaddr);
544 }
545 }
546
547 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
548 {
549 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
550 gen6_gtt_pte_t __iomem *pd_addr;
551 uint32_t pd_entry;
552 int i;
553
554 WARN_ON(ppgtt->pd_offset & 0x3f);
555 pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
556 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
557 for (i = 0; i < ppgtt->num_pd_entries; i++) {
558 dma_addr_t pt_addr;
559
560 pt_addr = ppgtt->pt_dma_addr[i];
561 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
562 pd_entry |= GEN6_PDE_VALID;
563
564 writel(pd_entry, pd_addr + i);
565 }
566 readl(pd_addr);
567 }
568
569 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
570 {
571 BUG_ON(ppgtt->pd_offset & 0x3f);
572
573 return (ppgtt->pd_offset / 64) << 16;
574 }
575
576 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
577 struct intel_ring_buffer *ring,
578 bool synchronous)
579 {
580 struct drm_device *dev = ppgtt->base.dev;
581 struct drm_i915_private *dev_priv = dev->dev_private;
582 int ret;
583
584 /* If we're in reset, we can assume the GPU is sufficiently idle to
585 * manually frob these bits. Ideally we could use the ring functions,
586 * except our error handling makes it quite difficult (can't use
587 * intel_ring_begin, ring->flush, or intel_ring_advance)
588 *
589 * FIXME: We should try not to special case reset
590 */
591 if (synchronous ||
592 i915_reset_in_progress(&dev_priv->gpu_error)) {
593 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
594 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
595 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
596 POSTING_READ(RING_PP_DIR_BASE(ring));
597 return 0;
598 }
599
600 /* NB: TLBs must be flushed and invalidated before a switch */
601 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
602 if (ret)
603 return ret;
604
605 ret = intel_ring_begin(ring, 6);
606 if (ret)
607 return ret;
608
609 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
610 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
611 intel_ring_emit(ring, PP_DIR_DCLV_2G);
612 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
613 intel_ring_emit(ring, get_pd_offset(ppgtt));
614 intel_ring_emit(ring, MI_NOOP);
615 intel_ring_advance(ring);
616
617 return 0;
618 }
619
620 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
621 struct intel_ring_buffer *ring,
622 bool synchronous)
623 {
624 struct drm_device *dev = ppgtt->base.dev;
625 struct drm_i915_private *dev_priv = dev->dev_private;
626 int ret;
627
628 /* If we're in reset, we can assume the GPU is sufficiently idle to
629 * manually frob these bits. Ideally we could use the ring functions,
630 * except our error handling makes it quite difficult (can't use
631 * intel_ring_begin, ring->flush, or intel_ring_advance)
632 *
633 * FIXME: We should try not to special case reset
634 */
635 if (synchronous ||
636 i915_reset_in_progress(&dev_priv->gpu_error)) {
637 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
638 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
639 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
640 POSTING_READ(RING_PP_DIR_BASE(ring));
641 return 0;
642 }
643
644 /* NB: TLBs must be flushed and invalidated before a switch */
645 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
646 if (ret)
647 return ret;
648
649 ret = intel_ring_begin(ring, 6);
650 if (ret)
651 return ret;
652
653 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
654 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
655 intel_ring_emit(ring, PP_DIR_DCLV_2G);
656 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
657 intel_ring_emit(ring, get_pd_offset(ppgtt));
658 intel_ring_emit(ring, MI_NOOP);
659 intel_ring_advance(ring);
660
661 /* XXX: RCS is the only one to auto invalidate the TLBs? */
662 if (ring->id != RCS) {
663 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
664 if (ret)
665 return ret;
666 }
667
668 return 0;
669 }
670
671 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
672 struct intel_ring_buffer *ring,
673 bool synchronous)
674 {
675 struct drm_device *dev = ppgtt->base.dev;
676 struct drm_i915_private *dev_priv = dev->dev_private;
677
678 if (!synchronous)
679 return 0;
680
681 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
682 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
683
684 POSTING_READ(RING_PP_DIR_DCLV(ring));
685
686 return 0;
687 }
688
689 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
690 {
691 struct drm_device *dev = ppgtt->base.dev;
692 struct drm_i915_private *dev_priv = dev->dev_private;
693 struct intel_ring_buffer *ring;
694 int j, ret;
695
696 for_each_ring(ring, dev_priv, j) {
697 I915_WRITE(RING_MODE_GEN7(ring),
698 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
699
700 /* We promise to do a switch later with FULL PPGTT. If this is
701 * aliasing, this is the one and only switch we'll do */
702 if (USES_FULL_PPGTT(dev))
703 continue;
704
705 ret = ppgtt->switch_mm(ppgtt, ring, true);
706 if (ret)
707 goto err_out;
708 }
709
710 return 0;
711
712 err_out:
713 for_each_ring(ring, dev_priv, j)
714 I915_WRITE(RING_MODE_GEN7(ring),
715 _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE));
716 return ret;
717 }
718
719 static int gen7_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
720 {
721 struct drm_device *dev = ppgtt->base.dev;
722 drm_i915_private_t *dev_priv = dev->dev_private;
723 struct intel_ring_buffer *ring;
724 uint32_t ecochk, ecobits;
725 int i;
726
727 ecobits = I915_READ(GAC_ECO_BITS);
728 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
729
730 ecochk = I915_READ(GAM_ECOCHK);
731 if (IS_HASWELL(dev)) {
732 ecochk |= ECOCHK_PPGTT_WB_HSW;
733 } else {
734 ecochk |= ECOCHK_PPGTT_LLC_IVB;
735 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
736 }
737 I915_WRITE(GAM_ECOCHK, ecochk);
738
739 for_each_ring(ring, dev_priv, i) {
740 int ret;
741 /* GFX_MODE is per-ring on gen7+ */
742 I915_WRITE(RING_MODE_GEN7(ring),
743 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
744
745 /* We promise to do a switch later with FULL PPGTT. If this is
746 * aliasing, this is the one and only switch we'll do */
747 if (USES_FULL_PPGTT(dev))
748 continue;
749
750 ret = ppgtt->switch_mm(ppgtt, ring, true);
751 if (ret)
752 return ret;
753 }
754
755 return 0;
756 }
757
758 static int gen6_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
759 {
760 struct drm_device *dev = ppgtt->base.dev;
761 drm_i915_private_t *dev_priv = dev->dev_private;
762 struct intel_ring_buffer *ring;
763 uint32_t ecochk, gab_ctl, ecobits;
764 int i;
765
766 ecobits = I915_READ(GAC_ECO_BITS);
767 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
768 ECOBITS_PPGTT_CACHE64B);
769
770 gab_ctl = I915_READ(GAB_CTL);
771 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
772
773 ecochk = I915_READ(GAM_ECOCHK);
774 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
775
776 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
777
778 for_each_ring(ring, dev_priv, i) {
779 int ret = ppgtt->switch_mm(ppgtt, ring, true);
780 if (ret)
781 return ret;
782 }
783
784 return 0;
785 }
786
787 /* PPGTT support for Sandybdrige/Gen6 and later */
788 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
789 unsigned first_entry,
790 unsigned num_entries,
791 bool use_scratch)
792 {
793 struct i915_hw_ppgtt *ppgtt =
794 container_of(vm, struct i915_hw_ppgtt, base);
795 gen6_gtt_pte_t *pt_vaddr, scratch_pte;
796 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
797 unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
798 unsigned last_pte, i;
799
800 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
801
802 while (num_entries) {
803 last_pte = first_pte + num_entries;
804 if (last_pte > I915_PPGTT_PT_ENTRIES)
805 last_pte = I915_PPGTT_PT_ENTRIES;
806
807 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
808
809 for (i = first_pte; i < last_pte; i++)
810 pt_vaddr[i] = scratch_pte;
811
812 kunmap_atomic(pt_vaddr);
813
814 num_entries -= last_pte - first_pte;
815 first_pte = 0;
816 act_pt++;
817 }
818 }
819
820 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
821 struct sg_table *pages,
822 unsigned first_entry,
823 enum i915_cache_level cache_level)
824 {
825 struct i915_hw_ppgtt *ppgtt =
826 container_of(vm, struct i915_hw_ppgtt, base);
827 gen6_gtt_pte_t *pt_vaddr;
828 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
829 unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
830 struct sg_page_iter sg_iter;
831
832 pt_vaddr = NULL;
833 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
834 if (pt_vaddr == NULL)
835 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
836
837 pt_vaddr[act_pte] =
838 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
839 cache_level, true);
840 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
841 kunmap_atomic(pt_vaddr);
842 pt_vaddr = NULL;
843 act_pt++;
844 act_pte = 0;
845 }
846 }
847 if (pt_vaddr)
848 kunmap_atomic(pt_vaddr);
849 }
850
851 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
852 {
853 struct i915_hw_ppgtt *ppgtt =
854 container_of(vm, struct i915_hw_ppgtt, base);
855 int i;
856
857 list_del(&vm->global_link);
858 drm_mm_takedown(&ppgtt->base.mm);
859 drm_mm_remove_node(&ppgtt->node);
860
861 if (ppgtt->pt_dma_addr) {
862 for (i = 0; i < ppgtt->num_pd_entries; i++)
863 pci_unmap_page(ppgtt->base.dev->pdev,
864 ppgtt->pt_dma_addr[i],
865 4096, PCI_DMA_BIDIRECTIONAL);
866 }
867
868 kfree(ppgtt->pt_dma_addr);
869 for (i = 0; i < ppgtt->num_pd_entries; i++)
870 __free_page(ppgtt->pt_pages[i]);
871 kfree(ppgtt->pt_pages);
872 }
873
874 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
875 {
876 #define GEN6_PD_ALIGN (PAGE_SIZE * 16)
877 #define GEN6_PD_SIZE (GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE)
878 struct drm_device *dev = ppgtt->base.dev;
879 struct drm_i915_private *dev_priv = dev->dev_private;
880 bool retried = false;
881 int i, ret;
882
883 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
884 * allocator works in address space sizes, so it's multiplied by page
885 * size. We allocate at the top of the GTT to avoid fragmentation.
886 */
887 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
888 alloc:
889 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
890 &ppgtt->node, GEN6_PD_SIZE,
891 GEN6_PD_ALIGN, 0,
892 0, dev_priv->gtt.base.total,
893 DRM_MM_SEARCH_DEFAULT);
894 if (ret == -ENOSPC && !retried) {
895 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
896 GEN6_PD_SIZE, GEN6_PD_ALIGN,
897 I915_CACHE_NONE, 0);
898 if (ret)
899 return ret;
900
901 retried = true;
902 goto alloc;
903 }
904
905 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
906 DRM_DEBUG("Forced to use aperture for PDEs\n");
907
908 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
909 ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
910 if (IS_GEN6(dev)) {
911 ppgtt->enable = gen6_ppgtt_enable;
912 ppgtt->switch_mm = gen6_mm_switch;
913 } else if (IS_HASWELL(dev)) {
914 ppgtt->enable = gen7_ppgtt_enable;
915 ppgtt->switch_mm = hsw_mm_switch;
916 } else if (IS_GEN7(dev)) {
917 ppgtt->enable = gen7_ppgtt_enable;
918 ppgtt->switch_mm = gen7_mm_switch;
919 } else
920 BUG();
921 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
922 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
923 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
924 ppgtt->base.scratch = dev_priv->gtt.base.scratch;
925 ppgtt->base.start = 0;
926 ppgtt->base.total = GEN6_PPGTT_PD_ENTRIES * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
927 ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
928 GFP_KERNEL);
929 if (!ppgtt->pt_pages) {
930 drm_mm_remove_node(&ppgtt->node);
931 return -ENOMEM;
932 }
933
934 for (i = 0; i < ppgtt->num_pd_entries; i++) {
935 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
936 if (!ppgtt->pt_pages[i])
937 goto err_pt_alloc;
938 }
939
940 ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
941 GFP_KERNEL);
942 if (!ppgtt->pt_dma_addr)
943 goto err_pt_alloc;
944
945 for (i = 0; i < ppgtt->num_pd_entries; i++) {
946 dma_addr_t pt_addr;
947
948 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
949 PCI_DMA_BIDIRECTIONAL);
950
951 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
952 ret = -EIO;
953 goto err_pd_pin;
954
955 }
956 ppgtt->pt_dma_addr[i] = pt_addr;
957 }
958
959 ppgtt->base.clear_range(&ppgtt->base, 0,
960 ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES, true);
961 ppgtt->debug_dump = gen6_dump_ppgtt;
962
963 DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
964 ppgtt->node.size >> 20,
965 ppgtt->node.start / PAGE_SIZE);
966 ppgtt->pd_offset =
967 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t);
968
969 return 0;
970
971 err_pd_pin:
972 if (ppgtt->pt_dma_addr) {
973 for (i--; i >= 0; i--)
974 pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
975 4096, PCI_DMA_BIDIRECTIONAL);
976 }
977 err_pt_alloc:
978 kfree(ppgtt->pt_dma_addr);
979 for (i = 0; i < ppgtt->num_pd_entries; i++) {
980 if (ppgtt->pt_pages[i])
981 __free_page(ppgtt->pt_pages[i]);
982 }
983 kfree(ppgtt->pt_pages);
984 drm_mm_remove_node(&ppgtt->node);
985
986 return ret;
987 }
988
989 int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
990 {
991 struct drm_i915_private *dev_priv = dev->dev_private;
992 int ret = 0;
993
994 ppgtt->base.dev = dev;
995
996 if (INTEL_INFO(dev)->gen < 8)
997 ret = gen6_ppgtt_init(ppgtt);
998 else if (IS_GEN8(dev))
999 ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
1000 else
1001 BUG();
1002
1003 if (!ret) {
1004 struct drm_i915_private *dev_priv = dev->dev_private;
1005 kref_init(&ppgtt->ref);
1006 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1007 ppgtt->base.total);
1008 i915_init_vm(dev_priv, &ppgtt->base);
1009 if (INTEL_INFO(dev)->gen < 8) {
1010 gen6_write_pdes(ppgtt);
1011 DRM_DEBUG("Adding PPGTT at offset %x\n",
1012 ppgtt->pd_offset << 10);
1013 }
1014 }
1015
1016 return ret;
1017 }
1018
1019 static void
1020 ppgtt_bind_vma(struct i915_vma *vma,
1021 enum i915_cache_level cache_level,
1022 u32 flags)
1023 {
1024 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1025
1026 WARN_ON(flags);
1027
1028 vma->vm->insert_entries(vma->vm, vma->obj->pages, entry, cache_level);
1029 }
1030
1031 static void ppgtt_unbind_vma(struct i915_vma *vma)
1032 {
1033 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1034
1035 vma->vm->clear_range(vma->vm,
1036 entry,
1037 vma->obj->base.size >> PAGE_SHIFT,
1038 true);
1039 }
1040
1041 extern int intel_iommu_gfx_mapped;
1042 /* Certain Gen5 chipsets require require idling the GPU before
1043 * unmapping anything from the GTT when VT-d is enabled.
1044 */
1045 static inline bool needs_idle_maps(struct drm_device *dev)
1046 {
1047 #ifdef CONFIG_INTEL_IOMMU
1048 /* Query intel_iommu to see if we need the workaround. Presumably that
1049 * was loaded first.
1050 */
1051 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1052 return true;
1053 #endif
1054 return false;
1055 }
1056
1057 static bool do_idling(struct drm_i915_private *dev_priv)
1058 {
1059 bool ret = dev_priv->mm.interruptible;
1060
1061 if (unlikely(dev_priv->gtt.do_idle_maps)) {
1062 dev_priv->mm.interruptible = false;
1063 if (i915_gpu_idle(dev_priv->dev)) {
1064 DRM_ERROR("Couldn't idle GPU\n");
1065 /* Wait a bit, in hopes it avoids the hang */
1066 udelay(10);
1067 }
1068 }
1069
1070 return ret;
1071 }
1072
1073 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1074 {
1075 if (unlikely(dev_priv->gtt.do_idle_maps))
1076 dev_priv->mm.interruptible = interruptible;
1077 }
1078
1079 void i915_check_and_clear_faults(struct drm_device *dev)
1080 {
1081 struct drm_i915_private *dev_priv = dev->dev_private;
1082 struct intel_ring_buffer *ring;
1083 int i;
1084
1085 if (INTEL_INFO(dev)->gen < 6)
1086 return;
1087
1088 for_each_ring(ring, dev_priv, i) {
1089 u32 fault_reg;
1090 fault_reg = I915_READ(RING_FAULT_REG(ring));
1091 if (fault_reg & RING_FAULT_VALID) {
1092 DRM_DEBUG_DRIVER("Unexpected fault\n"
1093 "\tAddr: 0x%08lx\\n"
1094 "\tAddress space: %s\n"
1095 "\tSource ID: %d\n"
1096 "\tType: %d\n",
1097 fault_reg & PAGE_MASK,
1098 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1099 RING_FAULT_SRCID(fault_reg),
1100 RING_FAULT_FAULT_TYPE(fault_reg));
1101 I915_WRITE(RING_FAULT_REG(ring),
1102 fault_reg & ~RING_FAULT_VALID);
1103 }
1104 }
1105 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1106 }
1107
1108 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1109 {
1110 struct drm_i915_private *dev_priv = dev->dev_private;
1111
1112 /* Don't bother messing with faults pre GEN6 as we have little
1113 * documentation supporting that it's a good idea.
1114 */
1115 if (INTEL_INFO(dev)->gen < 6)
1116 return;
1117
1118 i915_check_and_clear_faults(dev);
1119
1120 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1121 dev_priv->gtt.base.start / PAGE_SIZE,
1122 dev_priv->gtt.base.total / PAGE_SIZE,
1123 false);
1124 }
1125
1126 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
1127 {
1128 struct drm_i915_private *dev_priv = dev->dev_private;
1129 struct drm_i915_gem_object *obj;
1130 struct i915_address_space *vm;
1131
1132 i915_check_and_clear_faults(dev);
1133
1134 /* First fill our portion of the GTT with scratch pages */
1135 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1136 dev_priv->gtt.base.start / PAGE_SIZE,
1137 dev_priv->gtt.base.total / PAGE_SIZE,
1138 true);
1139
1140 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1141 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
1142 &dev_priv->gtt.base);
1143 if (!vma)
1144 continue;
1145
1146 i915_gem_clflush_object(obj, obj->pin_display);
1147 /* The bind_vma code tries to be smart about tracking mappings.
1148 * Unfortunately above, we've just wiped out the mappings
1149 * without telling our object about it. So we need to fake it.
1150 */
1151 obj->has_global_gtt_mapping = 0;
1152 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
1153 }
1154
1155
1156 if (INTEL_INFO(dev)->gen >= 8)
1157 return;
1158
1159 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
1160 /* TODO: Perhaps it shouldn't be gen6 specific */
1161 if (i915_is_ggtt(vm)) {
1162 if (dev_priv->mm.aliasing_ppgtt)
1163 gen6_write_pdes(dev_priv->mm.aliasing_ppgtt);
1164 continue;
1165 }
1166
1167 gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
1168 }
1169
1170 i915_gem_chipset_flush(dev);
1171 }
1172
1173 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1174 {
1175 if (obj->has_dma_mapping)
1176 return 0;
1177
1178 if (!dma_map_sg(&obj->base.dev->pdev->dev,
1179 obj->pages->sgl, obj->pages->nents,
1180 PCI_DMA_BIDIRECTIONAL))
1181 return -ENOSPC;
1182
1183 return 0;
1184 }
1185
1186 static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
1187 {
1188 #ifdef writeq
1189 writeq(pte, addr);
1190 #else
1191 iowrite32((u32)pte, addr);
1192 iowrite32(pte >> 32, addr + 4);
1193 #endif
1194 }
1195
1196 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1197 struct sg_table *st,
1198 unsigned int first_entry,
1199 enum i915_cache_level level)
1200 {
1201 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1202 gen8_gtt_pte_t __iomem *gtt_entries =
1203 (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1204 int i = 0;
1205 struct sg_page_iter sg_iter;
1206 dma_addr_t addr;
1207
1208 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1209 addr = sg_dma_address(sg_iter.sg) +
1210 (sg_iter.sg_pgoffset << PAGE_SHIFT);
1211 gen8_set_pte(&gtt_entries[i],
1212 gen8_pte_encode(addr, level, true));
1213 i++;
1214 }
1215
1216 /*
1217 * XXX: This serves as a posting read to make sure that the PTE has
1218 * actually been updated. There is some concern that even though
1219 * registers and PTEs are within the same BAR that they are potentially
1220 * of NUMA access patterns. Therefore, even with the way we assume
1221 * hardware should work, we must keep this posting read for paranoia.
1222 */
1223 if (i != 0)
1224 WARN_ON(readq(&gtt_entries[i-1])
1225 != gen8_pte_encode(addr, level, true));
1226
1227 /* This next bit makes the above posting read even more important. We
1228 * want to flush the TLBs only after we're certain all the PTE updates
1229 * have finished.
1230 */
1231 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1232 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1233 }
1234
1235 /*
1236 * Binds an object into the global gtt with the specified cache level. The object
1237 * will be accessible to the GPU via commands whose operands reference offsets
1238 * within the global GTT as well as accessible by the GPU through the GMADR
1239 * mapped BAR (dev_priv->mm.gtt->gtt).
1240 */
1241 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1242 struct sg_table *st,
1243 unsigned int first_entry,
1244 enum i915_cache_level level)
1245 {
1246 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1247 gen6_gtt_pte_t __iomem *gtt_entries =
1248 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1249 int i = 0;
1250 struct sg_page_iter sg_iter;
1251 dma_addr_t addr;
1252
1253 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1254 addr = sg_page_iter_dma_address(&sg_iter);
1255 iowrite32(vm->pte_encode(addr, level, true), &gtt_entries[i]);
1256 i++;
1257 }
1258
1259 /* XXX: This serves as a posting read to make sure that the PTE has
1260 * actually been updated. There is some concern that even though
1261 * registers and PTEs are within the same BAR that they are potentially
1262 * of NUMA access patterns. Therefore, even with the way we assume
1263 * hardware should work, we must keep this posting read for paranoia.
1264 */
1265 if (i != 0)
1266 WARN_ON(readl(&gtt_entries[i-1]) !=
1267 vm->pte_encode(addr, level, true));
1268
1269 /* This next bit makes the above posting read even more important. We
1270 * want to flush the TLBs only after we're certain all the PTE updates
1271 * have finished.
1272 */
1273 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1274 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1275 }
1276
1277 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1278 unsigned int first_entry,
1279 unsigned int num_entries,
1280 bool use_scratch)
1281 {
1282 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1283 gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
1284 (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1285 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1286 int i;
1287
1288 if (WARN(num_entries > max_entries,
1289 "First entry = %d; Num entries = %d (max=%d)\n",
1290 first_entry, num_entries, max_entries))
1291 num_entries = max_entries;
1292
1293 scratch_pte = gen8_pte_encode(vm->scratch.addr,
1294 I915_CACHE_LLC,
1295 use_scratch);
1296 for (i = 0; i < num_entries; i++)
1297 gen8_set_pte(&gtt_base[i], scratch_pte);
1298 readl(gtt_base);
1299 }
1300
1301 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1302 unsigned int first_entry,
1303 unsigned int num_entries,
1304 bool use_scratch)
1305 {
1306 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1307 gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
1308 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1309 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1310 int i;
1311
1312 if (WARN(num_entries > max_entries,
1313 "First entry = %d; Num entries = %d (max=%d)\n",
1314 first_entry, num_entries, max_entries))
1315 num_entries = max_entries;
1316
1317 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch);
1318
1319 for (i = 0; i < num_entries; i++)
1320 iowrite32(scratch_pte, &gtt_base[i]);
1321 readl(gtt_base);
1322 }
1323
1324
1325 static void i915_ggtt_bind_vma(struct i915_vma *vma,
1326 enum i915_cache_level cache_level,
1327 u32 unused)
1328 {
1329 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1330 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1331 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1332
1333 BUG_ON(!i915_is_ggtt(vma->vm));
1334 intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags);
1335 vma->obj->has_global_gtt_mapping = 1;
1336 }
1337
1338 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1339 unsigned int first_entry,
1340 unsigned int num_entries,
1341 bool unused)
1342 {
1343 intel_gtt_clear_range(first_entry, num_entries);
1344 }
1345
1346 static void i915_ggtt_unbind_vma(struct i915_vma *vma)
1347 {
1348 const unsigned int first = vma->node.start >> PAGE_SHIFT;
1349 const unsigned int size = vma->obj->base.size >> PAGE_SHIFT;
1350
1351 BUG_ON(!i915_is_ggtt(vma->vm));
1352 vma->obj->has_global_gtt_mapping = 0;
1353 intel_gtt_clear_range(first, size);
1354 }
1355
1356 static void ggtt_bind_vma(struct i915_vma *vma,
1357 enum i915_cache_level cache_level,
1358 u32 flags)
1359 {
1360 struct drm_device *dev = vma->vm->dev;
1361 struct drm_i915_private *dev_priv = dev->dev_private;
1362 struct drm_i915_gem_object *obj = vma->obj;
1363 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1364
1365 /* If there is no aliasing PPGTT, or the caller needs a global mapping,
1366 * or we have a global mapping already but the cacheability flags have
1367 * changed, set the global PTEs.
1368 *
1369 * If there is an aliasing PPGTT it is anecdotally faster, so use that
1370 * instead if none of the above hold true.
1371 *
1372 * NB: A global mapping should only be needed for special regions like
1373 * "gtt mappable", SNB errata, or if specified via special execbuf
1374 * flags. At all other times, the GPU will use the aliasing PPGTT.
1375 */
1376 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1377 if (!obj->has_global_gtt_mapping ||
1378 (cache_level != obj->cache_level)) {
1379 vma->vm->insert_entries(vma->vm, obj->pages, entry,
1380 cache_level);
1381 obj->has_global_gtt_mapping = 1;
1382 }
1383 }
1384
1385 if (dev_priv->mm.aliasing_ppgtt &&
1386 (!obj->has_aliasing_ppgtt_mapping ||
1387 (cache_level != obj->cache_level))) {
1388 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1389 appgtt->base.insert_entries(&appgtt->base,
1390 vma->obj->pages, entry, cache_level);
1391 vma->obj->has_aliasing_ppgtt_mapping = 1;
1392 }
1393 }
1394
1395 static void ggtt_unbind_vma(struct i915_vma *vma)
1396 {
1397 struct drm_device *dev = vma->vm->dev;
1398 struct drm_i915_private *dev_priv = dev->dev_private;
1399 struct drm_i915_gem_object *obj = vma->obj;
1400 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1401
1402 if (obj->has_global_gtt_mapping) {
1403 vma->vm->clear_range(vma->vm, entry,
1404 vma->obj->base.size >> PAGE_SHIFT,
1405 true);
1406 obj->has_global_gtt_mapping = 0;
1407 }
1408
1409 if (obj->has_aliasing_ppgtt_mapping) {
1410 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1411 appgtt->base.clear_range(&appgtt->base,
1412 entry,
1413 obj->base.size >> PAGE_SHIFT,
1414 true);
1415 obj->has_aliasing_ppgtt_mapping = 0;
1416 }
1417 }
1418
1419 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1420 {
1421 struct drm_device *dev = obj->base.dev;
1422 struct drm_i915_private *dev_priv = dev->dev_private;
1423 bool interruptible;
1424
1425 interruptible = do_idling(dev_priv);
1426
1427 if (!obj->has_dma_mapping)
1428 dma_unmap_sg(&dev->pdev->dev,
1429 obj->pages->sgl, obj->pages->nents,
1430 PCI_DMA_BIDIRECTIONAL);
1431
1432 undo_idling(dev_priv, interruptible);
1433 }
1434
1435 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1436 unsigned long color,
1437 unsigned long *start,
1438 unsigned long *end)
1439 {
1440 if (node->color != color)
1441 *start += 4096;
1442
1443 if (!list_empty(&node->node_list)) {
1444 node = list_entry(node->node_list.next,
1445 struct drm_mm_node,
1446 node_list);
1447 if (node->allocated && node->color != color)
1448 *end -= 4096;
1449 }
1450 }
1451
1452 void i915_gem_setup_global_gtt(struct drm_device *dev,
1453 unsigned long start,
1454 unsigned long mappable_end,
1455 unsigned long end)
1456 {
1457 /* Let GEM Manage all of the aperture.
1458 *
1459 * However, leave one page at the end still bound to the scratch page.
1460 * There are a number of places where the hardware apparently prefetches
1461 * past the end of the object, and we've seen multiple hangs with the
1462 * GPU head pointer stuck in a batchbuffer bound at the last page of the
1463 * aperture. One page should be enough to keep any prefetching inside
1464 * of the aperture.
1465 */
1466 struct drm_i915_private *dev_priv = dev->dev_private;
1467 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1468 struct drm_mm_node *entry;
1469 struct drm_i915_gem_object *obj;
1470 unsigned long hole_start, hole_end;
1471
1472 BUG_ON(mappable_end > end);
1473
1474 /* Subtract the guard page ... */
1475 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
1476 if (!HAS_LLC(dev))
1477 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
1478
1479 /* Mark any preallocated objects as occupied */
1480 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1481 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1482 int ret;
1483 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
1484 i915_gem_obj_ggtt_offset(obj), obj->base.size);
1485
1486 WARN_ON(i915_gem_obj_ggtt_bound(obj));
1487 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
1488 if (ret)
1489 DRM_DEBUG_KMS("Reservation failed\n");
1490 obj->has_global_gtt_mapping = 1;
1491 }
1492
1493 dev_priv->gtt.base.start = start;
1494 dev_priv->gtt.base.total = end - start;
1495
1496 /* Clear any non-preallocated blocks */
1497 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
1498 const unsigned long count = (hole_end - hole_start) / PAGE_SIZE;
1499 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1500 hole_start, hole_end);
1501 ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count, true);
1502 }
1503
1504 /* And finally clear the reserved guard page */
1505 ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1, true);
1506 }
1507
1508 void i915_gem_init_global_gtt(struct drm_device *dev)
1509 {
1510 struct drm_i915_private *dev_priv = dev->dev_private;
1511 unsigned long gtt_size, mappable_size;
1512
1513 gtt_size = dev_priv->gtt.base.total;
1514 mappable_size = dev_priv->gtt.mappable_end;
1515
1516 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1517 }
1518
1519 static int setup_scratch_page(struct drm_device *dev)
1520 {
1521 struct drm_i915_private *dev_priv = dev->dev_private;
1522 struct page *page;
1523 dma_addr_t dma_addr;
1524
1525 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
1526 if (page == NULL)
1527 return -ENOMEM;
1528 get_page(page);
1529 set_pages_uc(page, 1);
1530
1531 #ifdef CONFIG_INTEL_IOMMU
1532 dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
1533 PCI_DMA_BIDIRECTIONAL);
1534 if (pci_dma_mapping_error(dev->pdev, dma_addr))
1535 return -EINVAL;
1536 #else
1537 dma_addr = page_to_phys(page);
1538 #endif
1539 dev_priv->gtt.base.scratch.page = page;
1540 dev_priv->gtt.base.scratch.addr = dma_addr;
1541
1542 return 0;
1543 }
1544
1545 static void teardown_scratch_page(struct drm_device *dev)
1546 {
1547 struct drm_i915_private *dev_priv = dev->dev_private;
1548 struct page *page = dev_priv->gtt.base.scratch.page;
1549
1550 set_pages_wb(page, 1);
1551 pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
1552 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1553 put_page(page);
1554 __free_page(page);
1555 }
1556
1557 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
1558 {
1559 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
1560 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
1561 return snb_gmch_ctl << 20;
1562 }
1563
1564 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1565 {
1566 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
1567 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1568 if (bdw_gmch_ctl)
1569 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1570 if (bdw_gmch_ctl > 4) {
1571 WARN_ON(!i915.preliminary_hw_support);
1572 return 4<<20;
1573 }
1574
1575 return bdw_gmch_ctl << 20;
1576 }
1577
1578 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
1579 {
1580 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
1581 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
1582 return snb_gmch_ctl << 25; /* 32 MB units */
1583 }
1584
1585 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
1586 {
1587 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1588 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
1589 return bdw_gmch_ctl << 25; /* 32 MB units */
1590 }
1591
1592 static int ggtt_probe_common(struct drm_device *dev,
1593 size_t gtt_size)
1594 {
1595 struct drm_i915_private *dev_priv = dev->dev_private;
1596 phys_addr_t gtt_bus_addr;
1597 int ret;
1598
1599 /* For Modern GENs the PTEs and register space are split in the BAR */
1600 gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
1601 (pci_resource_len(dev->pdev, 0) / 2);
1602
1603 dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
1604 if (!dev_priv->gtt.gsm) {
1605 DRM_ERROR("Failed to map the gtt page table\n");
1606 return -ENOMEM;
1607 }
1608
1609 ret = setup_scratch_page(dev);
1610 if (ret) {
1611 DRM_ERROR("Scratch setup failed\n");
1612 /* iounmap will also get called at remove, but meh */
1613 iounmap(dev_priv->gtt.gsm);
1614 }
1615
1616 return ret;
1617 }
1618
1619 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
1620 * bits. When using advanced contexts each context stores its own PAT, but
1621 * writing this data shouldn't be harmful even in those cases. */
1622 static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv)
1623 {
1624 #define GEN8_PPAT_UC (0<<0)
1625 #define GEN8_PPAT_WC (1<<0)
1626 #define GEN8_PPAT_WT (2<<0)
1627 #define GEN8_PPAT_WB (3<<0)
1628 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
1629 /* FIXME(BDW): Bspec is completely confused about cache control bits. */
1630 #define GEN8_PPAT_LLC (1<<2)
1631 #define GEN8_PPAT_LLCELLC (2<<2)
1632 #define GEN8_PPAT_LLCeLLC (3<<2)
1633 #define GEN8_PPAT_AGE(x) (x<<4)
1634 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
1635 uint64_t pat;
1636
1637 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
1638 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
1639 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
1640 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
1641 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
1642 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
1643 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
1644 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
1645
1646 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
1647 * write would work. */
1648 I915_WRITE(GEN8_PRIVATE_PAT, pat);
1649 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1650 }
1651
1652 static int gen8_gmch_probe(struct drm_device *dev,
1653 size_t *gtt_total,
1654 size_t *stolen,
1655 phys_addr_t *mappable_base,
1656 unsigned long *mappable_end)
1657 {
1658 struct drm_i915_private *dev_priv = dev->dev_private;
1659 unsigned int gtt_size;
1660 u16 snb_gmch_ctl;
1661 int ret;
1662
1663 /* TODO: We're not aware of mappable constraints on gen8 yet */
1664 *mappable_base = pci_resource_start(dev->pdev, 2);
1665 *mappable_end = pci_resource_len(dev->pdev, 2);
1666
1667 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
1668 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
1669
1670 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1671
1672 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
1673
1674 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
1675 *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
1676
1677 gen8_setup_private_ppat(dev_priv);
1678
1679 ret = ggtt_probe_common(dev, gtt_size);
1680
1681 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
1682 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
1683
1684 return ret;
1685 }
1686
1687 static int gen6_gmch_probe(struct drm_device *dev,
1688 size_t *gtt_total,
1689 size_t *stolen,
1690 phys_addr_t *mappable_base,
1691 unsigned long *mappable_end)
1692 {
1693 struct drm_i915_private *dev_priv = dev->dev_private;
1694 unsigned int gtt_size;
1695 u16 snb_gmch_ctl;
1696 int ret;
1697
1698 *mappable_base = pci_resource_start(dev->pdev, 2);
1699 *mappable_end = pci_resource_len(dev->pdev, 2);
1700
1701 /* 64/512MB is the current min/max we actually know of, but this is just
1702 * a coarse sanity check.
1703 */
1704 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
1705 DRM_ERROR("Unknown GMADR size (%lx)\n",
1706 dev_priv->gtt.mappable_end);
1707 return -ENXIO;
1708 }
1709
1710 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
1711 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
1712 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1713
1714 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
1715
1716 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
1717 *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
1718
1719 ret = ggtt_probe_common(dev, gtt_size);
1720
1721 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
1722 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
1723
1724 return ret;
1725 }
1726
1727 static void gen6_gmch_remove(struct i915_address_space *vm)
1728 {
1729
1730 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
1731
1732 drm_mm_takedown(&vm->mm);
1733 iounmap(gtt->gsm);
1734 teardown_scratch_page(vm->dev);
1735 }
1736
1737 static int i915_gmch_probe(struct drm_device *dev,
1738 size_t *gtt_total,
1739 size_t *stolen,
1740 phys_addr_t *mappable_base,
1741 unsigned long *mappable_end)
1742 {
1743 struct drm_i915_private *dev_priv = dev->dev_private;
1744 int ret;
1745
1746 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
1747 if (!ret) {
1748 DRM_ERROR("failed to set up gmch\n");
1749 return -EIO;
1750 }
1751
1752 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
1753
1754 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
1755 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
1756
1757 if (unlikely(dev_priv->gtt.do_idle_maps))
1758 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
1759
1760 return 0;
1761 }
1762
1763 static void i915_gmch_remove(struct i915_address_space *vm)
1764 {
1765 intel_gmch_remove();
1766 }
1767
1768 int i915_gem_gtt_init(struct drm_device *dev)
1769 {
1770 struct drm_i915_private *dev_priv = dev->dev_private;
1771 struct i915_gtt *gtt = &dev_priv->gtt;
1772 int ret;
1773
1774 if (INTEL_INFO(dev)->gen <= 5) {
1775 gtt->gtt_probe = i915_gmch_probe;
1776 gtt->base.cleanup = i915_gmch_remove;
1777 } else if (INTEL_INFO(dev)->gen < 8) {
1778 gtt->gtt_probe = gen6_gmch_probe;
1779 gtt->base.cleanup = gen6_gmch_remove;
1780 if (IS_HASWELL(dev) && dev_priv->ellc_size)
1781 gtt->base.pte_encode = iris_pte_encode;
1782 else if (IS_HASWELL(dev))
1783 gtt->base.pte_encode = hsw_pte_encode;
1784 else if (IS_VALLEYVIEW(dev))
1785 gtt->base.pte_encode = byt_pte_encode;
1786 else if (INTEL_INFO(dev)->gen >= 7)
1787 gtt->base.pte_encode = ivb_pte_encode;
1788 else
1789 gtt->base.pte_encode = snb_pte_encode;
1790 } else {
1791 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
1792 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
1793 }
1794
1795 ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
1796 &gtt->mappable_base, &gtt->mappable_end);
1797 if (ret)
1798 return ret;
1799
1800 gtt->base.dev = dev;
1801
1802 /* GMADR is the PCI mmio aperture into the global GTT. */
1803 DRM_INFO("Memory usable by graphics device = %zdM\n",
1804 gtt->base.total >> 20);
1805 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
1806 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
1807
1808 return 0;
1809 }
1810
1811 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
1812 struct i915_address_space *vm)
1813 {
1814 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
1815 if (vma == NULL)
1816 return ERR_PTR(-ENOMEM);
1817
1818 INIT_LIST_HEAD(&vma->vma_link);
1819 INIT_LIST_HEAD(&vma->mm_list);
1820 INIT_LIST_HEAD(&vma->exec_list);
1821 vma->vm = vm;
1822 vma->obj = obj;
1823
1824 switch (INTEL_INFO(vm->dev)->gen) {
1825 case 8:
1826 case 7:
1827 case 6:
1828 if (i915_is_ggtt(vm)) {
1829 vma->unbind_vma = ggtt_unbind_vma;
1830 vma->bind_vma = ggtt_bind_vma;
1831 } else {
1832 vma->unbind_vma = ppgtt_unbind_vma;
1833 vma->bind_vma = ppgtt_bind_vma;
1834 }
1835 break;
1836 case 5:
1837 case 4:
1838 case 3:
1839 case 2:
1840 BUG_ON(!i915_is_ggtt(vm));
1841 vma->unbind_vma = i915_ggtt_unbind_vma;
1842 vma->bind_vma = i915_ggtt_bind_vma;
1843 break;
1844 default:
1845 BUG();
1846 }
1847
1848 /* Keep GGTT vmas first to make debug easier */
1849 if (i915_is_ggtt(vm))
1850 list_add(&vma->vma_link, &obj->vma_list);
1851 else
1852 list_add_tail(&vma->vma_link, &obj->vma_list);
1853
1854 return vma;
1855 }
1856
1857 struct i915_vma *
1858 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
1859 struct i915_address_space *vm)
1860 {
1861 struct i915_vma *vma;
1862
1863 vma = i915_gem_obj_to_vma(obj, vm);
1864 if (!vma)
1865 vma = __i915_gem_vma_create(obj, vm);
1866
1867 return vma;
1868 }
Linux kernel - Deliverables
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