2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
28 #include <drm/i915_drm.h>
30 #include "i915_vgpu.h"
31 #include "i915_trace.h"
32 #include "intel_drv.h"
35 * DOC: Global GTT views
37 * Background and previous state
39 * Historically objects could exists (be bound) in global GTT space only as
40 * singular instances with a view representing all of the object's backing pages
41 * in a linear fashion. This view will be called a normal view.
43 * To support multiple views of the same object, where the number of mapped
44 * pages is not equal to the backing store, or where the layout of the pages
45 * is not linear, concept of a GGTT view was added.
47 * One example of an alternative view is a stereo display driven by a single
48 * image. In this case we would have a framebuffer looking like this
54 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
55 * rendering. In contrast, fed to the display engine would be an alternative
56 * view which could look something like this:
61 * In this example both the size and layout of pages in the alternative view is
62 * different from the normal view.
64 * Implementation and usage
66 * GGTT views are implemented using VMAs and are distinguished via enum
67 * i915_ggtt_view_type and struct i915_ggtt_view.
69 * A new flavour of core GEM functions which work with GGTT bound objects were
70 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
71 * renaming in large amounts of code. They take the struct i915_ggtt_view
72 * parameter encapsulating all metadata required to implement a view.
74 * As a helper for callers which are only interested in the normal view,
75 * globally const i915_ggtt_view_normal singleton instance exists. All old core
76 * GEM API functions, the ones not taking the view parameter, are operating on,
77 * or with the normal GGTT view.
79 * Code wanting to add or use a new GGTT view needs to:
81 * 1. Add a new enum with a suitable name.
82 * 2. Extend the metadata in the i915_ggtt_view structure if required.
83 * 3. Add support to i915_get_vma_pages().
85 * New views are required to build a scatter-gather table from within the
86 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
87 * exists for the lifetime of an VMA.
89 * Core API is designed to have copy semantics which means that passed in
90 * struct i915_ggtt_view does not need to be persistent (left around after
91 * calling the core API functions).
96 i915_get_ggtt_vma_pages(struct i915_vma
*vma
);
98 const struct i915_ggtt_view i915_ggtt_view_normal
;
99 const struct i915_ggtt_view i915_ggtt_view_rotated
= {
100 .type
= I915_GGTT_VIEW_ROTATED
103 static int sanitize_enable_ppgtt(struct drm_device
*dev
, int enable_ppgtt
)
105 bool has_aliasing_ppgtt
;
108 has_aliasing_ppgtt
= INTEL_INFO(dev
)->gen
>= 6;
109 has_full_ppgtt
= INTEL_INFO(dev
)->gen
>= 7;
111 if (intel_vgpu_active(dev
))
112 has_full_ppgtt
= false; /* emulation is too hard */
115 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
116 * execlists, the sole mechanism available to submit work.
118 if (INTEL_INFO(dev
)->gen
< 9 &&
119 (enable_ppgtt
== 0 || !has_aliasing_ppgtt
))
122 if (enable_ppgtt
== 1)
125 if (enable_ppgtt
== 2 && has_full_ppgtt
)
128 #ifdef CONFIG_INTEL_IOMMU
129 /* Disable ppgtt on SNB if VT-d is on. */
130 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
) {
131 DRM_INFO("Disabling PPGTT because VT-d is on\n");
136 /* Early VLV doesn't have this */
137 if (IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
138 dev
->pdev
->revision
< 0xb) {
139 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
143 if (INTEL_INFO(dev
)->gen
>= 8 && i915
.enable_execlists
)
146 return has_aliasing_ppgtt
? 1 : 0;
149 static int ppgtt_bind_vma(struct i915_vma
*vma
,
150 enum i915_cache_level cache_level
,
155 /* Currently applicable only to VLV */
157 pte_flags
|= PTE_READ_ONLY
;
159 vma
->vm
->insert_entries(vma
->vm
, vma
->obj
->pages
, vma
->node
.start
,
160 cache_level
, pte_flags
);
165 static void ppgtt_unbind_vma(struct i915_vma
*vma
)
167 vma
->vm
->clear_range(vma
->vm
,
173 static gen8_pte_t
gen8_pte_encode(dma_addr_t addr
,
174 enum i915_cache_level level
,
177 gen8_pte_t pte
= valid
? _PAGE_PRESENT
| _PAGE_RW
: 0;
181 case I915_CACHE_NONE
:
182 pte
|= PPAT_UNCACHED_INDEX
;
185 pte
|= PPAT_DISPLAY_ELLC_INDEX
;
188 pte
|= PPAT_CACHED_INDEX
;
195 static gen8_pde_t
gen8_pde_encode(const dma_addr_t addr
,
196 const enum i915_cache_level level
)
198 gen8_pde_t pde
= _PAGE_PRESENT
| _PAGE_RW
;
200 if (level
!= I915_CACHE_NONE
)
201 pde
|= PPAT_CACHED_PDE_INDEX
;
203 pde
|= PPAT_UNCACHED_INDEX
;
207 static gen6_pte_t
snb_pte_encode(dma_addr_t addr
,
208 enum i915_cache_level level
,
209 bool valid
, u32 unused
)
211 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
212 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
215 case I915_CACHE_L3_LLC
:
217 pte
|= GEN6_PTE_CACHE_LLC
;
219 case I915_CACHE_NONE
:
220 pte
|= GEN6_PTE_UNCACHED
;
229 static gen6_pte_t
ivb_pte_encode(dma_addr_t addr
,
230 enum i915_cache_level level
,
231 bool valid
, u32 unused
)
233 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
234 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
237 case I915_CACHE_L3_LLC
:
238 pte
|= GEN7_PTE_CACHE_L3_LLC
;
241 pte
|= GEN6_PTE_CACHE_LLC
;
243 case I915_CACHE_NONE
:
244 pte
|= GEN6_PTE_UNCACHED
;
253 static gen6_pte_t
byt_pte_encode(dma_addr_t addr
,
254 enum i915_cache_level level
,
255 bool valid
, u32 flags
)
257 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
258 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
260 if (!(flags
& PTE_READ_ONLY
))
261 pte
|= BYT_PTE_WRITEABLE
;
263 if (level
!= I915_CACHE_NONE
)
264 pte
|= BYT_PTE_SNOOPED_BY_CPU_CACHES
;
269 static gen6_pte_t
hsw_pte_encode(dma_addr_t addr
,
270 enum i915_cache_level level
,
271 bool valid
, u32 unused
)
273 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
274 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
276 if (level
!= I915_CACHE_NONE
)
277 pte
|= HSW_WB_LLC_AGE3
;
282 static gen6_pte_t
iris_pte_encode(dma_addr_t addr
,
283 enum i915_cache_level level
,
284 bool valid
, u32 unused
)
286 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
287 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
290 case I915_CACHE_NONE
:
293 pte
|= HSW_WT_ELLC_LLC_AGE3
;
296 pte
|= HSW_WB_ELLC_LLC_AGE3
;
303 static int __setup_page_dma(struct drm_device
*dev
,
304 struct i915_page_dma
*p
, gfp_t flags
)
306 struct device
*device
= &dev
->pdev
->dev
;
308 p
->page
= alloc_page(flags
);
312 p
->daddr
= dma_map_page(device
,
313 p
->page
, 0, 4096, PCI_DMA_BIDIRECTIONAL
);
315 if (dma_mapping_error(device
, p
->daddr
)) {
316 __free_page(p
->page
);
323 static int setup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
325 return __setup_page_dma(dev
, p
, GFP_KERNEL
);
328 static void cleanup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
330 if (WARN_ON(!p
->page
))
333 dma_unmap_page(&dev
->pdev
->dev
, p
->daddr
, 4096, PCI_DMA_BIDIRECTIONAL
);
334 __free_page(p
->page
);
335 memset(p
, 0, sizeof(*p
));
338 static void *kmap_page_dma(struct i915_page_dma
*p
)
340 return kmap_atomic(p
->page
);
343 /* We use the flushing unmap only with ppgtt structures:
344 * page directories, page tables and scratch pages.
346 static void kunmap_page_dma(struct drm_device
*dev
, void *vaddr
)
348 /* There are only few exceptions for gen >=6. chv and bxt.
349 * And we are not sure about the latter so play safe for now.
351 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
352 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
354 kunmap_atomic(vaddr
);
357 #define kmap_px(px) kmap_page_dma(px_base(px))
358 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
360 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
361 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
362 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
363 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
365 static void fill_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
,
369 uint64_t * const vaddr
= kmap_page_dma(p
);
371 for (i
= 0; i
< 512; i
++)
374 kunmap_page_dma(dev
, vaddr
);
377 static void fill_page_dma_32(struct drm_device
*dev
, struct i915_page_dma
*p
,
378 const uint32_t val32
)
384 fill_page_dma(dev
, p
, v
);
387 static struct i915_page_scratch
*alloc_scratch_page(struct drm_device
*dev
)
389 struct i915_page_scratch
*sp
;
392 sp
= kzalloc(sizeof(*sp
), GFP_KERNEL
);
394 return ERR_PTR(-ENOMEM
);
396 ret
= __setup_page_dma(dev
, px_base(sp
), GFP_DMA32
| __GFP_ZERO
);
402 set_pages_uc(px_page(sp
), 1);
407 static void free_scratch_page(struct drm_device
*dev
,
408 struct i915_page_scratch
*sp
)
410 set_pages_wb(px_page(sp
), 1);
416 static struct i915_page_table
*alloc_pt(struct drm_device
*dev
)
418 struct i915_page_table
*pt
;
419 const size_t count
= INTEL_INFO(dev
)->gen
>= 8 ?
420 GEN8_PTES
: GEN6_PTES
;
423 pt
= kzalloc(sizeof(*pt
), GFP_KERNEL
);
425 return ERR_PTR(-ENOMEM
);
427 pt
->used_ptes
= kcalloc(BITS_TO_LONGS(count
), sizeof(*pt
->used_ptes
),
433 ret
= setup_px(dev
, pt
);
440 kfree(pt
->used_ptes
);
447 static void free_pt(struct drm_device
*dev
, struct i915_page_table
*pt
)
450 kfree(pt
->used_ptes
);
454 static void gen8_initialize_pt(struct i915_address_space
*vm
,
455 struct i915_page_table
*pt
)
457 gen8_pte_t scratch_pte
;
459 scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
460 I915_CACHE_LLC
, true);
462 fill_px(vm
->dev
, pt
, scratch_pte
);
465 static void gen6_initialize_pt(struct i915_address_space
*vm
,
466 struct i915_page_table
*pt
)
468 gen6_pte_t scratch_pte
;
470 WARN_ON(px_dma(vm
->scratch_page
) == 0);
472 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
473 I915_CACHE_LLC
, true, 0);
475 fill32_px(vm
->dev
, pt
, scratch_pte
);
478 static struct i915_page_directory
*alloc_pd(struct drm_device
*dev
)
480 struct i915_page_directory
*pd
;
483 pd
= kzalloc(sizeof(*pd
), GFP_KERNEL
);
485 return ERR_PTR(-ENOMEM
);
487 pd
->used_pdes
= kcalloc(BITS_TO_LONGS(I915_PDES
),
488 sizeof(*pd
->used_pdes
), GFP_KERNEL
);
492 ret
= setup_px(dev
, pd
);
499 kfree(pd
->used_pdes
);
506 static void free_pd(struct drm_device
*dev
, struct i915_page_directory
*pd
)
510 kfree(pd
->used_pdes
);
515 static void gen8_initialize_pd(struct i915_address_space
*vm
,
516 struct i915_page_directory
*pd
)
518 gen8_pde_t scratch_pde
;
520 scratch_pde
= gen8_pde_encode(px_dma(vm
->scratch_pt
), I915_CACHE_LLC
);
522 fill_px(vm
->dev
, pd
, scratch_pde
);
525 static int __pdp_init(struct drm_device
*dev
,
526 struct i915_page_directory_pointer
*pdp
)
528 size_t pdpes
= I915_PDPES_PER_PDP(dev
);
530 pdp
->used_pdpes
= kcalloc(BITS_TO_LONGS(pdpes
),
531 sizeof(unsigned long),
533 if (!pdp
->used_pdpes
)
536 pdp
->page_directory
= kcalloc(pdpes
, sizeof(*pdp
->page_directory
),
538 if (!pdp
->page_directory
) {
539 kfree(pdp
->used_pdpes
);
540 /* the PDP might be the statically allocated top level. Keep it
541 * as clean as possible */
542 pdp
->used_pdpes
= NULL
;
549 static void __pdp_fini(struct i915_page_directory_pointer
*pdp
)
551 kfree(pdp
->used_pdpes
);
552 kfree(pdp
->page_directory
);
553 pdp
->page_directory
= NULL
;
556 static void free_pdp(struct drm_device
*dev
,
557 struct i915_page_directory_pointer
*pdp
)
562 /* Broadwell Page Directory Pointer Descriptors */
563 static int gen8_write_pdp(struct drm_i915_gem_request
*req
,
567 struct intel_engine_cs
*ring
= req
->ring
;
572 ret
= intel_ring_begin(req
, 6);
576 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
577 intel_ring_emit(ring
, GEN8_RING_PDP_UDW(ring
, entry
));
578 intel_ring_emit(ring
, upper_32_bits(addr
));
579 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
580 intel_ring_emit(ring
, GEN8_RING_PDP_LDW(ring
, entry
));
581 intel_ring_emit(ring
, lower_32_bits(addr
));
582 intel_ring_advance(ring
);
587 static int gen8_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
588 struct drm_i915_gem_request
*req
)
592 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
593 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
595 ret
= gen8_write_pdp(req
, i
, pd_daddr
);
603 static void gen8_ppgtt_clear_range(struct i915_address_space
*vm
,
608 struct i915_hw_ppgtt
*ppgtt
=
609 container_of(vm
, struct i915_hw_ppgtt
, base
);
610 gen8_pte_t
*pt_vaddr
, scratch_pte
;
611 unsigned pdpe
= start
>> GEN8_PDPE_SHIFT
& GEN8_PDPE_MASK
;
612 unsigned pde
= start
>> GEN8_PDE_SHIFT
& GEN8_PDE_MASK
;
613 unsigned pte
= start
>> GEN8_PTE_SHIFT
& GEN8_PTE_MASK
;
614 unsigned num_entries
= length
>> PAGE_SHIFT
;
615 unsigned last_pte
, i
;
617 scratch_pte
= gen8_pte_encode(px_dma(ppgtt
->base
.scratch_page
),
618 I915_CACHE_LLC
, use_scratch
);
620 while (num_entries
) {
621 struct i915_page_directory
*pd
;
622 struct i915_page_table
*pt
;
624 if (WARN_ON(!ppgtt
->pdp
.page_directory
[pdpe
]))
627 pd
= ppgtt
->pdp
.page_directory
[pdpe
];
629 if (WARN_ON(!pd
->page_table
[pde
]))
632 pt
= pd
->page_table
[pde
];
634 if (WARN_ON(!px_page(pt
)))
637 last_pte
= pte
+ num_entries
;
638 if (last_pte
> GEN8_PTES
)
639 last_pte
= GEN8_PTES
;
641 pt_vaddr
= kmap_px(pt
);
643 for (i
= pte
; i
< last_pte
; i
++) {
644 pt_vaddr
[i
] = scratch_pte
;
648 kunmap_px(ppgtt
, pt
);
651 if (++pde
== I915_PDES
) {
658 static void gen8_ppgtt_insert_entries(struct i915_address_space
*vm
,
659 struct sg_table
*pages
,
661 enum i915_cache_level cache_level
, u32 unused
)
663 struct i915_hw_ppgtt
*ppgtt
=
664 container_of(vm
, struct i915_hw_ppgtt
, base
);
665 gen8_pte_t
*pt_vaddr
;
666 unsigned pdpe
= start
>> GEN8_PDPE_SHIFT
& GEN8_PDPE_MASK
;
667 unsigned pde
= start
>> GEN8_PDE_SHIFT
& GEN8_PDE_MASK
;
668 unsigned pte
= start
>> GEN8_PTE_SHIFT
& GEN8_PTE_MASK
;
669 struct sg_page_iter sg_iter
;
673 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
674 if (WARN_ON(pdpe
>= GEN8_LEGACY_PDPES
))
677 if (pt_vaddr
== NULL
) {
678 struct i915_page_directory
*pd
= ppgtt
->pdp
.page_directory
[pdpe
];
679 struct i915_page_table
*pt
= pd
->page_table
[pde
];
680 pt_vaddr
= kmap_px(pt
);
684 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter
),
686 if (++pte
== GEN8_PTES
) {
687 kunmap_px(ppgtt
, pt_vaddr
);
689 if (++pde
== I915_PDES
) {
698 kunmap_px(ppgtt
, pt_vaddr
);
701 static void gen8_free_page_tables(struct drm_device
*dev
,
702 struct i915_page_directory
*pd
)
709 for_each_set_bit(i
, pd
->used_pdes
, I915_PDES
) {
710 if (WARN_ON(!pd
->page_table
[i
]))
713 free_pt(dev
, pd
->page_table
[i
]);
714 pd
->page_table
[i
] = NULL
;
718 static int gen8_init_scratch(struct i915_address_space
*vm
)
720 struct drm_device
*dev
= vm
->dev
;
722 vm
->scratch_page
= alloc_scratch_page(dev
);
723 if (IS_ERR(vm
->scratch_page
))
724 return PTR_ERR(vm
->scratch_page
);
726 vm
->scratch_pt
= alloc_pt(dev
);
727 if (IS_ERR(vm
->scratch_pt
)) {
728 free_scratch_page(dev
, vm
->scratch_page
);
729 return PTR_ERR(vm
->scratch_pt
);
732 vm
->scratch_pd
= alloc_pd(dev
);
733 if (IS_ERR(vm
->scratch_pd
)) {
734 free_pt(dev
, vm
->scratch_pt
);
735 free_scratch_page(dev
, vm
->scratch_page
);
736 return PTR_ERR(vm
->scratch_pd
);
739 gen8_initialize_pt(vm
, vm
->scratch_pt
);
740 gen8_initialize_pd(vm
, vm
->scratch_pd
);
745 static void gen8_free_scratch(struct i915_address_space
*vm
)
747 struct drm_device
*dev
= vm
->dev
;
749 free_pd(dev
, vm
->scratch_pd
);
750 free_pt(dev
, vm
->scratch_pt
);
751 free_scratch_page(dev
, vm
->scratch_page
);
754 static void gen8_ppgtt_cleanup(struct i915_address_space
*vm
)
756 struct i915_hw_ppgtt
*ppgtt
=
757 container_of(vm
, struct i915_hw_ppgtt
, base
);
760 for_each_set_bit(i
, ppgtt
->pdp
.used_pdpes
,
761 I915_PDPES_PER_PDP(ppgtt
->base
.dev
)) {
762 if (WARN_ON(!ppgtt
->pdp
.page_directory
[i
]))
765 gen8_free_page_tables(ppgtt
->base
.dev
,
766 ppgtt
->pdp
.page_directory
[i
]);
767 free_pd(ppgtt
->base
.dev
, ppgtt
->pdp
.page_directory
[i
]);
770 free_pdp(ppgtt
->base
.dev
, &ppgtt
->pdp
);
771 gen8_free_scratch(vm
);
775 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
776 * @ppgtt: Master ppgtt structure.
777 * @pd: Page directory for this address range.
778 * @start: Starting virtual address to begin allocations.
779 * @length Size of the allocations.
780 * @new_pts: Bitmap set by function with new allocations. Likely used by the
781 * caller to free on error.
783 * Allocate the required number of page tables. Extremely similar to
784 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
785 * the page directory boundary (instead of the page directory pointer). That
786 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
787 * possible, and likely that the caller will need to use multiple calls of this
788 * function to achieve the appropriate allocation.
790 * Return: 0 if success; negative error code otherwise.
792 static int gen8_ppgtt_alloc_pagetabs(struct i915_hw_ppgtt
*ppgtt
,
793 struct i915_page_directory
*pd
,
796 unsigned long *new_pts
)
798 struct drm_device
*dev
= ppgtt
->base
.dev
;
799 struct i915_page_table
*pt
;
803 gen8_for_each_pde(pt
, pd
, start
, length
, temp
, pde
) {
804 /* Don't reallocate page tables */
805 if (test_bit(pde
, pd
->used_pdes
)) {
806 /* Scratch is never allocated this way */
807 WARN_ON(pt
== ppgtt
->base
.scratch_pt
);
815 gen8_initialize_pt(&ppgtt
->base
, pt
);
816 pd
->page_table
[pde
] = pt
;
817 __set_bit(pde
, new_pts
);
823 for_each_set_bit(pde
, new_pts
, I915_PDES
)
824 free_pt(dev
, pd
->page_table
[pde
]);
830 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
831 * @ppgtt: Master ppgtt structure.
832 * @pdp: Page directory pointer for this address range.
833 * @start: Starting virtual address to begin allocations.
834 * @length Size of the allocations.
835 * @new_pds Bitmap set by function with new allocations. Likely used by the
836 * caller to free on error.
838 * Allocate the required number of page directories starting at the pde index of
839 * @start, and ending at the pde index @start + @length. This function will skip
840 * over already allocated page directories within the range, and only allocate
841 * new ones, setting the appropriate pointer within the pdp as well as the
842 * correct position in the bitmap @new_pds.
844 * The function will only allocate the pages within the range for a give page
845 * directory pointer. In other words, if @start + @length straddles a virtually
846 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
847 * required by the caller, This is not currently possible, and the BUG in the
848 * code will prevent it.
850 * Return: 0 if success; negative error code otherwise.
852 static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt
*ppgtt
,
853 struct i915_page_directory_pointer
*pdp
,
856 unsigned long *new_pds
)
858 struct drm_device
*dev
= ppgtt
->base
.dev
;
859 struct i915_page_directory
*pd
;
862 uint32_t pdpes
= I915_PDPES_PER_PDP(dev
);
864 WARN_ON(!bitmap_empty(new_pds
, pdpes
));
866 gen8_for_each_pdpe(pd
, pdp
, start
, length
, temp
, pdpe
) {
867 if (test_bit(pdpe
, pdp
->used_pdpes
))
874 gen8_initialize_pd(&ppgtt
->base
, pd
);
875 pdp
->page_directory
[pdpe
] = pd
;
876 __set_bit(pdpe
, new_pds
);
882 for_each_set_bit(pdpe
, new_pds
, pdpes
)
883 free_pd(dev
, pdp
->page_directory
[pdpe
]);
889 free_gen8_temp_bitmaps(unsigned long *new_pds
, unsigned long **new_pts
,
894 for (i
= 0; i
< pdpes
; i
++)
900 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
901 * of these are based on the number of PDPEs in the system.
904 int __must_check
alloc_gen8_temp_bitmaps(unsigned long **new_pds
,
905 unsigned long ***new_pts
,
912 pds
= kcalloc(BITS_TO_LONGS(pdpes
), sizeof(unsigned long), GFP_KERNEL
);
916 pts
= kcalloc(pdpes
, sizeof(unsigned long *), GFP_KERNEL
);
922 for (i
= 0; i
< pdpes
; i
++) {
923 pts
[i
] = kcalloc(BITS_TO_LONGS(I915_PDES
),
924 sizeof(unsigned long), GFP_KERNEL
);
935 free_gen8_temp_bitmaps(pds
, pts
, pdpes
);
939 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
940 * the page table structures, we mark them dirty so that
941 * context switching/execlist queuing code takes extra steps
942 * to ensure that tlbs are flushed.
944 static void mark_tlbs_dirty(struct i915_hw_ppgtt
*ppgtt
)
946 ppgtt
->pd_dirty_rings
= INTEL_INFO(ppgtt
->base
.dev
)->ring_mask
;
949 static int gen8_alloc_va_range(struct i915_address_space
*vm
,
953 struct i915_hw_ppgtt
*ppgtt
=
954 container_of(vm
, struct i915_hw_ppgtt
, base
);
955 unsigned long *new_page_dirs
, **new_page_tables
;
956 struct i915_page_directory
*pd
;
957 const uint64_t orig_start
= start
;
958 const uint64_t orig_length
= length
;
961 uint32_t pdpes
= I915_PDPES_PER_PDP(ppgtt
->base
.dev
);
964 /* Wrap is never okay since we can only represent 48b, and we don't
965 * actually use the other side of the canonical address space.
967 if (WARN_ON(start
+ length
< start
))
970 if (WARN_ON(start
+ length
> ppgtt
->base
.total
))
973 ret
= alloc_gen8_temp_bitmaps(&new_page_dirs
, &new_page_tables
, pdpes
);
977 /* Do the allocations first so we can easily bail out */
978 ret
= gen8_ppgtt_alloc_page_directories(ppgtt
, &ppgtt
->pdp
, start
, length
,
981 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
, pdpes
);
985 /* For every page directory referenced, allocate page tables */
986 gen8_for_each_pdpe(pd
, &ppgtt
->pdp
, start
, length
, temp
, pdpe
) {
987 ret
= gen8_ppgtt_alloc_pagetabs(ppgtt
, pd
, start
, length
,
988 new_page_tables
[pdpe
]);
994 length
= orig_length
;
996 /* Allocations have completed successfully, so set the bitmaps, and do
998 gen8_for_each_pdpe(pd
, &ppgtt
->pdp
, start
, length
, temp
, pdpe
) {
999 gen8_pde_t
*const page_directory
= kmap_px(pd
);
1000 struct i915_page_table
*pt
;
1001 uint64_t pd_len
= length
;
1002 uint64_t pd_start
= start
;
1005 /* Every pd should be allocated, we just did that above. */
1008 gen8_for_each_pde(pt
, pd
, pd_start
, pd_len
, temp
, pde
) {
1009 /* Same reasoning as pd */
1012 WARN_ON(!gen8_pte_count(pd_start
, pd_len
));
1014 /* Set our used ptes within the page table */
1015 bitmap_set(pt
->used_ptes
,
1016 gen8_pte_index(pd_start
),
1017 gen8_pte_count(pd_start
, pd_len
));
1019 /* Our pde is now pointing to the pagetable, pt */
1020 __set_bit(pde
, pd
->used_pdes
);
1022 /* Map the PDE to the page table */
1023 page_directory
[pde
] = gen8_pde_encode(px_dma(pt
),
1026 /* NB: We haven't yet mapped ptes to pages. At this
1027 * point we're still relying on insert_entries() */
1030 kunmap_px(ppgtt
, page_directory
);
1032 __set_bit(pdpe
, ppgtt
->pdp
.used_pdpes
);
1035 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
, pdpes
);
1036 mark_tlbs_dirty(ppgtt
);
1041 for_each_set_bit(temp
, new_page_tables
[pdpe
], I915_PDES
)
1042 free_pt(vm
->dev
, ppgtt
->pdp
.page_directory
[pdpe
]->page_table
[temp
]);
1045 for_each_set_bit(pdpe
, new_page_dirs
, pdpes
)
1046 free_pd(vm
->dev
, ppgtt
->pdp
.page_directory
[pdpe
]);
1048 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
, pdpes
);
1049 mark_tlbs_dirty(ppgtt
);
1054 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1055 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1056 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1060 static int gen8_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
1064 ret
= gen8_init_scratch(&ppgtt
->base
);
1068 ppgtt
->base
.start
= 0;
1069 ppgtt
->base
.total
= 1ULL << 32;
1070 if (IS_ENABLED(CONFIG_X86_32
))
1071 /* While we have a proliferation of size_t variables
1072 * we cannot represent the full ppgtt size on 32bit,
1073 * so limit it to the same size as the GGTT (currently
1076 ppgtt
->base
.total
= to_i915(ppgtt
->base
.dev
)->gtt
.base
.total
;
1077 ppgtt
->base
.cleanup
= gen8_ppgtt_cleanup
;
1078 ppgtt
->base
.allocate_va_range
= gen8_alloc_va_range
;
1079 ppgtt
->base
.insert_entries
= gen8_ppgtt_insert_entries
;
1080 ppgtt
->base
.clear_range
= gen8_ppgtt_clear_range
;
1081 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
1082 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
1084 ppgtt
->switch_mm
= gen8_mm_switch
;
1086 ret
= __pdp_init(false, &ppgtt
->pdp
);
1094 gen8_free_scratch(&ppgtt
->base
);
1098 static void gen6_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
1100 struct i915_address_space
*vm
= &ppgtt
->base
;
1101 struct i915_page_table
*unused
;
1102 gen6_pte_t scratch_pte
;
1104 uint32_t pte
, pde
, temp
;
1105 uint32_t start
= ppgtt
->base
.start
, length
= ppgtt
->base
.total
;
1107 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1108 I915_CACHE_LLC
, true, 0);
1110 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1112 gen6_pte_t
*pt_vaddr
;
1113 const dma_addr_t pt_addr
= px_dma(ppgtt
->pd
.page_table
[pde
]);
1114 pd_entry
= readl(ppgtt
->pd_addr
+ pde
);
1115 expected
= (GEN6_PDE_ADDR_ENCODE(pt_addr
) | GEN6_PDE_VALID
);
1117 if (pd_entry
!= expected
)
1118 seq_printf(m
, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1122 seq_printf(m
, "\tPDE: %x\n", pd_entry
);
1124 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[pde
]);
1126 for (pte
= 0; pte
< GEN6_PTES
; pte
+=4) {
1128 (pde
* PAGE_SIZE
* GEN6_PTES
) +
1132 for (i
= 0; i
< 4; i
++)
1133 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1138 seq_printf(m
, "\t\t0x%lx [%03d,%04d]: =", va
, pde
, pte
);
1139 for (i
= 0; i
< 4; i
++) {
1140 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1141 seq_printf(m
, " %08x", pt_vaddr
[pte
+ i
]);
1143 seq_puts(m
, " SCRATCH ");
1147 kunmap_px(ppgtt
, pt_vaddr
);
1151 /* Write pde (index) from the page directory @pd to the page table @pt */
1152 static void gen6_write_pde(struct i915_page_directory
*pd
,
1153 const int pde
, struct i915_page_table
*pt
)
1155 /* Caller needs to make sure the write completes if necessary */
1156 struct i915_hw_ppgtt
*ppgtt
=
1157 container_of(pd
, struct i915_hw_ppgtt
, pd
);
1160 pd_entry
= GEN6_PDE_ADDR_ENCODE(px_dma(pt
));
1161 pd_entry
|= GEN6_PDE_VALID
;
1163 writel(pd_entry
, ppgtt
->pd_addr
+ pde
);
1166 /* Write all the page tables found in the ppgtt structure to incrementing page
1168 static void gen6_write_page_range(struct drm_i915_private
*dev_priv
,
1169 struct i915_page_directory
*pd
,
1170 uint32_t start
, uint32_t length
)
1172 struct i915_page_table
*pt
;
1175 gen6_for_each_pde(pt
, pd
, start
, length
, temp
, pde
)
1176 gen6_write_pde(pd
, pde
, pt
);
1178 /* Make sure write is complete before other code can use this page
1179 * table. Also require for WC mapped PTEs */
1180 readl(dev_priv
->gtt
.gsm
);
1183 static uint32_t get_pd_offset(struct i915_hw_ppgtt
*ppgtt
)
1185 BUG_ON(ppgtt
->pd
.base
.ggtt_offset
& 0x3f);
1187 return (ppgtt
->pd
.base
.ggtt_offset
/ 64) << 16;
1190 static int hsw_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1191 struct drm_i915_gem_request
*req
)
1193 struct intel_engine_cs
*ring
= req
->ring
;
1196 /* NB: TLBs must be flushed and invalidated before a switch */
1197 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1201 ret
= intel_ring_begin(req
, 6);
1205 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1206 intel_ring_emit(ring
, RING_PP_DIR_DCLV(ring
));
1207 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1208 intel_ring_emit(ring
, RING_PP_DIR_BASE(ring
));
1209 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1210 intel_ring_emit(ring
, MI_NOOP
);
1211 intel_ring_advance(ring
);
1216 static int vgpu_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1217 struct drm_i915_gem_request
*req
)
1219 struct intel_engine_cs
*ring
= req
->ring
;
1220 struct drm_i915_private
*dev_priv
= to_i915(ppgtt
->base
.dev
);
1222 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
1223 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
1227 static int gen7_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1228 struct drm_i915_gem_request
*req
)
1230 struct intel_engine_cs
*ring
= req
->ring
;
1233 /* NB: TLBs must be flushed and invalidated before a switch */
1234 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1238 ret
= intel_ring_begin(req
, 6);
1242 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1243 intel_ring_emit(ring
, RING_PP_DIR_DCLV(ring
));
1244 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1245 intel_ring_emit(ring
, RING_PP_DIR_BASE(ring
));
1246 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1247 intel_ring_emit(ring
, MI_NOOP
);
1248 intel_ring_advance(ring
);
1250 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1251 if (ring
->id
!= RCS
) {
1252 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1260 static int gen6_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1261 struct drm_i915_gem_request
*req
)
1263 struct intel_engine_cs
*ring
= req
->ring
;
1264 struct drm_device
*dev
= ppgtt
->base
.dev
;
1265 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1268 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
1269 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
1271 POSTING_READ(RING_PP_DIR_DCLV(ring
));
1276 static void gen8_ppgtt_enable(struct drm_device
*dev
)
1278 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1279 struct intel_engine_cs
*ring
;
1282 for_each_ring(ring
, dev_priv
, j
) {
1283 I915_WRITE(RING_MODE_GEN7(ring
),
1284 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1288 static void gen7_ppgtt_enable(struct drm_device
*dev
)
1290 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1291 struct intel_engine_cs
*ring
;
1292 uint32_t ecochk
, ecobits
;
1295 ecobits
= I915_READ(GAC_ECO_BITS
);
1296 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
1298 ecochk
= I915_READ(GAM_ECOCHK
);
1299 if (IS_HASWELL(dev
)) {
1300 ecochk
|= ECOCHK_PPGTT_WB_HSW
;
1302 ecochk
|= ECOCHK_PPGTT_LLC_IVB
;
1303 ecochk
&= ~ECOCHK_PPGTT_GFDT_IVB
;
1305 I915_WRITE(GAM_ECOCHK
, ecochk
);
1307 for_each_ring(ring
, dev_priv
, i
) {
1308 /* GFX_MODE is per-ring on gen7+ */
1309 I915_WRITE(RING_MODE_GEN7(ring
),
1310 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1314 static void gen6_ppgtt_enable(struct drm_device
*dev
)
1316 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1317 uint32_t ecochk
, gab_ctl
, ecobits
;
1319 ecobits
= I915_READ(GAC_ECO_BITS
);
1320 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_SNB_BIT
|
1321 ECOBITS_PPGTT_CACHE64B
);
1323 gab_ctl
= I915_READ(GAB_CTL
);
1324 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
1326 ecochk
= I915_READ(GAM_ECOCHK
);
1327 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
| ECOCHK_PPGTT_CACHE64B
);
1329 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1332 /* PPGTT support for Sandybdrige/Gen6 and later */
1333 static void gen6_ppgtt_clear_range(struct i915_address_space
*vm
,
1338 struct i915_hw_ppgtt
*ppgtt
=
1339 container_of(vm
, struct i915_hw_ppgtt
, base
);
1340 gen6_pte_t
*pt_vaddr
, scratch_pte
;
1341 unsigned first_entry
= start
>> PAGE_SHIFT
;
1342 unsigned num_entries
= length
>> PAGE_SHIFT
;
1343 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1344 unsigned first_pte
= first_entry
% GEN6_PTES
;
1345 unsigned last_pte
, i
;
1347 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1348 I915_CACHE_LLC
, true, 0);
1350 while (num_entries
) {
1351 last_pte
= first_pte
+ num_entries
;
1352 if (last_pte
> GEN6_PTES
)
1353 last_pte
= GEN6_PTES
;
1355 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1357 for (i
= first_pte
; i
< last_pte
; i
++)
1358 pt_vaddr
[i
] = scratch_pte
;
1360 kunmap_px(ppgtt
, pt_vaddr
);
1362 num_entries
-= last_pte
- first_pte
;
1368 static void gen6_ppgtt_insert_entries(struct i915_address_space
*vm
,
1369 struct sg_table
*pages
,
1371 enum i915_cache_level cache_level
, u32 flags
)
1373 struct i915_hw_ppgtt
*ppgtt
=
1374 container_of(vm
, struct i915_hw_ppgtt
, base
);
1375 gen6_pte_t
*pt_vaddr
;
1376 unsigned first_entry
= start
>> PAGE_SHIFT
;
1377 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1378 unsigned act_pte
= first_entry
% GEN6_PTES
;
1379 struct sg_page_iter sg_iter
;
1382 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
1383 if (pt_vaddr
== NULL
)
1384 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1387 vm
->pte_encode(sg_page_iter_dma_address(&sg_iter
),
1388 cache_level
, true, flags
);
1390 if (++act_pte
== GEN6_PTES
) {
1391 kunmap_px(ppgtt
, pt_vaddr
);
1398 kunmap_px(ppgtt
, pt_vaddr
);
1401 static int gen6_alloc_va_range(struct i915_address_space
*vm
,
1402 uint64_t start_in
, uint64_t length_in
)
1404 DECLARE_BITMAP(new_page_tables
, I915_PDES
);
1405 struct drm_device
*dev
= vm
->dev
;
1406 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1407 struct i915_hw_ppgtt
*ppgtt
=
1408 container_of(vm
, struct i915_hw_ppgtt
, base
);
1409 struct i915_page_table
*pt
;
1410 uint32_t start
, length
, start_save
, length_save
;
1414 if (WARN_ON(start_in
+ length_in
> ppgtt
->base
.total
))
1417 start
= start_save
= start_in
;
1418 length
= length_save
= length_in
;
1420 bitmap_zero(new_page_tables
, I915_PDES
);
1422 /* The allocation is done in two stages so that we can bail out with
1423 * minimal amount of pain. The first stage finds new page tables that
1424 * need allocation. The second stage marks use ptes within the page
1427 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1428 if (pt
!= vm
->scratch_pt
) {
1429 WARN_ON(bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1433 /* We've already allocated a page table */
1434 WARN_ON(!bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1442 gen6_initialize_pt(vm
, pt
);
1444 ppgtt
->pd
.page_table
[pde
] = pt
;
1445 __set_bit(pde
, new_page_tables
);
1446 trace_i915_page_table_entry_alloc(vm
, pde
, start
, GEN6_PDE_SHIFT
);
1450 length
= length_save
;
1452 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1453 DECLARE_BITMAP(tmp_bitmap
, GEN6_PTES
);
1455 bitmap_zero(tmp_bitmap
, GEN6_PTES
);
1456 bitmap_set(tmp_bitmap
, gen6_pte_index(start
),
1457 gen6_pte_count(start
, length
));
1459 if (__test_and_clear_bit(pde
, new_page_tables
))
1460 gen6_write_pde(&ppgtt
->pd
, pde
, pt
);
1462 trace_i915_page_table_entry_map(vm
, pde
, pt
,
1463 gen6_pte_index(start
),
1464 gen6_pte_count(start
, length
),
1466 bitmap_or(pt
->used_ptes
, tmp_bitmap
, pt
->used_ptes
,
1470 WARN_ON(!bitmap_empty(new_page_tables
, I915_PDES
));
1472 /* Make sure write is complete before other code can use this page
1473 * table. Also require for WC mapped PTEs */
1474 readl(dev_priv
->gtt
.gsm
);
1476 mark_tlbs_dirty(ppgtt
);
1480 for_each_set_bit(pde
, new_page_tables
, I915_PDES
) {
1481 struct i915_page_table
*pt
= ppgtt
->pd
.page_table
[pde
];
1483 ppgtt
->pd
.page_table
[pde
] = vm
->scratch_pt
;
1484 free_pt(vm
->dev
, pt
);
1487 mark_tlbs_dirty(ppgtt
);
1491 static int gen6_init_scratch(struct i915_address_space
*vm
)
1493 struct drm_device
*dev
= vm
->dev
;
1495 vm
->scratch_page
= alloc_scratch_page(dev
);
1496 if (IS_ERR(vm
->scratch_page
))
1497 return PTR_ERR(vm
->scratch_page
);
1499 vm
->scratch_pt
= alloc_pt(dev
);
1500 if (IS_ERR(vm
->scratch_pt
)) {
1501 free_scratch_page(dev
, vm
->scratch_page
);
1502 return PTR_ERR(vm
->scratch_pt
);
1505 gen6_initialize_pt(vm
, vm
->scratch_pt
);
1510 static void gen6_free_scratch(struct i915_address_space
*vm
)
1512 struct drm_device
*dev
= vm
->dev
;
1514 free_pt(dev
, vm
->scratch_pt
);
1515 free_scratch_page(dev
, vm
->scratch_page
);
1518 static void gen6_ppgtt_cleanup(struct i915_address_space
*vm
)
1520 struct i915_hw_ppgtt
*ppgtt
=
1521 container_of(vm
, struct i915_hw_ppgtt
, base
);
1522 struct i915_page_table
*pt
;
1525 drm_mm_remove_node(&ppgtt
->node
);
1527 gen6_for_all_pdes(pt
, ppgtt
, pde
) {
1528 if (pt
!= vm
->scratch_pt
)
1529 free_pt(ppgtt
->base
.dev
, pt
);
1532 gen6_free_scratch(vm
);
1535 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt
*ppgtt
)
1537 struct i915_address_space
*vm
= &ppgtt
->base
;
1538 struct drm_device
*dev
= ppgtt
->base
.dev
;
1539 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1540 bool retried
= false;
1543 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1544 * allocator works in address space sizes, so it's multiplied by page
1545 * size. We allocate at the top of the GTT to avoid fragmentation.
1547 BUG_ON(!drm_mm_initialized(&dev_priv
->gtt
.base
.mm
));
1549 ret
= gen6_init_scratch(vm
);
1554 ret
= drm_mm_insert_node_in_range_generic(&dev_priv
->gtt
.base
.mm
,
1555 &ppgtt
->node
, GEN6_PD_SIZE
,
1557 0, dev_priv
->gtt
.base
.total
,
1559 if (ret
== -ENOSPC
&& !retried
) {
1560 ret
= i915_gem_evict_something(dev
, &dev_priv
->gtt
.base
,
1561 GEN6_PD_SIZE
, GEN6_PD_ALIGN
,
1563 0, dev_priv
->gtt
.base
.total
,
1576 if (ppgtt
->node
.start
< dev_priv
->gtt
.mappable_end
)
1577 DRM_DEBUG("Forced to use aperture for PDEs\n");
1582 gen6_free_scratch(vm
);
1586 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt
*ppgtt
)
1588 return gen6_ppgtt_allocate_page_directories(ppgtt
);
1591 static void gen6_scratch_va_range(struct i915_hw_ppgtt
*ppgtt
,
1592 uint64_t start
, uint64_t length
)
1594 struct i915_page_table
*unused
;
1597 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, temp
, pde
)
1598 ppgtt
->pd
.page_table
[pde
] = ppgtt
->base
.scratch_pt
;
1601 static int gen6_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
1603 struct drm_device
*dev
= ppgtt
->base
.dev
;
1604 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1607 ppgtt
->base
.pte_encode
= dev_priv
->gtt
.base
.pte_encode
;
1609 ppgtt
->switch_mm
= gen6_mm_switch
;
1610 } else if (IS_HASWELL(dev
)) {
1611 ppgtt
->switch_mm
= hsw_mm_switch
;
1612 } else if (IS_GEN7(dev
)) {
1613 ppgtt
->switch_mm
= gen7_mm_switch
;
1617 if (intel_vgpu_active(dev
))
1618 ppgtt
->switch_mm
= vgpu_mm_switch
;
1620 ret
= gen6_ppgtt_alloc(ppgtt
);
1624 ppgtt
->base
.allocate_va_range
= gen6_alloc_va_range
;
1625 ppgtt
->base
.clear_range
= gen6_ppgtt_clear_range
;
1626 ppgtt
->base
.insert_entries
= gen6_ppgtt_insert_entries
;
1627 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
1628 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
1629 ppgtt
->base
.cleanup
= gen6_ppgtt_cleanup
;
1630 ppgtt
->base
.start
= 0;
1631 ppgtt
->base
.total
= I915_PDES
* GEN6_PTES
* PAGE_SIZE
;
1632 ppgtt
->debug_dump
= gen6_dump_ppgtt
;
1634 ppgtt
->pd
.base
.ggtt_offset
=
1635 ppgtt
->node
.start
/ PAGE_SIZE
* sizeof(gen6_pte_t
);
1637 ppgtt
->pd_addr
= (gen6_pte_t __iomem
*)dev_priv
->gtt
.gsm
+
1638 ppgtt
->pd
.base
.ggtt_offset
/ sizeof(gen6_pte_t
);
1640 gen6_scratch_va_range(ppgtt
, 0, ppgtt
->base
.total
);
1642 gen6_write_page_range(dev_priv
, &ppgtt
->pd
, 0, ppgtt
->base
.total
);
1644 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
1645 ppgtt
->node
.size
>> 20,
1646 ppgtt
->node
.start
/ PAGE_SIZE
);
1648 DRM_DEBUG("Adding PPGTT at offset %x\n",
1649 ppgtt
->pd
.base
.ggtt_offset
<< 10);
1654 static int __hw_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
)
1656 ppgtt
->base
.dev
= dev
;
1658 if (INTEL_INFO(dev
)->gen
< 8)
1659 return gen6_ppgtt_init(ppgtt
);
1661 return gen8_ppgtt_init(ppgtt
);
1664 int i915_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
)
1666 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1669 ret
= __hw_ppgtt_init(dev
, ppgtt
);
1671 kref_init(&ppgtt
->ref
);
1672 drm_mm_init(&ppgtt
->base
.mm
, ppgtt
->base
.start
,
1674 i915_init_vm(dev_priv
, &ppgtt
->base
);
1680 int i915_ppgtt_init_hw(struct drm_device
*dev
)
1682 /* In the case of execlists, PPGTT is enabled by the context descriptor
1683 * and the PDPs are contained within the context itself. We don't
1684 * need to do anything here. */
1685 if (i915
.enable_execlists
)
1688 if (!USES_PPGTT(dev
))
1692 gen6_ppgtt_enable(dev
);
1693 else if (IS_GEN7(dev
))
1694 gen7_ppgtt_enable(dev
);
1695 else if (INTEL_INFO(dev
)->gen
>= 8)
1696 gen8_ppgtt_enable(dev
);
1698 MISSING_CASE(INTEL_INFO(dev
)->gen
);
1703 int i915_ppgtt_init_ring(struct drm_i915_gem_request
*req
)
1705 struct drm_i915_private
*dev_priv
= req
->ring
->dev
->dev_private
;
1706 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1708 if (i915
.enable_execlists
)
1714 return ppgtt
->switch_mm(ppgtt
, req
);
1717 struct i915_hw_ppgtt
*
1718 i915_ppgtt_create(struct drm_device
*dev
, struct drm_i915_file_private
*fpriv
)
1720 struct i915_hw_ppgtt
*ppgtt
;
1723 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
1725 return ERR_PTR(-ENOMEM
);
1727 ret
= i915_ppgtt_init(dev
, ppgtt
);
1730 return ERR_PTR(ret
);
1733 ppgtt
->file_priv
= fpriv
;
1735 trace_i915_ppgtt_create(&ppgtt
->base
);
1740 void i915_ppgtt_release(struct kref
*kref
)
1742 struct i915_hw_ppgtt
*ppgtt
=
1743 container_of(kref
, struct i915_hw_ppgtt
, ref
);
1745 trace_i915_ppgtt_release(&ppgtt
->base
);
1747 /* vmas should already be unbound */
1748 WARN_ON(!list_empty(&ppgtt
->base
.active_list
));
1749 WARN_ON(!list_empty(&ppgtt
->base
.inactive_list
));
1751 list_del(&ppgtt
->base
.global_link
);
1752 drm_mm_takedown(&ppgtt
->base
.mm
);
1754 ppgtt
->base
.cleanup(&ppgtt
->base
);
1758 extern int intel_iommu_gfx_mapped
;
1759 /* Certain Gen5 chipsets require require idling the GPU before
1760 * unmapping anything from the GTT when VT-d is enabled.
1762 static bool needs_idle_maps(struct drm_device
*dev
)
1764 #ifdef CONFIG_INTEL_IOMMU
1765 /* Query intel_iommu to see if we need the workaround. Presumably that
1768 if (IS_GEN5(dev
) && IS_MOBILE(dev
) && intel_iommu_gfx_mapped
)
1774 static bool do_idling(struct drm_i915_private
*dev_priv
)
1776 bool ret
= dev_priv
->mm
.interruptible
;
1778 if (unlikely(dev_priv
->gtt
.do_idle_maps
)) {
1779 dev_priv
->mm
.interruptible
= false;
1780 if (i915_gpu_idle(dev_priv
->dev
)) {
1781 DRM_ERROR("Couldn't idle GPU\n");
1782 /* Wait a bit, in hopes it avoids the hang */
1790 static void undo_idling(struct drm_i915_private
*dev_priv
, bool interruptible
)
1792 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
1793 dev_priv
->mm
.interruptible
= interruptible
;
1796 void i915_check_and_clear_faults(struct drm_device
*dev
)
1798 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1799 struct intel_engine_cs
*ring
;
1802 if (INTEL_INFO(dev
)->gen
< 6)
1805 for_each_ring(ring
, dev_priv
, i
) {
1807 fault_reg
= I915_READ(RING_FAULT_REG(ring
));
1808 if (fault_reg
& RING_FAULT_VALID
) {
1809 DRM_DEBUG_DRIVER("Unexpected fault\n"
1811 "\tAddress space: %s\n"
1814 fault_reg
& PAGE_MASK
,
1815 fault_reg
& RING_FAULT_GTTSEL_MASK
? "GGTT" : "PPGTT",
1816 RING_FAULT_SRCID(fault_reg
),
1817 RING_FAULT_FAULT_TYPE(fault_reg
));
1818 I915_WRITE(RING_FAULT_REG(ring
),
1819 fault_reg
& ~RING_FAULT_VALID
);
1822 POSTING_READ(RING_FAULT_REG(&dev_priv
->ring
[RCS
]));
1825 static void i915_ggtt_flush(struct drm_i915_private
*dev_priv
)
1827 if (INTEL_INFO(dev_priv
->dev
)->gen
< 6) {
1828 intel_gtt_chipset_flush();
1830 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
1831 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
1835 void i915_gem_suspend_gtt_mappings(struct drm_device
*dev
)
1837 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1839 /* Don't bother messing with faults pre GEN6 as we have little
1840 * documentation supporting that it's a good idea.
1842 if (INTEL_INFO(dev
)->gen
< 6)
1845 i915_check_and_clear_faults(dev
);
1847 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
1848 dev_priv
->gtt
.base
.start
,
1849 dev_priv
->gtt
.base
.total
,
1852 i915_ggtt_flush(dev_priv
);
1855 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
)
1857 if (!dma_map_sg(&obj
->base
.dev
->pdev
->dev
,
1858 obj
->pages
->sgl
, obj
->pages
->nents
,
1859 PCI_DMA_BIDIRECTIONAL
))
1865 static void gen8_set_pte(void __iomem
*addr
, gen8_pte_t pte
)
1870 iowrite32((u32
)pte
, addr
);
1871 iowrite32(pte
>> 32, addr
+ 4);
1875 static void gen8_ggtt_insert_entries(struct i915_address_space
*vm
,
1876 struct sg_table
*st
,
1878 enum i915_cache_level level
, u32 unused
)
1880 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1881 unsigned first_entry
= start
>> PAGE_SHIFT
;
1882 gen8_pte_t __iomem
*gtt_entries
=
1883 (gen8_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
1885 struct sg_page_iter sg_iter
;
1886 dma_addr_t addr
= 0; /* shut up gcc */
1888 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
1889 addr
= sg_dma_address(sg_iter
.sg
) +
1890 (sg_iter
.sg_pgoffset
<< PAGE_SHIFT
);
1891 gen8_set_pte(>t_entries
[i
],
1892 gen8_pte_encode(addr
, level
, true));
1897 * XXX: This serves as a posting read to make sure that the PTE has
1898 * actually been updated. There is some concern that even though
1899 * registers and PTEs are within the same BAR that they are potentially
1900 * of NUMA access patterns. Therefore, even with the way we assume
1901 * hardware should work, we must keep this posting read for paranoia.
1904 WARN_ON(readq(>t_entries
[i
-1])
1905 != gen8_pte_encode(addr
, level
, true));
1907 /* This next bit makes the above posting read even more important. We
1908 * want to flush the TLBs only after we're certain all the PTE updates
1911 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
1912 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
1916 * Binds an object into the global gtt with the specified cache level. The object
1917 * will be accessible to the GPU via commands whose operands reference offsets
1918 * within the global GTT as well as accessible by the GPU through the GMADR
1919 * mapped BAR (dev_priv->mm.gtt->gtt).
1921 static void gen6_ggtt_insert_entries(struct i915_address_space
*vm
,
1922 struct sg_table
*st
,
1924 enum i915_cache_level level
, u32 flags
)
1926 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1927 unsigned first_entry
= start
>> PAGE_SHIFT
;
1928 gen6_pte_t __iomem
*gtt_entries
=
1929 (gen6_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
1931 struct sg_page_iter sg_iter
;
1932 dma_addr_t addr
= 0;
1934 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
1935 addr
= sg_page_iter_dma_address(&sg_iter
);
1936 iowrite32(vm
->pte_encode(addr
, level
, true, flags
), >t_entries
[i
]);
1940 /* XXX: This serves as a posting read to make sure that the PTE has
1941 * actually been updated. There is some concern that even though
1942 * registers and PTEs are within the same BAR that they are potentially
1943 * of NUMA access patterns. Therefore, even with the way we assume
1944 * hardware should work, we must keep this posting read for paranoia.
1947 unsigned long gtt
= readl(>t_entries
[i
-1]);
1948 WARN_ON(gtt
!= vm
->pte_encode(addr
, level
, true, flags
));
1951 /* This next bit makes the above posting read even more important. We
1952 * want to flush the TLBs only after we're certain all the PTE updates
1955 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
1956 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
1959 static void gen8_ggtt_clear_range(struct i915_address_space
*vm
,
1964 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1965 unsigned first_entry
= start
>> PAGE_SHIFT
;
1966 unsigned num_entries
= length
>> PAGE_SHIFT
;
1967 gen8_pte_t scratch_pte
, __iomem
*gtt_base
=
1968 (gen8_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
1969 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
1972 if (WARN(num_entries
> max_entries
,
1973 "First entry = %d; Num entries = %d (max=%d)\n",
1974 first_entry
, num_entries
, max_entries
))
1975 num_entries
= max_entries
;
1977 scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
1980 for (i
= 0; i
< num_entries
; i
++)
1981 gen8_set_pte(>t_base
[i
], scratch_pte
);
1985 static void gen6_ggtt_clear_range(struct i915_address_space
*vm
,
1990 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1991 unsigned first_entry
= start
>> PAGE_SHIFT
;
1992 unsigned num_entries
= length
>> PAGE_SHIFT
;
1993 gen6_pte_t scratch_pte
, __iomem
*gtt_base
=
1994 (gen6_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
1995 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
1998 if (WARN(num_entries
> max_entries
,
1999 "First entry = %d; Num entries = %d (max=%d)\n",
2000 first_entry
, num_entries
, max_entries
))
2001 num_entries
= max_entries
;
2003 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
2004 I915_CACHE_LLC
, use_scratch
, 0);
2006 for (i
= 0; i
< num_entries
; i
++)
2007 iowrite32(scratch_pte
, >t_base
[i
]);
2011 static void i915_ggtt_insert_entries(struct i915_address_space
*vm
,
2012 struct sg_table
*pages
,
2014 enum i915_cache_level cache_level
, u32 unused
)
2016 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
2017 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
2019 intel_gtt_insert_sg_entries(pages
, start
>> PAGE_SHIFT
, flags
);
2023 static void i915_ggtt_clear_range(struct i915_address_space
*vm
,
2028 unsigned first_entry
= start
>> PAGE_SHIFT
;
2029 unsigned num_entries
= length
>> PAGE_SHIFT
;
2030 intel_gtt_clear_range(first_entry
, num_entries
);
2033 static int ggtt_bind_vma(struct i915_vma
*vma
,
2034 enum i915_cache_level cache_level
,
2037 struct drm_device
*dev
= vma
->vm
->dev
;
2038 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2039 struct drm_i915_gem_object
*obj
= vma
->obj
;
2040 struct sg_table
*pages
= obj
->pages
;
2044 ret
= i915_get_ggtt_vma_pages(vma
);
2047 pages
= vma
->ggtt_view
.pages
;
2049 /* Currently applicable only to VLV */
2051 pte_flags
|= PTE_READ_ONLY
;
2054 if (!dev_priv
->mm
.aliasing_ppgtt
|| flags
& GLOBAL_BIND
) {
2055 vma
->vm
->insert_entries(vma
->vm
, pages
,
2057 cache_level
, pte_flags
);
2059 /* Note the inconsistency here is due to absence of the
2060 * aliasing ppgtt on gen4 and earlier. Though we always
2061 * request PIN_USER for execbuffer (translated to LOCAL_BIND),
2062 * without the appgtt, we cannot honour that request and so
2063 * must substitute it with a global binding. Since we do this
2064 * behind the upper layers back, we need to explicitly set
2065 * the bound flag ourselves.
2067 vma
->bound
|= GLOBAL_BIND
;
2071 if (dev_priv
->mm
.aliasing_ppgtt
&& flags
& LOCAL_BIND
) {
2072 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2073 appgtt
->base
.insert_entries(&appgtt
->base
, pages
,
2075 cache_level
, pte_flags
);
2081 static void ggtt_unbind_vma(struct i915_vma
*vma
)
2083 struct drm_device
*dev
= vma
->vm
->dev
;
2084 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2085 struct drm_i915_gem_object
*obj
= vma
->obj
;
2086 const uint64_t size
= min_t(uint64_t,
2090 if (vma
->bound
& GLOBAL_BIND
) {
2091 vma
->vm
->clear_range(vma
->vm
,
2097 if (dev_priv
->mm
.aliasing_ppgtt
&& vma
->bound
& LOCAL_BIND
) {
2098 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2100 appgtt
->base
.clear_range(&appgtt
->base
,
2107 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
)
2109 struct drm_device
*dev
= obj
->base
.dev
;
2110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2113 interruptible
= do_idling(dev_priv
);
2115 dma_unmap_sg(&dev
->pdev
->dev
, obj
->pages
->sgl
, obj
->pages
->nents
,
2116 PCI_DMA_BIDIRECTIONAL
);
2118 undo_idling(dev_priv
, interruptible
);
2121 static void i915_gtt_color_adjust(struct drm_mm_node
*node
,
2122 unsigned long color
,
2126 if (node
->color
!= color
)
2129 if (!list_empty(&node
->node_list
)) {
2130 node
= list_entry(node
->node_list
.next
,
2133 if (node
->allocated
&& node
->color
!= color
)
2138 static int i915_gem_setup_global_gtt(struct drm_device
*dev
,
2139 unsigned long start
,
2140 unsigned long mappable_end
,
2143 /* Let GEM Manage all of the aperture.
2145 * However, leave one page at the end still bound to the scratch page.
2146 * There are a number of places where the hardware apparently prefetches
2147 * past the end of the object, and we've seen multiple hangs with the
2148 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2149 * aperture. One page should be enough to keep any prefetching inside
2152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2153 struct i915_address_space
*ggtt_vm
= &dev_priv
->gtt
.base
;
2154 struct drm_mm_node
*entry
;
2155 struct drm_i915_gem_object
*obj
;
2156 unsigned long hole_start
, hole_end
;
2159 BUG_ON(mappable_end
> end
);
2161 /* Subtract the guard page ... */
2162 drm_mm_init(&ggtt_vm
->mm
, start
, end
- start
- PAGE_SIZE
);
2164 dev_priv
->gtt
.base
.start
= start
;
2165 dev_priv
->gtt
.base
.total
= end
- start
;
2167 if (intel_vgpu_active(dev
)) {
2168 ret
= intel_vgt_balloon(dev
);
2174 dev_priv
->gtt
.base
.mm
.color_adjust
= i915_gtt_color_adjust
;
2176 /* Mark any preallocated objects as occupied */
2177 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
2178 struct i915_vma
*vma
= i915_gem_obj_to_vma(obj
, ggtt_vm
);
2180 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
2181 i915_gem_obj_ggtt_offset(obj
), obj
->base
.size
);
2183 WARN_ON(i915_gem_obj_ggtt_bound(obj
));
2184 ret
= drm_mm_reserve_node(&ggtt_vm
->mm
, &vma
->node
);
2186 DRM_DEBUG_KMS("Reservation failed: %i\n", ret
);
2189 vma
->bound
|= GLOBAL_BIND
;
2192 /* Clear any non-preallocated blocks */
2193 drm_mm_for_each_hole(entry
, &ggtt_vm
->mm
, hole_start
, hole_end
) {
2194 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2195 hole_start
, hole_end
);
2196 ggtt_vm
->clear_range(ggtt_vm
, hole_start
,
2197 hole_end
- hole_start
, true);
2200 /* And finally clear the reserved guard page */
2201 ggtt_vm
->clear_range(ggtt_vm
, end
- PAGE_SIZE
, PAGE_SIZE
, true);
2203 if (USES_PPGTT(dev
) && !USES_FULL_PPGTT(dev
)) {
2204 struct i915_hw_ppgtt
*ppgtt
;
2206 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
2210 ret
= __hw_ppgtt_init(dev
, ppgtt
);
2212 ppgtt
->base
.cleanup(&ppgtt
->base
);
2217 if (ppgtt
->base
.allocate_va_range
)
2218 ret
= ppgtt
->base
.allocate_va_range(&ppgtt
->base
, 0,
2221 ppgtt
->base
.cleanup(&ppgtt
->base
);
2226 ppgtt
->base
.clear_range(&ppgtt
->base
,
2231 dev_priv
->mm
.aliasing_ppgtt
= ppgtt
;
2237 void i915_gem_init_global_gtt(struct drm_device
*dev
)
2239 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2240 u64 gtt_size
, mappable_size
;
2242 gtt_size
= dev_priv
->gtt
.base
.total
;
2243 mappable_size
= dev_priv
->gtt
.mappable_end
;
2245 i915_gem_setup_global_gtt(dev
, 0, mappable_size
, gtt_size
);
2248 void i915_global_gtt_cleanup(struct drm_device
*dev
)
2250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2251 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
2253 if (dev_priv
->mm
.aliasing_ppgtt
) {
2254 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2256 ppgtt
->base
.cleanup(&ppgtt
->base
);
2259 if (drm_mm_initialized(&vm
->mm
)) {
2260 if (intel_vgpu_active(dev
))
2261 intel_vgt_deballoon();
2263 drm_mm_takedown(&vm
->mm
);
2264 list_del(&vm
->global_link
);
2270 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
2272 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
2273 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
2274 return snb_gmch_ctl
<< 20;
2277 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl
)
2279 bdw_gmch_ctl
>>= BDW_GMCH_GGMS_SHIFT
;
2280 bdw_gmch_ctl
&= BDW_GMCH_GGMS_MASK
;
2282 bdw_gmch_ctl
= 1 << bdw_gmch_ctl
;
2284 #ifdef CONFIG_X86_32
2285 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2286 if (bdw_gmch_ctl
> 4)
2290 return bdw_gmch_ctl
<< 20;
2293 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl
)
2295 gmch_ctrl
>>= SNB_GMCH_GGMS_SHIFT
;
2296 gmch_ctrl
&= SNB_GMCH_GGMS_MASK
;
2299 return 1 << (20 + gmch_ctrl
);
2304 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl
)
2306 snb_gmch_ctl
>>= SNB_GMCH_GMS_SHIFT
;
2307 snb_gmch_ctl
&= SNB_GMCH_GMS_MASK
;
2308 return snb_gmch_ctl
<< 25; /* 32 MB units */
2311 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl
)
2313 bdw_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2314 bdw_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2315 return bdw_gmch_ctl
<< 25; /* 32 MB units */
2318 static size_t chv_get_stolen_size(u16 gmch_ctrl
)
2320 gmch_ctrl
>>= SNB_GMCH_GMS_SHIFT
;
2321 gmch_ctrl
&= SNB_GMCH_GMS_MASK
;
2324 * 0x0 to 0x10: 32MB increments starting at 0MB
2325 * 0x11 to 0x16: 4MB increments starting at 8MB
2326 * 0x17 to 0x1d: 4MB increments start at 36MB
2328 if (gmch_ctrl
< 0x11)
2329 return gmch_ctrl
<< 25;
2330 else if (gmch_ctrl
< 0x17)
2331 return (gmch_ctrl
- 0x11 + 2) << 22;
2333 return (gmch_ctrl
- 0x17 + 9) << 22;
2336 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl
)
2338 gen9_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2339 gen9_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2341 if (gen9_gmch_ctl
< 0xf0)
2342 return gen9_gmch_ctl
<< 25; /* 32 MB units */
2344 /* 4MB increments starting at 0xf0 for 4MB */
2345 return (gen9_gmch_ctl
- 0xf0 + 1) << 22;
2348 static int ggtt_probe_common(struct drm_device
*dev
,
2351 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2352 struct i915_page_scratch
*scratch_page
;
2353 phys_addr_t gtt_phys_addr
;
2355 /* For Modern GENs the PTEs and register space are split in the BAR */
2356 gtt_phys_addr
= pci_resource_start(dev
->pdev
, 0) +
2357 (pci_resource_len(dev
->pdev
, 0) / 2);
2360 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2361 * dropped. For WC mappings in general we have 64 byte burst writes
2362 * when the WC buffer is flushed, so we can't use it, but have to
2363 * resort to an uncached mapping. The WC issue is easily caught by the
2364 * readback check when writing GTT PTE entries.
2366 if (IS_BROXTON(dev
))
2367 dev_priv
->gtt
.gsm
= ioremap_nocache(gtt_phys_addr
, gtt_size
);
2369 dev_priv
->gtt
.gsm
= ioremap_wc(gtt_phys_addr
, gtt_size
);
2370 if (!dev_priv
->gtt
.gsm
) {
2371 DRM_ERROR("Failed to map the gtt page table\n");
2375 scratch_page
= alloc_scratch_page(dev
);
2376 if (IS_ERR(scratch_page
)) {
2377 DRM_ERROR("Scratch setup failed\n");
2378 /* iounmap will also get called at remove, but meh */
2379 iounmap(dev_priv
->gtt
.gsm
);
2380 return PTR_ERR(scratch_page
);
2383 dev_priv
->gtt
.base
.scratch_page
= scratch_page
;
2388 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2389 * bits. When using advanced contexts each context stores its own PAT, but
2390 * writing this data shouldn't be harmful even in those cases. */
2391 static void bdw_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2395 pat
= GEN8_PPAT(0, GEN8_PPAT_WB
| GEN8_PPAT_LLC
) | /* for normal objects, no eLLC */
2396 GEN8_PPAT(1, GEN8_PPAT_WC
| GEN8_PPAT_LLCELLC
) | /* for something pointing to ptes? */
2397 GEN8_PPAT(2, GEN8_PPAT_WT
| GEN8_PPAT_LLCELLC
) | /* for scanout with eLLC */
2398 GEN8_PPAT(3, GEN8_PPAT_UC
) | /* Uncached objects, mostly for scanout */
2399 GEN8_PPAT(4, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(0)) |
2400 GEN8_PPAT(5, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(1)) |
2401 GEN8_PPAT(6, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(2)) |
2402 GEN8_PPAT(7, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(3));
2404 if (!USES_PPGTT(dev_priv
->dev
))
2405 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2406 * so RTL will always use the value corresponding to
2408 * So let's disable cache for GGTT to avoid screen corruptions.
2409 * MOCS still can be used though.
2410 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2411 * before this patch, i.e. the same uncached + snooping access
2412 * like on gen6/7 seems to be in effect.
2413 * - So this just fixes blitter/render access. Again it looks
2414 * like it's not just uncached access, but uncached + snooping.
2415 * So we can still hold onto all our assumptions wrt cpu
2416 * clflushing on LLC machines.
2418 pat
= GEN8_PPAT(0, GEN8_PPAT_UC
);
2420 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2421 * write would work. */
2422 I915_WRITE(GEN8_PRIVATE_PAT
, pat
);
2423 I915_WRITE(GEN8_PRIVATE_PAT
+ 4, pat
>> 32);
2426 static void chv_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2431 * Map WB on BDW to snooped on CHV.
2433 * Only the snoop bit has meaning for CHV, the rest is
2436 * The hardware will never snoop for certain types of accesses:
2437 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2438 * - PPGTT page tables
2439 * - some other special cycles
2441 * As with BDW, we also need to consider the following for GT accesses:
2442 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2443 * so RTL will always use the value corresponding to
2445 * Which means we must set the snoop bit in PAT entry 0
2446 * in order to keep the global status page working.
2448 pat
= GEN8_PPAT(0, CHV_PPAT_SNOOP
) |
2452 GEN8_PPAT(4, CHV_PPAT_SNOOP
) |
2453 GEN8_PPAT(5, CHV_PPAT_SNOOP
) |
2454 GEN8_PPAT(6, CHV_PPAT_SNOOP
) |
2455 GEN8_PPAT(7, CHV_PPAT_SNOOP
);
2457 I915_WRITE(GEN8_PRIVATE_PAT
, pat
);
2458 I915_WRITE(GEN8_PRIVATE_PAT
+ 4, pat
>> 32);
2461 static int gen8_gmch_probe(struct drm_device
*dev
,
2464 phys_addr_t
*mappable_base
,
2467 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2472 /* TODO: We're not aware of mappable constraints on gen8 yet */
2473 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
2474 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
2476 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(39)))
2477 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(39));
2479 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
2481 if (INTEL_INFO(dev
)->gen
>= 9) {
2482 *stolen
= gen9_get_stolen_size(snb_gmch_ctl
);
2483 gtt_size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
2484 } else if (IS_CHERRYVIEW(dev
)) {
2485 *stolen
= chv_get_stolen_size(snb_gmch_ctl
);
2486 gtt_size
= chv_get_total_gtt_size(snb_gmch_ctl
);
2488 *stolen
= gen8_get_stolen_size(snb_gmch_ctl
);
2489 gtt_size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
2492 *gtt_total
= (gtt_size
/ sizeof(gen8_pte_t
)) << PAGE_SHIFT
;
2494 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
2495 chv_setup_private_ppat(dev_priv
);
2497 bdw_setup_private_ppat(dev_priv
);
2499 ret
= ggtt_probe_common(dev
, gtt_size
);
2501 dev_priv
->gtt
.base
.clear_range
= gen8_ggtt_clear_range
;
2502 dev_priv
->gtt
.base
.insert_entries
= gen8_ggtt_insert_entries
;
2503 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
2504 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
2509 static int gen6_gmch_probe(struct drm_device
*dev
,
2512 phys_addr_t
*mappable_base
,
2515 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2516 unsigned int gtt_size
;
2520 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
2521 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
2523 /* 64/512MB is the current min/max we actually know of, but this is just
2524 * a coarse sanity check.
2526 if ((*mappable_end
< (64<<20) || (*mappable_end
> (512<<20)))) {
2527 DRM_ERROR("Unknown GMADR size (%llx)\n",
2528 dev_priv
->gtt
.mappable_end
);
2532 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(40)))
2533 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(40));
2534 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
2536 *stolen
= gen6_get_stolen_size(snb_gmch_ctl
);
2538 gtt_size
= gen6_get_total_gtt_size(snb_gmch_ctl
);
2539 *gtt_total
= (gtt_size
/ sizeof(gen6_pte_t
)) << PAGE_SHIFT
;
2541 ret
= ggtt_probe_common(dev
, gtt_size
);
2543 dev_priv
->gtt
.base
.clear_range
= gen6_ggtt_clear_range
;
2544 dev_priv
->gtt
.base
.insert_entries
= gen6_ggtt_insert_entries
;
2545 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
2546 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
2551 static void gen6_gmch_remove(struct i915_address_space
*vm
)
2554 struct i915_gtt
*gtt
= container_of(vm
, struct i915_gtt
, base
);
2557 free_scratch_page(vm
->dev
, vm
->scratch_page
);
2560 static int i915_gmch_probe(struct drm_device
*dev
,
2563 phys_addr_t
*mappable_base
,
2566 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2569 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev_priv
->dev
->pdev
, NULL
);
2571 DRM_ERROR("failed to set up gmch\n");
2575 intel_gtt_get(gtt_total
, stolen
, mappable_base
, mappable_end
);
2577 dev_priv
->gtt
.do_idle_maps
= needs_idle_maps(dev_priv
->dev
);
2578 dev_priv
->gtt
.base
.insert_entries
= i915_ggtt_insert_entries
;
2579 dev_priv
->gtt
.base
.clear_range
= i915_ggtt_clear_range
;
2580 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
2581 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
2583 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
2584 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2589 static void i915_gmch_remove(struct i915_address_space
*vm
)
2591 intel_gmch_remove();
2594 int i915_gem_gtt_init(struct drm_device
*dev
)
2596 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2597 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
2600 if (INTEL_INFO(dev
)->gen
<= 5) {
2601 gtt
->gtt_probe
= i915_gmch_probe
;
2602 gtt
->base
.cleanup
= i915_gmch_remove
;
2603 } else if (INTEL_INFO(dev
)->gen
< 8) {
2604 gtt
->gtt_probe
= gen6_gmch_probe
;
2605 gtt
->base
.cleanup
= gen6_gmch_remove
;
2606 if (IS_HASWELL(dev
) && dev_priv
->ellc_size
)
2607 gtt
->base
.pte_encode
= iris_pte_encode
;
2608 else if (IS_HASWELL(dev
))
2609 gtt
->base
.pte_encode
= hsw_pte_encode
;
2610 else if (IS_VALLEYVIEW(dev
))
2611 gtt
->base
.pte_encode
= byt_pte_encode
;
2612 else if (INTEL_INFO(dev
)->gen
>= 7)
2613 gtt
->base
.pte_encode
= ivb_pte_encode
;
2615 gtt
->base
.pte_encode
= snb_pte_encode
;
2617 dev_priv
->gtt
.gtt_probe
= gen8_gmch_probe
;
2618 dev_priv
->gtt
.base
.cleanup
= gen6_gmch_remove
;
2621 gtt
->base
.dev
= dev
;
2623 ret
= gtt
->gtt_probe(dev
, >t
->base
.total
, >t
->stolen_size
,
2624 >t
->mappable_base
, >t
->mappable_end
);
2628 /* GMADR is the PCI mmio aperture into the global GTT. */
2629 DRM_INFO("Memory usable by graphics device = %lluM\n",
2630 gtt
->base
.total
>> 20);
2631 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt
->mappable_end
>> 20);
2632 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt
->stolen_size
>> 20);
2633 #ifdef CONFIG_INTEL_IOMMU
2634 if (intel_iommu_gfx_mapped
)
2635 DRM_INFO("VT-d active for gfx access\n");
2638 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2639 * user's requested state against the hardware/driver capabilities. We
2640 * do this now so that we can print out any log messages once rather
2641 * than every time we check intel_enable_ppgtt().
2643 i915
.enable_ppgtt
= sanitize_enable_ppgtt(dev
, i915
.enable_ppgtt
);
2644 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915
.enable_ppgtt
);
2649 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
)
2651 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2652 struct drm_i915_gem_object
*obj
;
2653 struct i915_address_space
*vm
;
2654 struct i915_vma
*vma
;
2657 i915_check_and_clear_faults(dev
);
2659 /* First fill our portion of the GTT with scratch pages */
2660 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
2661 dev_priv
->gtt
.base
.start
,
2662 dev_priv
->gtt
.base
.total
,
2665 /* Cache flush objects bound into GGTT and rebind them. */
2666 vm
= &dev_priv
->gtt
.base
;
2667 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
2669 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
2673 WARN_ON(i915_vma_bind(vma
, obj
->cache_level
,
2680 i915_gem_clflush_object(obj
, obj
->pin_display
);
2683 if (INTEL_INFO(dev
)->gen
>= 8) {
2684 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
2685 chv_setup_private_ppat(dev_priv
);
2687 bdw_setup_private_ppat(dev_priv
);
2692 if (USES_PPGTT(dev
)) {
2693 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
2694 /* TODO: Perhaps it shouldn't be gen6 specific */
2696 struct i915_hw_ppgtt
*ppgtt
=
2697 container_of(vm
, struct i915_hw_ppgtt
,
2700 if (i915_is_ggtt(vm
))
2701 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2703 gen6_write_page_range(dev_priv
, &ppgtt
->pd
,
2704 0, ppgtt
->base
.total
);
2708 i915_ggtt_flush(dev_priv
);
2711 static struct i915_vma
*
2712 __i915_gem_vma_create(struct drm_i915_gem_object
*obj
,
2713 struct i915_address_space
*vm
,
2714 const struct i915_ggtt_view
*ggtt_view
)
2716 struct i915_vma
*vma
;
2718 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
2719 return ERR_PTR(-EINVAL
);
2721 vma
= kmem_cache_zalloc(to_i915(obj
->base
.dev
)->vmas
, GFP_KERNEL
);
2723 return ERR_PTR(-ENOMEM
);
2725 INIT_LIST_HEAD(&vma
->vma_link
);
2726 INIT_LIST_HEAD(&vma
->mm_list
);
2727 INIT_LIST_HEAD(&vma
->exec_list
);
2731 if (i915_is_ggtt(vm
))
2732 vma
->ggtt_view
= *ggtt_view
;
2734 list_add_tail(&vma
->vma_link
, &obj
->vma_list
);
2735 if (!i915_is_ggtt(vm
))
2736 i915_ppgtt_get(i915_vm_to_ppgtt(vm
));
2742 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2743 struct i915_address_space
*vm
)
2745 struct i915_vma
*vma
;
2747 vma
= i915_gem_obj_to_vma(obj
, vm
);
2749 vma
= __i915_gem_vma_create(obj
, vm
,
2750 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
);
2756 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
2757 const struct i915_ggtt_view
*view
)
2759 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
2760 struct i915_vma
*vma
;
2763 return ERR_PTR(-EINVAL
);
2765 vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
2771 vma
= __i915_gem_vma_create(obj
, ggtt
, view
);
2778 rotate_pages(dma_addr_t
*in
, unsigned int width
, unsigned int height
,
2779 struct sg_table
*st
)
2781 unsigned int column
, row
;
2782 unsigned int src_idx
;
2783 struct scatterlist
*sg
= st
->sgl
;
2787 for (column
= 0; column
< width
; column
++) {
2788 src_idx
= width
* (height
- 1) + column
;
2789 for (row
= 0; row
< height
; row
++) {
2791 /* We don't need the pages, but need to initialize
2792 * the entries so the sg list can be happily traversed.
2793 * The only thing we need are DMA addresses.
2795 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
2796 sg_dma_address(sg
) = in
[src_idx
];
2797 sg_dma_len(sg
) = PAGE_SIZE
;
2804 static struct sg_table
*
2805 intel_rotate_fb_obj_pages(struct i915_ggtt_view
*ggtt_view
,
2806 struct drm_i915_gem_object
*obj
)
2808 struct intel_rotation_info
*rot_info
= &ggtt_view
->rotation_info
;
2809 unsigned int size_pages
= rot_info
->size
>> PAGE_SHIFT
;
2810 struct sg_page_iter sg_iter
;
2812 dma_addr_t
*page_addr_list
;
2813 struct sg_table
*st
;
2816 /* Allocate a temporary list of source pages for random access. */
2817 page_addr_list
= drm_malloc_ab(obj
->base
.size
/ PAGE_SIZE
,
2818 sizeof(dma_addr_t
));
2819 if (!page_addr_list
)
2820 return ERR_PTR(ret
);
2822 /* Allocate target SG list. */
2823 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2827 ret
= sg_alloc_table(st
, size_pages
, GFP_KERNEL
);
2831 /* Populate source page list from the object. */
2833 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
2834 page_addr_list
[i
] = sg_page_iter_dma_address(&sg_iter
);
2838 /* Rotate the pages. */
2839 rotate_pages(page_addr_list
,
2840 rot_info
->width_pages
, rot_info
->height_pages
,
2844 "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages).\n",
2845 obj
->base
.size
, rot_info
->pitch
, rot_info
->height
,
2846 rot_info
->pixel_format
, rot_info
->width_pages
,
2847 rot_info
->height_pages
, size_pages
);
2849 drm_free_large(page_addr_list
);
2856 drm_free_large(page_addr_list
);
2859 "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages)\n",
2860 obj
->base
.size
, ret
, rot_info
->pitch
, rot_info
->height
,
2861 rot_info
->pixel_format
, rot_info
->width_pages
,
2862 rot_info
->height_pages
, size_pages
);
2863 return ERR_PTR(ret
);
2866 static struct sg_table
*
2867 intel_partial_pages(const struct i915_ggtt_view
*view
,
2868 struct drm_i915_gem_object
*obj
)
2870 struct sg_table
*st
;
2871 struct scatterlist
*sg
;
2872 struct sg_page_iter obj_sg_iter
;
2875 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2879 ret
= sg_alloc_table(st
, view
->params
.partial
.size
, GFP_KERNEL
);
2885 for_each_sg_page(obj
->pages
->sgl
, &obj_sg_iter
, obj
->pages
->nents
,
2886 view
->params
.partial
.offset
)
2888 if (st
->nents
>= view
->params
.partial
.size
)
2891 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
2892 sg_dma_address(sg
) = sg_page_iter_dma_address(&obj_sg_iter
);
2893 sg_dma_len(sg
) = PAGE_SIZE
;
2904 return ERR_PTR(ret
);
2908 i915_get_ggtt_vma_pages(struct i915_vma
*vma
)
2912 if (vma
->ggtt_view
.pages
)
2915 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
)
2916 vma
->ggtt_view
.pages
= vma
->obj
->pages
;
2917 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_ROTATED
)
2918 vma
->ggtt_view
.pages
=
2919 intel_rotate_fb_obj_pages(&vma
->ggtt_view
, vma
->obj
);
2920 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_PARTIAL
)
2921 vma
->ggtt_view
.pages
=
2922 intel_partial_pages(&vma
->ggtt_view
, vma
->obj
);
2924 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2925 vma
->ggtt_view
.type
);
2927 if (!vma
->ggtt_view
.pages
) {
2928 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
2929 vma
->ggtt_view
.type
);
2931 } else if (IS_ERR(vma
->ggtt_view
.pages
)) {
2932 ret
= PTR_ERR(vma
->ggtt_view
.pages
);
2933 vma
->ggtt_view
.pages
= NULL
;
2934 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
2935 vma
->ggtt_view
.type
, ret
);
2942 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
2944 * @cache_level: mapping cache level
2945 * @flags: flags like global or local mapping
2947 * DMA addresses are taken from the scatter-gather table of this object (or of
2948 * this VMA in case of non-default GGTT views) and PTE entries set up.
2949 * Note that DMA addresses are also the only part of the SG table we care about.
2951 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
2957 if (WARN_ON(flags
== 0))
2961 if (flags
& PIN_GLOBAL
)
2962 bind_flags
|= GLOBAL_BIND
;
2963 if (flags
& PIN_USER
)
2964 bind_flags
|= LOCAL_BIND
;
2966 if (flags
& PIN_UPDATE
)
2967 bind_flags
|= vma
->bound
;
2969 bind_flags
&= ~vma
->bound
;
2971 if (bind_flags
== 0)
2974 if (vma
->bound
== 0 && vma
->vm
->allocate_va_range
) {
2975 trace_i915_va_alloc(vma
->vm
,
2978 VM_TO_TRACE_NAME(vma
->vm
));
2980 /* XXX: i915_vma_pin() will fix this +- hack */
2982 ret
= vma
->vm
->allocate_va_range(vma
->vm
,
2990 ret
= vma
->vm
->bind_vma(vma
, cache_level
, bind_flags
);
2994 vma
->bound
|= bind_flags
;
3000 * i915_ggtt_view_size - Get the size of a GGTT view.
3001 * @obj: Object the view is of.
3002 * @view: The view in question.
3004 * @return The size of the GGTT view in bytes.
3007 i915_ggtt_view_size(struct drm_i915_gem_object
*obj
,
3008 const struct i915_ggtt_view
*view
)
3010 if (view
->type
== I915_GGTT_VIEW_NORMAL
) {
3011 return obj
->base
.size
;
3012 } else if (view
->type
== I915_GGTT_VIEW_ROTATED
) {
3013 return view
->rotation_info
.size
;
3014 } else if (view
->type
== I915_GGTT_VIEW_PARTIAL
) {
3015 return view
->params
.partial
.size
<< PAGE_SHIFT
;
3017 WARN_ONCE(1, "GGTT view %u not implemented!\n", view
->type
);
3018 return obj
->base
.size
;