2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
27 #include <linux/stop_machine.h>
29 #include <drm/i915_drm.h>
31 #include "i915_vgpu.h"
32 #include "i915_trace.h"
33 #include "intel_drv.h"
36 * DOC: Global GTT views
38 * Background and previous state
40 * Historically objects could exists (be bound) in global GTT space only as
41 * singular instances with a view representing all of the object's backing pages
42 * in a linear fashion. This view will be called a normal view.
44 * To support multiple views of the same object, where the number of mapped
45 * pages is not equal to the backing store, or where the layout of the pages
46 * is not linear, concept of a GGTT view was added.
48 * One example of an alternative view is a stereo display driven by a single
49 * image. In this case we would have a framebuffer looking like this
55 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
56 * rendering. In contrast, fed to the display engine would be an alternative
57 * view which could look something like this:
62 * In this example both the size and layout of pages in the alternative view is
63 * different from the normal view.
65 * Implementation and usage
67 * GGTT views are implemented using VMAs and are distinguished via enum
68 * i915_ggtt_view_type and struct i915_ggtt_view.
70 * A new flavour of core GEM functions which work with GGTT bound objects were
71 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
72 * renaming in large amounts of code. They take the struct i915_ggtt_view
73 * parameter encapsulating all metadata required to implement a view.
75 * As a helper for callers which are only interested in the normal view,
76 * globally const i915_ggtt_view_normal singleton instance exists. All old core
77 * GEM API functions, the ones not taking the view parameter, are operating on,
78 * or with the normal GGTT view.
80 * Code wanting to add or use a new GGTT view needs to:
82 * 1. Add a new enum with a suitable name.
83 * 2. Extend the metadata in the i915_ggtt_view structure if required.
84 * 3. Add support to i915_get_vma_pages().
86 * New views are required to build a scatter-gather table from within the
87 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
88 * exists for the lifetime of an VMA.
90 * Core API is designed to have copy semantics which means that passed in
91 * struct i915_ggtt_view does not need to be persistent (left around after
92 * calling the core API functions).
97 i915_get_ggtt_vma_pages(struct i915_vma
*vma
);
99 const struct i915_ggtt_view i915_ggtt_view_normal
= {
100 .type
= I915_GGTT_VIEW_NORMAL
,
102 const struct i915_ggtt_view i915_ggtt_view_rotated
= {
103 .type
= I915_GGTT_VIEW_ROTATED
,
106 static int sanitize_enable_ppgtt(struct drm_device
*dev
, int enable_ppgtt
)
108 bool has_aliasing_ppgtt
;
110 bool has_full_48bit_ppgtt
;
112 has_aliasing_ppgtt
= INTEL_INFO(dev
)->gen
>= 6;
113 has_full_ppgtt
= INTEL_INFO(dev
)->gen
>= 7;
114 has_full_48bit_ppgtt
= IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9;
116 if (intel_vgpu_active(dev
))
117 has_full_ppgtt
= false; /* emulation is too hard */
120 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
121 * execlists, the sole mechanism available to submit work.
123 if (INTEL_INFO(dev
)->gen
< 9 &&
124 (enable_ppgtt
== 0 || !has_aliasing_ppgtt
))
127 if (enable_ppgtt
== 1)
130 if (enable_ppgtt
== 2 && has_full_ppgtt
)
133 if (enable_ppgtt
== 3 && has_full_48bit_ppgtt
)
136 #ifdef CONFIG_INTEL_IOMMU
137 /* Disable ppgtt on SNB if VT-d is on. */
138 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
) {
139 DRM_INFO("Disabling PPGTT because VT-d is on\n");
144 /* Early VLV doesn't have this */
145 if (IS_VALLEYVIEW(dev
) && dev
->pdev
->revision
< 0xb) {
146 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
150 if (INTEL_INFO(dev
)->gen
>= 8 && i915
.enable_execlists
)
151 return has_full_48bit_ppgtt
? 3 : 2;
153 return has_aliasing_ppgtt
? 1 : 0;
156 static int ppgtt_bind_vma(struct i915_vma
*vma
,
157 enum i915_cache_level cache_level
,
162 /* Currently applicable only to VLV */
164 pte_flags
|= PTE_READ_ONLY
;
166 vma
->vm
->insert_entries(vma
->vm
, vma
->obj
->pages
, vma
->node
.start
,
167 cache_level
, pte_flags
);
172 static void ppgtt_unbind_vma(struct i915_vma
*vma
)
174 vma
->vm
->clear_range(vma
->vm
,
180 static gen8_pte_t
gen8_pte_encode(dma_addr_t addr
,
181 enum i915_cache_level level
,
184 gen8_pte_t pte
= valid
? _PAGE_PRESENT
| _PAGE_RW
: 0;
188 case I915_CACHE_NONE
:
189 pte
|= PPAT_UNCACHED_INDEX
;
192 pte
|= PPAT_DISPLAY_ELLC_INDEX
;
195 pte
|= PPAT_CACHED_INDEX
;
202 static gen8_pde_t
gen8_pde_encode(const dma_addr_t addr
,
203 const enum i915_cache_level level
)
205 gen8_pde_t pde
= _PAGE_PRESENT
| _PAGE_RW
;
207 if (level
!= I915_CACHE_NONE
)
208 pde
|= PPAT_CACHED_PDE_INDEX
;
210 pde
|= PPAT_UNCACHED_INDEX
;
214 #define gen8_pdpe_encode gen8_pde_encode
215 #define gen8_pml4e_encode gen8_pde_encode
217 static gen6_pte_t
snb_pte_encode(dma_addr_t addr
,
218 enum i915_cache_level level
,
219 bool valid
, u32 unused
)
221 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
222 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
225 case I915_CACHE_L3_LLC
:
227 pte
|= GEN6_PTE_CACHE_LLC
;
229 case I915_CACHE_NONE
:
230 pte
|= GEN6_PTE_UNCACHED
;
239 static gen6_pte_t
ivb_pte_encode(dma_addr_t addr
,
240 enum i915_cache_level level
,
241 bool valid
, u32 unused
)
243 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
244 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
247 case I915_CACHE_L3_LLC
:
248 pte
|= GEN7_PTE_CACHE_L3_LLC
;
251 pte
|= GEN6_PTE_CACHE_LLC
;
253 case I915_CACHE_NONE
:
254 pte
|= GEN6_PTE_UNCACHED
;
263 static gen6_pte_t
byt_pte_encode(dma_addr_t addr
,
264 enum i915_cache_level level
,
265 bool valid
, u32 flags
)
267 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
268 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
270 if (!(flags
& PTE_READ_ONLY
))
271 pte
|= BYT_PTE_WRITEABLE
;
273 if (level
!= I915_CACHE_NONE
)
274 pte
|= BYT_PTE_SNOOPED_BY_CPU_CACHES
;
279 static gen6_pte_t
hsw_pte_encode(dma_addr_t addr
,
280 enum i915_cache_level level
,
281 bool valid
, u32 unused
)
283 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
284 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
286 if (level
!= I915_CACHE_NONE
)
287 pte
|= HSW_WB_LLC_AGE3
;
292 static gen6_pte_t
iris_pte_encode(dma_addr_t addr
,
293 enum i915_cache_level level
,
294 bool valid
, u32 unused
)
296 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
297 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
300 case I915_CACHE_NONE
:
303 pte
|= HSW_WT_ELLC_LLC_AGE3
;
306 pte
|= HSW_WB_ELLC_LLC_AGE3
;
313 static int __setup_page_dma(struct drm_device
*dev
,
314 struct i915_page_dma
*p
, gfp_t flags
)
316 struct device
*device
= &dev
->pdev
->dev
;
318 p
->page
= alloc_page(flags
);
322 p
->daddr
= dma_map_page(device
,
323 p
->page
, 0, 4096, PCI_DMA_BIDIRECTIONAL
);
325 if (dma_mapping_error(device
, p
->daddr
)) {
326 __free_page(p
->page
);
333 static int setup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
335 return __setup_page_dma(dev
, p
, GFP_KERNEL
);
338 static void cleanup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
340 if (WARN_ON(!p
->page
))
343 dma_unmap_page(&dev
->pdev
->dev
, p
->daddr
, 4096, PCI_DMA_BIDIRECTIONAL
);
344 __free_page(p
->page
);
345 memset(p
, 0, sizeof(*p
));
348 static void *kmap_page_dma(struct i915_page_dma
*p
)
350 return kmap_atomic(p
->page
);
353 /* We use the flushing unmap only with ppgtt structures:
354 * page directories, page tables and scratch pages.
356 static void kunmap_page_dma(struct drm_device
*dev
, void *vaddr
)
358 /* There are only few exceptions for gen >=6. chv and bxt.
359 * And we are not sure about the latter so play safe for now.
361 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
362 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
364 kunmap_atomic(vaddr
);
367 #define kmap_px(px) kmap_page_dma(px_base(px))
368 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
370 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
371 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
372 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
373 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
375 static void fill_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
,
379 uint64_t * const vaddr
= kmap_page_dma(p
);
381 for (i
= 0; i
< 512; i
++)
384 kunmap_page_dma(dev
, vaddr
);
387 static void fill_page_dma_32(struct drm_device
*dev
, struct i915_page_dma
*p
,
388 const uint32_t val32
)
394 fill_page_dma(dev
, p
, v
);
397 static struct i915_page_scratch
*alloc_scratch_page(struct drm_device
*dev
)
399 struct i915_page_scratch
*sp
;
402 sp
= kzalloc(sizeof(*sp
), GFP_KERNEL
);
404 return ERR_PTR(-ENOMEM
);
406 ret
= __setup_page_dma(dev
, px_base(sp
), GFP_DMA32
| __GFP_ZERO
);
412 set_pages_uc(px_page(sp
), 1);
417 static void free_scratch_page(struct drm_device
*dev
,
418 struct i915_page_scratch
*sp
)
420 set_pages_wb(px_page(sp
), 1);
426 static struct i915_page_table
*alloc_pt(struct drm_device
*dev
)
428 struct i915_page_table
*pt
;
429 const size_t count
= INTEL_INFO(dev
)->gen
>= 8 ?
430 GEN8_PTES
: GEN6_PTES
;
433 pt
= kzalloc(sizeof(*pt
), GFP_KERNEL
);
435 return ERR_PTR(-ENOMEM
);
437 pt
->used_ptes
= kcalloc(BITS_TO_LONGS(count
), sizeof(*pt
->used_ptes
),
443 ret
= setup_px(dev
, pt
);
450 kfree(pt
->used_ptes
);
457 static void free_pt(struct drm_device
*dev
, struct i915_page_table
*pt
)
460 kfree(pt
->used_ptes
);
464 static void gen8_initialize_pt(struct i915_address_space
*vm
,
465 struct i915_page_table
*pt
)
467 gen8_pte_t scratch_pte
;
469 scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
470 I915_CACHE_LLC
, true);
472 fill_px(vm
->dev
, pt
, scratch_pte
);
475 static void gen6_initialize_pt(struct i915_address_space
*vm
,
476 struct i915_page_table
*pt
)
478 gen6_pte_t scratch_pte
;
480 WARN_ON(px_dma(vm
->scratch_page
) == 0);
482 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
483 I915_CACHE_LLC
, true, 0);
485 fill32_px(vm
->dev
, pt
, scratch_pte
);
488 static struct i915_page_directory
*alloc_pd(struct drm_device
*dev
)
490 struct i915_page_directory
*pd
;
493 pd
= kzalloc(sizeof(*pd
), GFP_KERNEL
);
495 return ERR_PTR(-ENOMEM
);
497 pd
->used_pdes
= kcalloc(BITS_TO_LONGS(I915_PDES
),
498 sizeof(*pd
->used_pdes
), GFP_KERNEL
);
502 ret
= setup_px(dev
, pd
);
509 kfree(pd
->used_pdes
);
516 static void free_pd(struct drm_device
*dev
, struct i915_page_directory
*pd
)
520 kfree(pd
->used_pdes
);
525 static void gen8_initialize_pd(struct i915_address_space
*vm
,
526 struct i915_page_directory
*pd
)
528 gen8_pde_t scratch_pde
;
530 scratch_pde
= gen8_pde_encode(px_dma(vm
->scratch_pt
), I915_CACHE_LLC
);
532 fill_px(vm
->dev
, pd
, scratch_pde
);
535 static int __pdp_init(struct drm_device
*dev
,
536 struct i915_page_directory_pointer
*pdp
)
538 size_t pdpes
= I915_PDPES_PER_PDP(dev
);
540 pdp
->used_pdpes
= kcalloc(BITS_TO_LONGS(pdpes
),
541 sizeof(unsigned long),
543 if (!pdp
->used_pdpes
)
546 pdp
->page_directory
= kcalloc(pdpes
, sizeof(*pdp
->page_directory
),
548 if (!pdp
->page_directory
) {
549 kfree(pdp
->used_pdpes
);
550 /* the PDP might be the statically allocated top level. Keep it
551 * as clean as possible */
552 pdp
->used_pdpes
= NULL
;
559 static void __pdp_fini(struct i915_page_directory_pointer
*pdp
)
561 kfree(pdp
->used_pdpes
);
562 kfree(pdp
->page_directory
);
563 pdp
->page_directory
= NULL
;
567 i915_page_directory_pointer
*alloc_pdp(struct drm_device
*dev
)
569 struct i915_page_directory_pointer
*pdp
;
572 WARN_ON(!USES_FULL_48BIT_PPGTT(dev
));
574 pdp
= kzalloc(sizeof(*pdp
), GFP_KERNEL
);
576 return ERR_PTR(-ENOMEM
);
578 ret
= __pdp_init(dev
, pdp
);
582 ret
= setup_px(dev
, pdp
);
596 static void free_pdp(struct drm_device
*dev
,
597 struct i915_page_directory_pointer
*pdp
)
600 if (USES_FULL_48BIT_PPGTT(dev
)) {
601 cleanup_px(dev
, pdp
);
606 static void gen8_initialize_pdp(struct i915_address_space
*vm
,
607 struct i915_page_directory_pointer
*pdp
)
609 gen8_ppgtt_pdpe_t scratch_pdpe
;
611 scratch_pdpe
= gen8_pdpe_encode(px_dma(vm
->scratch_pd
), I915_CACHE_LLC
);
613 fill_px(vm
->dev
, pdp
, scratch_pdpe
);
616 static void gen8_initialize_pml4(struct i915_address_space
*vm
,
617 struct i915_pml4
*pml4
)
619 gen8_ppgtt_pml4e_t scratch_pml4e
;
621 scratch_pml4e
= gen8_pml4e_encode(px_dma(vm
->scratch_pdp
),
624 fill_px(vm
->dev
, pml4
, scratch_pml4e
);
628 gen8_setup_page_directory(struct i915_hw_ppgtt
*ppgtt
,
629 struct i915_page_directory_pointer
*pdp
,
630 struct i915_page_directory
*pd
,
633 gen8_ppgtt_pdpe_t
*page_directorypo
;
635 if (!USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
638 page_directorypo
= kmap_px(pdp
);
639 page_directorypo
[index
] = gen8_pdpe_encode(px_dma(pd
), I915_CACHE_LLC
);
640 kunmap_px(ppgtt
, page_directorypo
);
644 gen8_setup_page_directory_pointer(struct i915_hw_ppgtt
*ppgtt
,
645 struct i915_pml4
*pml4
,
646 struct i915_page_directory_pointer
*pdp
,
649 gen8_ppgtt_pml4e_t
*pagemap
= kmap_px(pml4
);
651 WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
));
652 pagemap
[index
] = gen8_pml4e_encode(px_dma(pdp
), I915_CACHE_LLC
);
653 kunmap_px(ppgtt
, pagemap
);
656 /* Broadwell Page Directory Pointer Descriptors */
657 static int gen8_write_pdp(struct drm_i915_gem_request
*req
,
661 struct intel_engine_cs
*engine
= req
->engine
;
666 ret
= intel_ring_begin(req
, 6);
670 intel_ring_emit(engine
, MI_LOAD_REGISTER_IMM(1));
671 intel_ring_emit_reg(engine
, GEN8_RING_PDP_UDW(engine
, entry
));
672 intel_ring_emit(engine
, upper_32_bits(addr
));
673 intel_ring_emit(engine
, MI_LOAD_REGISTER_IMM(1));
674 intel_ring_emit_reg(engine
, GEN8_RING_PDP_LDW(engine
, entry
));
675 intel_ring_emit(engine
, lower_32_bits(addr
));
676 intel_ring_advance(engine
);
681 static int gen8_legacy_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
682 struct drm_i915_gem_request
*req
)
686 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
687 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
689 ret
= gen8_write_pdp(req
, i
, pd_daddr
);
697 static int gen8_48b_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
698 struct drm_i915_gem_request
*req
)
700 return gen8_write_pdp(req
, 0, px_dma(&ppgtt
->pml4
));
703 static void gen8_ppgtt_clear_pte_range(struct i915_address_space
*vm
,
704 struct i915_page_directory_pointer
*pdp
,
707 gen8_pte_t scratch_pte
)
709 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
710 gen8_pte_t
*pt_vaddr
;
711 unsigned pdpe
= gen8_pdpe_index(start
);
712 unsigned pde
= gen8_pde_index(start
);
713 unsigned pte
= gen8_pte_index(start
);
714 unsigned num_entries
= length
>> PAGE_SHIFT
;
715 unsigned last_pte
, i
;
720 while (num_entries
) {
721 struct i915_page_directory
*pd
;
722 struct i915_page_table
*pt
;
724 if (WARN_ON(!pdp
->page_directory
[pdpe
]))
727 pd
= pdp
->page_directory
[pdpe
];
729 if (WARN_ON(!pd
->page_table
[pde
]))
732 pt
= pd
->page_table
[pde
];
734 if (WARN_ON(!px_page(pt
)))
737 last_pte
= pte
+ num_entries
;
738 if (last_pte
> GEN8_PTES
)
739 last_pte
= GEN8_PTES
;
741 pt_vaddr
= kmap_px(pt
);
743 for (i
= pte
; i
< last_pte
; i
++) {
744 pt_vaddr
[i
] = scratch_pte
;
748 kunmap_px(ppgtt
, pt_vaddr
);
751 if (++pde
== I915_PDES
) {
752 if (++pdpe
== I915_PDPES_PER_PDP(vm
->dev
))
759 static void gen8_ppgtt_clear_range(struct i915_address_space
*vm
,
764 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
765 gen8_pte_t scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
766 I915_CACHE_LLC
, use_scratch
);
768 if (!USES_FULL_48BIT_PPGTT(vm
->dev
)) {
769 gen8_ppgtt_clear_pte_range(vm
, &ppgtt
->pdp
, start
, length
,
773 struct i915_page_directory_pointer
*pdp
;
775 gen8_for_each_pml4e(pdp
, &ppgtt
->pml4
, start
, length
, pml4e
) {
776 gen8_ppgtt_clear_pte_range(vm
, pdp
, start
, length
,
783 gen8_ppgtt_insert_pte_entries(struct i915_address_space
*vm
,
784 struct i915_page_directory_pointer
*pdp
,
785 struct sg_page_iter
*sg_iter
,
787 enum i915_cache_level cache_level
)
789 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
790 gen8_pte_t
*pt_vaddr
;
791 unsigned pdpe
= gen8_pdpe_index(start
);
792 unsigned pde
= gen8_pde_index(start
);
793 unsigned pte
= gen8_pte_index(start
);
797 while (__sg_page_iter_next(sg_iter
)) {
798 if (pt_vaddr
== NULL
) {
799 struct i915_page_directory
*pd
= pdp
->page_directory
[pdpe
];
800 struct i915_page_table
*pt
= pd
->page_table
[pde
];
801 pt_vaddr
= kmap_px(pt
);
805 gen8_pte_encode(sg_page_iter_dma_address(sg_iter
),
807 if (++pte
== GEN8_PTES
) {
808 kunmap_px(ppgtt
, pt_vaddr
);
810 if (++pde
== I915_PDES
) {
811 if (++pdpe
== I915_PDPES_PER_PDP(vm
->dev
))
820 kunmap_px(ppgtt
, pt_vaddr
);
823 static void gen8_ppgtt_insert_entries(struct i915_address_space
*vm
,
824 struct sg_table
*pages
,
826 enum i915_cache_level cache_level
,
829 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
830 struct sg_page_iter sg_iter
;
832 __sg_page_iter_start(&sg_iter
, pages
->sgl
, sg_nents(pages
->sgl
), 0);
834 if (!USES_FULL_48BIT_PPGTT(vm
->dev
)) {
835 gen8_ppgtt_insert_pte_entries(vm
, &ppgtt
->pdp
, &sg_iter
, start
,
838 struct i915_page_directory_pointer
*pdp
;
840 uint64_t length
= (uint64_t)pages
->orig_nents
<< PAGE_SHIFT
;
842 gen8_for_each_pml4e(pdp
, &ppgtt
->pml4
, start
, length
, pml4e
) {
843 gen8_ppgtt_insert_pte_entries(vm
, pdp
, &sg_iter
,
849 static void gen8_free_page_tables(struct drm_device
*dev
,
850 struct i915_page_directory
*pd
)
857 for_each_set_bit(i
, pd
->used_pdes
, I915_PDES
) {
858 if (WARN_ON(!pd
->page_table
[i
]))
861 free_pt(dev
, pd
->page_table
[i
]);
862 pd
->page_table
[i
] = NULL
;
866 static int gen8_init_scratch(struct i915_address_space
*vm
)
868 struct drm_device
*dev
= vm
->dev
;
870 vm
->scratch_page
= alloc_scratch_page(dev
);
871 if (IS_ERR(vm
->scratch_page
))
872 return PTR_ERR(vm
->scratch_page
);
874 vm
->scratch_pt
= alloc_pt(dev
);
875 if (IS_ERR(vm
->scratch_pt
)) {
876 free_scratch_page(dev
, vm
->scratch_page
);
877 return PTR_ERR(vm
->scratch_pt
);
880 vm
->scratch_pd
= alloc_pd(dev
);
881 if (IS_ERR(vm
->scratch_pd
)) {
882 free_pt(dev
, vm
->scratch_pt
);
883 free_scratch_page(dev
, vm
->scratch_page
);
884 return PTR_ERR(vm
->scratch_pd
);
887 if (USES_FULL_48BIT_PPGTT(dev
)) {
888 vm
->scratch_pdp
= alloc_pdp(dev
);
889 if (IS_ERR(vm
->scratch_pdp
)) {
890 free_pd(dev
, vm
->scratch_pd
);
891 free_pt(dev
, vm
->scratch_pt
);
892 free_scratch_page(dev
, vm
->scratch_page
);
893 return PTR_ERR(vm
->scratch_pdp
);
897 gen8_initialize_pt(vm
, vm
->scratch_pt
);
898 gen8_initialize_pd(vm
, vm
->scratch_pd
);
899 if (USES_FULL_48BIT_PPGTT(dev
))
900 gen8_initialize_pdp(vm
, vm
->scratch_pdp
);
905 static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt
*ppgtt
, bool create
)
907 enum vgt_g2v_type msg
;
908 struct drm_i915_private
*dev_priv
= to_i915(ppgtt
->base
.dev
);
911 if (USES_FULL_48BIT_PPGTT(dev_priv
)) {
912 u64 daddr
= px_dma(&ppgtt
->pml4
);
914 I915_WRITE(vgtif_reg(pdp
[0].lo
), lower_32_bits(daddr
));
915 I915_WRITE(vgtif_reg(pdp
[0].hi
), upper_32_bits(daddr
));
917 msg
= (create
? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE
:
918 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY
);
920 for (i
= 0; i
< GEN8_LEGACY_PDPES
; i
++) {
921 u64 daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
923 I915_WRITE(vgtif_reg(pdp
[i
].lo
), lower_32_bits(daddr
));
924 I915_WRITE(vgtif_reg(pdp
[i
].hi
), upper_32_bits(daddr
));
927 msg
= (create
? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE
:
928 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY
);
931 I915_WRITE(vgtif_reg(g2v_notify
), msg
);
936 static void gen8_free_scratch(struct i915_address_space
*vm
)
938 struct drm_device
*dev
= vm
->dev
;
940 if (USES_FULL_48BIT_PPGTT(dev
))
941 free_pdp(dev
, vm
->scratch_pdp
);
942 free_pd(dev
, vm
->scratch_pd
);
943 free_pt(dev
, vm
->scratch_pt
);
944 free_scratch_page(dev
, vm
->scratch_page
);
947 static void gen8_ppgtt_cleanup_3lvl(struct drm_device
*dev
,
948 struct i915_page_directory_pointer
*pdp
)
952 for_each_set_bit(i
, pdp
->used_pdpes
, I915_PDPES_PER_PDP(dev
)) {
953 if (WARN_ON(!pdp
->page_directory
[i
]))
956 gen8_free_page_tables(dev
, pdp
->page_directory
[i
]);
957 free_pd(dev
, pdp
->page_directory
[i
]);
963 static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt
*ppgtt
)
967 for_each_set_bit(i
, ppgtt
->pml4
.used_pml4es
, GEN8_PML4ES_PER_PML4
) {
968 if (WARN_ON(!ppgtt
->pml4
.pdps
[i
]))
971 gen8_ppgtt_cleanup_3lvl(ppgtt
->base
.dev
, ppgtt
->pml4
.pdps
[i
]);
974 cleanup_px(ppgtt
->base
.dev
, &ppgtt
->pml4
);
977 static void gen8_ppgtt_cleanup(struct i915_address_space
*vm
)
979 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
981 if (intel_vgpu_active(vm
->dev
))
982 gen8_ppgtt_notify_vgt(ppgtt
, false);
984 if (!USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
985 gen8_ppgtt_cleanup_3lvl(ppgtt
->base
.dev
, &ppgtt
->pdp
);
987 gen8_ppgtt_cleanup_4lvl(ppgtt
);
989 gen8_free_scratch(vm
);
993 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
994 * @vm: Master vm structure.
995 * @pd: Page directory for this address range.
996 * @start: Starting virtual address to begin allocations.
997 * @length: Size of the allocations.
998 * @new_pts: Bitmap set by function with new allocations. Likely used by the
999 * caller to free on error.
1001 * Allocate the required number of page tables. Extremely similar to
1002 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
1003 * the page directory boundary (instead of the page directory pointer). That
1004 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
1005 * possible, and likely that the caller will need to use multiple calls of this
1006 * function to achieve the appropriate allocation.
1008 * Return: 0 if success; negative error code otherwise.
1010 static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space
*vm
,
1011 struct i915_page_directory
*pd
,
1014 unsigned long *new_pts
)
1016 struct drm_device
*dev
= vm
->dev
;
1017 struct i915_page_table
*pt
;
1020 gen8_for_each_pde(pt
, pd
, start
, length
, pde
) {
1021 /* Don't reallocate page tables */
1022 if (test_bit(pde
, pd
->used_pdes
)) {
1023 /* Scratch is never allocated this way */
1024 WARN_ON(pt
== vm
->scratch_pt
);
1032 gen8_initialize_pt(vm
, pt
);
1033 pd
->page_table
[pde
] = pt
;
1034 __set_bit(pde
, new_pts
);
1035 trace_i915_page_table_entry_alloc(vm
, pde
, start
, GEN8_PDE_SHIFT
);
1041 for_each_set_bit(pde
, new_pts
, I915_PDES
)
1042 free_pt(dev
, pd
->page_table
[pde
]);
1048 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
1049 * @vm: Master vm structure.
1050 * @pdp: Page directory pointer for this address range.
1051 * @start: Starting virtual address to begin allocations.
1052 * @length: Size of the allocations.
1053 * @new_pds: Bitmap set by function with new allocations. Likely used by the
1054 * caller to free on error.
1056 * Allocate the required number of page directories starting at the pde index of
1057 * @start, and ending at the pde index @start + @length. This function will skip
1058 * over already allocated page directories within the range, and only allocate
1059 * new ones, setting the appropriate pointer within the pdp as well as the
1060 * correct position in the bitmap @new_pds.
1062 * The function will only allocate the pages within the range for a give page
1063 * directory pointer. In other words, if @start + @length straddles a virtually
1064 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
1065 * required by the caller, This is not currently possible, and the BUG in the
1066 * code will prevent it.
1068 * Return: 0 if success; negative error code otherwise.
1071 gen8_ppgtt_alloc_page_directories(struct i915_address_space
*vm
,
1072 struct i915_page_directory_pointer
*pdp
,
1075 unsigned long *new_pds
)
1077 struct drm_device
*dev
= vm
->dev
;
1078 struct i915_page_directory
*pd
;
1080 uint32_t pdpes
= I915_PDPES_PER_PDP(dev
);
1082 WARN_ON(!bitmap_empty(new_pds
, pdpes
));
1084 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1085 if (test_bit(pdpe
, pdp
->used_pdpes
))
1092 gen8_initialize_pd(vm
, pd
);
1093 pdp
->page_directory
[pdpe
] = pd
;
1094 __set_bit(pdpe
, new_pds
);
1095 trace_i915_page_directory_entry_alloc(vm
, pdpe
, start
, GEN8_PDPE_SHIFT
);
1101 for_each_set_bit(pdpe
, new_pds
, pdpes
)
1102 free_pd(dev
, pdp
->page_directory
[pdpe
]);
1108 * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range.
1109 * @vm: Master vm structure.
1110 * @pml4: Page map level 4 for this address range.
1111 * @start: Starting virtual address to begin allocations.
1112 * @length: Size of the allocations.
1113 * @new_pdps: Bitmap set by function with new allocations. Likely used by the
1114 * caller to free on error.
1116 * Allocate the required number of page directory pointers. Extremely similar to
1117 * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs().
1118 * The main difference is here we are limited by the pml4 boundary (instead of
1119 * the page directory pointer).
1121 * Return: 0 if success; negative error code otherwise.
1124 gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space
*vm
,
1125 struct i915_pml4
*pml4
,
1128 unsigned long *new_pdps
)
1130 struct drm_device
*dev
= vm
->dev
;
1131 struct i915_page_directory_pointer
*pdp
;
1134 WARN_ON(!bitmap_empty(new_pdps
, GEN8_PML4ES_PER_PML4
));
1136 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, pml4e
) {
1137 if (!test_bit(pml4e
, pml4
->used_pml4es
)) {
1138 pdp
= alloc_pdp(dev
);
1142 gen8_initialize_pdp(vm
, pdp
);
1143 pml4
->pdps
[pml4e
] = pdp
;
1144 __set_bit(pml4e
, new_pdps
);
1145 trace_i915_page_directory_pointer_entry_alloc(vm
,
1155 for_each_set_bit(pml4e
, new_pdps
, GEN8_PML4ES_PER_PML4
)
1156 free_pdp(dev
, pml4
->pdps
[pml4e
]);
1162 free_gen8_temp_bitmaps(unsigned long *new_pds
, unsigned long *new_pts
)
1168 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
1169 * of these are based on the number of PDPEs in the system.
1172 int __must_check
alloc_gen8_temp_bitmaps(unsigned long **new_pds
,
1173 unsigned long **new_pts
,
1179 pds
= kcalloc(BITS_TO_LONGS(pdpes
), sizeof(unsigned long), GFP_TEMPORARY
);
1183 pts
= kcalloc(pdpes
, BITS_TO_LONGS(I915_PDES
) * sizeof(unsigned long),
1194 free_gen8_temp_bitmaps(pds
, pts
);
1198 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
1199 * the page table structures, we mark them dirty so that
1200 * context switching/execlist queuing code takes extra steps
1201 * to ensure that tlbs are flushed.
1203 static void mark_tlbs_dirty(struct i915_hw_ppgtt
*ppgtt
)
1205 ppgtt
->pd_dirty_rings
= INTEL_INFO(ppgtt
->base
.dev
)->ring_mask
;
1208 static int gen8_alloc_va_range_3lvl(struct i915_address_space
*vm
,
1209 struct i915_page_directory_pointer
*pdp
,
1213 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1214 unsigned long *new_page_dirs
, *new_page_tables
;
1215 struct drm_device
*dev
= vm
->dev
;
1216 struct i915_page_directory
*pd
;
1217 const uint64_t orig_start
= start
;
1218 const uint64_t orig_length
= length
;
1220 uint32_t pdpes
= I915_PDPES_PER_PDP(dev
);
1223 /* Wrap is never okay since we can only represent 48b, and we don't
1224 * actually use the other side of the canonical address space.
1226 if (WARN_ON(start
+ length
< start
))
1229 if (WARN_ON(start
+ length
> vm
->total
))
1232 ret
= alloc_gen8_temp_bitmaps(&new_page_dirs
, &new_page_tables
, pdpes
);
1236 /* Do the allocations first so we can easily bail out */
1237 ret
= gen8_ppgtt_alloc_page_directories(vm
, pdp
, start
, length
,
1240 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1244 /* For every page directory referenced, allocate page tables */
1245 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1246 ret
= gen8_ppgtt_alloc_pagetabs(vm
, pd
, start
, length
,
1247 new_page_tables
+ pdpe
* BITS_TO_LONGS(I915_PDES
));
1253 length
= orig_length
;
1255 /* Allocations have completed successfully, so set the bitmaps, and do
1257 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1258 gen8_pde_t
*const page_directory
= kmap_px(pd
);
1259 struct i915_page_table
*pt
;
1260 uint64_t pd_len
= length
;
1261 uint64_t pd_start
= start
;
1264 /* Every pd should be allocated, we just did that above. */
1267 gen8_for_each_pde(pt
, pd
, pd_start
, pd_len
, pde
) {
1268 /* Same reasoning as pd */
1271 WARN_ON(!gen8_pte_count(pd_start
, pd_len
));
1273 /* Set our used ptes within the page table */
1274 bitmap_set(pt
->used_ptes
,
1275 gen8_pte_index(pd_start
),
1276 gen8_pte_count(pd_start
, pd_len
));
1278 /* Our pde is now pointing to the pagetable, pt */
1279 __set_bit(pde
, pd
->used_pdes
);
1281 /* Map the PDE to the page table */
1282 page_directory
[pde
] = gen8_pde_encode(px_dma(pt
),
1284 trace_i915_page_table_entry_map(&ppgtt
->base
, pde
, pt
,
1285 gen8_pte_index(start
),
1286 gen8_pte_count(start
, length
),
1289 /* NB: We haven't yet mapped ptes to pages. At this
1290 * point we're still relying on insert_entries() */
1293 kunmap_px(ppgtt
, page_directory
);
1294 __set_bit(pdpe
, pdp
->used_pdpes
);
1295 gen8_setup_page_directory(ppgtt
, pdp
, pd
, pdpe
);
1298 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1299 mark_tlbs_dirty(ppgtt
);
1306 for_each_set_bit(temp
, new_page_tables
+ pdpe
*
1307 BITS_TO_LONGS(I915_PDES
), I915_PDES
)
1308 free_pt(dev
, pdp
->page_directory
[pdpe
]->page_table
[temp
]);
1311 for_each_set_bit(pdpe
, new_page_dirs
, pdpes
)
1312 free_pd(dev
, pdp
->page_directory
[pdpe
]);
1314 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1315 mark_tlbs_dirty(ppgtt
);
1319 static int gen8_alloc_va_range_4lvl(struct i915_address_space
*vm
,
1320 struct i915_pml4
*pml4
,
1324 DECLARE_BITMAP(new_pdps
, GEN8_PML4ES_PER_PML4
);
1325 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1326 struct i915_page_directory_pointer
*pdp
;
1330 /* Do the pml4 allocations first, so we don't need to track the newly
1331 * allocated tables below the pdp */
1332 bitmap_zero(new_pdps
, GEN8_PML4ES_PER_PML4
);
1334 /* The pagedirectory and pagetable allocations are done in the shared 3
1335 * and 4 level code. Just allocate the pdps.
1337 ret
= gen8_ppgtt_alloc_page_dirpointers(vm
, pml4
, start
, length
,
1342 WARN(bitmap_weight(new_pdps
, GEN8_PML4ES_PER_PML4
) > 2,
1343 "The allocation has spanned more than 512GB. "
1344 "It is highly likely this is incorrect.");
1346 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, pml4e
) {
1349 ret
= gen8_alloc_va_range_3lvl(vm
, pdp
, start
, length
);
1353 gen8_setup_page_directory_pointer(ppgtt
, pml4
, pdp
, pml4e
);
1356 bitmap_or(pml4
->used_pml4es
, new_pdps
, pml4
->used_pml4es
,
1357 GEN8_PML4ES_PER_PML4
);
1362 for_each_set_bit(pml4e
, new_pdps
, GEN8_PML4ES_PER_PML4
)
1363 gen8_ppgtt_cleanup_3lvl(vm
->dev
, pml4
->pdps
[pml4e
]);
1368 static int gen8_alloc_va_range(struct i915_address_space
*vm
,
1369 uint64_t start
, uint64_t length
)
1371 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1373 if (USES_FULL_48BIT_PPGTT(vm
->dev
))
1374 return gen8_alloc_va_range_4lvl(vm
, &ppgtt
->pml4
, start
, length
);
1376 return gen8_alloc_va_range_3lvl(vm
, &ppgtt
->pdp
, start
, length
);
1379 static void gen8_dump_pdp(struct i915_page_directory_pointer
*pdp
,
1380 uint64_t start
, uint64_t length
,
1381 gen8_pte_t scratch_pte
,
1384 struct i915_page_directory
*pd
;
1387 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1388 struct i915_page_table
*pt
;
1389 uint64_t pd_len
= length
;
1390 uint64_t pd_start
= start
;
1393 if (!test_bit(pdpe
, pdp
->used_pdpes
))
1396 seq_printf(m
, "\tPDPE #%d\n", pdpe
);
1397 gen8_for_each_pde(pt
, pd
, pd_start
, pd_len
, pde
) {
1399 gen8_pte_t
*pt_vaddr
;
1401 if (!test_bit(pde
, pd
->used_pdes
))
1404 pt_vaddr
= kmap_px(pt
);
1405 for (pte
= 0; pte
< GEN8_PTES
; pte
+= 4) {
1407 (pdpe
<< GEN8_PDPE_SHIFT
) |
1408 (pde
<< GEN8_PDE_SHIFT
) |
1409 (pte
<< GEN8_PTE_SHIFT
);
1413 for (i
= 0; i
< 4; i
++)
1414 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1419 seq_printf(m
, "\t\t0x%llx [%03d,%03d,%04d]: =", va
, pdpe
, pde
, pte
);
1420 for (i
= 0; i
< 4; i
++) {
1421 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1422 seq_printf(m
, " %llx", pt_vaddr
[pte
+ i
]);
1424 seq_puts(m
, " SCRATCH ");
1428 /* don't use kunmap_px, it could trigger
1429 * an unnecessary flush.
1431 kunmap_atomic(pt_vaddr
);
1436 static void gen8_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
1438 struct i915_address_space
*vm
= &ppgtt
->base
;
1439 uint64_t start
= ppgtt
->base
.start
;
1440 uint64_t length
= ppgtt
->base
.total
;
1441 gen8_pte_t scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
1442 I915_CACHE_LLC
, true);
1444 if (!USES_FULL_48BIT_PPGTT(vm
->dev
)) {
1445 gen8_dump_pdp(&ppgtt
->pdp
, start
, length
, scratch_pte
, m
);
1448 struct i915_pml4
*pml4
= &ppgtt
->pml4
;
1449 struct i915_page_directory_pointer
*pdp
;
1451 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, pml4e
) {
1452 if (!test_bit(pml4e
, pml4
->used_pml4es
))
1455 seq_printf(m
, " PML4E #%llu\n", pml4e
);
1456 gen8_dump_pdp(pdp
, start
, length
, scratch_pte
, m
);
1461 static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt
*ppgtt
)
1463 unsigned long *new_page_dirs
, *new_page_tables
;
1464 uint32_t pdpes
= I915_PDPES_PER_PDP(dev
);
1467 /* We allocate temp bitmap for page tables for no gain
1468 * but as this is for init only, lets keep the things simple
1470 ret
= alloc_gen8_temp_bitmaps(&new_page_dirs
, &new_page_tables
, pdpes
);
1474 /* Allocate for all pdps regardless of how the ppgtt
1477 ret
= gen8_ppgtt_alloc_page_directories(&ppgtt
->base
, &ppgtt
->pdp
,
1481 *ppgtt
->pdp
.used_pdpes
= *new_page_dirs
;
1483 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1489 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1490 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1491 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1495 static int gen8_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
1499 ret
= gen8_init_scratch(&ppgtt
->base
);
1503 ppgtt
->base
.start
= 0;
1504 ppgtt
->base
.cleanup
= gen8_ppgtt_cleanup
;
1505 ppgtt
->base
.allocate_va_range
= gen8_alloc_va_range
;
1506 ppgtt
->base
.insert_entries
= gen8_ppgtt_insert_entries
;
1507 ppgtt
->base
.clear_range
= gen8_ppgtt_clear_range
;
1508 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
1509 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
1510 ppgtt
->debug_dump
= gen8_dump_ppgtt
;
1512 if (USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
1513 ret
= setup_px(ppgtt
->base
.dev
, &ppgtt
->pml4
);
1517 gen8_initialize_pml4(&ppgtt
->base
, &ppgtt
->pml4
);
1519 ppgtt
->base
.total
= 1ULL << 48;
1520 ppgtt
->switch_mm
= gen8_48b_mm_switch
;
1522 ret
= __pdp_init(ppgtt
->base
.dev
, &ppgtt
->pdp
);
1526 ppgtt
->base
.total
= 1ULL << 32;
1527 ppgtt
->switch_mm
= gen8_legacy_mm_switch
;
1528 trace_i915_page_directory_pointer_entry_alloc(&ppgtt
->base
,
1532 if (intel_vgpu_active(ppgtt
->base
.dev
)) {
1533 ret
= gen8_preallocate_top_level_pdps(ppgtt
);
1539 if (intel_vgpu_active(ppgtt
->base
.dev
))
1540 gen8_ppgtt_notify_vgt(ppgtt
, true);
1545 gen8_free_scratch(&ppgtt
->base
);
1549 static void gen6_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
1551 struct i915_address_space
*vm
= &ppgtt
->base
;
1552 struct i915_page_table
*unused
;
1553 gen6_pte_t scratch_pte
;
1555 uint32_t pte
, pde
, temp
;
1556 uint32_t start
= ppgtt
->base
.start
, length
= ppgtt
->base
.total
;
1558 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1559 I915_CACHE_LLC
, true, 0);
1561 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1563 gen6_pte_t
*pt_vaddr
;
1564 const dma_addr_t pt_addr
= px_dma(ppgtt
->pd
.page_table
[pde
]);
1565 pd_entry
= readl(ppgtt
->pd_addr
+ pde
);
1566 expected
= (GEN6_PDE_ADDR_ENCODE(pt_addr
) | GEN6_PDE_VALID
);
1568 if (pd_entry
!= expected
)
1569 seq_printf(m
, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1573 seq_printf(m
, "\tPDE: %x\n", pd_entry
);
1575 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[pde
]);
1577 for (pte
= 0; pte
< GEN6_PTES
; pte
+=4) {
1579 (pde
* PAGE_SIZE
* GEN6_PTES
) +
1583 for (i
= 0; i
< 4; i
++)
1584 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1589 seq_printf(m
, "\t\t0x%lx [%03d,%04d]: =", va
, pde
, pte
);
1590 for (i
= 0; i
< 4; i
++) {
1591 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1592 seq_printf(m
, " %08x", pt_vaddr
[pte
+ i
]);
1594 seq_puts(m
, " SCRATCH ");
1598 kunmap_px(ppgtt
, pt_vaddr
);
1602 /* Write pde (index) from the page directory @pd to the page table @pt */
1603 static void gen6_write_pde(struct i915_page_directory
*pd
,
1604 const int pde
, struct i915_page_table
*pt
)
1606 /* Caller needs to make sure the write completes if necessary */
1607 struct i915_hw_ppgtt
*ppgtt
=
1608 container_of(pd
, struct i915_hw_ppgtt
, pd
);
1611 pd_entry
= GEN6_PDE_ADDR_ENCODE(px_dma(pt
));
1612 pd_entry
|= GEN6_PDE_VALID
;
1614 writel(pd_entry
, ppgtt
->pd_addr
+ pde
);
1617 /* Write all the page tables found in the ppgtt structure to incrementing page
1619 static void gen6_write_page_range(struct drm_i915_private
*dev_priv
,
1620 struct i915_page_directory
*pd
,
1621 uint32_t start
, uint32_t length
)
1623 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1624 struct i915_page_table
*pt
;
1627 gen6_for_each_pde(pt
, pd
, start
, length
, temp
, pde
)
1628 gen6_write_pde(pd
, pde
, pt
);
1630 /* Make sure write is complete before other code can use this page
1631 * table. Also require for WC mapped PTEs */
1635 static uint32_t get_pd_offset(struct i915_hw_ppgtt
*ppgtt
)
1637 BUG_ON(ppgtt
->pd
.base
.ggtt_offset
& 0x3f);
1639 return (ppgtt
->pd
.base
.ggtt_offset
/ 64) << 16;
1642 static int hsw_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1643 struct drm_i915_gem_request
*req
)
1645 struct intel_engine_cs
*engine
= req
->engine
;
1648 /* NB: TLBs must be flushed and invalidated before a switch */
1649 ret
= engine
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1653 ret
= intel_ring_begin(req
, 6);
1657 intel_ring_emit(engine
, MI_LOAD_REGISTER_IMM(2));
1658 intel_ring_emit_reg(engine
, RING_PP_DIR_DCLV(engine
));
1659 intel_ring_emit(engine
, PP_DIR_DCLV_2G
);
1660 intel_ring_emit_reg(engine
, RING_PP_DIR_BASE(engine
));
1661 intel_ring_emit(engine
, get_pd_offset(ppgtt
));
1662 intel_ring_emit(engine
, MI_NOOP
);
1663 intel_ring_advance(engine
);
1668 static int vgpu_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1669 struct drm_i915_gem_request
*req
)
1671 struct intel_engine_cs
*engine
= req
->engine
;
1672 struct drm_i915_private
*dev_priv
= to_i915(ppgtt
->base
.dev
);
1674 I915_WRITE(RING_PP_DIR_DCLV(engine
), PP_DIR_DCLV_2G
);
1675 I915_WRITE(RING_PP_DIR_BASE(engine
), get_pd_offset(ppgtt
));
1679 static int gen7_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1680 struct drm_i915_gem_request
*req
)
1682 struct intel_engine_cs
*engine
= req
->engine
;
1685 /* NB: TLBs must be flushed and invalidated before a switch */
1686 ret
= engine
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1690 ret
= intel_ring_begin(req
, 6);
1694 intel_ring_emit(engine
, MI_LOAD_REGISTER_IMM(2));
1695 intel_ring_emit_reg(engine
, RING_PP_DIR_DCLV(engine
));
1696 intel_ring_emit(engine
, PP_DIR_DCLV_2G
);
1697 intel_ring_emit_reg(engine
, RING_PP_DIR_BASE(engine
));
1698 intel_ring_emit(engine
, get_pd_offset(ppgtt
));
1699 intel_ring_emit(engine
, MI_NOOP
);
1700 intel_ring_advance(engine
);
1702 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1703 if (engine
->id
!= RCS
) {
1704 ret
= engine
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1712 static int gen6_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1713 struct drm_i915_gem_request
*req
)
1715 struct intel_engine_cs
*engine
= req
->engine
;
1716 struct drm_device
*dev
= ppgtt
->base
.dev
;
1717 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1720 I915_WRITE(RING_PP_DIR_DCLV(engine
), PP_DIR_DCLV_2G
);
1721 I915_WRITE(RING_PP_DIR_BASE(engine
), get_pd_offset(ppgtt
));
1723 POSTING_READ(RING_PP_DIR_DCLV(engine
));
1728 static void gen8_ppgtt_enable(struct drm_device
*dev
)
1730 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1731 struct intel_engine_cs
*engine
;
1733 for_each_engine(engine
, dev_priv
) {
1734 u32 four_level
= USES_FULL_48BIT_PPGTT(dev
) ? GEN8_GFX_PPGTT_48B
: 0;
1735 I915_WRITE(RING_MODE_GEN7(engine
),
1736 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
| four_level
));
1740 static void gen7_ppgtt_enable(struct drm_device
*dev
)
1742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1743 struct intel_engine_cs
*engine
;
1744 uint32_t ecochk
, ecobits
;
1746 ecobits
= I915_READ(GAC_ECO_BITS
);
1747 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
1749 ecochk
= I915_READ(GAM_ECOCHK
);
1750 if (IS_HASWELL(dev
)) {
1751 ecochk
|= ECOCHK_PPGTT_WB_HSW
;
1753 ecochk
|= ECOCHK_PPGTT_LLC_IVB
;
1754 ecochk
&= ~ECOCHK_PPGTT_GFDT_IVB
;
1756 I915_WRITE(GAM_ECOCHK
, ecochk
);
1758 for_each_engine(engine
, dev_priv
) {
1759 /* GFX_MODE is per-ring on gen7+ */
1760 I915_WRITE(RING_MODE_GEN7(engine
),
1761 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1765 static void gen6_ppgtt_enable(struct drm_device
*dev
)
1767 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1768 uint32_t ecochk
, gab_ctl
, ecobits
;
1770 ecobits
= I915_READ(GAC_ECO_BITS
);
1771 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_SNB_BIT
|
1772 ECOBITS_PPGTT_CACHE64B
);
1774 gab_ctl
= I915_READ(GAB_CTL
);
1775 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
1777 ecochk
= I915_READ(GAM_ECOCHK
);
1778 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
| ECOCHK_PPGTT_CACHE64B
);
1780 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1783 /* PPGTT support for Sandybdrige/Gen6 and later */
1784 static void gen6_ppgtt_clear_range(struct i915_address_space
*vm
,
1789 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1790 gen6_pte_t
*pt_vaddr
, scratch_pte
;
1791 unsigned first_entry
= start
>> PAGE_SHIFT
;
1792 unsigned num_entries
= length
>> PAGE_SHIFT
;
1793 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1794 unsigned first_pte
= first_entry
% GEN6_PTES
;
1795 unsigned last_pte
, i
;
1797 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1798 I915_CACHE_LLC
, true, 0);
1800 while (num_entries
) {
1801 last_pte
= first_pte
+ num_entries
;
1802 if (last_pte
> GEN6_PTES
)
1803 last_pte
= GEN6_PTES
;
1805 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1807 for (i
= first_pte
; i
< last_pte
; i
++)
1808 pt_vaddr
[i
] = scratch_pte
;
1810 kunmap_px(ppgtt
, pt_vaddr
);
1812 num_entries
-= last_pte
- first_pte
;
1818 static void gen6_ppgtt_insert_entries(struct i915_address_space
*vm
,
1819 struct sg_table
*pages
,
1821 enum i915_cache_level cache_level
, u32 flags
)
1823 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1824 gen6_pte_t
*pt_vaddr
;
1825 unsigned first_entry
= start
>> PAGE_SHIFT
;
1826 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1827 unsigned act_pte
= first_entry
% GEN6_PTES
;
1828 struct sg_page_iter sg_iter
;
1831 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
1832 if (pt_vaddr
== NULL
)
1833 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1836 vm
->pte_encode(sg_page_iter_dma_address(&sg_iter
),
1837 cache_level
, true, flags
);
1839 if (++act_pte
== GEN6_PTES
) {
1840 kunmap_px(ppgtt
, pt_vaddr
);
1847 kunmap_px(ppgtt
, pt_vaddr
);
1850 static int gen6_alloc_va_range(struct i915_address_space
*vm
,
1851 uint64_t start_in
, uint64_t length_in
)
1853 DECLARE_BITMAP(new_page_tables
, I915_PDES
);
1854 struct drm_device
*dev
= vm
->dev
;
1855 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1856 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1857 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1858 struct i915_page_table
*pt
;
1859 uint32_t start
, length
, start_save
, length_save
;
1863 if (WARN_ON(start_in
+ length_in
> ppgtt
->base
.total
))
1866 start
= start_save
= start_in
;
1867 length
= length_save
= length_in
;
1869 bitmap_zero(new_page_tables
, I915_PDES
);
1871 /* The allocation is done in two stages so that we can bail out with
1872 * minimal amount of pain. The first stage finds new page tables that
1873 * need allocation. The second stage marks use ptes within the page
1876 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1877 if (pt
!= vm
->scratch_pt
) {
1878 WARN_ON(bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1882 /* We've already allocated a page table */
1883 WARN_ON(!bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1891 gen6_initialize_pt(vm
, pt
);
1893 ppgtt
->pd
.page_table
[pde
] = pt
;
1894 __set_bit(pde
, new_page_tables
);
1895 trace_i915_page_table_entry_alloc(vm
, pde
, start
, GEN6_PDE_SHIFT
);
1899 length
= length_save
;
1901 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1902 DECLARE_BITMAP(tmp_bitmap
, GEN6_PTES
);
1904 bitmap_zero(tmp_bitmap
, GEN6_PTES
);
1905 bitmap_set(tmp_bitmap
, gen6_pte_index(start
),
1906 gen6_pte_count(start
, length
));
1908 if (__test_and_clear_bit(pde
, new_page_tables
))
1909 gen6_write_pde(&ppgtt
->pd
, pde
, pt
);
1911 trace_i915_page_table_entry_map(vm
, pde
, pt
,
1912 gen6_pte_index(start
),
1913 gen6_pte_count(start
, length
),
1915 bitmap_or(pt
->used_ptes
, tmp_bitmap
, pt
->used_ptes
,
1919 WARN_ON(!bitmap_empty(new_page_tables
, I915_PDES
));
1921 /* Make sure write is complete before other code can use this page
1922 * table. Also require for WC mapped PTEs */
1925 mark_tlbs_dirty(ppgtt
);
1929 for_each_set_bit(pde
, new_page_tables
, I915_PDES
) {
1930 struct i915_page_table
*pt
= ppgtt
->pd
.page_table
[pde
];
1932 ppgtt
->pd
.page_table
[pde
] = vm
->scratch_pt
;
1933 free_pt(vm
->dev
, pt
);
1936 mark_tlbs_dirty(ppgtt
);
1940 static int gen6_init_scratch(struct i915_address_space
*vm
)
1942 struct drm_device
*dev
= vm
->dev
;
1944 vm
->scratch_page
= alloc_scratch_page(dev
);
1945 if (IS_ERR(vm
->scratch_page
))
1946 return PTR_ERR(vm
->scratch_page
);
1948 vm
->scratch_pt
= alloc_pt(dev
);
1949 if (IS_ERR(vm
->scratch_pt
)) {
1950 free_scratch_page(dev
, vm
->scratch_page
);
1951 return PTR_ERR(vm
->scratch_pt
);
1954 gen6_initialize_pt(vm
, vm
->scratch_pt
);
1959 static void gen6_free_scratch(struct i915_address_space
*vm
)
1961 struct drm_device
*dev
= vm
->dev
;
1963 free_pt(dev
, vm
->scratch_pt
);
1964 free_scratch_page(dev
, vm
->scratch_page
);
1967 static void gen6_ppgtt_cleanup(struct i915_address_space
*vm
)
1969 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1970 struct i915_page_table
*pt
;
1973 drm_mm_remove_node(&ppgtt
->node
);
1975 gen6_for_all_pdes(pt
, ppgtt
, pde
) {
1976 if (pt
!= vm
->scratch_pt
)
1977 free_pt(ppgtt
->base
.dev
, pt
);
1980 gen6_free_scratch(vm
);
1983 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt
*ppgtt
)
1985 struct i915_address_space
*vm
= &ppgtt
->base
;
1986 struct drm_device
*dev
= ppgtt
->base
.dev
;
1987 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1988 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1989 bool retried
= false;
1992 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1993 * allocator works in address space sizes, so it's multiplied by page
1994 * size. We allocate at the top of the GTT to avoid fragmentation.
1996 BUG_ON(!drm_mm_initialized(&ggtt
->base
.mm
));
1998 ret
= gen6_init_scratch(vm
);
2003 ret
= drm_mm_insert_node_in_range_generic(&ggtt
->base
.mm
,
2004 &ppgtt
->node
, GEN6_PD_SIZE
,
2006 0, ggtt
->base
.total
,
2008 if (ret
== -ENOSPC
&& !retried
) {
2009 ret
= i915_gem_evict_something(dev
, &ggtt
->base
,
2010 GEN6_PD_SIZE
, GEN6_PD_ALIGN
,
2012 0, ggtt
->base
.total
,
2025 if (ppgtt
->node
.start
< ggtt
->mappable_end
)
2026 DRM_DEBUG("Forced to use aperture for PDEs\n");
2031 gen6_free_scratch(vm
);
2035 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt
*ppgtt
)
2037 return gen6_ppgtt_allocate_page_directories(ppgtt
);
2040 static void gen6_scratch_va_range(struct i915_hw_ppgtt
*ppgtt
,
2041 uint64_t start
, uint64_t length
)
2043 struct i915_page_table
*unused
;
2046 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, temp
, pde
)
2047 ppgtt
->pd
.page_table
[pde
] = ppgtt
->base
.scratch_pt
;
2050 static int gen6_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
2052 struct drm_device
*dev
= ppgtt
->base
.dev
;
2053 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2054 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2057 ppgtt
->base
.pte_encode
= ggtt
->base
.pte_encode
;
2059 ppgtt
->switch_mm
= gen6_mm_switch
;
2060 } else if (IS_HASWELL(dev
)) {
2061 ppgtt
->switch_mm
= hsw_mm_switch
;
2062 } else if (IS_GEN7(dev
)) {
2063 ppgtt
->switch_mm
= gen7_mm_switch
;
2067 if (intel_vgpu_active(dev
))
2068 ppgtt
->switch_mm
= vgpu_mm_switch
;
2070 ret
= gen6_ppgtt_alloc(ppgtt
);
2074 ppgtt
->base
.allocate_va_range
= gen6_alloc_va_range
;
2075 ppgtt
->base
.clear_range
= gen6_ppgtt_clear_range
;
2076 ppgtt
->base
.insert_entries
= gen6_ppgtt_insert_entries
;
2077 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
2078 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
2079 ppgtt
->base
.cleanup
= gen6_ppgtt_cleanup
;
2080 ppgtt
->base
.start
= 0;
2081 ppgtt
->base
.total
= I915_PDES
* GEN6_PTES
* PAGE_SIZE
;
2082 ppgtt
->debug_dump
= gen6_dump_ppgtt
;
2084 ppgtt
->pd
.base
.ggtt_offset
=
2085 ppgtt
->node
.start
/ PAGE_SIZE
* sizeof(gen6_pte_t
);
2087 ppgtt
->pd_addr
= (gen6_pte_t __iomem
*)ggtt
->gsm
+
2088 ppgtt
->pd
.base
.ggtt_offset
/ sizeof(gen6_pte_t
);
2090 gen6_scratch_va_range(ppgtt
, 0, ppgtt
->base
.total
);
2092 gen6_write_page_range(dev_priv
, &ppgtt
->pd
, 0, ppgtt
->base
.total
);
2094 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
2095 ppgtt
->node
.size
>> 20,
2096 ppgtt
->node
.start
/ PAGE_SIZE
);
2098 DRM_DEBUG("Adding PPGTT at offset %x\n",
2099 ppgtt
->pd
.base
.ggtt_offset
<< 10);
2104 static int __hw_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
)
2106 ppgtt
->base
.dev
= dev
;
2108 if (INTEL_INFO(dev
)->gen
< 8)
2109 return gen6_ppgtt_init(ppgtt
);
2111 return gen8_ppgtt_init(ppgtt
);
2114 static void i915_address_space_init(struct i915_address_space
*vm
,
2115 struct drm_i915_private
*dev_priv
)
2117 drm_mm_init(&vm
->mm
, vm
->start
, vm
->total
);
2118 vm
->dev
= dev_priv
->dev
;
2119 INIT_LIST_HEAD(&vm
->active_list
);
2120 INIT_LIST_HEAD(&vm
->inactive_list
);
2121 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
2124 static void gtt_write_workarounds(struct drm_device
*dev
)
2126 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2128 /* This function is for gtt related workarounds. This function is
2129 * called on driver load and after a GPU reset, so you can place
2130 * workarounds here even if they get overwritten by GPU reset.
2132 /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */
2133 if (IS_BROADWELL(dev
))
2134 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW
);
2135 else if (IS_CHERRYVIEW(dev
))
2136 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV
);
2137 else if (IS_SKYLAKE(dev
))
2138 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL
);
2139 else if (IS_BROXTON(dev
))
2140 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT
);
2143 int i915_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
)
2145 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2148 ret
= __hw_ppgtt_init(dev
, ppgtt
);
2150 kref_init(&ppgtt
->ref
);
2151 i915_address_space_init(&ppgtt
->base
, dev_priv
);
2157 int i915_ppgtt_init_hw(struct drm_device
*dev
)
2159 gtt_write_workarounds(dev
);
2161 /* In the case of execlists, PPGTT is enabled by the context descriptor
2162 * and the PDPs are contained within the context itself. We don't
2163 * need to do anything here. */
2164 if (i915
.enable_execlists
)
2167 if (!USES_PPGTT(dev
))
2171 gen6_ppgtt_enable(dev
);
2172 else if (IS_GEN7(dev
))
2173 gen7_ppgtt_enable(dev
);
2174 else if (INTEL_INFO(dev
)->gen
>= 8)
2175 gen8_ppgtt_enable(dev
);
2177 MISSING_CASE(INTEL_INFO(dev
)->gen
);
2182 int i915_ppgtt_init_ring(struct drm_i915_gem_request
*req
)
2184 struct drm_i915_private
*dev_priv
= req
->i915
;
2185 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2187 if (i915
.enable_execlists
)
2193 return ppgtt
->switch_mm(ppgtt
, req
);
2196 struct i915_hw_ppgtt
*
2197 i915_ppgtt_create(struct drm_device
*dev
, struct drm_i915_file_private
*fpriv
)
2199 struct i915_hw_ppgtt
*ppgtt
;
2202 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
2204 return ERR_PTR(-ENOMEM
);
2206 ret
= i915_ppgtt_init(dev
, ppgtt
);
2209 return ERR_PTR(ret
);
2212 ppgtt
->file_priv
= fpriv
;
2214 trace_i915_ppgtt_create(&ppgtt
->base
);
2219 void i915_ppgtt_release(struct kref
*kref
)
2221 struct i915_hw_ppgtt
*ppgtt
=
2222 container_of(kref
, struct i915_hw_ppgtt
, ref
);
2224 trace_i915_ppgtt_release(&ppgtt
->base
);
2226 /* vmas should already be unbound */
2227 WARN_ON(!list_empty(&ppgtt
->base
.active_list
));
2228 WARN_ON(!list_empty(&ppgtt
->base
.inactive_list
));
2230 list_del(&ppgtt
->base
.global_link
);
2231 drm_mm_takedown(&ppgtt
->base
.mm
);
2233 ppgtt
->base
.cleanup(&ppgtt
->base
);
2237 extern int intel_iommu_gfx_mapped
;
2238 /* Certain Gen5 chipsets require require idling the GPU before
2239 * unmapping anything from the GTT when VT-d is enabled.
2241 static bool needs_idle_maps(struct drm_device
*dev
)
2243 #ifdef CONFIG_INTEL_IOMMU
2244 /* Query intel_iommu to see if we need the workaround. Presumably that
2247 if (IS_GEN5(dev
) && IS_MOBILE(dev
) && intel_iommu_gfx_mapped
)
2253 static bool do_idling(struct drm_i915_private
*dev_priv
)
2255 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2256 bool ret
= dev_priv
->mm
.interruptible
;
2258 if (unlikely(ggtt
->do_idle_maps
)) {
2259 dev_priv
->mm
.interruptible
= false;
2260 if (i915_gpu_idle(dev_priv
->dev
)) {
2261 DRM_ERROR("Couldn't idle GPU\n");
2262 /* Wait a bit, in hopes it avoids the hang */
2270 static void undo_idling(struct drm_i915_private
*dev_priv
, bool interruptible
)
2272 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2274 if (unlikely(ggtt
->do_idle_maps
))
2275 dev_priv
->mm
.interruptible
= interruptible
;
2278 void i915_check_and_clear_faults(struct drm_device
*dev
)
2280 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2281 struct intel_engine_cs
*engine
;
2283 if (INTEL_INFO(dev
)->gen
< 6)
2286 for_each_engine(engine
, dev_priv
) {
2288 fault_reg
= I915_READ(RING_FAULT_REG(engine
));
2289 if (fault_reg
& RING_FAULT_VALID
) {
2290 DRM_DEBUG_DRIVER("Unexpected fault\n"
2292 "\tAddress space: %s\n"
2295 fault_reg
& PAGE_MASK
,
2296 fault_reg
& RING_FAULT_GTTSEL_MASK
? "GGTT" : "PPGTT",
2297 RING_FAULT_SRCID(fault_reg
),
2298 RING_FAULT_FAULT_TYPE(fault_reg
));
2299 I915_WRITE(RING_FAULT_REG(engine
),
2300 fault_reg
& ~RING_FAULT_VALID
);
2303 POSTING_READ(RING_FAULT_REG(&dev_priv
->engine
[RCS
]));
2306 static void i915_ggtt_flush(struct drm_i915_private
*dev_priv
)
2308 if (INTEL_INFO(dev_priv
)->gen
< 6) {
2309 intel_gtt_chipset_flush();
2311 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2312 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2316 void i915_gem_suspend_gtt_mappings(struct drm_device
*dev
)
2318 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2319 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2321 /* Don't bother messing with faults pre GEN6 as we have little
2322 * documentation supporting that it's a good idea.
2324 if (INTEL_INFO(dev
)->gen
< 6)
2327 i915_check_and_clear_faults(dev
);
2329 ggtt
->base
.clear_range(&ggtt
->base
, ggtt
->base
.start
, ggtt
->base
.total
,
2332 i915_ggtt_flush(dev_priv
);
2335 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
)
2337 if (!dma_map_sg(&obj
->base
.dev
->pdev
->dev
,
2338 obj
->pages
->sgl
, obj
->pages
->nents
,
2339 PCI_DMA_BIDIRECTIONAL
))
2345 static void gen8_set_pte(void __iomem
*addr
, gen8_pte_t pte
)
2350 iowrite32((u32
)pte
, addr
);
2351 iowrite32(pte
>> 32, addr
+ 4);
2355 static void gen8_ggtt_insert_entries(struct i915_address_space
*vm
,
2356 struct sg_table
*st
,
2358 enum i915_cache_level level
, u32 unused
)
2360 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2361 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2362 unsigned first_entry
= start
>> PAGE_SHIFT
;
2363 gen8_pte_t __iomem
*gtt_entries
=
2364 (gen8_pte_t __iomem
*)ggtt
->gsm
+ first_entry
;
2366 struct sg_page_iter sg_iter
;
2367 dma_addr_t addr
= 0; /* shut up gcc */
2370 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2372 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
2373 addr
= sg_dma_address(sg_iter
.sg
) +
2374 (sg_iter
.sg_pgoffset
<< PAGE_SHIFT
);
2375 gen8_set_pte(>t_entries
[i
],
2376 gen8_pte_encode(addr
, level
, true));
2381 * XXX: This serves as a posting read to make sure that the PTE has
2382 * actually been updated. There is some concern that even though
2383 * registers and PTEs are within the same BAR that they are potentially
2384 * of NUMA access patterns. Therefore, even with the way we assume
2385 * hardware should work, we must keep this posting read for paranoia.
2388 WARN_ON(readq(>t_entries
[i
-1])
2389 != gen8_pte_encode(addr
, level
, true));
2391 /* This next bit makes the above posting read even more important. We
2392 * want to flush the TLBs only after we're certain all the PTE updates
2395 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2396 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2398 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2401 struct insert_entries
{
2402 struct i915_address_space
*vm
;
2403 struct sg_table
*st
;
2405 enum i915_cache_level level
;
2409 static int gen8_ggtt_insert_entries__cb(void *_arg
)
2411 struct insert_entries
*arg
= _arg
;
2412 gen8_ggtt_insert_entries(arg
->vm
, arg
->st
,
2413 arg
->start
, arg
->level
, arg
->flags
);
2417 static void gen8_ggtt_insert_entries__BKL(struct i915_address_space
*vm
,
2418 struct sg_table
*st
,
2420 enum i915_cache_level level
,
2423 struct insert_entries arg
= { vm
, st
, start
, level
, flags
};
2424 stop_machine(gen8_ggtt_insert_entries__cb
, &arg
, NULL
);
2428 * Binds an object into the global gtt with the specified cache level. The object
2429 * will be accessible to the GPU via commands whose operands reference offsets
2430 * within the global GTT as well as accessible by the GPU through the GMADR
2431 * mapped BAR (dev_priv->mm.gtt->gtt).
2433 static void gen6_ggtt_insert_entries(struct i915_address_space
*vm
,
2434 struct sg_table
*st
,
2436 enum i915_cache_level level
, u32 flags
)
2438 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2439 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2440 unsigned first_entry
= start
>> PAGE_SHIFT
;
2441 gen6_pte_t __iomem
*gtt_entries
=
2442 (gen6_pte_t __iomem
*)ggtt
->gsm
+ first_entry
;
2444 struct sg_page_iter sg_iter
;
2445 dma_addr_t addr
= 0;
2448 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2450 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
2451 addr
= sg_page_iter_dma_address(&sg_iter
);
2452 iowrite32(vm
->pte_encode(addr
, level
, true, flags
), >t_entries
[i
]);
2456 /* XXX: This serves as a posting read to make sure that the PTE has
2457 * actually been updated. There is some concern that even though
2458 * registers and PTEs are within the same BAR that they are potentially
2459 * of NUMA access patterns. Therefore, even with the way we assume
2460 * hardware should work, we must keep this posting read for paranoia.
2463 unsigned long gtt
= readl(>t_entries
[i
-1]);
2464 WARN_ON(gtt
!= vm
->pte_encode(addr
, level
, true, flags
));
2467 /* This next bit makes the above posting read even more important. We
2468 * want to flush the TLBs only after we're certain all the PTE updates
2471 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2472 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2474 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2477 static void gen8_ggtt_clear_range(struct i915_address_space
*vm
,
2482 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2483 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2484 unsigned first_entry
= start
>> PAGE_SHIFT
;
2485 unsigned num_entries
= length
>> PAGE_SHIFT
;
2486 gen8_pte_t scratch_pte
, __iomem
*gtt_base
=
2487 (gen8_pte_t __iomem
*)ggtt
->gsm
+ first_entry
;
2488 const int max_entries
= ggtt_total_entries(ggtt
) - first_entry
;
2492 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2494 if (WARN(num_entries
> max_entries
,
2495 "First entry = %d; Num entries = %d (max=%d)\n",
2496 first_entry
, num_entries
, max_entries
))
2497 num_entries
= max_entries
;
2499 scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
2502 for (i
= 0; i
< num_entries
; i
++)
2503 gen8_set_pte(>t_base
[i
], scratch_pte
);
2506 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2509 static void gen6_ggtt_clear_range(struct i915_address_space
*vm
,
2514 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2515 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2516 unsigned first_entry
= start
>> PAGE_SHIFT
;
2517 unsigned num_entries
= length
>> PAGE_SHIFT
;
2518 gen6_pte_t scratch_pte
, __iomem
*gtt_base
=
2519 (gen6_pte_t __iomem
*)ggtt
->gsm
+ first_entry
;
2520 const int max_entries
= ggtt_total_entries(ggtt
) - first_entry
;
2524 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2526 if (WARN(num_entries
> max_entries
,
2527 "First entry = %d; Num entries = %d (max=%d)\n",
2528 first_entry
, num_entries
, max_entries
))
2529 num_entries
= max_entries
;
2531 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
2532 I915_CACHE_LLC
, use_scratch
, 0);
2534 for (i
= 0; i
< num_entries
; i
++)
2535 iowrite32(scratch_pte
, >t_base
[i
]);
2538 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2541 static void i915_ggtt_insert_entries(struct i915_address_space
*vm
,
2542 struct sg_table
*pages
,
2544 enum i915_cache_level cache_level
, u32 unused
)
2546 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
2547 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
2548 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
2551 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2553 intel_gtt_insert_sg_entries(pages
, start
>> PAGE_SHIFT
, flags
);
2555 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2559 static void i915_ggtt_clear_range(struct i915_address_space
*vm
,
2564 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
2565 unsigned first_entry
= start
>> PAGE_SHIFT
;
2566 unsigned num_entries
= length
>> PAGE_SHIFT
;
2569 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2571 intel_gtt_clear_range(first_entry
, num_entries
);
2573 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2576 static int ggtt_bind_vma(struct i915_vma
*vma
,
2577 enum i915_cache_level cache_level
,
2580 struct drm_i915_gem_object
*obj
= vma
->obj
;
2584 ret
= i915_get_ggtt_vma_pages(vma
);
2588 /* Currently applicable only to VLV */
2590 pte_flags
|= PTE_READ_ONLY
;
2592 vma
->vm
->insert_entries(vma
->vm
, vma
->ggtt_view
.pages
,
2594 cache_level
, pte_flags
);
2597 * Without aliasing PPGTT there's no difference between
2598 * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
2599 * upgrade to both bound if we bind either to avoid double-binding.
2601 vma
->bound
|= GLOBAL_BIND
| LOCAL_BIND
;
2606 static int aliasing_gtt_bind_vma(struct i915_vma
*vma
,
2607 enum i915_cache_level cache_level
,
2613 ret
= i915_get_ggtt_vma_pages(vma
);
2617 /* Currently applicable only to VLV */
2619 if (vma
->obj
->gt_ro
)
2620 pte_flags
|= PTE_READ_ONLY
;
2623 if (flags
& GLOBAL_BIND
) {
2624 vma
->vm
->insert_entries(vma
->vm
,
2625 vma
->ggtt_view
.pages
,
2627 cache_level
, pte_flags
);
2630 if (flags
& LOCAL_BIND
) {
2631 struct i915_hw_ppgtt
*appgtt
=
2632 to_i915(vma
->vm
->dev
)->mm
.aliasing_ppgtt
;
2633 appgtt
->base
.insert_entries(&appgtt
->base
,
2634 vma
->ggtt_view
.pages
,
2636 cache_level
, pte_flags
);
2642 static void ggtt_unbind_vma(struct i915_vma
*vma
)
2644 struct drm_device
*dev
= vma
->vm
->dev
;
2645 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2646 struct drm_i915_gem_object
*obj
= vma
->obj
;
2647 const uint64_t size
= min_t(uint64_t,
2651 if (vma
->bound
& GLOBAL_BIND
) {
2652 vma
->vm
->clear_range(vma
->vm
,
2658 if (dev_priv
->mm
.aliasing_ppgtt
&& vma
->bound
& LOCAL_BIND
) {
2659 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2661 appgtt
->base
.clear_range(&appgtt
->base
,
2668 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
)
2670 struct drm_device
*dev
= obj
->base
.dev
;
2671 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2674 interruptible
= do_idling(dev_priv
);
2676 dma_unmap_sg(&dev
->pdev
->dev
, obj
->pages
->sgl
, obj
->pages
->nents
,
2677 PCI_DMA_BIDIRECTIONAL
);
2679 undo_idling(dev_priv
, interruptible
);
2682 static void i915_gtt_color_adjust(struct drm_mm_node
*node
,
2683 unsigned long color
,
2687 if (node
->color
!= color
)
2690 if (!list_empty(&node
->node_list
)) {
2691 node
= list_entry(node
->node_list
.next
,
2694 if (node
->allocated
&& node
->color
!= color
)
2699 static int i915_gem_setup_global_gtt(struct drm_device
*dev
,
2704 /* Let GEM Manage all of the aperture.
2706 * However, leave one page at the end still bound to the scratch page.
2707 * There are a number of places where the hardware apparently prefetches
2708 * past the end of the object, and we've seen multiple hangs with the
2709 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2710 * aperture. One page should be enough to keep any prefetching inside
2713 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2714 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2715 struct drm_mm_node
*entry
;
2716 struct drm_i915_gem_object
*obj
;
2717 unsigned long hole_start
, hole_end
;
2720 BUG_ON(mappable_end
> end
);
2722 ggtt
->base
.start
= start
;
2724 /* Subtract the guard page before address space initialization to
2725 * shrink the range used by drm_mm */
2726 ggtt
->base
.total
= end
- start
- PAGE_SIZE
;
2727 i915_address_space_init(&ggtt
->base
, dev_priv
);
2728 ggtt
->base
.total
+= PAGE_SIZE
;
2730 if (intel_vgpu_active(dev
)) {
2731 ret
= intel_vgt_balloon(dev
);
2737 ggtt
->base
.mm
.color_adjust
= i915_gtt_color_adjust
;
2739 /* Mark any preallocated objects as occupied */
2740 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
2741 struct i915_vma
*vma
= i915_gem_obj_to_vma(obj
, &ggtt
->base
);
2743 DRM_DEBUG_KMS("reserving preallocated space: %llx + %zx\n",
2744 i915_gem_obj_ggtt_offset(obj
), obj
->base
.size
);
2746 WARN_ON(i915_gem_obj_ggtt_bound(obj
));
2747 ret
= drm_mm_reserve_node(&ggtt
->base
.mm
, &vma
->node
);
2749 DRM_DEBUG_KMS("Reservation failed: %i\n", ret
);
2752 vma
->bound
|= GLOBAL_BIND
;
2753 __i915_vma_set_map_and_fenceable(vma
);
2754 list_add_tail(&vma
->vm_link
, &ggtt
->base
.inactive_list
);
2757 /* Clear any non-preallocated blocks */
2758 drm_mm_for_each_hole(entry
, &ggtt
->base
.mm
, hole_start
, hole_end
) {
2759 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2760 hole_start
, hole_end
);
2761 ggtt
->base
.clear_range(&ggtt
->base
, hole_start
,
2762 hole_end
- hole_start
, true);
2765 /* And finally clear the reserved guard page */
2766 ggtt
->base
.clear_range(&ggtt
->base
, end
- PAGE_SIZE
, PAGE_SIZE
, true);
2768 if (USES_PPGTT(dev
) && !USES_FULL_PPGTT(dev
)) {
2769 struct i915_hw_ppgtt
*ppgtt
;
2771 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
2775 ret
= __hw_ppgtt_init(dev
, ppgtt
);
2777 ppgtt
->base
.cleanup(&ppgtt
->base
);
2782 if (ppgtt
->base
.allocate_va_range
)
2783 ret
= ppgtt
->base
.allocate_va_range(&ppgtt
->base
, 0,
2786 ppgtt
->base
.cleanup(&ppgtt
->base
);
2791 ppgtt
->base
.clear_range(&ppgtt
->base
,
2796 dev_priv
->mm
.aliasing_ppgtt
= ppgtt
;
2797 WARN_ON(ggtt
->base
.bind_vma
!= ggtt_bind_vma
);
2798 ggtt
->base
.bind_vma
= aliasing_gtt_bind_vma
;
2805 * i915_gem_init_ggtt - Initialize GEM for Global GTT
2808 void i915_gem_init_ggtt(struct drm_device
*dev
)
2810 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2811 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2813 i915_gem_setup_global_gtt(dev
, 0, ggtt
->mappable_end
, ggtt
->base
.total
);
2817 * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
2820 void i915_ggtt_cleanup_hw(struct drm_device
*dev
)
2822 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2823 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2825 if (dev_priv
->mm
.aliasing_ppgtt
) {
2826 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2828 ppgtt
->base
.cleanup(&ppgtt
->base
);
2831 i915_gem_cleanup_stolen(dev
);
2833 if (drm_mm_initialized(&ggtt
->base
.mm
)) {
2834 if (intel_vgpu_active(dev
))
2835 intel_vgt_deballoon();
2837 drm_mm_takedown(&ggtt
->base
.mm
);
2838 list_del(&ggtt
->base
.global_link
);
2841 ggtt
->base
.cleanup(&ggtt
->base
);
2844 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
2846 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
2847 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
2848 return snb_gmch_ctl
<< 20;
2851 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl
)
2853 bdw_gmch_ctl
>>= BDW_GMCH_GGMS_SHIFT
;
2854 bdw_gmch_ctl
&= BDW_GMCH_GGMS_MASK
;
2856 bdw_gmch_ctl
= 1 << bdw_gmch_ctl
;
2858 #ifdef CONFIG_X86_32
2859 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2860 if (bdw_gmch_ctl
> 4)
2864 return bdw_gmch_ctl
<< 20;
2867 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl
)
2869 gmch_ctrl
>>= SNB_GMCH_GGMS_SHIFT
;
2870 gmch_ctrl
&= SNB_GMCH_GGMS_MASK
;
2873 return 1 << (20 + gmch_ctrl
);
2878 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl
)
2880 snb_gmch_ctl
>>= SNB_GMCH_GMS_SHIFT
;
2881 snb_gmch_ctl
&= SNB_GMCH_GMS_MASK
;
2882 return snb_gmch_ctl
<< 25; /* 32 MB units */
2885 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl
)
2887 bdw_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2888 bdw_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2889 return bdw_gmch_ctl
<< 25; /* 32 MB units */
2892 static size_t chv_get_stolen_size(u16 gmch_ctrl
)
2894 gmch_ctrl
>>= SNB_GMCH_GMS_SHIFT
;
2895 gmch_ctrl
&= SNB_GMCH_GMS_MASK
;
2898 * 0x0 to 0x10: 32MB increments starting at 0MB
2899 * 0x11 to 0x16: 4MB increments starting at 8MB
2900 * 0x17 to 0x1d: 4MB increments start at 36MB
2902 if (gmch_ctrl
< 0x11)
2903 return gmch_ctrl
<< 25;
2904 else if (gmch_ctrl
< 0x17)
2905 return (gmch_ctrl
- 0x11 + 2) << 22;
2907 return (gmch_ctrl
- 0x17 + 9) << 22;
2910 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl
)
2912 gen9_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2913 gen9_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2915 if (gen9_gmch_ctl
< 0xf0)
2916 return gen9_gmch_ctl
<< 25; /* 32 MB units */
2918 /* 4MB increments starting at 0xf0 for 4MB */
2919 return (gen9_gmch_ctl
- 0xf0 + 1) << 22;
2922 static int ggtt_probe_common(struct drm_device
*dev
,
2925 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2926 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2927 struct i915_page_scratch
*scratch_page
;
2928 phys_addr_t ggtt_phys_addr
;
2930 /* For Modern GENs the PTEs and register space are split in the BAR */
2931 ggtt_phys_addr
= pci_resource_start(dev
->pdev
, 0) +
2932 (pci_resource_len(dev
->pdev
, 0) / 2);
2935 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2936 * dropped. For WC mappings in general we have 64 byte burst writes
2937 * when the WC buffer is flushed, so we can't use it, but have to
2938 * resort to an uncached mapping. The WC issue is easily caught by the
2939 * readback check when writing GTT PTE entries.
2941 if (IS_BROXTON(dev
))
2942 ggtt
->gsm
= ioremap_nocache(ggtt_phys_addr
, gtt_size
);
2944 ggtt
->gsm
= ioremap_wc(ggtt_phys_addr
, gtt_size
);
2946 DRM_ERROR("Failed to map the gtt page table\n");
2950 scratch_page
= alloc_scratch_page(dev
);
2951 if (IS_ERR(scratch_page
)) {
2952 DRM_ERROR("Scratch setup failed\n");
2953 /* iounmap will also get called at remove, but meh */
2955 return PTR_ERR(scratch_page
);
2958 ggtt
->base
.scratch_page
= scratch_page
;
2963 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2964 * bits. When using advanced contexts each context stores its own PAT, but
2965 * writing this data shouldn't be harmful even in those cases. */
2966 static void bdw_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2970 pat
= GEN8_PPAT(0, GEN8_PPAT_WB
| GEN8_PPAT_LLC
) | /* for normal objects, no eLLC */
2971 GEN8_PPAT(1, GEN8_PPAT_WC
| GEN8_PPAT_LLCELLC
) | /* for something pointing to ptes? */
2972 GEN8_PPAT(2, GEN8_PPAT_WT
| GEN8_PPAT_LLCELLC
) | /* for scanout with eLLC */
2973 GEN8_PPAT(3, GEN8_PPAT_UC
) | /* Uncached objects, mostly for scanout */
2974 GEN8_PPAT(4, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(0)) |
2975 GEN8_PPAT(5, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(1)) |
2976 GEN8_PPAT(6, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(2)) |
2977 GEN8_PPAT(7, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(3));
2979 if (!USES_PPGTT(dev_priv
))
2980 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2981 * so RTL will always use the value corresponding to
2983 * So let's disable cache for GGTT to avoid screen corruptions.
2984 * MOCS still can be used though.
2985 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2986 * before this patch, i.e. the same uncached + snooping access
2987 * like on gen6/7 seems to be in effect.
2988 * - So this just fixes blitter/render access. Again it looks
2989 * like it's not just uncached access, but uncached + snooping.
2990 * So we can still hold onto all our assumptions wrt cpu
2991 * clflushing on LLC machines.
2993 pat
= GEN8_PPAT(0, GEN8_PPAT_UC
);
2995 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2996 * write would work. */
2997 I915_WRITE(GEN8_PRIVATE_PAT_LO
, pat
);
2998 I915_WRITE(GEN8_PRIVATE_PAT_HI
, pat
>> 32);
3001 static void chv_setup_private_ppat(struct drm_i915_private
*dev_priv
)
3006 * Map WB on BDW to snooped on CHV.
3008 * Only the snoop bit has meaning for CHV, the rest is
3011 * The hardware will never snoop for certain types of accesses:
3012 * - CPU GTT (GMADR->GGTT->no snoop->memory)
3013 * - PPGTT page tables
3014 * - some other special cycles
3016 * As with BDW, we also need to consider the following for GT accesses:
3017 * "For GGTT, there is NO pat_sel[2:0] from the entry,
3018 * so RTL will always use the value corresponding to
3020 * Which means we must set the snoop bit in PAT entry 0
3021 * in order to keep the global status page working.
3023 pat
= GEN8_PPAT(0, CHV_PPAT_SNOOP
) |
3027 GEN8_PPAT(4, CHV_PPAT_SNOOP
) |
3028 GEN8_PPAT(5, CHV_PPAT_SNOOP
) |
3029 GEN8_PPAT(6, CHV_PPAT_SNOOP
) |
3030 GEN8_PPAT(7, CHV_PPAT_SNOOP
);
3032 I915_WRITE(GEN8_PRIVATE_PAT_LO
, pat
);
3033 I915_WRITE(GEN8_PRIVATE_PAT_HI
, pat
>> 32);
3036 static int gen8_gmch_probe(struct i915_ggtt
*ggtt
)
3038 struct drm_device
*dev
= ggtt
->base
.dev
;
3039 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3043 /* TODO: We're not aware of mappable constraints on gen8 yet */
3044 ggtt
->mappable_base
= pci_resource_start(dev
->pdev
, 2);
3045 ggtt
->mappable_end
= pci_resource_len(dev
->pdev
, 2);
3047 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(39)))
3048 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(39));
3050 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
3052 if (INTEL_INFO(dev
)->gen
>= 9) {
3053 ggtt
->stolen_size
= gen9_get_stolen_size(snb_gmch_ctl
);
3054 ggtt
->size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
3055 } else if (IS_CHERRYVIEW(dev
)) {
3056 ggtt
->stolen_size
= chv_get_stolen_size(snb_gmch_ctl
);
3057 ggtt
->size
= chv_get_total_gtt_size(snb_gmch_ctl
);
3059 ggtt
->stolen_size
= gen8_get_stolen_size(snb_gmch_ctl
);
3060 ggtt
->size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
3063 ggtt
->base
.total
= (ggtt
->size
/ sizeof(gen8_pte_t
)) << PAGE_SHIFT
;
3065 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
3066 chv_setup_private_ppat(dev_priv
);
3068 bdw_setup_private_ppat(dev_priv
);
3070 ret
= ggtt_probe_common(dev
, ggtt
->size
);
3072 ggtt
->base
.clear_range
= gen8_ggtt_clear_range
;
3073 if (IS_CHERRYVIEW(dev_priv
))
3074 ggtt
->base
.insert_entries
= gen8_ggtt_insert_entries__BKL
;
3076 ggtt
->base
.insert_entries
= gen8_ggtt_insert_entries
;
3077 ggtt
->base
.bind_vma
= ggtt_bind_vma
;
3078 ggtt
->base
.unbind_vma
= ggtt_unbind_vma
;
3083 static int gen6_gmch_probe(struct i915_ggtt
*ggtt
)
3085 struct drm_device
*dev
= ggtt
->base
.dev
;
3089 ggtt
->mappable_base
= pci_resource_start(dev
->pdev
, 2);
3090 ggtt
->mappable_end
= pci_resource_len(dev
->pdev
, 2);
3092 /* 64/512MB is the current min/max we actually know of, but this is just
3093 * a coarse sanity check.
3095 if ((ggtt
->mappable_end
< (64<<20) || (ggtt
->mappable_end
> (512<<20)))) {
3096 DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt
->mappable_end
);
3100 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(40)))
3101 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(40));
3102 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
3104 ggtt
->stolen_size
= gen6_get_stolen_size(snb_gmch_ctl
);
3105 ggtt
->size
= gen6_get_total_gtt_size(snb_gmch_ctl
);
3106 ggtt
->base
.total
= (ggtt
->size
/ sizeof(gen6_pte_t
)) << PAGE_SHIFT
;
3108 ret
= ggtt_probe_common(dev
, ggtt
->size
);
3110 ggtt
->base
.clear_range
= gen6_ggtt_clear_range
;
3111 ggtt
->base
.insert_entries
= gen6_ggtt_insert_entries
;
3112 ggtt
->base
.bind_vma
= ggtt_bind_vma
;
3113 ggtt
->base
.unbind_vma
= ggtt_unbind_vma
;
3118 static void gen6_gmch_remove(struct i915_address_space
*vm
)
3120 struct i915_ggtt
*ggtt
= container_of(vm
, struct i915_ggtt
, base
);
3123 free_scratch_page(vm
->dev
, vm
->scratch_page
);
3126 static int i915_gmch_probe(struct i915_ggtt
*ggtt
)
3128 struct drm_device
*dev
= ggtt
->base
.dev
;
3129 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3132 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev_priv
->dev
->pdev
, NULL
);
3134 DRM_ERROR("failed to set up gmch\n");
3138 intel_gtt_get(&ggtt
->base
.total
, &ggtt
->stolen_size
,
3139 &ggtt
->mappable_base
, &ggtt
->mappable_end
);
3141 ggtt
->do_idle_maps
= needs_idle_maps(dev_priv
->dev
);
3142 ggtt
->base
.insert_entries
= i915_ggtt_insert_entries
;
3143 ggtt
->base
.clear_range
= i915_ggtt_clear_range
;
3144 ggtt
->base
.bind_vma
= ggtt_bind_vma
;
3145 ggtt
->base
.unbind_vma
= ggtt_unbind_vma
;
3147 if (unlikely(ggtt
->do_idle_maps
))
3148 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
3153 static void i915_gmch_remove(struct i915_address_space
*vm
)
3155 intel_gmch_remove();
3159 * i915_ggtt_init_hw - Initialize GGTT hardware
3162 int i915_ggtt_init_hw(struct drm_device
*dev
)
3164 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3165 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3168 if (INTEL_INFO(dev
)->gen
<= 5) {
3169 ggtt
->probe
= i915_gmch_probe
;
3170 ggtt
->base
.cleanup
= i915_gmch_remove
;
3171 } else if (INTEL_INFO(dev
)->gen
< 8) {
3172 ggtt
->probe
= gen6_gmch_probe
;
3173 ggtt
->base
.cleanup
= gen6_gmch_remove
;
3176 ggtt
->base
.pte_encode
= iris_pte_encode
;
3177 else if (IS_HASWELL(dev
))
3178 ggtt
->base
.pte_encode
= hsw_pte_encode
;
3179 else if (IS_VALLEYVIEW(dev
))
3180 ggtt
->base
.pte_encode
= byt_pte_encode
;
3181 else if (INTEL_INFO(dev
)->gen
>= 7)
3182 ggtt
->base
.pte_encode
= ivb_pte_encode
;
3184 ggtt
->base
.pte_encode
= snb_pte_encode
;
3186 ggtt
->probe
= gen8_gmch_probe
;
3187 ggtt
->base
.cleanup
= gen6_gmch_remove
;
3190 ggtt
->base
.dev
= dev
;
3191 ggtt
->base
.is_ggtt
= true;
3193 ret
= ggtt
->probe(ggtt
);
3197 if ((ggtt
->base
.total
- 1) >> 32) {
3198 DRM_ERROR("We never expected a Global GTT with more than 32bits"
3199 "of address space! Found %lldM!\n",
3200 ggtt
->base
.total
>> 20);
3201 ggtt
->base
.total
= 1ULL << 32;
3202 ggtt
->mappable_end
= min(ggtt
->mappable_end
, ggtt
->base
.total
);
3206 * Initialise stolen early so that we may reserve preallocated
3207 * objects for the BIOS to KMS transition.
3209 ret
= i915_gem_init_stolen(dev
);
3211 goto out_gtt_cleanup
;
3213 /* GMADR is the PCI mmio aperture into the global GTT. */
3214 DRM_INFO("Memory usable by graphics device = %lluM\n",
3215 ggtt
->base
.total
>> 20);
3216 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt
->mappable_end
>> 20);
3217 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", ggtt
->stolen_size
>> 20);
3218 #ifdef CONFIG_INTEL_IOMMU
3219 if (intel_iommu_gfx_mapped
)
3220 DRM_INFO("VT-d active for gfx access\n");
3223 * i915.enable_ppgtt is read-only, so do an early pass to validate the
3224 * user's requested state against the hardware/driver capabilities. We
3225 * do this now so that we can print out any log messages once rather
3226 * than every time we check intel_enable_ppgtt().
3228 i915
.enable_ppgtt
= sanitize_enable_ppgtt(dev
, i915
.enable_ppgtt
);
3229 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915
.enable_ppgtt
);
3234 ggtt
->base
.cleanup(&ggtt
->base
);
3239 int i915_ggtt_enable_hw(struct drm_device
*dev
)
3241 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
3247 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
)
3249 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3250 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3251 struct drm_i915_gem_object
*obj
;
3252 struct i915_vma
*vma
;
3255 i915_check_and_clear_faults(dev
);
3257 /* First fill our portion of the GTT with scratch pages */
3258 ggtt
->base
.clear_range(&ggtt
->base
, ggtt
->base
.start
, ggtt
->base
.total
,
3261 /* Cache flush objects bound into GGTT and rebind them. */
3262 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
3264 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3265 if (vma
->vm
!= &ggtt
->base
)
3268 WARN_ON(i915_vma_bind(vma
, obj
->cache_level
,
3275 i915_gem_clflush_object(obj
, obj
->pin_display
);
3278 if (INTEL_INFO(dev
)->gen
>= 8) {
3279 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
3280 chv_setup_private_ppat(dev_priv
);
3282 bdw_setup_private_ppat(dev_priv
);
3287 if (USES_PPGTT(dev
)) {
3288 struct i915_address_space
*vm
;
3290 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
3291 /* TODO: Perhaps it shouldn't be gen6 specific */
3293 struct i915_hw_ppgtt
*ppgtt
;
3296 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
3298 ppgtt
= i915_vm_to_ppgtt(vm
);
3300 gen6_write_page_range(dev_priv
, &ppgtt
->pd
,
3301 0, ppgtt
->base
.total
);
3305 i915_ggtt_flush(dev_priv
);
3308 static struct i915_vma
*
3309 __i915_gem_vma_create(struct drm_i915_gem_object
*obj
,
3310 struct i915_address_space
*vm
,
3311 const struct i915_ggtt_view
*ggtt_view
)
3313 struct i915_vma
*vma
;
3315 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
3316 return ERR_PTR(-EINVAL
);
3318 vma
= kmem_cache_zalloc(to_i915(obj
->base
.dev
)->vmas
, GFP_KERNEL
);
3320 return ERR_PTR(-ENOMEM
);
3322 INIT_LIST_HEAD(&vma
->vm_link
);
3323 INIT_LIST_HEAD(&vma
->obj_link
);
3324 INIT_LIST_HEAD(&vma
->exec_list
);
3327 vma
->is_ggtt
= i915_is_ggtt(vm
);
3329 if (i915_is_ggtt(vm
))
3330 vma
->ggtt_view
= *ggtt_view
;
3332 i915_ppgtt_get(i915_vm_to_ppgtt(vm
));
3334 list_add_tail(&vma
->obj_link
, &obj
->vma_list
);
3340 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3341 struct i915_address_space
*vm
)
3343 struct i915_vma
*vma
;
3345 vma
= i915_gem_obj_to_vma(obj
, vm
);
3347 vma
= __i915_gem_vma_create(obj
, vm
,
3348 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
);
3354 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
3355 const struct i915_ggtt_view
*view
)
3357 struct drm_device
*dev
= obj
->base
.dev
;
3358 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3359 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3360 struct i915_vma
*vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
3363 vma
= __i915_gem_vma_create(obj
, &ggtt
->base
, view
);
3369 static struct scatterlist
*
3370 rotate_pages(const dma_addr_t
*in
, unsigned int offset
,
3371 unsigned int width
, unsigned int height
,
3372 unsigned int stride
,
3373 struct sg_table
*st
, struct scatterlist
*sg
)
3375 unsigned int column
, row
;
3376 unsigned int src_idx
;
3378 for (column
= 0; column
< width
; column
++) {
3379 src_idx
= stride
* (height
- 1) + column
;
3380 for (row
= 0; row
< height
; row
++) {
3382 /* We don't need the pages, but need to initialize
3383 * the entries so the sg list can be happily traversed.
3384 * The only thing we need are DMA addresses.
3386 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
3387 sg_dma_address(sg
) = in
[offset
+ src_idx
];
3388 sg_dma_len(sg
) = PAGE_SIZE
;
3397 static struct sg_table
*
3398 intel_rotate_fb_obj_pages(struct intel_rotation_info
*rot_info
,
3399 struct drm_i915_gem_object
*obj
)
3401 unsigned int size_pages
= rot_info
->plane
[0].width
* rot_info
->plane
[0].height
;
3402 unsigned int size_pages_uv
;
3403 struct sg_page_iter sg_iter
;
3405 dma_addr_t
*page_addr_list
;
3406 struct sg_table
*st
;
3407 unsigned int uv_start_page
;
3408 struct scatterlist
*sg
;
3411 /* Allocate a temporary list of source pages for random access. */
3412 page_addr_list
= drm_malloc_gfp(obj
->base
.size
/ PAGE_SIZE
,
3415 if (!page_addr_list
)
3416 return ERR_PTR(ret
);
3418 /* Account for UV plane with NV12. */
3419 if (rot_info
->pixel_format
== DRM_FORMAT_NV12
)
3420 size_pages_uv
= rot_info
->plane
[1].width
* rot_info
->plane
[1].height
;
3424 /* Allocate target SG list. */
3425 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
3429 ret
= sg_alloc_table(st
, size_pages
+ size_pages_uv
, GFP_KERNEL
);
3433 /* Populate source page list from the object. */
3435 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
3436 page_addr_list
[i
] = sg_page_iter_dma_address(&sg_iter
);
3443 /* Rotate the pages. */
3444 sg
= rotate_pages(page_addr_list
, 0,
3445 rot_info
->plane
[0].width
, rot_info
->plane
[0].height
,
3446 rot_info
->plane
[0].width
,
3449 /* Append the UV plane if NV12. */
3450 if (rot_info
->pixel_format
== DRM_FORMAT_NV12
) {
3451 uv_start_page
= size_pages
;
3453 /* Check for tile-row un-alignment. */
3454 if (offset_in_page(rot_info
->uv_offset
))
3457 rot_info
->uv_start_page
= uv_start_page
;
3459 sg
= rotate_pages(page_addr_list
, rot_info
->uv_start_page
,
3460 rot_info
->plane
[1].width
, rot_info
->plane
[1].height
,
3461 rot_info
->plane
[1].width
,
3465 DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages (%u plane 0)).\n",
3466 obj
->base
.size
, rot_info
->plane
[0].width
,
3467 rot_info
->plane
[0].height
, size_pages
+ size_pages_uv
,
3470 drm_free_large(page_addr_list
);
3477 drm_free_large(page_addr_list
);
3479 DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%d) (%ux%u tiles, %u pages (%u plane 0))\n",
3480 obj
->base
.size
, ret
, rot_info
->plane
[0].width
,
3481 rot_info
->plane
[0].height
, size_pages
+ size_pages_uv
,
3483 return ERR_PTR(ret
);
3486 static struct sg_table
*
3487 intel_partial_pages(const struct i915_ggtt_view
*view
,
3488 struct drm_i915_gem_object
*obj
)
3490 struct sg_table
*st
;
3491 struct scatterlist
*sg
;
3492 struct sg_page_iter obj_sg_iter
;
3495 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
3499 ret
= sg_alloc_table(st
, view
->params
.partial
.size
, GFP_KERNEL
);
3505 for_each_sg_page(obj
->pages
->sgl
, &obj_sg_iter
, obj
->pages
->nents
,
3506 view
->params
.partial
.offset
)
3508 if (st
->nents
>= view
->params
.partial
.size
)
3511 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
3512 sg_dma_address(sg
) = sg_page_iter_dma_address(&obj_sg_iter
);
3513 sg_dma_len(sg
) = PAGE_SIZE
;
3524 return ERR_PTR(ret
);
3528 i915_get_ggtt_vma_pages(struct i915_vma
*vma
)
3532 if (vma
->ggtt_view
.pages
)
3535 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
)
3536 vma
->ggtt_view
.pages
= vma
->obj
->pages
;
3537 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_ROTATED
)
3538 vma
->ggtt_view
.pages
=
3539 intel_rotate_fb_obj_pages(&vma
->ggtt_view
.params
.rotated
, vma
->obj
);
3540 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_PARTIAL
)
3541 vma
->ggtt_view
.pages
=
3542 intel_partial_pages(&vma
->ggtt_view
, vma
->obj
);
3544 WARN_ONCE(1, "GGTT view %u not implemented!\n",
3545 vma
->ggtt_view
.type
);
3547 if (!vma
->ggtt_view
.pages
) {
3548 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
3549 vma
->ggtt_view
.type
);
3551 } else if (IS_ERR(vma
->ggtt_view
.pages
)) {
3552 ret
= PTR_ERR(vma
->ggtt_view
.pages
);
3553 vma
->ggtt_view
.pages
= NULL
;
3554 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3555 vma
->ggtt_view
.type
, ret
);
3562 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
3564 * @cache_level: mapping cache level
3565 * @flags: flags like global or local mapping
3567 * DMA addresses are taken from the scatter-gather table of this object (or of
3568 * this VMA in case of non-default GGTT views) and PTE entries set up.
3569 * Note that DMA addresses are also the only part of the SG table we care about.
3571 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
3577 if (WARN_ON(flags
== 0))
3581 if (flags
& PIN_GLOBAL
)
3582 bind_flags
|= GLOBAL_BIND
;
3583 if (flags
& PIN_USER
)
3584 bind_flags
|= LOCAL_BIND
;
3586 if (flags
& PIN_UPDATE
)
3587 bind_flags
|= vma
->bound
;
3589 bind_flags
&= ~vma
->bound
;
3591 if (bind_flags
== 0)
3594 if (vma
->bound
== 0 && vma
->vm
->allocate_va_range
) {
3595 /* XXX: i915_vma_pin() will fix this +- hack */
3597 trace_i915_va_alloc(vma
);
3598 ret
= vma
->vm
->allocate_va_range(vma
->vm
,
3606 ret
= vma
->vm
->bind_vma(vma
, cache_level
, bind_flags
);
3610 vma
->bound
|= bind_flags
;
3616 * i915_ggtt_view_size - Get the size of a GGTT view.
3617 * @obj: Object the view is of.
3618 * @view: The view in question.
3620 * @return The size of the GGTT view in bytes.
3623 i915_ggtt_view_size(struct drm_i915_gem_object
*obj
,
3624 const struct i915_ggtt_view
*view
)
3626 if (view
->type
== I915_GGTT_VIEW_NORMAL
) {
3627 return obj
->base
.size
;
3628 } else if (view
->type
== I915_GGTT_VIEW_ROTATED
) {
3629 return intel_rotation_info_size(&view
->params
.rotated
) << PAGE_SHIFT
;
3630 } else if (view
->type
== I915_GGTT_VIEW_PARTIAL
) {
3631 return view
->params
.partial
.size
<< PAGE_SHIFT
;
3633 WARN_ONCE(1, "GGTT view %u not implemented!\n", view
->type
);
3634 return obj
->base
.size
;