drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drmP.h>
  26 #include <drm/i915_drm.h>
  27 #include "i915_drv.h"
  28 #include "i915_trace.h"
  29 #include "intel_drv.h"
  30
  31 /* PPGTT stuff */
  32 #define GEN6_GTT_ADDR_ENCODE(addr)      ((addr) | (((addr) >> 28) & 0xff0))
  33
  34 #define GEN6_PDE_VALID                  (1 << 0)
  35 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
  36 #define GEN6_PDE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  37
  38 #define GEN6_PTE_VALID                  (1 << 0)
  39 #define GEN6_PTE_UNCACHED               (1 << 1)
  40 #define HSW_PTE_UNCACHED                (0)
  41 #define GEN6_PTE_CACHE_LLC              (2 << 1)
  42 #define GEN6_PTE_CACHE_LLC_MLC          (3 << 1)
  43 #define GEN6_PTE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  44
  45 static gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev,
  46                                       dma_addr_t addr,
  47                                       enum i915_cache_level level)
  48 {
  49         gen6_gtt_pte_t pte = GEN6_PTE_VALID;
  50         pte |= GEN6_PTE_ADDR_ENCODE(addr);
  51
  52         switch (level) {
  53         case I915_CACHE_LLC_MLC:
  54                 pte |= GEN6_PTE_CACHE_LLC_MLC;
  55                 break;
  56         case I915_CACHE_LLC:
  57                 pte |= GEN6_PTE_CACHE_LLC;
  58                 break;
  59         case I915_CACHE_NONE:
  60                 pte |= GEN6_PTE_UNCACHED;
  61                 break;
  62         default:
  63                 BUG();
  64         }
  65
  66         return pte;
  67 }
  68
  69 #define BYT_PTE_WRITEABLE               (1 << 1)
  70 #define BYT_PTE_SNOOPED_BY_CPU_CACHES   (1 << 2)
  71
  72 static gen6_gtt_pte_t byt_pte_encode(struct drm_device *dev,
  73                                      dma_addr_t addr,
  74                                      enum i915_cache_level level)
  75 {
  76         gen6_gtt_pte_t pte = GEN6_PTE_VALID;
  77         pte |= GEN6_PTE_ADDR_ENCODE(addr);
  78
  79         /* Mark the page as writeable.  Other platforms don't have a
  80          * setting for read-only/writable, so this matches that behavior.
  81          */
  82         pte |= BYT_PTE_WRITEABLE;
  83
  84         if (level != I915_CACHE_NONE)
  85                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
  86
  87         return pte;
  88 }
  89
  90 static gen6_gtt_pte_t hsw_pte_encode(struct drm_device *dev,
  91                                      dma_addr_t addr,
  92                                      enum i915_cache_level level)
  93 {
  94         gen6_gtt_pte_t pte = GEN6_PTE_VALID;
  95         pte |= GEN6_PTE_ADDR_ENCODE(addr);
  96
  97         if (level != I915_CACHE_NONE)
  98                 pte |= GEN6_PTE_CACHE_LLC;
  99
 100         return pte;
 101 }
 102
 103 static int gen6_ppgtt_enable(struct drm_device *dev)
 104 {
 105         drm_i915_private_t *dev_priv = dev->dev_private;
 106         uint32_t pd_offset;
 107         struct intel_ring_buffer *ring;
 108         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 109         gen6_gtt_pte_t __iomem *pd_addr;
 110         uint32_t pd_entry;
 111         int i;
 112
 113         WARN_ON(ppgtt->pd_offset & 0x3f);
 114
 115         pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
 116                 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
 117         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 118                 dma_addr_t pt_addr;
 119
 120                 pt_addr = ppgtt->pt_dma_addr[i];
 121                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
 122                 pd_entry |= GEN6_PDE_VALID;
 123
 124                 writel(pd_entry, pd_addr + i);
 125         }
 126         readl(pd_addr);
 127
 128         pd_offset = ppgtt->pd_offset;
 129         pd_offset /= 64; /* in cachelines, */
 130         pd_offset <<= 16;
 131
 132         if (INTEL_INFO(dev)->gen == 6) {
 133                 uint32_t ecochk, gab_ctl, ecobits;
 134
 135                 ecobits = I915_READ(GAC_ECO_BITS);
 136                 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
 137                                          ECOBITS_PPGTT_CACHE64B);
 138
 139                 gab_ctl = I915_READ(GAB_CTL);
 140                 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
 141
 142                 ecochk = I915_READ(GAM_ECOCHK);
 143                 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
 144                                        ECOCHK_PPGTT_CACHE64B);
 145                 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 146         } else if (INTEL_INFO(dev)->gen >= 7) {
 147                 uint32_t ecochk, ecobits;
 148
 149                 ecobits = I915_READ(GAC_ECO_BITS);
 150                 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 151
 152                 ecochk = I915_READ(GAM_ECOCHK);
 153                 if (IS_HASWELL(dev)) {
 154                         ecochk |= ECOCHK_PPGTT_WB_HSW;
 155                 } else {
 156                         ecochk |= ECOCHK_PPGTT_LLC_IVB;
 157                         ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
 158                 }
 159                 I915_WRITE(GAM_ECOCHK, ecochk);
 160                 /* GFX_MODE is per-ring on gen7+ */
 161         }
 162
 163         for_each_ring(ring, dev_priv, i) {
 164                 if (INTEL_INFO(dev)->gen >= 7)
 165                         I915_WRITE(RING_MODE_GEN7(ring),
 166                                    _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 167
 168                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 169                 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
 170         }
 171         return 0;
 172 }
 173
 174 /* PPGTT support for Sandybdrige/Gen6 and later */
 175 static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
 176                                    unsigned first_entry,
 177                                    unsigned num_entries)
 178 {
 179         gen6_gtt_pte_t *pt_vaddr, scratch_pte;
 180         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 181         unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 182         unsigned last_pte, i;
 183
 184         scratch_pte = ppgtt->pte_encode(ppgtt->dev,
 185                                         ppgtt->scratch_page_dma_addr,
 186                                         I915_CACHE_LLC);
 187
 188         while (num_entries) {
 189                 last_pte = first_pte + num_entries;
 190                 if (last_pte > I915_PPGTT_PT_ENTRIES)
 191                         last_pte = I915_PPGTT_PT_ENTRIES;
 192
 193                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 194
 195                 for (i = first_pte; i < last_pte; i++)
 196                         pt_vaddr[i] = scratch_pte;
 197
 198                 kunmap_atomic(pt_vaddr);
 199
 200                 num_entries -= last_pte - first_pte;
 201                 first_pte = 0;
 202                 act_pt++;
 203         }
 204 }
 205
 206 static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt,
 207                                       struct sg_table *pages,
 208                                       unsigned first_entry,
 209                                       enum i915_cache_level cache_level)
 210 {
 211         gen6_gtt_pte_t *pt_vaddr;
 212         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 213         unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 214         struct sg_page_iter sg_iter;
 215
 216         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 217         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 218                 dma_addr_t page_addr;
 219
 220                 page_addr = sg_page_iter_dma_address(&sg_iter);
 221                 pt_vaddr[act_pte] = ppgtt->pte_encode(ppgtt->dev, page_addr,
 222                                                       cache_level);
 223                 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
 224                         kunmap_atomic(pt_vaddr);
 225                         act_pt++;
 226                         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 227                         act_pte = 0;
 228
 229                 }
 230         }
 231         kunmap_atomic(pt_vaddr);
 232 }
 233
 234 static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt)
 235 {
 236         int i;
 237
 238         if (ppgtt->pt_dma_addr) {
 239                 for (i = 0; i < ppgtt->num_pd_entries; i++)
 240                         pci_unmap_page(ppgtt->dev->pdev,
 241                                        ppgtt->pt_dma_addr[i],
 242                                        4096, PCI_DMA_BIDIRECTIONAL);
 243         }
 244
 245         kfree(ppgtt->pt_dma_addr);
 246         for (i = 0; i < ppgtt->num_pd_entries; i++)
 247                 __free_page(ppgtt->pt_pages[i]);
 248         kfree(ppgtt->pt_pages);
 249         kfree(ppgtt);
 250 }
 251
 252 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 253 {
 254         struct drm_device *dev = ppgtt->dev;
 255         struct drm_i915_private *dev_priv = dev->dev_private;
 256         unsigned first_pd_entry_in_global_pt;
 257         int i;
 258         int ret = -ENOMEM;
 259
 260         /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
 261          * entries. For aliasing ppgtt support we just steal them at the end for
 262          * now. */
 263         first_pd_entry_in_global_pt =
 264                 gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES;
 265
 266         if (IS_HASWELL(dev)) {
 267                 ppgtt->pte_encode = hsw_pte_encode;
 268         } else if (IS_VALLEYVIEW(dev)) {
 269                 ppgtt->pte_encode = byt_pte_encode;
 270         } else {
 271                 ppgtt->pte_encode = gen6_pte_encode;
 272         }
 273         ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
 274         ppgtt->enable = gen6_ppgtt_enable;
 275         ppgtt->clear_range = gen6_ppgtt_clear_range;
 276         ppgtt->insert_entries = gen6_ppgtt_insert_entries;
 277         ppgtt->cleanup = gen6_ppgtt_cleanup;
 278         ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
 279                                   GFP_KERNEL);
 280         if (!ppgtt->pt_pages)
 281                 return -ENOMEM;
 282
 283         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 284                 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
 285                 if (!ppgtt->pt_pages[i])
 286                         goto err_pt_alloc;
 287         }
 288
 289         ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries,
 290                                      GFP_KERNEL);
 291         if (!ppgtt->pt_dma_addr)
 292                 goto err_pt_alloc;
 293
 294         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 295                 dma_addr_t pt_addr;
 296
 297                 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
 298                                        PCI_DMA_BIDIRECTIONAL);
 299
 300                 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
 301                         ret = -EIO;
 302                         goto err_pd_pin;
 303
 304                 }
 305                 ppgtt->pt_dma_addr[i] = pt_addr;
 306         }
 307
 308         ppgtt->clear_range(ppgtt, 0,
 309                            ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES);
 310
 311         ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t);
 312
 313         return 0;
 314
 315 err_pd_pin:
 316         if (ppgtt->pt_dma_addr) {
 317                 for (i--; i >= 0; i--)
 318                         pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
 319                                        4096, PCI_DMA_BIDIRECTIONAL);
 320         }
 321 err_pt_alloc:
 322         kfree(ppgtt->pt_dma_addr);
 323         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 324                 if (ppgtt->pt_pages[i])
 325                         __free_page(ppgtt->pt_pages[i]);
 326         }
 327         kfree(ppgtt->pt_pages);
 328
 329         return ret;
 330 }
 331
 332 static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
 333 {
 334         struct drm_i915_private *dev_priv = dev->dev_private;
 335         struct i915_hw_ppgtt *ppgtt;
 336         int ret;
 337
 338         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
 339         if (!ppgtt)
 340                 return -ENOMEM;
 341
 342         ppgtt->dev = dev;
 343         ppgtt->scratch_page_dma_addr = dev_priv->gtt.scratch_page_dma;
 344
 345         if (INTEL_INFO(dev)->gen < 8)
 346                 ret = gen6_ppgtt_init(ppgtt);
 347         else
 348                 BUG();
 349
 350         if (ret)
 351                 kfree(ppgtt);
 352         else
 353                 dev_priv->mm.aliasing_ppgtt = ppgtt;
 354
 355         return ret;
 356 }
 357
 358 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
 359 {
 360         struct drm_i915_private *dev_priv = dev->dev_private;
 361         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 362
 363         if (!ppgtt)
 364                 return;
 365
 366         ppgtt->cleanup(ppgtt);
 367         dev_priv->mm.aliasing_ppgtt = NULL;
 368 }
 369
 370 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
 371                             struct drm_i915_gem_object *obj,
 372                             enum i915_cache_level cache_level)
 373 {
 374         ppgtt->insert_entries(ppgtt, obj->pages,
 375                               obj->gtt_space->start >> PAGE_SHIFT,
 376                               cache_level);
 377 }
 378
 379 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
 380                               struct drm_i915_gem_object *obj)
 381 {
 382         ppgtt->clear_range(ppgtt,
 383                            obj->gtt_space->start >> PAGE_SHIFT,
 384                            obj->base.size >> PAGE_SHIFT);
 385 }
 386
 387 extern int intel_iommu_gfx_mapped;
 388 /* Certain Gen5 chipsets require require idling the GPU before
 389  * unmapping anything from the GTT when VT-d is enabled.
 390  */
 391 static inline bool needs_idle_maps(struct drm_device *dev)
 392 {
 393 #ifdef CONFIG_INTEL_IOMMU
 394         /* Query intel_iommu to see if we need the workaround. Presumably that
 395          * was loaded first.
 396          */
 397         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
 398                 return true;
 399 #endif
 400         return false;
 401 }
 402
 403 static bool do_idling(struct drm_i915_private *dev_priv)
 404 {
 405         bool ret = dev_priv->mm.interruptible;
 406
 407         if (unlikely(dev_priv->gtt.do_idle_maps)) {
 408                 dev_priv->mm.interruptible = false;
 409                 if (i915_gpu_idle(dev_priv->dev)) {
 410                         DRM_ERROR("Couldn't idle GPU\n");
 411                         /* Wait a bit, in hopes it avoids the hang */
 412                         udelay(10);
 413                 }
 414         }
 415
 416         return ret;
 417 }
 418
 419 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
 420 {
 421         if (unlikely(dev_priv->gtt.do_idle_maps))
 422                 dev_priv->mm.interruptible = interruptible;
 423 }
 424
 425 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
 426 {
 427         struct drm_i915_private *dev_priv = dev->dev_private;
 428         struct drm_i915_gem_object *obj;
 429
 430         /* First fill our portion of the GTT with scratch pages */
 431         dev_priv->gtt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE,
 432                                       dev_priv->gtt.total / PAGE_SIZE);
 433
 434         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
 435                 i915_gem_clflush_object(obj);
 436                 i915_gem_gtt_bind_object(obj, obj->cache_level);
 437         }
 438
 439         i915_gem_chipset_flush(dev);
 440 }
 441
 442 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
 443 {
 444         if (obj->has_dma_mapping)
 445                 return 0;
 446
 447         if (!dma_map_sg(&obj->base.dev->pdev->dev,
 448                         obj->pages->sgl, obj->pages->nents,
 449                         PCI_DMA_BIDIRECTIONAL))
 450                 return -ENOSPC;
 451
 452         return 0;
 453 }
 454
 455 /*
 456  * Binds an object into the global gtt with the specified cache level. The object
 457  * will be accessible to the GPU via commands whose operands reference offsets
 458  * within the global GTT as well as accessible by the GPU through the GMADR
 459  * mapped BAR (dev_priv->mm.gtt->gtt).
 460  */
 461 static void gen6_ggtt_insert_entries(struct drm_device *dev,
 462                                      struct sg_table *st,
 463                                      unsigned int first_entry,
 464                                      enum i915_cache_level level)
 465 {
 466         struct drm_i915_private *dev_priv = dev->dev_private;
 467         gen6_gtt_pte_t __iomem *gtt_entries =
 468                 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
 469         int i = 0;
 470         struct sg_page_iter sg_iter;
 471         dma_addr_t addr;
 472
 473         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
 474                 addr = sg_page_iter_dma_address(&sg_iter);
 475                 iowrite32(dev_priv->gtt.pte_encode(dev, addr, level),
 476                           &gtt_entries[i]);
 477                 i++;
 478         }
 479
 480         /* XXX: This serves as a posting read to make sure that the PTE has
 481          * actually been updated. There is some concern that even though
 482          * registers and PTEs are within the same BAR that they are potentially
 483          * of NUMA access patterns. Therefore, even with the way we assume
 484          * hardware should work, we must keep this posting read for paranoia.
 485          */
 486         if (i != 0)
 487                 WARN_ON(readl(&gtt_entries[i-1])
 488                         != dev_priv->gtt.pte_encode(dev, addr, level));
 489
 490         /* This next bit makes the above posting read even more important. We
 491          * want to flush the TLBs only after we're certain all the PTE updates
 492          * have finished.
 493          */
 494         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 495         POSTING_READ(GFX_FLSH_CNTL_GEN6);
 496 }
 497
 498 static void gen6_ggtt_clear_range(struct drm_device *dev,
 499                                   unsigned int first_entry,
 500                                   unsigned int num_entries)
 501 {
 502         struct drm_i915_private *dev_priv = dev->dev_private;
 503         gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
 504                 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
 505         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
 506         int i;
 507
 508         if (WARN(num_entries > max_entries,
 509                  "First entry = %d; Num entries = %d (max=%d)\n",
 510                  first_entry, num_entries, max_entries))
 511                 num_entries = max_entries;
 512
 513         scratch_pte = dev_priv->gtt.pte_encode(dev,
 514                                                dev_priv->gtt.scratch_page_dma,
 515                                                I915_CACHE_LLC);
 516         for (i = 0; i < num_entries; i++)
 517                 iowrite32(scratch_pte, &gtt_base[i]);
 518         readl(gtt_base);
 519 }
 520
 521
 522 static void i915_ggtt_insert_entries(struct drm_device *dev,
 523                                      struct sg_table *st,
 524                                      unsigned int pg_start,
 525                                      enum i915_cache_level cache_level)
 526 {
 527         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
 528                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
 529
 530         intel_gtt_insert_sg_entries(st, pg_start, flags);
 531
 532 }
 533
 534 static void i915_ggtt_clear_range(struct drm_device *dev,
 535                                   unsigned int first_entry,
 536                                   unsigned int num_entries)
 537 {
 538         intel_gtt_clear_range(first_entry, num_entries);
 539 }
 540
 541
 542 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
 543                               enum i915_cache_level cache_level)
 544 {
 545         struct drm_device *dev = obj->base.dev;
 546         struct drm_i915_private *dev_priv = dev->dev_private;
 547
 548         dev_priv->gtt.gtt_insert_entries(dev, obj->pages,
 549                                          obj->gtt_space->start >> PAGE_SHIFT,
 550                                          cache_level);
 551
 552         obj->has_global_gtt_mapping = 1;
 553 }
 554
 555 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
 556 {
 557         struct drm_device *dev = obj->base.dev;
 558         struct drm_i915_private *dev_priv = dev->dev_private;
 559
 560         dev_priv->gtt.gtt_clear_range(obj->base.dev,
 561                                       obj->gtt_space->start >> PAGE_SHIFT,
 562                                       obj->base.size >> PAGE_SHIFT);
 563
 564         obj->has_global_gtt_mapping = 0;
 565 }
 566
 567 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
 568 {
 569         struct drm_device *dev = obj->base.dev;
 570         struct drm_i915_private *dev_priv = dev->dev_private;
 571         bool interruptible;
 572
 573         interruptible = do_idling(dev_priv);
 574
 575         if (!obj->has_dma_mapping)
 576                 dma_unmap_sg(&dev->pdev->dev,
 577                              obj->pages->sgl, obj->pages->nents,
 578                              PCI_DMA_BIDIRECTIONAL);
 579
 580         undo_idling(dev_priv, interruptible);
 581 }
 582
 583 static void i915_gtt_color_adjust(struct drm_mm_node *node,
 584                                   unsigned long color,
 585                                   unsigned long *start,
 586                                   unsigned long *end)
 587 {
 588         if (node->color != color)
 589                 *start += 4096;
 590
 591         if (!list_empty(&node->node_list)) {
 592                 node = list_entry(node->node_list.next,
 593                                   struct drm_mm_node,
 594                                   node_list);
 595                 if (node->allocated && node->color != color)
 596                         *end -= 4096;
 597         }
 598 }
 599 void i915_gem_setup_global_gtt(struct drm_device *dev,
 600                                unsigned long start,
 601                                unsigned long mappable_end,
 602                                unsigned long end)
 603 {
 604         /* Let GEM Manage all of the aperture.
 605          *
 606          * However, leave one page at the end still bound to the scratch page.
 607          * There are a number of places where the hardware apparently prefetches
 608          * past the end of the object, and we've seen multiple hangs with the
 609          * GPU head pointer stuck in a batchbuffer bound at the last page of the
 610          * aperture.  One page should be enough to keep any prefetching inside
 611          * of the aperture.
 612          */
 613         drm_i915_private_t *dev_priv = dev->dev_private;
 614         struct drm_mm_node *entry;
 615         struct drm_i915_gem_object *obj;
 616         unsigned long hole_start, hole_end;
 617
 618         BUG_ON(mappable_end > end);
 619
 620         /* Subtract the guard page ... */
 621         drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE);
 622         if (!HAS_LLC(dev))
 623                 dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust;
 624
 625         /* Mark any preallocated objects as occupied */
 626         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
 627                 DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n",
 628                               obj->gtt_offset, obj->base.size);
 629
 630                 BUG_ON(obj->gtt_space != I915_GTT_RESERVED);
 631                 obj->gtt_space = drm_mm_create_block(&dev_priv->mm.gtt_space,
 632                                                      obj->gtt_offset,
 633                                                      obj->base.size,
 634                                                      false);
 635                 obj->has_global_gtt_mapping = 1;
 636         }
 637
 638         dev_priv->gtt.start = start;
 639         dev_priv->gtt.total = end - start;
 640
 641         /* Clear any non-preallocated blocks */
 642         drm_mm_for_each_hole(entry, &dev_priv->mm.gtt_space,
 643                              hole_start, hole_end) {
 644                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
 645                               hole_start, hole_end);
 646                 dev_priv->gtt.gtt_clear_range(dev, hole_start / PAGE_SIZE,
 647                                               (hole_end-hole_start) / PAGE_SIZE);
 648         }
 649
 650         /* And finally clear the reserved guard page */
 651         dev_priv->gtt.gtt_clear_range(dev, end / PAGE_SIZE - 1, 1);
 652 }
 653
 654 static bool
 655 intel_enable_ppgtt(struct drm_device *dev)
 656 {
 657         if (i915_enable_ppgtt >= 0)
 658                 return i915_enable_ppgtt;
 659
 660 #ifdef CONFIG_INTEL_IOMMU
 661         /* Disable ppgtt on SNB if VT-d is on. */
 662         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 663                 return false;
 664 #endif
 665
 666         return true;
 667 }
 668
 669 void i915_gem_init_global_gtt(struct drm_device *dev)
 670 {
 671         struct drm_i915_private *dev_priv = dev->dev_private;
 672         unsigned long gtt_size, mappable_size;
 673
 674         gtt_size = dev_priv->gtt.total;
 675         mappable_size = dev_priv->gtt.mappable_end;
 676
 677         if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
 678                 int ret;
 679
 680                 if (INTEL_INFO(dev)->gen <= 7) {
 681                         /* PPGTT pdes are stolen from global gtt ptes, so shrink the
 682                          * aperture accordingly when using aliasing ppgtt. */
 683                         gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
 684                 }
 685
 686                 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
 687
 688                 ret = i915_gem_init_aliasing_ppgtt(dev);
 689                 if (!ret)
 690                         return;
 691
 692                 DRM_ERROR("Aliased PPGTT setup failed %d\n", ret);
 693                 drm_mm_takedown(&dev_priv->mm.gtt_space);
 694                 gtt_size += I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
 695         }
 696         i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
 697 }
 698
 699 static int setup_scratch_page(struct drm_device *dev)
 700 {
 701         struct drm_i915_private *dev_priv = dev->dev_private;
 702         struct page *page;
 703         dma_addr_t dma_addr;
 704
 705         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
 706         if (page == NULL)
 707                 return -ENOMEM;
 708         get_page(page);
 709         set_pages_uc(page, 1);
 710
 711 #ifdef CONFIG_INTEL_IOMMU
 712         dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
 713                                 PCI_DMA_BIDIRECTIONAL);
 714         if (pci_dma_mapping_error(dev->pdev, dma_addr))
 715                 return -EINVAL;
 716 #else
 717         dma_addr = page_to_phys(page);
 718 #endif
 719         dev_priv->gtt.scratch_page = page;
 720         dev_priv->gtt.scratch_page_dma = dma_addr;
 721
 722         return 0;
 723 }
 724
 725 static void teardown_scratch_page(struct drm_device *dev)
 726 {
 727         struct drm_i915_private *dev_priv = dev->dev_private;
 728         set_pages_wb(dev_priv->gtt.scratch_page, 1);
 729         pci_unmap_page(dev->pdev, dev_priv->gtt.scratch_page_dma,
 730                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 731         put_page(dev_priv->gtt.scratch_page);
 732         __free_page(dev_priv->gtt.scratch_page);
 733 }
 734
 735 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
 736 {
 737         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
 738         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
 739         return snb_gmch_ctl << 20;
 740 }
 741
 742 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
 743 {
 744         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
 745         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
 746         return snb_gmch_ctl << 25; /* 32 MB units */
 747 }
 748
 749 static inline size_t gen7_get_stolen_size(u16 snb_gmch_ctl)
 750 {
 751         static const int stolen_decoder[] = {
 752                 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352};
 753         snb_gmch_ctl >>= IVB_GMCH_GMS_SHIFT;
 754         snb_gmch_ctl &= IVB_GMCH_GMS_MASK;
 755         return stolen_decoder[snb_gmch_ctl] << 20;
 756 }
 757
 758 static int gen6_gmch_probe(struct drm_device *dev,
 759                            size_t *gtt_total,
 760                            size_t *stolen,
 761                            phys_addr_t *mappable_base,
 762                            unsigned long *mappable_end)
 763 {
 764         struct drm_i915_private *dev_priv = dev->dev_private;
 765         phys_addr_t gtt_bus_addr;
 766         unsigned int gtt_size;
 767         u16 snb_gmch_ctl;
 768         int ret;
 769
 770         *mappable_base = pci_resource_start(dev->pdev, 2);
 771         *mappable_end = pci_resource_len(dev->pdev, 2);
 772
 773         /* 64/512MB is the current min/max we actually know of, but this is just
 774          * a coarse sanity check.
 775          */
 776         if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
 777                 DRM_ERROR("Unknown GMADR size (%lx)\n",
 778                           dev_priv->gtt.mappable_end);
 779                 return -ENXIO;
 780         }
 781
 782         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
 783                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
 784         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 785         gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
 786
 787         if (IS_GEN7(dev) && !IS_VALLEYVIEW(dev))
 788                 *stolen = gen7_get_stolen_size(snb_gmch_ctl);
 789         else
 790                 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
 791
 792         *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
 793
 794         /* For Modern GENs the PTEs and register space are split in the BAR */
 795         gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
 796                 (pci_resource_len(dev->pdev, 0) / 2);
 797
 798         dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
 799         if (!dev_priv->gtt.gsm) {
 800                 DRM_ERROR("Failed to map the gtt page table\n");
 801                 return -ENOMEM;
 802         }
 803
 804         ret = setup_scratch_page(dev);
 805         if (ret)
 806                 DRM_ERROR("Scratch setup failed\n");
 807
 808         dev_priv->gtt.gtt_clear_range = gen6_ggtt_clear_range;
 809         dev_priv->gtt.gtt_insert_entries = gen6_ggtt_insert_entries;
 810
 811         return ret;
 812 }
 813
 814 static void gen6_gmch_remove(struct drm_device *dev)
 815 {
 816         struct drm_i915_private *dev_priv = dev->dev_private;
 817         iounmap(dev_priv->gtt.gsm);
 818         teardown_scratch_page(dev_priv->dev);
 819 }
 820
 821 static int i915_gmch_probe(struct drm_device *dev,
 822                            size_t *gtt_total,
 823                            size_t *stolen,
 824                            phys_addr_t *mappable_base,
 825                            unsigned long *mappable_end)
 826 {
 827         struct drm_i915_private *dev_priv = dev->dev_private;
 828         int ret;
 829
 830         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
 831         if (!ret) {
 832                 DRM_ERROR("failed to set up gmch\n");
 833                 return -EIO;
 834         }
 835
 836         intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
 837
 838         dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
 839         dev_priv->gtt.gtt_clear_range = i915_ggtt_clear_range;
 840         dev_priv->gtt.gtt_insert_entries = i915_ggtt_insert_entries;
 841
 842         return 0;
 843 }
 844
 845 static void i915_gmch_remove(struct drm_device *dev)
 846 {
 847         intel_gmch_remove();
 848 }
 849
 850 int i915_gem_gtt_init(struct drm_device *dev)
 851 {
 852         struct drm_i915_private *dev_priv = dev->dev_private;
 853         struct i915_gtt *gtt = &dev_priv->gtt;
 854         int ret;
 855
 856         if (INTEL_INFO(dev)->gen <= 5) {
 857                 dev_priv->gtt.gtt_probe = i915_gmch_probe;
 858                 dev_priv->gtt.gtt_remove = i915_gmch_remove;
 859         } else {
 860                 dev_priv->gtt.gtt_probe = gen6_gmch_probe;
 861                 dev_priv->gtt.gtt_remove = gen6_gmch_remove;
 862                 if (IS_HASWELL(dev)) {
 863                         dev_priv->gtt.pte_encode = hsw_pte_encode;
 864                 } else if (IS_VALLEYVIEW(dev)) {
 865                         dev_priv->gtt.pte_encode = byt_pte_encode;
 866                 } else {
 867                         dev_priv->gtt.pte_encode = gen6_pte_encode;
 868                 }
 869         }
 870
 871         ret = dev_priv->gtt.gtt_probe(dev, &dev_priv->gtt.total,
 872                                      &dev_priv->gtt.stolen_size,
 873                                      &gtt->mappable_base,
 874                                      &gtt->mappable_end);
 875         if (ret)
 876                 return ret;
 877
 878         /* GMADR is the PCI mmio aperture into the global GTT. */
 879         DRM_INFO("Memory usable by graphics device = %zdM\n",
 880                  dev_priv->gtt.total >> 20);
 881         DRM_DEBUG_DRIVER("GMADR size = %ldM\n",
 882                          dev_priv->gtt.mappable_end >> 20);
 883         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n",
 884                          dev_priv->gtt.stolen_size >> 20);
 885
 886         return 0;
 887 }