2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
28 #include <linux/string.h>
29 #include <linux/bitops.h>
31 #include <drm/i915_drm.h>
35 * DOC: buffer object tiling
37 * i915_gem_set_tiling() and i915_gem_get_tiling() is the userspace interface to
38 * declare fence register requirements.
40 * In principle GEM doesn't care at all about the internal data layout of an
41 * object, and hence it also doesn't care about tiling or swizzling. There's two
44 * - For X and Y tiling the hardware provides detilers for CPU access, so called
45 * fences. Since there's only a limited amount of them the kernel must manage
46 * these, and therefore userspace must tell the kernel the object tiling if it
47 * wants to use fences for detiling.
48 * - On gen3 and gen4 platforms have a swizzling pattern for tiled objects which
49 * depends upon the physical page frame number. When swapping such objects the
50 * page frame number might change and the kernel must be able to fix this up
51 * and hence now the tiling. Note that on a subset of platforms with
52 * asymmetric memory channel population the swizzling pattern changes in an
53 * unknown way, and for those the kernel simply forbids swapping completely.
55 * Since neither of this applies for new tiling layouts on modern platforms like
56 * W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled.
57 * Anything else can be handled in userspace entirely without the kernel's
61 /* Check pitch constriants for all chips & tiling formats */
63 i915_tiling_ok(struct drm_device
*dev
, int stride
, int size
, int tiling_mode
)
67 /* Linear is always fine */
68 if (tiling_mode
== I915_TILING_NONE
)
71 if (tiling_mode
> I915_TILING_LAST
)
75 (tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
)))
80 /* check maximum stride & object size */
81 /* i965+ stores the end address of the gtt mapping in the fence
82 * reg, so dont bother to check the size */
83 if (INTEL_INFO(dev
)->gen
>= 7) {
84 if (stride
/ 128 > GEN7_FENCE_MAX_PITCH_VAL
)
86 } else if (INTEL_INFO(dev
)->gen
>= 4) {
87 if (stride
/ 128 > I965_FENCE_MAX_PITCH_VAL
)
94 if (size
> I830_FENCE_MAX_SIZE_VAL
<< 20)
97 if (size
> I830_FENCE_MAX_SIZE_VAL
<< 19)
102 if (stride
< tile_width
)
105 /* 965+ just needs multiples of tile width */
106 if (INTEL_INFO(dev
)->gen
>= 4) {
107 if (stride
& (tile_width
- 1))
112 /* Pre-965 needs power of two tile widths */
113 if (stride
& (stride
- 1))
119 /* Make the current GTT allocation valid for the change in tiling. */
121 i915_gem_object_fence_prepare(struct drm_i915_gem_object
*obj
, int tiling_mode
)
123 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
124 struct i915_vma
*vma
;
127 if (tiling_mode
== I915_TILING_NONE
)
130 if (INTEL_GEN(dev_priv
) >= 4)
133 vma
= i915_gem_obj_to_ggtt(obj
);
137 if (!obj
->map_and_fenceable
)
140 if (IS_GEN3(dev_priv
)) {
141 if (vma
->node
.start
& ~I915_FENCE_START_MASK
)
144 if (vma
->node
.start
& ~I830_FENCE_START_MASK
)
148 size
= i915_gem_get_ggtt_size(dev_priv
, obj
->base
.size
, tiling_mode
);
149 if (vma
->node
.size
< size
)
152 if (vma
->node
.start
& (size
- 1))
158 return i915_vma_unbind(vma
);
162 * i915_gem_set_tiling - IOCTL handler to set tiling mode
164 * @data: data pointer for the ioctl
165 * @file: DRM file for the ioctl call
167 * Sets the tiling mode of an object, returning the required swizzling of
168 * bit 6 of addresses in the object.
170 * Called by the user via ioctl.
173 * Zero on success, negative errno on failure.
176 i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
177 struct drm_file
*file
)
179 struct drm_i915_gem_set_tiling
*args
= data
;
180 struct drm_i915_private
*dev_priv
= to_i915(dev
);
181 struct drm_i915_gem_object
*obj
;
184 /* Make sure we don't cross-contaminate obj->tiling_and_stride */
185 BUILD_BUG_ON(I915_TILING_LAST
& STRIDE_MASK
);
187 obj
= i915_gem_object_lookup(file
, args
->handle
);
191 if (!i915_tiling_ok(dev
,
192 args
->stride
, obj
->base
.size
, args
->tiling_mode
)) {
193 i915_gem_object_put_unlocked(obj
);
197 intel_runtime_pm_get(dev_priv
);
199 mutex_lock(&dev
->struct_mutex
);
200 if (obj
->pin_display
|| obj
->framebuffer_references
) {
205 if (args
->tiling_mode
== I915_TILING_NONE
) {
206 args
->swizzle_mode
= I915_BIT_6_SWIZZLE_NONE
;
209 if (args
->tiling_mode
== I915_TILING_X
)
210 args
->swizzle_mode
= dev_priv
->mm
.bit_6_swizzle_x
;
212 args
->swizzle_mode
= dev_priv
->mm
.bit_6_swizzle_y
;
214 /* Hide bit 17 swizzling from the user. This prevents old Mesa
215 * from aborting the application on sw fallbacks to bit 17,
216 * and we use the pread/pwrite bit17 paths to swizzle for it.
217 * If there was a user that was relying on the swizzle
218 * information for drm_intel_bo_map()ed reads/writes this would
219 * break it, but we don't have any of those.
221 if (args
->swizzle_mode
== I915_BIT_6_SWIZZLE_9_17
)
222 args
->swizzle_mode
= I915_BIT_6_SWIZZLE_9
;
223 if (args
->swizzle_mode
== I915_BIT_6_SWIZZLE_9_10_17
)
224 args
->swizzle_mode
= I915_BIT_6_SWIZZLE_9_10
;
226 /* If we can't handle the swizzling, make it untiled. */
227 if (args
->swizzle_mode
== I915_BIT_6_SWIZZLE_UNKNOWN
) {
228 args
->tiling_mode
= I915_TILING_NONE
;
229 args
->swizzle_mode
= I915_BIT_6_SWIZZLE_NONE
;
234 if (args
->tiling_mode
!= i915_gem_object_get_tiling(obj
) ||
235 args
->stride
!= i915_gem_object_get_stride(obj
)) {
236 /* We need to rebind the object if its current allocation
237 * no longer meets the alignment restrictions for its new
238 * tiling mode. Otherwise we can just leave it alone, but
239 * need to ensure that any fence register is updated before
240 * the next fenced (either through the GTT or by the BLT unit
241 * on older GPUs) access.
243 * After updating the tiling parameters, we then flag whether
244 * we need to update an associated fence register. Note this
245 * has to also include the unfenced register the GPU uses
246 * whilst executing a fenced command for an untiled object.
249 err
= i915_gem_object_fence_prepare(obj
, args
->tiling_mode
);
252 obj
->madv
== I915_MADV_WILLNEED
&&
253 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
254 if (args
->tiling_mode
== I915_TILING_NONE
)
255 i915_gem_object_unpin_pages(obj
);
256 if (!i915_gem_object_is_tiled(obj
))
257 i915_gem_object_pin_pages(obj
);
261 !i915_gem_active_is_idle(&obj
->last_fence
,
262 &dev
->struct_mutex
) ||
263 obj
->fence_reg
!= I915_FENCE_REG_NONE
;
265 obj
->tiling_and_stride
=
266 args
->stride
| args
->tiling_mode
;
268 /* Force the fence to be reacquired for GTT access */
269 i915_gem_release_mmap(obj
);
272 /* we have to maintain this existing ABI... */
273 args
->stride
= i915_gem_object_get_stride(obj
);
274 args
->tiling_mode
= i915_gem_object_get_tiling(obj
);
276 /* Try to preallocate memory required to save swizzling on put-pages */
277 if (i915_gem_object_needs_bit17_swizzle(obj
)) {
278 if (obj
->bit_17
== NULL
) {
279 obj
->bit_17
= kcalloc(BITS_TO_LONGS(obj
->base
.size
>> PAGE_SHIFT
),
280 sizeof(long), GFP_KERNEL
);
288 i915_gem_object_put(obj
);
289 mutex_unlock(&dev
->struct_mutex
);
291 intel_runtime_pm_put(dev_priv
);
297 * i915_gem_get_tiling - IOCTL handler to get tiling mode
299 * @data: data pointer for the ioctl
300 * @file: DRM file for the ioctl call
302 * Returns the current tiling mode and required bit 6 swizzling for the object.
304 * Called by the user via ioctl.
307 * Zero on success, negative errno on failure.
310 i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
311 struct drm_file
*file
)
313 struct drm_i915_gem_get_tiling
*args
= data
;
314 struct drm_i915_private
*dev_priv
= to_i915(dev
);
315 struct drm_i915_gem_object
*obj
;
317 obj
= i915_gem_object_lookup(file
, args
->handle
);
321 args
->tiling_mode
= READ_ONCE(obj
->tiling_and_stride
) & TILING_MASK
;
322 switch (args
->tiling_mode
) {
324 args
->swizzle_mode
= dev_priv
->mm
.bit_6_swizzle_x
;
327 args
->swizzle_mode
= dev_priv
->mm
.bit_6_swizzle_y
;
329 case I915_TILING_NONE
:
330 args
->swizzle_mode
= I915_BIT_6_SWIZZLE_NONE
;
333 DRM_ERROR("unknown tiling mode\n");
336 /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
337 if (dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
338 args
->phys_swizzle_mode
= I915_BIT_6_SWIZZLE_UNKNOWN
;
340 args
->phys_swizzle_mode
= args
->swizzle_mode
;
341 if (args
->swizzle_mode
== I915_BIT_6_SWIZZLE_9_17
)
342 args
->swizzle_mode
= I915_BIT_6_SWIZZLE_9
;
343 if (args
->swizzle_mode
== I915_BIT_6_SWIZZLE_9_10_17
)
344 args
->swizzle_mode
= I915_BIT_6_SWIZZLE_9_10
;
346 i915_gem_object_put_unlocked(obj
);