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[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
34 #include <drm/drmP.h>
35 #include <drm/i915_drm.h>
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "intel_drv.h"
39
40 static const u32 hpd_ibx[] = {
41 [HPD_CRT] = SDE_CRT_HOTPLUG,
42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
46 };
47
48 static const u32 hpd_cpt[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
54 };
55
56 static const u32 hpd_mask_i915[] = {
57 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
63 };
64
65 static const u32 hpd_status_g4x[] = {
66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
72 };
73
74 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
81 };
82
83 /* For display hotplug interrupt */
84 static void
85 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
86 {
87 assert_spin_locked(&dev_priv->irq_lock);
88
89 if (dev_priv->pc8.irqs_disabled) {
90 WARN(1, "IRQs disabled\n");
91 dev_priv->pc8.regsave.deimr &= ~mask;
92 return;
93 }
94
95 if ((dev_priv->irq_mask & mask) != 0) {
96 dev_priv->irq_mask &= ~mask;
97 I915_WRITE(DEIMR, dev_priv->irq_mask);
98 POSTING_READ(DEIMR);
99 }
100 }
101
102 static void
103 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
104 {
105 assert_spin_locked(&dev_priv->irq_lock);
106
107 if (dev_priv->pc8.irqs_disabled) {
108 WARN(1, "IRQs disabled\n");
109 dev_priv->pc8.regsave.deimr |= mask;
110 return;
111 }
112
113 if ((dev_priv->irq_mask & mask) != mask) {
114 dev_priv->irq_mask |= mask;
115 I915_WRITE(DEIMR, dev_priv->irq_mask);
116 POSTING_READ(DEIMR);
117 }
118 }
119
120 /**
121 * ilk_update_gt_irq - update GTIMR
122 * @dev_priv: driver private
123 * @interrupt_mask: mask of interrupt bits to update
124 * @enabled_irq_mask: mask of interrupt bits to enable
125 */
126 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
127 uint32_t interrupt_mask,
128 uint32_t enabled_irq_mask)
129 {
130 assert_spin_locked(&dev_priv->irq_lock);
131
132 if (dev_priv->pc8.irqs_disabled) {
133 WARN(1, "IRQs disabled\n");
134 dev_priv->pc8.regsave.gtimr &= ~interrupt_mask;
135 dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask &
136 interrupt_mask);
137 return;
138 }
139
140 dev_priv->gt_irq_mask &= ~interrupt_mask;
141 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
142 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
143 POSTING_READ(GTIMR);
144 }
145
146 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
147 {
148 ilk_update_gt_irq(dev_priv, mask, mask);
149 }
150
151 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
152 {
153 ilk_update_gt_irq(dev_priv, mask, 0);
154 }
155
156 /**
157 * snb_update_pm_irq - update GEN6_PMIMR
158 * @dev_priv: driver private
159 * @interrupt_mask: mask of interrupt bits to update
160 * @enabled_irq_mask: mask of interrupt bits to enable
161 */
162 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
163 uint32_t interrupt_mask,
164 uint32_t enabled_irq_mask)
165 {
166 uint32_t new_val;
167
168 assert_spin_locked(&dev_priv->irq_lock);
169
170 if (dev_priv->pc8.irqs_disabled) {
171 WARN(1, "IRQs disabled\n");
172 dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask;
173 dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask &
174 interrupt_mask);
175 return;
176 }
177
178 new_val = dev_priv->pm_irq_mask;
179 new_val &= ~interrupt_mask;
180 new_val |= (~enabled_irq_mask & interrupt_mask);
181
182 if (new_val != dev_priv->pm_irq_mask) {
183 dev_priv->pm_irq_mask = new_val;
184 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
185 POSTING_READ(GEN6_PMIMR);
186 }
187 }
188
189 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
190 {
191 snb_update_pm_irq(dev_priv, mask, mask);
192 }
193
194 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
195 {
196 snb_update_pm_irq(dev_priv, mask, 0);
197 }
198
199 static bool ivb_can_enable_err_int(struct drm_device *dev)
200 {
201 struct drm_i915_private *dev_priv = dev->dev_private;
202 struct intel_crtc *crtc;
203 enum pipe pipe;
204
205 assert_spin_locked(&dev_priv->irq_lock);
206
207 for_each_pipe(pipe) {
208 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
209
210 if (crtc->cpu_fifo_underrun_disabled)
211 return false;
212 }
213
214 return true;
215 }
216
217 static bool cpt_can_enable_serr_int(struct drm_device *dev)
218 {
219 struct drm_i915_private *dev_priv = dev->dev_private;
220 enum pipe pipe;
221 struct intel_crtc *crtc;
222
223 assert_spin_locked(&dev_priv->irq_lock);
224
225 for_each_pipe(pipe) {
226 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
227
228 if (crtc->pch_fifo_underrun_disabled)
229 return false;
230 }
231
232 return true;
233 }
234
235 static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe)
236 {
237 struct drm_i915_private *dev_priv = dev->dev_private;
238 u32 reg = PIPESTAT(pipe);
239 u32 pipestat = I915_READ(reg) & 0x7fff0000;
240
241 assert_spin_locked(&dev_priv->irq_lock);
242
243 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
244 POSTING_READ(reg);
245 }
246
247 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
248 enum pipe pipe, bool enable)
249 {
250 struct drm_i915_private *dev_priv = dev->dev_private;
251 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
252 DE_PIPEB_FIFO_UNDERRUN;
253
254 if (enable)
255 ironlake_enable_display_irq(dev_priv, bit);
256 else
257 ironlake_disable_display_irq(dev_priv, bit);
258 }
259
260 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
261 enum pipe pipe, bool enable)
262 {
263 struct drm_i915_private *dev_priv = dev->dev_private;
264 if (enable) {
265 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
266
267 if (!ivb_can_enable_err_int(dev))
268 return;
269
270 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
271 } else {
272 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
273
274 /* Change the state _after_ we've read out the current one. */
275 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
276
277 if (!was_enabled &&
278 (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
279 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
280 pipe_name(pipe));
281 }
282 }
283 }
284
285 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
286 enum pipe pipe, bool enable)
287 {
288 struct drm_i915_private *dev_priv = dev->dev_private;
289
290 assert_spin_locked(&dev_priv->irq_lock);
291
292 if (enable)
293 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
294 else
295 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
296 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
297 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
298 }
299
300 /**
301 * ibx_display_interrupt_update - update SDEIMR
302 * @dev_priv: driver private
303 * @interrupt_mask: mask of interrupt bits to update
304 * @enabled_irq_mask: mask of interrupt bits to enable
305 */
306 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
307 uint32_t interrupt_mask,
308 uint32_t enabled_irq_mask)
309 {
310 uint32_t sdeimr = I915_READ(SDEIMR);
311 sdeimr &= ~interrupt_mask;
312 sdeimr |= (~enabled_irq_mask & interrupt_mask);
313
314 assert_spin_locked(&dev_priv->irq_lock);
315
316 if (dev_priv->pc8.irqs_disabled &&
317 (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
318 WARN(1, "IRQs disabled\n");
319 dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask;
320 dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask &
321 interrupt_mask);
322 return;
323 }
324
325 I915_WRITE(SDEIMR, sdeimr);
326 POSTING_READ(SDEIMR);
327 }
328 #define ibx_enable_display_interrupt(dev_priv, bits) \
329 ibx_display_interrupt_update((dev_priv), (bits), (bits))
330 #define ibx_disable_display_interrupt(dev_priv, bits) \
331 ibx_display_interrupt_update((dev_priv), (bits), 0)
332
333 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
334 enum transcoder pch_transcoder,
335 bool enable)
336 {
337 struct drm_i915_private *dev_priv = dev->dev_private;
338 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
339 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
340
341 if (enable)
342 ibx_enable_display_interrupt(dev_priv, bit);
343 else
344 ibx_disable_display_interrupt(dev_priv, bit);
345 }
346
347 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
348 enum transcoder pch_transcoder,
349 bool enable)
350 {
351 struct drm_i915_private *dev_priv = dev->dev_private;
352
353 if (enable) {
354 I915_WRITE(SERR_INT,
355 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
356
357 if (!cpt_can_enable_serr_int(dev))
358 return;
359
360 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
361 } else {
362 uint32_t tmp = I915_READ(SERR_INT);
363 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
364
365 /* Change the state _after_ we've read out the current one. */
366 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
367
368 if (!was_enabled &&
369 (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
370 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
371 transcoder_name(pch_transcoder));
372 }
373 }
374 }
375
376 /**
377 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
378 * @dev: drm device
379 * @pipe: pipe
380 * @enable: true if we want to report FIFO underrun errors, false otherwise
381 *
382 * This function makes us disable or enable CPU fifo underruns for a specific
383 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
384 * reporting for one pipe may also disable all the other CPU error interruts for
385 * the other pipes, due to the fact that there's just one interrupt mask/enable
386 * bit for all the pipes.
387 *
388 * Returns the previous state of underrun reporting.
389 */
390 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
391 enum pipe pipe, bool enable)
392 {
393 struct drm_i915_private *dev_priv = dev->dev_private;
394 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
396 unsigned long flags;
397 bool ret;
398
399 spin_lock_irqsave(&dev_priv->irq_lock, flags);
400
401 ret = !intel_crtc->cpu_fifo_underrun_disabled;
402
403 if (enable == ret)
404 goto done;
405
406 intel_crtc->cpu_fifo_underrun_disabled = !enable;
407
408 if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)))
409 i9xx_clear_fifo_underrun(dev, pipe);
410 else if (IS_GEN5(dev) || IS_GEN6(dev))
411 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
412 else if (IS_GEN7(dev))
413 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
414 else if (IS_GEN8(dev))
415 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
416
417 done:
418 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
419 return ret;
420 }
421
422 /**
423 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
424 * @dev: drm device
425 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
426 * @enable: true if we want to report FIFO underrun errors, false otherwise
427 *
428 * This function makes us disable or enable PCH fifo underruns for a specific
429 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
430 * underrun reporting for one transcoder may also disable all the other PCH
431 * error interruts for the other transcoders, due to the fact that there's just
432 * one interrupt mask/enable bit for all the transcoders.
433 *
434 * Returns the previous state of underrun reporting.
435 */
436 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
437 enum transcoder pch_transcoder,
438 bool enable)
439 {
440 struct drm_i915_private *dev_priv = dev->dev_private;
441 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
443 unsigned long flags;
444 bool ret;
445
446 /*
447 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
448 * has only one pch transcoder A that all pipes can use. To avoid racy
449 * pch transcoder -> pipe lookups from interrupt code simply store the
450 * underrun statistics in crtc A. Since we never expose this anywhere
451 * nor use it outside of the fifo underrun code here using the "wrong"
452 * crtc on LPT won't cause issues.
453 */
454
455 spin_lock_irqsave(&dev_priv->irq_lock, flags);
456
457 ret = !intel_crtc->pch_fifo_underrun_disabled;
458
459 if (enable == ret)
460 goto done;
461
462 intel_crtc->pch_fifo_underrun_disabled = !enable;
463
464 if (HAS_PCH_IBX(dev))
465 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
466 else
467 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
468
469 done:
470 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
471 return ret;
472 }
473
474
475 void
476 i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
477 {
478 u32 reg = PIPESTAT(pipe);
479 u32 pipestat = I915_READ(reg) & 0x7fff0000;
480
481 assert_spin_locked(&dev_priv->irq_lock);
482
483 if ((pipestat & mask) == mask)
484 return;
485
486 /* Enable the interrupt, clear any pending status */
487 pipestat |= mask | (mask >> 16);
488 I915_WRITE(reg, pipestat);
489 POSTING_READ(reg);
490 }
491
492 void
493 i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
494 {
495 u32 reg = PIPESTAT(pipe);
496 u32 pipestat = I915_READ(reg) & 0x7fff0000;
497
498 assert_spin_locked(&dev_priv->irq_lock);
499
500 if ((pipestat & mask) == 0)
501 return;
502
503 pipestat &= ~mask;
504 I915_WRITE(reg, pipestat);
505 POSTING_READ(reg);
506 }
507
508 /**
509 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
510 */
511 static void i915_enable_asle_pipestat(struct drm_device *dev)
512 {
513 drm_i915_private_t *dev_priv = dev->dev_private;
514 unsigned long irqflags;
515
516 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
517 return;
518
519 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
520
521 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_ENABLE);
522 if (INTEL_INFO(dev)->gen >= 4)
523 i915_enable_pipestat(dev_priv, PIPE_A,
524 PIPE_LEGACY_BLC_EVENT_ENABLE);
525
526 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
527 }
528
529 /**
530 * i915_pipe_enabled - check if a pipe is enabled
531 * @dev: DRM device
532 * @pipe: pipe to check
533 *
534 * Reading certain registers when the pipe is disabled can hang the chip.
535 * Use this routine to make sure the PLL is running and the pipe is active
536 * before reading such registers if unsure.
537 */
538 static int
539 i915_pipe_enabled(struct drm_device *dev, int pipe)
540 {
541 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
542
543 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
544 /* Locking is horribly broken here, but whatever. */
545 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
546 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
547
548 return intel_crtc->active;
549 } else {
550 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
551 }
552 }
553
554 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
555 {
556 /* Gen2 doesn't have a hardware frame counter */
557 return 0;
558 }
559
560 /* Called from drm generic code, passed a 'crtc', which
561 * we use as a pipe index
562 */
563 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
564 {
565 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
566 unsigned long high_frame;
567 unsigned long low_frame;
568 u32 high1, high2, low, pixel, vbl_start;
569
570 if (!i915_pipe_enabled(dev, pipe)) {
571 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
572 "pipe %c\n", pipe_name(pipe));
573 return 0;
574 }
575
576 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
577 struct intel_crtc *intel_crtc =
578 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
579 const struct drm_display_mode *mode =
580 &intel_crtc->config.adjusted_mode;
581
582 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
583 } else {
584 enum transcoder cpu_transcoder =
585 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
586 u32 htotal;
587
588 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
589 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
590
591 vbl_start *= htotal;
592 }
593
594 high_frame = PIPEFRAME(pipe);
595 low_frame = PIPEFRAMEPIXEL(pipe);
596
597 /*
598 * High & low register fields aren't synchronized, so make sure
599 * we get a low value that's stable across two reads of the high
600 * register.
601 */
602 do {
603 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
604 low = I915_READ(low_frame);
605 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
606 } while (high1 != high2);
607
608 high1 >>= PIPE_FRAME_HIGH_SHIFT;
609 pixel = low & PIPE_PIXEL_MASK;
610 low >>= PIPE_FRAME_LOW_SHIFT;
611
612 /*
613 * The frame counter increments at beginning of active.
614 * Cook up a vblank counter by also checking the pixel
615 * counter against vblank start.
616 */
617 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
618 }
619
620 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
621 {
622 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
623 int reg = PIPE_FRMCOUNT_GM45(pipe);
624
625 if (!i915_pipe_enabled(dev, pipe)) {
626 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
627 "pipe %c\n", pipe_name(pipe));
628 return 0;
629 }
630
631 return I915_READ(reg);
632 }
633
634 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
635 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
636 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
637
638 static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
639 {
640 struct drm_i915_private *dev_priv = dev->dev_private;
641 uint32_t status;
642
643 if (INTEL_INFO(dev)->gen < 7) {
644 status = pipe == PIPE_A ?
645 DE_PIPEA_VBLANK :
646 DE_PIPEB_VBLANK;
647 } else {
648 switch (pipe) {
649 default:
650 case PIPE_A:
651 status = DE_PIPEA_VBLANK_IVB;
652 break;
653 case PIPE_B:
654 status = DE_PIPEB_VBLANK_IVB;
655 break;
656 case PIPE_C:
657 status = DE_PIPEC_VBLANK_IVB;
658 break;
659 }
660 }
661
662 return __raw_i915_read32(dev_priv, DEISR) & status;
663 }
664
665 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
666 unsigned int flags, int *vpos, int *hpos,
667 ktime_t *stime, ktime_t *etime)
668 {
669 struct drm_i915_private *dev_priv = dev->dev_private;
670 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
672 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
673 int position;
674 int vbl_start, vbl_end, htotal, vtotal;
675 bool in_vbl = true;
676 int ret = 0;
677 unsigned long irqflags;
678
679 if (!intel_crtc->active) {
680 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
681 "pipe %c\n", pipe_name(pipe));
682 return 0;
683 }
684
685 htotal = mode->crtc_htotal;
686 vtotal = mode->crtc_vtotal;
687 vbl_start = mode->crtc_vblank_start;
688 vbl_end = mode->crtc_vblank_end;
689
690 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
691 vbl_start = DIV_ROUND_UP(vbl_start, 2);
692 vbl_end /= 2;
693 vtotal /= 2;
694 }
695
696 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
697
698 /*
699 * Lock uncore.lock, as we will do multiple timing critical raw
700 * register reads, potentially with preemption disabled, so the
701 * following code must not block on uncore.lock.
702 */
703 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
704
705 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
706
707 /* Get optional system timestamp before query. */
708 if (stime)
709 *stime = ktime_get();
710
711 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
712 /* No obvious pixelcount register. Only query vertical
713 * scanout position from Display scan line register.
714 */
715 if (IS_GEN2(dev))
716 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
717 else
718 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
719
720 if (HAS_PCH_SPLIT(dev)) {
721 /*
722 * The scanline counter increments at the leading edge
723 * of hsync, ie. it completely misses the active portion
724 * of the line. Fix up the counter at both edges of vblank
725 * to get a more accurate picture whether we're in vblank
726 * or not.
727 */
728 in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
729 if ((in_vbl && position == vbl_start - 1) ||
730 (!in_vbl && position == vbl_end - 1))
731 position = (position + 1) % vtotal;
732 } else {
733 /*
734 * ISR vblank status bits don't work the way we'd want
735 * them to work on non-PCH platforms (for
736 * ilk_pipe_in_vblank_locked()), and there doesn't
737 * appear any other way to determine if we're currently
738 * in vblank.
739 *
740 * Instead let's assume that we're already in vblank if
741 * we got called from the vblank interrupt and the
742 * scanline counter value indicates that we're on the
743 * line just prior to vblank start. This should result
744 * in the correct answer, unless the vblank interrupt
745 * delivery really got delayed for almost exactly one
746 * full frame/field.
747 */
748 if (flags & DRM_CALLED_FROM_VBLIRQ &&
749 position == vbl_start - 1) {
750 position = (position + 1) % vtotal;
751
752 /* Signal this correction as "applied". */
753 ret |= 0x8;
754 }
755 }
756 } else {
757 /* Have access to pixelcount since start of frame.
758 * We can split this into vertical and horizontal
759 * scanout position.
760 */
761 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
762
763 /* convert to pixel counts */
764 vbl_start *= htotal;
765 vbl_end *= htotal;
766 vtotal *= htotal;
767 }
768
769 /* Get optional system timestamp after query. */
770 if (etime)
771 *etime = ktime_get();
772
773 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
774
775 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
776
777 in_vbl = position >= vbl_start && position < vbl_end;
778
779 /*
780 * While in vblank, position will be negative
781 * counting up towards 0 at vbl_end. And outside
782 * vblank, position will be positive counting
783 * up since vbl_end.
784 */
785 if (position >= vbl_start)
786 position -= vbl_end;
787 else
788 position += vtotal - vbl_end;
789
790 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
791 *vpos = position;
792 *hpos = 0;
793 } else {
794 *vpos = position / htotal;
795 *hpos = position - (*vpos * htotal);
796 }
797
798 /* In vblank? */
799 if (in_vbl)
800 ret |= DRM_SCANOUTPOS_INVBL;
801
802 return ret;
803 }
804
805 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
806 int *max_error,
807 struct timeval *vblank_time,
808 unsigned flags)
809 {
810 struct drm_crtc *crtc;
811
812 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
813 DRM_ERROR("Invalid crtc %d\n", pipe);
814 return -EINVAL;
815 }
816
817 /* Get drm_crtc to timestamp: */
818 crtc = intel_get_crtc_for_pipe(dev, pipe);
819 if (crtc == NULL) {
820 DRM_ERROR("Invalid crtc %d\n", pipe);
821 return -EINVAL;
822 }
823
824 if (!crtc->enabled) {
825 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
826 return -EBUSY;
827 }
828
829 /* Helper routine in DRM core does all the work: */
830 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
831 vblank_time, flags,
832 crtc,
833 &to_intel_crtc(crtc)->config.adjusted_mode);
834 }
835
836 static bool intel_hpd_irq_event(struct drm_device *dev,
837 struct drm_connector *connector)
838 {
839 enum drm_connector_status old_status;
840
841 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
842 old_status = connector->status;
843
844 connector->status = connector->funcs->detect(connector, false);
845 if (old_status == connector->status)
846 return false;
847
848 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
849 connector->base.id,
850 drm_get_connector_name(connector),
851 drm_get_connector_status_name(old_status),
852 drm_get_connector_status_name(connector->status));
853
854 return true;
855 }
856
857 /*
858 * Handle hotplug events outside the interrupt handler proper.
859 */
860 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
861
862 static void i915_hotplug_work_func(struct work_struct *work)
863 {
864 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
865 hotplug_work);
866 struct drm_device *dev = dev_priv->dev;
867 struct drm_mode_config *mode_config = &dev->mode_config;
868 struct intel_connector *intel_connector;
869 struct intel_encoder *intel_encoder;
870 struct drm_connector *connector;
871 unsigned long irqflags;
872 bool hpd_disabled = false;
873 bool changed = false;
874 u32 hpd_event_bits;
875
876 /* HPD irq before everything is fully set up. */
877 if (!dev_priv->enable_hotplug_processing)
878 return;
879
880 mutex_lock(&mode_config->mutex);
881 DRM_DEBUG_KMS("running encoder hotplug functions\n");
882
883 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
884
885 hpd_event_bits = dev_priv->hpd_event_bits;
886 dev_priv->hpd_event_bits = 0;
887 list_for_each_entry(connector, &mode_config->connector_list, head) {
888 intel_connector = to_intel_connector(connector);
889 intel_encoder = intel_connector->encoder;
890 if (intel_encoder->hpd_pin > HPD_NONE &&
891 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
892 connector->polled == DRM_CONNECTOR_POLL_HPD) {
893 DRM_INFO("HPD interrupt storm detected on connector %s: "
894 "switching from hotplug detection to polling\n",
895 drm_get_connector_name(connector));
896 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
897 connector->polled = DRM_CONNECTOR_POLL_CONNECT
898 | DRM_CONNECTOR_POLL_DISCONNECT;
899 hpd_disabled = true;
900 }
901 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
902 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
903 drm_get_connector_name(connector), intel_encoder->hpd_pin);
904 }
905 }
906 /* if there were no outputs to poll, poll was disabled,
907 * therefore make sure it's enabled when disabling HPD on
908 * some connectors */
909 if (hpd_disabled) {
910 drm_kms_helper_poll_enable(dev);
911 mod_timer(&dev_priv->hotplug_reenable_timer,
912 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
913 }
914
915 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
916
917 list_for_each_entry(connector, &mode_config->connector_list, head) {
918 intel_connector = to_intel_connector(connector);
919 intel_encoder = intel_connector->encoder;
920 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
921 if (intel_encoder->hot_plug)
922 intel_encoder->hot_plug(intel_encoder);
923 if (intel_hpd_irq_event(dev, connector))
924 changed = true;
925 }
926 }
927 mutex_unlock(&mode_config->mutex);
928
929 if (changed)
930 drm_kms_helper_hotplug_event(dev);
931 }
932
933 static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv)
934 {
935 del_timer_sync(&dev_priv->hotplug_reenable_timer);
936 }
937
938 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
939 {
940 drm_i915_private_t *dev_priv = dev->dev_private;
941 u32 busy_up, busy_down, max_avg, min_avg;
942 u8 new_delay;
943
944 spin_lock(&mchdev_lock);
945
946 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
947
948 new_delay = dev_priv->ips.cur_delay;
949
950 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
951 busy_up = I915_READ(RCPREVBSYTUPAVG);
952 busy_down = I915_READ(RCPREVBSYTDNAVG);
953 max_avg = I915_READ(RCBMAXAVG);
954 min_avg = I915_READ(RCBMINAVG);
955
956 /* Handle RCS change request from hw */
957 if (busy_up > max_avg) {
958 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
959 new_delay = dev_priv->ips.cur_delay - 1;
960 if (new_delay < dev_priv->ips.max_delay)
961 new_delay = dev_priv->ips.max_delay;
962 } else if (busy_down < min_avg) {
963 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
964 new_delay = dev_priv->ips.cur_delay + 1;
965 if (new_delay > dev_priv->ips.min_delay)
966 new_delay = dev_priv->ips.min_delay;
967 }
968
969 if (ironlake_set_drps(dev, new_delay))
970 dev_priv->ips.cur_delay = new_delay;
971
972 spin_unlock(&mchdev_lock);
973
974 return;
975 }
976
977 static void notify_ring(struct drm_device *dev,
978 struct intel_ring_buffer *ring)
979 {
980 if (ring->obj == NULL)
981 return;
982
983 trace_i915_gem_request_complete(ring);
984
985 wake_up_all(&ring->irq_queue);
986 i915_queue_hangcheck(dev);
987 }
988
989 static void gen6_pm_rps_work(struct work_struct *work)
990 {
991 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
992 rps.work);
993 u32 pm_iir;
994 int new_delay, adj;
995
996 spin_lock_irq(&dev_priv->irq_lock);
997 pm_iir = dev_priv->rps.pm_iir;
998 dev_priv->rps.pm_iir = 0;
999 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
1000 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
1001 spin_unlock_irq(&dev_priv->irq_lock);
1002
1003 /* Make sure we didn't queue anything we're not going to process. */
1004 WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS);
1005
1006 if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
1007 return;
1008
1009 mutex_lock(&dev_priv->rps.hw_lock);
1010
1011 adj = dev_priv->rps.last_adj;
1012 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1013 if (adj > 0)
1014 adj *= 2;
1015 else
1016 adj = 1;
1017 new_delay = dev_priv->rps.cur_delay + adj;
1018
1019 /*
1020 * For better performance, jump directly
1021 * to RPe if we're below it.
1022 */
1023 if (new_delay < dev_priv->rps.rpe_delay)
1024 new_delay = dev_priv->rps.rpe_delay;
1025 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1026 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
1027 new_delay = dev_priv->rps.rpe_delay;
1028 else
1029 new_delay = dev_priv->rps.min_delay;
1030 adj = 0;
1031 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1032 if (adj < 0)
1033 adj *= 2;
1034 else
1035 adj = -1;
1036 new_delay = dev_priv->rps.cur_delay + adj;
1037 } else { /* unknown event */
1038 new_delay = dev_priv->rps.cur_delay;
1039 }
1040
1041 /* sysfs frequency interfaces may have snuck in while servicing the
1042 * interrupt
1043 */
1044 new_delay = clamp_t(int, new_delay,
1045 dev_priv->rps.min_delay, dev_priv->rps.max_delay);
1046 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay;
1047
1048 if (IS_VALLEYVIEW(dev_priv->dev))
1049 valleyview_set_rps(dev_priv->dev, new_delay);
1050 else
1051 gen6_set_rps(dev_priv->dev, new_delay);
1052
1053 mutex_unlock(&dev_priv->rps.hw_lock);
1054 }
1055
1056
1057 /**
1058 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1059 * occurred.
1060 * @work: workqueue struct
1061 *
1062 * Doesn't actually do anything except notify userspace. As a consequence of
1063 * this event, userspace should try to remap the bad rows since statistically
1064 * it is likely the same row is more likely to go bad again.
1065 */
1066 static void ivybridge_parity_work(struct work_struct *work)
1067 {
1068 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
1069 l3_parity.error_work);
1070 u32 error_status, row, bank, subbank;
1071 char *parity_event[6];
1072 uint32_t misccpctl;
1073 unsigned long flags;
1074 uint8_t slice = 0;
1075
1076 /* We must turn off DOP level clock gating to access the L3 registers.
1077 * In order to prevent a get/put style interface, acquire struct mutex
1078 * any time we access those registers.
1079 */
1080 mutex_lock(&dev_priv->dev->struct_mutex);
1081
1082 /* If we've screwed up tracking, just let the interrupt fire again */
1083 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1084 goto out;
1085
1086 misccpctl = I915_READ(GEN7_MISCCPCTL);
1087 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1088 POSTING_READ(GEN7_MISCCPCTL);
1089
1090 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1091 u32 reg;
1092
1093 slice--;
1094 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1095 break;
1096
1097 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1098
1099 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1100
1101 error_status = I915_READ(reg);
1102 row = GEN7_PARITY_ERROR_ROW(error_status);
1103 bank = GEN7_PARITY_ERROR_BANK(error_status);
1104 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1105
1106 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1107 POSTING_READ(reg);
1108
1109 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1110 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1111 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1112 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1113 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1114 parity_event[5] = NULL;
1115
1116 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1117 KOBJ_CHANGE, parity_event);
1118
1119 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1120 slice, row, bank, subbank);
1121
1122 kfree(parity_event[4]);
1123 kfree(parity_event[3]);
1124 kfree(parity_event[2]);
1125 kfree(parity_event[1]);
1126 }
1127
1128 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1129
1130 out:
1131 WARN_ON(dev_priv->l3_parity.which_slice);
1132 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1133 ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1134 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1135
1136 mutex_unlock(&dev_priv->dev->struct_mutex);
1137 }
1138
1139 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1140 {
1141 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1142
1143 if (!HAS_L3_DPF(dev))
1144 return;
1145
1146 spin_lock(&dev_priv->irq_lock);
1147 ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1148 spin_unlock(&dev_priv->irq_lock);
1149
1150 iir &= GT_PARITY_ERROR(dev);
1151 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1152 dev_priv->l3_parity.which_slice |= 1 << 1;
1153
1154 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1155 dev_priv->l3_parity.which_slice |= 1 << 0;
1156
1157 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1158 }
1159
1160 static void ilk_gt_irq_handler(struct drm_device *dev,
1161 struct drm_i915_private *dev_priv,
1162 u32 gt_iir)
1163 {
1164 if (gt_iir &
1165 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1166 notify_ring(dev, &dev_priv->ring[RCS]);
1167 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1168 notify_ring(dev, &dev_priv->ring[VCS]);
1169 }
1170
1171 static void snb_gt_irq_handler(struct drm_device *dev,
1172 struct drm_i915_private *dev_priv,
1173 u32 gt_iir)
1174 {
1175
1176 if (gt_iir &
1177 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1178 notify_ring(dev, &dev_priv->ring[RCS]);
1179 if (gt_iir & GT_BSD_USER_INTERRUPT)
1180 notify_ring(dev, &dev_priv->ring[VCS]);
1181 if (gt_iir & GT_BLT_USER_INTERRUPT)
1182 notify_ring(dev, &dev_priv->ring[BCS]);
1183
1184 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1185 GT_BSD_CS_ERROR_INTERRUPT |
1186 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1187 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
1188 i915_handle_error(dev, false);
1189 }
1190
1191 if (gt_iir & GT_PARITY_ERROR(dev))
1192 ivybridge_parity_error_irq_handler(dev, gt_iir);
1193 }
1194
1195 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1196 struct drm_i915_private *dev_priv,
1197 u32 master_ctl)
1198 {
1199 u32 rcs, bcs, vcs;
1200 uint32_t tmp = 0;
1201 irqreturn_t ret = IRQ_NONE;
1202
1203 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1204 tmp = I915_READ(GEN8_GT_IIR(0));
1205 if (tmp) {
1206 ret = IRQ_HANDLED;
1207 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1208 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1209 if (rcs & GT_RENDER_USER_INTERRUPT)
1210 notify_ring(dev, &dev_priv->ring[RCS]);
1211 if (bcs & GT_RENDER_USER_INTERRUPT)
1212 notify_ring(dev, &dev_priv->ring[BCS]);
1213 I915_WRITE(GEN8_GT_IIR(0), tmp);
1214 } else
1215 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1216 }
1217
1218 if (master_ctl & GEN8_GT_VCS1_IRQ) {
1219 tmp = I915_READ(GEN8_GT_IIR(1));
1220 if (tmp) {
1221 ret = IRQ_HANDLED;
1222 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1223 if (vcs & GT_RENDER_USER_INTERRUPT)
1224 notify_ring(dev, &dev_priv->ring[VCS]);
1225 I915_WRITE(GEN8_GT_IIR(1), tmp);
1226 } else
1227 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1228 }
1229
1230 if (master_ctl & GEN8_GT_VECS_IRQ) {
1231 tmp = I915_READ(GEN8_GT_IIR(3));
1232 if (tmp) {
1233 ret = IRQ_HANDLED;
1234 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1235 if (vcs & GT_RENDER_USER_INTERRUPT)
1236 notify_ring(dev, &dev_priv->ring[VECS]);
1237 I915_WRITE(GEN8_GT_IIR(3), tmp);
1238 } else
1239 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1240 }
1241
1242 return ret;
1243 }
1244
1245 #define HPD_STORM_DETECT_PERIOD 1000
1246 #define HPD_STORM_THRESHOLD 5
1247
1248 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1249 u32 hotplug_trigger,
1250 const u32 *hpd)
1251 {
1252 drm_i915_private_t *dev_priv = dev->dev_private;
1253 int i;
1254 bool storm_detected = false;
1255
1256 if (!hotplug_trigger)
1257 return;
1258
1259 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1260 hotplug_trigger);
1261
1262 spin_lock(&dev_priv->irq_lock);
1263 for (i = 1; i < HPD_NUM_PINS; i++) {
1264
1265 WARN_ONCE(hpd[i] & hotplug_trigger &&
1266 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED,
1267 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1268 hotplug_trigger, i, hpd[i]);
1269
1270 if (!(hpd[i] & hotplug_trigger) ||
1271 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1272 continue;
1273
1274 dev_priv->hpd_event_bits |= (1 << i);
1275 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1276 dev_priv->hpd_stats[i].hpd_last_jiffies
1277 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1278 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1279 dev_priv->hpd_stats[i].hpd_cnt = 0;
1280 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1281 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1282 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1283 dev_priv->hpd_event_bits &= ~(1 << i);
1284 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1285 storm_detected = true;
1286 } else {
1287 dev_priv->hpd_stats[i].hpd_cnt++;
1288 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1289 dev_priv->hpd_stats[i].hpd_cnt);
1290 }
1291 }
1292
1293 if (storm_detected)
1294 dev_priv->display.hpd_irq_setup(dev);
1295 spin_unlock(&dev_priv->irq_lock);
1296
1297 /*
1298 * Our hotplug handler can grab modeset locks (by calling down into the
1299 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1300 * queue for otherwise the flush_work in the pageflip code will
1301 * deadlock.
1302 */
1303 schedule_work(&dev_priv->hotplug_work);
1304 }
1305
1306 static void gmbus_irq_handler(struct drm_device *dev)
1307 {
1308 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1309
1310 wake_up_all(&dev_priv->gmbus_wait_queue);
1311 }
1312
1313 static void dp_aux_irq_handler(struct drm_device *dev)
1314 {
1315 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1316
1317 wake_up_all(&dev_priv->gmbus_wait_queue);
1318 }
1319
1320 #if defined(CONFIG_DEBUG_FS)
1321 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1322 uint32_t crc0, uint32_t crc1,
1323 uint32_t crc2, uint32_t crc3,
1324 uint32_t crc4)
1325 {
1326 struct drm_i915_private *dev_priv = dev->dev_private;
1327 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1328 struct intel_pipe_crc_entry *entry;
1329 int head, tail;
1330
1331 spin_lock(&pipe_crc->lock);
1332
1333 if (!pipe_crc->entries) {
1334 spin_unlock(&pipe_crc->lock);
1335 DRM_ERROR("spurious interrupt\n");
1336 return;
1337 }
1338
1339 head = pipe_crc->head;
1340 tail = pipe_crc->tail;
1341
1342 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1343 spin_unlock(&pipe_crc->lock);
1344 DRM_ERROR("CRC buffer overflowing\n");
1345 return;
1346 }
1347
1348 entry = &pipe_crc->entries[head];
1349
1350 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1351 entry->crc[0] = crc0;
1352 entry->crc[1] = crc1;
1353 entry->crc[2] = crc2;
1354 entry->crc[3] = crc3;
1355 entry->crc[4] = crc4;
1356
1357 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1358 pipe_crc->head = head;
1359
1360 spin_unlock(&pipe_crc->lock);
1361
1362 wake_up_interruptible(&pipe_crc->wq);
1363 }
1364 #else
1365 static inline void
1366 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1367 uint32_t crc0, uint32_t crc1,
1368 uint32_t crc2, uint32_t crc3,
1369 uint32_t crc4) {}
1370 #endif
1371
1372
1373 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1374 {
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1376
1377 display_pipe_crc_irq_handler(dev, pipe,
1378 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1379 0, 0, 0, 0);
1380 }
1381
1382 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1383 {
1384 struct drm_i915_private *dev_priv = dev->dev_private;
1385
1386 display_pipe_crc_irq_handler(dev, pipe,
1387 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1388 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1389 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1390 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1391 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1392 }
1393
1394 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1395 {
1396 struct drm_i915_private *dev_priv = dev->dev_private;
1397 uint32_t res1, res2;
1398
1399 if (INTEL_INFO(dev)->gen >= 3)
1400 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1401 else
1402 res1 = 0;
1403
1404 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1405 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1406 else
1407 res2 = 0;
1408
1409 display_pipe_crc_irq_handler(dev, pipe,
1410 I915_READ(PIPE_CRC_RES_RED(pipe)),
1411 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1412 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1413 res1, res2);
1414 }
1415
1416 /* The RPS events need forcewake, so we add them to a work queue and mask their
1417 * IMR bits until the work is done. Other interrupts can be processed without
1418 * the work queue. */
1419 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1420 {
1421 if (pm_iir & GEN6_PM_RPS_EVENTS) {
1422 spin_lock(&dev_priv->irq_lock);
1423 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
1424 snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS);
1425 spin_unlock(&dev_priv->irq_lock);
1426
1427 queue_work(dev_priv->wq, &dev_priv->rps.work);
1428 }
1429
1430 if (HAS_VEBOX(dev_priv->dev)) {
1431 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1432 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1433
1434 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1435 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
1436 i915_handle_error(dev_priv->dev, false);
1437 }
1438 }
1439 }
1440
1441 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1442 {
1443 struct drm_device *dev = (struct drm_device *) arg;
1444 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1445 u32 iir, gt_iir, pm_iir;
1446 irqreturn_t ret = IRQ_NONE;
1447 unsigned long irqflags;
1448 int pipe;
1449 u32 pipe_stats[I915_MAX_PIPES];
1450
1451 while (true) {
1452 iir = I915_READ(VLV_IIR);
1453 gt_iir = I915_READ(GTIIR);
1454 pm_iir = I915_READ(GEN6_PMIIR);
1455
1456 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1457 goto out;
1458
1459 ret = IRQ_HANDLED;
1460
1461 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1462
1463 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1464 for_each_pipe(pipe) {
1465 int reg = PIPESTAT(pipe);
1466 pipe_stats[pipe] = I915_READ(reg);
1467
1468 /*
1469 * Clear the PIPE*STAT regs before the IIR
1470 */
1471 if (pipe_stats[pipe] & 0x8000ffff)
1472 I915_WRITE(reg, pipe_stats[pipe]);
1473 }
1474 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1475
1476 for_each_pipe(pipe) {
1477 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1478 drm_handle_vblank(dev, pipe);
1479
1480 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1481 intel_prepare_page_flip(dev, pipe);
1482 intel_finish_page_flip(dev, pipe);
1483 }
1484
1485 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1486 i9xx_pipe_crc_irq_handler(dev, pipe);
1487
1488 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
1489 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1490 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
1491 }
1492
1493 /* Consume port. Then clear IIR or we'll miss events */
1494 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1495 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1496 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1497
1498 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1499
1500 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1501 dp_aux_irq_handler(dev);
1502
1503 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1504 I915_READ(PORT_HOTPLUG_STAT);
1505 }
1506
1507 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1508 gmbus_irq_handler(dev);
1509
1510 if (pm_iir)
1511 gen6_rps_irq_handler(dev_priv, pm_iir);
1512
1513 I915_WRITE(GTIIR, gt_iir);
1514 I915_WRITE(GEN6_PMIIR, pm_iir);
1515 I915_WRITE(VLV_IIR, iir);
1516 }
1517
1518 out:
1519 return ret;
1520 }
1521
1522 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1523 {
1524 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1525 int pipe;
1526 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1527
1528 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1529
1530 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1531 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1532 SDE_AUDIO_POWER_SHIFT);
1533 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1534 port_name(port));
1535 }
1536
1537 if (pch_iir & SDE_AUX_MASK)
1538 dp_aux_irq_handler(dev);
1539
1540 if (pch_iir & SDE_GMBUS)
1541 gmbus_irq_handler(dev);
1542
1543 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1544 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1545
1546 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1547 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1548
1549 if (pch_iir & SDE_POISON)
1550 DRM_ERROR("PCH poison interrupt\n");
1551
1552 if (pch_iir & SDE_FDI_MASK)
1553 for_each_pipe(pipe)
1554 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1555 pipe_name(pipe),
1556 I915_READ(FDI_RX_IIR(pipe)));
1557
1558 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1559 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1560
1561 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1562 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1563
1564 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1565 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1566 false))
1567 DRM_ERROR("PCH transcoder A FIFO underrun\n");
1568
1569 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1570 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1571 false))
1572 DRM_ERROR("PCH transcoder B FIFO underrun\n");
1573 }
1574
1575 static void ivb_err_int_handler(struct drm_device *dev)
1576 {
1577 struct drm_i915_private *dev_priv = dev->dev_private;
1578 u32 err_int = I915_READ(GEN7_ERR_INT);
1579 enum pipe pipe;
1580
1581 if (err_int & ERR_INT_POISON)
1582 DRM_ERROR("Poison interrupt\n");
1583
1584 for_each_pipe(pipe) {
1585 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1586 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1587 false))
1588 DRM_ERROR("Pipe %c FIFO underrun\n",
1589 pipe_name(pipe));
1590 }
1591
1592 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1593 if (IS_IVYBRIDGE(dev))
1594 ivb_pipe_crc_irq_handler(dev, pipe);
1595 else
1596 hsw_pipe_crc_irq_handler(dev, pipe);
1597 }
1598 }
1599
1600 I915_WRITE(GEN7_ERR_INT, err_int);
1601 }
1602
1603 static void cpt_serr_int_handler(struct drm_device *dev)
1604 {
1605 struct drm_i915_private *dev_priv = dev->dev_private;
1606 u32 serr_int = I915_READ(SERR_INT);
1607
1608 if (serr_int & SERR_INT_POISON)
1609 DRM_ERROR("PCH poison interrupt\n");
1610
1611 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1612 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1613 false))
1614 DRM_ERROR("PCH transcoder A FIFO underrun\n");
1615
1616 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1617 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1618 false))
1619 DRM_ERROR("PCH transcoder B FIFO underrun\n");
1620
1621 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1622 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1623 false))
1624 DRM_ERROR("PCH transcoder C FIFO underrun\n");
1625
1626 I915_WRITE(SERR_INT, serr_int);
1627 }
1628
1629 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1630 {
1631 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1632 int pipe;
1633 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1634
1635 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1636
1637 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1638 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1639 SDE_AUDIO_POWER_SHIFT_CPT);
1640 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1641 port_name(port));
1642 }
1643
1644 if (pch_iir & SDE_AUX_MASK_CPT)
1645 dp_aux_irq_handler(dev);
1646
1647 if (pch_iir & SDE_GMBUS_CPT)
1648 gmbus_irq_handler(dev);
1649
1650 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1651 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1652
1653 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1654 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1655
1656 if (pch_iir & SDE_FDI_MASK_CPT)
1657 for_each_pipe(pipe)
1658 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1659 pipe_name(pipe),
1660 I915_READ(FDI_RX_IIR(pipe)));
1661
1662 if (pch_iir & SDE_ERROR_CPT)
1663 cpt_serr_int_handler(dev);
1664 }
1665
1666 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1667 {
1668 struct drm_i915_private *dev_priv = dev->dev_private;
1669 enum pipe pipe;
1670
1671 if (de_iir & DE_AUX_CHANNEL_A)
1672 dp_aux_irq_handler(dev);
1673
1674 if (de_iir & DE_GSE)
1675 intel_opregion_asle_intr(dev);
1676
1677 if (de_iir & DE_POISON)
1678 DRM_ERROR("Poison interrupt\n");
1679
1680 for_each_pipe(pipe) {
1681 if (de_iir & DE_PIPE_VBLANK(pipe))
1682 drm_handle_vblank(dev, pipe);
1683
1684 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1685 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1686 DRM_ERROR("Pipe %c FIFO underrun\n",
1687 pipe_name(pipe));
1688
1689 if (de_iir & DE_PIPE_CRC_DONE(pipe))
1690 i9xx_pipe_crc_irq_handler(dev, pipe);
1691
1692 /* plane/pipes map 1:1 on ilk+ */
1693 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
1694 intel_prepare_page_flip(dev, pipe);
1695 intel_finish_page_flip_plane(dev, pipe);
1696 }
1697 }
1698
1699 /* check event from PCH */
1700 if (de_iir & DE_PCH_EVENT) {
1701 u32 pch_iir = I915_READ(SDEIIR);
1702
1703 if (HAS_PCH_CPT(dev))
1704 cpt_irq_handler(dev, pch_iir);
1705 else
1706 ibx_irq_handler(dev, pch_iir);
1707
1708 /* should clear PCH hotplug event before clear CPU irq */
1709 I915_WRITE(SDEIIR, pch_iir);
1710 }
1711
1712 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1713 ironlake_rps_change_irq_handler(dev);
1714 }
1715
1716 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1717 {
1718 struct drm_i915_private *dev_priv = dev->dev_private;
1719 enum pipe i;
1720
1721 if (de_iir & DE_ERR_INT_IVB)
1722 ivb_err_int_handler(dev);
1723
1724 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1725 dp_aux_irq_handler(dev);
1726
1727 if (de_iir & DE_GSE_IVB)
1728 intel_opregion_asle_intr(dev);
1729
1730 for_each_pipe(i) {
1731 if (de_iir & (DE_PIPE_VBLANK_IVB(i)))
1732 drm_handle_vblank(dev, i);
1733
1734 /* plane/pipes map 1:1 on ilk+ */
1735 if (de_iir & DE_PLANE_FLIP_DONE_IVB(i)) {
1736 intel_prepare_page_flip(dev, i);
1737 intel_finish_page_flip_plane(dev, i);
1738 }
1739 }
1740
1741 /* check event from PCH */
1742 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1743 u32 pch_iir = I915_READ(SDEIIR);
1744
1745 cpt_irq_handler(dev, pch_iir);
1746
1747 /* clear PCH hotplug event before clear CPU irq */
1748 I915_WRITE(SDEIIR, pch_iir);
1749 }
1750 }
1751
1752 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1753 {
1754 struct drm_device *dev = (struct drm_device *) arg;
1755 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1756 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
1757 irqreturn_t ret = IRQ_NONE;
1758
1759 /* We get interrupts on unclaimed registers, so check for this before we
1760 * do any I915_{READ,WRITE}. */
1761 intel_uncore_check_errors(dev);
1762
1763 /* disable master interrupt before clearing iir */
1764 de_ier = I915_READ(DEIER);
1765 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1766 POSTING_READ(DEIER);
1767
1768 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1769 * interrupts will will be stored on its back queue, and then we'll be
1770 * able to process them after we restore SDEIER (as soon as we restore
1771 * it, we'll get an interrupt if SDEIIR still has something to process
1772 * due to its back queue). */
1773 if (!HAS_PCH_NOP(dev)) {
1774 sde_ier = I915_READ(SDEIER);
1775 I915_WRITE(SDEIER, 0);
1776 POSTING_READ(SDEIER);
1777 }
1778
1779 gt_iir = I915_READ(GTIIR);
1780 if (gt_iir) {
1781 if (INTEL_INFO(dev)->gen >= 6)
1782 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1783 else
1784 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1785 I915_WRITE(GTIIR, gt_iir);
1786 ret = IRQ_HANDLED;
1787 }
1788
1789 de_iir = I915_READ(DEIIR);
1790 if (de_iir) {
1791 if (INTEL_INFO(dev)->gen >= 7)
1792 ivb_display_irq_handler(dev, de_iir);
1793 else
1794 ilk_display_irq_handler(dev, de_iir);
1795 I915_WRITE(DEIIR, de_iir);
1796 ret = IRQ_HANDLED;
1797 }
1798
1799 if (INTEL_INFO(dev)->gen >= 6) {
1800 u32 pm_iir = I915_READ(GEN6_PMIIR);
1801 if (pm_iir) {
1802 gen6_rps_irq_handler(dev_priv, pm_iir);
1803 I915_WRITE(GEN6_PMIIR, pm_iir);
1804 ret = IRQ_HANDLED;
1805 }
1806 }
1807
1808 I915_WRITE(DEIER, de_ier);
1809 POSTING_READ(DEIER);
1810 if (!HAS_PCH_NOP(dev)) {
1811 I915_WRITE(SDEIER, sde_ier);
1812 POSTING_READ(SDEIER);
1813 }
1814
1815 return ret;
1816 }
1817
1818 static irqreturn_t gen8_irq_handler(int irq, void *arg)
1819 {
1820 struct drm_device *dev = arg;
1821 struct drm_i915_private *dev_priv = dev->dev_private;
1822 u32 master_ctl;
1823 irqreturn_t ret = IRQ_NONE;
1824 uint32_t tmp = 0;
1825 enum pipe pipe;
1826
1827 master_ctl = I915_READ(GEN8_MASTER_IRQ);
1828 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
1829 if (!master_ctl)
1830 return IRQ_NONE;
1831
1832 I915_WRITE(GEN8_MASTER_IRQ, 0);
1833 POSTING_READ(GEN8_MASTER_IRQ);
1834
1835 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1836
1837 if (master_ctl & GEN8_DE_MISC_IRQ) {
1838 tmp = I915_READ(GEN8_DE_MISC_IIR);
1839 if (tmp & GEN8_DE_MISC_GSE)
1840 intel_opregion_asle_intr(dev);
1841 else if (tmp)
1842 DRM_ERROR("Unexpected DE Misc interrupt\n");
1843 else
1844 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
1845
1846 if (tmp) {
1847 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
1848 ret = IRQ_HANDLED;
1849 }
1850 }
1851
1852 if (master_ctl & GEN8_DE_PORT_IRQ) {
1853 tmp = I915_READ(GEN8_DE_PORT_IIR);
1854 if (tmp & GEN8_AUX_CHANNEL_A)
1855 dp_aux_irq_handler(dev);
1856 else if (tmp)
1857 DRM_ERROR("Unexpected DE Port interrupt\n");
1858 else
1859 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
1860
1861 if (tmp) {
1862 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
1863 ret = IRQ_HANDLED;
1864 }
1865 }
1866
1867 for_each_pipe(pipe) {
1868 uint32_t pipe_iir;
1869
1870 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
1871 continue;
1872
1873 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
1874 if (pipe_iir & GEN8_PIPE_VBLANK)
1875 drm_handle_vblank(dev, pipe);
1876
1877 if (pipe_iir & GEN8_PIPE_FLIP_DONE) {
1878 intel_prepare_page_flip(dev, pipe);
1879 intel_finish_page_flip_plane(dev, pipe);
1880 }
1881
1882 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
1883 hsw_pipe_crc_irq_handler(dev, pipe);
1884
1885 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
1886 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1887 false))
1888 DRM_ERROR("Pipe %c FIFO underrun\n",
1889 pipe_name(pipe));
1890 }
1891
1892 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
1893 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
1894 pipe_name(pipe),
1895 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
1896 }
1897
1898 if (pipe_iir) {
1899 ret = IRQ_HANDLED;
1900 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
1901 } else
1902 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
1903 }
1904
1905 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
1906 /*
1907 * FIXME(BDW): Assume for now that the new interrupt handling
1908 * scheme also closed the SDE interrupt handling race we've seen
1909 * on older pch-split platforms. But this needs testing.
1910 */
1911 u32 pch_iir = I915_READ(SDEIIR);
1912
1913 cpt_irq_handler(dev, pch_iir);
1914
1915 if (pch_iir) {
1916 I915_WRITE(SDEIIR, pch_iir);
1917 ret = IRQ_HANDLED;
1918 }
1919 }
1920
1921 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1922 POSTING_READ(GEN8_MASTER_IRQ);
1923
1924 return ret;
1925 }
1926
1927 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
1928 bool reset_completed)
1929 {
1930 struct intel_ring_buffer *ring;
1931 int i;
1932
1933 /*
1934 * Notify all waiters for GPU completion events that reset state has
1935 * been changed, and that they need to restart their wait after
1936 * checking for potential errors (and bail out to drop locks if there is
1937 * a gpu reset pending so that i915_error_work_func can acquire them).
1938 */
1939
1940 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
1941 for_each_ring(ring, dev_priv, i)
1942 wake_up_all(&ring->irq_queue);
1943
1944 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
1945 wake_up_all(&dev_priv->pending_flip_queue);
1946
1947 /*
1948 * Signal tasks blocked in i915_gem_wait_for_error that the pending
1949 * reset state is cleared.
1950 */
1951 if (reset_completed)
1952 wake_up_all(&dev_priv->gpu_error.reset_queue);
1953 }
1954
1955 /**
1956 * i915_error_work_func - do process context error handling work
1957 * @work: work struct
1958 *
1959 * Fire an error uevent so userspace can see that a hang or error
1960 * was detected.
1961 */
1962 static void i915_error_work_func(struct work_struct *work)
1963 {
1964 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1965 work);
1966 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1967 gpu_error);
1968 struct drm_device *dev = dev_priv->dev;
1969 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1970 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1971 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1972 int ret;
1973
1974 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
1975
1976 /*
1977 * Note that there's only one work item which does gpu resets, so we
1978 * need not worry about concurrent gpu resets potentially incrementing
1979 * error->reset_counter twice. We only need to take care of another
1980 * racing irq/hangcheck declaring the gpu dead for a second time. A
1981 * quick check for that is good enough: schedule_work ensures the
1982 * correct ordering between hang detection and this work item, and since
1983 * the reset in-progress bit is only ever set by code outside of this
1984 * work we don't need to worry about any other races.
1985 */
1986 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
1987 DRM_DEBUG_DRIVER("resetting chip\n");
1988 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
1989 reset_event);
1990
1991 /*
1992 * All state reset _must_ be completed before we update the
1993 * reset counter, for otherwise waiters might miss the reset
1994 * pending state and not properly drop locks, resulting in
1995 * deadlocks with the reset work.
1996 */
1997 ret = i915_reset(dev);
1998
1999 intel_display_handle_reset(dev);
2000
2001 if (ret == 0) {
2002 /*
2003 * After all the gem state is reset, increment the reset
2004 * counter and wake up everyone waiting for the reset to
2005 * complete.
2006 *
2007 * Since unlock operations are a one-sided barrier only,
2008 * we need to insert a barrier here to order any seqno
2009 * updates before
2010 * the counter increment.
2011 */
2012 smp_mb__before_atomic_inc();
2013 atomic_inc(&dev_priv->gpu_error.reset_counter);
2014
2015 kobject_uevent_env(&dev->primary->kdev->kobj,
2016 KOBJ_CHANGE, reset_done_event);
2017 } else {
2018 atomic_set_mask(I915_WEDGED, &error->reset_counter);
2019 }
2020
2021 /*
2022 * Note: The wake_up also serves as a memory barrier so that
2023 * waiters see the update value of the reset counter atomic_t.
2024 */
2025 i915_error_wake_up(dev_priv, true);
2026 }
2027 }
2028
2029 static void i915_report_and_clear_eir(struct drm_device *dev)
2030 {
2031 struct drm_i915_private *dev_priv = dev->dev_private;
2032 uint32_t instdone[I915_NUM_INSTDONE_REG];
2033 u32 eir = I915_READ(EIR);
2034 int pipe, i;
2035
2036 if (!eir)
2037 return;
2038
2039 pr_err("render error detected, EIR: 0x%08x\n", eir);
2040
2041 i915_get_extra_instdone(dev, instdone);
2042
2043 if (IS_G4X(dev)) {
2044 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2045 u32 ipeir = I915_READ(IPEIR_I965);
2046
2047 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2048 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2049 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2050 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2051 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2052 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2053 I915_WRITE(IPEIR_I965, ipeir);
2054 POSTING_READ(IPEIR_I965);
2055 }
2056 if (eir & GM45_ERROR_PAGE_TABLE) {
2057 u32 pgtbl_err = I915_READ(PGTBL_ER);
2058 pr_err("page table error\n");
2059 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2060 I915_WRITE(PGTBL_ER, pgtbl_err);
2061 POSTING_READ(PGTBL_ER);
2062 }
2063 }
2064
2065 if (!IS_GEN2(dev)) {
2066 if (eir & I915_ERROR_PAGE_TABLE) {
2067 u32 pgtbl_err = I915_READ(PGTBL_ER);
2068 pr_err("page table error\n");
2069 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2070 I915_WRITE(PGTBL_ER, pgtbl_err);
2071 POSTING_READ(PGTBL_ER);
2072 }
2073 }
2074
2075 if (eir & I915_ERROR_MEMORY_REFRESH) {
2076 pr_err("memory refresh error:\n");
2077 for_each_pipe(pipe)
2078 pr_err("pipe %c stat: 0x%08x\n",
2079 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2080 /* pipestat has already been acked */
2081 }
2082 if (eir & I915_ERROR_INSTRUCTION) {
2083 pr_err("instruction error\n");
2084 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2085 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2086 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2087 if (INTEL_INFO(dev)->gen < 4) {
2088 u32 ipeir = I915_READ(IPEIR);
2089
2090 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2091 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2092 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2093 I915_WRITE(IPEIR, ipeir);
2094 POSTING_READ(IPEIR);
2095 } else {
2096 u32 ipeir = I915_READ(IPEIR_I965);
2097
2098 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2099 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2100 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2101 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2102 I915_WRITE(IPEIR_I965, ipeir);
2103 POSTING_READ(IPEIR_I965);
2104 }
2105 }
2106
2107 I915_WRITE(EIR, eir);
2108 POSTING_READ(EIR);
2109 eir = I915_READ(EIR);
2110 if (eir) {
2111 /*
2112 * some errors might have become stuck,
2113 * mask them.
2114 */
2115 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2116 I915_WRITE(EMR, I915_READ(EMR) | eir);
2117 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2118 }
2119 }
2120
2121 /**
2122 * i915_handle_error - handle an error interrupt
2123 * @dev: drm device
2124 *
2125 * Do some basic checking of regsiter state at error interrupt time and
2126 * dump it to the syslog. Also call i915_capture_error_state() to make
2127 * sure we get a record and make it available in debugfs. Fire a uevent
2128 * so userspace knows something bad happened (should trigger collection
2129 * of a ring dump etc.).
2130 */
2131 void i915_handle_error(struct drm_device *dev, bool wedged)
2132 {
2133 struct drm_i915_private *dev_priv = dev->dev_private;
2134
2135 i915_capture_error_state(dev);
2136 i915_report_and_clear_eir(dev);
2137
2138 if (wedged) {
2139 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2140 &dev_priv->gpu_error.reset_counter);
2141
2142 /*
2143 * Wakeup waiting processes so that the reset work function
2144 * i915_error_work_func doesn't deadlock trying to grab various
2145 * locks. By bumping the reset counter first, the woken
2146 * processes will see a reset in progress and back off,
2147 * releasing their locks and then wait for the reset completion.
2148 * We must do this for _all_ gpu waiters that might hold locks
2149 * that the reset work needs to acquire.
2150 *
2151 * Note: The wake_up serves as the required memory barrier to
2152 * ensure that the waiters see the updated value of the reset
2153 * counter atomic_t.
2154 */
2155 i915_error_wake_up(dev_priv, false);
2156 }
2157
2158 /*
2159 * Our reset work can grab modeset locks (since it needs to reset the
2160 * state of outstanding pagelips). Hence it must not be run on our own
2161 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2162 * code will deadlock.
2163 */
2164 schedule_work(&dev_priv->gpu_error.work);
2165 }
2166
2167 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2168 {
2169 drm_i915_private_t *dev_priv = dev->dev_private;
2170 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2172 struct drm_i915_gem_object *obj;
2173 struct intel_unpin_work *work;
2174 unsigned long flags;
2175 bool stall_detected;
2176
2177 /* Ignore early vblank irqs */
2178 if (intel_crtc == NULL)
2179 return;
2180
2181 spin_lock_irqsave(&dev->event_lock, flags);
2182 work = intel_crtc->unpin_work;
2183
2184 if (work == NULL ||
2185 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2186 !work->enable_stall_check) {
2187 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2188 spin_unlock_irqrestore(&dev->event_lock, flags);
2189 return;
2190 }
2191
2192 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2193 obj = work->pending_flip_obj;
2194 if (INTEL_INFO(dev)->gen >= 4) {
2195 int dspsurf = DSPSURF(intel_crtc->plane);
2196 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2197 i915_gem_obj_ggtt_offset(obj);
2198 } else {
2199 int dspaddr = DSPADDR(intel_crtc->plane);
2200 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2201 crtc->y * crtc->fb->pitches[0] +
2202 crtc->x * crtc->fb->bits_per_pixel/8);
2203 }
2204
2205 spin_unlock_irqrestore(&dev->event_lock, flags);
2206
2207 if (stall_detected) {
2208 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2209 intel_prepare_page_flip(dev, intel_crtc->plane);
2210 }
2211 }
2212
2213 /* Called from drm generic code, passed 'crtc' which
2214 * we use as a pipe index
2215 */
2216 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2217 {
2218 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2219 unsigned long irqflags;
2220
2221 if (!i915_pipe_enabled(dev, pipe))
2222 return -EINVAL;
2223
2224 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2225 if (INTEL_INFO(dev)->gen >= 4)
2226 i915_enable_pipestat(dev_priv, pipe,
2227 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2228 else
2229 i915_enable_pipestat(dev_priv, pipe,
2230 PIPE_VBLANK_INTERRUPT_ENABLE);
2231
2232 /* maintain vblank delivery even in deep C-states */
2233 if (dev_priv->info->gen == 3)
2234 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
2235 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2236
2237 return 0;
2238 }
2239
2240 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2241 {
2242 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2243 unsigned long irqflags;
2244 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2245 DE_PIPE_VBLANK(pipe);
2246
2247 if (!i915_pipe_enabled(dev, pipe))
2248 return -EINVAL;
2249
2250 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2251 ironlake_enable_display_irq(dev_priv, bit);
2252 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2253
2254 return 0;
2255 }
2256
2257 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2258 {
2259 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2260 unsigned long irqflags;
2261 u32 imr;
2262
2263 if (!i915_pipe_enabled(dev, pipe))
2264 return -EINVAL;
2265
2266 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2267 imr = I915_READ(VLV_IMR);
2268 if (pipe == PIPE_A)
2269 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
2270 else
2271 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2272 I915_WRITE(VLV_IMR, imr);
2273 i915_enable_pipestat(dev_priv, pipe,
2274 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2275 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2276
2277 return 0;
2278 }
2279
2280 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2281 {
2282 struct drm_i915_private *dev_priv = dev->dev_private;
2283 unsigned long irqflags;
2284
2285 if (!i915_pipe_enabled(dev, pipe))
2286 return -EINVAL;
2287
2288 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2289 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2290 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2291 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2292 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2293 return 0;
2294 }
2295
2296 /* Called from drm generic code, passed 'crtc' which
2297 * we use as a pipe index
2298 */
2299 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2300 {
2301 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2302 unsigned long irqflags;
2303
2304 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2305 if (dev_priv->info->gen == 3)
2306 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
2307
2308 i915_disable_pipestat(dev_priv, pipe,
2309 PIPE_VBLANK_INTERRUPT_ENABLE |
2310 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2311 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2312 }
2313
2314 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2315 {
2316 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2317 unsigned long irqflags;
2318 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2319 DE_PIPE_VBLANK(pipe);
2320
2321 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2322 ironlake_disable_display_irq(dev_priv, bit);
2323 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2324 }
2325
2326 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2327 {
2328 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2329 unsigned long irqflags;
2330 u32 imr;
2331
2332 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2333 i915_disable_pipestat(dev_priv, pipe,
2334 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2335 imr = I915_READ(VLV_IMR);
2336 if (pipe == PIPE_A)
2337 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
2338 else
2339 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2340 I915_WRITE(VLV_IMR, imr);
2341 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2342 }
2343
2344 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2345 {
2346 struct drm_i915_private *dev_priv = dev->dev_private;
2347 unsigned long irqflags;
2348
2349 if (!i915_pipe_enabled(dev, pipe))
2350 return;
2351
2352 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2353 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2354 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2355 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2356 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2357 }
2358
2359 static u32
2360 ring_last_seqno(struct intel_ring_buffer *ring)
2361 {
2362 return list_entry(ring->request_list.prev,
2363 struct drm_i915_gem_request, list)->seqno;
2364 }
2365
2366 static bool
2367 ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2368 {
2369 return (list_empty(&ring->request_list) ||
2370 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2371 }
2372
2373 static struct intel_ring_buffer *
2374 semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
2375 {
2376 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2377 u32 cmd, ipehr, acthd, acthd_min;
2378
2379 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2380 if ((ipehr & ~(0x3 << 16)) !=
2381 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
2382 return NULL;
2383
2384 /* ACTHD is likely pointing to the dword after the actual command,
2385 * so scan backwards until we find the MBOX.
2386 */
2387 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
2388 acthd_min = max((int)acthd - 3 * 4, 0);
2389 do {
2390 cmd = ioread32(ring->virtual_start + acthd);
2391 if (cmd == ipehr)
2392 break;
2393
2394 acthd -= 4;
2395 if (acthd < acthd_min)
2396 return NULL;
2397 } while (1);
2398
2399 *seqno = ioread32(ring->virtual_start+acthd+4)+1;
2400 return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
2401 }
2402
2403 static int semaphore_passed(struct intel_ring_buffer *ring)
2404 {
2405 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2406 struct intel_ring_buffer *signaller;
2407 u32 seqno, ctl;
2408
2409 ring->hangcheck.deadlock = true;
2410
2411 signaller = semaphore_waits_for(ring, &seqno);
2412 if (signaller == NULL || signaller->hangcheck.deadlock)
2413 return -1;
2414
2415 /* cursory check for an unkickable deadlock */
2416 ctl = I915_READ_CTL(signaller);
2417 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2418 return -1;
2419
2420 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2421 }
2422
2423 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2424 {
2425 struct intel_ring_buffer *ring;
2426 int i;
2427
2428 for_each_ring(ring, dev_priv, i)
2429 ring->hangcheck.deadlock = false;
2430 }
2431
2432 static enum intel_ring_hangcheck_action
2433 ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
2434 {
2435 struct drm_device *dev = ring->dev;
2436 struct drm_i915_private *dev_priv = dev->dev_private;
2437 u32 tmp;
2438
2439 if (ring->hangcheck.acthd != acthd)
2440 return HANGCHECK_ACTIVE;
2441
2442 if (IS_GEN2(dev))
2443 return HANGCHECK_HUNG;
2444
2445 /* Is the chip hanging on a WAIT_FOR_EVENT?
2446 * If so we can simply poke the RB_WAIT bit
2447 * and break the hang. This should work on
2448 * all but the second generation chipsets.
2449 */
2450 tmp = I915_READ_CTL(ring);
2451 if (tmp & RING_WAIT) {
2452 DRM_ERROR("Kicking stuck wait on %s\n",
2453 ring->name);
2454 i915_handle_error(dev, false);
2455 I915_WRITE_CTL(ring, tmp);
2456 return HANGCHECK_KICK;
2457 }
2458
2459 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2460 switch (semaphore_passed(ring)) {
2461 default:
2462 return HANGCHECK_HUNG;
2463 case 1:
2464 DRM_ERROR("Kicking stuck semaphore on %s\n",
2465 ring->name);
2466 i915_handle_error(dev, false);
2467 I915_WRITE_CTL(ring, tmp);
2468 return HANGCHECK_KICK;
2469 case 0:
2470 return HANGCHECK_WAIT;
2471 }
2472 }
2473
2474 return HANGCHECK_HUNG;
2475 }
2476
2477 /**
2478 * This is called when the chip hasn't reported back with completed
2479 * batchbuffers in a long time. We keep track per ring seqno progress and
2480 * if there are no progress, hangcheck score for that ring is increased.
2481 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2482 * we kick the ring. If we see no progress on three subsequent calls
2483 * we assume chip is wedged and try to fix it by resetting the chip.
2484 */
2485 static void i915_hangcheck_elapsed(unsigned long data)
2486 {
2487 struct drm_device *dev = (struct drm_device *)data;
2488 drm_i915_private_t *dev_priv = dev->dev_private;
2489 struct intel_ring_buffer *ring;
2490 int i;
2491 int busy_count = 0, rings_hung = 0;
2492 bool stuck[I915_NUM_RINGS] = { 0 };
2493 #define BUSY 1
2494 #define KICK 5
2495 #define HUNG 20
2496 #define FIRE 30
2497
2498 if (!i915_enable_hangcheck)
2499 return;
2500
2501 for_each_ring(ring, dev_priv, i) {
2502 u32 seqno, acthd;
2503 bool busy = true;
2504
2505 semaphore_clear_deadlocks(dev_priv);
2506
2507 seqno = ring->get_seqno(ring, false);
2508 acthd = intel_ring_get_active_head(ring);
2509
2510 if (ring->hangcheck.seqno == seqno) {
2511 if (ring_idle(ring, seqno)) {
2512 ring->hangcheck.action = HANGCHECK_IDLE;
2513
2514 if (waitqueue_active(&ring->irq_queue)) {
2515 /* Issue a wake-up to catch stuck h/w. */
2516 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2517 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2518 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2519 ring->name);
2520 else
2521 DRM_INFO("Fake missed irq on %s\n",
2522 ring->name);
2523 wake_up_all(&ring->irq_queue);
2524 }
2525 /* Safeguard against driver failure */
2526 ring->hangcheck.score += BUSY;
2527 } else
2528 busy = false;
2529 } else {
2530 /* We always increment the hangcheck score
2531 * if the ring is busy and still processing
2532 * the same request, so that no single request
2533 * can run indefinitely (such as a chain of
2534 * batches). The only time we do not increment
2535 * the hangcheck score on this ring, if this
2536 * ring is in a legitimate wait for another
2537 * ring. In that case the waiting ring is a
2538 * victim and we want to be sure we catch the
2539 * right culprit. Then every time we do kick
2540 * the ring, add a small increment to the
2541 * score so that we can catch a batch that is
2542 * being repeatedly kicked and so responsible
2543 * for stalling the machine.
2544 */
2545 ring->hangcheck.action = ring_stuck(ring,
2546 acthd);
2547
2548 switch (ring->hangcheck.action) {
2549 case HANGCHECK_IDLE:
2550 case HANGCHECK_WAIT:
2551 break;
2552 case HANGCHECK_ACTIVE:
2553 ring->hangcheck.score += BUSY;
2554 break;
2555 case HANGCHECK_KICK:
2556 ring->hangcheck.score += KICK;
2557 break;
2558 case HANGCHECK_HUNG:
2559 ring->hangcheck.score += HUNG;
2560 stuck[i] = true;
2561 break;
2562 }
2563 }
2564 } else {
2565 ring->hangcheck.action = HANGCHECK_ACTIVE;
2566
2567 /* Gradually reduce the count so that we catch DoS
2568 * attempts across multiple batches.
2569 */
2570 if (ring->hangcheck.score > 0)
2571 ring->hangcheck.score--;
2572 }
2573
2574 ring->hangcheck.seqno = seqno;
2575 ring->hangcheck.acthd = acthd;
2576 busy_count += busy;
2577 }
2578
2579 for_each_ring(ring, dev_priv, i) {
2580 if (ring->hangcheck.score > FIRE) {
2581 DRM_INFO("%s on %s\n",
2582 stuck[i] ? "stuck" : "no progress",
2583 ring->name);
2584 rings_hung++;
2585 }
2586 }
2587
2588 if (rings_hung)
2589 return i915_handle_error(dev, true);
2590
2591 if (busy_count)
2592 /* Reset timer case chip hangs without another request
2593 * being added */
2594 i915_queue_hangcheck(dev);
2595 }
2596
2597 void i915_queue_hangcheck(struct drm_device *dev)
2598 {
2599 struct drm_i915_private *dev_priv = dev->dev_private;
2600 if (!i915_enable_hangcheck)
2601 return;
2602
2603 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2604 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2605 }
2606
2607 static void ibx_irq_preinstall(struct drm_device *dev)
2608 {
2609 struct drm_i915_private *dev_priv = dev->dev_private;
2610
2611 if (HAS_PCH_NOP(dev))
2612 return;
2613
2614 /* south display irq */
2615 I915_WRITE(SDEIMR, 0xffffffff);
2616 /*
2617 * SDEIER is also touched by the interrupt handler to work around missed
2618 * PCH interrupts. Hence we can't update it after the interrupt handler
2619 * is enabled - instead we unconditionally enable all PCH interrupt
2620 * sources here, but then only unmask them as needed with SDEIMR.
2621 */
2622 I915_WRITE(SDEIER, 0xffffffff);
2623 POSTING_READ(SDEIER);
2624 }
2625
2626 static void gen5_gt_irq_preinstall(struct drm_device *dev)
2627 {
2628 struct drm_i915_private *dev_priv = dev->dev_private;
2629
2630 /* and GT */
2631 I915_WRITE(GTIMR, 0xffffffff);
2632 I915_WRITE(GTIER, 0x0);
2633 POSTING_READ(GTIER);
2634
2635 if (INTEL_INFO(dev)->gen >= 6) {
2636 /* and PM */
2637 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2638 I915_WRITE(GEN6_PMIER, 0x0);
2639 POSTING_READ(GEN6_PMIER);
2640 }
2641 }
2642
2643 /* drm_dma.h hooks
2644 */
2645 static void ironlake_irq_preinstall(struct drm_device *dev)
2646 {
2647 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2648
2649 I915_WRITE(HWSTAM, 0xeffe);
2650
2651 I915_WRITE(DEIMR, 0xffffffff);
2652 I915_WRITE(DEIER, 0x0);
2653 POSTING_READ(DEIER);
2654
2655 gen5_gt_irq_preinstall(dev);
2656
2657 ibx_irq_preinstall(dev);
2658 }
2659
2660 static void valleyview_irq_preinstall(struct drm_device *dev)
2661 {
2662 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2663 int pipe;
2664
2665 /* VLV magic */
2666 I915_WRITE(VLV_IMR, 0);
2667 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2668 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2669 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2670
2671 /* and GT */
2672 I915_WRITE(GTIIR, I915_READ(GTIIR));
2673 I915_WRITE(GTIIR, I915_READ(GTIIR));
2674
2675 gen5_gt_irq_preinstall(dev);
2676
2677 I915_WRITE(DPINVGTT, 0xff);
2678
2679 I915_WRITE(PORT_HOTPLUG_EN, 0);
2680 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2681 for_each_pipe(pipe)
2682 I915_WRITE(PIPESTAT(pipe), 0xffff);
2683 I915_WRITE(VLV_IIR, 0xffffffff);
2684 I915_WRITE(VLV_IMR, 0xffffffff);
2685 I915_WRITE(VLV_IER, 0x0);
2686 POSTING_READ(VLV_IER);
2687 }
2688
2689 static void gen8_irq_preinstall(struct drm_device *dev)
2690 {
2691 struct drm_i915_private *dev_priv = dev->dev_private;
2692 int pipe;
2693
2694 I915_WRITE(GEN8_MASTER_IRQ, 0);
2695 POSTING_READ(GEN8_MASTER_IRQ);
2696
2697 /* IIR can theoretically queue up two events. Be paranoid */
2698 #define GEN8_IRQ_INIT_NDX(type, which) do { \
2699 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
2700 POSTING_READ(GEN8_##type##_IMR(which)); \
2701 I915_WRITE(GEN8_##type##_IER(which), 0); \
2702 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2703 POSTING_READ(GEN8_##type##_IIR(which)); \
2704 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2705 } while (0)
2706
2707 #define GEN8_IRQ_INIT(type) do { \
2708 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
2709 POSTING_READ(GEN8_##type##_IMR); \
2710 I915_WRITE(GEN8_##type##_IER, 0); \
2711 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2712 POSTING_READ(GEN8_##type##_IIR); \
2713 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2714 } while (0)
2715
2716 GEN8_IRQ_INIT_NDX(GT, 0);
2717 GEN8_IRQ_INIT_NDX(GT, 1);
2718 GEN8_IRQ_INIT_NDX(GT, 2);
2719 GEN8_IRQ_INIT_NDX(GT, 3);
2720
2721 for_each_pipe(pipe) {
2722 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe);
2723 }
2724
2725 GEN8_IRQ_INIT(DE_PORT);
2726 GEN8_IRQ_INIT(DE_MISC);
2727 GEN8_IRQ_INIT(PCU);
2728 #undef GEN8_IRQ_INIT
2729 #undef GEN8_IRQ_INIT_NDX
2730
2731 POSTING_READ(GEN8_PCU_IIR);
2732
2733 ibx_irq_preinstall(dev);
2734 }
2735
2736 static void ibx_hpd_irq_setup(struct drm_device *dev)
2737 {
2738 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2739 struct drm_mode_config *mode_config = &dev->mode_config;
2740 struct intel_encoder *intel_encoder;
2741 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
2742
2743 if (HAS_PCH_IBX(dev)) {
2744 hotplug_irqs = SDE_HOTPLUG_MASK;
2745 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2746 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2747 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
2748 } else {
2749 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
2750 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2751 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2752 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
2753 }
2754
2755 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
2756
2757 /*
2758 * Enable digital hotplug on the PCH, and configure the DP short pulse
2759 * duration to 2ms (which is the minimum in the Display Port spec)
2760 *
2761 * This register is the same on all known PCH chips.
2762 */
2763 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2764 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2765 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2766 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2767 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2768 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2769 }
2770
2771 static void ibx_irq_postinstall(struct drm_device *dev)
2772 {
2773 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2774 u32 mask;
2775
2776 if (HAS_PCH_NOP(dev))
2777 return;
2778
2779 if (HAS_PCH_IBX(dev)) {
2780 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
2781 SDE_TRANSA_FIFO_UNDER | SDE_POISON;
2782 } else {
2783 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2784
2785 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2786 }
2787
2788 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2789 I915_WRITE(SDEIMR, ~mask);
2790 }
2791
2792 static void gen5_gt_irq_postinstall(struct drm_device *dev)
2793 {
2794 struct drm_i915_private *dev_priv = dev->dev_private;
2795 u32 pm_irqs, gt_irqs;
2796
2797 pm_irqs = gt_irqs = 0;
2798
2799 dev_priv->gt_irq_mask = ~0;
2800 if (HAS_L3_DPF(dev)) {
2801 /* L3 parity interrupt is always unmasked. */
2802 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
2803 gt_irqs |= GT_PARITY_ERROR(dev);
2804 }
2805
2806 gt_irqs |= GT_RENDER_USER_INTERRUPT;
2807 if (IS_GEN5(dev)) {
2808 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2809 ILK_BSD_USER_INTERRUPT;
2810 } else {
2811 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2812 }
2813
2814 I915_WRITE(GTIIR, I915_READ(GTIIR));
2815 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2816 I915_WRITE(GTIER, gt_irqs);
2817 POSTING_READ(GTIER);
2818
2819 if (INTEL_INFO(dev)->gen >= 6) {
2820 pm_irqs |= GEN6_PM_RPS_EVENTS;
2821
2822 if (HAS_VEBOX(dev))
2823 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
2824
2825 dev_priv->pm_irq_mask = 0xffffffff;
2826 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2827 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
2828 I915_WRITE(GEN6_PMIER, pm_irqs);
2829 POSTING_READ(GEN6_PMIER);
2830 }
2831 }
2832
2833 static int ironlake_irq_postinstall(struct drm_device *dev)
2834 {
2835 unsigned long irqflags;
2836 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2837 u32 display_mask, extra_mask;
2838
2839 if (INTEL_INFO(dev)->gen >= 7) {
2840 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2841 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
2842 DE_PLANEB_FLIP_DONE_IVB |
2843 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
2844 DE_ERR_INT_IVB);
2845 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
2846 DE_PIPEA_VBLANK_IVB);
2847
2848 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2849 } else {
2850 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2851 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2852 DE_AUX_CHANNEL_A |
2853 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
2854 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
2855 DE_POISON);
2856 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
2857 }
2858
2859 dev_priv->irq_mask = ~display_mask;
2860
2861 /* should always can generate irq */
2862 I915_WRITE(DEIIR, I915_READ(DEIIR));
2863 I915_WRITE(DEIMR, dev_priv->irq_mask);
2864 I915_WRITE(DEIER, display_mask | extra_mask);
2865 POSTING_READ(DEIER);
2866
2867 gen5_gt_irq_postinstall(dev);
2868
2869 ibx_irq_postinstall(dev);
2870
2871 if (IS_IRONLAKE_M(dev)) {
2872 /* Enable PCU event interrupts
2873 *
2874 * spinlocking not required here for correctness since interrupt
2875 * setup is guaranteed to run in single-threaded context. But we
2876 * need it to make the assert_spin_locked happy. */
2877 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2878 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2879 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2880 }
2881
2882 return 0;
2883 }
2884
2885 static int valleyview_irq_postinstall(struct drm_device *dev)
2886 {
2887 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2888 u32 enable_mask;
2889 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV |
2890 PIPE_CRC_DONE_ENABLE;
2891 unsigned long irqflags;
2892
2893 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2894 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2895 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2896 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2897 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2898
2899 /*
2900 *Leave vblank interrupts masked initially. enable/disable will
2901 * toggle them based on usage.
2902 */
2903 dev_priv->irq_mask = (~enable_mask) |
2904 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2905 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2906
2907 I915_WRITE(PORT_HOTPLUG_EN, 0);
2908 POSTING_READ(PORT_HOTPLUG_EN);
2909
2910 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2911 I915_WRITE(VLV_IER, enable_mask);
2912 I915_WRITE(VLV_IIR, 0xffffffff);
2913 I915_WRITE(PIPESTAT(0), 0xffff);
2914 I915_WRITE(PIPESTAT(1), 0xffff);
2915 POSTING_READ(VLV_IER);
2916
2917 /* Interrupt setup is already guaranteed to be single-threaded, this is
2918 * just to make the assert_spin_locked check happy. */
2919 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2920 i915_enable_pipestat(dev_priv, PIPE_A, pipestat_enable);
2921 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE);
2922 i915_enable_pipestat(dev_priv, PIPE_B, pipestat_enable);
2923 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2924
2925 I915_WRITE(VLV_IIR, 0xffffffff);
2926 I915_WRITE(VLV_IIR, 0xffffffff);
2927
2928 gen5_gt_irq_postinstall(dev);
2929
2930 /* ack & enable invalid PTE error interrupts */
2931 #if 0 /* FIXME: add support to irq handler for checking these bits */
2932 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2933 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2934 #endif
2935
2936 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2937
2938 return 0;
2939 }
2940
2941 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
2942 {
2943 int i;
2944
2945 /* These are interrupts we'll toggle with the ring mask register */
2946 uint32_t gt_interrupts[] = {
2947 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
2948 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
2949 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
2950 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
2951 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
2952 0,
2953 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
2954 };
2955
2956 for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) {
2957 u32 tmp = I915_READ(GEN8_GT_IIR(i));
2958 if (tmp)
2959 DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
2960 i, tmp);
2961 I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]);
2962 I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]);
2963 }
2964 POSTING_READ(GEN8_GT_IER(0));
2965 }
2966
2967 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
2968 {
2969 struct drm_device *dev = dev_priv->dev;
2970 uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE |
2971 GEN8_PIPE_CDCLK_CRC_DONE |
2972 GEN8_PIPE_FIFO_UNDERRUN |
2973 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2974 uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK;
2975 int pipe;
2976 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
2977 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
2978 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
2979
2980 for_each_pipe(pipe) {
2981 u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2982 if (tmp)
2983 DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
2984 pipe, tmp);
2985 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2986 I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables);
2987 }
2988 POSTING_READ(GEN8_DE_PIPE_ISR(0));
2989
2990 I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A);
2991 I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A);
2992 POSTING_READ(GEN8_DE_PORT_IER);
2993 }
2994
2995 static int gen8_irq_postinstall(struct drm_device *dev)
2996 {
2997 struct drm_i915_private *dev_priv = dev->dev_private;
2998
2999 gen8_gt_irq_postinstall(dev_priv);
3000 gen8_de_irq_postinstall(dev_priv);
3001
3002 ibx_irq_postinstall(dev);
3003
3004 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3005 POSTING_READ(GEN8_MASTER_IRQ);
3006
3007 return 0;
3008 }
3009
3010 static void gen8_irq_uninstall(struct drm_device *dev)
3011 {
3012 struct drm_i915_private *dev_priv = dev->dev_private;
3013 int pipe;
3014
3015 if (!dev_priv)
3016 return;
3017
3018 I915_WRITE(GEN8_MASTER_IRQ, 0);
3019
3020 #define GEN8_IRQ_FINI_NDX(type, which) do { \
3021 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
3022 I915_WRITE(GEN8_##type##_IER(which), 0); \
3023 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3024 } while (0)
3025
3026 #define GEN8_IRQ_FINI(type) do { \
3027 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
3028 I915_WRITE(GEN8_##type##_IER, 0); \
3029 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3030 } while (0)
3031
3032 GEN8_IRQ_FINI_NDX(GT, 0);
3033 GEN8_IRQ_FINI_NDX(GT, 1);
3034 GEN8_IRQ_FINI_NDX(GT, 2);
3035 GEN8_IRQ_FINI_NDX(GT, 3);
3036
3037 for_each_pipe(pipe) {
3038 GEN8_IRQ_FINI_NDX(DE_PIPE, pipe);
3039 }
3040
3041 GEN8_IRQ_FINI(DE_PORT);
3042 GEN8_IRQ_FINI(DE_MISC);
3043 GEN8_IRQ_FINI(PCU);
3044 #undef GEN8_IRQ_FINI
3045 #undef GEN8_IRQ_FINI_NDX
3046
3047 POSTING_READ(GEN8_PCU_IIR);
3048 }
3049
3050 static void valleyview_irq_uninstall(struct drm_device *dev)
3051 {
3052 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3053 int pipe;
3054
3055 if (!dev_priv)
3056 return;
3057
3058 intel_hpd_irq_uninstall(dev_priv);
3059
3060 for_each_pipe(pipe)
3061 I915_WRITE(PIPESTAT(pipe), 0xffff);
3062
3063 I915_WRITE(HWSTAM, 0xffffffff);
3064 I915_WRITE(PORT_HOTPLUG_EN, 0);
3065 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3066 for_each_pipe(pipe)
3067 I915_WRITE(PIPESTAT(pipe), 0xffff);
3068 I915_WRITE(VLV_IIR, 0xffffffff);
3069 I915_WRITE(VLV_IMR, 0xffffffff);
3070 I915_WRITE(VLV_IER, 0x0);
3071 POSTING_READ(VLV_IER);
3072 }
3073
3074 static void ironlake_irq_uninstall(struct drm_device *dev)
3075 {
3076 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3077
3078 if (!dev_priv)
3079 return;
3080
3081 intel_hpd_irq_uninstall(dev_priv);
3082
3083 I915_WRITE(HWSTAM, 0xffffffff);
3084
3085 I915_WRITE(DEIMR, 0xffffffff);
3086 I915_WRITE(DEIER, 0x0);
3087 I915_WRITE(DEIIR, I915_READ(DEIIR));
3088 if (IS_GEN7(dev))
3089 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
3090
3091 I915_WRITE(GTIMR, 0xffffffff);
3092 I915_WRITE(GTIER, 0x0);
3093 I915_WRITE(GTIIR, I915_READ(GTIIR));
3094
3095 if (HAS_PCH_NOP(dev))
3096 return;
3097
3098 I915_WRITE(SDEIMR, 0xffffffff);
3099 I915_WRITE(SDEIER, 0x0);
3100 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
3101 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3102 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
3103 }
3104
3105 static void i8xx_irq_preinstall(struct drm_device * dev)
3106 {
3107 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3108 int pipe;
3109
3110 for_each_pipe(pipe)
3111 I915_WRITE(PIPESTAT(pipe), 0);
3112 I915_WRITE16(IMR, 0xffff);
3113 I915_WRITE16(IER, 0x0);
3114 POSTING_READ16(IER);
3115 }
3116
3117 static int i8xx_irq_postinstall(struct drm_device *dev)
3118 {
3119 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3120 unsigned long irqflags;
3121
3122 I915_WRITE16(EMR,
3123 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3124
3125 /* Unmask the interrupts that we always want on. */
3126 dev_priv->irq_mask =
3127 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3128 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3129 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3130 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3131 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3132 I915_WRITE16(IMR, dev_priv->irq_mask);
3133
3134 I915_WRITE16(IER,
3135 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3136 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3137 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3138 I915_USER_INTERRUPT);
3139 POSTING_READ16(IER);
3140
3141 /* Interrupt setup is already guaranteed to be single-threaded, this is
3142 * just to make the assert_spin_locked check happy. */
3143 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3144 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3145 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3146 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3147
3148 return 0;
3149 }
3150
3151 /*
3152 * Returns true when a page flip has completed.
3153 */
3154 static bool i8xx_handle_vblank(struct drm_device *dev,
3155 int plane, int pipe, u32 iir)
3156 {
3157 drm_i915_private_t *dev_priv = dev->dev_private;
3158 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3159
3160 if (!drm_handle_vblank(dev, pipe))
3161 return false;
3162
3163 if ((iir & flip_pending) == 0)
3164 return false;
3165
3166 intel_prepare_page_flip(dev, plane);
3167
3168 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3169 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3170 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3171 * the flip is completed (no longer pending). Since this doesn't raise
3172 * an interrupt per se, we watch for the change at vblank.
3173 */
3174 if (I915_READ16(ISR) & flip_pending)
3175 return false;
3176
3177 intel_finish_page_flip(dev, pipe);
3178
3179 return true;
3180 }
3181
3182 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3183 {
3184 struct drm_device *dev = (struct drm_device *) arg;
3185 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3186 u16 iir, new_iir;
3187 u32 pipe_stats[2];
3188 unsigned long irqflags;
3189 int pipe;
3190 u16 flip_mask =
3191 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3192 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3193
3194 iir = I915_READ16(IIR);
3195 if (iir == 0)
3196 return IRQ_NONE;
3197
3198 while (iir & ~flip_mask) {
3199 /* Can't rely on pipestat interrupt bit in iir as it might
3200 * have been cleared after the pipestat interrupt was received.
3201 * It doesn't set the bit in iir again, but it still produces
3202 * interrupts (for non-MSI).
3203 */
3204 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3205 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3206 i915_handle_error(dev, false);
3207
3208 for_each_pipe(pipe) {
3209 int reg = PIPESTAT(pipe);
3210 pipe_stats[pipe] = I915_READ(reg);
3211
3212 /*
3213 * Clear the PIPE*STAT regs before the IIR
3214 */
3215 if (pipe_stats[pipe] & 0x8000ffff)
3216 I915_WRITE(reg, pipe_stats[pipe]);
3217 }
3218 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3219
3220 I915_WRITE16(IIR, iir & ~flip_mask);
3221 new_iir = I915_READ16(IIR); /* Flush posted writes */
3222
3223 i915_update_dri1_breadcrumb(dev);
3224
3225 if (iir & I915_USER_INTERRUPT)
3226 notify_ring(dev, &dev_priv->ring[RCS]);
3227
3228 for_each_pipe(pipe) {
3229 int plane = pipe;
3230 if (HAS_FBC(dev))
3231 plane = !plane;
3232
3233 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3234 i8xx_handle_vblank(dev, plane, pipe, iir))
3235 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3236
3237 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3238 i9xx_pipe_crc_irq_handler(dev, pipe);
3239
3240 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3241 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3242 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3243 }
3244
3245 iir = new_iir;
3246 }
3247
3248 return IRQ_HANDLED;
3249 }
3250
3251 static void i8xx_irq_uninstall(struct drm_device * dev)
3252 {
3253 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3254 int pipe;
3255
3256 for_each_pipe(pipe) {
3257 /* Clear enable bits; then clear status bits */
3258 I915_WRITE(PIPESTAT(pipe), 0);
3259 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3260 }
3261 I915_WRITE16(IMR, 0xffff);
3262 I915_WRITE16(IER, 0x0);
3263 I915_WRITE16(IIR, I915_READ16(IIR));
3264 }
3265
3266 static void i915_irq_preinstall(struct drm_device * dev)
3267 {
3268 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3269 int pipe;
3270
3271 if (I915_HAS_HOTPLUG(dev)) {
3272 I915_WRITE(PORT_HOTPLUG_EN, 0);
3273 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3274 }
3275
3276 I915_WRITE16(HWSTAM, 0xeffe);
3277 for_each_pipe(pipe)
3278 I915_WRITE(PIPESTAT(pipe), 0);
3279 I915_WRITE(IMR, 0xffffffff);
3280 I915_WRITE(IER, 0x0);
3281 POSTING_READ(IER);
3282 }
3283
3284 static int i915_irq_postinstall(struct drm_device *dev)
3285 {
3286 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3287 u32 enable_mask;
3288 unsigned long irqflags;
3289
3290 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3291
3292 /* Unmask the interrupts that we always want on. */
3293 dev_priv->irq_mask =
3294 ~(I915_ASLE_INTERRUPT |
3295 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3296 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3297 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3298 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3299 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3300
3301 enable_mask =
3302 I915_ASLE_INTERRUPT |
3303 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3304 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3305 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3306 I915_USER_INTERRUPT;
3307
3308 if (I915_HAS_HOTPLUG(dev)) {
3309 I915_WRITE(PORT_HOTPLUG_EN, 0);
3310 POSTING_READ(PORT_HOTPLUG_EN);
3311
3312 /* Enable in IER... */
3313 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3314 /* and unmask in IMR */
3315 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3316 }
3317
3318 I915_WRITE(IMR, dev_priv->irq_mask);
3319 I915_WRITE(IER, enable_mask);
3320 POSTING_READ(IER);
3321
3322 i915_enable_asle_pipestat(dev);
3323
3324 /* Interrupt setup is already guaranteed to be single-threaded, this is
3325 * just to make the assert_spin_locked check happy. */
3326 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3327 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3328 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3329 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3330
3331 return 0;
3332 }
3333
3334 /*
3335 * Returns true when a page flip has completed.
3336 */
3337 static bool i915_handle_vblank(struct drm_device *dev,
3338 int plane, int pipe, u32 iir)
3339 {
3340 drm_i915_private_t *dev_priv = dev->dev_private;
3341 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3342
3343 if (!drm_handle_vblank(dev, pipe))
3344 return false;
3345
3346 if ((iir & flip_pending) == 0)
3347 return false;
3348
3349 intel_prepare_page_flip(dev, plane);
3350
3351 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3352 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3353 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3354 * the flip is completed (no longer pending). Since this doesn't raise
3355 * an interrupt per se, we watch for the change at vblank.
3356 */
3357 if (I915_READ(ISR) & flip_pending)
3358 return false;
3359
3360 intel_finish_page_flip(dev, pipe);
3361
3362 return true;
3363 }
3364
3365 static irqreturn_t i915_irq_handler(int irq, void *arg)
3366 {
3367 struct drm_device *dev = (struct drm_device *) arg;
3368 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3369 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3370 unsigned long irqflags;
3371 u32 flip_mask =
3372 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3373 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3374 int pipe, ret = IRQ_NONE;
3375
3376 iir = I915_READ(IIR);
3377 do {
3378 bool irq_received = (iir & ~flip_mask) != 0;
3379 bool blc_event = false;
3380
3381 /* Can't rely on pipestat interrupt bit in iir as it might
3382 * have been cleared after the pipestat interrupt was received.
3383 * It doesn't set the bit in iir again, but it still produces
3384 * interrupts (for non-MSI).
3385 */
3386 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3387 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3388 i915_handle_error(dev, false);
3389
3390 for_each_pipe(pipe) {
3391 int reg = PIPESTAT(pipe);
3392 pipe_stats[pipe] = I915_READ(reg);
3393
3394 /* Clear the PIPE*STAT regs before the IIR */
3395 if (pipe_stats[pipe] & 0x8000ffff) {
3396 I915_WRITE(reg, pipe_stats[pipe]);
3397 irq_received = true;
3398 }
3399 }
3400 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3401
3402 if (!irq_received)
3403 break;
3404
3405 /* Consume port. Then clear IIR or we'll miss events */
3406 if ((I915_HAS_HOTPLUG(dev)) &&
3407 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
3408 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3409 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
3410
3411 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
3412
3413 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3414 POSTING_READ(PORT_HOTPLUG_STAT);
3415 }
3416
3417 I915_WRITE(IIR, iir & ~flip_mask);
3418 new_iir = I915_READ(IIR); /* Flush posted writes */
3419
3420 if (iir & I915_USER_INTERRUPT)
3421 notify_ring(dev, &dev_priv->ring[RCS]);
3422
3423 for_each_pipe(pipe) {
3424 int plane = pipe;
3425 if (HAS_FBC(dev))
3426 plane = !plane;
3427
3428 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3429 i915_handle_vblank(dev, plane, pipe, iir))
3430 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3431
3432 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3433 blc_event = true;
3434
3435 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3436 i9xx_pipe_crc_irq_handler(dev, pipe);
3437
3438 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3439 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3440 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3441 }
3442
3443 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3444 intel_opregion_asle_intr(dev);
3445
3446 /* With MSI, interrupts are only generated when iir
3447 * transitions from zero to nonzero. If another bit got
3448 * set while we were handling the existing iir bits, then
3449 * we would never get another interrupt.
3450 *
3451 * This is fine on non-MSI as well, as if we hit this path
3452 * we avoid exiting the interrupt handler only to generate
3453 * another one.
3454 *
3455 * Note that for MSI this could cause a stray interrupt report
3456 * if an interrupt landed in the time between writing IIR and
3457 * the posting read. This should be rare enough to never
3458 * trigger the 99% of 100,000 interrupts test for disabling
3459 * stray interrupts.
3460 */
3461 ret = IRQ_HANDLED;
3462 iir = new_iir;
3463 } while (iir & ~flip_mask);
3464
3465 i915_update_dri1_breadcrumb(dev);
3466
3467 return ret;
3468 }
3469
3470 static void i915_irq_uninstall(struct drm_device * dev)
3471 {
3472 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3473 int pipe;
3474
3475 intel_hpd_irq_uninstall(dev_priv);
3476
3477 if (I915_HAS_HOTPLUG(dev)) {
3478 I915_WRITE(PORT_HOTPLUG_EN, 0);
3479 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3480 }
3481
3482 I915_WRITE16(HWSTAM, 0xffff);
3483 for_each_pipe(pipe) {
3484 /* Clear enable bits; then clear status bits */
3485 I915_WRITE(PIPESTAT(pipe), 0);
3486 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3487 }
3488 I915_WRITE(IMR, 0xffffffff);
3489 I915_WRITE(IER, 0x0);
3490
3491 I915_WRITE(IIR, I915_READ(IIR));
3492 }
3493
3494 static void i965_irq_preinstall(struct drm_device * dev)
3495 {
3496 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3497 int pipe;
3498
3499 I915_WRITE(PORT_HOTPLUG_EN, 0);
3500 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3501
3502 I915_WRITE(HWSTAM, 0xeffe);
3503 for_each_pipe(pipe)
3504 I915_WRITE(PIPESTAT(pipe), 0);
3505 I915_WRITE(IMR, 0xffffffff);
3506 I915_WRITE(IER, 0x0);
3507 POSTING_READ(IER);
3508 }
3509
3510 static int i965_irq_postinstall(struct drm_device *dev)
3511 {
3512 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3513 u32 enable_mask;
3514 u32 error_mask;
3515 unsigned long irqflags;
3516
3517 /* Unmask the interrupts that we always want on. */
3518 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3519 I915_DISPLAY_PORT_INTERRUPT |
3520 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3521 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3522 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3523 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3524 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3525
3526 enable_mask = ~dev_priv->irq_mask;
3527 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3528 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3529 enable_mask |= I915_USER_INTERRUPT;
3530
3531 if (IS_G4X(dev))
3532 enable_mask |= I915_BSD_USER_INTERRUPT;
3533
3534 /* Interrupt setup is already guaranteed to be single-threaded, this is
3535 * just to make the assert_spin_locked check happy. */
3536 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3537 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE);
3538 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3539 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3540 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3541
3542 /*
3543 * Enable some error detection, note the instruction error mask
3544 * bit is reserved, so we leave it masked.
3545 */
3546 if (IS_G4X(dev)) {
3547 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3548 GM45_ERROR_MEM_PRIV |
3549 GM45_ERROR_CP_PRIV |
3550 I915_ERROR_MEMORY_REFRESH);
3551 } else {
3552 error_mask = ~(I915_ERROR_PAGE_TABLE |
3553 I915_ERROR_MEMORY_REFRESH);
3554 }
3555 I915_WRITE(EMR, error_mask);
3556
3557 I915_WRITE(IMR, dev_priv->irq_mask);
3558 I915_WRITE(IER, enable_mask);
3559 POSTING_READ(IER);
3560
3561 I915_WRITE(PORT_HOTPLUG_EN, 0);
3562 POSTING_READ(PORT_HOTPLUG_EN);
3563
3564 i915_enable_asle_pipestat(dev);
3565
3566 return 0;
3567 }
3568
3569 static void i915_hpd_irq_setup(struct drm_device *dev)
3570 {
3571 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3572 struct drm_mode_config *mode_config = &dev->mode_config;
3573 struct intel_encoder *intel_encoder;
3574 u32 hotplug_en;
3575
3576 assert_spin_locked(&dev_priv->irq_lock);
3577
3578 if (I915_HAS_HOTPLUG(dev)) {
3579 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3580 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3581 /* Note HDMI and DP share hotplug bits */
3582 /* enable bits are the same for all generations */
3583 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3584 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3585 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
3586 /* Programming the CRT detection parameters tends
3587 to generate a spurious hotplug event about three
3588 seconds later. So just do it once.
3589 */
3590 if (IS_G4X(dev))
3591 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3592 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
3593 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3594
3595 /* Ignore TV since it's buggy */
3596 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3597 }
3598 }
3599
3600 static irqreturn_t i965_irq_handler(int irq, void *arg)
3601 {
3602 struct drm_device *dev = (struct drm_device *) arg;
3603 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3604 u32 iir, new_iir;
3605 u32 pipe_stats[I915_MAX_PIPES];
3606 unsigned long irqflags;
3607 int ret = IRQ_NONE, pipe;
3608 u32 flip_mask =
3609 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3610 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3611
3612 iir = I915_READ(IIR);
3613
3614 for (;;) {
3615 bool irq_received = (iir & ~flip_mask) != 0;
3616 bool blc_event = false;
3617
3618 /* Can't rely on pipestat interrupt bit in iir as it might
3619 * have been cleared after the pipestat interrupt was received.
3620 * It doesn't set the bit in iir again, but it still produces
3621 * interrupts (for non-MSI).
3622 */
3623 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3624 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3625 i915_handle_error(dev, false);
3626
3627 for_each_pipe(pipe) {
3628 int reg = PIPESTAT(pipe);
3629 pipe_stats[pipe] = I915_READ(reg);
3630
3631 /*
3632 * Clear the PIPE*STAT regs before the IIR
3633 */
3634 if (pipe_stats[pipe] & 0x8000ffff) {
3635 I915_WRITE(reg, pipe_stats[pipe]);
3636 irq_received = true;
3637 }
3638 }
3639 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3640
3641 if (!irq_received)
3642 break;
3643
3644 ret = IRQ_HANDLED;
3645
3646 /* Consume port. Then clear IIR or we'll miss events */
3647 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
3648 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3649 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3650 HOTPLUG_INT_STATUS_G4X :
3651 HOTPLUG_INT_STATUS_I915);
3652
3653 intel_hpd_irq_handler(dev, hotplug_trigger,
3654 IS_G4X(dev) ? hpd_status_g4x : hpd_status_i915);
3655
3656 if (IS_G4X(dev) &&
3657 (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X))
3658 dp_aux_irq_handler(dev);
3659
3660 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3661 I915_READ(PORT_HOTPLUG_STAT);
3662 }
3663
3664 I915_WRITE(IIR, iir & ~flip_mask);
3665 new_iir = I915_READ(IIR); /* Flush posted writes */
3666
3667 if (iir & I915_USER_INTERRUPT)
3668 notify_ring(dev, &dev_priv->ring[RCS]);
3669 if (iir & I915_BSD_USER_INTERRUPT)
3670 notify_ring(dev, &dev_priv->ring[VCS]);
3671
3672 for_each_pipe(pipe) {
3673 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3674 i915_handle_vblank(dev, pipe, pipe, iir))
3675 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3676
3677 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3678 blc_event = true;
3679
3680 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3681 i9xx_pipe_crc_irq_handler(dev, pipe);
3682
3683 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3684 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3685 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3686 }
3687
3688 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3689 intel_opregion_asle_intr(dev);
3690
3691 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3692 gmbus_irq_handler(dev);
3693
3694 /* With MSI, interrupts are only generated when iir
3695 * transitions from zero to nonzero. If another bit got
3696 * set while we were handling the existing iir bits, then
3697 * we would never get another interrupt.
3698 *
3699 * This is fine on non-MSI as well, as if we hit this path
3700 * we avoid exiting the interrupt handler only to generate
3701 * another one.
3702 *
3703 * Note that for MSI this could cause a stray interrupt report
3704 * if an interrupt landed in the time between writing IIR and
3705 * the posting read. This should be rare enough to never
3706 * trigger the 99% of 100,000 interrupts test for disabling
3707 * stray interrupts.
3708 */
3709 iir = new_iir;
3710 }
3711
3712 i915_update_dri1_breadcrumb(dev);
3713
3714 return ret;
3715 }
3716
3717 static void i965_irq_uninstall(struct drm_device * dev)
3718 {
3719 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3720 int pipe;
3721
3722 if (!dev_priv)
3723 return;
3724
3725 intel_hpd_irq_uninstall(dev_priv);
3726
3727 I915_WRITE(PORT_HOTPLUG_EN, 0);
3728 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3729
3730 I915_WRITE(HWSTAM, 0xffffffff);
3731 for_each_pipe(pipe)
3732 I915_WRITE(PIPESTAT(pipe), 0);
3733 I915_WRITE(IMR, 0xffffffff);
3734 I915_WRITE(IER, 0x0);
3735
3736 for_each_pipe(pipe)
3737 I915_WRITE(PIPESTAT(pipe),
3738 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3739 I915_WRITE(IIR, I915_READ(IIR));
3740 }
3741
3742 static void intel_hpd_irq_reenable(unsigned long data)
3743 {
3744 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3745 struct drm_device *dev = dev_priv->dev;
3746 struct drm_mode_config *mode_config = &dev->mode_config;
3747 unsigned long irqflags;
3748 int i;
3749
3750 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3751 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3752 struct drm_connector *connector;
3753
3754 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3755 continue;
3756
3757 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3758
3759 list_for_each_entry(connector, &mode_config->connector_list, head) {
3760 struct intel_connector *intel_connector = to_intel_connector(connector);
3761
3762 if (intel_connector->encoder->hpd_pin == i) {
3763 if (connector->polled != intel_connector->polled)
3764 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3765 drm_get_connector_name(connector));
3766 connector->polled = intel_connector->polled;
3767 if (!connector->polled)
3768 connector->polled = DRM_CONNECTOR_POLL_HPD;
3769 }
3770 }
3771 }
3772 if (dev_priv->display.hpd_irq_setup)
3773 dev_priv->display.hpd_irq_setup(dev);
3774 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3775 }
3776
3777 void intel_irq_init(struct drm_device *dev)
3778 {
3779 struct drm_i915_private *dev_priv = dev->dev_private;
3780
3781 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
3782 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
3783 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
3784 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
3785
3786 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3787 i915_hangcheck_elapsed,
3788 (unsigned long) dev);
3789 setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable,
3790 (unsigned long) dev_priv);
3791
3792 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
3793
3794 if (IS_GEN2(dev)) {
3795 dev->max_vblank_count = 0;
3796 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
3797 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3798 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3799 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3800 } else {
3801 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3802 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
3803 }
3804
3805 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
3806 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3807 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3808 }
3809
3810 if (IS_VALLEYVIEW(dev)) {
3811 dev->driver->irq_handler = valleyview_irq_handler;
3812 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3813 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3814 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3815 dev->driver->enable_vblank = valleyview_enable_vblank;
3816 dev->driver->disable_vblank = valleyview_disable_vblank;
3817 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3818 } else if (IS_GEN8(dev)) {
3819 dev->driver->irq_handler = gen8_irq_handler;
3820 dev->driver->irq_preinstall = gen8_irq_preinstall;
3821 dev->driver->irq_postinstall = gen8_irq_postinstall;
3822 dev->driver->irq_uninstall = gen8_irq_uninstall;
3823 dev->driver->enable_vblank = gen8_enable_vblank;
3824 dev->driver->disable_vblank = gen8_disable_vblank;
3825 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3826 } else if (HAS_PCH_SPLIT(dev)) {
3827 dev->driver->irq_handler = ironlake_irq_handler;
3828 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3829 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3830 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3831 dev->driver->enable_vblank = ironlake_enable_vblank;
3832 dev->driver->disable_vblank = ironlake_disable_vblank;
3833 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3834 } else {
3835 if (INTEL_INFO(dev)->gen == 2) {
3836 dev->driver->irq_preinstall = i8xx_irq_preinstall;
3837 dev->driver->irq_postinstall = i8xx_irq_postinstall;
3838 dev->driver->irq_handler = i8xx_irq_handler;
3839 dev->driver->irq_uninstall = i8xx_irq_uninstall;
3840 } else if (INTEL_INFO(dev)->gen == 3) {
3841 dev->driver->irq_preinstall = i915_irq_preinstall;
3842 dev->driver->irq_postinstall = i915_irq_postinstall;
3843 dev->driver->irq_uninstall = i915_irq_uninstall;
3844 dev->driver->irq_handler = i915_irq_handler;
3845 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3846 } else {
3847 dev->driver->irq_preinstall = i965_irq_preinstall;
3848 dev->driver->irq_postinstall = i965_irq_postinstall;
3849 dev->driver->irq_uninstall = i965_irq_uninstall;
3850 dev->driver->irq_handler = i965_irq_handler;
3851 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3852 }
3853 dev->driver->enable_vblank = i915_enable_vblank;
3854 dev->driver->disable_vblank = i915_disable_vblank;
3855 }
3856 }
3857
3858 void intel_hpd_init(struct drm_device *dev)
3859 {
3860 struct drm_i915_private *dev_priv = dev->dev_private;
3861 struct drm_mode_config *mode_config = &dev->mode_config;
3862 struct drm_connector *connector;
3863 unsigned long irqflags;
3864 int i;
3865
3866 for (i = 1; i < HPD_NUM_PINS; i++) {
3867 dev_priv->hpd_stats[i].hpd_cnt = 0;
3868 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3869 }
3870 list_for_each_entry(connector, &mode_config->connector_list, head) {
3871 struct intel_connector *intel_connector = to_intel_connector(connector);
3872 connector->polled = intel_connector->polled;
3873 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3874 connector->polled = DRM_CONNECTOR_POLL_HPD;
3875 }
3876
3877 /* Interrupt setup is already guaranteed to be single-threaded, this is
3878 * just to make the assert_spin_locked checks happy. */
3879 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3880 if (dev_priv->display.hpd_irq_setup)
3881 dev_priv->display.hpd_irq_setup(dev);
3882 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3883 }
3884
3885 /* Disable interrupts so we can allow Package C8+. */
3886 void hsw_pc8_disable_interrupts(struct drm_device *dev)
3887 {
3888 struct drm_i915_private *dev_priv = dev->dev_private;
3889 unsigned long irqflags;
3890
3891 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3892
3893 dev_priv->pc8.regsave.deimr = I915_READ(DEIMR);
3894 dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR);
3895 dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR);
3896 dev_priv->pc8.regsave.gtier = I915_READ(GTIER);
3897 dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
3898
3899 ironlake_disable_display_irq(dev_priv, 0xffffffff);
3900 ibx_disable_display_interrupt(dev_priv, 0xffffffff);
3901 ilk_disable_gt_irq(dev_priv, 0xffffffff);
3902 snb_disable_pm_irq(dev_priv, 0xffffffff);
3903
3904 dev_priv->pc8.irqs_disabled = true;
3905
3906 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3907 }
3908
3909 /* Restore interrupts so we can recover from Package C8+. */
3910 void hsw_pc8_restore_interrupts(struct drm_device *dev)
3911 {
3912 struct drm_i915_private *dev_priv = dev->dev_private;
3913 unsigned long irqflags;
3914 uint32_t val;
3915
3916 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3917
3918 val = I915_READ(DEIMR);
3919 WARN(val != 0xffffffff, "DEIMR is 0x%08x\n", val);
3920
3921 val = I915_READ(SDEIMR);
3922 WARN(val != 0xffffffff, "SDEIMR is 0x%08x\n", val);
3923
3924 val = I915_READ(GTIMR);
3925 WARN(val != 0xffffffff, "GTIMR is 0x%08x\n", val);
3926
3927 val = I915_READ(GEN6_PMIMR);
3928 WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val);
3929
3930 dev_priv->pc8.irqs_disabled = false;
3931
3932 ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr);
3933 ibx_enable_display_interrupt(dev_priv, ~dev_priv->pc8.regsave.sdeimr);
3934 ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr);
3935 snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr);
3936 I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier);
3937
3938 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3939 }
Linux kernel - Deliverables
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