1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
40 static const u32 hpd_ibx
[] = {
41 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
42 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
43 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
44 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
45 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
48 static const u32 hpd_cpt
[] = {
49 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
50 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
51 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
52 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
53 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
56 static const u32 hpd_mask_i915
[] = {
57 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
58 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
59 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
60 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
61 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
62 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
65 static const u32 hpd_status_g4x
[] = {
66 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
67 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
68 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
69 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
70 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
71 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
74 static const u32 hpd_status_i915
[] = { /* i915 and valleyview are the same */
75 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
76 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
77 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
78 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
79 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
80 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
83 /* IIR can theoretically queue up two events. Be paranoid. */
84 #define GEN8_IRQ_RESET_NDX(type, which) do { \
85 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
86 POSTING_READ(GEN8_##type##_IMR(which)); \
87 I915_WRITE(GEN8_##type##_IER(which), 0); \
88 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
89 POSTING_READ(GEN8_##type##_IIR(which)); \
90 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
91 POSTING_READ(GEN8_##type##_IIR(which)); \
94 #define GEN5_IRQ_RESET(type) do { \
95 I915_WRITE(type##IMR, 0xffffffff); \
96 POSTING_READ(type##IMR); \
97 I915_WRITE(type##IER, 0); \
98 I915_WRITE(type##IIR, 0xffffffff); \
99 POSTING_READ(type##IIR); \
100 I915_WRITE(type##IIR, 0xffffffff); \
101 POSTING_READ(type##IIR); \
105 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
107 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
108 u32 val = I915_READ(reg); \
110 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
112 I915_WRITE((reg), 0xffffffff); \
114 I915_WRITE((reg), 0xffffffff); \
119 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
120 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
121 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
122 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
123 POSTING_READ(GEN8_##type##_IER(which)); \
126 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
127 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
128 I915_WRITE(type##IMR, (imr_val)); \
129 I915_WRITE(type##IER, (ier_val)); \
130 POSTING_READ(type##IER); \
133 /* For display hotplug interrupt */
135 ironlake_enable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
)
137 assert_spin_locked(&dev_priv
->irq_lock
);
139 if (dev_priv
->pm
.irqs_disabled
) {
140 WARN(1, "IRQs disabled\n");
141 dev_priv
->pm
.regsave
.deimr
&= ~mask
;
145 if ((dev_priv
->irq_mask
& mask
) != 0) {
146 dev_priv
->irq_mask
&= ~mask
;
147 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
153 ironlake_disable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
)
155 assert_spin_locked(&dev_priv
->irq_lock
);
157 if (dev_priv
->pm
.irqs_disabled
) {
158 WARN(1, "IRQs disabled\n");
159 dev_priv
->pm
.regsave
.deimr
|= mask
;
163 if ((dev_priv
->irq_mask
& mask
) != mask
) {
164 dev_priv
->irq_mask
|= mask
;
165 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
171 * ilk_update_gt_irq - update GTIMR
172 * @dev_priv: driver private
173 * @interrupt_mask: mask of interrupt bits to update
174 * @enabled_irq_mask: mask of interrupt bits to enable
176 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
177 uint32_t interrupt_mask
,
178 uint32_t enabled_irq_mask
)
180 assert_spin_locked(&dev_priv
->irq_lock
);
182 if (dev_priv
->pm
.irqs_disabled
) {
183 WARN(1, "IRQs disabled\n");
184 dev_priv
->pm
.regsave
.gtimr
&= ~interrupt_mask
;
185 dev_priv
->pm
.regsave
.gtimr
|= (~enabled_irq_mask
&
190 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
191 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
192 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
196 void ilk_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
198 ilk_update_gt_irq(dev_priv
, mask
, mask
);
201 void ilk_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
203 ilk_update_gt_irq(dev_priv
, mask
, 0);
207 * snb_update_pm_irq - update GEN6_PMIMR
208 * @dev_priv: driver private
209 * @interrupt_mask: mask of interrupt bits to update
210 * @enabled_irq_mask: mask of interrupt bits to enable
212 static void snb_update_pm_irq(struct drm_i915_private
*dev_priv
,
213 uint32_t interrupt_mask
,
214 uint32_t enabled_irq_mask
)
218 assert_spin_locked(&dev_priv
->irq_lock
);
220 if (dev_priv
->pm
.irqs_disabled
) {
221 WARN(1, "IRQs disabled\n");
222 dev_priv
->pm
.regsave
.gen6_pmimr
&= ~interrupt_mask
;
223 dev_priv
->pm
.regsave
.gen6_pmimr
|= (~enabled_irq_mask
&
228 new_val
= dev_priv
->pm_irq_mask
;
229 new_val
&= ~interrupt_mask
;
230 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
232 if (new_val
!= dev_priv
->pm_irq_mask
) {
233 dev_priv
->pm_irq_mask
= new_val
;
234 I915_WRITE(GEN6_PMIMR
, dev_priv
->pm_irq_mask
);
235 POSTING_READ(GEN6_PMIMR
);
239 void snb_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
241 snb_update_pm_irq(dev_priv
, mask
, mask
);
244 void snb_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
246 snb_update_pm_irq(dev_priv
, mask
, 0);
249 static bool ivb_can_enable_err_int(struct drm_device
*dev
)
251 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
252 struct intel_crtc
*crtc
;
255 assert_spin_locked(&dev_priv
->irq_lock
);
257 for_each_pipe(pipe
) {
258 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
260 if (crtc
->cpu_fifo_underrun_disabled
)
267 static bool cpt_can_enable_serr_int(struct drm_device
*dev
)
269 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
271 struct intel_crtc
*crtc
;
273 assert_spin_locked(&dev_priv
->irq_lock
);
275 for_each_pipe(pipe
) {
276 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
278 if (crtc
->pch_fifo_underrun_disabled
)
285 static void i9xx_clear_fifo_underrun(struct drm_device
*dev
, enum pipe pipe
)
287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
288 u32 reg
= PIPESTAT(pipe
);
289 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
291 assert_spin_locked(&dev_priv
->irq_lock
);
293 I915_WRITE(reg
, pipestat
| PIPE_FIFO_UNDERRUN_STATUS
);
297 static void ironlake_set_fifo_underrun_reporting(struct drm_device
*dev
,
298 enum pipe pipe
, bool enable
)
300 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
301 uint32_t bit
= (pipe
== PIPE_A
) ? DE_PIPEA_FIFO_UNDERRUN
:
302 DE_PIPEB_FIFO_UNDERRUN
;
305 ironlake_enable_display_irq(dev_priv
, bit
);
307 ironlake_disable_display_irq(dev_priv
, bit
);
310 static void ivybridge_set_fifo_underrun_reporting(struct drm_device
*dev
,
311 enum pipe pipe
, bool enable
)
313 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
315 I915_WRITE(GEN7_ERR_INT
, ERR_INT_FIFO_UNDERRUN(pipe
));
317 if (!ivb_can_enable_err_int(dev
))
320 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
322 bool was_enabled
= !(I915_READ(DEIMR
) & DE_ERR_INT_IVB
);
324 /* Change the state _after_ we've read out the current one. */
325 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
328 (I915_READ(GEN7_ERR_INT
) & ERR_INT_FIFO_UNDERRUN(pipe
))) {
329 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
335 static void broadwell_set_fifo_underrun_reporting(struct drm_device
*dev
,
336 enum pipe pipe
, bool enable
)
338 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
340 assert_spin_locked(&dev_priv
->irq_lock
);
343 dev_priv
->de_irq_mask
[pipe
] &= ~GEN8_PIPE_FIFO_UNDERRUN
;
345 dev_priv
->de_irq_mask
[pipe
] |= GEN8_PIPE_FIFO_UNDERRUN
;
346 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
347 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
351 * ibx_display_interrupt_update - update SDEIMR
352 * @dev_priv: driver private
353 * @interrupt_mask: mask of interrupt bits to update
354 * @enabled_irq_mask: mask of interrupt bits to enable
356 static void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
357 uint32_t interrupt_mask
,
358 uint32_t enabled_irq_mask
)
360 uint32_t sdeimr
= I915_READ(SDEIMR
);
361 sdeimr
&= ~interrupt_mask
;
362 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
364 assert_spin_locked(&dev_priv
->irq_lock
);
366 if (dev_priv
->pm
.irqs_disabled
&&
367 (interrupt_mask
& SDE_HOTPLUG_MASK_CPT
)) {
368 WARN(1, "IRQs disabled\n");
369 dev_priv
->pm
.regsave
.sdeimr
&= ~interrupt_mask
;
370 dev_priv
->pm
.regsave
.sdeimr
|= (~enabled_irq_mask
&
375 I915_WRITE(SDEIMR
, sdeimr
);
376 POSTING_READ(SDEIMR
);
378 #define ibx_enable_display_interrupt(dev_priv, bits) \
379 ibx_display_interrupt_update((dev_priv), (bits), (bits))
380 #define ibx_disable_display_interrupt(dev_priv, bits) \
381 ibx_display_interrupt_update((dev_priv), (bits), 0)
383 static void ibx_set_fifo_underrun_reporting(struct drm_device
*dev
,
384 enum transcoder pch_transcoder
,
387 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
388 uint32_t bit
= (pch_transcoder
== TRANSCODER_A
) ?
389 SDE_TRANSA_FIFO_UNDER
: SDE_TRANSB_FIFO_UNDER
;
392 ibx_enable_display_interrupt(dev_priv
, bit
);
394 ibx_disable_display_interrupt(dev_priv
, bit
);
397 static void cpt_set_fifo_underrun_reporting(struct drm_device
*dev
,
398 enum transcoder pch_transcoder
,
401 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
405 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
));
407 if (!cpt_can_enable_serr_int(dev
))
410 ibx_enable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
412 uint32_t tmp
= I915_READ(SERR_INT
);
413 bool was_enabled
= !(I915_READ(SDEIMR
) & SDE_ERROR_CPT
);
415 /* Change the state _after_ we've read out the current one. */
416 ibx_disable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
419 (tmp
& SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
))) {
420 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
421 transcoder_name(pch_transcoder
));
427 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
430 * @enable: true if we want to report FIFO underrun errors, false otherwise
432 * This function makes us disable or enable CPU fifo underruns for a specific
433 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
434 * reporting for one pipe may also disable all the other CPU error interruts for
435 * the other pipes, due to the fact that there's just one interrupt mask/enable
436 * bit for all the pipes.
438 * Returns the previous state of underrun reporting.
440 bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
441 enum pipe pipe
, bool enable
)
443 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
444 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
445 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
448 assert_spin_locked(&dev_priv
->irq_lock
);
450 ret
= !intel_crtc
->cpu_fifo_underrun_disabled
;
455 intel_crtc
->cpu_fifo_underrun_disabled
= !enable
;
457 if (enable
&& (INTEL_INFO(dev
)->gen
< 5 || IS_VALLEYVIEW(dev
)))
458 i9xx_clear_fifo_underrun(dev
, pipe
);
459 else if (IS_GEN5(dev
) || IS_GEN6(dev
))
460 ironlake_set_fifo_underrun_reporting(dev
, pipe
, enable
);
461 else if (IS_GEN7(dev
))
462 ivybridge_set_fifo_underrun_reporting(dev
, pipe
, enable
);
463 else if (IS_GEN8(dev
))
464 broadwell_set_fifo_underrun_reporting(dev
, pipe
, enable
);
470 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
471 enum pipe pipe
, bool enable
)
473 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
477 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
478 ret
= __intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, enable
);
479 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
484 static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device
*dev
,
487 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
488 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
489 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
491 return !intel_crtc
->cpu_fifo_underrun_disabled
;
495 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
497 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
498 * @enable: true if we want to report FIFO underrun errors, false otherwise
500 * This function makes us disable or enable PCH fifo underruns for a specific
501 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
502 * underrun reporting for one transcoder may also disable all the other PCH
503 * error interruts for the other transcoders, due to the fact that there's just
504 * one interrupt mask/enable bit for all the transcoders.
506 * Returns the previous state of underrun reporting.
508 bool intel_set_pch_fifo_underrun_reporting(struct drm_device
*dev
,
509 enum transcoder pch_transcoder
,
512 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
513 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pch_transcoder
];
514 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
519 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
520 * has only one pch transcoder A that all pipes can use. To avoid racy
521 * pch transcoder -> pipe lookups from interrupt code simply store the
522 * underrun statistics in crtc A. Since we never expose this anywhere
523 * nor use it outside of the fifo underrun code here using the "wrong"
524 * crtc on LPT won't cause issues.
527 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
529 ret
= !intel_crtc
->pch_fifo_underrun_disabled
;
534 intel_crtc
->pch_fifo_underrun_disabled
= !enable
;
536 if (HAS_PCH_IBX(dev
))
537 ibx_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
539 cpt_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
542 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
548 __i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
549 u32 enable_mask
, u32 status_mask
)
551 u32 reg
= PIPESTAT(pipe
);
552 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
554 assert_spin_locked(&dev_priv
->irq_lock
);
556 if (WARN_ON_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
557 status_mask
& ~PIPESTAT_INT_STATUS_MASK
))
560 if ((pipestat
& enable_mask
) == enable_mask
)
563 dev_priv
->pipestat_irq_mask
[pipe
] |= status_mask
;
565 /* Enable the interrupt, clear any pending status */
566 pipestat
|= enable_mask
| status_mask
;
567 I915_WRITE(reg
, pipestat
);
572 __i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
573 u32 enable_mask
, u32 status_mask
)
575 u32 reg
= PIPESTAT(pipe
);
576 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
578 assert_spin_locked(&dev_priv
->irq_lock
);
580 if (WARN_ON_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
581 status_mask
& ~PIPESTAT_INT_STATUS_MASK
))
584 if ((pipestat
& enable_mask
) == 0)
587 dev_priv
->pipestat_irq_mask
[pipe
] &= ~status_mask
;
589 pipestat
&= ~enable_mask
;
590 I915_WRITE(reg
, pipestat
);
594 static u32
vlv_get_pipestat_enable_mask(struct drm_device
*dev
, u32 status_mask
)
596 u32 enable_mask
= status_mask
<< 16;
599 * On pipe A we don't support the PSR interrupt yet, on pipe B the
602 if (WARN_ON_ONCE(status_mask
& PIPE_A_PSR_STATUS_VLV
))
605 enable_mask
&= ~(PIPE_FIFO_UNDERRUN_STATUS
|
606 SPRITE0_FLIP_DONE_INT_EN_VLV
|
607 SPRITE1_FLIP_DONE_INT_EN_VLV
);
608 if (status_mask
& SPRITE0_FLIP_DONE_INT_STATUS_VLV
)
609 enable_mask
|= SPRITE0_FLIP_DONE_INT_EN_VLV
;
610 if (status_mask
& SPRITE1_FLIP_DONE_INT_STATUS_VLV
)
611 enable_mask
|= SPRITE1_FLIP_DONE_INT_EN_VLV
;
617 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
622 if (IS_VALLEYVIEW(dev_priv
->dev
))
623 enable_mask
= vlv_get_pipestat_enable_mask(dev_priv
->dev
,
626 enable_mask
= status_mask
<< 16;
627 __i915_enable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
631 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
636 if (IS_VALLEYVIEW(dev_priv
->dev
))
637 enable_mask
= vlv_get_pipestat_enable_mask(dev_priv
->dev
,
640 enable_mask
= status_mask
<< 16;
641 __i915_disable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
645 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
647 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
649 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
650 unsigned long irqflags
;
652 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
655 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
657 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_LEGACY_BLC_EVENT_STATUS
);
658 if (INTEL_INFO(dev
)->gen
>= 4)
659 i915_enable_pipestat(dev_priv
, PIPE_A
,
660 PIPE_LEGACY_BLC_EVENT_STATUS
);
662 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
666 * i915_pipe_enabled - check if a pipe is enabled
668 * @pipe: pipe to check
670 * Reading certain registers when the pipe is disabled can hang the chip.
671 * Use this routine to make sure the PLL is running and the pipe is active
672 * before reading such registers if unsure.
675 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
677 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
679 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
680 /* Locking is horribly broken here, but whatever. */
681 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
682 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
684 return intel_crtc
->active
;
686 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
690 static u32
i8xx_get_vblank_counter(struct drm_device
*dev
, int pipe
)
692 /* Gen2 doesn't have a hardware frame counter */
696 /* Called from drm generic code, passed a 'crtc', which
697 * we use as a pipe index
699 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
702 unsigned long high_frame
;
703 unsigned long low_frame
;
704 u32 high1
, high2
, low
, pixel
, vbl_start
;
706 if (!i915_pipe_enabled(dev
, pipe
)) {
707 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
708 "pipe %c\n", pipe_name(pipe
));
712 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
713 struct intel_crtc
*intel_crtc
=
714 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
715 const struct drm_display_mode
*mode
=
716 &intel_crtc
->config
.adjusted_mode
;
718 vbl_start
= mode
->crtc_vblank_start
* mode
->crtc_htotal
;
720 enum transcoder cpu_transcoder
= (enum transcoder
) pipe
;
723 htotal
= ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff) + 1;
724 vbl_start
= (I915_READ(VBLANK(cpu_transcoder
)) & 0x1fff) + 1;
729 high_frame
= PIPEFRAME(pipe
);
730 low_frame
= PIPEFRAMEPIXEL(pipe
);
733 * High & low register fields aren't synchronized, so make sure
734 * we get a low value that's stable across two reads of the high
738 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
739 low
= I915_READ(low_frame
);
740 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
741 } while (high1
!= high2
);
743 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
744 pixel
= low
& PIPE_PIXEL_MASK
;
745 low
>>= PIPE_FRAME_LOW_SHIFT
;
748 * The frame counter increments at beginning of active.
749 * Cook up a vblank counter by also checking the pixel
750 * counter against vblank start.
752 return (((high1
<< 8) | low
) + (pixel
>= vbl_start
)) & 0xffffff;
755 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
757 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
758 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
760 if (!i915_pipe_enabled(dev
, pipe
)) {
761 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
762 "pipe %c\n", pipe_name(pipe
));
766 return I915_READ(reg
);
769 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
770 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
772 static bool ilk_pipe_in_vblank_locked(struct drm_device
*dev
, enum pipe pipe
)
774 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
778 if (INTEL_INFO(dev
)->gen
>= 8) {
779 status
= GEN8_PIPE_VBLANK
;
780 reg
= GEN8_DE_PIPE_ISR(pipe
);
781 } else if (INTEL_INFO(dev
)->gen
>= 7) {
782 status
= DE_PIPE_VBLANK_IVB(pipe
);
785 status
= DE_PIPE_VBLANK(pipe
);
789 return __raw_i915_read32(dev_priv
, reg
) & status
;
792 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
793 unsigned int flags
, int *vpos
, int *hpos
,
794 ktime_t
*stime
, ktime_t
*etime
)
796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
797 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
798 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
799 const struct drm_display_mode
*mode
= &intel_crtc
->config
.adjusted_mode
;
801 int vbl_start
, vbl_end
, htotal
, vtotal
;
804 unsigned long irqflags
;
806 if (!intel_crtc
->active
) {
807 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
808 "pipe %c\n", pipe_name(pipe
));
812 htotal
= mode
->crtc_htotal
;
813 vtotal
= mode
->crtc_vtotal
;
814 vbl_start
= mode
->crtc_vblank_start
;
815 vbl_end
= mode
->crtc_vblank_end
;
817 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
818 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
823 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
826 * Lock uncore.lock, as we will do multiple timing critical raw
827 * register reads, potentially with preemption disabled, so the
828 * following code must not block on uncore.lock.
830 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
832 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
834 /* Get optional system timestamp before query. */
836 *stime
= ktime_get();
838 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
839 /* No obvious pixelcount register. Only query vertical
840 * scanout position from Display scan line register.
843 position
= __raw_i915_read32(dev_priv
, PIPEDSL(pipe
)) & DSL_LINEMASK_GEN2
;
845 position
= __raw_i915_read32(dev_priv
, PIPEDSL(pipe
)) & DSL_LINEMASK_GEN3
;
849 * On HSW HDMI outputs there seems to be a 2 line
850 * difference, whereas eDP has the normal 1 line
851 * difference that earlier platforms have. External
852 * DP is unknown. For now just check for the 2 line
853 * difference case on all output types on HSW+.
855 * This might misinterpret the scanline counter being
856 * one line too far along on eDP, but that's less
857 * dangerous than the alternative since that would lead
858 * the vblank timestamp code astray when it sees a
859 * scanline count before vblank_start during a vblank
862 in_vbl
= ilk_pipe_in_vblank_locked(dev
, pipe
);
863 if ((in_vbl
&& (position
== vbl_start
- 2 ||
864 position
== vbl_start
- 1)) ||
865 (!in_vbl
&& (position
== vbl_end
- 2 ||
866 position
== vbl_end
- 1)))
867 position
= (position
+ 2) % vtotal
;
868 } else if (HAS_PCH_SPLIT(dev
)) {
870 * The scanline counter increments at the leading edge
871 * of hsync, ie. it completely misses the active portion
872 * of the line. Fix up the counter at both edges of vblank
873 * to get a more accurate picture whether we're in vblank
876 in_vbl
= ilk_pipe_in_vblank_locked(dev
, pipe
);
877 if ((in_vbl
&& position
== vbl_start
- 1) ||
878 (!in_vbl
&& position
== vbl_end
- 1))
879 position
= (position
+ 1) % vtotal
;
882 * ISR vblank status bits don't work the way we'd want
883 * them to work on non-PCH platforms (for
884 * ilk_pipe_in_vblank_locked()), and there doesn't
885 * appear any other way to determine if we're currently
888 * Instead let's assume that we're already in vblank if
889 * we got called from the vblank interrupt and the
890 * scanline counter value indicates that we're on the
891 * line just prior to vblank start. This should result
892 * in the correct answer, unless the vblank interrupt
893 * delivery really got delayed for almost exactly one
896 if (flags
& DRM_CALLED_FROM_VBLIRQ
&&
897 position
== vbl_start
- 1) {
898 position
= (position
+ 1) % vtotal
;
900 /* Signal this correction as "applied". */
905 /* Have access to pixelcount since start of frame.
906 * We can split this into vertical and horizontal
909 position
= (__raw_i915_read32(dev_priv
, PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
911 /* convert to pixel counts */
917 /* Get optional system timestamp after query. */
919 *etime
= ktime_get();
921 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
923 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
925 in_vbl
= position
>= vbl_start
&& position
< vbl_end
;
928 * While in vblank, position will be negative
929 * counting up towards 0 at vbl_end. And outside
930 * vblank, position will be positive counting
933 if (position
>= vbl_start
)
936 position
+= vtotal
- vbl_end
;
938 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
942 *vpos
= position
/ htotal
;
943 *hpos
= position
- (*vpos
* htotal
);
948 ret
|= DRM_SCANOUTPOS_INVBL
;
953 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
955 struct timeval
*vblank_time
,
958 struct drm_crtc
*crtc
;
960 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
961 DRM_ERROR("Invalid crtc %d\n", pipe
);
965 /* Get drm_crtc to timestamp: */
966 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
968 DRM_ERROR("Invalid crtc %d\n", pipe
);
972 if (!crtc
->enabled
) {
973 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
977 /* Helper routine in DRM core does all the work: */
978 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
981 &to_intel_crtc(crtc
)->config
.adjusted_mode
);
984 static bool intel_hpd_irq_event(struct drm_device
*dev
,
985 struct drm_connector
*connector
)
987 enum drm_connector_status old_status
;
989 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
990 old_status
= connector
->status
;
992 connector
->status
= connector
->funcs
->detect(connector
, false);
993 if (old_status
== connector
->status
)
996 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
998 drm_get_connector_name(connector
),
999 drm_get_connector_status_name(old_status
),
1000 drm_get_connector_status_name(connector
->status
));
1006 * Handle hotplug events outside the interrupt handler proper.
1008 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
1010 static void i915_hotplug_work_func(struct work_struct
*work
)
1012 struct drm_i915_private
*dev_priv
=
1013 container_of(work
, struct drm_i915_private
, hotplug_work
);
1014 struct drm_device
*dev
= dev_priv
->dev
;
1015 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
1016 struct intel_connector
*intel_connector
;
1017 struct intel_encoder
*intel_encoder
;
1018 struct drm_connector
*connector
;
1019 unsigned long irqflags
;
1020 bool hpd_disabled
= false;
1021 bool changed
= false;
1024 /* HPD irq before everything is fully set up. */
1025 if (!dev_priv
->enable_hotplug_processing
)
1028 mutex_lock(&mode_config
->mutex
);
1029 DRM_DEBUG_KMS("running encoder hotplug functions\n");
1031 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1033 hpd_event_bits
= dev_priv
->hpd_event_bits
;
1034 dev_priv
->hpd_event_bits
= 0;
1035 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
1036 intel_connector
= to_intel_connector(connector
);
1037 intel_encoder
= intel_connector
->encoder
;
1038 if (intel_encoder
->hpd_pin
> HPD_NONE
&&
1039 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_MARK_DISABLED
&&
1040 connector
->polled
== DRM_CONNECTOR_POLL_HPD
) {
1041 DRM_INFO("HPD interrupt storm detected on connector %s: "
1042 "switching from hotplug detection to polling\n",
1043 drm_get_connector_name(connector
));
1044 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
= HPD_DISABLED
;
1045 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
1046 | DRM_CONNECTOR_POLL_DISCONNECT
;
1047 hpd_disabled
= true;
1049 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
1050 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
1051 drm_get_connector_name(connector
), intel_encoder
->hpd_pin
);
1054 /* if there were no outputs to poll, poll was disabled,
1055 * therefore make sure it's enabled when disabling HPD on
1056 * some connectors */
1058 drm_kms_helper_poll_enable(dev
);
1059 mod_timer(&dev_priv
->hotplug_reenable_timer
,
1060 jiffies
+ msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY
));
1063 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1065 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
1066 intel_connector
= to_intel_connector(connector
);
1067 intel_encoder
= intel_connector
->encoder
;
1068 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
1069 if (intel_encoder
->hot_plug
)
1070 intel_encoder
->hot_plug(intel_encoder
);
1071 if (intel_hpd_irq_event(dev
, connector
))
1075 mutex_unlock(&mode_config
->mutex
);
1078 drm_kms_helper_hotplug_event(dev
);
1081 static void intel_hpd_irq_uninstall(struct drm_i915_private
*dev_priv
)
1083 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
1086 static void ironlake_rps_change_irq_handler(struct drm_device
*dev
)
1088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1089 u32 busy_up
, busy_down
, max_avg
, min_avg
;
1092 spin_lock(&mchdev_lock
);
1094 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
1096 new_delay
= dev_priv
->ips
.cur_delay
;
1098 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
1099 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
1100 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
1101 max_avg
= I915_READ(RCBMAXAVG
);
1102 min_avg
= I915_READ(RCBMINAVG
);
1104 /* Handle RCS change request from hw */
1105 if (busy_up
> max_avg
) {
1106 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
1107 new_delay
= dev_priv
->ips
.cur_delay
- 1;
1108 if (new_delay
< dev_priv
->ips
.max_delay
)
1109 new_delay
= dev_priv
->ips
.max_delay
;
1110 } else if (busy_down
< min_avg
) {
1111 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
1112 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
1113 if (new_delay
> dev_priv
->ips
.min_delay
)
1114 new_delay
= dev_priv
->ips
.min_delay
;
1117 if (ironlake_set_drps(dev
, new_delay
))
1118 dev_priv
->ips
.cur_delay
= new_delay
;
1120 spin_unlock(&mchdev_lock
);
1125 static void notify_ring(struct drm_device
*dev
,
1126 struct intel_ring_buffer
*ring
)
1128 if (ring
->obj
== NULL
)
1131 trace_i915_gem_request_complete(ring
);
1133 wake_up_all(&ring
->irq_queue
);
1134 i915_queue_hangcheck(dev
);
1137 static void gen6_pm_rps_work(struct work_struct
*work
)
1139 struct drm_i915_private
*dev_priv
=
1140 container_of(work
, struct drm_i915_private
, rps
.work
);
1144 spin_lock_irq(&dev_priv
->irq_lock
);
1145 pm_iir
= dev_priv
->rps
.pm_iir
;
1146 dev_priv
->rps
.pm_iir
= 0;
1147 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
1148 snb_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
1149 spin_unlock_irq(&dev_priv
->irq_lock
);
1151 /* Make sure we didn't queue anything we're not going to process. */
1152 WARN_ON(pm_iir
& ~dev_priv
->pm_rps_events
);
1154 if ((pm_iir
& dev_priv
->pm_rps_events
) == 0)
1157 mutex_lock(&dev_priv
->rps
.hw_lock
);
1159 adj
= dev_priv
->rps
.last_adj
;
1160 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
1165 new_delay
= dev_priv
->rps
.cur_freq
+ adj
;
1168 * For better performance, jump directly
1169 * to RPe if we're below it.
1171 if (new_delay
< dev_priv
->rps
.efficient_freq
)
1172 new_delay
= dev_priv
->rps
.efficient_freq
;
1173 } else if (pm_iir
& GEN6_PM_RP_DOWN_TIMEOUT
) {
1174 if (dev_priv
->rps
.cur_freq
> dev_priv
->rps
.efficient_freq
)
1175 new_delay
= dev_priv
->rps
.efficient_freq
;
1177 new_delay
= dev_priv
->rps
.min_freq_softlimit
;
1179 } else if (pm_iir
& GEN6_PM_RP_DOWN_THRESHOLD
) {
1184 new_delay
= dev_priv
->rps
.cur_freq
+ adj
;
1185 } else { /* unknown event */
1186 new_delay
= dev_priv
->rps
.cur_freq
;
1189 /* sysfs frequency interfaces may have snuck in while servicing the
1192 new_delay
= clamp_t(int, new_delay
,
1193 dev_priv
->rps
.min_freq_softlimit
,
1194 dev_priv
->rps
.max_freq_softlimit
);
1196 dev_priv
->rps
.last_adj
= new_delay
- dev_priv
->rps
.cur_freq
;
1198 if (IS_VALLEYVIEW(dev_priv
->dev
))
1199 valleyview_set_rps(dev_priv
->dev
, new_delay
);
1201 gen6_set_rps(dev_priv
->dev
, new_delay
);
1203 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1208 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1210 * @work: workqueue struct
1212 * Doesn't actually do anything except notify userspace. As a consequence of
1213 * this event, userspace should try to remap the bad rows since statistically
1214 * it is likely the same row is more likely to go bad again.
1216 static void ivybridge_parity_work(struct work_struct
*work
)
1218 struct drm_i915_private
*dev_priv
=
1219 container_of(work
, struct drm_i915_private
, l3_parity
.error_work
);
1220 u32 error_status
, row
, bank
, subbank
;
1221 char *parity_event
[6];
1223 unsigned long flags
;
1226 /* We must turn off DOP level clock gating to access the L3 registers.
1227 * In order to prevent a get/put style interface, acquire struct mutex
1228 * any time we access those registers.
1230 mutex_lock(&dev_priv
->dev
->struct_mutex
);
1232 /* If we've screwed up tracking, just let the interrupt fire again */
1233 if (WARN_ON(!dev_priv
->l3_parity
.which_slice
))
1236 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1237 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
1238 POSTING_READ(GEN7_MISCCPCTL
);
1240 while ((slice
= ffs(dev_priv
->l3_parity
.which_slice
)) != 0) {
1244 if (WARN_ON_ONCE(slice
>= NUM_L3_SLICES(dev_priv
->dev
)))
1247 dev_priv
->l3_parity
.which_slice
&= ~(1<<slice
);
1249 reg
= GEN7_L3CDERRST1
+ (slice
* 0x200);
1251 error_status
= I915_READ(reg
);
1252 row
= GEN7_PARITY_ERROR_ROW(error_status
);
1253 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
1254 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
1256 I915_WRITE(reg
, GEN7_PARITY_ERROR_VALID
| GEN7_L3CDERRST1_ENABLE
);
1259 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
1260 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
1261 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
1262 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
1263 parity_event
[4] = kasprintf(GFP_KERNEL
, "SLICE=%d", slice
);
1264 parity_event
[5] = NULL
;
1266 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
->kobj
,
1267 KOBJ_CHANGE
, parity_event
);
1269 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1270 slice
, row
, bank
, subbank
);
1272 kfree(parity_event
[4]);
1273 kfree(parity_event
[3]);
1274 kfree(parity_event
[2]);
1275 kfree(parity_event
[1]);
1278 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
1281 WARN_ON(dev_priv
->l3_parity
.which_slice
);
1282 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1283 ilk_enable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
->dev
));
1284 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1286 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
1289 static void ivybridge_parity_error_irq_handler(struct drm_device
*dev
, u32 iir
)
1291 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1293 if (!HAS_L3_DPF(dev
))
1296 spin_lock(&dev_priv
->irq_lock
);
1297 ilk_disable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev
));
1298 spin_unlock(&dev_priv
->irq_lock
);
1300 iir
&= GT_PARITY_ERROR(dev
);
1301 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1
)
1302 dev_priv
->l3_parity
.which_slice
|= 1 << 1;
1304 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
1305 dev_priv
->l3_parity
.which_slice
|= 1 << 0;
1307 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
1310 static void ilk_gt_irq_handler(struct drm_device
*dev
,
1311 struct drm_i915_private
*dev_priv
,
1315 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1316 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1317 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
1318 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1321 static void snb_gt_irq_handler(struct drm_device
*dev
,
1322 struct drm_i915_private
*dev_priv
,
1327 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1328 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1329 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
1330 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1331 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
1332 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
1334 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
1335 GT_BSD_CS_ERROR_INTERRUPT
|
1336 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
)) {
1337 i915_handle_error(dev
, false, "GT error interrupt 0x%08x",
1341 if (gt_iir
& GT_PARITY_ERROR(dev
))
1342 ivybridge_parity_error_irq_handler(dev
, gt_iir
);
1345 static irqreturn_t
gen8_gt_irq_handler(struct drm_device
*dev
,
1346 struct drm_i915_private
*dev_priv
,
1351 irqreturn_t ret
= IRQ_NONE
;
1353 if (master_ctl
& (GEN8_GT_RCS_IRQ
| GEN8_GT_BCS_IRQ
)) {
1354 tmp
= I915_READ(GEN8_GT_IIR(0));
1357 rcs
= tmp
>> GEN8_RCS_IRQ_SHIFT
;
1358 bcs
= tmp
>> GEN8_BCS_IRQ_SHIFT
;
1359 if (rcs
& GT_RENDER_USER_INTERRUPT
)
1360 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1361 if (bcs
& GT_RENDER_USER_INTERRUPT
)
1362 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
1363 I915_WRITE(GEN8_GT_IIR(0), tmp
);
1365 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1368 if (master_ctl
& GEN8_GT_VCS1_IRQ
) {
1369 tmp
= I915_READ(GEN8_GT_IIR(1));
1372 vcs
= tmp
>> GEN8_VCS1_IRQ_SHIFT
;
1373 if (vcs
& GT_RENDER_USER_INTERRUPT
)
1374 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1375 I915_WRITE(GEN8_GT_IIR(1), tmp
);
1377 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1380 if (master_ctl
& GEN8_GT_VECS_IRQ
) {
1381 tmp
= I915_READ(GEN8_GT_IIR(3));
1384 vcs
= tmp
>> GEN8_VECS_IRQ_SHIFT
;
1385 if (vcs
& GT_RENDER_USER_INTERRUPT
)
1386 notify_ring(dev
, &dev_priv
->ring
[VECS
]);
1387 I915_WRITE(GEN8_GT_IIR(3), tmp
);
1389 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1395 #define HPD_STORM_DETECT_PERIOD 1000
1396 #define HPD_STORM_THRESHOLD 5
1398 static inline void intel_hpd_irq_handler(struct drm_device
*dev
,
1399 u32 hotplug_trigger
,
1402 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1404 bool storm_detected
= false;
1406 if (!hotplug_trigger
)
1409 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1412 spin_lock(&dev_priv
->irq_lock
);
1413 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
1415 WARN_ONCE(hpd
[i
] & hotplug_trigger
&&
1416 dev_priv
->hpd_stats
[i
].hpd_mark
== HPD_DISABLED
,
1417 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1418 hotplug_trigger
, i
, hpd
[i
]);
1420 if (!(hpd
[i
] & hotplug_trigger
) ||
1421 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
)
1424 dev_priv
->hpd_event_bits
|= (1 << i
);
1425 if (!time_in_range(jiffies
, dev_priv
->hpd_stats
[i
].hpd_last_jiffies
,
1426 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
1427 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD
))) {
1428 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
= jiffies
;
1429 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
1430 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i
);
1431 } else if (dev_priv
->hpd_stats
[i
].hpd_cnt
> HPD_STORM_THRESHOLD
) {
1432 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_MARK_DISABLED
;
1433 dev_priv
->hpd_event_bits
&= ~(1 << i
);
1434 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i
);
1435 storm_detected
= true;
1437 dev_priv
->hpd_stats
[i
].hpd_cnt
++;
1438 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i
,
1439 dev_priv
->hpd_stats
[i
].hpd_cnt
);
1444 dev_priv
->display
.hpd_irq_setup(dev
);
1445 spin_unlock(&dev_priv
->irq_lock
);
1448 * Our hotplug handler can grab modeset locks (by calling down into the
1449 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1450 * queue for otherwise the flush_work in the pageflip code will
1453 schedule_work(&dev_priv
->hotplug_work
);
1456 static void gmbus_irq_handler(struct drm_device
*dev
)
1458 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1460 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1463 static void dp_aux_irq_handler(struct drm_device
*dev
)
1465 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1467 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1470 #if defined(CONFIG_DEBUG_FS)
1471 static void display_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
,
1472 uint32_t crc0
, uint32_t crc1
,
1473 uint32_t crc2
, uint32_t crc3
,
1476 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1477 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
1478 struct intel_pipe_crc_entry
*entry
;
1481 spin_lock(&pipe_crc
->lock
);
1483 if (!pipe_crc
->entries
) {
1484 spin_unlock(&pipe_crc
->lock
);
1485 DRM_ERROR("spurious interrupt\n");
1489 head
= pipe_crc
->head
;
1490 tail
= pipe_crc
->tail
;
1492 if (CIRC_SPACE(head
, tail
, INTEL_PIPE_CRC_ENTRIES_NR
) < 1) {
1493 spin_unlock(&pipe_crc
->lock
);
1494 DRM_ERROR("CRC buffer overflowing\n");
1498 entry
= &pipe_crc
->entries
[head
];
1500 entry
->frame
= dev
->driver
->get_vblank_counter(dev
, pipe
);
1501 entry
->crc
[0] = crc0
;
1502 entry
->crc
[1] = crc1
;
1503 entry
->crc
[2] = crc2
;
1504 entry
->crc
[3] = crc3
;
1505 entry
->crc
[4] = crc4
;
1507 head
= (head
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
1508 pipe_crc
->head
= head
;
1510 spin_unlock(&pipe_crc
->lock
);
1512 wake_up_interruptible(&pipe_crc
->wq
);
1516 display_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
,
1517 uint32_t crc0
, uint32_t crc1
,
1518 uint32_t crc2
, uint32_t crc3
,
1523 static void hsw_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1525 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1527 display_pipe_crc_irq_handler(dev
, pipe
,
1528 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1532 static void ivb_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1534 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1536 display_pipe_crc_irq_handler(dev
, pipe
,
1537 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1538 I915_READ(PIPE_CRC_RES_2_IVB(pipe
)),
1539 I915_READ(PIPE_CRC_RES_3_IVB(pipe
)),
1540 I915_READ(PIPE_CRC_RES_4_IVB(pipe
)),
1541 I915_READ(PIPE_CRC_RES_5_IVB(pipe
)));
1544 static void i9xx_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1546 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1547 uint32_t res1
, res2
;
1549 if (INTEL_INFO(dev
)->gen
>= 3)
1550 res1
= I915_READ(PIPE_CRC_RES_RES1_I915(pipe
));
1554 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
1555 res2
= I915_READ(PIPE_CRC_RES_RES2_G4X(pipe
));
1559 display_pipe_crc_irq_handler(dev
, pipe
,
1560 I915_READ(PIPE_CRC_RES_RED(pipe
)),
1561 I915_READ(PIPE_CRC_RES_GREEN(pipe
)),
1562 I915_READ(PIPE_CRC_RES_BLUE(pipe
)),
1566 /* The RPS events need forcewake, so we add them to a work queue and mask their
1567 * IMR bits until the work is done. Other interrupts can be processed without
1568 * the work queue. */
1569 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1571 if (pm_iir
& dev_priv
->pm_rps_events
) {
1572 spin_lock(&dev_priv
->irq_lock
);
1573 dev_priv
->rps
.pm_iir
|= pm_iir
& dev_priv
->pm_rps_events
;
1574 snb_disable_pm_irq(dev_priv
, pm_iir
& dev_priv
->pm_rps_events
);
1575 spin_unlock(&dev_priv
->irq_lock
);
1577 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
1580 if (HAS_VEBOX(dev_priv
->dev
)) {
1581 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1582 notify_ring(dev_priv
->dev
, &dev_priv
->ring
[VECS
]);
1584 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
) {
1585 i915_handle_error(dev_priv
->dev
, false,
1586 "VEBOX CS error interrupt 0x%08x",
1592 static void valleyview_pipestat_irq_handler(struct drm_device
*dev
, u32 iir
)
1594 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1595 u32 pipe_stats
[I915_MAX_PIPES
] = { };
1598 spin_lock(&dev_priv
->irq_lock
);
1599 for_each_pipe(pipe
) {
1601 u32 mask
, iir_bit
= 0;
1604 * PIPESTAT bits get signalled even when the interrupt is
1605 * disabled with the mask bits, and some of the status bits do
1606 * not generate interrupts at all (like the underrun bit). Hence
1607 * we need to be careful that we only handle what we want to
1611 if (__cpu_fifo_underrun_reporting_enabled(dev
, pipe
))
1612 mask
|= PIPE_FIFO_UNDERRUN_STATUS
;
1616 iir_bit
= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
;
1619 iir_bit
= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
1623 mask
|= dev_priv
->pipestat_irq_mask
[pipe
];
1628 reg
= PIPESTAT(pipe
);
1629 mask
|= PIPESTAT_INT_ENABLE_MASK
;
1630 pipe_stats
[pipe
] = I915_READ(reg
) & mask
;
1633 * Clear the PIPE*STAT regs before the IIR
1635 if (pipe_stats
[pipe
] & (PIPE_FIFO_UNDERRUN_STATUS
|
1636 PIPESTAT_INT_STATUS_MASK
))
1637 I915_WRITE(reg
, pipe_stats
[pipe
]);
1639 spin_unlock(&dev_priv
->irq_lock
);
1641 for_each_pipe(pipe
) {
1642 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
)
1643 drm_handle_vblank(dev
, pipe
);
1645 if (pipe_stats
[pipe
] & PLANE_FLIP_DONE_INT_STATUS_VLV
) {
1646 intel_prepare_page_flip(dev
, pipe
);
1647 intel_finish_page_flip(dev
, pipe
);
1650 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
1651 i9xx_pipe_crc_irq_handler(dev
, pipe
);
1653 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
&&
1654 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false))
1655 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe
));
1658 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1659 gmbus_irq_handler(dev
);
1662 static void i9xx_hpd_irq_handler(struct drm_device
*dev
)
1664 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1665 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1668 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_G4X
;
1670 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_g4x
);
1672 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1674 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
1677 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) &&
1678 hotplug_status
& DP_AUX_CHANNEL_MASK_INT_STATUS_G4X
)
1679 dp_aux_irq_handler(dev
);
1681 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1683 * Make sure hotplug status is cleared before we clear IIR, or else we
1684 * may miss hotplug events.
1686 POSTING_READ(PORT_HOTPLUG_STAT
);
1689 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1691 struct drm_device
*dev
= (struct drm_device
*) arg
;
1692 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1693 u32 iir
, gt_iir
, pm_iir
;
1694 irqreturn_t ret
= IRQ_NONE
;
1697 iir
= I915_READ(VLV_IIR
);
1698 gt_iir
= I915_READ(GTIIR
);
1699 pm_iir
= I915_READ(GEN6_PMIIR
);
1701 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1706 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1708 valleyview_pipestat_irq_handler(dev
, iir
);
1710 /* Consume port. Then clear IIR or we'll miss events */
1711 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1712 i9xx_hpd_irq_handler(dev
);
1715 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1717 I915_WRITE(GTIIR
, gt_iir
);
1718 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1719 I915_WRITE(VLV_IIR
, iir
);
1726 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1728 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1730 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1732 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ibx
);
1734 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1735 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1736 SDE_AUDIO_POWER_SHIFT
);
1737 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1741 if (pch_iir
& SDE_AUX_MASK
)
1742 dp_aux_irq_handler(dev
);
1744 if (pch_iir
& SDE_GMBUS
)
1745 gmbus_irq_handler(dev
);
1747 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1748 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1750 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1751 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1753 if (pch_iir
& SDE_POISON
)
1754 DRM_ERROR("PCH poison interrupt\n");
1756 if (pch_iir
& SDE_FDI_MASK
)
1758 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1760 I915_READ(FDI_RX_IIR(pipe
)));
1762 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1763 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1765 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1766 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1768 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1769 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1771 DRM_ERROR("PCH transcoder A FIFO underrun\n");
1773 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1774 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1776 DRM_ERROR("PCH transcoder B FIFO underrun\n");
1779 static void ivb_err_int_handler(struct drm_device
*dev
)
1781 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1782 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1785 if (err_int
& ERR_INT_POISON
)
1786 DRM_ERROR("Poison interrupt\n");
1788 for_each_pipe(pipe
) {
1789 if (err_int
& ERR_INT_FIFO_UNDERRUN(pipe
)) {
1790 if (intel_set_cpu_fifo_underrun_reporting(dev
, pipe
,
1792 DRM_ERROR("Pipe %c FIFO underrun\n",
1796 if (err_int
& ERR_INT_PIPE_CRC_DONE(pipe
)) {
1797 if (IS_IVYBRIDGE(dev
))
1798 ivb_pipe_crc_irq_handler(dev
, pipe
);
1800 hsw_pipe_crc_irq_handler(dev
, pipe
);
1804 I915_WRITE(GEN7_ERR_INT
, err_int
);
1807 static void cpt_serr_int_handler(struct drm_device
*dev
)
1809 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1810 u32 serr_int
= I915_READ(SERR_INT
);
1812 if (serr_int
& SERR_INT_POISON
)
1813 DRM_ERROR("PCH poison interrupt\n");
1815 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
1816 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1818 DRM_ERROR("PCH transcoder A FIFO underrun\n");
1820 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
1821 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1823 DRM_ERROR("PCH transcoder B FIFO underrun\n");
1825 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
1826 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_C
,
1828 DRM_ERROR("PCH transcoder C FIFO underrun\n");
1830 I915_WRITE(SERR_INT
, serr_int
);
1833 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1835 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1837 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
1839 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_cpt
);
1841 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
1842 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
1843 SDE_AUDIO_POWER_SHIFT_CPT
);
1844 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1848 if (pch_iir
& SDE_AUX_MASK_CPT
)
1849 dp_aux_irq_handler(dev
);
1851 if (pch_iir
& SDE_GMBUS_CPT
)
1852 gmbus_irq_handler(dev
);
1854 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
1855 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1857 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
1858 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1860 if (pch_iir
& SDE_FDI_MASK_CPT
)
1862 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1864 I915_READ(FDI_RX_IIR(pipe
)));
1866 if (pch_iir
& SDE_ERROR_CPT
)
1867 cpt_serr_int_handler(dev
);
1870 static void ilk_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1872 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1875 if (de_iir
& DE_AUX_CHANNEL_A
)
1876 dp_aux_irq_handler(dev
);
1878 if (de_iir
& DE_GSE
)
1879 intel_opregion_asle_intr(dev
);
1881 if (de_iir
& DE_POISON
)
1882 DRM_ERROR("Poison interrupt\n");
1884 for_each_pipe(pipe
) {
1885 if (de_iir
& DE_PIPE_VBLANK(pipe
))
1886 drm_handle_vblank(dev
, pipe
);
1888 if (de_iir
& DE_PIPE_FIFO_UNDERRUN(pipe
))
1889 if (intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false))
1890 DRM_ERROR("Pipe %c FIFO underrun\n",
1893 if (de_iir
& DE_PIPE_CRC_DONE(pipe
))
1894 i9xx_pipe_crc_irq_handler(dev
, pipe
);
1896 /* plane/pipes map 1:1 on ilk+ */
1897 if (de_iir
& DE_PLANE_FLIP_DONE(pipe
)) {
1898 intel_prepare_page_flip(dev
, pipe
);
1899 intel_finish_page_flip_plane(dev
, pipe
);
1903 /* check event from PCH */
1904 if (de_iir
& DE_PCH_EVENT
) {
1905 u32 pch_iir
= I915_READ(SDEIIR
);
1907 if (HAS_PCH_CPT(dev
))
1908 cpt_irq_handler(dev
, pch_iir
);
1910 ibx_irq_handler(dev
, pch_iir
);
1912 /* should clear PCH hotplug event before clear CPU irq */
1913 I915_WRITE(SDEIIR
, pch_iir
);
1916 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
1917 ironlake_rps_change_irq_handler(dev
);
1920 static void ivb_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1922 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1925 if (de_iir
& DE_ERR_INT_IVB
)
1926 ivb_err_int_handler(dev
);
1928 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
1929 dp_aux_irq_handler(dev
);
1931 if (de_iir
& DE_GSE_IVB
)
1932 intel_opregion_asle_intr(dev
);
1934 for_each_pipe(pipe
) {
1935 if (de_iir
& (DE_PIPE_VBLANK_IVB(pipe
)))
1936 drm_handle_vblank(dev
, pipe
);
1938 /* plane/pipes map 1:1 on ilk+ */
1939 if (de_iir
& DE_PLANE_FLIP_DONE_IVB(pipe
)) {
1940 intel_prepare_page_flip(dev
, pipe
);
1941 intel_finish_page_flip_plane(dev
, pipe
);
1945 /* check event from PCH */
1946 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
1947 u32 pch_iir
= I915_READ(SDEIIR
);
1949 cpt_irq_handler(dev
, pch_iir
);
1951 /* clear PCH hotplug event before clear CPU irq */
1952 I915_WRITE(SDEIIR
, pch_iir
);
1956 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
1958 struct drm_device
*dev
= (struct drm_device
*) arg
;
1959 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1960 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
1961 irqreturn_t ret
= IRQ_NONE
;
1963 /* We get interrupts on unclaimed registers, so check for this before we
1964 * do any I915_{READ,WRITE}. */
1965 intel_uncore_check_errors(dev
);
1967 /* disable master interrupt before clearing iir */
1968 de_ier
= I915_READ(DEIER
);
1969 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
1970 POSTING_READ(DEIER
);
1972 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1973 * interrupts will will be stored on its back queue, and then we'll be
1974 * able to process them after we restore SDEIER (as soon as we restore
1975 * it, we'll get an interrupt if SDEIIR still has something to process
1976 * due to its back queue). */
1977 if (!HAS_PCH_NOP(dev
)) {
1978 sde_ier
= I915_READ(SDEIER
);
1979 I915_WRITE(SDEIER
, 0);
1980 POSTING_READ(SDEIER
);
1983 gt_iir
= I915_READ(GTIIR
);
1985 if (INTEL_INFO(dev
)->gen
>= 6)
1986 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1988 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1989 I915_WRITE(GTIIR
, gt_iir
);
1993 de_iir
= I915_READ(DEIIR
);
1995 if (INTEL_INFO(dev
)->gen
>= 7)
1996 ivb_display_irq_handler(dev
, de_iir
);
1998 ilk_display_irq_handler(dev
, de_iir
);
1999 I915_WRITE(DEIIR
, de_iir
);
2003 if (INTEL_INFO(dev
)->gen
>= 6) {
2004 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
2006 gen6_rps_irq_handler(dev_priv
, pm_iir
);
2007 I915_WRITE(GEN6_PMIIR
, pm_iir
);
2012 I915_WRITE(DEIER
, de_ier
);
2013 POSTING_READ(DEIER
);
2014 if (!HAS_PCH_NOP(dev
)) {
2015 I915_WRITE(SDEIER
, sde_ier
);
2016 POSTING_READ(SDEIER
);
2022 static irqreturn_t
gen8_irq_handler(int irq
, void *arg
)
2024 struct drm_device
*dev
= arg
;
2025 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2027 irqreturn_t ret
= IRQ_NONE
;
2031 master_ctl
= I915_READ(GEN8_MASTER_IRQ
);
2032 master_ctl
&= ~GEN8_MASTER_IRQ_CONTROL
;
2036 I915_WRITE(GEN8_MASTER_IRQ
, 0);
2037 POSTING_READ(GEN8_MASTER_IRQ
);
2039 ret
= gen8_gt_irq_handler(dev
, dev_priv
, master_ctl
);
2041 if (master_ctl
& GEN8_DE_MISC_IRQ
) {
2042 tmp
= I915_READ(GEN8_DE_MISC_IIR
);
2043 if (tmp
& GEN8_DE_MISC_GSE
)
2044 intel_opregion_asle_intr(dev
);
2046 DRM_ERROR("Unexpected DE Misc interrupt\n");
2048 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2051 I915_WRITE(GEN8_DE_MISC_IIR
, tmp
);
2056 if (master_ctl
& GEN8_DE_PORT_IRQ
) {
2057 tmp
= I915_READ(GEN8_DE_PORT_IIR
);
2058 if (tmp
& GEN8_AUX_CHANNEL_A
)
2059 dp_aux_irq_handler(dev
);
2061 DRM_ERROR("Unexpected DE Port interrupt\n");
2063 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2066 I915_WRITE(GEN8_DE_PORT_IIR
, tmp
);
2071 for_each_pipe(pipe
) {
2074 if (!(master_ctl
& GEN8_DE_PIPE_IRQ(pipe
)))
2077 pipe_iir
= I915_READ(GEN8_DE_PIPE_IIR(pipe
));
2078 if (pipe_iir
& GEN8_PIPE_VBLANK
)
2079 drm_handle_vblank(dev
, pipe
);
2081 if (pipe_iir
& GEN8_PIPE_FLIP_DONE
) {
2082 intel_prepare_page_flip(dev
, pipe
);
2083 intel_finish_page_flip_plane(dev
, pipe
);
2086 if (pipe_iir
& GEN8_PIPE_CDCLK_CRC_DONE
)
2087 hsw_pipe_crc_irq_handler(dev
, pipe
);
2089 if (pipe_iir
& GEN8_PIPE_FIFO_UNDERRUN
) {
2090 if (intel_set_cpu_fifo_underrun_reporting(dev
, pipe
,
2092 DRM_ERROR("Pipe %c FIFO underrun\n",
2096 if (pipe_iir
& GEN8_DE_PIPE_IRQ_FAULT_ERRORS
) {
2097 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2099 pipe_iir
& GEN8_DE_PIPE_IRQ_FAULT_ERRORS
);
2104 I915_WRITE(GEN8_DE_PIPE_IIR(pipe
), pipe_iir
);
2106 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2109 if (!HAS_PCH_NOP(dev
) && master_ctl
& GEN8_DE_PCH_IRQ
) {
2111 * FIXME(BDW): Assume for now that the new interrupt handling
2112 * scheme also closed the SDE interrupt handling race we've seen
2113 * on older pch-split platforms. But this needs testing.
2115 u32 pch_iir
= I915_READ(SDEIIR
);
2117 cpt_irq_handler(dev
, pch_iir
);
2120 I915_WRITE(SDEIIR
, pch_iir
);
2125 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
2126 POSTING_READ(GEN8_MASTER_IRQ
);
2131 static void i915_error_wake_up(struct drm_i915_private
*dev_priv
,
2132 bool reset_completed
)
2134 struct intel_ring_buffer
*ring
;
2138 * Notify all waiters for GPU completion events that reset state has
2139 * been changed, and that they need to restart their wait after
2140 * checking for potential errors (and bail out to drop locks if there is
2141 * a gpu reset pending so that i915_error_work_func can acquire them).
2144 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2145 for_each_ring(ring
, dev_priv
, i
)
2146 wake_up_all(&ring
->irq_queue
);
2148 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2149 wake_up_all(&dev_priv
->pending_flip_queue
);
2152 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2153 * reset state is cleared.
2155 if (reset_completed
)
2156 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
2160 * i915_error_work_func - do process context error handling work
2161 * @work: work struct
2163 * Fire an error uevent so userspace can see that a hang or error
2166 static void i915_error_work_func(struct work_struct
*work
)
2168 struct i915_gpu_error
*error
= container_of(work
, struct i915_gpu_error
,
2170 struct drm_i915_private
*dev_priv
=
2171 container_of(error
, struct drm_i915_private
, gpu_error
);
2172 struct drm_device
*dev
= dev_priv
->dev
;
2173 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
2174 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
2175 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
2178 kobject_uevent_env(&dev
->primary
->kdev
->kobj
, KOBJ_CHANGE
, error_event
);
2181 * Note that there's only one work item which does gpu resets, so we
2182 * need not worry about concurrent gpu resets potentially incrementing
2183 * error->reset_counter twice. We only need to take care of another
2184 * racing irq/hangcheck declaring the gpu dead for a second time. A
2185 * quick check for that is good enough: schedule_work ensures the
2186 * correct ordering between hang detection and this work item, and since
2187 * the reset in-progress bit is only ever set by code outside of this
2188 * work we don't need to worry about any other races.
2190 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
2191 DRM_DEBUG_DRIVER("resetting chip\n");
2192 kobject_uevent_env(&dev
->primary
->kdev
->kobj
, KOBJ_CHANGE
,
2196 * All state reset _must_ be completed before we update the
2197 * reset counter, for otherwise waiters might miss the reset
2198 * pending state and not properly drop locks, resulting in
2199 * deadlocks with the reset work.
2201 ret
= i915_reset(dev
);
2203 intel_display_handle_reset(dev
);
2207 * After all the gem state is reset, increment the reset
2208 * counter and wake up everyone waiting for the reset to
2211 * Since unlock operations are a one-sided barrier only,
2212 * we need to insert a barrier here to order any seqno
2214 * the counter increment.
2216 smp_mb__before_atomic_inc();
2217 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
2219 kobject_uevent_env(&dev
->primary
->kdev
->kobj
,
2220 KOBJ_CHANGE
, reset_done_event
);
2222 atomic_set_mask(I915_WEDGED
, &error
->reset_counter
);
2226 * Note: The wake_up also serves as a memory barrier so that
2227 * waiters see the update value of the reset counter atomic_t.
2229 i915_error_wake_up(dev_priv
, true);
2233 static void i915_report_and_clear_eir(struct drm_device
*dev
)
2235 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2236 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
2237 u32 eir
= I915_READ(EIR
);
2243 pr_err("render error detected, EIR: 0x%08x\n", eir
);
2245 i915_get_extra_instdone(dev
, instdone
);
2248 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
2249 u32 ipeir
= I915_READ(IPEIR_I965
);
2251 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2252 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2253 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2254 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2255 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2256 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2257 I915_WRITE(IPEIR_I965
, ipeir
);
2258 POSTING_READ(IPEIR_I965
);
2260 if (eir
& GM45_ERROR_PAGE_TABLE
) {
2261 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2262 pr_err("page table error\n");
2263 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2264 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2265 POSTING_READ(PGTBL_ER
);
2269 if (!IS_GEN2(dev
)) {
2270 if (eir
& I915_ERROR_PAGE_TABLE
) {
2271 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2272 pr_err("page table error\n");
2273 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2274 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2275 POSTING_READ(PGTBL_ER
);
2279 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
2280 pr_err("memory refresh error:\n");
2282 pr_err("pipe %c stat: 0x%08x\n",
2283 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
2284 /* pipestat has already been acked */
2286 if (eir
& I915_ERROR_INSTRUCTION
) {
2287 pr_err("instruction error\n");
2288 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
2289 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2290 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2291 if (INTEL_INFO(dev
)->gen
< 4) {
2292 u32 ipeir
= I915_READ(IPEIR
);
2294 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
2295 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
2296 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
2297 I915_WRITE(IPEIR
, ipeir
);
2298 POSTING_READ(IPEIR
);
2300 u32 ipeir
= I915_READ(IPEIR_I965
);
2302 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2303 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2304 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2305 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2306 I915_WRITE(IPEIR_I965
, ipeir
);
2307 POSTING_READ(IPEIR_I965
);
2311 I915_WRITE(EIR
, eir
);
2313 eir
= I915_READ(EIR
);
2316 * some errors might have become stuck,
2319 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
2320 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
2321 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2326 * i915_handle_error - handle an error interrupt
2329 * Do some basic checking of regsiter state at error interrupt time and
2330 * dump it to the syslog. Also call i915_capture_error_state() to make
2331 * sure we get a record and make it available in debugfs. Fire a uevent
2332 * so userspace knows something bad happened (should trigger collection
2333 * of a ring dump etc.).
2335 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2336 const char *fmt
, ...)
2338 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2342 va_start(args
, fmt
);
2343 vscnprintf(error_msg
, sizeof(error_msg
), fmt
, args
);
2346 i915_capture_error_state(dev
, wedged
, error_msg
);
2347 i915_report_and_clear_eir(dev
);
2350 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
2351 &dev_priv
->gpu_error
.reset_counter
);
2354 * Wakeup waiting processes so that the reset work function
2355 * i915_error_work_func doesn't deadlock trying to grab various
2356 * locks. By bumping the reset counter first, the woken
2357 * processes will see a reset in progress and back off,
2358 * releasing their locks and then wait for the reset completion.
2359 * We must do this for _all_ gpu waiters that might hold locks
2360 * that the reset work needs to acquire.
2362 * Note: The wake_up serves as the required memory barrier to
2363 * ensure that the waiters see the updated value of the reset
2366 i915_error_wake_up(dev_priv
, false);
2370 * Our reset work can grab modeset locks (since it needs to reset the
2371 * state of outstanding pagelips). Hence it must not be run on our own
2372 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2373 * code will deadlock.
2375 schedule_work(&dev_priv
->gpu_error
.work
);
2378 static void __always_unused
i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
2380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2381 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
2382 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2383 struct drm_i915_gem_object
*obj
;
2384 struct intel_unpin_work
*work
;
2385 unsigned long flags
;
2386 bool stall_detected
;
2388 /* Ignore early vblank irqs */
2389 if (intel_crtc
== NULL
)
2392 spin_lock_irqsave(&dev
->event_lock
, flags
);
2393 work
= intel_crtc
->unpin_work
;
2396 atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
||
2397 !work
->enable_stall_check
) {
2398 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2399 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2403 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2404 obj
= work
->pending_flip_obj
;
2405 if (INTEL_INFO(dev
)->gen
>= 4) {
2406 int dspsurf
= DSPSURF(intel_crtc
->plane
);
2407 stall_detected
= I915_HI_DISPBASE(I915_READ(dspsurf
)) ==
2408 i915_gem_obj_ggtt_offset(obj
);
2410 int dspaddr
= DSPADDR(intel_crtc
->plane
);
2411 stall_detected
= I915_READ(dspaddr
) == (i915_gem_obj_ggtt_offset(obj
) +
2412 crtc
->y
* crtc
->fb
->pitches
[0] +
2413 crtc
->x
* crtc
->fb
->bits_per_pixel
/8);
2416 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2418 if (stall_detected
) {
2419 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2420 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
2424 /* Called from drm generic code, passed 'crtc' which
2425 * we use as a pipe index
2427 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
2429 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2430 unsigned long irqflags
;
2432 if (!i915_pipe_enabled(dev
, pipe
))
2435 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2436 if (INTEL_INFO(dev
)->gen
>= 4)
2437 i915_enable_pipestat(dev_priv
, pipe
,
2438 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2440 i915_enable_pipestat(dev_priv
, pipe
,
2441 PIPE_VBLANK_INTERRUPT_STATUS
);
2443 /* maintain vblank delivery even in deep C-states */
2444 if (INTEL_INFO(dev
)->gen
== 3)
2445 I915_WRITE(INSTPM
, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS
));
2446 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2451 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
2453 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2454 unsigned long irqflags
;
2455 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2456 DE_PIPE_VBLANK(pipe
);
2458 if (!i915_pipe_enabled(dev
, pipe
))
2461 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2462 ironlake_enable_display_irq(dev_priv
, bit
);
2463 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2468 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
2470 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2471 unsigned long irqflags
;
2473 if (!i915_pipe_enabled(dev
, pipe
))
2476 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2477 i915_enable_pipestat(dev_priv
, pipe
,
2478 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2479 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2484 static int gen8_enable_vblank(struct drm_device
*dev
, int pipe
)
2486 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2487 unsigned long irqflags
;
2489 if (!i915_pipe_enabled(dev
, pipe
))
2492 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2493 dev_priv
->de_irq_mask
[pipe
] &= ~GEN8_PIPE_VBLANK
;
2494 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
2495 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
2496 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2500 /* Called from drm generic code, passed 'crtc' which
2501 * we use as a pipe index
2503 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
2505 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2506 unsigned long irqflags
;
2508 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2509 if (INTEL_INFO(dev
)->gen
== 3)
2510 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS
));
2512 i915_disable_pipestat(dev_priv
, pipe
,
2513 PIPE_VBLANK_INTERRUPT_STATUS
|
2514 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2515 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2518 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
2520 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2521 unsigned long irqflags
;
2522 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2523 DE_PIPE_VBLANK(pipe
);
2525 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2526 ironlake_disable_display_irq(dev_priv
, bit
);
2527 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2530 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
2532 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2533 unsigned long irqflags
;
2535 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2536 i915_disable_pipestat(dev_priv
, pipe
,
2537 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2538 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2541 static void gen8_disable_vblank(struct drm_device
*dev
, int pipe
)
2543 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2544 unsigned long irqflags
;
2546 if (!i915_pipe_enabled(dev
, pipe
))
2549 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2550 dev_priv
->de_irq_mask
[pipe
] |= GEN8_PIPE_VBLANK
;
2551 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
2552 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
2553 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2557 ring_last_seqno(struct intel_ring_buffer
*ring
)
2559 return list_entry(ring
->request_list
.prev
,
2560 struct drm_i915_gem_request
, list
)->seqno
;
2564 ring_idle(struct intel_ring_buffer
*ring
, u32 seqno
)
2566 return (list_empty(&ring
->request_list
) ||
2567 i915_seqno_passed(seqno
, ring_last_seqno(ring
)));
2571 ipehr_is_semaphore_wait(struct drm_device
*dev
, u32 ipehr
)
2573 if (INTEL_INFO(dev
)->gen
>= 8) {
2575 * FIXME: gen8 semaphore support - currently we don't emit
2576 * semaphores on bdw anyway, but this needs to be addressed when
2577 * we merge that code.
2581 ipehr
&= ~MI_SEMAPHORE_SYNC_MASK
;
2582 return ipehr
== (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
|
2583 MI_SEMAPHORE_REGISTER
);
2587 static struct intel_ring_buffer
*
2588 semaphore_wait_to_signaller_ring(struct intel_ring_buffer
*ring
, u32 ipehr
)
2590 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2591 struct intel_ring_buffer
*signaller
;
2594 if (INTEL_INFO(dev_priv
->dev
)->gen
>= 8) {
2596 * FIXME: gen8 semaphore support - currently we don't emit
2597 * semaphores on bdw anyway, but this needs to be addressed when
2598 * we merge that code.
2602 u32 sync_bits
= ipehr
& MI_SEMAPHORE_SYNC_MASK
;
2604 for_each_ring(signaller
, dev_priv
, i
) {
2605 if(ring
== signaller
)
2609 signaller
->semaphore_register
[ring
->id
])
2614 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x\n",
2620 static struct intel_ring_buffer
*
2621 semaphore_waits_for(struct intel_ring_buffer
*ring
, u32
*seqno
)
2623 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2624 u32 cmd
, ipehr
, head
;
2627 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
2628 if (!ipehr_is_semaphore_wait(ring
->dev
, ipehr
))
2632 * HEAD is likely pointing to the dword after the actual command,
2633 * so scan backwards until we find the MBOX. But limit it to just 3
2634 * dwords. Note that we don't care about ACTHD here since that might
2635 * point at at batch, and semaphores are always emitted into the
2636 * ringbuffer itself.
2638 head
= I915_READ_HEAD(ring
) & HEAD_ADDR
;
2640 for (i
= 4; i
; --i
) {
2642 * Be paranoid and presume the hw has gone off into the wild -
2643 * our ring is smaller than what the hardware (and hence
2644 * HEAD_ADDR) allows. Also handles wrap-around.
2646 head
&= ring
->size
- 1;
2648 /* This here seems to blow up */
2649 cmd
= ioread32(ring
->virtual_start
+ head
);
2659 *seqno
= ioread32(ring
->virtual_start
+ head
+ 4) + 1;
2660 return semaphore_wait_to_signaller_ring(ring
, ipehr
);
2663 static int semaphore_passed(struct intel_ring_buffer
*ring
)
2665 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2666 struct intel_ring_buffer
*signaller
;
2669 ring
->hangcheck
.deadlock
= true;
2671 signaller
= semaphore_waits_for(ring
, &seqno
);
2672 if (signaller
== NULL
|| signaller
->hangcheck
.deadlock
)
2675 /* cursory check for an unkickable deadlock */
2676 ctl
= I915_READ_CTL(signaller
);
2677 if (ctl
& RING_WAIT_SEMAPHORE
&& semaphore_passed(signaller
) < 0)
2680 return i915_seqno_passed(signaller
->get_seqno(signaller
, false), seqno
);
2683 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
2685 struct intel_ring_buffer
*ring
;
2688 for_each_ring(ring
, dev_priv
, i
)
2689 ring
->hangcheck
.deadlock
= false;
2692 static enum intel_ring_hangcheck_action
2693 ring_stuck(struct intel_ring_buffer
*ring
, u64 acthd
)
2695 struct drm_device
*dev
= ring
->dev
;
2696 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2699 if (ring
->hangcheck
.acthd
!= acthd
)
2700 return HANGCHECK_ACTIVE
;
2703 return HANGCHECK_HUNG
;
2705 /* Is the chip hanging on a WAIT_FOR_EVENT?
2706 * If so we can simply poke the RB_WAIT bit
2707 * and break the hang. This should work on
2708 * all but the second generation chipsets.
2710 tmp
= I915_READ_CTL(ring
);
2711 if (tmp
& RING_WAIT
) {
2712 i915_handle_error(dev
, false,
2713 "Kicking stuck wait on %s",
2715 I915_WRITE_CTL(ring
, tmp
);
2716 return HANGCHECK_KICK
;
2719 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
2720 switch (semaphore_passed(ring
)) {
2722 return HANGCHECK_HUNG
;
2724 i915_handle_error(dev
, false,
2725 "Kicking stuck semaphore on %s",
2727 I915_WRITE_CTL(ring
, tmp
);
2728 return HANGCHECK_KICK
;
2730 return HANGCHECK_WAIT
;
2734 return HANGCHECK_HUNG
;
2738 * This is called when the chip hasn't reported back with completed
2739 * batchbuffers in a long time. We keep track per ring seqno progress and
2740 * if there are no progress, hangcheck score for that ring is increased.
2741 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2742 * we kick the ring. If we see no progress on three subsequent calls
2743 * we assume chip is wedged and try to fix it by resetting the chip.
2745 static void i915_hangcheck_elapsed(unsigned long data
)
2747 struct drm_device
*dev
= (struct drm_device
*)data
;
2748 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2749 struct intel_ring_buffer
*ring
;
2751 int busy_count
= 0, rings_hung
= 0;
2752 bool stuck
[I915_NUM_RINGS
] = { 0 };
2757 if (!i915
.enable_hangcheck
)
2760 for_each_ring(ring
, dev_priv
, i
) {
2765 semaphore_clear_deadlocks(dev_priv
);
2767 seqno
= ring
->get_seqno(ring
, false);
2768 acthd
= intel_ring_get_active_head(ring
);
2770 if (ring
->hangcheck
.seqno
== seqno
) {
2771 if (ring_idle(ring
, seqno
)) {
2772 ring
->hangcheck
.action
= HANGCHECK_IDLE
;
2774 if (waitqueue_active(&ring
->irq_queue
)) {
2775 /* Issue a wake-up to catch stuck h/w. */
2776 if (!test_and_set_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
)) {
2777 if (!(dev_priv
->gpu_error
.test_irq_rings
& intel_ring_flag(ring
)))
2778 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2781 DRM_INFO("Fake missed irq on %s\n",
2783 wake_up_all(&ring
->irq_queue
);
2785 /* Safeguard against driver failure */
2786 ring
->hangcheck
.score
+= BUSY
;
2790 /* We always increment the hangcheck score
2791 * if the ring is busy and still processing
2792 * the same request, so that no single request
2793 * can run indefinitely (such as a chain of
2794 * batches). The only time we do not increment
2795 * the hangcheck score on this ring, if this
2796 * ring is in a legitimate wait for another
2797 * ring. In that case the waiting ring is a
2798 * victim and we want to be sure we catch the
2799 * right culprit. Then every time we do kick
2800 * the ring, add a small increment to the
2801 * score so that we can catch a batch that is
2802 * being repeatedly kicked and so responsible
2803 * for stalling the machine.
2805 ring
->hangcheck
.action
= ring_stuck(ring
,
2808 switch (ring
->hangcheck
.action
) {
2809 case HANGCHECK_IDLE
:
2810 case HANGCHECK_WAIT
:
2812 case HANGCHECK_ACTIVE
:
2813 ring
->hangcheck
.score
+= BUSY
;
2815 case HANGCHECK_KICK
:
2816 ring
->hangcheck
.score
+= KICK
;
2818 case HANGCHECK_HUNG
:
2819 ring
->hangcheck
.score
+= HUNG
;
2825 ring
->hangcheck
.action
= HANGCHECK_ACTIVE
;
2827 /* Gradually reduce the count so that we catch DoS
2828 * attempts across multiple batches.
2830 if (ring
->hangcheck
.score
> 0)
2831 ring
->hangcheck
.score
--;
2834 ring
->hangcheck
.seqno
= seqno
;
2835 ring
->hangcheck
.acthd
= acthd
;
2839 for_each_ring(ring
, dev_priv
, i
) {
2840 if (ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
) {
2841 DRM_INFO("%s on %s\n",
2842 stuck
[i
] ? "stuck" : "no progress",
2849 return i915_handle_error(dev
, true, "Ring hung");
2852 /* Reset timer case chip hangs without another request
2854 i915_queue_hangcheck(dev
);
2857 void i915_queue_hangcheck(struct drm_device
*dev
)
2859 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2860 if (!i915
.enable_hangcheck
)
2863 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2864 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2867 static void ibx_irq_reset(struct drm_device
*dev
)
2869 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2871 if (HAS_PCH_NOP(dev
))
2874 GEN5_IRQ_RESET(SDE
);
2876 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
2877 I915_WRITE(SERR_INT
, 0xffffffff);
2881 * SDEIER is also touched by the interrupt handler to work around missed PCH
2882 * interrupts. Hence we can't update it after the interrupt handler is enabled -
2883 * instead we unconditionally enable all PCH interrupt sources here, but then
2884 * only unmask them as needed with SDEIMR.
2886 * This function needs to be called before interrupts are enabled.
2888 static void ibx_irq_pre_postinstall(struct drm_device
*dev
)
2890 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2892 if (HAS_PCH_NOP(dev
))
2895 WARN_ON(I915_READ(SDEIER
) != 0);
2896 I915_WRITE(SDEIER
, 0xffffffff);
2897 POSTING_READ(SDEIER
);
2900 static void gen5_gt_irq_reset(struct drm_device
*dev
)
2902 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2905 if (INTEL_INFO(dev
)->gen
>= 6)
2906 GEN5_IRQ_RESET(GEN6_PM
);
2911 static void ironlake_irq_reset(struct drm_device
*dev
)
2913 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2917 I915_WRITE(GEN7_ERR_INT
, 0xffffffff);
2919 gen5_gt_irq_reset(dev
);
2924 static void ironlake_irq_preinstall(struct drm_device
*dev
)
2926 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2928 I915_WRITE(HWSTAM
, 0xeffe);
2930 ironlake_irq_reset(dev
);
2933 static void valleyview_irq_preinstall(struct drm_device
*dev
)
2935 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2939 I915_WRITE(VLV_IMR
, 0);
2940 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
2941 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
2942 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
2945 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2946 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2948 gen5_gt_irq_reset(dev
);
2950 I915_WRITE(DPINVGTT
, 0xff);
2952 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2953 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2955 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2956 I915_WRITE(VLV_IIR
, 0xffffffff);
2957 I915_WRITE(VLV_IMR
, 0xffffffff);
2958 I915_WRITE(VLV_IER
, 0x0);
2959 POSTING_READ(VLV_IER
);
2962 static void gen8_irq_reset(struct drm_device
*dev
)
2964 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2967 I915_WRITE(GEN8_MASTER_IRQ
, 0);
2968 POSTING_READ(GEN8_MASTER_IRQ
);
2970 GEN8_IRQ_RESET_NDX(GT
, 0);
2971 GEN8_IRQ_RESET_NDX(GT
, 1);
2972 GEN8_IRQ_RESET_NDX(GT
, 2);
2973 GEN8_IRQ_RESET_NDX(GT
, 3);
2976 GEN8_IRQ_RESET_NDX(DE_PIPE
, pipe
);
2978 GEN5_IRQ_RESET(GEN8_DE_PORT_
);
2979 GEN5_IRQ_RESET(GEN8_DE_MISC_
);
2980 GEN5_IRQ_RESET(GEN8_PCU_
);
2985 static void gen8_irq_preinstall(struct drm_device
*dev
)
2987 gen8_irq_reset(dev
);
2990 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
2992 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2993 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2994 struct intel_encoder
*intel_encoder
;
2995 u32 hotplug_irqs
, hotplug
, enabled_irqs
= 0;
2997 if (HAS_PCH_IBX(dev
)) {
2998 hotplug_irqs
= SDE_HOTPLUG_MASK
;
2999 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
3000 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
3001 enabled_irqs
|= hpd_ibx
[intel_encoder
->hpd_pin
];
3003 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
3004 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
3005 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
3006 enabled_irqs
|= hpd_cpt
[intel_encoder
->hpd_pin
];
3009 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
3012 * Enable digital hotplug on the PCH, and configure the DP short pulse
3013 * duration to 2ms (which is the minimum in the Display Port spec)
3015 * This register is the same on all known PCH chips.
3017 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3018 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
3019 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
3020 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
3021 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
3022 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3025 static void ibx_irq_postinstall(struct drm_device
*dev
)
3027 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3030 if (HAS_PCH_NOP(dev
))
3033 if (HAS_PCH_IBX(dev
))
3034 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_POISON
;
3036 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
;
3038 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR
);
3039 I915_WRITE(SDEIMR
, ~mask
);
3042 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
3044 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3045 u32 pm_irqs
, gt_irqs
;
3047 pm_irqs
= gt_irqs
= 0;
3049 dev_priv
->gt_irq_mask
= ~0;
3050 if (HAS_L3_DPF(dev
)) {
3051 /* L3 parity interrupt is always unmasked. */
3052 dev_priv
->gt_irq_mask
= ~GT_PARITY_ERROR(dev
);
3053 gt_irqs
|= GT_PARITY_ERROR(dev
);
3056 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
3058 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
3059 ILK_BSD_USER_INTERRUPT
;
3061 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
3064 GEN5_IRQ_INIT(GT
, dev_priv
->gt_irq_mask
, gt_irqs
);
3066 if (INTEL_INFO(dev
)->gen
>= 6) {
3067 pm_irqs
|= dev_priv
->pm_rps_events
;
3070 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
3072 dev_priv
->pm_irq_mask
= 0xffffffff;
3073 GEN5_IRQ_INIT(GEN6_PM
, dev_priv
->pm_irq_mask
, pm_irqs
);
3077 static int ironlake_irq_postinstall(struct drm_device
*dev
)
3079 unsigned long irqflags
;
3080 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3081 u32 display_mask
, extra_mask
;
3083 if (INTEL_INFO(dev
)->gen
>= 7) {
3084 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
3085 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
3086 DE_PLANEB_FLIP_DONE_IVB
|
3087 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
);
3088 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
3089 DE_PIPEA_VBLANK_IVB
| DE_ERR_INT_IVB
);
3091 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
3092 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
3094 DE_PIPEB_CRC_DONE
| DE_PIPEA_CRC_DONE
|
3096 extra_mask
= DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
|
3097 DE_PIPEB_FIFO_UNDERRUN
| DE_PIPEA_FIFO_UNDERRUN
;
3100 dev_priv
->irq_mask
= ~display_mask
;
3102 ibx_irq_pre_postinstall(dev
);
3104 GEN5_IRQ_INIT(DE
, dev_priv
->irq_mask
, display_mask
| extra_mask
);
3106 gen5_gt_irq_postinstall(dev
);
3108 ibx_irq_postinstall(dev
);
3110 if (IS_IRONLAKE_M(dev
)) {
3111 /* Enable PCU event interrupts
3113 * spinlocking not required here for correctness since interrupt
3114 * setup is guaranteed to run in single-threaded context. But we
3115 * need it to make the assert_spin_locked happy. */
3116 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3117 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
3118 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3124 static void valleyview_display_irqs_install(struct drm_i915_private
*dev_priv
)
3129 pipestat_mask
= PIPESTAT_INT_STATUS_MASK
|
3130 PIPE_FIFO_UNDERRUN_STATUS
;
3132 I915_WRITE(PIPESTAT(PIPE_A
), pipestat_mask
);
3133 I915_WRITE(PIPESTAT(PIPE_B
), pipestat_mask
);
3134 POSTING_READ(PIPESTAT(PIPE_A
));
3136 pipestat_mask
= PLANE_FLIP_DONE_INT_STATUS_VLV
|
3137 PIPE_CRC_DONE_INTERRUPT_STATUS
;
3139 i915_enable_pipestat(dev_priv
, PIPE_A
, pipestat_mask
|
3140 PIPE_GMBUS_INTERRUPT_STATUS
);
3141 i915_enable_pipestat(dev_priv
, PIPE_B
, pipestat_mask
);
3143 iir_mask
= I915_DISPLAY_PORT_INTERRUPT
|
3144 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3145 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
3146 dev_priv
->irq_mask
&= ~iir_mask
;
3148 I915_WRITE(VLV_IIR
, iir_mask
);
3149 I915_WRITE(VLV_IIR
, iir_mask
);
3150 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3151 I915_WRITE(VLV_IER
, ~dev_priv
->irq_mask
);
3152 POSTING_READ(VLV_IER
);
3155 static void valleyview_display_irqs_uninstall(struct drm_i915_private
*dev_priv
)
3160 iir_mask
= I915_DISPLAY_PORT_INTERRUPT
|
3161 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3162 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
3164 dev_priv
->irq_mask
|= iir_mask
;
3165 I915_WRITE(VLV_IER
, ~dev_priv
->irq_mask
);
3166 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3167 I915_WRITE(VLV_IIR
, iir_mask
);
3168 I915_WRITE(VLV_IIR
, iir_mask
);
3169 POSTING_READ(VLV_IIR
);
3171 pipestat_mask
= PLANE_FLIP_DONE_INT_STATUS_VLV
|
3172 PIPE_CRC_DONE_INTERRUPT_STATUS
;
3174 i915_disable_pipestat(dev_priv
, PIPE_A
, pipestat_mask
|
3175 PIPE_GMBUS_INTERRUPT_STATUS
);
3176 i915_disable_pipestat(dev_priv
, PIPE_B
, pipestat_mask
);
3178 pipestat_mask
= PIPESTAT_INT_STATUS_MASK
|
3179 PIPE_FIFO_UNDERRUN_STATUS
;
3180 I915_WRITE(PIPESTAT(PIPE_A
), pipestat_mask
);
3181 I915_WRITE(PIPESTAT(PIPE_B
), pipestat_mask
);
3182 POSTING_READ(PIPESTAT(PIPE_A
));
3185 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
)
3187 assert_spin_locked(&dev_priv
->irq_lock
);
3189 if (dev_priv
->display_irqs_enabled
)
3192 dev_priv
->display_irqs_enabled
= true;
3194 if (dev_priv
->dev
->irq_enabled
)
3195 valleyview_display_irqs_install(dev_priv
);
3198 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
)
3200 assert_spin_locked(&dev_priv
->irq_lock
);
3202 if (!dev_priv
->display_irqs_enabled
)
3205 dev_priv
->display_irqs_enabled
= false;
3207 if (dev_priv
->dev
->irq_enabled
)
3208 valleyview_display_irqs_uninstall(dev_priv
);
3211 static int valleyview_irq_postinstall(struct drm_device
*dev
)
3213 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3214 unsigned long irqflags
;
3216 dev_priv
->irq_mask
= ~0;
3218 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3219 POSTING_READ(PORT_HOTPLUG_EN
);
3221 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3222 I915_WRITE(VLV_IER
, ~dev_priv
->irq_mask
);
3223 I915_WRITE(VLV_IIR
, 0xffffffff);
3224 POSTING_READ(VLV_IER
);
3226 /* Interrupt setup is already guaranteed to be single-threaded, this is
3227 * just to make the assert_spin_locked check happy. */
3228 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3229 if (dev_priv
->display_irqs_enabled
)
3230 valleyview_display_irqs_install(dev_priv
);
3231 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3233 I915_WRITE(VLV_IIR
, 0xffffffff);
3234 I915_WRITE(VLV_IIR
, 0xffffffff);
3236 gen5_gt_irq_postinstall(dev
);
3238 /* ack & enable invalid PTE error interrupts */
3239 #if 0 /* FIXME: add support to irq handler for checking these bits */
3240 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
3241 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
3244 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
3249 static void gen8_gt_irq_postinstall(struct drm_i915_private
*dev_priv
)
3253 /* These are interrupts we'll toggle with the ring mask register */
3254 uint32_t gt_interrupts
[] = {
3255 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3256 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
|
3257 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
,
3258 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3259 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
,
3261 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
3264 for (i
= 0; i
< ARRAY_SIZE(gt_interrupts
); i
++)
3265 GEN8_IRQ_INIT_NDX(GT
, i
, ~gt_interrupts
[i
], gt_interrupts
[i
]);
3268 static void gen8_de_irq_postinstall(struct drm_i915_private
*dev_priv
)
3270 struct drm_device
*dev
= dev_priv
->dev
;
3271 uint32_t de_pipe_masked
= GEN8_PIPE_FLIP_DONE
|
3272 GEN8_PIPE_CDCLK_CRC_DONE
|
3273 GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
3274 uint32_t de_pipe_enables
= de_pipe_masked
| GEN8_PIPE_VBLANK
|
3275 GEN8_PIPE_FIFO_UNDERRUN
;
3277 dev_priv
->de_irq_mask
[PIPE_A
] = ~de_pipe_masked
;
3278 dev_priv
->de_irq_mask
[PIPE_B
] = ~de_pipe_masked
;
3279 dev_priv
->de_irq_mask
[PIPE_C
] = ~de_pipe_masked
;
3282 GEN8_IRQ_INIT_NDX(DE_PIPE
, pipe
, dev_priv
->de_irq_mask
[pipe
],
3285 GEN5_IRQ_INIT(GEN8_DE_PORT_
, ~GEN8_AUX_CHANNEL_A
, GEN8_AUX_CHANNEL_A
);
3288 static int gen8_irq_postinstall(struct drm_device
*dev
)
3290 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3292 ibx_irq_pre_postinstall(dev
);
3294 gen8_gt_irq_postinstall(dev_priv
);
3295 gen8_de_irq_postinstall(dev_priv
);
3297 ibx_irq_postinstall(dev
);
3299 I915_WRITE(GEN8_MASTER_IRQ
, DE_MASTER_IRQ_CONTROL
);
3300 POSTING_READ(GEN8_MASTER_IRQ
);
3305 static void gen8_irq_uninstall(struct drm_device
*dev
)
3307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3312 intel_hpd_irq_uninstall(dev_priv
);
3314 gen8_irq_reset(dev
);
3317 static void valleyview_irq_uninstall(struct drm_device
*dev
)
3319 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3320 unsigned long irqflags
;
3326 intel_hpd_irq_uninstall(dev_priv
);
3329 I915_WRITE(PIPESTAT(pipe
), 0xffff);
3331 I915_WRITE(HWSTAM
, 0xffffffff);
3332 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3333 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3335 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3336 if (dev_priv
->display_irqs_enabled
)
3337 valleyview_display_irqs_uninstall(dev_priv
);
3338 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3340 dev_priv
->irq_mask
= 0;
3342 I915_WRITE(VLV_IIR
, 0xffffffff);
3343 I915_WRITE(VLV_IMR
, 0xffffffff);
3344 I915_WRITE(VLV_IER
, 0x0);
3345 POSTING_READ(VLV_IER
);
3348 static void ironlake_irq_uninstall(struct drm_device
*dev
)
3350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3355 intel_hpd_irq_uninstall(dev_priv
);
3357 I915_WRITE(HWSTAM
, 0xffffffff);
3359 ironlake_irq_reset(dev
);
3362 static void i8xx_irq_preinstall(struct drm_device
* dev
)
3364 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3368 I915_WRITE(PIPESTAT(pipe
), 0);
3369 I915_WRITE16(IMR
, 0xffff);
3370 I915_WRITE16(IER
, 0x0);
3371 POSTING_READ16(IER
);
3374 static int i8xx_irq_postinstall(struct drm_device
*dev
)
3376 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3377 unsigned long irqflags
;
3380 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3382 /* Unmask the interrupts that we always want on. */
3383 dev_priv
->irq_mask
=
3384 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3385 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3386 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3387 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
3388 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
3389 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
3392 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3393 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3394 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
3395 I915_USER_INTERRUPT
);
3396 POSTING_READ16(IER
);
3398 /* Interrupt setup is already guaranteed to be single-threaded, this is
3399 * just to make the assert_spin_locked check happy. */
3400 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3401 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3402 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3403 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3409 * Returns true when a page flip has completed.
3411 static bool i8xx_handle_vblank(struct drm_device
*dev
,
3412 int plane
, int pipe
, u32 iir
)
3414 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3415 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3417 if (!drm_handle_vblank(dev
, pipe
))
3420 if ((iir
& flip_pending
) == 0)
3423 intel_prepare_page_flip(dev
, plane
);
3425 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3426 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3427 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3428 * the flip is completed (no longer pending). Since this doesn't raise
3429 * an interrupt per se, we watch for the change at vblank.
3431 if (I915_READ16(ISR
) & flip_pending
)
3434 intel_finish_page_flip(dev
, pipe
);
3439 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
3441 struct drm_device
*dev
= (struct drm_device
*) arg
;
3442 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3445 unsigned long irqflags
;
3448 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3449 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3451 iir
= I915_READ16(IIR
);
3455 while (iir
& ~flip_mask
) {
3456 /* Can't rely on pipestat interrupt bit in iir as it might
3457 * have been cleared after the pipestat interrupt was received.
3458 * It doesn't set the bit in iir again, but it still produces
3459 * interrupts (for non-MSI).
3461 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3462 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3463 i915_handle_error(dev
, false,
3464 "Command parser error, iir 0x%08x",
3467 for_each_pipe(pipe
) {
3468 int reg
= PIPESTAT(pipe
);
3469 pipe_stats
[pipe
] = I915_READ(reg
);
3472 * Clear the PIPE*STAT regs before the IIR
3474 if (pipe_stats
[pipe
] & 0x8000ffff)
3475 I915_WRITE(reg
, pipe_stats
[pipe
]);
3477 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3479 I915_WRITE16(IIR
, iir
& ~flip_mask
);
3480 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
3482 i915_update_dri1_breadcrumb(dev
);
3484 if (iir
& I915_USER_INTERRUPT
)
3485 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3487 for_each_pipe(pipe
) {
3492 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3493 i8xx_handle_vblank(dev
, plane
, pipe
, iir
))
3494 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
3496 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
3497 i9xx_pipe_crc_irq_handler(dev
, pipe
);
3499 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
&&
3500 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false))
3501 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe
));
3510 static void i8xx_irq_uninstall(struct drm_device
* dev
)
3512 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3515 for_each_pipe(pipe
) {
3516 /* Clear enable bits; then clear status bits */
3517 I915_WRITE(PIPESTAT(pipe
), 0);
3518 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
3520 I915_WRITE16(IMR
, 0xffff);
3521 I915_WRITE16(IER
, 0x0);
3522 I915_WRITE16(IIR
, I915_READ16(IIR
));
3525 static void i915_irq_preinstall(struct drm_device
* dev
)
3527 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3530 if (I915_HAS_HOTPLUG(dev
)) {
3531 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3532 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3535 I915_WRITE16(HWSTAM
, 0xeffe);
3537 I915_WRITE(PIPESTAT(pipe
), 0);
3538 I915_WRITE(IMR
, 0xffffffff);
3539 I915_WRITE(IER
, 0x0);
3543 static int i915_irq_postinstall(struct drm_device
*dev
)
3545 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3547 unsigned long irqflags
;
3549 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3551 /* Unmask the interrupts that we always want on. */
3552 dev_priv
->irq_mask
=
3553 ~(I915_ASLE_INTERRUPT
|
3554 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3555 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3556 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3557 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
3558 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
3561 I915_ASLE_INTERRUPT
|
3562 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3563 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3564 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
3565 I915_USER_INTERRUPT
;
3567 if (I915_HAS_HOTPLUG(dev
)) {
3568 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3569 POSTING_READ(PORT_HOTPLUG_EN
);
3571 /* Enable in IER... */
3572 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
3573 /* and unmask in IMR */
3574 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
3577 I915_WRITE(IMR
, dev_priv
->irq_mask
);
3578 I915_WRITE(IER
, enable_mask
);
3581 i915_enable_asle_pipestat(dev
);
3583 /* Interrupt setup is already guaranteed to be single-threaded, this is
3584 * just to make the assert_spin_locked check happy. */
3585 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3586 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3587 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3588 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3594 * Returns true when a page flip has completed.
3596 static bool i915_handle_vblank(struct drm_device
*dev
,
3597 int plane
, int pipe
, u32 iir
)
3599 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3600 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3602 if (!drm_handle_vblank(dev
, pipe
))
3605 if ((iir
& flip_pending
) == 0)
3608 intel_prepare_page_flip(dev
, plane
);
3610 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3611 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3612 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3613 * the flip is completed (no longer pending). Since this doesn't raise
3614 * an interrupt per se, we watch for the change at vblank.
3616 if (I915_READ(ISR
) & flip_pending
)
3619 intel_finish_page_flip(dev
, pipe
);
3624 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
3626 struct drm_device
*dev
= (struct drm_device
*) arg
;
3627 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3628 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
3629 unsigned long irqflags
;
3631 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3632 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3633 int pipe
, ret
= IRQ_NONE
;
3635 iir
= I915_READ(IIR
);
3637 bool irq_received
= (iir
& ~flip_mask
) != 0;
3638 bool blc_event
= false;
3640 /* Can't rely on pipestat interrupt bit in iir as it might
3641 * have been cleared after the pipestat interrupt was received.
3642 * It doesn't set the bit in iir again, but it still produces
3643 * interrupts (for non-MSI).
3645 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3646 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3647 i915_handle_error(dev
, false,
3648 "Command parser error, iir 0x%08x",
3651 for_each_pipe(pipe
) {
3652 int reg
= PIPESTAT(pipe
);
3653 pipe_stats
[pipe
] = I915_READ(reg
);
3655 /* Clear the PIPE*STAT regs before the IIR */
3656 if (pipe_stats
[pipe
] & 0x8000ffff) {
3657 I915_WRITE(reg
, pipe_stats
[pipe
]);
3658 irq_received
= true;
3661 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3666 /* Consume port. Then clear IIR or we'll miss events */
3667 if (I915_HAS_HOTPLUG(dev
) &&
3668 iir
& I915_DISPLAY_PORT_INTERRUPT
)
3669 i9xx_hpd_irq_handler(dev
);
3671 I915_WRITE(IIR
, iir
& ~flip_mask
);
3672 new_iir
= I915_READ(IIR
); /* Flush posted writes */
3674 if (iir
& I915_USER_INTERRUPT
)
3675 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3677 for_each_pipe(pipe
) {
3682 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3683 i915_handle_vblank(dev
, plane
, pipe
, iir
))
3684 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
3686 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
3689 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
3690 i9xx_pipe_crc_irq_handler(dev
, pipe
);
3692 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
&&
3693 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false))
3694 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe
));
3697 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
3698 intel_opregion_asle_intr(dev
);
3700 /* With MSI, interrupts are only generated when iir
3701 * transitions from zero to nonzero. If another bit got
3702 * set while we were handling the existing iir bits, then
3703 * we would never get another interrupt.
3705 * This is fine on non-MSI as well, as if we hit this path
3706 * we avoid exiting the interrupt handler only to generate
3709 * Note that for MSI this could cause a stray interrupt report
3710 * if an interrupt landed in the time between writing IIR and
3711 * the posting read. This should be rare enough to never
3712 * trigger the 99% of 100,000 interrupts test for disabling
3717 } while (iir
& ~flip_mask
);
3719 i915_update_dri1_breadcrumb(dev
);
3724 static void i915_irq_uninstall(struct drm_device
* dev
)
3726 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3729 intel_hpd_irq_uninstall(dev_priv
);
3731 if (I915_HAS_HOTPLUG(dev
)) {
3732 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3733 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3736 I915_WRITE16(HWSTAM
, 0xffff);
3737 for_each_pipe(pipe
) {
3738 /* Clear enable bits; then clear status bits */
3739 I915_WRITE(PIPESTAT(pipe
), 0);
3740 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
3742 I915_WRITE(IMR
, 0xffffffff);
3743 I915_WRITE(IER
, 0x0);
3745 I915_WRITE(IIR
, I915_READ(IIR
));
3748 static void i965_irq_preinstall(struct drm_device
* dev
)
3750 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3753 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3754 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3756 I915_WRITE(HWSTAM
, 0xeffe);
3758 I915_WRITE(PIPESTAT(pipe
), 0);
3759 I915_WRITE(IMR
, 0xffffffff);
3760 I915_WRITE(IER
, 0x0);
3764 static int i965_irq_postinstall(struct drm_device
*dev
)
3766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3769 unsigned long irqflags
;
3771 /* Unmask the interrupts that we always want on. */
3772 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
3773 I915_DISPLAY_PORT_INTERRUPT
|
3774 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3775 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3776 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3777 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
3778 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
3780 enable_mask
= ~dev_priv
->irq_mask
;
3781 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3782 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
3783 enable_mask
|= I915_USER_INTERRUPT
;
3786 enable_mask
|= I915_BSD_USER_INTERRUPT
;
3788 /* Interrupt setup is already guaranteed to be single-threaded, this is
3789 * just to make the assert_spin_locked check happy. */
3790 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3791 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
3792 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3793 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3794 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3797 * Enable some error detection, note the instruction error mask
3798 * bit is reserved, so we leave it masked.
3801 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
3802 GM45_ERROR_MEM_PRIV
|
3803 GM45_ERROR_CP_PRIV
|
3804 I915_ERROR_MEMORY_REFRESH
);
3806 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
3807 I915_ERROR_MEMORY_REFRESH
);
3809 I915_WRITE(EMR
, error_mask
);
3811 I915_WRITE(IMR
, dev_priv
->irq_mask
);
3812 I915_WRITE(IER
, enable_mask
);
3815 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3816 POSTING_READ(PORT_HOTPLUG_EN
);
3818 i915_enable_asle_pipestat(dev
);
3823 static void i915_hpd_irq_setup(struct drm_device
*dev
)
3825 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3826 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3827 struct intel_encoder
*intel_encoder
;
3830 assert_spin_locked(&dev_priv
->irq_lock
);
3832 if (I915_HAS_HOTPLUG(dev
)) {
3833 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
3834 hotplug_en
&= ~HOTPLUG_INT_EN_MASK
;
3835 /* Note HDMI and DP share hotplug bits */
3836 /* enable bits are the same for all generations */
3837 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
3838 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
3839 hotplug_en
|= hpd_mask_i915
[intel_encoder
->hpd_pin
];
3840 /* Programming the CRT detection parameters tends
3841 to generate a spurious hotplug event about three
3842 seconds later. So just do it once.
3845 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
3846 hotplug_en
&= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
;
3847 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
3849 /* Ignore TV since it's buggy */
3850 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
3854 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
3856 struct drm_device
*dev
= (struct drm_device
*) arg
;
3857 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3859 u32 pipe_stats
[I915_MAX_PIPES
];
3860 unsigned long irqflags
;
3861 int ret
= IRQ_NONE
, pipe
;
3863 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3864 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3866 iir
= I915_READ(IIR
);
3869 bool irq_received
= (iir
& ~flip_mask
) != 0;
3870 bool blc_event
= false;
3872 /* Can't rely on pipestat interrupt bit in iir as it might
3873 * have been cleared after the pipestat interrupt was received.
3874 * It doesn't set the bit in iir again, but it still produces
3875 * interrupts (for non-MSI).
3877 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3878 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3879 i915_handle_error(dev
, false,
3880 "Command parser error, iir 0x%08x",
3883 for_each_pipe(pipe
) {
3884 int reg
= PIPESTAT(pipe
);
3885 pipe_stats
[pipe
] = I915_READ(reg
);
3888 * Clear the PIPE*STAT regs before the IIR
3890 if (pipe_stats
[pipe
] & 0x8000ffff) {
3891 I915_WRITE(reg
, pipe_stats
[pipe
]);
3892 irq_received
= true;
3895 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3902 /* Consume port. Then clear IIR or we'll miss events */
3903 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
3904 i9xx_hpd_irq_handler(dev
);
3906 I915_WRITE(IIR
, iir
& ~flip_mask
);
3907 new_iir
= I915_READ(IIR
); /* Flush posted writes */
3909 if (iir
& I915_USER_INTERRUPT
)
3910 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3911 if (iir
& I915_BSD_USER_INTERRUPT
)
3912 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
3914 for_each_pipe(pipe
) {
3915 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
3916 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
3917 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
3919 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
3922 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
3923 i9xx_pipe_crc_irq_handler(dev
, pipe
);
3925 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
&&
3926 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false))
3927 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe
));
3930 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
3931 intel_opregion_asle_intr(dev
);
3933 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
3934 gmbus_irq_handler(dev
);
3936 /* With MSI, interrupts are only generated when iir
3937 * transitions from zero to nonzero. If another bit got
3938 * set while we were handling the existing iir bits, then
3939 * we would never get another interrupt.
3941 * This is fine on non-MSI as well, as if we hit this path
3942 * we avoid exiting the interrupt handler only to generate
3945 * Note that for MSI this could cause a stray interrupt report
3946 * if an interrupt landed in the time between writing IIR and
3947 * the posting read. This should be rare enough to never
3948 * trigger the 99% of 100,000 interrupts test for disabling
3954 i915_update_dri1_breadcrumb(dev
);
3959 static void i965_irq_uninstall(struct drm_device
* dev
)
3961 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3967 intel_hpd_irq_uninstall(dev_priv
);
3969 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3970 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3972 I915_WRITE(HWSTAM
, 0xffffffff);
3974 I915_WRITE(PIPESTAT(pipe
), 0);
3975 I915_WRITE(IMR
, 0xffffffff);
3976 I915_WRITE(IER
, 0x0);
3979 I915_WRITE(PIPESTAT(pipe
),
3980 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
3981 I915_WRITE(IIR
, I915_READ(IIR
));
3984 static void intel_hpd_irq_reenable(unsigned long data
)
3986 struct drm_i915_private
*dev_priv
= (struct drm_i915_private
*)data
;
3987 struct drm_device
*dev
= dev_priv
->dev
;
3988 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3989 unsigned long irqflags
;
3992 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3993 for (i
= (HPD_NONE
+ 1); i
< HPD_NUM_PINS
; i
++) {
3994 struct drm_connector
*connector
;
3996 if (dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_DISABLED
)
3999 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
4001 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
4002 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4004 if (intel_connector
->encoder
->hpd_pin
== i
) {
4005 if (connector
->polled
!= intel_connector
->polled
)
4006 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4007 drm_get_connector_name(connector
));
4008 connector
->polled
= intel_connector
->polled
;
4009 if (!connector
->polled
)
4010 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
4014 if (dev_priv
->display
.hpd_irq_setup
)
4015 dev_priv
->display
.hpd_irq_setup(dev
);
4016 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
4019 void intel_irq_init(struct drm_device
*dev
)
4021 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4023 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
4024 INIT_WORK(&dev_priv
->gpu_error
.work
, i915_error_work_func
);
4025 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
4026 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
4028 /* Let's track the enabled rps events */
4029 dev_priv
->pm_rps_events
= GEN6_PM_RPS_EVENTS
;
4031 setup_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
4032 i915_hangcheck_elapsed
,
4033 (unsigned long) dev
);
4034 setup_timer(&dev_priv
->hotplug_reenable_timer
, intel_hpd_irq_reenable
,
4035 (unsigned long) dev_priv
);
4037 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
4040 dev
->max_vblank_count
= 0;
4041 dev
->driver
->get_vblank_counter
= i8xx_get_vblank_counter
;
4042 } else if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
4043 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
4044 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
4046 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
4047 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
4050 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4051 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
4052 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
4055 if (IS_VALLEYVIEW(dev
)) {
4056 dev
->driver
->irq_handler
= valleyview_irq_handler
;
4057 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
4058 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
4059 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
4060 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
4061 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
4062 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4063 } else if (IS_GEN8(dev
)) {
4064 dev
->driver
->irq_handler
= gen8_irq_handler
;
4065 dev
->driver
->irq_preinstall
= gen8_irq_preinstall
;
4066 dev
->driver
->irq_postinstall
= gen8_irq_postinstall
;
4067 dev
->driver
->irq_uninstall
= gen8_irq_uninstall
;
4068 dev
->driver
->enable_vblank
= gen8_enable_vblank
;
4069 dev
->driver
->disable_vblank
= gen8_disable_vblank
;
4070 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
4071 } else if (HAS_PCH_SPLIT(dev
)) {
4072 dev
->driver
->irq_handler
= ironlake_irq_handler
;
4073 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
4074 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
4075 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
4076 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
4077 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
4078 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
4080 if (INTEL_INFO(dev
)->gen
== 2) {
4081 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
4082 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
4083 dev
->driver
->irq_handler
= i8xx_irq_handler
;
4084 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
4085 } else if (INTEL_INFO(dev
)->gen
== 3) {
4086 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
4087 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
4088 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
4089 dev
->driver
->irq_handler
= i915_irq_handler
;
4090 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4092 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
4093 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
4094 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
4095 dev
->driver
->irq_handler
= i965_irq_handler
;
4096 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4098 dev
->driver
->enable_vblank
= i915_enable_vblank
;
4099 dev
->driver
->disable_vblank
= i915_disable_vblank
;
4103 void intel_hpd_init(struct drm_device
*dev
)
4105 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4106 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4107 struct drm_connector
*connector
;
4108 unsigned long irqflags
;
4111 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
4112 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
4113 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
4115 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
4116 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4117 connector
->polled
= intel_connector
->polled
;
4118 if (!connector
->polled
&& I915_HAS_HOTPLUG(dev
) && intel_connector
->encoder
->hpd_pin
> HPD_NONE
)
4119 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
4122 /* Interrupt setup is already guaranteed to be single-threaded, this is
4123 * just to make the assert_spin_locked checks happy. */
4124 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
4125 if (dev_priv
->display
.hpd_irq_setup
)
4126 dev_priv
->display
.hpd_irq_setup(dev
);
4127 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
4130 /* Disable interrupts so we can allow runtime PM. */
4131 void hsw_runtime_pm_disable_interrupts(struct drm_device
*dev
)
4133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4134 unsigned long irqflags
;
4136 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
4138 dev_priv
->pm
.regsave
.deimr
= I915_READ(DEIMR
);
4139 dev_priv
->pm
.regsave
.sdeimr
= I915_READ(SDEIMR
);
4140 dev_priv
->pm
.regsave
.gtimr
= I915_READ(GTIMR
);
4141 dev_priv
->pm
.regsave
.gtier
= I915_READ(GTIER
);
4142 dev_priv
->pm
.regsave
.gen6_pmimr
= I915_READ(GEN6_PMIMR
);
4144 ironlake_disable_display_irq(dev_priv
, 0xffffffff);
4145 ibx_disable_display_interrupt(dev_priv
, 0xffffffff);
4146 ilk_disable_gt_irq(dev_priv
, 0xffffffff);
4147 snb_disable_pm_irq(dev_priv
, 0xffffffff);
4149 dev_priv
->pm
.irqs_disabled
= true;
4151 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
4154 /* Restore interrupts so we can recover from runtime PM. */
4155 void hsw_runtime_pm_restore_interrupts(struct drm_device
*dev
)
4157 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4158 unsigned long irqflags
;
4161 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
4163 val
= I915_READ(DEIMR
);
4164 WARN(val
!= 0xffffffff, "DEIMR is 0x%08x\n", val
);
4166 val
= I915_READ(SDEIMR
);
4167 WARN(val
!= 0xffffffff, "SDEIMR is 0x%08x\n", val
);
4169 val
= I915_READ(GTIMR
);
4170 WARN(val
!= 0xffffffff, "GTIMR is 0x%08x\n", val
);
4172 val
= I915_READ(GEN6_PMIMR
);
4173 WARN(val
!= 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val
);
4175 dev_priv
->pm
.irqs_disabled
= false;
4177 ironlake_enable_display_irq(dev_priv
, ~dev_priv
->pm
.regsave
.deimr
);
4178 ibx_enable_display_interrupt(dev_priv
, ~dev_priv
->pm
.regsave
.sdeimr
);
4179 ilk_enable_gt_irq(dev_priv
, ~dev_priv
->pm
.regsave
.gtimr
);
4180 snb_enable_pm_irq(dev_priv
, ~dev_priv
->pm
.regsave
.gen6_pmimr
);
4181 I915_WRITE(GTIER
, dev_priv
->pm
.regsave
.gtier
);
4183 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);