projects / deliverable / linux.git / blob
? search:


44209442ff1a96440afe73c632f86eb5edc1d902
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
34 #include <drm/drmP.h>
35 #include <drm/i915_drm.h>
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "intel_drv.h"
39
40 static const u32 hpd_ibx[] = {
41 [HPD_CRT] = SDE_CRT_HOTPLUG,
42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
46 };
47
48 static const u32 hpd_cpt[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
54 };
55
56 static const u32 hpd_mask_i915[] = {
57 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
63 };
64
65 static const u32 hpd_status_gen4[] = {
66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
72 };
73
74 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
81 };
82
83 /* For display hotplug interrupt */
84 static void
85 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
86 {
87 assert_spin_locked(&dev_priv->irq_lock);
88
89 if (dev_priv->pc8.irqs_disabled) {
90 WARN(1, "IRQs disabled\n");
91 dev_priv->pc8.regsave.deimr &= ~mask;
92 return;
93 }
94
95 if ((dev_priv->irq_mask & mask) != 0) {
96 dev_priv->irq_mask &= ~mask;
97 I915_WRITE(DEIMR, dev_priv->irq_mask);
98 POSTING_READ(DEIMR);
99 }
100 }
101
102 static void
103 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
104 {
105 assert_spin_locked(&dev_priv->irq_lock);
106
107 if (dev_priv->pc8.irqs_disabled) {
108 WARN(1, "IRQs disabled\n");
109 dev_priv->pc8.regsave.deimr |= mask;
110 return;
111 }
112
113 if ((dev_priv->irq_mask & mask) != mask) {
114 dev_priv->irq_mask |= mask;
115 I915_WRITE(DEIMR, dev_priv->irq_mask);
116 POSTING_READ(DEIMR);
117 }
118 }
119
120 /**
121 * ilk_update_gt_irq - update GTIMR
122 * @dev_priv: driver private
123 * @interrupt_mask: mask of interrupt bits to update
124 * @enabled_irq_mask: mask of interrupt bits to enable
125 */
126 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
127 uint32_t interrupt_mask,
128 uint32_t enabled_irq_mask)
129 {
130 assert_spin_locked(&dev_priv->irq_lock);
131
132 if (dev_priv->pc8.irqs_disabled) {
133 WARN(1, "IRQs disabled\n");
134 dev_priv->pc8.regsave.gtimr &= ~interrupt_mask;
135 dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask &
136 interrupt_mask);
137 return;
138 }
139
140 dev_priv->gt_irq_mask &= ~interrupt_mask;
141 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
142 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
143 POSTING_READ(GTIMR);
144 }
145
146 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
147 {
148 ilk_update_gt_irq(dev_priv, mask, mask);
149 }
150
151 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
152 {
153 ilk_update_gt_irq(dev_priv, mask, 0);
154 }
155
156 /**
157 * snb_update_pm_irq - update GEN6_PMIMR
158 * @dev_priv: driver private
159 * @interrupt_mask: mask of interrupt bits to update
160 * @enabled_irq_mask: mask of interrupt bits to enable
161 */
162 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
163 uint32_t interrupt_mask,
164 uint32_t enabled_irq_mask)
165 {
166 uint32_t new_val;
167
168 assert_spin_locked(&dev_priv->irq_lock);
169
170 if (dev_priv->pc8.irqs_disabled) {
171 WARN(1, "IRQs disabled\n");
172 dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask;
173 dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask &
174 interrupt_mask);
175 return;
176 }
177
178 new_val = dev_priv->pm_irq_mask;
179 new_val &= ~interrupt_mask;
180 new_val |= (~enabled_irq_mask & interrupt_mask);
181
182 if (new_val != dev_priv->pm_irq_mask) {
183 dev_priv->pm_irq_mask = new_val;
184 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
185 POSTING_READ(GEN6_PMIMR);
186 }
187 }
188
189 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
190 {
191 snb_update_pm_irq(dev_priv, mask, mask);
192 }
193
194 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
195 {
196 snb_update_pm_irq(dev_priv, mask, 0);
197 }
198
199 static bool ivb_can_enable_err_int(struct drm_device *dev)
200 {
201 struct drm_i915_private *dev_priv = dev->dev_private;
202 struct intel_crtc *crtc;
203 enum pipe pipe;
204
205 assert_spin_locked(&dev_priv->irq_lock);
206
207 for_each_pipe(pipe) {
208 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
209
210 if (crtc->cpu_fifo_underrun_disabled)
211 return false;
212 }
213
214 return true;
215 }
216
217 static bool cpt_can_enable_serr_int(struct drm_device *dev)
218 {
219 struct drm_i915_private *dev_priv = dev->dev_private;
220 enum pipe pipe;
221 struct intel_crtc *crtc;
222
223 assert_spin_locked(&dev_priv->irq_lock);
224
225 for_each_pipe(pipe) {
226 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
227
228 if (crtc->pch_fifo_underrun_disabled)
229 return false;
230 }
231
232 return true;
233 }
234
235 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
236 enum pipe pipe, bool enable)
237 {
238 struct drm_i915_private *dev_priv = dev->dev_private;
239 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
240 DE_PIPEB_FIFO_UNDERRUN;
241
242 if (enable)
243 ironlake_enable_display_irq(dev_priv, bit);
244 else
245 ironlake_disable_display_irq(dev_priv, bit);
246 }
247
248 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
249 enum pipe pipe, bool enable)
250 {
251 struct drm_i915_private *dev_priv = dev->dev_private;
252 if (enable) {
253 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
254
255 if (!ivb_can_enable_err_int(dev))
256 return;
257
258 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
259 } else {
260 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
261
262 /* Change the state _after_ we've read out the current one. */
263 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
264
265 if (!was_enabled &&
266 (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
267 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
268 pipe_name(pipe));
269 }
270 }
271 }
272
273 /**
274 * ibx_display_interrupt_update - update SDEIMR
275 * @dev_priv: driver private
276 * @interrupt_mask: mask of interrupt bits to update
277 * @enabled_irq_mask: mask of interrupt bits to enable
278 */
279 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
280 uint32_t interrupt_mask,
281 uint32_t enabled_irq_mask)
282 {
283 uint32_t sdeimr = I915_READ(SDEIMR);
284 sdeimr &= ~interrupt_mask;
285 sdeimr |= (~enabled_irq_mask & interrupt_mask);
286
287 assert_spin_locked(&dev_priv->irq_lock);
288
289 if (dev_priv->pc8.irqs_disabled &&
290 (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
291 WARN(1, "IRQs disabled\n");
292 dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask;
293 dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask &
294 interrupt_mask);
295 return;
296 }
297
298 I915_WRITE(SDEIMR, sdeimr);
299 POSTING_READ(SDEIMR);
300 }
301 #define ibx_enable_display_interrupt(dev_priv, bits) \
302 ibx_display_interrupt_update((dev_priv), (bits), (bits))
303 #define ibx_disable_display_interrupt(dev_priv, bits) \
304 ibx_display_interrupt_update((dev_priv), (bits), 0)
305
306 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
307 enum transcoder pch_transcoder,
308 bool enable)
309 {
310 struct drm_i915_private *dev_priv = dev->dev_private;
311 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
312 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
313
314 if (enable)
315 ibx_enable_display_interrupt(dev_priv, bit);
316 else
317 ibx_disable_display_interrupt(dev_priv, bit);
318 }
319
320 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
321 enum transcoder pch_transcoder,
322 bool enable)
323 {
324 struct drm_i915_private *dev_priv = dev->dev_private;
325
326 if (enable) {
327 I915_WRITE(SERR_INT,
328 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
329
330 if (!cpt_can_enable_serr_int(dev))
331 return;
332
333 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
334 } else {
335 uint32_t tmp = I915_READ(SERR_INT);
336 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
337
338 /* Change the state _after_ we've read out the current one. */
339 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
340
341 if (!was_enabled &&
342 (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
343 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
344 transcoder_name(pch_transcoder));
345 }
346 }
347 }
348
349 /**
350 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
351 * @dev: drm device
352 * @pipe: pipe
353 * @enable: true if we want to report FIFO underrun errors, false otherwise
354 *
355 * This function makes us disable or enable CPU fifo underruns for a specific
356 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
357 * reporting for one pipe may also disable all the other CPU error interruts for
358 * the other pipes, due to the fact that there's just one interrupt mask/enable
359 * bit for all the pipes.
360 *
361 * Returns the previous state of underrun reporting.
362 */
363 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
364 enum pipe pipe, bool enable)
365 {
366 struct drm_i915_private *dev_priv = dev->dev_private;
367 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
369 unsigned long flags;
370 bool ret;
371
372 spin_lock_irqsave(&dev_priv->irq_lock, flags);
373
374 ret = !intel_crtc->cpu_fifo_underrun_disabled;
375
376 if (enable == ret)
377 goto done;
378
379 intel_crtc->cpu_fifo_underrun_disabled = !enable;
380
381 if (IS_GEN5(dev) || IS_GEN6(dev))
382 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
383 else if (IS_GEN7(dev))
384 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
385
386 done:
387 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
388 return ret;
389 }
390
391 /**
392 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
393 * @dev: drm device
394 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
395 * @enable: true if we want to report FIFO underrun errors, false otherwise
396 *
397 * This function makes us disable or enable PCH fifo underruns for a specific
398 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
399 * underrun reporting for one transcoder may also disable all the other PCH
400 * error interruts for the other transcoders, due to the fact that there's just
401 * one interrupt mask/enable bit for all the transcoders.
402 *
403 * Returns the previous state of underrun reporting.
404 */
405 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
406 enum transcoder pch_transcoder,
407 bool enable)
408 {
409 struct drm_i915_private *dev_priv = dev->dev_private;
410 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
412 unsigned long flags;
413 bool ret;
414
415 /*
416 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
417 * has only one pch transcoder A that all pipes can use. To avoid racy
418 * pch transcoder -> pipe lookups from interrupt code simply store the
419 * underrun statistics in crtc A. Since we never expose this anywhere
420 * nor use it outside of the fifo underrun code here using the "wrong"
421 * crtc on LPT won't cause issues.
422 */
423
424 spin_lock_irqsave(&dev_priv->irq_lock, flags);
425
426 ret = !intel_crtc->pch_fifo_underrun_disabled;
427
428 if (enable == ret)
429 goto done;
430
431 intel_crtc->pch_fifo_underrun_disabled = !enable;
432
433 if (HAS_PCH_IBX(dev))
434 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
435 else
436 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
437
438 done:
439 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
440 return ret;
441 }
442
443
444 void
445 i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
446 {
447 u32 reg = PIPESTAT(pipe);
448 u32 pipestat = I915_READ(reg) & 0x7fff0000;
449
450 assert_spin_locked(&dev_priv->irq_lock);
451
452 if ((pipestat & mask) == mask)
453 return;
454
455 /* Enable the interrupt, clear any pending status */
456 pipestat |= mask | (mask >> 16);
457 I915_WRITE(reg, pipestat);
458 POSTING_READ(reg);
459 }
460
461 void
462 i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
463 {
464 u32 reg = PIPESTAT(pipe);
465 u32 pipestat = I915_READ(reg) & 0x7fff0000;
466
467 assert_spin_locked(&dev_priv->irq_lock);
468
469 if ((pipestat & mask) == 0)
470 return;
471
472 pipestat &= ~mask;
473 I915_WRITE(reg, pipestat);
474 POSTING_READ(reg);
475 }
476
477 /**
478 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
479 */
480 static void i915_enable_asle_pipestat(struct drm_device *dev)
481 {
482 drm_i915_private_t *dev_priv = dev->dev_private;
483 unsigned long irqflags;
484
485 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
486 return;
487
488 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
489
490 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_ENABLE);
491 if (INTEL_INFO(dev)->gen >= 4)
492 i915_enable_pipestat(dev_priv, PIPE_A,
493 PIPE_LEGACY_BLC_EVENT_ENABLE);
494
495 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
496 }
497
498 /**
499 * i915_pipe_enabled - check if a pipe is enabled
500 * @dev: DRM device
501 * @pipe: pipe to check
502 *
503 * Reading certain registers when the pipe is disabled can hang the chip.
504 * Use this routine to make sure the PLL is running and the pipe is active
505 * before reading such registers if unsure.
506 */
507 static int
508 i915_pipe_enabled(struct drm_device *dev, int pipe)
509 {
510 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
511
512 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
513 /* Locking is horribly broken here, but whatever. */
514 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
516
517 return intel_crtc->active;
518 } else {
519 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
520 }
521 }
522
523 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
524 {
525 /* Gen2 doesn't have a hardware frame counter */
526 return 0;
527 }
528
529 /* Called from drm generic code, passed a 'crtc', which
530 * we use as a pipe index
531 */
532 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
533 {
534 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
535 unsigned long high_frame;
536 unsigned long low_frame;
537 u32 high1, high2, low, pixel, vbl_start;
538
539 if (!i915_pipe_enabled(dev, pipe)) {
540 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
541 "pipe %c\n", pipe_name(pipe));
542 return 0;
543 }
544
545 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
546 struct intel_crtc *intel_crtc =
547 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
548 const struct drm_display_mode *mode =
549 &intel_crtc->config.adjusted_mode;
550
551 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
552 } else {
553 enum transcoder cpu_transcoder =
554 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
555 u32 htotal;
556
557 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
558 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
559
560 vbl_start *= htotal;
561 }
562
563 high_frame = PIPEFRAME(pipe);
564 low_frame = PIPEFRAMEPIXEL(pipe);
565
566 /*
567 * High & low register fields aren't synchronized, so make sure
568 * we get a low value that's stable across two reads of the high
569 * register.
570 */
571 do {
572 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
573 low = I915_READ(low_frame);
574 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
575 } while (high1 != high2);
576
577 high1 >>= PIPE_FRAME_HIGH_SHIFT;
578 pixel = low & PIPE_PIXEL_MASK;
579 low >>= PIPE_FRAME_LOW_SHIFT;
580
581 /*
582 * The frame counter increments at beginning of active.
583 * Cook up a vblank counter by also checking the pixel
584 * counter against vblank start.
585 */
586 return ((high1 << 8) | low) + (pixel >= vbl_start);
587 }
588
589 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
590 {
591 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
592 int reg = PIPE_FRMCOUNT_GM45(pipe);
593
594 if (!i915_pipe_enabled(dev, pipe)) {
595 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
596 "pipe %c\n", pipe_name(pipe));
597 return 0;
598 }
599
600 return I915_READ(reg);
601 }
602
603 static bool intel_pipe_in_vblank(struct drm_device *dev, enum pipe pipe)
604 {
605 struct drm_i915_private *dev_priv = dev->dev_private;
606 uint32_t status;
607
608 if (IS_VALLEYVIEW(dev)) {
609 status = pipe == PIPE_A ?
610 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
611 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
612
613 return I915_READ(VLV_ISR) & status;
614 } else if (IS_GEN2(dev)) {
615 status = pipe == PIPE_A ?
616 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
617 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
618
619 return I915_READ16(ISR) & status;
620 } else if (INTEL_INFO(dev)->gen < 5) {
621 status = pipe == PIPE_A ?
622 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
623 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
624
625 return I915_READ(ISR) & status;
626 } else if (INTEL_INFO(dev)->gen < 7) {
627 status = pipe == PIPE_A ?
628 DE_PIPEA_VBLANK :
629 DE_PIPEB_VBLANK;
630
631 return I915_READ(DEISR) & status;
632 } else {
633 switch (pipe) {
634 default:
635 case PIPE_A:
636 status = DE_PIPEA_VBLANK_IVB;
637 break;
638 case PIPE_B:
639 status = DE_PIPEB_VBLANK_IVB;
640 break;
641 case PIPE_C:
642 status = DE_PIPEC_VBLANK_IVB;
643 break;
644 }
645
646 return I915_READ(DEISR) & status;
647 }
648 }
649
650 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
651 int *vpos, int *hpos)
652 {
653 struct drm_i915_private *dev_priv = dev->dev_private;
654 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
656 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
657 int position;
658 int vbl_start, vbl_end, htotal, vtotal;
659 bool in_vbl = true;
660 int ret = 0;
661
662 if (!intel_crtc->active) {
663 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
664 "pipe %c\n", pipe_name(pipe));
665 return 0;
666 }
667
668 htotal = mode->crtc_htotal;
669 vtotal = mode->crtc_vtotal;
670 vbl_start = mode->crtc_vblank_start;
671 vbl_end = mode->crtc_vblank_end;
672
673 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
674
675 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
676 /* No obvious pixelcount register. Only query vertical
677 * scanout position from Display scan line register.
678 */
679 if (IS_GEN2(dev))
680 position = I915_READ(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
681 else
682 position = I915_READ(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
683
684 /*
685 * The scanline counter increments at the leading edge
686 * of hsync, ie. it completely misses the active portion
687 * of the line. Fix up the counter at both edges of vblank
688 * to get a more accurate picture whether we're in vblank
689 * or not.
690 */
691 in_vbl = intel_pipe_in_vblank(dev, pipe);
692 if ((in_vbl && position == vbl_start - 1) ||
693 (!in_vbl && position == vbl_end - 1))
694 position = (position + 1) % vtotal;
695 } else {
696 /* Have access to pixelcount since start of frame.
697 * We can split this into vertical and horizontal
698 * scanout position.
699 */
700 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
701
702 /* convert to pixel counts */
703 vbl_start *= htotal;
704 vbl_end *= htotal;
705 vtotal *= htotal;
706 }
707
708 in_vbl = position >= vbl_start && position < vbl_end;
709
710 /*
711 * While in vblank, position will be negative
712 * counting up towards 0 at vbl_end. And outside
713 * vblank, position will be positive counting
714 * up since vbl_end.
715 */
716 if (position >= vbl_start)
717 position -= vbl_end;
718 else
719 position += vtotal - vbl_end;
720
721 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
722 *vpos = position;
723 *hpos = 0;
724 } else {
725 *vpos = position / htotal;
726 *hpos = position - (*vpos * htotal);
727 }
728
729 /* In vblank? */
730 if (in_vbl)
731 ret |= DRM_SCANOUTPOS_INVBL;
732
733 return ret;
734 }
735
736 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
737 int *max_error,
738 struct timeval *vblank_time,
739 unsigned flags)
740 {
741 struct drm_crtc *crtc;
742
743 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
744 DRM_ERROR("Invalid crtc %d\n", pipe);
745 return -EINVAL;
746 }
747
748 /* Get drm_crtc to timestamp: */
749 crtc = intel_get_crtc_for_pipe(dev, pipe);
750 if (crtc == NULL) {
751 DRM_ERROR("Invalid crtc %d\n", pipe);
752 return -EINVAL;
753 }
754
755 if (!crtc->enabled) {
756 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
757 return -EBUSY;
758 }
759
760 /* Helper routine in DRM core does all the work: */
761 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
762 vblank_time, flags,
763 crtc);
764 }
765
766 static bool intel_hpd_irq_event(struct drm_device *dev,
767 struct drm_connector *connector)
768 {
769 enum drm_connector_status old_status;
770
771 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
772 old_status = connector->status;
773
774 connector->status = connector->funcs->detect(connector, false);
775 if (old_status == connector->status)
776 return false;
777
778 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
779 connector->base.id,
780 drm_get_connector_name(connector),
781 drm_get_connector_status_name(old_status),
782 drm_get_connector_status_name(connector->status));
783
784 return true;
785 }
786
787 /*
788 * Handle hotplug events outside the interrupt handler proper.
789 */
790 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
791
792 static void i915_hotplug_work_func(struct work_struct *work)
793 {
794 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
795 hotplug_work);
796 struct drm_device *dev = dev_priv->dev;
797 struct drm_mode_config *mode_config = &dev->mode_config;
798 struct intel_connector *intel_connector;
799 struct intel_encoder *intel_encoder;
800 struct drm_connector *connector;
801 unsigned long irqflags;
802 bool hpd_disabled = false;
803 bool changed = false;
804 u32 hpd_event_bits;
805
806 /* HPD irq before everything is fully set up. */
807 if (!dev_priv->enable_hotplug_processing)
808 return;
809
810 mutex_lock(&mode_config->mutex);
811 DRM_DEBUG_KMS("running encoder hotplug functions\n");
812
813 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
814
815 hpd_event_bits = dev_priv->hpd_event_bits;
816 dev_priv->hpd_event_bits = 0;
817 list_for_each_entry(connector, &mode_config->connector_list, head) {
818 intel_connector = to_intel_connector(connector);
819 intel_encoder = intel_connector->encoder;
820 if (intel_encoder->hpd_pin > HPD_NONE &&
821 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
822 connector->polled == DRM_CONNECTOR_POLL_HPD) {
823 DRM_INFO("HPD interrupt storm detected on connector %s: "
824 "switching from hotplug detection to polling\n",
825 drm_get_connector_name(connector));
826 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
827 connector->polled = DRM_CONNECTOR_POLL_CONNECT
828 | DRM_CONNECTOR_POLL_DISCONNECT;
829 hpd_disabled = true;
830 }
831 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
832 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
833 drm_get_connector_name(connector), intel_encoder->hpd_pin);
834 }
835 }
836 /* if there were no outputs to poll, poll was disabled,
837 * therefore make sure it's enabled when disabling HPD on
838 * some connectors */
839 if (hpd_disabled) {
840 drm_kms_helper_poll_enable(dev);
841 mod_timer(&dev_priv->hotplug_reenable_timer,
842 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
843 }
844
845 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
846
847 list_for_each_entry(connector, &mode_config->connector_list, head) {
848 intel_connector = to_intel_connector(connector);
849 intel_encoder = intel_connector->encoder;
850 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
851 if (intel_encoder->hot_plug)
852 intel_encoder->hot_plug(intel_encoder);
853 if (intel_hpd_irq_event(dev, connector))
854 changed = true;
855 }
856 }
857 mutex_unlock(&mode_config->mutex);
858
859 if (changed)
860 drm_kms_helper_hotplug_event(dev);
861 }
862
863 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
864 {
865 drm_i915_private_t *dev_priv = dev->dev_private;
866 u32 busy_up, busy_down, max_avg, min_avg;
867 u8 new_delay;
868
869 spin_lock(&mchdev_lock);
870
871 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
872
873 new_delay = dev_priv->ips.cur_delay;
874
875 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
876 busy_up = I915_READ(RCPREVBSYTUPAVG);
877 busy_down = I915_READ(RCPREVBSYTDNAVG);
878 max_avg = I915_READ(RCBMAXAVG);
879 min_avg = I915_READ(RCBMINAVG);
880
881 /* Handle RCS change request from hw */
882 if (busy_up > max_avg) {
883 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
884 new_delay = dev_priv->ips.cur_delay - 1;
885 if (new_delay < dev_priv->ips.max_delay)
886 new_delay = dev_priv->ips.max_delay;
887 } else if (busy_down < min_avg) {
888 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
889 new_delay = dev_priv->ips.cur_delay + 1;
890 if (new_delay > dev_priv->ips.min_delay)
891 new_delay = dev_priv->ips.min_delay;
892 }
893
894 if (ironlake_set_drps(dev, new_delay))
895 dev_priv->ips.cur_delay = new_delay;
896
897 spin_unlock(&mchdev_lock);
898
899 return;
900 }
901
902 static void notify_ring(struct drm_device *dev,
903 struct intel_ring_buffer *ring)
904 {
905 if (ring->obj == NULL)
906 return;
907
908 trace_i915_gem_request_complete(ring);
909
910 wake_up_all(&ring->irq_queue);
911 i915_queue_hangcheck(dev);
912 }
913
914 static void gen6_pm_rps_work(struct work_struct *work)
915 {
916 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
917 rps.work);
918 u32 pm_iir;
919 int new_delay, adj;
920
921 spin_lock_irq(&dev_priv->irq_lock);
922 pm_iir = dev_priv->rps.pm_iir;
923 dev_priv->rps.pm_iir = 0;
924 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
925 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
926 spin_unlock_irq(&dev_priv->irq_lock);
927
928 /* Make sure we didn't queue anything we're not going to process. */
929 WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS);
930
931 if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
932 return;
933
934 mutex_lock(&dev_priv->rps.hw_lock);
935
936 adj = dev_priv->rps.last_adj;
937 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
938 if (adj > 0)
939 adj *= 2;
940 else
941 adj = 1;
942 new_delay = dev_priv->rps.cur_delay + adj;
943
944 /*
945 * For better performance, jump directly
946 * to RPe if we're below it.
947 */
948 if (new_delay < dev_priv->rps.rpe_delay)
949 new_delay = dev_priv->rps.rpe_delay;
950 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
951 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
952 new_delay = dev_priv->rps.rpe_delay;
953 else
954 new_delay = dev_priv->rps.min_delay;
955 adj = 0;
956 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
957 if (adj < 0)
958 adj *= 2;
959 else
960 adj = -1;
961 new_delay = dev_priv->rps.cur_delay + adj;
962 } else { /* unknown event */
963 new_delay = dev_priv->rps.cur_delay;
964 }
965
966 /* sysfs frequency interfaces may have snuck in while servicing the
967 * interrupt
968 */
969 if (new_delay < (int)dev_priv->rps.min_delay)
970 new_delay = dev_priv->rps.min_delay;
971 if (new_delay > (int)dev_priv->rps.max_delay)
972 new_delay = dev_priv->rps.max_delay;
973 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay;
974
975 if (IS_VALLEYVIEW(dev_priv->dev))
976 valleyview_set_rps(dev_priv->dev, new_delay);
977 else
978 gen6_set_rps(dev_priv->dev, new_delay);
979
980 mutex_unlock(&dev_priv->rps.hw_lock);
981 }
982
983
984 /**
985 * ivybridge_parity_work - Workqueue called when a parity error interrupt
986 * occurred.
987 * @work: workqueue struct
988 *
989 * Doesn't actually do anything except notify userspace. As a consequence of
990 * this event, userspace should try to remap the bad rows since statistically
991 * it is likely the same row is more likely to go bad again.
992 */
993 static void ivybridge_parity_work(struct work_struct *work)
994 {
995 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
996 l3_parity.error_work);
997 u32 error_status, row, bank, subbank;
998 char *parity_event[6];
999 uint32_t misccpctl;
1000 unsigned long flags;
1001 uint8_t slice = 0;
1002
1003 /* We must turn off DOP level clock gating to access the L3 registers.
1004 * In order to prevent a get/put style interface, acquire struct mutex
1005 * any time we access those registers.
1006 */
1007 mutex_lock(&dev_priv->dev->struct_mutex);
1008
1009 /* If we've screwed up tracking, just let the interrupt fire again */
1010 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1011 goto out;
1012
1013 misccpctl = I915_READ(GEN7_MISCCPCTL);
1014 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1015 POSTING_READ(GEN7_MISCCPCTL);
1016
1017 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1018 u32 reg;
1019
1020 slice--;
1021 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1022 break;
1023
1024 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1025
1026 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1027
1028 error_status = I915_READ(reg);
1029 row = GEN7_PARITY_ERROR_ROW(error_status);
1030 bank = GEN7_PARITY_ERROR_BANK(error_status);
1031 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1032
1033 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1034 POSTING_READ(reg);
1035
1036 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1037 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1038 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1039 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1040 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1041 parity_event[5] = NULL;
1042
1043 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
1044 KOBJ_CHANGE, parity_event);
1045
1046 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1047 slice, row, bank, subbank);
1048
1049 kfree(parity_event[4]);
1050 kfree(parity_event[3]);
1051 kfree(parity_event[2]);
1052 kfree(parity_event[1]);
1053 }
1054
1055 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1056
1057 out:
1058 WARN_ON(dev_priv->l3_parity.which_slice);
1059 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1060 ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1061 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1062
1063 mutex_unlock(&dev_priv->dev->struct_mutex);
1064 }
1065
1066 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1067 {
1068 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1069
1070 if (!HAS_L3_DPF(dev))
1071 return;
1072
1073 spin_lock(&dev_priv->irq_lock);
1074 ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1075 spin_unlock(&dev_priv->irq_lock);
1076
1077 iir &= GT_PARITY_ERROR(dev);
1078 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1079 dev_priv->l3_parity.which_slice |= 1 << 1;
1080
1081 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1082 dev_priv->l3_parity.which_slice |= 1 << 0;
1083
1084 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1085 }
1086
1087 static void ilk_gt_irq_handler(struct drm_device *dev,
1088 struct drm_i915_private *dev_priv,
1089 u32 gt_iir)
1090 {
1091 if (gt_iir &
1092 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1093 notify_ring(dev, &dev_priv->ring[RCS]);
1094 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1095 notify_ring(dev, &dev_priv->ring[VCS]);
1096 }
1097
1098 static void snb_gt_irq_handler(struct drm_device *dev,
1099 struct drm_i915_private *dev_priv,
1100 u32 gt_iir)
1101 {
1102
1103 if (gt_iir &
1104 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1105 notify_ring(dev, &dev_priv->ring[RCS]);
1106 if (gt_iir & GT_BSD_USER_INTERRUPT)
1107 notify_ring(dev, &dev_priv->ring[VCS]);
1108 if (gt_iir & GT_BLT_USER_INTERRUPT)
1109 notify_ring(dev, &dev_priv->ring[BCS]);
1110
1111 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1112 GT_BSD_CS_ERROR_INTERRUPT |
1113 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1114 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
1115 i915_handle_error(dev, false);
1116 }
1117
1118 if (gt_iir & GT_PARITY_ERROR(dev))
1119 ivybridge_parity_error_irq_handler(dev, gt_iir);
1120 }
1121
1122 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1123 struct drm_i915_private *dev_priv,
1124 u32 master_ctl)
1125 {
1126 u32 rcs, bcs, vcs;
1127 uint32_t tmp = 0;
1128 irqreturn_t ret = IRQ_NONE;
1129
1130 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1131 tmp = I915_READ(GEN8_GT_IIR(0));
1132 if (tmp) {
1133 ret = IRQ_HANDLED;
1134 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1135 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1136 if (rcs & GT_RENDER_USER_INTERRUPT)
1137 notify_ring(dev, &dev_priv->ring[RCS]);
1138 if (bcs & GT_RENDER_USER_INTERRUPT)
1139 notify_ring(dev, &dev_priv->ring[BCS]);
1140 I915_WRITE(GEN8_GT_IIR(0), tmp);
1141 } else
1142 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1143 }
1144
1145 if (master_ctl & GEN8_GT_VCS1_IRQ) {
1146 tmp = I915_READ(GEN8_GT_IIR(1));
1147 if (tmp) {
1148 ret = IRQ_HANDLED;
1149 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1150 if (vcs & GT_RENDER_USER_INTERRUPT)
1151 notify_ring(dev, &dev_priv->ring[VCS]);
1152 I915_WRITE(GEN8_GT_IIR(1), tmp);
1153 } else
1154 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1155 }
1156
1157 if (master_ctl & GEN8_GT_VECS_IRQ) {
1158 tmp = I915_READ(GEN8_GT_IIR(3));
1159 if (tmp) {
1160 ret = IRQ_HANDLED;
1161 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1162 if (vcs & GT_RENDER_USER_INTERRUPT)
1163 notify_ring(dev, &dev_priv->ring[VECS]);
1164 I915_WRITE(GEN8_GT_IIR(3), tmp);
1165 } else
1166 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1167 }
1168
1169 return ret;
1170 }
1171
1172 #define HPD_STORM_DETECT_PERIOD 1000
1173 #define HPD_STORM_THRESHOLD 5
1174
1175 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1176 u32 hotplug_trigger,
1177 const u32 *hpd)
1178 {
1179 drm_i915_private_t *dev_priv = dev->dev_private;
1180 int i;
1181 bool storm_detected = false;
1182
1183 if (!hotplug_trigger)
1184 return;
1185
1186 spin_lock(&dev_priv->irq_lock);
1187 for (i = 1; i < HPD_NUM_PINS; i++) {
1188
1189 WARN(((hpd[i] & hotplug_trigger) &&
1190 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED),
1191 "Received HPD interrupt although disabled\n");
1192
1193 if (!(hpd[i] & hotplug_trigger) ||
1194 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1195 continue;
1196
1197 dev_priv->hpd_event_bits |= (1 << i);
1198 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1199 dev_priv->hpd_stats[i].hpd_last_jiffies
1200 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1201 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1202 dev_priv->hpd_stats[i].hpd_cnt = 0;
1203 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1204 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1205 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1206 dev_priv->hpd_event_bits &= ~(1 << i);
1207 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1208 storm_detected = true;
1209 } else {
1210 dev_priv->hpd_stats[i].hpd_cnt++;
1211 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1212 dev_priv->hpd_stats[i].hpd_cnt);
1213 }
1214 }
1215
1216 if (storm_detected)
1217 dev_priv->display.hpd_irq_setup(dev);
1218 spin_unlock(&dev_priv->irq_lock);
1219
1220 /*
1221 * Our hotplug handler can grab modeset locks (by calling down into the
1222 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1223 * queue for otherwise the flush_work in the pageflip code will
1224 * deadlock.
1225 */
1226 schedule_work(&dev_priv->hotplug_work);
1227 }
1228
1229 static void gmbus_irq_handler(struct drm_device *dev)
1230 {
1231 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1232
1233 wake_up_all(&dev_priv->gmbus_wait_queue);
1234 }
1235
1236 static void dp_aux_irq_handler(struct drm_device *dev)
1237 {
1238 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1239
1240 wake_up_all(&dev_priv->gmbus_wait_queue);
1241 }
1242
1243 #if defined(CONFIG_DEBUG_FS)
1244 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1245 uint32_t crc0, uint32_t crc1,
1246 uint32_t crc2, uint32_t crc3,
1247 uint32_t crc4)
1248 {
1249 struct drm_i915_private *dev_priv = dev->dev_private;
1250 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1251 struct intel_pipe_crc_entry *entry;
1252 int head, tail;
1253
1254 spin_lock(&pipe_crc->lock);
1255
1256 if (!pipe_crc->entries) {
1257 spin_unlock(&pipe_crc->lock);
1258 DRM_ERROR("spurious interrupt\n");
1259 return;
1260 }
1261
1262 head = pipe_crc->head;
1263 tail = pipe_crc->tail;
1264
1265 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1266 spin_unlock(&pipe_crc->lock);
1267 DRM_ERROR("CRC buffer overflowing\n");
1268 return;
1269 }
1270
1271 entry = &pipe_crc->entries[head];
1272
1273 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1274 entry->crc[0] = crc0;
1275 entry->crc[1] = crc1;
1276 entry->crc[2] = crc2;
1277 entry->crc[3] = crc3;
1278 entry->crc[4] = crc4;
1279
1280 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1281 pipe_crc->head = head;
1282
1283 spin_unlock(&pipe_crc->lock);
1284
1285 wake_up_interruptible(&pipe_crc->wq);
1286 }
1287 #else
1288 static inline void
1289 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1290 uint32_t crc0, uint32_t crc1,
1291 uint32_t crc2, uint32_t crc3,
1292 uint32_t crc4) {}
1293 #endif
1294
1295
1296 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1297 {
1298 struct drm_i915_private *dev_priv = dev->dev_private;
1299
1300 display_pipe_crc_irq_handler(dev, pipe,
1301 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1302 0, 0, 0, 0);
1303 }
1304
1305 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1306 {
1307 struct drm_i915_private *dev_priv = dev->dev_private;
1308
1309 display_pipe_crc_irq_handler(dev, pipe,
1310 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1311 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1312 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1313 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1314 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1315 }
1316
1317 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1318 {
1319 struct drm_i915_private *dev_priv = dev->dev_private;
1320 uint32_t res1, res2;
1321
1322 if (INTEL_INFO(dev)->gen >= 3)
1323 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1324 else
1325 res1 = 0;
1326
1327 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1328 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1329 else
1330 res2 = 0;
1331
1332 display_pipe_crc_irq_handler(dev, pipe,
1333 I915_READ(PIPE_CRC_RES_RED(pipe)),
1334 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1335 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1336 res1, res2);
1337 }
1338
1339 /* The RPS events need forcewake, so we add them to a work queue and mask their
1340 * IMR bits until the work is done. Other interrupts can be processed without
1341 * the work queue. */
1342 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1343 {
1344 if (pm_iir & GEN6_PM_RPS_EVENTS) {
1345 spin_lock(&dev_priv->irq_lock);
1346 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
1347 snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS);
1348 spin_unlock(&dev_priv->irq_lock);
1349
1350 queue_work(dev_priv->wq, &dev_priv->rps.work);
1351 }
1352
1353 if (HAS_VEBOX(dev_priv->dev)) {
1354 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1355 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1356
1357 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1358 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
1359 i915_handle_error(dev_priv->dev, false);
1360 }
1361 }
1362 }
1363
1364 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1365 {
1366 struct drm_device *dev = (struct drm_device *) arg;
1367 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1368 u32 iir, gt_iir, pm_iir;
1369 irqreturn_t ret = IRQ_NONE;
1370 unsigned long irqflags;
1371 int pipe;
1372 u32 pipe_stats[I915_MAX_PIPES];
1373
1374 atomic_inc(&dev_priv->irq_received);
1375
1376 while (true) {
1377 iir = I915_READ(VLV_IIR);
1378 gt_iir = I915_READ(GTIIR);
1379 pm_iir = I915_READ(GEN6_PMIIR);
1380
1381 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1382 goto out;
1383
1384 ret = IRQ_HANDLED;
1385
1386 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1387
1388 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1389 for_each_pipe(pipe) {
1390 int reg = PIPESTAT(pipe);
1391 pipe_stats[pipe] = I915_READ(reg);
1392
1393 /*
1394 * Clear the PIPE*STAT regs before the IIR
1395 */
1396 if (pipe_stats[pipe] & 0x8000ffff) {
1397 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1398 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1399 pipe_name(pipe));
1400 I915_WRITE(reg, pipe_stats[pipe]);
1401 }
1402 }
1403 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1404
1405 for_each_pipe(pipe) {
1406 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1407 drm_handle_vblank(dev, pipe);
1408
1409 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1410 intel_prepare_page_flip(dev, pipe);
1411 intel_finish_page_flip(dev, pipe);
1412 }
1413
1414 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1415 i9xx_pipe_crc_irq_handler(dev, pipe);
1416 }
1417
1418 /* Consume port. Then clear IIR or we'll miss events */
1419 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1420 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1421 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1422
1423 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1424 hotplug_status);
1425
1426 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1427
1428 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1429 I915_READ(PORT_HOTPLUG_STAT);
1430 }
1431
1432 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1433 gmbus_irq_handler(dev);
1434
1435 if (pm_iir)
1436 gen6_rps_irq_handler(dev_priv, pm_iir);
1437
1438 I915_WRITE(GTIIR, gt_iir);
1439 I915_WRITE(GEN6_PMIIR, pm_iir);
1440 I915_WRITE(VLV_IIR, iir);
1441 }
1442
1443 out:
1444 return ret;
1445 }
1446
1447 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1448 {
1449 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1450 int pipe;
1451 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1452
1453 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1454
1455 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1456 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1457 SDE_AUDIO_POWER_SHIFT);
1458 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1459 port_name(port));
1460 }
1461
1462 if (pch_iir & SDE_AUX_MASK)
1463 dp_aux_irq_handler(dev);
1464
1465 if (pch_iir & SDE_GMBUS)
1466 gmbus_irq_handler(dev);
1467
1468 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1469 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1470
1471 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1472 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1473
1474 if (pch_iir & SDE_POISON)
1475 DRM_ERROR("PCH poison interrupt\n");
1476
1477 if (pch_iir & SDE_FDI_MASK)
1478 for_each_pipe(pipe)
1479 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1480 pipe_name(pipe),
1481 I915_READ(FDI_RX_IIR(pipe)));
1482
1483 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1484 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1485
1486 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1487 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1488
1489 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1490 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1491 false))
1492 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1493
1494 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1495 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1496 false))
1497 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1498 }
1499
1500 static void ivb_err_int_handler(struct drm_device *dev)
1501 {
1502 struct drm_i915_private *dev_priv = dev->dev_private;
1503 u32 err_int = I915_READ(GEN7_ERR_INT);
1504 enum pipe pipe;
1505
1506 if (err_int & ERR_INT_POISON)
1507 DRM_ERROR("Poison interrupt\n");
1508
1509 for_each_pipe(pipe) {
1510 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1511 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1512 false))
1513 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
1514 pipe_name(pipe));
1515 }
1516
1517 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1518 if (IS_IVYBRIDGE(dev))
1519 ivb_pipe_crc_irq_handler(dev, pipe);
1520 else
1521 hsw_pipe_crc_irq_handler(dev, pipe);
1522 }
1523 }
1524
1525 I915_WRITE(GEN7_ERR_INT, err_int);
1526 }
1527
1528 static void cpt_serr_int_handler(struct drm_device *dev)
1529 {
1530 struct drm_i915_private *dev_priv = dev->dev_private;
1531 u32 serr_int = I915_READ(SERR_INT);
1532
1533 if (serr_int & SERR_INT_POISON)
1534 DRM_ERROR("PCH poison interrupt\n");
1535
1536 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1537 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1538 false))
1539 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1540
1541 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1542 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1543 false))
1544 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1545
1546 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1547 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1548 false))
1549 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1550
1551 I915_WRITE(SERR_INT, serr_int);
1552 }
1553
1554 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1555 {
1556 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1557 int pipe;
1558 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1559
1560 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1561
1562 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1563 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1564 SDE_AUDIO_POWER_SHIFT_CPT);
1565 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1566 port_name(port));
1567 }
1568
1569 if (pch_iir & SDE_AUX_MASK_CPT)
1570 dp_aux_irq_handler(dev);
1571
1572 if (pch_iir & SDE_GMBUS_CPT)
1573 gmbus_irq_handler(dev);
1574
1575 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1576 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1577
1578 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1579 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1580
1581 if (pch_iir & SDE_FDI_MASK_CPT)
1582 for_each_pipe(pipe)
1583 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1584 pipe_name(pipe),
1585 I915_READ(FDI_RX_IIR(pipe)));
1586
1587 if (pch_iir & SDE_ERROR_CPT)
1588 cpt_serr_int_handler(dev);
1589 }
1590
1591 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1592 {
1593 struct drm_i915_private *dev_priv = dev->dev_private;
1594 enum pipe pipe;
1595
1596 if (de_iir & DE_AUX_CHANNEL_A)
1597 dp_aux_irq_handler(dev);
1598
1599 if (de_iir & DE_GSE)
1600 intel_opregion_asle_intr(dev);
1601
1602 if (de_iir & DE_POISON)
1603 DRM_ERROR("Poison interrupt\n");
1604
1605 for_each_pipe(pipe) {
1606 if (de_iir & DE_PIPE_VBLANK(pipe))
1607 drm_handle_vblank(dev, pipe);
1608
1609 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1610 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1611 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
1612 pipe_name(pipe));
1613
1614 if (de_iir & DE_PIPE_CRC_DONE(pipe))
1615 i9xx_pipe_crc_irq_handler(dev, pipe);
1616
1617 /* plane/pipes map 1:1 on ilk+ */
1618 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
1619 intel_prepare_page_flip(dev, pipe);
1620 intel_finish_page_flip_plane(dev, pipe);
1621 }
1622 }
1623
1624 /* check event from PCH */
1625 if (de_iir & DE_PCH_EVENT) {
1626 u32 pch_iir = I915_READ(SDEIIR);
1627
1628 if (HAS_PCH_CPT(dev))
1629 cpt_irq_handler(dev, pch_iir);
1630 else
1631 ibx_irq_handler(dev, pch_iir);
1632
1633 /* should clear PCH hotplug event before clear CPU irq */
1634 I915_WRITE(SDEIIR, pch_iir);
1635 }
1636
1637 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1638 ironlake_rps_change_irq_handler(dev);
1639 }
1640
1641 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1642 {
1643 struct drm_i915_private *dev_priv = dev->dev_private;
1644 enum pipe i;
1645
1646 if (de_iir & DE_ERR_INT_IVB)
1647 ivb_err_int_handler(dev);
1648
1649 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1650 dp_aux_irq_handler(dev);
1651
1652 if (de_iir & DE_GSE_IVB)
1653 intel_opregion_asle_intr(dev);
1654
1655 for_each_pipe(i) {
1656 if (de_iir & (DE_PIPE_VBLANK_IVB(i)))
1657 drm_handle_vblank(dev, i);
1658
1659 /* plane/pipes map 1:1 on ilk+ */
1660 if (de_iir & DE_PLANE_FLIP_DONE_IVB(i)) {
1661 intel_prepare_page_flip(dev, i);
1662 intel_finish_page_flip_plane(dev, i);
1663 }
1664 }
1665
1666 /* check event from PCH */
1667 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1668 u32 pch_iir = I915_READ(SDEIIR);
1669
1670 cpt_irq_handler(dev, pch_iir);
1671
1672 /* clear PCH hotplug event before clear CPU irq */
1673 I915_WRITE(SDEIIR, pch_iir);
1674 }
1675 }
1676
1677 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1678 {
1679 struct drm_device *dev = (struct drm_device *) arg;
1680 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1681 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
1682 irqreturn_t ret = IRQ_NONE;
1683
1684 atomic_inc(&dev_priv->irq_received);
1685
1686 /* We get interrupts on unclaimed registers, so check for this before we
1687 * do any I915_{READ,WRITE}. */
1688 intel_uncore_check_errors(dev);
1689
1690 /* disable master interrupt before clearing iir */
1691 de_ier = I915_READ(DEIER);
1692 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1693 POSTING_READ(DEIER);
1694
1695 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1696 * interrupts will will be stored on its back queue, and then we'll be
1697 * able to process them after we restore SDEIER (as soon as we restore
1698 * it, we'll get an interrupt if SDEIIR still has something to process
1699 * due to its back queue). */
1700 if (!HAS_PCH_NOP(dev)) {
1701 sde_ier = I915_READ(SDEIER);
1702 I915_WRITE(SDEIER, 0);
1703 POSTING_READ(SDEIER);
1704 }
1705
1706 gt_iir = I915_READ(GTIIR);
1707 if (gt_iir) {
1708 if (INTEL_INFO(dev)->gen >= 6)
1709 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1710 else
1711 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1712 I915_WRITE(GTIIR, gt_iir);
1713 ret = IRQ_HANDLED;
1714 }
1715
1716 de_iir = I915_READ(DEIIR);
1717 if (de_iir) {
1718 if (INTEL_INFO(dev)->gen >= 7)
1719 ivb_display_irq_handler(dev, de_iir);
1720 else
1721 ilk_display_irq_handler(dev, de_iir);
1722 I915_WRITE(DEIIR, de_iir);
1723 ret = IRQ_HANDLED;
1724 }
1725
1726 if (INTEL_INFO(dev)->gen >= 6) {
1727 u32 pm_iir = I915_READ(GEN6_PMIIR);
1728 if (pm_iir) {
1729 gen6_rps_irq_handler(dev_priv, pm_iir);
1730 I915_WRITE(GEN6_PMIIR, pm_iir);
1731 ret = IRQ_HANDLED;
1732 }
1733 }
1734
1735 I915_WRITE(DEIER, de_ier);
1736 POSTING_READ(DEIER);
1737 if (!HAS_PCH_NOP(dev)) {
1738 I915_WRITE(SDEIER, sde_ier);
1739 POSTING_READ(SDEIER);
1740 }
1741
1742 return ret;
1743 }
1744
1745 static irqreturn_t gen8_irq_handler(int irq, void *arg)
1746 {
1747 struct drm_device *dev = arg;
1748 struct drm_i915_private *dev_priv = dev->dev_private;
1749 u32 master_ctl;
1750 irqreturn_t ret = IRQ_NONE;
1751 uint32_t tmp = 0;
1752 enum pipe pipe;
1753
1754 atomic_inc(&dev_priv->irq_received);
1755
1756 master_ctl = I915_READ(GEN8_MASTER_IRQ);
1757 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
1758 if (!master_ctl)
1759 return IRQ_NONE;
1760
1761 I915_WRITE(GEN8_MASTER_IRQ, 0);
1762 POSTING_READ(GEN8_MASTER_IRQ);
1763
1764 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1765
1766 if (master_ctl & GEN8_DE_MISC_IRQ) {
1767 tmp = I915_READ(GEN8_DE_MISC_IIR);
1768 if (tmp & GEN8_DE_MISC_GSE)
1769 intel_opregion_asle_intr(dev);
1770 else if (tmp)
1771 DRM_ERROR("Unexpected DE Misc interrupt\n");
1772 else
1773 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
1774
1775 if (tmp) {
1776 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
1777 ret = IRQ_HANDLED;
1778 }
1779 }
1780
1781 if (master_ctl & GEN8_DE_PORT_IRQ) {
1782 tmp = I915_READ(GEN8_DE_PORT_IIR);
1783 if (tmp & GEN8_AUX_CHANNEL_A)
1784 dp_aux_irq_handler(dev);
1785 else if (tmp)
1786 DRM_ERROR("Unexpected DE Port interrupt\n");
1787 else
1788 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
1789
1790 if (tmp) {
1791 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
1792 ret = IRQ_HANDLED;
1793 }
1794 }
1795
1796 for_each_pipe(pipe) {
1797 uint32_t pipe_iir;
1798
1799 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
1800 continue;
1801
1802 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
1803 if (pipe_iir & GEN8_PIPE_VBLANK)
1804 drm_handle_vblank(dev, pipe);
1805
1806 if (pipe_iir & GEN8_PIPE_FLIP_DONE) {
1807 intel_prepare_page_flip(dev, pipe);
1808 intel_finish_page_flip_plane(dev, pipe);
1809 }
1810
1811 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
1812 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
1813 pipe_name(pipe),
1814 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
1815 }
1816
1817 if (pipe_iir) {
1818 ret = IRQ_HANDLED;
1819 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
1820 } else
1821 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
1822 }
1823
1824 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
1825 /*
1826 * FIXME(BDW): Assume for now that the new interrupt handling
1827 * scheme also closed the SDE interrupt handling race we've seen
1828 * on older pch-split platforms. But this needs testing.
1829 */
1830 u32 pch_iir = I915_READ(SDEIIR);
1831
1832 cpt_irq_handler(dev, pch_iir);
1833
1834 if (pch_iir) {
1835 I915_WRITE(SDEIIR, pch_iir);
1836 ret = IRQ_HANDLED;
1837 }
1838 }
1839
1840 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1841 POSTING_READ(GEN8_MASTER_IRQ);
1842
1843 return ret;
1844 }
1845
1846 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
1847 bool reset_completed)
1848 {
1849 struct intel_ring_buffer *ring;
1850 int i;
1851
1852 /*
1853 * Notify all waiters for GPU completion events that reset state has
1854 * been changed, and that they need to restart their wait after
1855 * checking for potential errors (and bail out to drop locks if there is
1856 * a gpu reset pending so that i915_error_work_func can acquire them).
1857 */
1858
1859 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
1860 for_each_ring(ring, dev_priv, i)
1861 wake_up_all(&ring->irq_queue);
1862
1863 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
1864 wake_up_all(&dev_priv->pending_flip_queue);
1865
1866 /*
1867 * Signal tasks blocked in i915_gem_wait_for_error that the pending
1868 * reset state is cleared.
1869 */
1870 if (reset_completed)
1871 wake_up_all(&dev_priv->gpu_error.reset_queue);
1872 }
1873
1874 /**
1875 * i915_error_work_func - do process context error handling work
1876 * @work: work struct
1877 *
1878 * Fire an error uevent so userspace can see that a hang or error
1879 * was detected.
1880 */
1881 static void i915_error_work_func(struct work_struct *work)
1882 {
1883 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1884 work);
1885 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1886 gpu_error);
1887 struct drm_device *dev = dev_priv->dev;
1888 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1889 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1890 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1891 int ret;
1892
1893 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
1894
1895 /*
1896 * Note that there's only one work item which does gpu resets, so we
1897 * need not worry about concurrent gpu resets potentially incrementing
1898 * error->reset_counter twice. We only need to take care of another
1899 * racing irq/hangcheck declaring the gpu dead for a second time. A
1900 * quick check for that is good enough: schedule_work ensures the
1901 * correct ordering between hang detection and this work item, and since
1902 * the reset in-progress bit is only ever set by code outside of this
1903 * work we don't need to worry about any other races.
1904 */
1905 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
1906 DRM_DEBUG_DRIVER("resetting chip\n");
1907 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1908 reset_event);
1909
1910 /*
1911 * All state reset _must_ be completed before we update the
1912 * reset counter, for otherwise waiters might miss the reset
1913 * pending state and not properly drop locks, resulting in
1914 * deadlocks with the reset work.
1915 */
1916 ret = i915_reset(dev);
1917
1918 intel_display_handle_reset(dev);
1919
1920 if (ret == 0) {
1921 /*
1922 * After all the gem state is reset, increment the reset
1923 * counter and wake up everyone waiting for the reset to
1924 * complete.
1925 *
1926 * Since unlock operations are a one-sided barrier only,
1927 * we need to insert a barrier here to order any seqno
1928 * updates before
1929 * the counter increment.
1930 */
1931 smp_mb__before_atomic_inc();
1932 atomic_inc(&dev_priv->gpu_error.reset_counter);
1933
1934 kobject_uevent_env(&dev->primary->kdev.kobj,
1935 KOBJ_CHANGE, reset_done_event);
1936 } else {
1937 atomic_set(&error->reset_counter, I915_WEDGED);
1938 }
1939
1940 /*
1941 * Note: The wake_up also serves as a memory barrier so that
1942 * waiters see the update value of the reset counter atomic_t.
1943 */
1944 i915_error_wake_up(dev_priv, true);
1945 }
1946 }
1947
1948 static void i915_report_and_clear_eir(struct drm_device *dev)
1949 {
1950 struct drm_i915_private *dev_priv = dev->dev_private;
1951 uint32_t instdone[I915_NUM_INSTDONE_REG];
1952 u32 eir = I915_READ(EIR);
1953 int pipe, i;
1954
1955 if (!eir)
1956 return;
1957
1958 pr_err("render error detected, EIR: 0x%08x\n", eir);
1959
1960 i915_get_extra_instdone(dev, instdone);
1961
1962 if (IS_G4X(dev)) {
1963 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1964 u32 ipeir = I915_READ(IPEIR_I965);
1965
1966 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1967 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1968 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1969 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1970 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1971 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1972 I915_WRITE(IPEIR_I965, ipeir);
1973 POSTING_READ(IPEIR_I965);
1974 }
1975 if (eir & GM45_ERROR_PAGE_TABLE) {
1976 u32 pgtbl_err = I915_READ(PGTBL_ER);
1977 pr_err("page table error\n");
1978 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
1979 I915_WRITE(PGTBL_ER, pgtbl_err);
1980 POSTING_READ(PGTBL_ER);
1981 }
1982 }
1983
1984 if (!IS_GEN2(dev)) {
1985 if (eir & I915_ERROR_PAGE_TABLE) {
1986 u32 pgtbl_err = I915_READ(PGTBL_ER);
1987 pr_err("page table error\n");
1988 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
1989 I915_WRITE(PGTBL_ER, pgtbl_err);
1990 POSTING_READ(PGTBL_ER);
1991 }
1992 }
1993
1994 if (eir & I915_ERROR_MEMORY_REFRESH) {
1995 pr_err("memory refresh error:\n");
1996 for_each_pipe(pipe)
1997 pr_err("pipe %c stat: 0x%08x\n",
1998 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1999 /* pipestat has already been acked */
2000 }
2001 if (eir & I915_ERROR_INSTRUCTION) {
2002 pr_err("instruction error\n");
2003 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2004 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2005 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2006 if (INTEL_INFO(dev)->gen < 4) {
2007 u32 ipeir = I915_READ(IPEIR);
2008
2009 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2010 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2011 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2012 I915_WRITE(IPEIR, ipeir);
2013 POSTING_READ(IPEIR);
2014 } else {
2015 u32 ipeir = I915_READ(IPEIR_I965);
2016
2017 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2018 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2019 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2020 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2021 I915_WRITE(IPEIR_I965, ipeir);
2022 POSTING_READ(IPEIR_I965);
2023 }
2024 }
2025
2026 I915_WRITE(EIR, eir);
2027 POSTING_READ(EIR);
2028 eir = I915_READ(EIR);
2029 if (eir) {
2030 /*
2031 * some errors might have become stuck,
2032 * mask them.
2033 */
2034 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2035 I915_WRITE(EMR, I915_READ(EMR) | eir);
2036 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2037 }
2038 }
2039
2040 /**
2041 * i915_handle_error - handle an error interrupt
2042 * @dev: drm device
2043 *
2044 * Do some basic checking of regsiter state at error interrupt time and
2045 * dump it to the syslog. Also call i915_capture_error_state() to make
2046 * sure we get a record and make it available in debugfs. Fire a uevent
2047 * so userspace knows something bad happened (should trigger collection
2048 * of a ring dump etc.).
2049 */
2050 void i915_handle_error(struct drm_device *dev, bool wedged)
2051 {
2052 struct drm_i915_private *dev_priv = dev->dev_private;
2053
2054 i915_capture_error_state(dev);
2055 i915_report_and_clear_eir(dev);
2056
2057 if (wedged) {
2058 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2059 &dev_priv->gpu_error.reset_counter);
2060
2061 /*
2062 * Wakeup waiting processes so that the reset work function
2063 * i915_error_work_func doesn't deadlock trying to grab various
2064 * locks. By bumping the reset counter first, the woken
2065 * processes will see a reset in progress and back off,
2066 * releasing their locks and then wait for the reset completion.
2067 * We must do this for _all_ gpu waiters that might hold locks
2068 * that the reset work needs to acquire.
2069 *
2070 * Note: The wake_up serves as the required memory barrier to
2071 * ensure that the waiters see the updated value of the reset
2072 * counter atomic_t.
2073 */
2074 i915_error_wake_up(dev_priv, false);
2075 }
2076
2077 /*
2078 * Our reset work can grab modeset locks (since it needs to reset the
2079 * state of outstanding pagelips). Hence it must not be run on our own
2080 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2081 * code will deadlock.
2082 */
2083 schedule_work(&dev_priv->gpu_error.work);
2084 }
2085
2086 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2087 {
2088 drm_i915_private_t *dev_priv = dev->dev_private;
2089 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2091 struct drm_i915_gem_object *obj;
2092 struct intel_unpin_work *work;
2093 unsigned long flags;
2094 bool stall_detected;
2095
2096 /* Ignore early vblank irqs */
2097 if (intel_crtc == NULL)
2098 return;
2099
2100 spin_lock_irqsave(&dev->event_lock, flags);
2101 work = intel_crtc->unpin_work;
2102
2103 if (work == NULL ||
2104 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2105 !work->enable_stall_check) {
2106 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2107 spin_unlock_irqrestore(&dev->event_lock, flags);
2108 return;
2109 }
2110
2111 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2112 obj = work->pending_flip_obj;
2113 if (INTEL_INFO(dev)->gen >= 4) {
2114 int dspsurf = DSPSURF(intel_crtc->plane);
2115 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2116 i915_gem_obj_ggtt_offset(obj);
2117 } else {
2118 int dspaddr = DSPADDR(intel_crtc->plane);
2119 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2120 crtc->y * crtc->fb->pitches[0] +
2121 crtc->x * crtc->fb->bits_per_pixel/8);
2122 }
2123
2124 spin_unlock_irqrestore(&dev->event_lock, flags);
2125
2126 if (stall_detected) {
2127 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2128 intel_prepare_page_flip(dev, intel_crtc->plane);
2129 }
2130 }
2131
2132 /* Called from drm generic code, passed 'crtc' which
2133 * we use as a pipe index
2134 */
2135 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2136 {
2137 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2138 unsigned long irqflags;
2139
2140 if (!i915_pipe_enabled(dev, pipe))
2141 return -EINVAL;
2142
2143 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2144 if (INTEL_INFO(dev)->gen >= 4)
2145 i915_enable_pipestat(dev_priv, pipe,
2146 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2147 else
2148 i915_enable_pipestat(dev_priv, pipe,
2149 PIPE_VBLANK_INTERRUPT_ENABLE);
2150
2151 /* maintain vblank delivery even in deep C-states */
2152 if (dev_priv->info->gen == 3)
2153 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
2154 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2155
2156 return 0;
2157 }
2158
2159 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2160 {
2161 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2162 unsigned long irqflags;
2163 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2164 DE_PIPE_VBLANK(pipe);
2165
2166 if (!i915_pipe_enabled(dev, pipe))
2167 return -EINVAL;
2168
2169 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2170 ironlake_enable_display_irq(dev_priv, bit);
2171 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2172
2173 return 0;
2174 }
2175
2176 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2177 {
2178 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2179 unsigned long irqflags;
2180 u32 imr;
2181
2182 if (!i915_pipe_enabled(dev, pipe))
2183 return -EINVAL;
2184
2185 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2186 imr = I915_READ(VLV_IMR);
2187 if (pipe == PIPE_A)
2188 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
2189 else
2190 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2191 I915_WRITE(VLV_IMR, imr);
2192 i915_enable_pipestat(dev_priv, pipe,
2193 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2194 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2195
2196 return 0;
2197 }
2198
2199 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2200 {
2201 struct drm_i915_private *dev_priv = dev->dev_private;
2202 unsigned long irqflags;
2203 uint32_t imr;
2204
2205 if (!i915_pipe_enabled(dev, pipe))
2206 return -EINVAL;
2207
2208 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2209 imr = I915_READ(GEN8_DE_PIPE_IMR(pipe));
2210 if ((imr & GEN8_PIPE_VBLANK) == 1) {
2211 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), imr & ~GEN8_PIPE_VBLANK);
2212 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2213 }
2214 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2215 return 0;
2216 }
2217
2218 /* Called from drm generic code, passed 'crtc' which
2219 * we use as a pipe index
2220 */
2221 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2222 {
2223 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2224 unsigned long irqflags;
2225
2226 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2227 if (dev_priv->info->gen == 3)
2228 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
2229
2230 i915_disable_pipestat(dev_priv, pipe,
2231 PIPE_VBLANK_INTERRUPT_ENABLE |
2232 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2233 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2234 }
2235
2236 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2237 {
2238 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2239 unsigned long irqflags;
2240 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2241 DE_PIPE_VBLANK(pipe);
2242
2243 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2244 ironlake_disable_display_irq(dev_priv, bit);
2245 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2246 }
2247
2248 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2249 {
2250 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2251 unsigned long irqflags;
2252 u32 imr;
2253
2254 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2255 i915_disable_pipestat(dev_priv, pipe,
2256 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2257 imr = I915_READ(VLV_IMR);
2258 if (pipe == PIPE_A)
2259 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
2260 else
2261 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2262 I915_WRITE(VLV_IMR, imr);
2263 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2264 }
2265
2266 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2267 {
2268 struct drm_i915_private *dev_priv = dev->dev_private;
2269 unsigned long irqflags;
2270 uint32_t imr;
2271
2272 if (!i915_pipe_enabled(dev, pipe))
2273 return;
2274
2275 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2276 imr = I915_READ(GEN8_DE_PIPE_IMR(pipe));
2277 if ((imr & GEN8_PIPE_VBLANK) == 0) {
2278 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), imr | GEN8_PIPE_VBLANK);
2279 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2280 }
2281 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2282 }
2283
2284 static u32
2285 ring_last_seqno(struct intel_ring_buffer *ring)
2286 {
2287 return list_entry(ring->request_list.prev,
2288 struct drm_i915_gem_request, list)->seqno;
2289 }
2290
2291 static bool
2292 ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2293 {
2294 return (list_empty(&ring->request_list) ||
2295 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2296 }
2297
2298 static struct intel_ring_buffer *
2299 semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
2300 {
2301 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2302 u32 cmd, ipehr, acthd, acthd_min;
2303
2304 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2305 if ((ipehr & ~(0x3 << 16)) !=
2306 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
2307 return NULL;
2308
2309 /* ACTHD is likely pointing to the dword after the actual command,
2310 * so scan backwards until we find the MBOX.
2311 */
2312 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
2313 acthd_min = max((int)acthd - 3 * 4, 0);
2314 do {
2315 cmd = ioread32(ring->virtual_start + acthd);
2316 if (cmd == ipehr)
2317 break;
2318
2319 acthd -= 4;
2320 if (acthd < acthd_min)
2321 return NULL;
2322 } while (1);
2323
2324 *seqno = ioread32(ring->virtual_start+acthd+4)+1;
2325 return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
2326 }
2327
2328 static int semaphore_passed(struct intel_ring_buffer *ring)
2329 {
2330 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2331 struct intel_ring_buffer *signaller;
2332 u32 seqno, ctl;
2333
2334 ring->hangcheck.deadlock = true;
2335
2336 signaller = semaphore_waits_for(ring, &seqno);
2337 if (signaller == NULL || signaller->hangcheck.deadlock)
2338 return -1;
2339
2340 /* cursory check for an unkickable deadlock */
2341 ctl = I915_READ_CTL(signaller);
2342 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2343 return -1;
2344
2345 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2346 }
2347
2348 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2349 {
2350 struct intel_ring_buffer *ring;
2351 int i;
2352
2353 for_each_ring(ring, dev_priv, i)
2354 ring->hangcheck.deadlock = false;
2355 }
2356
2357 static enum intel_ring_hangcheck_action
2358 ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
2359 {
2360 struct drm_device *dev = ring->dev;
2361 struct drm_i915_private *dev_priv = dev->dev_private;
2362 u32 tmp;
2363
2364 if (ring->hangcheck.acthd != acthd)
2365 return HANGCHECK_ACTIVE;
2366
2367 if (IS_GEN2(dev))
2368 return HANGCHECK_HUNG;
2369
2370 /* Is the chip hanging on a WAIT_FOR_EVENT?
2371 * If so we can simply poke the RB_WAIT bit
2372 * and break the hang. This should work on
2373 * all but the second generation chipsets.
2374 */
2375 tmp = I915_READ_CTL(ring);
2376 if (tmp & RING_WAIT) {
2377 DRM_ERROR("Kicking stuck wait on %s\n",
2378 ring->name);
2379 i915_handle_error(dev, false);
2380 I915_WRITE_CTL(ring, tmp);
2381 return HANGCHECK_KICK;
2382 }
2383
2384 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2385 switch (semaphore_passed(ring)) {
2386 default:
2387 return HANGCHECK_HUNG;
2388 case 1:
2389 DRM_ERROR("Kicking stuck semaphore on %s\n",
2390 ring->name);
2391 i915_handle_error(dev, false);
2392 I915_WRITE_CTL(ring, tmp);
2393 return HANGCHECK_KICK;
2394 case 0:
2395 return HANGCHECK_WAIT;
2396 }
2397 }
2398
2399 return HANGCHECK_HUNG;
2400 }
2401
2402 /**
2403 * This is called when the chip hasn't reported back with completed
2404 * batchbuffers in a long time. We keep track per ring seqno progress and
2405 * if there are no progress, hangcheck score for that ring is increased.
2406 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2407 * we kick the ring. If we see no progress on three subsequent calls
2408 * we assume chip is wedged and try to fix it by resetting the chip.
2409 */
2410 static void i915_hangcheck_elapsed(unsigned long data)
2411 {
2412 struct drm_device *dev = (struct drm_device *)data;
2413 drm_i915_private_t *dev_priv = dev->dev_private;
2414 struct intel_ring_buffer *ring;
2415 int i;
2416 int busy_count = 0, rings_hung = 0;
2417 bool stuck[I915_NUM_RINGS] = { 0 };
2418 #define BUSY 1
2419 #define KICK 5
2420 #define HUNG 20
2421 #define FIRE 30
2422
2423 if (!i915_enable_hangcheck)
2424 return;
2425
2426 for_each_ring(ring, dev_priv, i) {
2427 u32 seqno, acthd;
2428 bool busy = true;
2429
2430 semaphore_clear_deadlocks(dev_priv);
2431
2432 seqno = ring->get_seqno(ring, false);
2433 acthd = intel_ring_get_active_head(ring);
2434
2435 if (ring->hangcheck.seqno == seqno) {
2436 if (ring_idle(ring, seqno)) {
2437 ring->hangcheck.action = HANGCHECK_IDLE;
2438
2439 if (waitqueue_active(&ring->irq_queue)) {
2440 /* Issue a wake-up to catch stuck h/w. */
2441 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2442 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2443 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2444 ring->name);
2445 else
2446 DRM_INFO("Fake missed irq on %s\n",
2447 ring->name);
2448 wake_up_all(&ring->irq_queue);
2449 }
2450 /* Safeguard against driver failure */
2451 ring->hangcheck.score += BUSY;
2452 } else
2453 busy = false;
2454 } else {
2455 /* We always increment the hangcheck score
2456 * if the ring is busy and still processing
2457 * the same request, so that no single request
2458 * can run indefinitely (such as a chain of
2459 * batches). The only time we do not increment
2460 * the hangcheck score on this ring, if this
2461 * ring is in a legitimate wait for another
2462 * ring. In that case the waiting ring is a
2463 * victim and we want to be sure we catch the
2464 * right culprit. Then every time we do kick
2465 * the ring, add a small increment to the
2466 * score so that we can catch a batch that is
2467 * being repeatedly kicked and so responsible
2468 * for stalling the machine.
2469 */
2470 ring->hangcheck.action = ring_stuck(ring,
2471 acthd);
2472
2473 switch (ring->hangcheck.action) {
2474 case HANGCHECK_IDLE:
2475 case HANGCHECK_WAIT:
2476 break;
2477 case HANGCHECK_ACTIVE:
2478 ring->hangcheck.score += BUSY;
2479 break;
2480 case HANGCHECK_KICK:
2481 ring->hangcheck.score += KICK;
2482 break;
2483 case HANGCHECK_HUNG:
2484 ring->hangcheck.score += HUNG;
2485 stuck[i] = true;
2486 break;
2487 }
2488 }
2489 } else {
2490 ring->hangcheck.action = HANGCHECK_ACTIVE;
2491
2492 /* Gradually reduce the count so that we catch DoS
2493 * attempts across multiple batches.
2494 */
2495 if (ring->hangcheck.score > 0)
2496 ring->hangcheck.score--;
2497 }
2498
2499 ring->hangcheck.seqno = seqno;
2500 ring->hangcheck.acthd = acthd;
2501 busy_count += busy;
2502 }
2503
2504 for_each_ring(ring, dev_priv, i) {
2505 if (ring->hangcheck.score > FIRE) {
2506 DRM_INFO("%s on %s\n",
2507 stuck[i] ? "stuck" : "no progress",
2508 ring->name);
2509 rings_hung++;
2510 }
2511 }
2512
2513 if (rings_hung)
2514 return i915_handle_error(dev, true);
2515
2516 if (busy_count)
2517 /* Reset timer case chip hangs without another request
2518 * being added */
2519 i915_queue_hangcheck(dev);
2520 }
2521
2522 void i915_queue_hangcheck(struct drm_device *dev)
2523 {
2524 struct drm_i915_private *dev_priv = dev->dev_private;
2525 if (!i915_enable_hangcheck)
2526 return;
2527
2528 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2529 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2530 }
2531
2532 static void ibx_irq_preinstall(struct drm_device *dev)
2533 {
2534 struct drm_i915_private *dev_priv = dev->dev_private;
2535
2536 if (HAS_PCH_NOP(dev))
2537 return;
2538
2539 /* south display irq */
2540 I915_WRITE(SDEIMR, 0xffffffff);
2541 /*
2542 * SDEIER is also touched by the interrupt handler to work around missed
2543 * PCH interrupts. Hence we can't update it after the interrupt handler
2544 * is enabled - instead we unconditionally enable all PCH interrupt
2545 * sources here, but then only unmask them as needed with SDEIMR.
2546 */
2547 I915_WRITE(SDEIER, 0xffffffff);
2548 POSTING_READ(SDEIER);
2549 }
2550
2551 static void gen5_gt_irq_preinstall(struct drm_device *dev)
2552 {
2553 struct drm_i915_private *dev_priv = dev->dev_private;
2554
2555 /* and GT */
2556 I915_WRITE(GTIMR, 0xffffffff);
2557 I915_WRITE(GTIER, 0x0);
2558 POSTING_READ(GTIER);
2559
2560 if (INTEL_INFO(dev)->gen >= 6) {
2561 /* and PM */
2562 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2563 I915_WRITE(GEN6_PMIER, 0x0);
2564 POSTING_READ(GEN6_PMIER);
2565 }
2566 }
2567
2568 /* drm_dma.h hooks
2569 */
2570 static void ironlake_irq_preinstall(struct drm_device *dev)
2571 {
2572 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2573
2574 atomic_set(&dev_priv->irq_received, 0);
2575
2576 I915_WRITE(HWSTAM, 0xeffe);
2577
2578 I915_WRITE(DEIMR, 0xffffffff);
2579 I915_WRITE(DEIER, 0x0);
2580 POSTING_READ(DEIER);
2581
2582 gen5_gt_irq_preinstall(dev);
2583
2584 ibx_irq_preinstall(dev);
2585 }
2586
2587 static void valleyview_irq_preinstall(struct drm_device *dev)
2588 {
2589 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2590 int pipe;
2591
2592 atomic_set(&dev_priv->irq_received, 0);
2593
2594 /* VLV magic */
2595 I915_WRITE(VLV_IMR, 0);
2596 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2597 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2598 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2599
2600 /* and GT */
2601 I915_WRITE(GTIIR, I915_READ(GTIIR));
2602 I915_WRITE(GTIIR, I915_READ(GTIIR));
2603
2604 gen5_gt_irq_preinstall(dev);
2605
2606 I915_WRITE(DPINVGTT, 0xff);
2607
2608 I915_WRITE(PORT_HOTPLUG_EN, 0);
2609 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2610 for_each_pipe(pipe)
2611 I915_WRITE(PIPESTAT(pipe), 0xffff);
2612 I915_WRITE(VLV_IIR, 0xffffffff);
2613 I915_WRITE(VLV_IMR, 0xffffffff);
2614 I915_WRITE(VLV_IER, 0x0);
2615 POSTING_READ(VLV_IER);
2616 }
2617
2618 static void gen8_irq_preinstall(struct drm_device *dev)
2619 {
2620 struct drm_i915_private *dev_priv = dev->dev_private;
2621 int pipe;
2622
2623 atomic_set(&dev_priv->irq_received, 0);
2624
2625 I915_WRITE(GEN8_MASTER_IRQ, 0);
2626 POSTING_READ(GEN8_MASTER_IRQ);
2627
2628 /* IIR can theoretically queue up two events. Be paranoid */
2629 #define GEN8_IRQ_INIT_NDX(type, which) do { \
2630 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
2631 POSTING_READ(GEN8_##type##_IMR(which)); \
2632 I915_WRITE(GEN8_##type##_IER(which), 0); \
2633 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2634 POSTING_READ(GEN8_##type##_IIR(which)); \
2635 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2636 } while (0)
2637
2638 #define GEN8_IRQ_INIT(type) do { \
2639 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
2640 POSTING_READ(GEN8_##type##_IMR); \
2641 I915_WRITE(GEN8_##type##_IER, 0); \
2642 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2643 POSTING_READ(GEN8_##type##_IIR); \
2644 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2645 } while (0)
2646
2647 GEN8_IRQ_INIT_NDX(GT, 0);
2648 GEN8_IRQ_INIT_NDX(GT, 1);
2649 GEN8_IRQ_INIT_NDX(GT, 2);
2650 GEN8_IRQ_INIT_NDX(GT, 3);
2651
2652 for_each_pipe(pipe) {
2653 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe);
2654 }
2655
2656 GEN8_IRQ_INIT(DE_PORT);
2657 GEN8_IRQ_INIT(DE_MISC);
2658 GEN8_IRQ_INIT(PCU);
2659 #undef GEN8_IRQ_INIT
2660 #undef GEN8_IRQ_INIT_NDX
2661
2662 POSTING_READ(GEN8_PCU_IIR);
2663 }
2664
2665 static void ibx_hpd_irq_setup(struct drm_device *dev)
2666 {
2667 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2668 struct drm_mode_config *mode_config = &dev->mode_config;
2669 struct intel_encoder *intel_encoder;
2670 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
2671
2672 if (HAS_PCH_IBX(dev)) {
2673 hotplug_irqs = SDE_HOTPLUG_MASK;
2674 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2675 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2676 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
2677 } else {
2678 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
2679 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2680 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2681 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
2682 }
2683
2684 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
2685
2686 /*
2687 * Enable digital hotplug on the PCH, and configure the DP short pulse
2688 * duration to 2ms (which is the minimum in the Display Port spec)
2689 *
2690 * This register is the same on all known PCH chips.
2691 */
2692 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2693 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2694 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2695 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2696 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2697 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2698 }
2699
2700 static void ibx_irq_postinstall(struct drm_device *dev)
2701 {
2702 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2703 u32 mask;
2704
2705 if (HAS_PCH_NOP(dev))
2706 return;
2707
2708 if (HAS_PCH_IBX(dev)) {
2709 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
2710 SDE_TRANSA_FIFO_UNDER | SDE_POISON;
2711 } else {
2712 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2713
2714 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2715 }
2716
2717 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2718 I915_WRITE(SDEIMR, ~mask);
2719 }
2720
2721 static void gen5_gt_irq_postinstall(struct drm_device *dev)
2722 {
2723 struct drm_i915_private *dev_priv = dev->dev_private;
2724 u32 pm_irqs, gt_irqs;
2725
2726 pm_irqs = gt_irqs = 0;
2727
2728 dev_priv->gt_irq_mask = ~0;
2729 if (HAS_L3_DPF(dev)) {
2730 /* L3 parity interrupt is always unmasked. */
2731 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
2732 gt_irqs |= GT_PARITY_ERROR(dev);
2733 }
2734
2735 gt_irqs |= GT_RENDER_USER_INTERRUPT;
2736 if (IS_GEN5(dev)) {
2737 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2738 ILK_BSD_USER_INTERRUPT;
2739 } else {
2740 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2741 }
2742
2743 I915_WRITE(GTIIR, I915_READ(GTIIR));
2744 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2745 I915_WRITE(GTIER, gt_irqs);
2746 POSTING_READ(GTIER);
2747
2748 if (INTEL_INFO(dev)->gen >= 6) {
2749 pm_irqs |= GEN6_PM_RPS_EVENTS;
2750
2751 if (HAS_VEBOX(dev))
2752 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
2753
2754 dev_priv->pm_irq_mask = 0xffffffff;
2755 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2756 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
2757 I915_WRITE(GEN6_PMIER, pm_irqs);
2758 POSTING_READ(GEN6_PMIER);
2759 }
2760 }
2761
2762 static int ironlake_irq_postinstall(struct drm_device *dev)
2763 {
2764 unsigned long irqflags;
2765 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2766 u32 display_mask, extra_mask;
2767
2768 if (INTEL_INFO(dev)->gen >= 7) {
2769 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2770 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
2771 DE_PLANEB_FLIP_DONE_IVB |
2772 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
2773 DE_ERR_INT_IVB);
2774 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
2775 DE_PIPEA_VBLANK_IVB);
2776
2777 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2778 } else {
2779 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2780 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2781 DE_AUX_CHANNEL_A |
2782 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
2783 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
2784 DE_POISON);
2785 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
2786 }
2787
2788 dev_priv->irq_mask = ~display_mask;
2789
2790 /* should always can generate irq */
2791 I915_WRITE(DEIIR, I915_READ(DEIIR));
2792 I915_WRITE(DEIMR, dev_priv->irq_mask);
2793 I915_WRITE(DEIER, display_mask | extra_mask);
2794 POSTING_READ(DEIER);
2795
2796 gen5_gt_irq_postinstall(dev);
2797
2798 ibx_irq_postinstall(dev);
2799
2800 if (IS_IRONLAKE_M(dev)) {
2801 /* Enable PCU event interrupts
2802 *
2803 * spinlocking not required here for correctness since interrupt
2804 * setup is guaranteed to run in single-threaded context. But we
2805 * need it to make the assert_spin_locked happy. */
2806 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2807 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2808 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2809 }
2810
2811 return 0;
2812 }
2813
2814 static int valleyview_irq_postinstall(struct drm_device *dev)
2815 {
2816 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2817 u32 enable_mask;
2818 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV |
2819 PIPE_CRC_DONE_ENABLE;
2820 unsigned long irqflags;
2821
2822 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2823 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2824 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2825 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2826 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2827
2828 /*
2829 *Leave vblank interrupts masked initially. enable/disable will
2830 * toggle them based on usage.
2831 */
2832 dev_priv->irq_mask = (~enable_mask) |
2833 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2834 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2835
2836 I915_WRITE(PORT_HOTPLUG_EN, 0);
2837 POSTING_READ(PORT_HOTPLUG_EN);
2838
2839 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2840 I915_WRITE(VLV_IER, enable_mask);
2841 I915_WRITE(VLV_IIR, 0xffffffff);
2842 I915_WRITE(PIPESTAT(0), 0xffff);
2843 I915_WRITE(PIPESTAT(1), 0xffff);
2844 POSTING_READ(VLV_IER);
2845
2846 /* Interrupt setup is already guaranteed to be single-threaded, this is
2847 * just to make the assert_spin_locked check happy. */
2848 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2849 i915_enable_pipestat(dev_priv, PIPE_A, pipestat_enable);
2850 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE);
2851 i915_enable_pipestat(dev_priv, PIPE_B, pipestat_enable);
2852 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2853
2854 I915_WRITE(VLV_IIR, 0xffffffff);
2855 I915_WRITE(VLV_IIR, 0xffffffff);
2856
2857 gen5_gt_irq_postinstall(dev);
2858
2859 /* ack & enable invalid PTE error interrupts */
2860 #if 0 /* FIXME: add support to irq handler for checking these bits */
2861 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2862 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2863 #endif
2864
2865 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2866
2867 return 0;
2868 }
2869
2870 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
2871 {
2872 int i;
2873
2874 /* These are interrupts we'll toggle with the ring mask register */
2875 uint32_t gt_interrupts[] = {
2876 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
2877 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
2878 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
2879 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
2880 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
2881 0,
2882 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
2883 };
2884
2885 for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) {
2886 u32 tmp = I915_READ(GEN8_GT_IIR(i));
2887 if (tmp)
2888 DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
2889 i, tmp);
2890 I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]);
2891 I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]);
2892 }
2893 POSTING_READ(GEN8_GT_IER(0));
2894 }
2895
2896 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
2897 {
2898 struct drm_device *dev = dev_priv->dev;
2899 uint32_t de_pipe_enables = GEN8_PIPE_FLIP_DONE |
2900 GEN8_PIPE_VBLANK |
2901 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2902 int pipe;
2903 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_enables;
2904 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_enables;
2905 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_enables;
2906
2907 for_each_pipe(pipe) {
2908 u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2909 if (tmp)
2910 DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
2911 pipe, tmp);
2912 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2913 I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables);
2914 }
2915 POSTING_READ(GEN8_DE_PIPE_ISR(0));
2916
2917 I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A);
2918 I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A);
2919 POSTING_READ(GEN8_DE_PORT_IER);
2920 }
2921
2922 static int gen8_irq_postinstall(struct drm_device *dev)
2923 {
2924 struct drm_i915_private *dev_priv = dev->dev_private;
2925
2926 gen8_gt_irq_postinstall(dev_priv);
2927 gen8_de_irq_postinstall(dev_priv);
2928
2929 ibx_irq_postinstall(dev);
2930
2931 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
2932 POSTING_READ(GEN8_MASTER_IRQ);
2933
2934 return 0;
2935 }
2936
2937 static void gen8_irq_uninstall(struct drm_device *dev)
2938 {
2939 struct drm_i915_private *dev_priv = dev->dev_private;
2940 int pipe;
2941
2942 if (!dev_priv)
2943 return;
2944
2945 atomic_set(&dev_priv->irq_received, 0);
2946
2947 I915_WRITE(GEN8_MASTER_IRQ, 0);
2948
2949 #define GEN8_IRQ_FINI_NDX(type, which) do { \
2950 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
2951 I915_WRITE(GEN8_##type##_IER(which), 0); \
2952 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2953 } while (0)
2954
2955 #define GEN8_IRQ_FINI(type) do { \
2956 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
2957 I915_WRITE(GEN8_##type##_IER, 0); \
2958 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2959 } while (0)
2960
2961 GEN8_IRQ_FINI_NDX(GT, 0);
2962 GEN8_IRQ_FINI_NDX(GT, 1);
2963 GEN8_IRQ_FINI_NDX(GT, 2);
2964 GEN8_IRQ_FINI_NDX(GT, 3);
2965
2966 for_each_pipe(pipe) {
2967 GEN8_IRQ_FINI_NDX(DE_PIPE, pipe);
2968 }
2969
2970 GEN8_IRQ_FINI(DE_PORT);
2971 GEN8_IRQ_FINI(DE_MISC);
2972 GEN8_IRQ_FINI(PCU);
2973 #undef GEN8_IRQ_FINI
2974 #undef GEN8_IRQ_FINI_NDX
2975
2976 POSTING_READ(GEN8_PCU_IIR);
2977 }
2978
2979 static void valleyview_irq_uninstall(struct drm_device *dev)
2980 {
2981 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2982 int pipe;
2983
2984 if (!dev_priv)
2985 return;
2986
2987 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2988
2989 for_each_pipe(pipe)
2990 I915_WRITE(PIPESTAT(pipe), 0xffff);
2991
2992 I915_WRITE(HWSTAM, 0xffffffff);
2993 I915_WRITE(PORT_HOTPLUG_EN, 0);
2994 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2995 for_each_pipe(pipe)
2996 I915_WRITE(PIPESTAT(pipe), 0xffff);
2997 I915_WRITE(VLV_IIR, 0xffffffff);
2998 I915_WRITE(VLV_IMR, 0xffffffff);
2999 I915_WRITE(VLV_IER, 0x0);
3000 POSTING_READ(VLV_IER);
3001 }
3002
3003 static void ironlake_irq_uninstall(struct drm_device *dev)
3004 {
3005 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3006
3007 if (!dev_priv)
3008 return;
3009
3010 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3011
3012 I915_WRITE(HWSTAM, 0xffffffff);
3013
3014 I915_WRITE(DEIMR, 0xffffffff);
3015 I915_WRITE(DEIER, 0x0);
3016 I915_WRITE(DEIIR, I915_READ(DEIIR));
3017 if (IS_GEN7(dev))
3018 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
3019
3020 I915_WRITE(GTIMR, 0xffffffff);
3021 I915_WRITE(GTIER, 0x0);
3022 I915_WRITE(GTIIR, I915_READ(GTIIR));
3023
3024 if (HAS_PCH_NOP(dev))
3025 return;
3026
3027 I915_WRITE(SDEIMR, 0xffffffff);
3028 I915_WRITE(SDEIER, 0x0);
3029 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
3030 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3031 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
3032 }
3033
3034 static void i8xx_irq_preinstall(struct drm_device * dev)
3035 {
3036 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3037 int pipe;
3038
3039 atomic_set(&dev_priv->irq_received, 0);
3040
3041 for_each_pipe(pipe)
3042 I915_WRITE(PIPESTAT(pipe), 0);
3043 I915_WRITE16(IMR, 0xffff);
3044 I915_WRITE16(IER, 0x0);
3045 POSTING_READ16(IER);
3046 }
3047
3048 static int i8xx_irq_postinstall(struct drm_device *dev)
3049 {
3050 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3051 unsigned long irqflags;
3052
3053 I915_WRITE16(EMR,
3054 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3055
3056 /* Unmask the interrupts that we always want on. */
3057 dev_priv->irq_mask =
3058 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3059 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3060 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3061 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3062 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3063 I915_WRITE16(IMR, dev_priv->irq_mask);
3064
3065 I915_WRITE16(IER,
3066 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3067 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3068 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3069 I915_USER_INTERRUPT);
3070 POSTING_READ16(IER);
3071
3072 /* Interrupt setup is already guaranteed to be single-threaded, this is
3073 * just to make the assert_spin_locked check happy. */
3074 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3075 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3076 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3077 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3078
3079 return 0;
3080 }
3081
3082 /*
3083 * Returns true when a page flip has completed.
3084 */
3085 static bool i8xx_handle_vblank(struct drm_device *dev,
3086 int pipe, u16 iir)
3087 {
3088 drm_i915_private_t *dev_priv = dev->dev_private;
3089 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
3090
3091 if (!drm_handle_vblank(dev, pipe))
3092 return false;
3093
3094 if ((iir & flip_pending) == 0)
3095 return false;
3096
3097 intel_prepare_page_flip(dev, pipe);
3098
3099 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3100 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3101 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3102 * the flip is completed (no longer pending). Since this doesn't raise
3103 * an interrupt per se, we watch for the change at vblank.
3104 */
3105 if (I915_READ16(ISR) & flip_pending)
3106 return false;
3107
3108 intel_finish_page_flip(dev, pipe);
3109
3110 return true;
3111 }
3112
3113 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3114 {
3115 struct drm_device *dev = (struct drm_device *) arg;
3116 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3117 u16 iir, new_iir;
3118 u32 pipe_stats[2];
3119 unsigned long irqflags;
3120 int pipe;
3121 u16 flip_mask =
3122 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3123 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3124
3125 atomic_inc(&dev_priv->irq_received);
3126
3127 iir = I915_READ16(IIR);
3128 if (iir == 0)
3129 return IRQ_NONE;
3130
3131 while (iir & ~flip_mask) {
3132 /* Can't rely on pipestat interrupt bit in iir as it might
3133 * have been cleared after the pipestat interrupt was received.
3134 * It doesn't set the bit in iir again, but it still produces
3135 * interrupts (for non-MSI).
3136 */
3137 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3138 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3139 i915_handle_error(dev, false);
3140
3141 for_each_pipe(pipe) {
3142 int reg = PIPESTAT(pipe);
3143 pipe_stats[pipe] = I915_READ(reg);
3144
3145 /*
3146 * Clear the PIPE*STAT regs before the IIR
3147 */
3148 if (pipe_stats[pipe] & 0x8000ffff) {
3149 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3150 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3151 pipe_name(pipe));
3152 I915_WRITE(reg, pipe_stats[pipe]);
3153 }
3154 }
3155 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3156
3157 I915_WRITE16(IIR, iir & ~flip_mask);
3158 new_iir = I915_READ16(IIR); /* Flush posted writes */
3159
3160 i915_update_dri1_breadcrumb(dev);
3161
3162 if (iir & I915_USER_INTERRUPT)
3163 notify_ring(dev, &dev_priv->ring[RCS]);
3164
3165 for_each_pipe(pipe) {
3166 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3167 i8xx_handle_vblank(dev, pipe, iir))
3168 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3169
3170 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3171 i9xx_pipe_crc_irq_handler(dev, pipe);
3172 }
3173
3174 iir = new_iir;
3175 }
3176
3177 return IRQ_HANDLED;
3178 }
3179
3180 static void i8xx_irq_uninstall(struct drm_device * dev)
3181 {
3182 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3183 int pipe;
3184
3185 for_each_pipe(pipe) {
3186 /* Clear enable bits; then clear status bits */
3187 I915_WRITE(PIPESTAT(pipe), 0);
3188 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3189 }
3190 I915_WRITE16(IMR, 0xffff);
3191 I915_WRITE16(IER, 0x0);
3192 I915_WRITE16(IIR, I915_READ16(IIR));
3193 }
3194
3195 static void i915_irq_preinstall(struct drm_device * dev)
3196 {
3197 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3198 int pipe;
3199
3200 atomic_set(&dev_priv->irq_received, 0);
3201
3202 if (I915_HAS_HOTPLUG(dev)) {
3203 I915_WRITE(PORT_HOTPLUG_EN, 0);
3204 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3205 }
3206
3207 I915_WRITE16(HWSTAM, 0xeffe);
3208 for_each_pipe(pipe)
3209 I915_WRITE(PIPESTAT(pipe), 0);
3210 I915_WRITE(IMR, 0xffffffff);
3211 I915_WRITE(IER, 0x0);
3212 POSTING_READ(IER);
3213 }
3214
3215 static int i915_irq_postinstall(struct drm_device *dev)
3216 {
3217 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3218 u32 enable_mask;
3219 unsigned long irqflags;
3220
3221 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3222
3223 /* Unmask the interrupts that we always want on. */
3224 dev_priv->irq_mask =
3225 ~(I915_ASLE_INTERRUPT |
3226 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3227 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3228 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3229 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3230 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3231
3232 enable_mask =
3233 I915_ASLE_INTERRUPT |
3234 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3235 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3236 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3237 I915_USER_INTERRUPT;
3238
3239 if (I915_HAS_HOTPLUG(dev)) {
3240 I915_WRITE(PORT_HOTPLUG_EN, 0);
3241 POSTING_READ(PORT_HOTPLUG_EN);
3242
3243 /* Enable in IER... */
3244 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3245 /* and unmask in IMR */
3246 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3247 }
3248
3249 I915_WRITE(IMR, dev_priv->irq_mask);
3250 I915_WRITE(IER, enable_mask);
3251 POSTING_READ(IER);
3252
3253 i915_enable_asle_pipestat(dev);
3254
3255 /* Interrupt setup is already guaranteed to be single-threaded, this is
3256 * just to make the assert_spin_locked check happy. */
3257 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3258 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3259 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3260 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3261
3262 return 0;
3263 }
3264
3265 /*
3266 * Returns true when a page flip has completed.
3267 */
3268 static bool i915_handle_vblank(struct drm_device *dev,
3269 int plane, int pipe, u32 iir)
3270 {
3271 drm_i915_private_t *dev_priv = dev->dev_private;
3272 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3273
3274 if (!drm_handle_vblank(dev, pipe))
3275 return false;
3276
3277 if ((iir & flip_pending) == 0)
3278 return false;
3279
3280 intel_prepare_page_flip(dev, plane);
3281
3282 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3283 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3284 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3285 * the flip is completed (no longer pending). Since this doesn't raise
3286 * an interrupt per se, we watch for the change at vblank.
3287 */
3288 if (I915_READ(ISR) & flip_pending)
3289 return false;
3290
3291 intel_finish_page_flip(dev, pipe);
3292
3293 return true;
3294 }
3295
3296 static irqreturn_t i915_irq_handler(int irq, void *arg)
3297 {
3298 struct drm_device *dev = (struct drm_device *) arg;
3299 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3300 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3301 unsigned long irqflags;
3302 u32 flip_mask =
3303 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3304 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3305 int pipe, ret = IRQ_NONE;
3306
3307 atomic_inc(&dev_priv->irq_received);
3308
3309 iir = I915_READ(IIR);
3310 do {
3311 bool irq_received = (iir & ~flip_mask) != 0;
3312 bool blc_event = false;
3313
3314 /* Can't rely on pipestat interrupt bit in iir as it might
3315 * have been cleared after the pipestat interrupt was received.
3316 * It doesn't set the bit in iir again, but it still produces
3317 * interrupts (for non-MSI).
3318 */
3319 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3320 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3321 i915_handle_error(dev, false);
3322
3323 for_each_pipe(pipe) {
3324 int reg = PIPESTAT(pipe);
3325 pipe_stats[pipe] = I915_READ(reg);
3326
3327 /* Clear the PIPE*STAT regs before the IIR */
3328 if (pipe_stats[pipe] & 0x8000ffff) {
3329 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3330 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3331 pipe_name(pipe));
3332 I915_WRITE(reg, pipe_stats[pipe]);
3333 irq_received = true;
3334 }
3335 }
3336 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3337
3338 if (!irq_received)
3339 break;
3340
3341 /* Consume port. Then clear IIR or we'll miss events */
3342 if ((I915_HAS_HOTPLUG(dev)) &&
3343 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
3344 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3345 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
3346
3347 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3348 hotplug_status);
3349
3350 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
3351
3352 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3353 POSTING_READ(PORT_HOTPLUG_STAT);
3354 }
3355
3356 I915_WRITE(IIR, iir & ~flip_mask);
3357 new_iir = I915_READ(IIR); /* Flush posted writes */
3358
3359 if (iir & I915_USER_INTERRUPT)
3360 notify_ring(dev, &dev_priv->ring[RCS]);
3361
3362 for_each_pipe(pipe) {
3363 int plane = pipe;
3364 if (IS_MOBILE(dev))
3365 plane = !plane;
3366
3367 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3368 i915_handle_vblank(dev, plane, pipe, iir))
3369 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3370
3371 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3372 blc_event = true;
3373
3374 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3375 i9xx_pipe_crc_irq_handler(dev, pipe);
3376 }
3377
3378 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3379 intel_opregion_asle_intr(dev);
3380
3381 /* With MSI, interrupts are only generated when iir
3382 * transitions from zero to nonzero. If another bit got
3383 * set while we were handling the existing iir bits, then
3384 * we would never get another interrupt.
3385 *
3386 * This is fine on non-MSI as well, as if we hit this path
3387 * we avoid exiting the interrupt handler only to generate
3388 * another one.
3389 *
3390 * Note that for MSI this could cause a stray interrupt report
3391 * if an interrupt landed in the time between writing IIR and
3392 * the posting read. This should be rare enough to never
3393 * trigger the 99% of 100,000 interrupts test for disabling
3394 * stray interrupts.
3395 */
3396 ret = IRQ_HANDLED;
3397 iir = new_iir;
3398 } while (iir & ~flip_mask);
3399
3400 i915_update_dri1_breadcrumb(dev);
3401
3402 return ret;
3403 }
3404
3405 static void i915_irq_uninstall(struct drm_device * dev)
3406 {
3407 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3408 int pipe;
3409
3410 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3411
3412 if (I915_HAS_HOTPLUG(dev)) {
3413 I915_WRITE(PORT_HOTPLUG_EN, 0);
3414 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3415 }
3416
3417 I915_WRITE16(HWSTAM, 0xffff);
3418 for_each_pipe(pipe) {
3419 /* Clear enable bits; then clear status bits */
3420 I915_WRITE(PIPESTAT(pipe), 0);
3421 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3422 }
3423 I915_WRITE(IMR, 0xffffffff);
3424 I915_WRITE(IER, 0x0);
3425
3426 I915_WRITE(IIR, I915_READ(IIR));
3427 }
3428
3429 static void i965_irq_preinstall(struct drm_device * dev)
3430 {
3431 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3432 int pipe;
3433
3434 atomic_set(&dev_priv->irq_received, 0);
3435
3436 I915_WRITE(PORT_HOTPLUG_EN, 0);
3437 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3438
3439 I915_WRITE(HWSTAM, 0xeffe);
3440 for_each_pipe(pipe)
3441 I915_WRITE(PIPESTAT(pipe), 0);
3442 I915_WRITE(IMR, 0xffffffff);
3443 I915_WRITE(IER, 0x0);
3444 POSTING_READ(IER);
3445 }
3446
3447 static int i965_irq_postinstall(struct drm_device *dev)
3448 {
3449 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3450 u32 enable_mask;
3451 u32 error_mask;
3452 unsigned long irqflags;
3453
3454 /* Unmask the interrupts that we always want on. */
3455 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3456 I915_DISPLAY_PORT_INTERRUPT |
3457 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3458 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3459 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3460 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3461 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3462
3463 enable_mask = ~dev_priv->irq_mask;
3464 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3465 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3466 enable_mask |= I915_USER_INTERRUPT;
3467
3468 if (IS_G4X(dev))
3469 enable_mask |= I915_BSD_USER_INTERRUPT;
3470
3471 /* Interrupt setup is already guaranteed to be single-threaded, this is
3472 * just to make the assert_spin_locked check happy. */
3473 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3474 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE);
3475 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3476 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3477 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3478
3479 /*
3480 * Enable some error detection, note the instruction error mask
3481 * bit is reserved, so we leave it masked.
3482 */
3483 if (IS_G4X(dev)) {
3484 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3485 GM45_ERROR_MEM_PRIV |
3486 GM45_ERROR_CP_PRIV |
3487 I915_ERROR_MEMORY_REFRESH);
3488 } else {
3489 error_mask = ~(I915_ERROR_PAGE_TABLE |
3490 I915_ERROR_MEMORY_REFRESH);
3491 }
3492 I915_WRITE(EMR, error_mask);
3493
3494 I915_WRITE(IMR, dev_priv->irq_mask);
3495 I915_WRITE(IER, enable_mask);
3496 POSTING_READ(IER);
3497
3498 I915_WRITE(PORT_HOTPLUG_EN, 0);
3499 POSTING_READ(PORT_HOTPLUG_EN);
3500
3501 i915_enable_asle_pipestat(dev);
3502
3503 return 0;
3504 }
3505
3506 static void i915_hpd_irq_setup(struct drm_device *dev)
3507 {
3508 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3509 struct drm_mode_config *mode_config = &dev->mode_config;
3510 struct intel_encoder *intel_encoder;
3511 u32 hotplug_en;
3512
3513 assert_spin_locked(&dev_priv->irq_lock);
3514
3515 if (I915_HAS_HOTPLUG(dev)) {
3516 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3517 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3518 /* Note HDMI and DP share hotplug bits */
3519 /* enable bits are the same for all generations */
3520 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3521 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3522 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
3523 /* Programming the CRT detection parameters tends
3524 to generate a spurious hotplug event about three
3525 seconds later. So just do it once.
3526 */
3527 if (IS_G4X(dev))
3528 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3529 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
3530 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3531
3532 /* Ignore TV since it's buggy */
3533 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3534 }
3535 }
3536
3537 static irqreturn_t i965_irq_handler(int irq, void *arg)
3538 {
3539 struct drm_device *dev = (struct drm_device *) arg;
3540 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3541 u32 iir, new_iir;
3542 u32 pipe_stats[I915_MAX_PIPES];
3543 unsigned long irqflags;
3544 int irq_received;
3545 int ret = IRQ_NONE, pipe;
3546 u32 flip_mask =
3547 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3548 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3549
3550 atomic_inc(&dev_priv->irq_received);
3551
3552 iir = I915_READ(IIR);
3553
3554 for (;;) {
3555 bool blc_event = false;
3556
3557 irq_received = (iir & ~flip_mask) != 0;
3558
3559 /* Can't rely on pipestat interrupt bit in iir as it might
3560 * have been cleared after the pipestat interrupt was received.
3561 * It doesn't set the bit in iir again, but it still produces
3562 * interrupts (for non-MSI).
3563 */
3564 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3565 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3566 i915_handle_error(dev, false);
3567
3568 for_each_pipe(pipe) {
3569 int reg = PIPESTAT(pipe);
3570 pipe_stats[pipe] = I915_READ(reg);
3571
3572 /*
3573 * Clear the PIPE*STAT regs before the IIR
3574 */
3575 if (pipe_stats[pipe] & 0x8000ffff) {
3576 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3577 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3578 pipe_name(pipe));
3579 I915_WRITE(reg, pipe_stats[pipe]);
3580 irq_received = 1;
3581 }
3582 }
3583 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3584
3585 if (!irq_received)
3586 break;
3587
3588 ret = IRQ_HANDLED;
3589
3590 /* Consume port. Then clear IIR or we'll miss events */
3591 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
3592 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3593 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3594 HOTPLUG_INT_STATUS_G4X :
3595 HOTPLUG_INT_STATUS_I915);
3596
3597 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3598 hotplug_status);
3599
3600 intel_hpd_irq_handler(dev, hotplug_trigger,
3601 IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915);
3602
3603 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3604 I915_READ(PORT_HOTPLUG_STAT);
3605 }
3606
3607 I915_WRITE(IIR, iir & ~flip_mask);
3608 new_iir = I915_READ(IIR); /* Flush posted writes */
3609
3610 if (iir & I915_USER_INTERRUPT)
3611 notify_ring(dev, &dev_priv->ring[RCS]);
3612 if (iir & I915_BSD_USER_INTERRUPT)
3613 notify_ring(dev, &dev_priv->ring[VCS]);
3614
3615 for_each_pipe(pipe) {
3616 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3617 i915_handle_vblank(dev, pipe, pipe, iir))
3618 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3619
3620 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3621 blc_event = true;
3622
3623 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3624 i9xx_pipe_crc_irq_handler(dev, pipe);
3625 }
3626
3627
3628 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3629 intel_opregion_asle_intr(dev);
3630
3631 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3632 gmbus_irq_handler(dev);
3633
3634 /* With MSI, interrupts are only generated when iir
3635 * transitions from zero to nonzero. If another bit got
3636 * set while we were handling the existing iir bits, then
3637 * we would never get another interrupt.
3638 *
3639 * This is fine on non-MSI as well, as if we hit this path
3640 * we avoid exiting the interrupt handler only to generate
3641 * another one.
3642 *
3643 * Note that for MSI this could cause a stray interrupt report
3644 * if an interrupt landed in the time between writing IIR and
3645 * the posting read. This should be rare enough to never
3646 * trigger the 99% of 100,000 interrupts test for disabling
3647 * stray interrupts.
3648 */
3649 iir = new_iir;
3650 }
3651
3652 i915_update_dri1_breadcrumb(dev);
3653
3654 return ret;
3655 }
3656
3657 static void i965_irq_uninstall(struct drm_device * dev)
3658 {
3659 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3660 int pipe;
3661
3662 if (!dev_priv)
3663 return;
3664
3665 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3666
3667 I915_WRITE(PORT_HOTPLUG_EN, 0);
3668 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3669
3670 I915_WRITE(HWSTAM, 0xffffffff);
3671 for_each_pipe(pipe)
3672 I915_WRITE(PIPESTAT(pipe), 0);
3673 I915_WRITE(IMR, 0xffffffff);
3674 I915_WRITE(IER, 0x0);
3675
3676 for_each_pipe(pipe)
3677 I915_WRITE(PIPESTAT(pipe),
3678 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3679 I915_WRITE(IIR, I915_READ(IIR));
3680 }
3681
3682 static void i915_reenable_hotplug_timer_func(unsigned long data)
3683 {
3684 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3685 struct drm_device *dev = dev_priv->dev;
3686 struct drm_mode_config *mode_config = &dev->mode_config;
3687 unsigned long irqflags;
3688 int i;
3689
3690 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3691 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3692 struct drm_connector *connector;
3693
3694 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3695 continue;
3696
3697 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3698
3699 list_for_each_entry(connector, &mode_config->connector_list, head) {
3700 struct intel_connector *intel_connector = to_intel_connector(connector);
3701
3702 if (intel_connector->encoder->hpd_pin == i) {
3703 if (connector->polled != intel_connector->polled)
3704 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3705 drm_get_connector_name(connector));
3706 connector->polled = intel_connector->polled;
3707 if (!connector->polled)
3708 connector->polled = DRM_CONNECTOR_POLL_HPD;
3709 }
3710 }
3711 }
3712 if (dev_priv->display.hpd_irq_setup)
3713 dev_priv->display.hpd_irq_setup(dev);
3714 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3715 }
3716
3717 void intel_irq_init(struct drm_device *dev)
3718 {
3719 struct drm_i915_private *dev_priv = dev->dev_private;
3720
3721 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
3722 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
3723 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
3724 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
3725
3726 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3727 i915_hangcheck_elapsed,
3728 (unsigned long) dev);
3729 setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3730 (unsigned long) dev_priv);
3731
3732 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
3733
3734 if (IS_GEN2(dev)) {
3735 dev->max_vblank_count = 0;
3736 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
3737 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3738 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3739 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3740 } else {
3741 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3742 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
3743 }
3744
3745 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
3746 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3747 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3748 }
3749
3750 if (IS_VALLEYVIEW(dev)) {
3751 dev->driver->irq_handler = valleyview_irq_handler;
3752 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3753 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3754 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3755 dev->driver->enable_vblank = valleyview_enable_vblank;
3756 dev->driver->disable_vblank = valleyview_disable_vblank;
3757 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3758 } else if (IS_GEN8(dev)) {
3759 dev->driver->irq_handler = gen8_irq_handler;
3760 dev->driver->irq_preinstall = gen8_irq_preinstall;
3761 dev->driver->irq_postinstall = gen8_irq_postinstall;
3762 dev->driver->irq_uninstall = gen8_irq_uninstall;
3763 dev->driver->enable_vblank = gen8_enable_vblank;
3764 dev->driver->disable_vblank = gen8_disable_vblank;
3765 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3766 } else if (HAS_PCH_SPLIT(dev)) {
3767 dev->driver->irq_handler = ironlake_irq_handler;
3768 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3769 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3770 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3771 dev->driver->enable_vblank = ironlake_enable_vblank;
3772 dev->driver->disable_vblank = ironlake_disable_vblank;
3773 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3774 } else {
3775 if (INTEL_INFO(dev)->gen == 2) {
3776 dev->driver->irq_preinstall = i8xx_irq_preinstall;
3777 dev->driver->irq_postinstall = i8xx_irq_postinstall;
3778 dev->driver->irq_handler = i8xx_irq_handler;
3779 dev->driver->irq_uninstall = i8xx_irq_uninstall;
3780 } else if (INTEL_INFO(dev)->gen == 3) {
3781 dev->driver->irq_preinstall = i915_irq_preinstall;
3782 dev->driver->irq_postinstall = i915_irq_postinstall;
3783 dev->driver->irq_uninstall = i915_irq_uninstall;
3784 dev->driver->irq_handler = i915_irq_handler;
3785 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3786 } else {
3787 dev->driver->irq_preinstall = i965_irq_preinstall;
3788 dev->driver->irq_postinstall = i965_irq_postinstall;
3789 dev->driver->irq_uninstall = i965_irq_uninstall;
3790 dev->driver->irq_handler = i965_irq_handler;
3791 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3792 }
3793 dev->driver->enable_vblank = i915_enable_vblank;
3794 dev->driver->disable_vblank = i915_disable_vblank;
3795 }
3796 }
3797
3798 void intel_hpd_init(struct drm_device *dev)
3799 {
3800 struct drm_i915_private *dev_priv = dev->dev_private;
3801 struct drm_mode_config *mode_config = &dev->mode_config;
3802 struct drm_connector *connector;
3803 unsigned long irqflags;
3804 int i;
3805
3806 for (i = 1; i < HPD_NUM_PINS; i++) {
3807 dev_priv->hpd_stats[i].hpd_cnt = 0;
3808 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3809 }
3810 list_for_each_entry(connector, &mode_config->connector_list, head) {
3811 struct intel_connector *intel_connector = to_intel_connector(connector);
3812 connector->polled = intel_connector->polled;
3813 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3814 connector->polled = DRM_CONNECTOR_POLL_HPD;
3815 }
3816
3817 /* Interrupt setup is already guaranteed to be single-threaded, this is
3818 * just to make the assert_spin_locked checks happy. */
3819 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3820 if (dev_priv->display.hpd_irq_setup)
3821 dev_priv->display.hpd_irq_setup(dev);
3822 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3823 }
3824
3825 /* Disable interrupts so we can allow Package C8+. */
3826 void hsw_pc8_disable_interrupts(struct drm_device *dev)
3827 {
3828 struct drm_i915_private *dev_priv = dev->dev_private;
3829 unsigned long irqflags;
3830
3831 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3832
3833 dev_priv->pc8.regsave.deimr = I915_READ(DEIMR);
3834 dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR);
3835 dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR);
3836 dev_priv->pc8.regsave.gtier = I915_READ(GTIER);
3837 dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
3838
3839 ironlake_disable_display_irq(dev_priv, ~DE_PCH_EVENT_IVB);
3840 ibx_disable_display_interrupt(dev_priv, ~SDE_HOTPLUG_MASK_CPT);
3841 ilk_disable_gt_irq(dev_priv, 0xffffffff);
3842 snb_disable_pm_irq(dev_priv, 0xffffffff);
3843
3844 dev_priv->pc8.irqs_disabled = true;
3845
3846 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3847 }
3848
3849 /* Restore interrupts so we can recover from Package C8+. */
3850 void hsw_pc8_restore_interrupts(struct drm_device *dev)
3851 {
3852 struct drm_i915_private *dev_priv = dev->dev_private;
3853 unsigned long irqflags;
3854 uint32_t val, expected;
3855
3856 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3857
3858 val = I915_READ(DEIMR);
3859 expected = ~DE_PCH_EVENT_IVB;
3860 WARN(val != expected, "DEIMR is 0x%08x, not 0x%08x\n", val, expected);
3861
3862 val = I915_READ(SDEIMR) & ~SDE_HOTPLUG_MASK_CPT;
3863 expected = ~SDE_HOTPLUG_MASK_CPT;
3864 WARN(val != expected, "SDEIMR non-HPD bits are 0x%08x, not 0x%08x\n",
3865 val, expected);
3866
3867 val = I915_READ(GTIMR);
3868 expected = 0xffffffff;
3869 WARN(val != expected, "GTIMR is 0x%08x, not 0x%08x\n", val, expected);
3870
3871 val = I915_READ(GEN6_PMIMR);
3872 expected = 0xffffffff;
3873 WARN(val != expected, "GEN6_PMIMR is 0x%08x, not 0x%08x\n", val,
3874 expected);
3875
3876 dev_priv->pc8.irqs_disabled = false;
3877
3878 ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr);
3879 ibx_enable_display_interrupt(dev_priv,
3880 ~dev_priv->pc8.regsave.sdeimr &
3881 ~SDE_HOTPLUG_MASK_CPT);
3882 ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr);
3883 snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr);
3884 I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier);
3885
3886 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3887 }
Linux kernel - Deliverables
This page took 0.10897 seconds and 4 git commands to generate.