1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
41 * DOC: interrupt handling
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
48 static const u32 hpd_ilk
[HPD_NUM_PINS
] = {
49 [HPD_PORT_A
] = DE_DP_A_HOTPLUG
,
52 static const u32 hpd_ivb
[HPD_NUM_PINS
] = {
53 [HPD_PORT_A
] = DE_DP_A_HOTPLUG_IVB
,
56 static const u32 hpd_bdw
[HPD_NUM_PINS
] = {
57 [HPD_PORT_A
] = GEN8_PORT_DP_A_HOTPLUG
,
60 static const u32 hpd_ibx
[HPD_NUM_PINS
] = {
61 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
62 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
63 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
64 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
65 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
68 static const u32 hpd_cpt
[HPD_NUM_PINS
] = {
69 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
70 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
71 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
72 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
73 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
76 static const u32 hpd_spt
[HPD_NUM_PINS
] = {
77 [HPD_PORT_A
] = SDE_PORTA_HOTPLUG_SPT
,
78 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
79 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
80 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
,
81 [HPD_PORT_E
] = SDE_PORTE_HOTPLUG_SPT
84 static const u32 hpd_mask_i915
[HPD_NUM_PINS
] = {
85 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
86 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
87 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
88 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
89 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
90 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
93 static const u32 hpd_status_g4x
[HPD_NUM_PINS
] = {
94 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
95 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
96 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
97 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
98 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
99 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
102 static const u32 hpd_status_i915
[HPD_NUM_PINS
] = {
103 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
104 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
105 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
106 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
107 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
108 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
112 static const u32 hpd_bxt
[HPD_NUM_PINS
] = {
113 [HPD_PORT_A
] = BXT_DE_PORT_HP_DDIA
,
114 [HPD_PORT_B
] = BXT_DE_PORT_HP_DDIB
,
115 [HPD_PORT_C
] = BXT_DE_PORT_HP_DDIC
118 /* IIR can theoretically queue up two events. Be paranoid. */
119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
120 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
121 POSTING_READ(GEN8_##type##_IMR(which)); \
122 I915_WRITE(GEN8_##type##_IER(which), 0); \
123 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
124 POSTING_READ(GEN8_##type##_IIR(which)); \
125 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
126 POSTING_READ(GEN8_##type##_IIR(which)); \
129 #define GEN5_IRQ_RESET(type) do { \
130 I915_WRITE(type##IMR, 0xffffffff); \
131 POSTING_READ(type##IMR); \
132 I915_WRITE(type##IER, 0); \
133 I915_WRITE(type##IIR, 0xffffffff); \
134 POSTING_READ(type##IIR); \
135 I915_WRITE(type##IIR, 0xffffffff); \
136 POSTING_READ(type##IIR); \
140 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
142 static void gen5_assert_iir_is_zero(struct drm_i915_private
*dev_priv
,
145 u32 val
= I915_READ(reg
);
150 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
151 i915_mmio_reg_offset(reg
), val
);
152 I915_WRITE(reg
, 0xffffffff);
154 I915_WRITE(reg
, 0xffffffff);
158 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
159 gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
160 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
161 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
162 POSTING_READ(GEN8_##type##_IMR(which)); \
165 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
166 gen5_assert_iir_is_zero(dev_priv, type##IIR); \
167 I915_WRITE(type##IER, (ier_val)); \
168 I915_WRITE(type##IMR, (imr_val)); \
169 POSTING_READ(type##IMR); \
172 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
);
174 /* For display hotplug interrupt */
176 i915_hotplug_interrupt_update_locked(struct drm_i915_private
*dev_priv
,
182 assert_spin_locked(&dev_priv
->irq_lock
);
183 WARN_ON(bits
& ~mask
);
185 val
= I915_READ(PORT_HOTPLUG_EN
);
188 I915_WRITE(PORT_HOTPLUG_EN
, val
);
192 * i915_hotplug_interrupt_update - update hotplug interrupt enable
193 * @dev_priv: driver private
194 * @mask: bits to update
195 * @bits: bits to enable
196 * NOTE: the HPD enable bits are modified both inside and outside
197 * of an interrupt context. To avoid that read-modify-write cycles
198 * interfer, these bits are protected by a spinlock. Since this
199 * function is usually not called from a context where the lock is
200 * held already, this function acquires the lock itself. A non-locking
201 * version is also available.
203 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
207 spin_lock_irq(&dev_priv
->irq_lock
);
208 i915_hotplug_interrupt_update_locked(dev_priv
, mask
, bits
);
209 spin_unlock_irq(&dev_priv
->irq_lock
);
213 * ilk_update_display_irq - update DEIMR
214 * @dev_priv: driver private
215 * @interrupt_mask: mask of interrupt bits to update
216 * @enabled_irq_mask: mask of interrupt bits to enable
218 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
219 uint32_t interrupt_mask
,
220 uint32_t enabled_irq_mask
)
224 assert_spin_locked(&dev_priv
->irq_lock
);
226 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
228 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
231 new_val
= dev_priv
->irq_mask
;
232 new_val
&= ~interrupt_mask
;
233 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
235 if (new_val
!= dev_priv
->irq_mask
) {
236 dev_priv
->irq_mask
= new_val
;
237 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
243 * ilk_update_gt_irq - update GTIMR
244 * @dev_priv: driver private
245 * @interrupt_mask: mask of interrupt bits to update
246 * @enabled_irq_mask: mask of interrupt bits to enable
248 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
249 uint32_t interrupt_mask
,
250 uint32_t enabled_irq_mask
)
252 assert_spin_locked(&dev_priv
->irq_lock
);
254 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
256 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
259 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
260 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
261 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
265 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
267 ilk_update_gt_irq(dev_priv
, mask
, mask
);
270 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
272 ilk_update_gt_irq(dev_priv
, mask
, 0);
275 static i915_reg_t
gen6_pm_iir(struct drm_i915_private
*dev_priv
)
277 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR
;
280 static i915_reg_t
gen6_pm_imr(struct drm_i915_private
*dev_priv
)
282 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR
;
285 static i915_reg_t
gen6_pm_ier(struct drm_i915_private
*dev_priv
)
287 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IER(2) : GEN6_PMIER
;
291 * snb_update_pm_irq - update GEN6_PMIMR
292 * @dev_priv: driver private
293 * @interrupt_mask: mask of interrupt bits to update
294 * @enabled_irq_mask: mask of interrupt bits to enable
296 static void snb_update_pm_irq(struct drm_i915_private
*dev_priv
,
297 uint32_t interrupt_mask
,
298 uint32_t enabled_irq_mask
)
302 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
304 assert_spin_locked(&dev_priv
->irq_lock
);
306 new_val
= dev_priv
->pm_irq_mask
;
307 new_val
&= ~interrupt_mask
;
308 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
310 if (new_val
!= dev_priv
->pm_irq_mask
) {
311 dev_priv
->pm_irq_mask
= new_val
;
312 I915_WRITE(gen6_pm_imr(dev_priv
), dev_priv
->pm_irq_mask
);
313 POSTING_READ(gen6_pm_imr(dev_priv
));
317 void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
319 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
322 snb_update_pm_irq(dev_priv
, mask
, mask
);
325 static void __gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
,
328 snb_update_pm_irq(dev_priv
, mask
, 0);
331 void gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
333 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
336 __gen6_disable_pm_irq(dev_priv
, mask
);
339 void gen6_reset_rps_interrupts(struct drm_device
*dev
)
341 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
342 i915_reg_t reg
= gen6_pm_iir(dev_priv
);
344 spin_lock_irq(&dev_priv
->irq_lock
);
345 I915_WRITE(reg
, dev_priv
->pm_rps_events
);
346 I915_WRITE(reg
, dev_priv
->pm_rps_events
);
348 dev_priv
->rps
.pm_iir
= 0;
349 spin_unlock_irq(&dev_priv
->irq_lock
);
352 void gen6_enable_rps_interrupts(struct drm_i915_private
*dev_priv
)
354 spin_lock_irq(&dev_priv
->irq_lock
);
356 WARN_ON(dev_priv
->rps
.pm_iir
);
357 WARN_ON(I915_READ(gen6_pm_iir(dev_priv
)) & dev_priv
->pm_rps_events
);
358 dev_priv
->rps
.interrupts_enabled
= true;
359 I915_WRITE(gen6_pm_ier(dev_priv
), I915_READ(gen6_pm_ier(dev_priv
)) |
360 dev_priv
->pm_rps_events
);
361 gen6_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
363 spin_unlock_irq(&dev_priv
->irq_lock
);
366 u32
gen6_sanitize_rps_pm_mask(struct drm_i915_private
*dev_priv
, u32 mask
)
369 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
370 * if GEN6_PM_UP_EI_EXPIRED is masked.
372 * TODO: verify if this can be reproduced on VLV,CHV.
374 if (INTEL_INFO(dev_priv
)->gen
<= 7 && !IS_HASWELL(dev_priv
))
375 mask
&= ~GEN6_PM_RP_UP_EI_EXPIRED
;
377 if (INTEL_INFO(dev_priv
)->gen
>= 8)
378 mask
&= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP
;
383 void gen6_disable_rps_interrupts(struct drm_i915_private
*dev_priv
)
385 spin_lock_irq(&dev_priv
->irq_lock
);
386 dev_priv
->rps
.interrupts_enabled
= false;
387 spin_unlock_irq(&dev_priv
->irq_lock
);
389 cancel_work_sync(&dev_priv
->rps
.work
);
391 spin_lock_irq(&dev_priv
->irq_lock
);
393 I915_WRITE(GEN6_PMINTRMSK
, gen6_sanitize_rps_pm_mask(dev_priv
, ~0));
395 __gen6_disable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
396 I915_WRITE(gen6_pm_ier(dev_priv
), I915_READ(gen6_pm_ier(dev_priv
)) &
397 ~dev_priv
->pm_rps_events
);
399 spin_unlock_irq(&dev_priv
->irq_lock
);
401 synchronize_irq(dev_priv
->dev
->irq
);
405 * bdw_update_port_irq - update DE port interrupt
406 * @dev_priv: driver private
407 * @interrupt_mask: mask of interrupt bits to update
408 * @enabled_irq_mask: mask of interrupt bits to enable
410 static void bdw_update_port_irq(struct drm_i915_private
*dev_priv
,
411 uint32_t interrupt_mask
,
412 uint32_t enabled_irq_mask
)
417 assert_spin_locked(&dev_priv
->irq_lock
);
419 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
421 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
424 old_val
= I915_READ(GEN8_DE_PORT_IMR
);
427 new_val
&= ~interrupt_mask
;
428 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
430 if (new_val
!= old_val
) {
431 I915_WRITE(GEN8_DE_PORT_IMR
, new_val
);
432 POSTING_READ(GEN8_DE_PORT_IMR
);
437 * bdw_update_pipe_irq - update DE pipe interrupt
438 * @dev_priv: driver private
439 * @pipe: pipe whose interrupt to update
440 * @interrupt_mask: mask of interrupt bits to update
441 * @enabled_irq_mask: mask of interrupt bits to enable
443 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
445 uint32_t interrupt_mask
,
446 uint32_t enabled_irq_mask
)
450 assert_spin_locked(&dev_priv
->irq_lock
);
452 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
454 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
457 new_val
= dev_priv
->de_irq_mask
[pipe
];
458 new_val
&= ~interrupt_mask
;
459 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
461 if (new_val
!= dev_priv
->de_irq_mask
[pipe
]) {
462 dev_priv
->de_irq_mask
[pipe
] = new_val
;
463 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
464 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
469 * ibx_display_interrupt_update - update SDEIMR
470 * @dev_priv: driver private
471 * @interrupt_mask: mask of interrupt bits to update
472 * @enabled_irq_mask: mask of interrupt bits to enable
474 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
475 uint32_t interrupt_mask
,
476 uint32_t enabled_irq_mask
)
478 uint32_t sdeimr
= I915_READ(SDEIMR
);
479 sdeimr
&= ~interrupt_mask
;
480 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
482 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
484 assert_spin_locked(&dev_priv
->irq_lock
);
486 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
489 I915_WRITE(SDEIMR
, sdeimr
);
490 POSTING_READ(SDEIMR
);
494 __i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
495 u32 enable_mask
, u32 status_mask
)
497 i915_reg_t reg
= PIPESTAT(pipe
);
498 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
500 assert_spin_locked(&dev_priv
->irq_lock
);
501 WARN_ON(!intel_irqs_enabled(dev_priv
));
503 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
504 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
505 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
506 pipe_name(pipe
), enable_mask
, status_mask
))
509 if ((pipestat
& enable_mask
) == enable_mask
)
512 dev_priv
->pipestat_irq_mask
[pipe
] |= status_mask
;
514 /* Enable the interrupt, clear any pending status */
515 pipestat
|= enable_mask
| status_mask
;
516 I915_WRITE(reg
, pipestat
);
521 __i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
522 u32 enable_mask
, u32 status_mask
)
524 i915_reg_t reg
= PIPESTAT(pipe
);
525 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
527 assert_spin_locked(&dev_priv
->irq_lock
);
528 WARN_ON(!intel_irqs_enabled(dev_priv
));
530 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
531 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
532 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
533 pipe_name(pipe
), enable_mask
, status_mask
))
536 if ((pipestat
& enable_mask
) == 0)
539 dev_priv
->pipestat_irq_mask
[pipe
] &= ~status_mask
;
541 pipestat
&= ~enable_mask
;
542 I915_WRITE(reg
, pipestat
);
546 static u32
vlv_get_pipestat_enable_mask(struct drm_device
*dev
, u32 status_mask
)
548 u32 enable_mask
= status_mask
<< 16;
551 * On pipe A we don't support the PSR interrupt yet,
552 * on pipe B and C the same bit MBZ.
554 if (WARN_ON_ONCE(status_mask
& PIPE_A_PSR_STATUS_VLV
))
557 * On pipe B and C we don't support the PSR interrupt yet, on pipe
558 * A the same bit is for perf counters which we don't use either.
560 if (WARN_ON_ONCE(status_mask
& PIPE_B_PSR_STATUS_VLV
))
563 enable_mask
&= ~(PIPE_FIFO_UNDERRUN_STATUS
|
564 SPRITE0_FLIP_DONE_INT_EN_VLV
|
565 SPRITE1_FLIP_DONE_INT_EN_VLV
);
566 if (status_mask
& SPRITE0_FLIP_DONE_INT_STATUS_VLV
)
567 enable_mask
|= SPRITE0_FLIP_DONE_INT_EN_VLV
;
568 if (status_mask
& SPRITE1_FLIP_DONE_INT_STATUS_VLV
)
569 enable_mask
|= SPRITE1_FLIP_DONE_INT_EN_VLV
;
575 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
580 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
581 enable_mask
= vlv_get_pipestat_enable_mask(dev_priv
->dev
,
584 enable_mask
= status_mask
<< 16;
585 __i915_enable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
589 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
594 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
595 enable_mask
= vlv_get_pipestat_enable_mask(dev_priv
->dev
,
598 enable_mask
= status_mask
<< 16;
599 __i915_disable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
603 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
606 static void i915_enable_asle_pipestat(struct drm_i915_private
*dev_priv
)
608 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev_priv
))
611 spin_lock_irq(&dev_priv
->irq_lock
);
613 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_LEGACY_BLC_EVENT_STATUS
);
614 if (INTEL_GEN(dev_priv
) >= 4)
615 i915_enable_pipestat(dev_priv
, PIPE_A
,
616 PIPE_LEGACY_BLC_EVENT_STATUS
);
618 spin_unlock_irq(&dev_priv
->irq_lock
);
622 * This timing diagram depicts the video signal in and
623 * around the vertical blanking period.
625 * Assumptions about the fictitious mode used in this example:
627 * vsync_start = vblank_start + 1
628 * vsync_end = vblank_start + 2
629 * vtotal = vblank_start + 3
632 * latch double buffered registers
633 * increment frame counter (ctg+)
634 * generate start of vblank interrupt (gen4+)
637 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
638 * | may be shifted forward 1-3 extra lines via PIPECONF
640 * | | start of vsync:
641 * | | generate vsync interrupt
643 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
644 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
645 * ----va---> <-----------------vb--------------------> <--------va-------------
646 * | | <----vs-----> |
647 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
648 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
649 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
651 * last visible pixel first visible pixel
652 * | increment frame counter (gen3/4)
653 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
655 * x = horizontal active
656 * _ = horizontal blanking
657 * hs = horizontal sync
658 * va = vertical active
659 * vb = vertical blanking
661 * vbs = vblank_start (number)
664 * - most events happen at the start of horizontal sync
665 * - frame start happens at the start of horizontal blank, 1-4 lines
666 * (depending on PIPECONF settings) after the start of vblank
667 * - gen3/4 pixel and frame counter are synchronized with the start
668 * of horizontal active on the first line of vertical active
671 static u32
i8xx_get_vblank_counter(struct drm_device
*dev
, unsigned int pipe
)
673 /* Gen2 doesn't have a hardware frame counter */
677 /* Called from drm generic code, passed a 'crtc', which
678 * we use as a pipe index
680 static u32
i915_get_vblank_counter(struct drm_device
*dev
, unsigned int pipe
)
682 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
683 i915_reg_t high_frame
, low_frame
;
684 u32 high1
, high2
, low
, pixel
, vbl_start
, hsync_start
, htotal
;
685 struct intel_crtc
*intel_crtc
=
686 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
687 const struct drm_display_mode
*mode
= &intel_crtc
->base
.hwmode
;
689 htotal
= mode
->crtc_htotal
;
690 hsync_start
= mode
->crtc_hsync_start
;
691 vbl_start
= mode
->crtc_vblank_start
;
692 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
693 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
695 /* Convert to pixel count */
698 /* Start of vblank event occurs at start of hsync */
699 vbl_start
-= htotal
- hsync_start
;
701 high_frame
= PIPEFRAME(pipe
);
702 low_frame
= PIPEFRAMEPIXEL(pipe
);
705 * High & low register fields aren't synchronized, so make sure
706 * we get a low value that's stable across two reads of the high
710 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
711 low
= I915_READ(low_frame
);
712 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
713 } while (high1
!= high2
);
715 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
716 pixel
= low
& PIPE_PIXEL_MASK
;
717 low
>>= PIPE_FRAME_LOW_SHIFT
;
720 * The frame counter increments at beginning of active.
721 * Cook up a vblank counter by also checking the pixel
722 * counter against vblank start.
724 return (((high1
<< 8) | low
) + (pixel
>= vbl_start
)) & 0xffffff;
727 static u32
g4x_get_vblank_counter(struct drm_device
*dev
, unsigned int pipe
)
729 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
731 return I915_READ(PIPE_FRMCOUNT_G4X(pipe
));
734 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
735 static int __intel_get_crtc_scanline(struct intel_crtc
*crtc
)
737 struct drm_device
*dev
= crtc
->base
.dev
;
738 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
739 const struct drm_display_mode
*mode
= &crtc
->base
.hwmode
;
740 enum pipe pipe
= crtc
->pipe
;
741 int position
, vtotal
;
743 vtotal
= mode
->crtc_vtotal
;
744 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
747 if (IS_GEN2(dev_priv
))
748 position
= I915_READ_FW(PIPEDSL(pipe
)) & DSL_LINEMASK_GEN2
;
750 position
= I915_READ_FW(PIPEDSL(pipe
)) & DSL_LINEMASK_GEN3
;
753 * On HSW, the DSL reg (0x70000) appears to return 0 if we
754 * read it just before the start of vblank. So try it again
755 * so we don't accidentally end up spanning a vblank frame
756 * increment, causing the pipe_update_end() code to squak at us.
758 * The nature of this problem means we can't simply check the ISR
759 * bit and return the vblank start value; nor can we use the scanline
760 * debug register in the transcoder as it appears to have the same
761 * problem. We may need to extend this to include other platforms,
762 * but so far testing only shows the problem on HSW.
764 if (HAS_DDI(dev_priv
) && !position
) {
767 for (i
= 0; i
< 100; i
++) {
769 temp
= __raw_i915_read32(dev_priv
, PIPEDSL(pipe
)) &
771 if (temp
!= position
) {
779 * See update_scanline_offset() for the details on the
780 * scanline_offset adjustment.
782 return (position
+ crtc
->scanline_offset
) % vtotal
;
785 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, unsigned int pipe
,
786 unsigned int flags
, int *vpos
, int *hpos
,
787 ktime_t
*stime
, ktime_t
*etime
,
788 const struct drm_display_mode
*mode
)
790 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
791 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
792 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
794 int vbl_start
, vbl_end
, hsync_start
, htotal
, vtotal
;
797 unsigned long irqflags
;
799 if (WARN_ON(!mode
->crtc_clock
)) {
800 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
801 "pipe %c\n", pipe_name(pipe
));
805 htotal
= mode
->crtc_htotal
;
806 hsync_start
= mode
->crtc_hsync_start
;
807 vtotal
= mode
->crtc_vtotal
;
808 vbl_start
= mode
->crtc_vblank_start
;
809 vbl_end
= mode
->crtc_vblank_end
;
811 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
812 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
817 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
820 * Lock uncore.lock, as we will do multiple timing critical raw
821 * register reads, potentially with preemption disabled, so the
822 * following code must not block on uncore.lock.
824 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
826 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
828 /* Get optional system timestamp before query. */
830 *stime
= ktime_get();
832 if (IS_GEN2(dev_priv
) || IS_G4X(dev_priv
) || INTEL_GEN(dev_priv
) >= 5) {
833 /* No obvious pixelcount register. Only query vertical
834 * scanout position from Display scan line register.
836 position
= __intel_get_crtc_scanline(intel_crtc
);
838 /* Have access to pixelcount since start of frame.
839 * We can split this into vertical and horizontal
842 position
= (I915_READ_FW(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
844 /* convert to pixel counts */
850 * In interlaced modes, the pixel counter counts all pixels,
851 * so one field will have htotal more pixels. In order to avoid
852 * the reported position from jumping backwards when the pixel
853 * counter is beyond the length of the shorter field, just
854 * clamp the position the length of the shorter field. This
855 * matches how the scanline counter based position works since
856 * the scanline counter doesn't count the two half lines.
858 if (position
>= vtotal
)
859 position
= vtotal
- 1;
862 * Start of vblank interrupt is triggered at start of hsync,
863 * just prior to the first active line of vblank. However we
864 * consider lines to start at the leading edge of horizontal
865 * active. So, should we get here before we've crossed into
866 * the horizontal active of the first line in vblank, we would
867 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
868 * always add htotal-hsync_start to the current pixel position.
870 position
= (position
+ htotal
- hsync_start
) % vtotal
;
873 /* Get optional system timestamp after query. */
875 *etime
= ktime_get();
877 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
879 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
881 in_vbl
= position
>= vbl_start
&& position
< vbl_end
;
884 * While in vblank, position will be negative
885 * counting up towards 0 at vbl_end. And outside
886 * vblank, position will be positive counting
889 if (position
>= vbl_start
)
892 position
+= vtotal
- vbl_end
;
894 if (IS_GEN2(dev_priv
) || IS_G4X(dev_priv
) || INTEL_GEN(dev_priv
) >= 5) {
898 *vpos
= position
/ htotal
;
899 *hpos
= position
- (*vpos
* htotal
);
904 ret
|= DRM_SCANOUTPOS_IN_VBLANK
;
909 int intel_get_crtc_scanline(struct intel_crtc
*crtc
)
911 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
912 unsigned long irqflags
;
915 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
916 position
= __intel_get_crtc_scanline(crtc
);
917 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
922 static int i915_get_vblank_timestamp(struct drm_device
*dev
, unsigned int pipe
,
924 struct timeval
*vblank_time
,
927 struct drm_crtc
*crtc
;
929 if (pipe
>= INTEL_INFO(dev
)->num_pipes
) {
930 DRM_ERROR("Invalid crtc %u\n", pipe
);
934 /* Get drm_crtc to timestamp: */
935 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
937 DRM_ERROR("Invalid crtc %u\n", pipe
);
941 if (!crtc
->hwmode
.crtc_clock
) {
942 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe
);
946 /* Helper routine in DRM core does all the work: */
947 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
952 static void ironlake_rps_change_irq_handler(struct drm_i915_private
*dev_priv
)
954 u32 busy_up
, busy_down
, max_avg
, min_avg
;
957 spin_lock(&mchdev_lock
);
959 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
961 new_delay
= dev_priv
->ips
.cur_delay
;
963 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
964 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
965 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
966 max_avg
= I915_READ(RCBMAXAVG
);
967 min_avg
= I915_READ(RCBMINAVG
);
969 /* Handle RCS change request from hw */
970 if (busy_up
> max_avg
) {
971 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
972 new_delay
= dev_priv
->ips
.cur_delay
- 1;
973 if (new_delay
< dev_priv
->ips
.max_delay
)
974 new_delay
= dev_priv
->ips
.max_delay
;
975 } else if (busy_down
< min_avg
) {
976 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
977 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
978 if (new_delay
> dev_priv
->ips
.min_delay
)
979 new_delay
= dev_priv
->ips
.min_delay
;
982 if (ironlake_set_drps(dev_priv
, new_delay
))
983 dev_priv
->ips
.cur_delay
= new_delay
;
985 spin_unlock(&mchdev_lock
);
990 static void notify_ring(struct intel_engine_cs
*engine
)
992 if (!intel_engine_initialized(engine
))
995 trace_i915_gem_request_notify(engine
);
996 engine
->user_interrupts
++;
998 wake_up_all(&engine
->irq_queue
);
1001 static void vlv_c0_read(struct drm_i915_private
*dev_priv
,
1002 struct intel_rps_ei
*ei
)
1004 ei
->cz_clock
= vlv_punit_read(dev_priv
, PUNIT_REG_CZ_TIMESTAMP
);
1005 ei
->render_c0
= I915_READ(VLV_RENDER_C0_COUNT
);
1006 ei
->media_c0
= I915_READ(VLV_MEDIA_C0_COUNT
);
1009 static bool vlv_c0_above(struct drm_i915_private
*dev_priv
,
1010 const struct intel_rps_ei
*old
,
1011 const struct intel_rps_ei
*now
,
1015 unsigned int mul
= 100;
1017 if (old
->cz_clock
== 0)
1020 if (I915_READ(VLV_COUNTER_CONTROL
) & VLV_COUNT_RANGE_HIGH
)
1023 time
= now
->cz_clock
- old
->cz_clock
;
1024 time
*= threshold
* dev_priv
->czclk_freq
;
1026 /* Workload can be split between render + media, e.g. SwapBuffers
1027 * being blitted in X after being rendered in mesa. To account for
1028 * this we need to combine both engines into our activity counter.
1030 c0
= now
->render_c0
- old
->render_c0
;
1031 c0
+= now
->media_c0
- old
->media_c0
;
1032 c0
*= mul
* VLV_CZ_CLOCK_TO_MILLI_SEC
;
1037 void gen6_rps_reset_ei(struct drm_i915_private
*dev_priv
)
1039 vlv_c0_read(dev_priv
, &dev_priv
->rps
.down_ei
);
1040 dev_priv
->rps
.up_ei
= dev_priv
->rps
.down_ei
;
1043 static u32
vlv_wa_c0_ei(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1045 struct intel_rps_ei now
;
1048 if ((pm_iir
& (GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
)) == 0)
1051 vlv_c0_read(dev_priv
, &now
);
1052 if (now
.cz_clock
== 0)
1055 if (pm_iir
& GEN6_PM_RP_DOWN_EI_EXPIRED
) {
1056 if (!vlv_c0_above(dev_priv
,
1057 &dev_priv
->rps
.down_ei
, &now
,
1058 dev_priv
->rps
.down_threshold
))
1059 events
|= GEN6_PM_RP_DOWN_THRESHOLD
;
1060 dev_priv
->rps
.down_ei
= now
;
1063 if (pm_iir
& GEN6_PM_RP_UP_EI_EXPIRED
) {
1064 if (vlv_c0_above(dev_priv
,
1065 &dev_priv
->rps
.up_ei
, &now
,
1066 dev_priv
->rps
.up_threshold
))
1067 events
|= GEN6_PM_RP_UP_THRESHOLD
;
1068 dev_priv
->rps
.up_ei
= now
;
1074 static bool any_waiters(struct drm_i915_private
*dev_priv
)
1076 struct intel_engine_cs
*engine
;
1078 for_each_engine(engine
, dev_priv
)
1079 if (engine
->irq_refcount
)
1085 static void gen6_pm_rps_work(struct work_struct
*work
)
1087 struct drm_i915_private
*dev_priv
=
1088 container_of(work
, struct drm_i915_private
, rps
.work
);
1090 int new_delay
, adj
, min
, max
;
1093 spin_lock_irq(&dev_priv
->irq_lock
);
1094 /* Speed up work cancelation during disabling rps interrupts. */
1095 if (!dev_priv
->rps
.interrupts_enabled
) {
1096 spin_unlock_irq(&dev_priv
->irq_lock
);
1101 * The RPS work is synced during runtime suspend, we don't require a
1102 * wakeref. TODO: instead of disabling the asserts make sure that we
1103 * always hold an RPM reference while the work is running.
1105 DISABLE_RPM_WAKEREF_ASSERTS(dev_priv
);
1107 pm_iir
= dev_priv
->rps
.pm_iir
;
1108 dev_priv
->rps
.pm_iir
= 0;
1109 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1110 gen6_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
1111 client_boost
= dev_priv
->rps
.client_boost
;
1112 dev_priv
->rps
.client_boost
= false;
1113 spin_unlock_irq(&dev_priv
->irq_lock
);
1115 /* Make sure we didn't queue anything we're not going to process. */
1116 WARN_ON(pm_iir
& ~dev_priv
->pm_rps_events
);
1118 if ((pm_iir
& dev_priv
->pm_rps_events
) == 0 && !client_boost
)
1121 mutex_lock(&dev_priv
->rps
.hw_lock
);
1123 pm_iir
|= vlv_wa_c0_ei(dev_priv
, pm_iir
);
1125 adj
= dev_priv
->rps
.last_adj
;
1126 new_delay
= dev_priv
->rps
.cur_freq
;
1127 min
= dev_priv
->rps
.min_freq_softlimit
;
1128 max
= dev_priv
->rps
.max_freq_softlimit
;
1131 new_delay
= dev_priv
->rps
.max_freq_softlimit
;
1133 } else if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
1136 else /* CHV needs even encode values */
1137 adj
= IS_CHERRYVIEW(dev_priv
) ? 2 : 1;
1139 * For better performance, jump directly
1140 * to RPe if we're below it.
1142 if (new_delay
< dev_priv
->rps
.efficient_freq
- adj
) {
1143 new_delay
= dev_priv
->rps
.efficient_freq
;
1146 } else if (any_waiters(dev_priv
)) {
1148 } else if (pm_iir
& GEN6_PM_RP_DOWN_TIMEOUT
) {
1149 if (dev_priv
->rps
.cur_freq
> dev_priv
->rps
.efficient_freq
)
1150 new_delay
= dev_priv
->rps
.efficient_freq
;
1152 new_delay
= dev_priv
->rps
.min_freq_softlimit
;
1154 } else if (pm_iir
& GEN6_PM_RP_DOWN_THRESHOLD
) {
1157 else /* CHV needs even encode values */
1158 adj
= IS_CHERRYVIEW(dev_priv
) ? -2 : -1;
1159 } else { /* unknown event */
1163 dev_priv
->rps
.last_adj
= adj
;
1165 /* sysfs frequency interfaces may have snuck in while servicing the
1169 new_delay
= clamp_t(int, new_delay
, min
, max
);
1171 intel_set_rps(dev_priv
->dev
, new_delay
);
1173 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1175 ENABLE_RPM_WAKEREF_ASSERTS(dev_priv
);
1180 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1182 * @work: workqueue struct
1184 * Doesn't actually do anything except notify userspace. As a consequence of
1185 * this event, userspace should try to remap the bad rows since statistically
1186 * it is likely the same row is more likely to go bad again.
1188 static void ivybridge_parity_work(struct work_struct
*work
)
1190 struct drm_i915_private
*dev_priv
=
1191 container_of(work
, struct drm_i915_private
, l3_parity
.error_work
);
1192 u32 error_status
, row
, bank
, subbank
;
1193 char *parity_event
[6];
1197 /* We must turn off DOP level clock gating to access the L3 registers.
1198 * In order to prevent a get/put style interface, acquire struct mutex
1199 * any time we access those registers.
1201 mutex_lock(&dev_priv
->dev
->struct_mutex
);
1203 /* If we've screwed up tracking, just let the interrupt fire again */
1204 if (WARN_ON(!dev_priv
->l3_parity
.which_slice
))
1207 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1208 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
1209 POSTING_READ(GEN7_MISCCPCTL
);
1211 while ((slice
= ffs(dev_priv
->l3_parity
.which_slice
)) != 0) {
1215 if (WARN_ON_ONCE(slice
>= NUM_L3_SLICES(dev_priv
)))
1218 dev_priv
->l3_parity
.which_slice
&= ~(1<<slice
);
1220 reg
= GEN7_L3CDERRST1(slice
);
1222 error_status
= I915_READ(reg
);
1223 row
= GEN7_PARITY_ERROR_ROW(error_status
);
1224 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
1225 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
1227 I915_WRITE(reg
, GEN7_PARITY_ERROR_VALID
| GEN7_L3CDERRST1_ENABLE
);
1230 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
1231 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
1232 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
1233 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
1234 parity_event
[4] = kasprintf(GFP_KERNEL
, "SLICE=%d", slice
);
1235 parity_event
[5] = NULL
;
1237 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
->kobj
,
1238 KOBJ_CHANGE
, parity_event
);
1240 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1241 slice
, row
, bank
, subbank
);
1243 kfree(parity_event
[4]);
1244 kfree(parity_event
[3]);
1245 kfree(parity_event
[2]);
1246 kfree(parity_event
[1]);
1249 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
1252 WARN_ON(dev_priv
->l3_parity
.which_slice
);
1253 spin_lock_irq(&dev_priv
->irq_lock
);
1254 gen5_enable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
));
1255 spin_unlock_irq(&dev_priv
->irq_lock
);
1257 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
1260 static void ivybridge_parity_error_irq_handler(struct drm_i915_private
*dev_priv
,
1263 if (!HAS_L3_DPF(dev_priv
))
1266 spin_lock(&dev_priv
->irq_lock
);
1267 gen5_disable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
));
1268 spin_unlock(&dev_priv
->irq_lock
);
1270 iir
&= GT_PARITY_ERROR(dev_priv
);
1271 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1
)
1272 dev_priv
->l3_parity
.which_slice
|= 1 << 1;
1274 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
1275 dev_priv
->l3_parity
.which_slice
|= 1 << 0;
1277 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
1280 static void ilk_gt_irq_handler(struct drm_i915_private
*dev_priv
,
1284 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1285 notify_ring(&dev_priv
->engine
[RCS
]);
1286 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
1287 notify_ring(&dev_priv
->engine
[VCS
]);
1290 static void snb_gt_irq_handler(struct drm_i915_private
*dev_priv
,
1295 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1296 notify_ring(&dev_priv
->engine
[RCS
]);
1297 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
1298 notify_ring(&dev_priv
->engine
[VCS
]);
1299 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
1300 notify_ring(&dev_priv
->engine
[BCS
]);
1302 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
1303 GT_BSD_CS_ERROR_INTERRUPT
|
1304 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
))
1305 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir
);
1307 if (gt_iir
& GT_PARITY_ERROR(dev_priv
))
1308 ivybridge_parity_error_irq_handler(dev_priv
, gt_iir
);
1311 static __always_inline
void
1312 gen8_cs_irq_handler(struct intel_engine_cs
*engine
, u32 iir
, int test_shift
)
1314 if (iir
& (GT_RENDER_USER_INTERRUPT
<< test_shift
))
1315 notify_ring(engine
);
1316 if (iir
& (GT_CONTEXT_SWITCH_INTERRUPT
<< test_shift
))
1317 tasklet_schedule(&engine
->irq_tasklet
);
1320 static irqreturn_t
gen8_gt_irq_ack(struct drm_i915_private
*dev_priv
,
1324 irqreturn_t ret
= IRQ_NONE
;
1326 if (master_ctl
& (GEN8_GT_RCS_IRQ
| GEN8_GT_BCS_IRQ
)) {
1327 gt_iir
[0] = I915_READ_FW(GEN8_GT_IIR(0));
1329 I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir
[0]);
1332 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1335 if (master_ctl
& (GEN8_GT_VCS1_IRQ
| GEN8_GT_VCS2_IRQ
)) {
1336 gt_iir
[1] = I915_READ_FW(GEN8_GT_IIR(1));
1338 I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir
[1]);
1341 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1344 if (master_ctl
& GEN8_GT_VECS_IRQ
) {
1345 gt_iir
[3] = I915_READ_FW(GEN8_GT_IIR(3));
1347 I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir
[3]);
1350 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1353 if (master_ctl
& GEN8_GT_PM_IRQ
) {
1354 gt_iir
[2] = I915_READ_FW(GEN8_GT_IIR(2));
1355 if (gt_iir
[2] & dev_priv
->pm_rps_events
) {
1356 I915_WRITE_FW(GEN8_GT_IIR(2),
1357 gt_iir
[2] & dev_priv
->pm_rps_events
);
1360 DRM_ERROR("The master control interrupt lied (PM)!\n");
1366 static void gen8_gt_irq_handler(struct drm_i915_private
*dev_priv
,
1370 gen8_cs_irq_handler(&dev_priv
->engine
[RCS
],
1371 gt_iir
[0], GEN8_RCS_IRQ_SHIFT
);
1372 gen8_cs_irq_handler(&dev_priv
->engine
[BCS
],
1373 gt_iir
[0], GEN8_BCS_IRQ_SHIFT
);
1377 gen8_cs_irq_handler(&dev_priv
->engine
[VCS
],
1378 gt_iir
[1], GEN8_VCS1_IRQ_SHIFT
);
1379 gen8_cs_irq_handler(&dev_priv
->engine
[VCS2
],
1380 gt_iir
[1], GEN8_VCS2_IRQ_SHIFT
);
1384 gen8_cs_irq_handler(&dev_priv
->engine
[VECS
],
1385 gt_iir
[3], GEN8_VECS_IRQ_SHIFT
);
1387 if (gt_iir
[2] & dev_priv
->pm_rps_events
)
1388 gen6_rps_irq_handler(dev_priv
, gt_iir
[2]);
1391 static bool bxt_port_hotplug_long_detect(enum port port
, u32 val
)
1395 return val
& PORTA_HOTPLUG_LONG_DETECT
;
1397 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1399 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1405 static bool spt_port_hotplug2_long_detect(enum port port
, u32 val
)
1409 return val
& PORTE_HOTPLUG_LONG_DETECT
;
1415 static bool spt_port_hotplug_long_detect(enum port port
, u32 val
)
1419 return val
& PORTA_HOTPLUG_LONG_DETECT
;
1421 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1423 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1425 return val
& PORTD_HOTPLUG_LONG_DETECT
;
1431 static bool ilk_port_hotplug_long_detect(enum port port
, u32 val
)
1435 return val
& DIGITAL_PORTA_HOTPLUG_LONG_DETECT
;
1441 static bool pch_port_hotplug_long_detect(enum port port
, u32 val
)
1445 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1447 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1449 return val
& PORTD_HOTPLUG_LONG_DETECT
;
1455 static bool i9xx_port_hotplug_long_detect(enum port port
, u32 val
)
1459 return val
& PORTB_HOTPLUG_INT_LONG_PULSE
;
1461 return val
& PORTC_HOTPLUG_INT_LONG_PULSE
;
1463 return val
& PORTD_HOTPLUG_INT_LONG_PULSE
;
1470 * Get a bit mask of pins that have triggered, and which ones may be long.
1471 * This can be called multiple times with the same masks to accumulate
1472 * hotplug detection results from several registers.
1474 * Note that the caller is expected to zero out the masks initially.
1476 static void intel_get_hpd_pins(u32
*pin_mask
, u32
*long_mask
,
1477 u32 hotplug_trigger
, u32 dig_hotplug_reg
,
1478 const u32 hpd
[HPD_NUM_PINS
],
1479 bool long_pulse_detect(enum port port
, u32 val
))
1484 for_each_hpd_pin(i
) {
1485 if ((hpd
[i
] & hotplug_trigger
) == 0)
1488 *pin_mask
|= BIT(i
);
1490 if (!intel_hpd_pin_to_port(i
, &port
))
1493 if (long_pulse_detect(port
, dig_hotplug_reg
))
1494 *long_mask
|= BIT(i
);
1497 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1498 hotplug_trigger
, dig_hotplug_reg
, *pin_mask
);
1502 static void gmbus_irq_handler(struct drm_i915_private
*dev_priv
)
1504 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1507 static void dp_aux_irq_handler(struct drm_i915_private
*dev_priv
)
1509 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1512 #if defined(CONFIG_DEBUG_FS)
1513 static void display_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1515 uint32_t crc0
, uint32_t crc1
,
1516 uint32_t crc2
, uint32_t crc3
,
1519 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
1520 struct intel_pipe_crc_entry
*entry
;
1523 spin_lock(&pipe_crc
->lock
);
1525 if (!pipe_crc
->entries
) {
1526 spin_unlock(&pipe_crc
->lock
);
1527 DRM_DEBUG_KMS("spurious interrupt\n");
1531 head
= pipe_crc
->head
;
1532 tail
= pipe_crc
->tail
;
1534 if (CIRC_SPACE(head
, tail
, INTEL_PIPE_CRC_ENTRIES_NR
) < 1) {
1535 spin_unlock(&pipe_crc
->lock
);
1536 DRM_ERROR("CRC buffer overflowing\n");
1540 entry
= &pipe_crc
->entries
[head
];
1542 entry
->frame
= dev_priv
->dev
->driver
->get_vblank_counter(dev_priv
->dev
,
1544 entry
->crc
[0] = crc0
;
1545 entry
->crc
[1] = crc1
;
1546 entry
->crc
[2] = crc2
;
1547 entry
->crc
[3] = crc3
;
1548 entry
->crc
[4] = crc4
;
1550 head
= (head
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
1551 pipe_crc
->head
= head
;
1553 spin_unlock(&pipe_crc
->lock
);
1555 wake_up_interruptible(&pipe_crc
->wq
);
1559 display_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1561 uint32_t crc0
, uint32_t crc1
,
1562 uint32_t crc2
, uint32_t crc3
,
1567 static void hsw_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1570 display_pipe_crc_irq_handler(dev_priv
, pipe
,
1571 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1575 static void ivb_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1578 display_pipe_crc_irq_handler(dev_priv
, pipe
,
1579 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1580 I915_READ(PIPE_CRC_RES_2_IVB(pipe
)),
1581 I915_READ(PIPE_CRC_RES_3_IVB(pipe
)),
1582 I915_READ(PIPE_CRC_RES_4_IVB(pipe
)),
1583 I915_READ(PIPE_CRC_RES_5_IVB(pipe
)));
1586 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1589 uint32_t res1
, res2
;
1591 if (INTEL_GEN(dev_priv
) >= 3)
1592 res1
= I915_READ(PIPE_CRC_RES_RES1_I915(pipe
));
1596 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
1597 res2
= I915_READ(PIPE_CRC_RES_RES2_G4X(pipe
));
1601 display_pipe_crc_irq_handler(dev_priv
, pipe
,
1602 I915_READ(PIPE_CRC_RES_RED(pipe
)),
1603 I915_READ(PIPE_CRC_RES_GREEN(pipe
)),
1604 I915_READ(PIPE_CRC_RES_BLUE(pipe
)),
1608 /* The RPS events need forcewake, so we add them to a work queue and mask their
1609 * IMR bits until the work is done. Other interrupts can be processed without
1610 * the work queue. */
1611 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1613 if (pm_iir
& dev_priv
->pm_rps_events
) {
1614 spin_lock(&dev_priv
->irq_lock
);
1615 gen6_disable_pm_irq(dev_priv
, pm_iir
& dev_priv
->pm_rps_events
);
1616 if (dev_priv
->rps
.interrupts_enabled
) {
1617 dev_priv
->rps
.pm_iir
|= pm_iir
& dev_priv
->pm_rps_events
;
1618 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
1620 spin_unlock(&dev_priv
->irq_lock
);
1623 if (INTEL_INFO(dev_priv
)->gen
>= 8)
1626 if (HAS_VEBOX(dev_priv
)) {
1627 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1628 notify_ring(&dev_priv
->engine
[VECS
]);
1630 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
)
1631 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir
);
1635 static bool intel_pipe_handle_vblank(struct drm_i915_private
*dev_priv
,
1638 return drm_handle_vblank(dev_priv
->dev
, pipe
);
1641 static void valleyview_pipestat_irq_ack(struct drm_i915_private
*dev_priv
,
1642 u32 iir
, u32 pipe_stats
[I915_MAX_PIPES
])
1646 spin_lock(&dev_priv
->irq_lock
);
1648 if (!dev_priv
->display_irqs_enabled
) {
1649 spin_unlock(&dev_priv
->irq_lock
);
1653 for_each_pipe(dev_priv
, pipe
) {
1655 u32 mask
, iir_bit
= 0;
1658 * PIPESTAT bits get signalled even when the interrupt is
1659 * disabled with the mask bits, and some of the status bits do
1660 * not generate interrupts at all (like the underrun bit). Hence
1661 * we need to be careful that we only handle what we want to
1665 /* fifo underruns are filterered in the underrun handler. */
1666 mask
= PIPE_FIFO_UNDERRUN_STATUS
;
1670 iir_bit
= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
;
1673 iir_bit
= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
1676 iir_bit
= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
1680 mask
|= dev_priv
->pipestat_irq_mask
[pipe
];
1685 reg
= PIPESTAT(pipe
);
1686 mask
|= PIPESTAT_INT_ENABLE_MASK
;
1687 pipe_stats
[pipe
] = I915_READ(reg
) & mask
;
1690 * Clear the PIPE*STAT regs before the IIR
1692 if (pipe_stats
[pipe
] & (PIPE_FIFO_UNDERRUN_STATUS
|
1693 PIPESTAT_INT_STATUS_MASK
))
1694 I915_WRITE(reg
, pipe_stats
[pipe
]);
1696 spin_unlock(&dev_priv
->irq_lock
);
1699 static void valleyview_pipestat_irq_handler(struct drm_i915_private
*dev_priv
,
1700 u32 pipe_stats
[I915_MAX_PIPES
])
1704 for_each_pipe(dev_priv
, pipe
) {
1705 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
1706 intel_pipe_handle_vblank(dev_priv
, pipe
))
1707 intel_check_page_flip(dev_priv
, pipe
);
1709 if (pipe_stats
[pipe
] & PLANE_FLIP_DONE_INT_STATUS_VLV
) {
1710 intel_prepare_page_flip(dev_priv
, pipe
);
1711 intel_finish_page_flip(dev_priv
, pipe
);
1714 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
1715 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
1717 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1718 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
1721 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1722 gmbus_irq_handler(dev_priv
);
1725 static u32
i9xx_hpd_irq_ack(struct drm_i915_private
*dev_priv
)
1727 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1730 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1732 return hotplug_status
;
1735 static void i9xx_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
1738 u32 pin_mask
= 0, long_mask
= 0;
1740 if (IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
1741 IS_CHERRYVIEW(dev_priv
)) {
1742 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_G4X
;
1744 if (hotplug_trigger
) {
1745 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
1746 hotplug_trigger
, hpd_status_g4x
,
1747 i9xx_port_hotplug_long_detect
);
1749 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
1752 if (hotplug_status
& DP_AUX_CHANNEL_MASK_INT_STATUS_G4X
)
1753 dp_aux_irq_handler(dev_priv
);
1755 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1757 if (hotplug_trigger
) {
1758 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
1759 hotplug_trigger
, hpd_status_i915
,
1760 i9xx_port_hotplug_long_detect
);
1761 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
1766 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1768 struct drm_device
*dev
= arg
;
1769 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1770 irqreturn_t ret
= IRQ_NONE
;
1772 if (!intel_irqs_enabled(dev_priv
))
1775 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1776 disable_rpm_wakeref_asserts(dev_priv
);
1779 u32 iir
, gt_iir
, pm_iir
;
1780 u32 pipe_stats
[I915_MAX_PIPES
] = {};
1781 u32 hotplug_status
= 0;
1784 gt_iir
= I915_READ(GTIIR
);
1785 pm_iir
= I915_READ(GEN6_PMIIR
);
1786 iir
= I915_READ(VLV_IIR
);
1788 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1794 * Theory on interrupt generation, based on empirical evidence:
1796 * x = ((VLV_IIR & VLV_IER) ||
1797 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1798 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1800 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1801 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1802 * guarantee the CPU interrupt will be raised again even if we
1803 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1804 * bits this time around.
1806 I915_WRITE(VLV_MASTER_IER
, 0);
1807 ier
= I915_READ(VLV_IER
);
1808 I915_WRITE(VLV_IER
, 0);
1811 I915_WRITE(GTIIR
, gt_iir
);
1813 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1815 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1816 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
1818 /* Call regardless, as some status bits might not be
1819 * signalled in iir */
1820 valleyview_pipestat_irq_ack(dev_priv
, iir
, pipe_stats
);
1823 * VLV_IIR is single buffered, and reflects the level
1824 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1827 I915_WRITE(VLV_IIR
, iir
);
1829 I915_WRITE(VLV_IER
, ier
);
1830 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
1831 POSTING_READ(VLV_MASTER_IER
);
1834 snb_gt_irq_handler(dev_priv
, gt_iir
);
1836 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1839 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
1841 valleyview_pipestat_irq_handler(dev_priv
, pipe_stats
);
1844 enable_rpm_wakeref_asserts(dev_priv
);
1849 static irqreturn_t
cherryview_irq_handler(int irq
, void *arg
)
1851 struct drm_device
*dev
= arg
;
1852 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1853 irqreturn_t ret
= IRQ_NONE
;
1855 if (!intel_irqs_enabled(dev_priv
))
1858 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1859 disable_rpm_wakeref_asserts(dev_priv
);
1862 u32 master_ctl
, iir
;
1864 u32 pipe_stats
[I915_MAX_PIPES
] = {};
1865 u32 hotplug_status
= 0;
1868 master_ctl
= I915_READ(GEN8_MASTER_IRQ
) & ~GEN8_MASTER_IRQ_CONTROL
;
1869 iir
= I915_READ(VLV_IIR
);
1871 if (master_ctl
== 0 && iir
== 0)
1877 * Theory on interrupt generation, based on empirical evidence:
1879 * x = ((VLV_IIR & VLV_IER) ||
1880 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1881 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1883 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1884 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1885 * guarantee the CPU interrupt will be raised again even if we
1886 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1887 * bits this time around.
1889 I915_WRITE(GEN8_MASTER_IRQ
, 0);
1890 ier
= I915_READ(VLV_IER
);
1891 I915_WRITE(VLV_IER
, 0);
1893 gen8_gt_irq_ack(dev_priv
, master_ctl
, gt_iir
);
1895 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1896 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
1898 /* Call regardless, as some status bits might not be
1899 * signalled in iir */
1900 valleyview_pipestat_irq_ack(dev_priv
, iir
, pipe_stats
);
1903 * VLV_IIR is single buffered, and reflects the level
1904 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1907 I915_WRITE(VLV_IIR
, iir
);
1909 I915_WRITE(VLV_IER
, ier
);
1910 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
1911 POSTING_READ(GEN8_MASTER_IRQ
);
1913 gen8_gt_irq_handler(dev_priv
, gt_iir
);
1916 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
1918 valleyview_pipestat_irq_handler(dev_priv
, pipe_stats
);
1921 enable_rpm_wakeref_asserts(dev_priv
);
1926 static void ibx_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
1927 u32 hotplug_trigger
,
1928 const u32 hpd
[HPD_NUM_PINS
])
1930 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
1933 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1934 * unless we touch the hotplug register, even if hotplug_trigger is
1935 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1938 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
1939 if (!hotplug_trigger
) {
1940 u32 mask
= PORTA_HOTPLUG_STATUS_MASK
|
1941 PORTD_HOTPLUG_STATUS_MASK
|
1942 PORTC_HOTPLUG_STATUS_MASK
|
1943 PORTB_HOTPLUG_STATUS_MASK
;
1944 dig_hotplug_reg
&= ~mask
;
1947 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
1948 if (!hotplug_trigger
)
1951 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
1952 dig_hotplug_reg
, hpd
,
1953 pch_port_hotplug_long_detect
);
1955 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
1958 static void ibx_irq_handler(struct drm_i915_private
*dev_priv
, u32 pch_iir
)
1961 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1963 ibx_hpd_irq_handler(dev_priv
, hotplug_trigger
, hpd_ibx
);
1965 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1966 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1967 SDE_AUDIO_POWER_SHIFT
);
1968 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1972 if (pch_iir
& SDE_AUX_MASK
)
1973 dp_aux_irq_handler(dev_priv
);
1975 if (pch_iir
& SDE_GMBUS
)
1976 gmbus_irq_handler(dev_priv
);
1978 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1979 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1981 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1982 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1984 if (pch_iir
& SDE_POISON
)
1985 DRM_ERROR("PCH poison interrupt\n");
1987 if (pch_iir
& SDE_FDI_MASK
)
1988 for_each_pipe(dev_priv
, pipe
)
1989 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1991 I915_READ(FDI_RX_IIR(pipe
)));
1993 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1994 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1996 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1997 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1999 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
2000 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_A
);
2002 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
2003 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_B
);
2006 static void ivb_err_int_handler(struct drm_i915_private
*dev_priv
)
2008 u32 err_int
= I915_READ(GEN7_ERR_INT
);
2011 if (err_int
& ERR_INT_POISON
)
2012 DRM_ERROR("Poison interrupt\n");
2014 for_each_pipe(dev_priv
, pipe
) {
2015 if (err_int
& ERR_INT_FIFO_UNDERRUN(pipe
))
2016 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2018 if (err_int
& ERR_INT_PIPE_CRC_DONE(pipe
)) {
2019 if (IS_IVYBRIDGE(dev_priv
))
2020 ivb_pipe_crc_irq_handler(dev_priv
, pipe
);
2022 hsw_pipe_crc_irq_handler(dev_priv
, pipe
);
2026 I915_WRITE(GEN7_ERR_INT
, err_int
);
2029 static void cpt_serr_int_handler(struct drm_i915_private
*dev_priv
)
2031 u32 serr_int
= I915_READ(SERR_INT
);
2033 if (serr_int
& SERR_INT_POISON
)
2034 DRM_ERROR("PCH poison interrupt\n");
2036 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
2037 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_A
);
2039 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
2040 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_B
);
2042 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
2043 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_C
);
2045 I915_WRITE(SERR_INT
, serr_int
);
2048 static void cpt_irq_handler(struct drm_i915_private
*dev_priv
, u32 pch_iir
)
2051 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
2053 ibx_hpd_irq_handler(dev_priv
, hotplug_trigger
, hpd_cpt
);
2055 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
2056 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
2057 SDE_AUDIO_POWER_SHIFT_CPT
);
2058 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2062 if (pch_iir
& SDE_AUX_MASK_CPT
)
2063 dp_aux_irq_handler(dev_priv
);
2065 if (pch_iir
& SDE_GMBUS_CPT
)
2066 gmbus_irq_handler(dev_priv
);
2068 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
2069 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2071 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
2072 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2074 if (pch_iir
& SDE_FDI_MASK_CPT
)
2075 for_each_pipe(dev_priv
, pipe
)
2076 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2078 I915_READ(FDI_RX_IIR(pipe
)));
2080 if (pch_iir
& SDE_ERROR_CPT
)
2081 cpt_serr_int_handler(dev_priv
);
2084 static void spt_irq_handler(struct drm_i915_private
*dev_priv
, u32 pch_iir
)
2086 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_SPT
&
2087 ~SDE_PORTE_HOTPLUG_SPT
;
2088 u32 hotplug2_trigger
= pch_iir
& SDE_PORTE_HOTPLUG_SPT
;
2089 u32 pin_mask
= 0, long_mask
= 0;
2091 if (hotplug_trigger
) {
2092 u32 dig_hotplug_reg
;
2094 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
2095 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
2097 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
2098 dig_hotplug_reg
, hpd_spt
,
2099 spt_port_hotplug_long_detect
);
2102 if (hotplug2_trigger
) {
2103 u32 dig_hotplug_reg
;
2105 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG2
);
2106 I915_WRITE(PCH_PORT_HOTPLUG2
, dig_hotplug_reg
);
2108 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug2_trigger
,
2109 dig_hotplug_reg
, hpd_spt
,
2110 spt_port_hotplug2_long_detect
);
2114 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
2116 if (pch_iir
& SDE_GMBUS_CPT
)
2117 gmbus_irq_handler(dev_priv
);
2120 static void ilk_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
2121 u32 hotplug_trigger
,
2122 const u32 hpd
[HPD_NUM_PINS
])
2124 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
2126 dig_hotplug_reg
= I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL
);
2127 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL
, dig_hotplug_reg
);
2129 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
2130 dig_hotplug_reg
, hpd
,
2131 ilk_port_hotplug_long_detect
);
2133 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
2136 static void ilk_display_irq_handler(struct drm_i915_private
*dev_priv
,
2140 u32 hotplug_trigger
= de_iir
& DE_DP_A_HOTPLUG
;
2142 if (hotplug_trigger
)
2143 ilk_hpd_irq_handler(dev_priv
, hotplug_trigger
, hpd_ilk
);
2145 if (de_iir
& DE_AUX_CHANNEL_A
)
2146 dp_aux_irq_handler(dev_priv
);
2148 if (de_iir
& DE_GSE
)
2149 intel_opregion_asle_intr(dev_priv
);
2151 if (de_iir
& DE_POISON
)
2152 DRM_ERROR("Poison interrupt\n");
2154 for_each_pipe(dev_priv
, pipe
) {
2155 if (de_iir
& DE_PIPE_VBLANK(pipe
) &&
2156 intel_pipe_handle_vblank(dev_priv
, pipe
))
2157 intel_check_page_flip(dev_priv
, pipe
);
2159 if (de_iir
& DE_PIPE_FIFO_UNDERRUN(pipe
))
2160 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2162 if (de_iir
& DE_PIPE_CRC_DONE(pipe
))
2163 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
2165 /* plane/pipes map 1:1 on ilk+ */
2166 if (de_iir
& DE_PLANE_FLIP_DONE(pipe
)) {
2167 intel_prepare_page_flip(dev_priv
, pipe
);
2168 intel_finish_page_flip_plane(dev_priv
, pipe
);
2172 /* check event from PCH */
2173 if (de_iir
& DE_PCH_EVENT
) {
2174 u32 pch_iir
= I915_READ(SDEIIR
);
2176 if (HAS_PCH_CPT(dev_priv
))
2177 cpt_irq_handler(dev_priv
, pch_iir
);
2179 ibx_irq_handler(dev_priv
, pch_iir
);
2181 /* should clear PCH hotplug event before clear CPU irq */
2182 I915_WRITE(SDEIIR
, pch_iir
);
2185 if (IS_GEN5(dev_priv
) && de_iir
& DE_PCU_EVENT
)
2186 ironlake_rps_change_irq_handler(dev_priv
);
2189 static void ivb_display_irq_handler(struct drm_i915_private
*dev_priv
,
2193 u32 hotplug_trigger
= de_iir
& DE_DP_A_HOTPLUG_IVB
;
2195 if (hotplug_trigger
)
2196 ilk_hpd_irq_handler(dev_priv
, hotplug_trigger
, hpd_ivb
);
2198 if (de_iir
& DE_ERR_INT_IVB
)
2199 ivb_err_int_handler(dev_priv
);
2201 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
2202 dp_aux_irq_handler(dev_priv
);
2204 if (de_iir
& DE_GSE_IVB
)
2205 intel_opregion_asle_intr(dev_priv
);
2207 for_each_pipe(dev_priv
, pipe
) {
2208 if (de_iir
& (DE_PIPE_VBLANK_IVB(pipe
)) &&
2209 intel_pipe_handle_vblank(dev_priv
, pipe
))
2210 intel_check_page_flip(dev_priv
, pipe
);
2212 /* plane/pipes map 1:1 on ilk+ */
2213 if (de_iir
& DE_PLANE_FLIP_DONE_IVB(pipe
)) {
2214 intel_prepare_page_flip(dev_priv
, pipe
);
2215 intel_finish_page_flip_plane(dev_priv
, pipe
);
2219 /* check event from PCH */
2220 if (!HAS_PCH_NOP(dev_priv
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
2221 u32 pch_iir
= I915_READ(SDEIIR
);
2223 cpt_irq_handler(dev_priv
, pch_iir
);
2225 /* clear PCH hotplug event before clear CPU irq */
2226 I915_WRITE(SDEIIR
, pch_iir
);
2231 * To handle irqs with the minimum potential races with fresh interrupts, we:
2232 * 1 - Disable Master Interrupt Control.
2233 * 2 - Find the source(s) of the interrupt.
2234 * 3 - Clear the Interrupt Identity bits (IIR).
2235 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2236 * 5 - Re-enable Master Interrupt Control.
2238 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
2240 struct drm_device
*dev
= arg
;
2241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2242 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
2243 irqreturn_t ret
= IRQ_NONE
;
2245 if (!intel_irqs_enabled(dev_priv
))
2248 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2249 disable_rpm_wakeref_asserts(dev_priv
);
2251 /* disable master interrupt before clearing iir */
2252 de_ier
= I915_READ(DEIER
);
2253 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
2254 POSTING_READ(DEIER
);
2256 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2257 * interrupts will will be stored on its back queue, and then we'll be
2258 * able to process them after we restore SDEIER (as soon as we restore
2259 * it, we'll get an interrupt if SDEIIR still has something to process
2260 * due to its back queue). */
2261 if (!HAS_PCH_NOP(dev_priv
)) {
2262 sde_ier
= I915_READ(SDEIER
);
2263 I915_WRITE(SDEIER
, 0);
2264 POSTING_READ(SDEIER
);
2267 /* Find, clear, then process each source of interrupt */
2269 gt_iir
= I915_READ(GTIIR
);
2271 I915_WRITE(GTIIR
, gt_iir
);
2273 if (INTEL_GEN(dev_priv
) >= 6)
2274 snb_gt_irq_handler(dev_priv
, gt_iir
);
2276 ilk_gt_irq_handler(dev_priv
, gt_iir
);
2279 de_iir
= I915_READ(DEIIR
);
2281 I915_WRITE(DEIIR
, de_iir
);
2283 if (INTEL_GEN(dev_priv
) >= 7)
2284 ivb_display_irq_handler(dev_priv
, de_iir
);
2286 ilk_display_irq_handler(dev_priv
, de_iir
);
2289 if (INTEL_GEN(dev_priv
) >= 6) {
2290 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
2292 I915_WRITE(GEN6_PMIIR
, pm_iir
);
2294 gen6_rps_irq_handler(dev_priv
, pm_iir
);
2298 I915_WRITE(DEIER
, de_ier
);
2299 POSTING_READ(DEIER
);
2300 if (!HAS_PCH_NOP(dev_priv
)) {
2301 I915_WRITE(SDEIER
, sde_ier
);
2302 POSTING_READ(SDEIER
);
2305 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2306 enable_rpm_wakeref_asserts(dev_priv
);
2311 static void bxt_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
2312 u32 hotplug_trigger
,
2313 const u32 hpd
[HPD_NUM_PINS
])
2315 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
2317 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
2318 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
2320 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
2321 dig_hotplug_reg
, hpd
,
2322 bxt_port_hotplug_long_detect
);
2324 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
2328 gen8_de_irq_handler(struct drm_i915_private
*dev_priv
, u32 master_ctl
)
2330 irqreturn_t ret
= IRQ_NONE
;
2334 if (master_ctl
& GEN8_DE_MISC_IRQ
) {
2335 iir
= I915_READ(GEN8_DE_MISC_IIR
);
2337 I915_WRITE(GEN8_DE_MISC_IIR
, iir
);
2339 if (iir
& GEN8_DE_MISC_GSE
)
2340 intel_opregion_asle_intr(dev_priv
);
2342 DRM_ERROR("Unexpected DE Misc interrupt\n");
2345 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2348 if (master_ctl
& GEN8_DE_PORT_IRQ
) {
2349 iir
= I915_READ(GEN8_DE_PORT_IIR
);
2354 I915_WRITE(GEN8_DE_PORT_IIR
, iir
);
2357 tmp_mask
= GEN8_AUX_CHANNEL_A
;
2358 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2359 tmp_mask
|= GEN9_AUX_CHANNEL_B
|
2360 GEN9_AUX_CHANNEL_C
|
2363 if (iir
& tmp_mask
) {
2364 dp_aux_irq_handler(dev_priv
);
2368 if (IS_BROXTON(dev_priv
)) {
2369 tmp_mask
= iir
& BXT_DE_PORT_HOTPLUG_MASK
;
2371 bxt_hpd_irq_handler(dev_priv
, tmp_mask
,
2375 } else if (IS_BROADWELL(dev_priv
)) {
2376 tmp_mask
= iir
& GEN8_PORT_DP_A_HOTPLUG
;
2378 ilk_hpd_irq_handler(dev_priv
,
2384 if (IS_BROXTON(dev_priv
) && (iir
& BXT_DE_PORT_GMBUS
)) {
2385 gmbus_irq_handler(dev_priv
);
2390 DRM_ERROR("Unexpected DE Port interrupt\n");
2393 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2396 for_each_pipe(dev_priv
, pipe
) {
2397 u32 flip_done
, fault_errors
;
2399 if (!(master_ctl
& GEN8_DE_PIPE_IRQ(pipe
)))
2402 iir
= I915_READ(GEN8_DE_PIPE_IIR(pipe
));
2404 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2409 I915_WRITE(GEN8_DE_PIPE_IIR(pipe
), iir
);
2411 if (iir
& GEN8_PIPE_VBLANK
&&
2412 intel_pipe_handle_vblank(dev_priv
, pipe
))
2413 intel_check_page_flip(dev_priv
, pipe
);
2416 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2417 flip_done
&= GEN9_PIPE_PLANE1_FLIP_DONE
;
2419 flip_done
&= GEN8_PIPE_PRIMARY_FLIP_DONE
;
2422 intel_prepare_page_flip(dev_priv
, pipe
);
2423 intel_finish_page_flip_plane(dev_priv
, pipe
);
2426 if (iir
& GEN8_PIPE_CDCLK_CRC_DONE
)
2427 hsw_pipe_crc_irq_handler(dev_priv
, pipe
);
2429 if (iir
& GEN8_PIPE_FIFO_UNDERRUN
)
2430 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2433 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2434 fault_errors
&= GEN9_DE_PIPE_IRQ_FAULT_ERRORS
;
2436 fault_errors
&= GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
2439 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2444 if (HAS_PCH_SPLIT(dev_priv
) && !HAS_PCH_NOP(dev_priv
) &&
2445 master_ctl
& GEN8_DE_PCH_IRQ
) {
2447 * FIXME(BDW): Assume for now that the new interrupt handling
2448 * scheme also closed the SDE interrupt handling race we've seen
2449 * on older pch-split platforms. But this needs testing.
2451 iir
= I915_READ(SDEIIR
);
2453 I915_WRITE(SDEIIR
, iir
);
2456 if (HAS_PCH_SPT(dev_priv
))
2457 spt_irq_handler(dev_priv
, iir
);
2459 cpt_irq_handler(dev_priv
, iir
);
2462 * Like on previous PCH there seems to be something
2463 * fishy going on with forwarding PCH interrupts.
2465 DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2472 static irqreturn_t
gen8_irq_handler(int irq
, void *arg
)
2474 struct drm_device
*dev
= arg
;
2475 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2480 if (!intel_irqs_enabled(dev_priv
))
2483 master_ctl
= I915_READ_FW(GEN8_MASTER_IRQ
);
2484 master_ctl
&= ~GEN8_MASTER_IRQ_CONTROL
;
2488 I915_WRITE_FW(GEN8_MASTER_IRQ
, 0);
2490 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2491 disable_rpm_wakeref_asserts(dev_priv
);
2493 /* Find, clear, then process each source of interrupt */
2494 ret
= gen8_gt_irq_ack(dev_priv
, master_ctl
, gt_iir
);
2495 gen8_gt_irq_handler(dev_priv
, gt_iir
);
2496 ret
|= gen8_de_irq_handler(dev_priv
, master_ctl
);
2498 I915_WRITE_FW(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
2499 POSTING_READ_FW(GEN8_MASTER_IRQ
);
2501 enable_rpm_wakeref_asserts(dev_priv
);
2506 static void i915_error_wake_up(struct drm_i915_private
*dev_priv
,
2507 bool reset_completed
)
2509 struct intel_engine_cs
*engine
;
2512 * Notify all waiters for GPU completion events that reset state has
2513 * been changed, and that they need to restart their wait after
2514 * checking for potential errors (and bail out to drop locks if there is
2515 * a gpu reset pending so that i915_error_work_func can acquire them).
2518 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2519 for_each_engine(engine
, dev_priv
)
2520 wake_up_all(&engine
->irq_queue
);
2522 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2523 wake_up_all(&dev_priv
->pending_flip_queue
);
2526 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2527 * reset state is cleared.
2529 if (reset_completed
)
2530 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
2534 * i915_reset_and_wakeup - do process context error handling work
2537 * Fire an error uevent so userspace can see that a hang or error
2540 static void i915_reset_and_wakeup(struct drm_i915_private
*dev_priv
)
2542 struct kobject
*kobj
= &dev_priv
->dev
->primary
->kdev
->kobj
;
2543 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
2544 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
2545 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
2548 kobject_uevent_env(kobj
, KOBJ_CHANGE
, error_event
);
2551 * Note that there's only one work item which does gpu resets, so we
2552 * need not worry about concurrent gpu resets potentially incrementing
2553 * error->reset_counter twice. We only need to take care of another
2554 * racing irq/hangcheck declaring the gpu dead for a second time. A
2555 * quick check for that is good enough: schedule_work ensures the
2556 * correct ordering between hang detection and this work item, and since
2557 * the reset in-progress bit is only ever set by code outside of this
2558 * work we don't need to worry about any other races.
2560 if (i915_reset_in_progress(&dev_priv
->gpu_error
)) {
2561 DRM_DEBUG_DRIVER("resetting chip\n");
2562 kobject_uevent_env(kobj
, KOBJ_CHANGE
, reset_event
);
2565 * In most cases it's guaranteed that we get here with an RPM
2566 * reference held, for example because there is a pending GPU
2567 * request that won't finish until the reset is done. This
2568 * isn't the case at least when we get here by doing a
2569 * simulated reset via debugs, so get an RPM reference.
2571 intel_runtime_pm_get(dev_priv
);
2573 intel_prepare_reset(dev_priv
);
2576 * All state reset _must_ be completed before we update the
2577 * reset counter, for otherwise waiters might miss the reset
2578 * pending state and not properly drop locks, resulting in
2579 * deadlocks with the reset work.
2581 ret
= i915_reset(dev_priv
);
2583 intel_finish_reset(dev_priv
);
2585 intel_runtime_pm_put(dev_priv
);
2588 kobject_uevent_env(kobj
,
2589 KOBJ_CHANGE
, reset_done_event
);
2592 * Note: The wake_up also serves as a memory barrier so that
2593 * waiters see the update value of the reset counter atomic_t.
2595 i915_error_wake_up(dev_priv
, true);
2599 static void i915_report_and_clear_eir(struct drm_i915_private
*dev_priv
)
2601 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
2602 u32 eir
= I915_READ(EIR
);
2608 pr_err("render error detected, EIR: 0x%08x\n", eir
);
2610 i915_get_extra_instdone(dev_priv
, instdone
);
2612 if (IS_G4X(dev_priv
)) {
2613 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
2614 u32 ipeir
= I915_READ(IPEIR_I965
);
2616 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2617 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2618 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2619 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2620 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2621 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2622 I915_WRITE(IPEIR_I965
, ipeir
);
2623 POSTING_READ(IPEIR_I965
);
2625 if (eir
& GM45_ERROR_PAGE_TABLE
) {
2626 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2627 pr_err("page table error\n");
2628 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2629 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2630 POSTING_READ(PGTBL_ER
);
2634 if (!IS_GEN2(dev_priv
)) {
2635 if (eir
& I915_ERROR_PAGE_TABLE
) {
2636 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2637 pr_err("page table error\n");
2638 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2639 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2640 POSTING_READ(PGTBL_ER
);
2644 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
2645 pr_err("memory refresh error:\n");
2646 for_each_pipe(dev_priv
, pipe
)
2647 pr_err("pipe %c stat: 0x%08x\n",
2648 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
2649 /* pipestat has already been acked */
2651 if (eir
& I915_ERROR_INSTRUCTION
) {
2652 pr_err("instruction error\n");
2653 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
2654 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2655 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2656 if (INTEL_GEN(dev_priv
) < 4) {
2657 u32 ipeir
= I915_READ(IPEIR
);
2659 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
2660 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
2661 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
2662 I915_WRITE(IPEIR
, ipeir
);
2663 POSTING_READ(IPEIR
);
2665 u32 ipeir
= I915_READ(IPEIR_I965
);
2667 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2668 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2669 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2670 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2671 I915_WRITE(IPEIR_I965
, ipeir
);
2672 POSTING_READ(IPEIR_I965
);
2676 I915_WRITE(EIR
, eir
);
2678 eir
= I915_READ(EIR
);
2681 * some errors might have become stuck,
2684 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
2685 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
2686 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2691 * i915_handle_error - handle a gpu error
2693 * @engine_mask: mask representing engines that are hung
2694 * Do some basic checking of register state at error time and
2695 * dump it to the syslog. Also call i915_capture_error_state() to make
2696 * sure we get a record and make it available in debugfs. Fire a uevent
2697 * so userspace knows something bad happened (should trigger collection
2698 * of a ring dump etc.).
2700 void i915_handle_error(struct drm_i915_private
*dev_priv
,
2702 const char *fmt
, ...)
2707 va_start(args
, fmt
);
2708 vscnprintf(error_msg
, sizeof(error_msg
), fmt
, args
);
2711 i915_capture_error_state(dev_priv
, engine_mask
, error_msg
);
2712 i915_report_and_clear_eir(dev_priv
);
2715 atomic_or(I915_RESET_IN_PROGRESS_FLAG
,
2716 &dev_priv
->gpu_error
.reset_counter
);
2719 * Wakeup waiting processes so that the reset function
2720 * i915_reset_and_wakeup doesn't deadlock trying to grab
2721 * various locks. By bumping the reset counter first, the woken
2722 * processes will see a reset in progress and back off,
2723 * releasing their locks and then wait for the reset completion.
2724 * We must do this for _all_ gpu waiters that might hold locks
2725 * that the reset work needs to acquire.
2727 * Note: The wake_up serves as the required memory barrier to
2728 * ensure that the waiters see the updated value of the reset
2731 i915_error_wake_up(dev_priv
, false);
2734 i915_reset_and_wakeup(dev_priv
);
2737 /* Called from drm generic code, passed 'crtc' which
2738 * we use as a pipe index
2740 static int i915_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2743 unsigned long irqflags
;
2745 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2746 if (INTEL_INFO(dev
)->gen
>= 4)
2747 i915_enable_pipestat(dev_priv
, pipe
,
2748 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2750 i915_enable_pipestat(dev_priv
, pipe
,
2751 PIPE_VBLANK_INTERRUPT_STATUS
);
2752 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2757 static int ironlake_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2759 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2760 unsigned long irqflags
;
2761 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2762 DE_PIPE_VBLANK(pipe
);
2764 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2765 ilk_enable_display_irq(dev_priv
, bit
);
2766 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2771 static int valleyview_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2773 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2774 unsigned long irqflags
;
2776 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2777 i915_enable_pipestat(dev_priv
, pipe
,
2778 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2779 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2784 static int gen8_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2786 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2787 unsigned long irqflags
;
2789 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2790 bdw_enable_pipe_irq(dev_priv
, pipe
, GEN8_PIPE_VBLANK
);
2791 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2796 /* Called from drm generic code, passed 'crtc' which
2797 * we use as a pipe index
2799 static void i915_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2801 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2802 unsigned long irqflags
;
2804 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2805 i915_disable_pipestat(dev_priv
, pipe
,
2806 PIPE_VBLANK_INTERRUPT_STATUS
|
2807 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2808 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2811 static void ironlake_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2813 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2814 unsigned long irqflags
;
2815 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2816 DE_PIPE_VBLANK(pipe
);
2818 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2819 ilk_disable_display_irq(dev_priv
, bit
);
2820 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2823 static void valleyview_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2825 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2826 unsigned long irqflags
;
2828 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2829 i915_disable_pipestat(dev_priv
, pipe
,
2830 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2831 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2834 static void gen8_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2836 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2837 unsigned long irqflags
;
2839 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2840 bdw_disable_pipe_irq(dev_priv
, pipe
, GEN8_PIPE_VBLANK
);
2841 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2845 ring_idle(struct intel_engine_cs
*engine
, u32 seqno
)
2847 return i915_seqno_passed(seqno
,
2848 READ_ONCE(engine
->last_submitted_seqno
));
2852 ipehr_is_semaphore_wait(struct drm_i915_private
*dev_priv
, u32 ipehr
)
2854 if (INTEL_GEN(dev_priv
) >= 8) {
2855 return (ipehr
>> 23) == 0x1c;
2857 ipehr
&= ~MI_SEMAPHORE_SYNC_MASK
;
2858 return ipehr
== (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
|
2859 MI_SEMAPHORE_REGISTER
);
2863 static struct intel_engine_cs
*
2864 semaphore_wait_to_signaller_ring(struct intel_engine_cs
*engine
, u32 ipehr
,
2867 struct drm_i915_private
*dev_priv
= engine
->i915
;
2868 struct intel_engine_cs
*signaller
;
2870 if (INTEL_GEN(dev_priv
) >= 8) {
2871 for_each_engine(signaller
, dev_priv
) {
2872 if (engine
== signaller
)
2875 if (offset
== signaller
->semaphore
.signal_ggtt
[engine
->id
])
2879 u32 sync_bits
= ipehr
& MI_SEMAPHORE_SYNC_MASK
;
2881 for_each_engine(signaller
, dev_priv
) {
2882 if(engine
== signaller
)
2885 if (sync_bits
== signaller
->semaphore
.mbox
.wait
[engine
->id
])
2890 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2891 engine
->id
, ipehr
, offset
);
2896 static struct intel_engine_cs
*
2897 semaphore_waits_for(struct intel_engine_cs
*engine
, u32
*seqno
)
2899 struct drm_i915_private
*dev_priv
= engine
->i915
;
2900 u32 cmd
, ipehr
, head
;
2905 * This function does not support execlist mode - any attempt to
2906 * proceed further into this function will result in a kernel panic
2907 * when dereferencing ring->buffer, which is not set up in execlist
2910 * The correct way of doing it would be to derive the currently
2911 * executing ring buffer from the current context, which is derived
2912 * from the currently running request. Unfortunately, to get the
2913 * current request we would have to grab the struct_mutex before doing
2914 * anything else, which would be ill-advised since some other thread
2915 * might have grabbed it already and managed to hang itself, causing
2916 * the hang checker to deadlock.
2918 * Therefore, this function does not support execlist mode in its
2919 * current form. Just return NULL and move on.
2921 if (engine
->buffer
== NULL
)
2924 ipehr
= I915_READ(RING_IPEHR(engine
->mmio_base
));
2925 if (!ipehr_is_semaphore_wait(engine
->i915
, ipehr
))
2929 * HEAD is likely pointing to the dword after the actual command,
2930 * so scan backwards until we find the MBOX. But limit it to just 3
2931 * or 4 dwords depending on the semaphore wait command size.
2932 * Note that we don't care about ACTHD here since that might
2933 * point at at batch, and semaphores are always emitted into the
2934 * ringbuffer itself.
2936 head
= I915_READ_HEAD(engine
) & HEAD_ADDR
;
2937 backwards
= (INTEL_GEN(dev_priv
) >= 8) ? 5 : 4;
2939 for (i
= backwards
; i
; --i
) {
2941 * Be paranoid and presume the hw has gone off into the wild -
2942 * our ring is smaller than what the hardware (and hence
2943 * HEAD_ADDR) allows. Also handles wrap-around.
2945 head
&= engine
->buffer
->size
- 1;
2947 /* This here seems to blow up */
2948 cmd
= ioread32(engine
->buffer
->virtual_start
+ head
);
2958 *seqno
= ioread32(engine
->buffer
->virtual_start
+ head
+ 4) + 1;
2959 if (INTEL_GEN(dev_priv
) >= 8) {
2960 offset
= ioread32(engine
->buffer
->virtual_start
+ head
+ 12);
2962 offset
= ioread32(engine
->buffer
->virtual_start
+ head
+ 8);
2964 return semaphore_wait_to_signaller_ring(engine
, ipehr
, offset
);
2967 static int semaphore_passed(struct intel_engine_cs
*engine
)
2969 struct drm_i915_private
*dev_priv
= engine
->i915
;
2970 struct intel_engine_cs
*signaller
;
2973 engine
->hangcheck
.deadlock
++;
2975 signaller
= semaphore_waits_for(engine
, &seqno
);
2976 if (signaller
== NULL
)
2979 /* Prevent pathological recursion due to driver bugs */
2980 if (signaller
->hangcheck
.deadlock
>= I915_NUM_ENGINES
)
2983 if (i915_seqno_passed(signaller
->get_seqno(signaller
), seqno
))
2986 /* cursory check for an unkickable deadlock */
2987 if (I915_READ_CTL(signaller
) & RING_WAIT_SEMAPHORE
&&
2988 semaphore_passed(signaller
) < 0)
2994 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
2996 struct intel_engine_cs
*engine
;
2998 for_each_engine(engine
, dev_priv
)
2999 engine
->hangcheck
.deadlock
= 0;
3002 static bool subunits_stuck(struct intel_engine_cs
*engine
)
3004 u32 instdone
[I915_NUM_INSTDONE_REG
];
3008 if (engine
->id
!= RCS
)
3011 i915_get_extra_instdone(engine
->i915
, instdone
);
3013 /* There might be unstable subunit states even when
3014 * actual head is not moving. Filter out the unstable ones by
3015 * accumulating the undone -> done transitions and only
3016 * consider those as progress.
3019 for (i
= 0; i
< I915_NUM_INSTDONE_REG
; i
++) {
3020 const u32 tmp
= instdone
[i
] | engine
->hangcheck
.instdone
[i
];
3022 if (tmp
!= engine
->hangcheck
.instdone
[i
])
3025 engine
->hangcheck
.instdone
[i
] |= tmp
;
3031 static enum intel_ring_hangcheck_action
3032 head_stuck(struct intel_engine_cs
*engine
, u64 acthd
)
3034 if (acthd
!= engine
->hangcheck
.acthd
) {
3036 /* Clear subunit states on head movement */
3037 memset(engine
->hangcheck
.instdone
, 0,
3038 sizeof(engine
->hangcheck
.instdone
));
3040 return HANGCHECK_ACTIVE
;
3043 if (!subunits_stuck(engine
))
3044 return HANGCHECK_ACTIVE
;
3046 return HANGCHECK_HUNG
;
3049 static enum intel_ring_hangcheck_action
3050 ring_stuck(struct intel_engine_cs
*engine
, u64 acthd
)
3052 struct drm_i915_private
*dev_priv
= engine
->i915
;
3053 enum intel_ring_hangcheck_action ha
;
3056 ha
= head_stuck(engine
, acthd
);
3057 if (ha
!= HANGCHECK_HUNG
)
3060 if (IS_GEN2(dev_priv
))
3061 return HANGCHECK_HUNG
;
3063 /* Is the chip hanging on a WAIT_FOR_EVENT?
3064 * If so we can simply poke the RB_WAIT bit
3065 * and break the hang. This should work on
3066 * all but the second generation chipsets.
3068 tmp
= I915_READ_CTL(engine
);
3069 if (tmp
& RING_WAIT
) {
3070 i915_handle_error(dev_priv
, 0,
3071 "Kicking stuck wait on %s",
3073 I915_WRITE_CTL(engine
, tmp
);
3074 return HANGCHECK_KICK
;
3077 if (INTEL_GEN(dev_priv
) >= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
3078 switch (semaphore_passed(engine
)) {
3080 return HANGCHECK_HUNG
;
3082 i915_handle_error(dev_priv
, 0,
3083 "Kicking stuck semaphore on %s",
3085 I915_WRITE_CTL(engine
, tmp
);
3086 return HANGCHECK_KICK
;
3088 return HANGCHECK_WAIT
;
3092 return HANGCHECK_HUNG
;
3095 static unsigned kick_waiters(struct intel_engine_cs
*engine
)
3097 struct drm_i915_private
*i915
= engine
->i915
;
3098 unsigned user_interrupts
= READ_ONCE(engine
->user_interrupts
);
3100 if (engine
->hangcheck
.user_interrupts
== user_interrupts
&&
3101 !test_and_set_bit(engine
->id
, &i915
->gpu_error
.missed_irq_rings
)) {
3102 if (!(i915
->gpu_error
.test_irq_rings
& intel_engine_flag(engine
)))
3103 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
3106 DRM_INFO("Fake missed irq on %s\n",
3108 wake_up_all(&engine
->irq_queue
);
3111 return user_interrupts
;
3114 * This is called when the chip hasn't reported back with completed
3115 * batchbuffers in a long time. We keep track per ring seqno progress and
3116 * if there are no progress, hangcheck score for that ring is increased.
3117 * Further, acthd is inspected to see if the ring is stuck. On stuck case
3118 * we kick the ring. If we see no progress on three subsequent calls
3119 * we assume chip is wedged and try to fix it by resetting the chip.
3121 static void i915_hangcheck_elapsed(struct work_struct
*work
)
3123 struct drm_i915_private
*dev_priv
=
3124 container_of(work
, typeof(*dev_priv
),
3125 gpu_error
.hangcheck_work
.work
);
3126 struct intel_engine_cs
*engine
;
3127 enum intel_engine_id id
;
3128 int busy_count
= 0, rings_hung
= 0;
3129 bool stuck
[I915_NUM_ENGINES
] = { 0 };
3133 #define ACTIVE_DECAY 15
3135 if (!i915
.enable_hangcheck
)
3139 * The hangcheck work is synced during runtime suspend, we don't
3140 * require a wakeref. TODO: instead of disabling the asserts make
3141 * sure that we hold a reference when this work is running.
3143 DISABLE_RPM_WAKEREF_ASSERTS(dev_priv
);
3145 /* As enabling the GPU requires fairly extensive mmio access,
3146 * periodically arm the mmio checker to see if we are triggering
3147 * any invalid access.
3149 intel_uncore_arm_unclaimed_mmio_detection(dev_priv
);
3151 for_each_engine_id(engine
, dev_priv
, id
) {
3154 unsigned user_interrupts
;
3157 semaphore_clear_deadlocks(dev_priv
);
3159 /* We don't strictly need an irq-barrier here, as we are not
3160 * serving an interrupt request, be paranoid in case the
3161 * barrier has side-effects (such as preventing a broken
3162 * cacheline snoop) and so be sure that we can see the seqno
3163 * advance. If the seqno should stick, due to a stale
3164 * cacheline, we would erroneously declare the GPU hung.
3166 if (engine
->irq_seqno_barrier
)
3167 engine
->irq_seqno_barrier(engine
);
3169 acthd
= intel_ring_get_active_head(engine
);
3170 seqno
= engine
->get_seqno(engine
);
3172 /* Reset stuck interrupts between batch advances */
3173 user_interrupts
= 0;
3175 if (engine
->hangcheck
.seqno
== seqno
) {
3176 if (ring_idle(engine
, seqno
)) {
3177 engine
->hangcheck
.action
= HANGCHECK_IDLE
;
3178 if (waitqueue_active(&engine
->irq_queue
)) {
3179 /* Safeguard against driver failure */
3180 user_interrupts
= kick_waiters(engine
);
3181 engine
->hangcheck
.score
+= BUSY
;
3185 /* We always increment the hangcheck score
3186 * if the ring is busy and still processing
3187 * the same request, so that no single request
3188 * can run indefinitely (such as a chain of
3189 * batches). The only time we do not increment
3190 * the hangcheck score on this ring, if this
3191 * ring is in a legitimate wait for another
3192 * ring. In that case the waiting ring is a
3193 * victim and we want to be sure we catch the
3194 * right culprit. Then every time we do kick
3195 * the ring, add a small increment to the
3196 * score so that we can catch a batch that is
3197 * being repeatedly kicked and so responsible
3198 * for stalling the machine.
3200 engine
->hangcheck
.action
= ring_stuck(engine
,
3203 switch (engine
->hangcheck
.action
) {
3204 case HANGCHECK_IDLE
:
3205 case HANGCHECK_WAIT
:
3207 case HANGCHECK_ACTIVE
:
3208 engine
->hangcheck
.score
+= BUSY
;
3210 case HANGCHECK_KICK
:
3211 engine
->hangcheck
.score
+= KICK
;
3213 case HANGCHECK_HUNG
:
3214 engine
->hangcheck
.score
+= HUNG
;
3220 engine
->hangcheck
.action
= HANGCHECK_ACTIVE
;
3222 /* Gradually reduce the count so that we catch DoS
3223 * attempts across multiple batches.
3225 if (engine
->hangcheck
.score
> 0)
3226 engine
->hangcheck
.score
-= ACTIVE_DECAY
;
3227 if (engine
->hangcheck
.score
< 0)
3228 engine
->hangcheck
.score
= 0;
3230 /* Clear head and subunit states on seqno movement */
3233 memset(engine
->hangcheck
.instdone
, 0,
3234 sizeof(engine
->hangcheck
.instdone
));
3237 engine
->hangcheck
.seqno
= seqno
;
3238 engine
->hangcheck
.acthd
= acthd
;
3239 engine
->hangcheck
.user_interrupts
= user_interrupts
;
3243 for_each_engine_id(engine
, dev_priv
, id
) {
3244 if (engine
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
) {
3245 DRM_INFO("%s on %s\n",
3246 stuck
[id
] ? "stuck" : "no progress",
3248 rings_hung
|= intel_engine_flag(engine
);
3253 i915_handle_error(dev_priv
, rings_hung
, "Engine(s) hung");
3258 /* Reset timer case chip hangs without another request
3260 i915_queue_hangcheck(dev_priv
);
3263 ENABLE_RPM_WAKEREF_ASSERTS(dev_priv
);
3266 void i915_queue_hangcheck(struct drm_i915_private
*dev_priv
)
3268 struct i915_gpu_error
*e
= &dev_priv
->gpu_error
;
3270 if (!i915
.enable_hangcheck
)
3273 /* Don't continually defer the hangcheck so that it is always run at
3274 * least once after work has been scheduled on any ring. Otherwise,
3275 * we will ignore a hung ring if a second ring is kept busy.
3278 queue_delayed_work(e
->hangcheck_wq
, &e
->hangcheck_work
,
3279 round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES
));
3282 static void ibx_irq_reset(struct drm_device
*dev
)
3284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3286 if (HAS_PCH_NOP(dev
))
3289 GEN5_IRQ_RESET(SDE
);
3291 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
3292 I915_WRITE(SERR_INT
, 0xffffffff);
3296 * SDEIER is also touched by the interrupt handler to work around missed PCH
3297 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3298 * instead we unconditionally enable all PCH interrupt sources here, but then
3299 * only unmask them as needed with SDEIMR.
3301 * This function needs to be called before interrupts are enabled.
3303 static void ibx_irq_pre_postinstall(struct drm_device
*dev
)
3305 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3307 if (HAS_PCH_NOP(dev
))
3310 WARN_ON(I915_READ(SDEIER
) != 0);
3311 I915_WRITE(SDEIER
, 0xffffffff);
3312 POSTING_READ(SDEIER
);
3315 static void gen5_gt_irq_reset(struct drm_device
*dev
)
3317 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3320 if (INTEL_INFO(dev
)->gen
>= 6)
3321 GEN5_IRQ_RESET(GEN6_PM
);
3324 static void vlv_display_irq_reset(struct drm_i915_private
*dev_priv
)
3328 if (IS_CHERRYVIEW(dev_priv
))
3329 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK_CHV
);
3331 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
3333 i915_hotplug_interrupt_update_locked(dev_priv
, 0xffffffff, 0);
3334 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3336 for_each_pipe(dev_priv
, pipe
) {
3337 I915_WRITE(PIPESTAT(pipe
),
3338 PIPE_FIFO_UNDERRUN_STATUS
|
3339 PIPESTAT_INT_STATUS_MASK
);
3340 dev_priv
->pipestat_irq_mask
[pipe
] = 0;
3343 GEN5_IRQ_RESET(VLV_
);
3344 dev_priv
->irq_mask
= ~0;
3347 static void vlv_display_irq_postinstall(struct drm_i915_private
*dev_priv
)
3353 pipestat_mask
= PLANE_FLIP_DONE_INT_STATUS_VLV
|
3354 PIPE_CRC_DONE_INTERRUPT_STATUS
;
3356 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
3357 for_each_pipe(dev_priv
, pipe
)
3358 i915_enable_pipestat(dev_priv
, pipe
, pipestat_mask
);
3360 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
|
3361 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3362 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
3363 if (IS_CHERRYVIEW(dev_priv
))
3364 enable_mask
|= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
3366 WARN_ON(dev_priv
->irq_mask
!= ~0);
3368 dev_priv
->irq_mask
= ~enable_mask
;
3370 GEN5_IRQ_INIT(VLV_
, dev_priv
->irq_mask
, enable_mask
);
3375 static void ironlake_irq_reset(struct drm_device
*dev
)
3377 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3379 I915_WRITE(HWSTAM
, 0xffffffff);
3383 I915_WRITE(GEN7_ERR_INT
, 0xffffffff);
3385 gen5_gt_irq_reset(dev
);
3390 static void valleyview_irq_preinstall(struct drm_device
*dev
)
3392 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3394 I915_WRITE(VLV_MASTER_IER
, 0);
3395 POSTING_READ(VLV_MASTER_IER
);
3397 gen5_gt_irq_reset(dev
);
3399 spin_lock_irq(&dev_priv
->irq_lock
);
3400 if (dev_priv
->display_irqs_enabled
)
3401 vlv_display_irq_reset(dev_priv
);
3402 spin_unlock_irq(&dev_priv
->irq_lock
);
3405 static void gen8_gt_irq_reset(struct drm_i915_private
*dev_priv
)
3407 GEN8_IRQ_RESET_NDX(GT
, 0);
3408 GEN8_IRQ_RESET_NDX(GT
, 1);
3409 GEN8_IRQ_RESET_NDX(GT
, 2);
3410 GEN8_IRQ_RESET_NDX(GT
, 3);
3413 static void gen8_irq_reset(struct drm_device
*dev
)
3415 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3418 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3419 POSTING_READ(GEN8_MASTER_IRQ
);
3421 gen8_gt_irq_reset(dev_priv
);
3423 for_each_pipe(dev_priv
, pipe
)
3424 if (intel_display_power_is_enabled(dev_priv
,
3425 POWER_DOMAIN_PIPE(pipe
)))
3426 GEN8_IRQ_RESET_NDX(DE_PIPE
, pipe
);
3428 GEN5_IRQ_RESET(GEN8_DE_PORT_
);
3429 GEN5_IRQ_RESET(GEN8_DE_MISC_
);
3430 GEN5_IRQ_RESET(GEN8_PCU_
);
3432 if (HAS_PCH_SPLIT(dev
))
3436 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
,
3437 unsigned int pipe_mask
)
3439 uint32_t extra_ier
= GEN8_PIPE_VBLANK
| GEN8_PIPE_FIFO_UNDERRUN
;
3442 spin_lock_irq(&dev_priv
->irq_lock
);
3443 for_each_pipe_masked(dev_priv
, pipe
, pipe_mask
)
3444 GEN8_IRQ_INIT_NDX(DE_PIPE
, pipe
,
3445 dev_priv
->de_irq_mask
[pipe
],
3446 ~dev_priv
->de_irq_mask
[pipe
] | extra_ier
);
3447 spin_unlock_irq(&dev_priv
->irq_lock
);
3450 void gen8_irq_power_well_pre_disable(struct drm_i915_private
*dev_priv
,
3451 unsigned int pipe_mask
)
3455 spin_lock_irq(&dev_priv
->irq_lock
);
3456 for_each_pipe_masked(dev_priv
, pipe
, pipe_mask
)
3457 GEN8_IRQ_RESET_NDX(DE_PIPE
, pipe
);
3458 spin_unlock_irq(&dev_priv
->irq_lock
);
3460 /* make sure we're done processing display irqs */
3461 synchronize_irq(dev_priv
->dev
->irq
);
3464 static void cherryview_irq_preinstall(struct drm_device
*dev
)
3466 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3468 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3469 POSTING_READ(GEN8_MASTER_IRQ
);
3471 gen8_gt_irq_reset(dev_priv
);
3473 GEN5_IRQ_RESET(GEN8_PCU_
);
3475 spin_lock_irq(&dev_priv
->irq_lock
);
3476 if (dev_priv
->display_irqs_enabled
)
3477 vlv_display_irq_reset(dev_priv
);
3478 spin_unlock_irq(&dev_priv
->irq_lock
);
3481 static u32
intel_hpd_enabled_irqs(struct drm_i915_private
*dev_priv
,
3482 const u32 hpd
[HPD_NUM_PINS
])
3484 struct intel_encoder
*encoder
;
3485 u32 enabled_irqs
= 0;
3487 for_each_intel_encoder(dev_priv
->dev
, encoder
)
3488 if (dev_priv
->hotplug
.stats
[encoder
->hpd_pin
].state
== HPD_ENABLED
)
3489 enabled_irqs
|= hpd
[encoder
->hpd_pin
];
3491 return enabled_irqs
;
3494 static void ibx_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3496 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3498 if (HAS_PCH_IBX(dev_priv
)) {
3499 hotplug_irqs
= SDE_HOTPLUG_MASK
;
3500 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_ibx
);
3502 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
3503 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_cpt
);
3506 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
3509 * Enable digital hotplug on the PCH, and configure the DP short pulse
3510 * duration to 2ms (which is the minimum in the Display Port spec).
3511 * The pulse duration bits are reserved on LPT+.
3513 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3514 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
3515 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
3516 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
3517 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
3519 * When CPU and PCH are on the same package, port A
3520 * HPD must be enabled in both north and south.
3522 if (HAS_PCH_LPT_LP(dev_priv
))
3523 hotplug
|= PORTA_HOTPLUG_ENABLE
;
3524 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3527 static void spt_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3529 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3531 hotplug_irqs
= SDE_HOTPLUG_MASK_SPT
;
3532 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_spt
);
3534 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
3536 /* Enable digital hotplug on the PCH */
3537 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3538 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTC_HOTPLUG_ENABLE
|
3539 PORTB_HOTPLUG_ENABLE
| PORTA_HOTPLUG_ENABLE
;
3540 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3542 hotplug
= I915_READ(PCH_PORT_HOTPLUG2
);
3543 hotplug
|= PORTE_HOTPLUG_ENABLE
;
3544 I915_WRITE(PCH_PORT_HOTPLUG2
, hotplug
);
3547 static void ilk_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3549 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3551 if (INTEL_GEN(dev_priv
) >= 8) {
3552 hotplug_irqs
= GEN8_PORT_DP_A_HOTPLUG
;
3553 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_bdw
);
3555 bdw_update_port_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3556 } else if (INTEL_GEN(dev_priv
) >= 7) {
3557 hotplug_irqs
= DE_DP_A_HOTPLUG_IVB
;
3558 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_ivb
);
3560 ilk_update_display_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3562 hotplug_irqs
= DE_DP_A_HOTPLUG
;
3563 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_ilk
);
3565 ilk_update_display_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3569 * Enable digital hotplug on the CPU, and configure the DP short pulse
3570 * duration to 2ms (which is the minimum in the Display Port spec)
3571 * The pulse duration bits are reserved on HSW+.
3573 hotplug
= I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL
);
3574 hotplug
&= ~DIGITAL_PORTA_PULSE_DURATION_MASK
;
3575 hotplug
|= DIGITAL_PORTA_HOTPLUG_ENABLE
| DIGITAL_PORTA_PULSE_DURATION_2ms
;
3576 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL
, hotplug
);
3578 ibx_hpd_irq_setup(dev_priv
);
3581 static void bxt_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3583 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3585 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_bxt
);
3586 hotplug_irqs
= BXT_DE_PORT_HOTPLUG_MASK
;
3588 bdw_update_port_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3590 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3591 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTB_HOTPLUG_ENABLE
|
3592 PORTA_HOTPLUG_ENABLE
;
3594 DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3595 hotplug
, enabled_irqs
);
3596 hotplug
&= ~BXT_DDI_HPD_INVERT_MASK
;
3599 * For BXT invert bit has to be set based on AOB design
3600 * for HPD detection logic, update it based on VBT fields.
3603 if ((enabled_irqs
& BXT_DE_PORT_HP_DDIA
) &&
3604 intel_bios_is_port_hpd_inverted(dev_priv
, PORT_A
))
3605 hotplug
|= BXT_DDIA_HPD_INVERT
;
3606 if ((enabled_irqs
& BXT_DE_PORT_HP_DDIB
) &&
3607 intel_bios_is_port_hpd_inverted(dev_priv
, PORT_B
))
3608 hotplug
|= BXT_DDIB_HPD_INVERT
;
3609 if ((enabled_irqs
& BXT_DE_PORT_HP_DDIC
) &&
3610 intel_bios_is_port_hpd_inverted(dev_priv
, PORT_C
))
3611 hotplug
|= BXT_DDIC_HPD_INVERT
;
3613 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3616 static void ibx_irq_postinstall(struct drm_device
*dev
)
3618 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3621 if (HAS_PCH_NOP(dev
))
3624 if (HAS_PCH_IBX(dev
))
3625 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_POISON
;
3627 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
;
3629 gen5_assert_iir_is_zero(dev_priv
, SDEIIR
);
3630 I915_WRITE(SDEIMR
, ~mask
);
3633 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
3635 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3636 u32 pm_irqs
, gt_irqs
;
3638 pm_irqs
= gt_irqs
= 0;
3640 dev_priv
->gt_irq_mask
= ~0;
3641 if (HAS_L3_DPF(dev
)) {
3642 /* L3 parity interrupt is always unmasked. */
3643 dev_priv
->gt_irq_mask
= ~GT_PARITY_ERROR(dev
);
3644 gt_irqs
|= GT_PARITY_ERROR(dev
);
3647 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
3649 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
3650 ILK_BSD_USER_INTERRUPT
;
3652 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
3655 GEN5_IRQ_INIT(GT
, dev_priv
->gt_irq_mask
, gt_irqs
);
3657 if (INTEL_INFO(dev
)->gen
>= 6) {
3659 * RPS interrupts will get enabled/disabled on demand when RPS
3660 * itself is enabled/disabled.
3663 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
3665 dev_priv
->pm_irq_mask
= 0xffffffff;
3666 GEN5_IRQ_INIT(GEN6_PM
, dev_priv
->pm_irq_mask
, pm_irqs
);
3670 static int ironlake_irq_postinstall(struct drm_device
*dev
)
3672 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3673 u32 display_mask
, extra_mask
;
3675 if (INTEL_INFO(dev
)->gen
>= 7) {
3676 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
3677 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
3678 DE_PLANEB_FLIP_DONE_IVB
|
3679 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
);
3680 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
3681 DE_PIPEA_VBLANK_IVB
| DE_ERR_INT_IVB
|
3682 DE_DP_A_HOTPLUG_IVB
);
3684 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
3685 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
3687 DE_PIPEB_CRC_DONE
| DE_PIPEA_CRC_DONE
|
3689 extra_mask
= (DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
|
3690 DE_PIPEB_FIFO_UNDERRUN
| DE_PIPEA_FIFO_UNDERRUN
|
3694 dev_priv
->irq_mask
= ~display_mask
;
3696 I915_WRITE(HWSTAM
, 0xeffe);
3698 ibx_irq_pre_postinstall(dev
);
3700 GEN5_IRQ_INIT(DE
, dev_priv
->irq_mask
, display_mask
| extra_mask
);
3702 gen5_gt_irq_postinstall(dev
);
3704 ibx_irq_postinstall(dev
);
3706 if (IS_IRONLAKE_M(dev
)) {
3707 /* Enable PCU event interrupts
3709 * spinlocking not required here for correctness since interrupt
3710 * setup is guaranteed to run in single-threaded context. But we
3711 * need it to make the assert_spin_locked happy. */
3712 spin_lock_irq(&dev_priv
->irq_lock
);
3713 ilk_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
3714 spin_unlock_irq(&dev_priv
->irq_lock
);
3720 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
)
3722 assert_spin_locked(&dev_priv
->irq_lock
);
3724 if (dev_priv
->display_irqs_enabled
)
3727 dev_priv
->display_irqs_enabled
= true;
3729 if (intel_irqs_enabled(dev_priv
)) {
3730 vlv_display_irq_reset(dev_priv
);
3731 vlv_display_irq_postinstall(dev_priv
);
3735 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
)
3737 assert_spin_locked(&dev_priv
->irq_lock
);
3739 if (!dev_priv
->display_irqs_enabled
)
3742 dev_priv
->display_irqs_enabled
= false;
3744 if (intel_irqs_enabled(dev_priv
))
3745 vlv_display_irq_reset(dev_priv
);
3749 static int valleyview_irq_postinstall(struct drm_device
*dev
)
3751 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3753 gen5_gt_irq_postinstall(dev
);
3755 spin_lock_irq(&dev_priv
->irq_lock
);
3756 if (dev_priv
->display_irqs_enabled
)
3757 vlv_display_irq_postinstall(dev_priv
);
3758 spin_unlock_irq(&dev_priv
->irq_lock
);
3760 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
3761 POSTING_READ(VLV_MASTER_IER
);
3766 static void gen8_gt_irq_postinstall(struct drm_i915_private
*dev_priv
)
3768 /* These are interrupts we'll toggle with the ring mask register */
3769 uint32_t gt_interrupts
[] = {
3770 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3771 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3772 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
|
3773 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
,
3774 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3775 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3776 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
|
3777 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
,
3779 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
|
3780 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
3783 if (HAS_L3_DPF(dev_priv
))
3784 gt_interrupts
[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
3786 dev_priv
->pm_irq_mask
= 0xffffffff;
3787 GEN8_IRQ_INIT_NDX(GT
, 0, ~gt_interrupts
[0], gt_interrupts
[0]);
3788 GEN8_IRQ_INIT_NDX(GT
, 1, ~gt_interrupts
[1], gt_interrupts
[1]);
3790 * RPS interrupts will get enabled/disabled on demand when RPS itself
3791 * is enabled/disabled.
3793 GEN8_IRQ_INIT_NDX(GT
, 2, dev_priv
->pm_irq_mask
, 0);
3794 GEN8_IRQ_INIT_NDX(GT
, 3, ~gt_interrupts
[3], gt_interrupts
[3]);
3797 static void gen8_de_irq_postinstall(struct drm_i915_private
*dev_priv
)
3799 uint32_t de_pipe_masked
= GEN8_PIPE_CDCLK_CRC_DONE
;
3800 uint32_t de_pipe_enables
;
3801 u32 de_port_masked
= GEN8_AUX_CHANNEL_A
;
3802 u32 de_port_enables
;
3805 if (INTEL_INFO(dev_priv
)->gen
>= 9) {
3806 de_pipe_masked
|= GEN9_PIPE_PLANE1_FLIP_DONE
|
3807 GEN9_DE_PIPE_IRQ_FAULT_ERRORS
;
3808 de_port_masked
|= GEN9_AUX_CHANNEL_B
| GEN9_AUX_CHANNEL_C
|
3810 if (IS_BROXTON(dev_priv
))
3811 de_port_masked
|= BXT_DE_PORT_GMBUS
;
3813 de_pipe_masked
|= GEN8_PIPE_PRIMARY_FLIP_DONE
|
3814 GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
3817 de_pipe_enables
= de_pipe_masked
| GEN8_PIPE_VBLANK
|
3818 GEN8_PIPE_FIFO_UNDERRUN
;
3820 de_port_enables
= de_port_masked
;
3821 if (IS_BROXTON(dev_priv
))
3822 de_port_enables
|= BXT_DE_PORT_HOTPLUG_MASK
;
3823 else if (IS_BROADWELL(dev_priv
))
3824 de_port_enables
|= GEN8_PORT_DP_A_HOTPLUG
;
3826 dev_priv
->de_irq_mask
[PIPE_A
] = ~de_pipe_masked
;
3827 dev_priv
->de_irq_mask
[PIPE_B
] = ~de_pipe_masked
;
3828 dev_priv
->de_irq_mask
[PIPE_C
] = ~de_pipe_masked
;
3830 for_each_pipe(dev_priv
, pipe
)
3831 if (intel_display_power_is_enabled(dev_priv
,
3832 POWER_DOMAIN_PIPE(pipe
)))
3833 GEN8_IRQ_INIT_NDX(DE_PIPE
, pipe
,
3834 dev_priv
->de_irq_mask
[pipe
],
3837 GEN5_IRQ_INIT(GEN8_DE_PORT_
, ~de_port_masked
, de_port_enables
);
3840 static int gen8_irq_postinstall(struct drm_device
*dev
)
3842 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3844 if (HAS_PCH_SPLIT(dev
))
3845 ibx_irq_pre_postinstall(dev
);
3847 gen8_gt_irq_postinstall(dev_priv
);
3848 gen8_de_irq_postinstall(dev_priv
);
3850 if (HAS_PCH_SPLIT(dev
))
3851 ibx_irq_postinstall(dev
);
3853 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
3854 POSTING_READ(GEN8_MASTER_IRQ
);
3859 static int cherryview_irq_postinstall(struct drm_device
*dev
)
3861 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3863 gen8_gt_irq_postinstall(dev_priv
);
3865 spin_lock_irq(&dev_priv
->irq_lock
);
3866 if (dev_priv
->display_irqs_enabled
)
3867 vlv_display_irq_postinstall(dev_priv
);
3868 spin_unlock_irq(&dev_priv
->irq_lock
);
3870 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
3871 POSTING_READ(GEN8_MASTER_IRQ
);
3876 static void gen8_irq_uninstall(struct drm_device
*dev
)
3878 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3883 gen8_irq_reset(dev
);
3886 static void valleyview_irq_uninstall(struct drm_device
*dev
)
3888 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3893 I915_WRITE(VLV_MASTER_IER
, 0);
3894 POSTING_READ(VLV_MASTER_IER
);
3896 gen5_gt_irq_reset(dev
);
3898 I915_WRITE(HWSTAM
, 0xffffffff);
3900 spin_lock_irq(&dev_priv
->irq_lock
);
3901 if (dev_priv
->display_irqs_enabled
)
3902 vlv_display_irq_reset(dev_priv
);
3903 spin_unlock_irq(&dev_priv
->irq_lock
);
3906 static void cherryview_irq_uninstall(struct drm_device
*dev
)
3908 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3913 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3914 POSTING_READ(GEN8_MASTER_IRQ
);
3916 gen8_gt_irq_reset(dev_priv
);
3918 GEN5_IRQ_RESET(GEN8_PCU_
);
3920 spin_lock_irq(&dev_priv
->irq_lock
);
3921 if (dev_priv
->display_irqs_enabled
)
3922 vlv_display_irq_reset(dev_priv
);
3923 spin_unlock_irq(&dev_priv
->irq_lock
);
3926 static void ironlake_irq_uninstall(struct drm_device
*dev
)
3928 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3933 ironlake_irq_reset(dev
);
3936 static void i8xx_irq_preinstall(struct drm_device
* dev
)
3938 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3941 for_each_pipe(dev_priv
, pipe
)
3942 I915_WRITE(PIPESTAT(pipe
), 0);
3943 I915_WRITE16(IMR
, 0xffff);
3944 I915_WRITE16(IER
, 0x0);
3945 POSTING_READ16(IER
);
3948 static int i8xx_irq_postinstall(struct drm_device
*dev
)
3950 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3953 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3955 /* Unmask the interrupts that we always want on. */
3956 dev_priv
->irq_mask
=
3957 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3958 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3959 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3960 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
3961 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
3964 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3965 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3966 I915_USER_INTERRUPT
);
3967 POSTING_READ16(IER
);
3969 /* Interrupt setup is already guaranteed to be single-threaded, this is
3970 * just to make the assert_spin_locked check happy. */
3971 spin_lock_irq(&dev_priv
->irq_lock
);
3972 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3973 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3974 spin_unlock_irq(&dev_priv
->irq_lock
);
3980 * Returns true when a page flip has completed.
3982 static bool i8xx_handle_vblank(struct drm_i915_private
*dev_priv
,
3983 int plane
, int pipe
, u32 iir
)
3985 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3987 if (!intel_pipe_handle_vblank(dev_priv
, pipe
))
3990 if ((iir
& flip_pending
) == 0)
3991 goto check_page_flip
;
3993 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3994 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3995 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3996 * the flip is completed (no longer pending). Since this doesn't raise
3997 * an interrupt per se, we watch for the change at vblank.
3999 if (I915_READ16(ISR
) & flip_pending
)
4000 goto check_page_flip
;
4002 intel_prepare_page_flip(dev_priv
, plane
);
4003 intel_finish_page_flip(dev_priv
, pipe
);
4007 intel_check_page_flip(dev_priv
, pipe
);
4011 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
4013 struct drm_device
*dev
= arg
;
4014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4019 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4020 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
4023 if (!intel_irqs_enabled(dev_priv
))
4026 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4027 disable_rpm_wakeref_asserts(dev_priv
);
4030 iir
= I915_READ16(IIR
);
4034 while (iir
& ~flip_mask
) {
4035 /* Can't rely on pipestat interrupt bit in iir as it might
4036 * have been cleared after the pipestat interrupt was received.
4037 * It doesn't set the bit in iir again, but it still produces
4038 * interrupts (for non-MSI).
4040 spin_lock(&dev_priv
->irq_lock
);
4041 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
4042 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
4044 for_each_pipe(dev_priv
, pipe
) {
4045 i915_reg_t reg
= PIPESTAT(pipe
);
4046 pipe_stats
[pipe
] = I915_READ(reg
);
4049 * Clear the PIPE*STAT regs before the IIR
4051 if (pipe_stats
[pipe
] & 0x8000ffff)
4052 I915_WRITE(reg
, pipe_stats
[pipe
]);
4054 spin_unlock(&dev_priv
->irq_lock
);
4056 I915_WRITE16(IIR
, iir
& ~flip_mask
);
4057 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
4059 if (iir
& I915_USER_INTERRUPT
)
4060 notify_ring(&dev_priv
->engine
[RCS
]);
4062 for_each_pipe(dev_priv
, pipe
) {
4064 if (HAS_FBC(dev_priv
))
4067 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
4068 i8xx_handle_vblank(dev_priv
, plane
, pipe
, iir
))
4069 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
4071 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
4072 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
4074 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
4075 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
4084 enable_rpm_wakeref_asserts(dev_priv
);
4089 static void i8xx_irq_uninstall(struct drm_device
* dev
)
4091 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4094 for_each_pipe(dev_priv
, pipe
) {
4095 /* Clear enable bits; then clear status bits */
4096 I915_WRITE(PIPESTAT(pipe
), 0);
4097 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
4099 I915_WRITE16(IMR
, 0xffff);
4100 I915_WRITE16(IER
, 0x0);
4101 I915_WRITE16(IIR
, I915_READ16(IIR
));
4104 static void i915_irq_preinstall(struct drm_device
* dev
)
4106 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4109 if (I915_HAS_HOTPLUG(dev
)) {
4110 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4111 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4114 I915_WRITE16(HWSTAM
, 0xeffe);
4115 for_each_pipe(dev_priv
, pipe
)
4116 I915_WRITE(PIPESTAT(pipe
), 0);
4117 I915_WRITE(IMR
, 0xffffffff);
4118 I915_WRITE(IER
, 0x0);
4122 static int i915_irq_postinstall(struct drm_device
*dev
)
4124 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4127 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
4129 /* Unmask the interrupts that we always want on. */
4130 dev_priv
->irq_mask
=
4131 ~(I915_ASLE_INTERRUPT
|
4132 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
4133 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
4134 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4135 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
4138 I915_ASLE_INTERRUPT
|
4139 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
4140 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
4141 I915_USER_INTERRUPT
;
4143 if (I915_HAS_HOTPLUG(dev
)) {
4144 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4145 POSTING_READ(PORT_HOTPLUG_EN
);
4147 /* Enable in IER... */
4148 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
4149 /* and unmask in IMR */
4150 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
4153 I915_WRITE(IMR
, dev_priv
->irq_mask
);
4154 I915_WRITE(IER
, enable_mask
);
4157 i915_enable_asle_pipestat(dev_priv
);
4159 /* Interrupt setup is already guaranteed to be single-threaded, this is
4160 * just to make the assert_spin_locked check happy. */
4161 spin_lock_irq(&dev_priv
->irq_lock
);
4162 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4163 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4164 spin_unlock_irq(&dev_priv
->irq_lock
);
4170 * Returns true when a page flip has completed.
4172 static bool i915_handle_vblank(struct drm_i915_private
*dev_priv
,
4173 int plane
, int pipe
, u32 iir
)
4175 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
4177 if (!intel_pipe_handle_vblank(dev_priv
, pipe
))
4180 if ((iir
& flip_pending
) == 0)
4181 goto check_page_flip
;
4183 /* We detect FlipDone by looking for the change in PendingFlip from '1'
4184 * to '0' on the following vblank, i.e. IIR has the Pendingflip
4185 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4186 * the flip is completed (no longer pending). Since this doesn't raise
4187 * an interrupt per se, we watch for the change at vblank.
4189 if (I915_READ(ISR
) & flip_pending
)
4190 goto check_page_flip
;
4192 intel_prepare_page_flip(dev_priv
, plane
);
4193 intel_finish_page_flip(dev_priv
, pipe
);
4197 intel_check_page_flip(dev_priv
, pipe
);
4201 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
4203 struct drm_device
*dev
= arg
;
4204 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4205 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
4207 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4208 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
4209 int pipe
, ret
= IRQ_NONE
;
4211 if (!intel_irqs_enabled(dev_priv
))
4214 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4215 disable_rpm_wakeref_asserts(dev_priv
);
4217 iir
= I915_READ(IIR
);
4219 bool irq_received
= (iir
& ~flip_mask
) != 0;
4220 bool blc_event
= false;
4222 /* Can't rely on pipestat interrupt bit in iir as it might
4223 * have been cleared after the pipestat interrupt was received.
4224 * It doesn't set the bit in iir again, but it still produces
4225 * interrupts (for non-MSI).
4227 spin_lock(&dev_priv
->irq_lock
);
4228 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
4229 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
4231 for_each_pipe(dev_priv
, pipe
) {
4232 i915_reg_t reg
= PIPESTAT(pipe
);
4233 pipe_stats
[pipe
] = I915_READ(reg
);
4235 /* Clear the PIPE*STAT regs before the IIR */
4236 if (pipe_stats
[pipe
] & 0x8000ffff) {
4237 I915_WRITE(reg
, pipe_stats
[pipe
]);
4238 irq_received
= true;
4241 spin_unlock(&dev_priv
->irq_lock
);
4246 /* Consume port. Then clear IIR or we'll miss events */
4247 if (I915_HAS_HOTPLUG(dev_priv
) &&
4248 iir
& I915_DISPLAY_PORT_INTERRUPT
) {
4249 u32 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
4251 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
4254 I915_WRITE(IIR
, iir
& ~flip_mask
);
4255 new_iir
= I915_READ(IIR
); /* Flush posted writes */
4257 if (iir
& I915_USER_INTERRUPT
)
4258 notify_ring(&dev_priv
->engine
[RCS
]);
4260 for_each_pipe(dev_priv
, pipe
) {
4262 if (HAS_FBC(dev_priv
))
4265 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
4266 i915_handle_vblank(dev_priv
, plane
, pipe
, iir
))
4267 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
4269 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
4272 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
4273 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
4275 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
4276 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
4280 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
4281 intel_opregion_asle_intr(dev_priv
);
4283 /* With MSI, interrupts are only generated when iir
4284 * transitions from zero to nonzero. If another bit got
4285 * set while we were handling the existing iir bits, then
4286 * we would never get another interrupt.
4288 * This is fine on non-MSI as well, as if we hit this path
4289 * we avoid exiting the interrupt handler only to generate
4292 * Note that for MSI this could cause a stray interrupt report
4293 * if an interrupt landed in the time between writing IIR and
4294 * the posting read. This should be rare enough to never
4295 * trigger the 99% of 100,000 interrupts test for disabling
4300 } while (iir
& ~flip_mask
);
4302 enable_rpm_wakeref_asserts(dev_priv
);
4307 static void i915_irq_uninstall(struct drm_device
* dev
)
4309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4312 if (I915_HAS_HOTPLUG(dev
)) {
4313 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4314 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4317 I915_WRITE16(HWSTAM
, 0xffff);
4318 for_each_pipe(dev_priv
, pipe
) {
4319 /* Clear enable bits; then clear status bits */
4320 I915_WRITE(PIPESTAT(pipe
), 0);
4321 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
4323 I915_WRITE(IMR
, 0xffffffff);
4324 I915_WRITE(IER
, 0x0);
4326 I915_WRITE(IIR
, I915_READ(IIR
));
4329 static void i965_irq_preinstall(struct drm_device
* dev
)
4331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4334 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4335 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4337 I915_WRITE(HWSTAM
, 0xeffe);
4338 for_each_pipe(dev_priv
, pipe
)
4339 I915_WRITE(PIPESTAT(pipe
), 0);
4340 I915_WRITE(IMR
, 0xffffffff);
4341 I915_WRITE(IER
, 0x0);
4345 static int i965_irq_postinstall(struct drm_device
*dev
)
4347 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4351 /* Unmask the interrupts that we always want on. */
4352 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
4353 I915_DISPLAY_PORT_INTERRUPT
|
4354 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
4355 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
4356 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4357 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
4358 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
4360 enable_mask
= ~dev_priv
->irq_mask
;
4361 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4362 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
4363 enable_mask
|= I915_USER_INTERRUPT
;
4365 if (IS_G4X(dev_priv
))
4366 enable_mask
|= I915_BSD_USER_INTERRUPT
;
4368 /* Interrupt setup is already guaranteed to be single-threaded, this is
4369 * just to make the assert_spin_locked check happy. */
4370 spin_lock_irq(&dev_priv
->irq_lock
);
4371 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
4372 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4373 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4374 spin_unlock_irq(&dev_priv
->irq_lock
);
4377 * Enable some error detection, note the instruction error mask
4378 * bit is reserved, so we leave it masked.
4380 if (IS_G4X(dev_priv
)) {
4381 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
4382 GM45_ERROR_MEM_PRIV
|
4383 GM45_ERROR_CP_PRIV
|
4384 I915_ERROR_MEMORY_REFRESH
);
4386 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
4387 I915_ERROR_MEMORY_REFRESH
);
4389 I915_WRITE(EMR
, error_mask
);
4391 I915_WRITE(IMR
, dev_priv
->irq_mask
);
4392 I915_WRITE(IER
, enable_mask
);
4395 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4396 POSTING_READ(PORT_HOTPLUG_EN
);
4398 i915_enable_asle_pipestat(dev_priv
);
4403 static void i915_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
4407 assert_spin_locked(&dev_priv
->irq_lock
);
4409 /* Note HDMI and DP share hotplug bits */
4410 /* enable bits are the same for all generations */
4411 hotplug_en
= intel_hpd_enabled_irqs(dev_priv
, hpd_mask_i915
);
4412 /* Programming the CRT detection parameters tends
4413 to generate a spurious hotplug event about three
4414 seconds later. So just do it once.
4416 if (IS_G4X(dev_priv
))
4417 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
4418 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
4420 /* Ignore TV since it's buggy */
4421 i915_hotplug_interrupt_update_locked(dev_priv
,
4422 HOTPLUG_INT_EN_MASK
|
4423 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
|
4424 CRT_HOTPLUG_ACTIVATION_PERIOD_64
,
4428 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
4430 struct drm_device
*dev
= arg
;
4431 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4433 u32 pipe_stats
[I915_MAX_PIPES
];
4434 int ret
= IRQ_NONE
, pipe
;
4436 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4437 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
4439 if (!intel_irqs_enabled(dev_priv
))
4442 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4443 disable_rpm_wakeref_asserts(dev_priv
);
4445 iir
= I915_READ(IIR
);
4448 bool irq_received
= (iir
& ~flip_mask
) != 0;
4449 bool blc_event
= false;
4451 /* Can't rely on pipestat interrupt bit in iir as it might
4452 * have been cleared after the pipestat interrupt was received.
4453 * It doesn't set the bit in iir again, but it still produces
4454 * interrupts (for non-MSI).
4456 spin_lock(&dev_priv
->irq_lock
);
4457 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
4458 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
4460 for_each_pipe(dev_priv
, pipe
) {
4461 i915_reg_t reg
= PIPESTAT(pipe
);
4462 pipe_stats
[pipe
] = I915_READ(reg
);
4465 * Clear the PIPE*STAT regs before the IIR
4467 if (pipe_stats
[pipe
] & 0x8000ffff) {
4468 I915_WRITE(reg
, pipe_stats
[pipe
]);
4469 irq_received
= true;
4472 spin_unlock(&dev_priv
->irq_lock
);
4479 /* Consume port. Then clear IIR or we'll miss events */
4480 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
4481 u32 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
4483 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
4486 I915_WRITE(IIR
, iir
& ~flip_mask
);
4487 new_iir
= I915_READ(IIR
); /* Flush posted writes */
4489 if (iir
& I915_USER_INTERRUPT
)
4490 notify_ring(&dev_priv
->engine
[RCS
]);
4491 if (iir
& I915_BSD_USER_INTERRUPT
)
4492 notify_ring(&dev_priv
->engine
[VCS
]);
4494 for_each_pipe(dev_priv
, pipe
) {
4495 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
4496 i915_handle_vblank(dev_priv
, pipe
, pipe
, iir
))
4497 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
4499 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
4502 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
4503 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
4505 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
4506 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
4509 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
4510 intel_opregion_asle_intr(dev_priv
);
4512 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
4513 gmbus_irq_handler(dev_priv
);
4515 /* With MSI, interrupts are only generated when iir
4516 * transitions from zero to nonzero. If another bit got
4517 * set while we were handling the existing iir bits, then
4518 * we would never get another interrupt.
4520 * This is fine on non-MSI as well, as if we hit this path
4521 * we avoid exiting the interrupt handler only to generate
4524 * Note that for MSI this could cause a stray interrupt report
4525 * if an interrupt landed in the time between writing IIR and
4526 * the posting read. This should be rare enough to never
4527 * trigger the 99% of 100,000 interrupts test for disabling
4533 enable_rpm_wakeref_asserts(dev_priv
);
4538 static void i965_irq_uninstall(struct drm_device
* dev
)
4540 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4546 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4547 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4549 I915_WRITE(HWSTAM
, 0xffffffff);
4550 for_each_pipe(dev_priv
, pipe
)
4551 I915_WRITE(PIPESTAT(pipe
), 0);
4552 I915_WRITE(IMR
, 0xffffffff);
4553 I915_WRITE(IER
, 0x0);
4555 for_each_pipe(dev_priv
, pipe
)
4556 I915_WRITE(PIPESTAT(pipe
),
4557 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
4558 I915_WRITE(IIR
, I915_READ(IIR
));
4562 * intel_irq_init - initializes irq support
4563 * @dev_priv: i915 device instance
4565 * This function initializes all the irq support including work items, timers
4566 * and all the vtables. It does not setup the interrupt itself though.
4568 void intel_irq_init(struct drm_i915_private
*dev_priv
)
4570 struct drm_device
*dev
= dev_priv
->dev
;
4572 intel_hpd_init_work(dev_priv
);
4574 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
4575 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
4577 /* Let's track the enabled rps events */
4578 if (IS_VALLEYVIEW(dev_priv
))
4579 /* WaGsvRC0ResidencyMethod:vlv */
4580 dev_priv
->pm_rps_events
= GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
;
4582 dev_priv
->pm_rps_events
= GEN6_PM_RPS_EVENTS
;
4584 INIT_DELAYED_WORK(&dev_priv
->gpu_error
.hangcheck_work
,
4585 i915_hangcheck_elapsed
);
4587 if (IS_GEN2(dev_priv
)) {
4588 dev
->max_vblank_count
= 0;
4589 dev
->driver
->get_vblank_counter
= i8xx_get_vblank_counter
;
4590 } else if (IS_G4X(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 5) {
4591 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
4592 dev
->driver
->get_vblank_counter
= g4x_get_vblank_counter
;
4594 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
4595 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
4599 * Opt out of the vblank disable timer on everything except gen2.
4600 * Gen2 doesn't have a hardware frame counter and so depends on
4601 * vblank interrupts to produce sane vblank seuquence numbers.
4603 if (!IS_GEN2(dev_priv
))
4604 dev
->vblank_disable_immediate
= true;
4606 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
4607 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
4609 if (IS_CHERRYVIEW(dev_priv
)) {
4610 dev
->driver
->irq_handler
= cherryview_irq_handler
;
4611 dev
->driver
->irq_preinstall
= cherryview_irq_preinstall
;
4612 dev
->driver
->irq_postinstall
= cherryview_irq_postinstall
;
4613 dev
->driver
->irq_uninstall
= cherryview_irq_uninstall
;
4614 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
4615 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
4616 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4617 } else if (IS_VALLEYVIEW(dev_priv
)) {
4618 dev
->driver
->irq_handler
= valleyview_irq_handler
;
4619 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
4620 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
4621 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
4622 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
4623 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
4624 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4625 } else if (INTEL_INFO(dev_priv
)->gen
>= 8) {
4626 dev
->driver
->irq_handler
= gen8_irq_handler
;
4627 dev
->driver
->irq_preinstall
= gen8_irq_reset
;
4628 dev
->driver
->irq_postinstall
= gen8_irq_postinstall
;
4629 dev
->driver
->irq_uninstall
= gen8_irq_uninstall
;
4630 dev
->driver
->enable_vblank
= gen8_enable_vblank
;
4631 dev
->driver
->disable_vblank
= gen8_disable_vblank
;
4632 if (IS_BROXTON(dev
))
4633 dev_priv
->display
.hpd_irq_setup
= bxt_hpd_irq_setup
;
4634 else if (HAS_PCH_SPT(dev
))
4635 dev_priv
->display
.hpd_irq_setup
= spt_hpd_irq_setup
;
4637 dev_priv
->display
.hpd_irq_setup
= ilk_hpd_irq_setup
;
4638 } else if (HAS_PCH_SPLIT(dev
)) {
4639 dev
->driver
->irq_handler
= ironlake_irq_handler
;
4640 dev
->driver
->irq_preinstall
= ironlake_irq_reset
;
4641 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
4642 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
4643 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
4644 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
4645 dev_priv
->display
.hpd_irq_setup
= ilk_hpd_irq_setup
;
4647 if (INTEL_INFO(dev_priv
)->gen
== 2) {
4648 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
4649 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
4650 dev
->driver
->irq_handler
= i8xx_irq_handler
;
4651 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
4652 } else if (INTEL_INFO(dev_priv
)->gen
== 3) {
4653 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
4654 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
4655 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
4656 dev
->driver
->irq_handler
= i915_irq_handler
;
4658 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
4659 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
4660 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
4661 dev
->driver
->irq_handler
= i965_irq_handler
;
4663 if (I915_HAS_HOTPLUG(dev_priv
))
4664 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4665 dev
->driver
->enable_vblank
= i915_enable_vblank
;
4666 dev
->driver
->disable_vblank
= i915_disable_vblank
;
4671 * intel_irq_install - enables the hardware interrupt
4672 * @dev_priv: i915 device instance
4674 * This function enables the hardware interrupt handling, but leaves the hotplug
4675 * handling still disabled. It is called after intel_irq_init().
4677 * In the driver load and resume code we need working interrupts in a few places
4678 * but don't want to deal with the hassle of concurrent probe and hotplug
4679 * workers. Hence the split into this two-stage approach.
4681 int intel_irq_install(struct drm_i915_private
*dev_priv
)
4684 * We enable some interrupt sources in our postinstall hooks, so mark
4685 * interrupts as enabled _before_ actually enabling them to avoid
4686 * special cases in our ordering checks.
4688 dev_priv
->pm
.irqs_enabled
= true;
4690 return drm_irq_install(dev_priv
->dev
, dev_priv
->dev
->pdev
->irq
);
4694 * intel_irq_uninstall - finilizes all irq handling
4695 * @dev_priv: i915 device instance
4697 * This stops interrupt and hotplug handling and unregisters and frees all
4698 * resources acquired in the init functions.
4700 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
)
4702 drm_irq_uninstall(dev_priv
->dev
);
4703 intel_hpd_cancel_work(dev_priv
);
4704 dev_priv
->pm
.irqs_enabled
= false;
4708 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4709 * @dev_priv: i915 device instance
4711 * This function is used to disable interrupts at runtime, both in the runtime
4712 * pm and the system suspend/resume code.
4714 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
)
4716 dev_priv
->dev
->driver
->irq_uninstall(dev_priv
->dev
);
4717 dev_priv
->pm
.irqs_enabled
= false;
4718 synchronize_irq(dev_priv
->dev
->irq
);
4722 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4723 * @dev_priv: i915 device instance
4725 * This function is used to enable interrupts at runtime, both in the runtime
4726 * pm and the system suspend/resume code.
4728 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
)
4730 dev_priv
->pm
.irqs_enabled
= true;
4731 dev_priv
->dev
->driver
->irq_preinstall(dev_priv
->dev
);
4732 dev_priv
->dev
->driver
->irq_postinstall(dev_priv
->dev
);