projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/i915: Don't touch South Display when PCH_NOP
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <drm/drmP.h>
34 #include <drm/i915_drm.h>
35 #include "i915_drv.h"
36 #include "i915_trace.h"
37 #include "intel_drv.h"
38
39 static const u32 hpd_ibx[] = {
40 [HPD_CRT] = SDE_CRT_HOTPLUG,
41 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
42 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
43 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
44 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
45 };
46
47 static const u32 hpd_cpt[] = {
48 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
49 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
50 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
51 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
52 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
53 };
54
55 static const u32 hpd_mask_i915[] = {
56 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
57 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
58 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
59 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
60 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
61 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
62 };
63
64 static const u32 hpd_status_gen4[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
71 };
72
73 static const u32 hpd_status_i965[] = {
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I965,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I965,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80 };
81
82 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
83 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
84 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
85 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
86 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
87 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
88 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
89 };
90
91
92
93 /* For display hotplug interrupt */
94 static void
95 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
96 {
97 if ((dev_priv->irq_mask & mask) != 0) {
98 dev_priv->irq_mask &= ~mask;
99 I915_WRITE(DEIMR, dev_priv->irq_mask);
100 POSTING_READ(DEIMR);
101 }
102 }
103
104 static void
105 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
106 {
107 if ((dev_priv->irq_mask & mask) != mask) {
108 dev_priv->irq_mask |= mask;
109 I915_WRITE(DEIMR, dev_priv->irq_mask);
110 POSTING_READ(DEIMR);
111 }
112 }
113
114 void
115 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
116 {
117 u32 reg = PIPESTAT(pipe);
118 u32 pipestat = I915_READ(reg) & 0x7fff0000;
119
120 if ((pipestat & mask) == mask)
121 return;
122
123 /* Enable the interrupt, clear any pending status */
124 pipestat |= mask | (mask >> 16);
125 I915_WRITE(reg, pipestat);
126 POSTING_READ(reg);
127 }
128
129 void
130 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
131 {
132 u32 reg = PIPESTAT(pipe);
133 u32 pipestat = I915_READ(reg) & 0x7fff0000;
134
135 if ((pipestat & mask) == 0)
136 return;
137
138 pipestat &= ~mask;
139 I915_WRITE(reg, pipestat);
140 POSTING_READ(reg);
141 }
142
143 /**
144 * intel_enable_asle - enable ASLE interrupt for OpRegion
145 */
146 void intel_enable_asle(struct drm_device *dev)
147 {
148 drm_i915_private_t *dev_priv = dev->dev_private;
149 unsigned long irqflags;
150
151 /* FIXME: opregion/asle for VLV */
152 if (IS_VALLEYVIEW(dev))
153 return;
154
155 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
156
157 if (HAS_PCH_SPLIT(dev))
158 ironlake_enable_display_irq(dev_priv, DE_GSE);
159 else {
160 i915_enable_pipestat(dev_priv, 1,
161 PIPE_LEGACY_BLC_EVENT_ENABLE);
162 if (INTEL_INFO(dev)->gen >= 4)
163 i915_enable_pipestat(dev_priv, 0,
164 PIPE_LEGACY_BLC_EVENT_ENABLE);
165 }
166
167 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
168 }
169
170 /**
171 * i915_pipe_enabled - check if a pipe is enabled
172 * @dev: DRM device
173 * @pipe: pipe to check
174 *
175 * Reading certain registers when the pipe is disabled can hang the chip.
176 * Use this routine to make sure the PLL is running and the pipe is active
177 * before reading such registers if unsure.
178 */
179 static int
180 i915_pipe_enabled(struct drm_device *dev, int pipe)
181 {
182 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
183 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
184 pipe);
185
186 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
187 }
188
189 /* Called from drm generic code, passed a 'crtc', which
190 * we use as a pipe index
191 */
192 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
193 {
194 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
195 unsigned long high_frame;
196 unsigned long low_frame;
197 u32 high1, high2, low;
198
199 if (!i915_pipe_enabled(dev, pipe)) {
200 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
201 "pipe %c\n", pipe_name(pipe));
202 return 0;
203 }
204
205 high_frame = PIPEFRAME(pipe);
206 low_frame = PIPEFRAMEPIXEL(pipe);
207
208 /*
209 * High & low register fields aren't synchronized, so make sure
210 * we get a low value that's stable across two reads of the high
211 * register.
212 */
213 do {
214 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
215 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
216 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
217 } while (high1 != high2);
218
219 high1 >>= PIPE_FRAME_HIGH_SHIFT;
220 low >>= PIPE_FRAME_LOW_SHIFT;
221 return (high1 << 8) | low;
222 }
223
224 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
225 {
226 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
227 int reg = PIPE_FRMCOUNT_GM45(pipe);
228
229 if (!i915_pipe_enabled(dev, pipe)) {
230 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
231 "pipe %c\n", pipe_name(pipe));
232 return 0;
233 }
234
235 return I915_READ(reg);
236 }
237
238 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
239 int *vpos, int *hpos)
240 {
241 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
242 u32 vbl = 0, position = 0;
243 int vbl_start, vbl_end, htotal, vtotal;
244 bool in_vbl = true;
245 int ret = 0;
246 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
247 pipe);
248
249 if (!i915_pipe_enabled(dev, pipe)) {
250 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
251 "pipe %c\n", pipe_name(pipe));
252 return 0;
253 }
254
255 /* Get vtotal. */
256 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
257
258 if (INTEL_INFO(dev)->gen >= 4) {
259 /* No obvious pixelcount register. Only query vertical
260 * scanout position from Display scan line register.
261 */
262 position = I915_READ(PIPEDSL(pipe));
263
264 /* Decode into vertical scanout position. Don't have
265 * horizontal scanout position.
266 */
267 *vpos = position & 0x1fff;
268 *hpos = 0;
269 } else {
270 /* Have access to pixelcount since start of frame.
271 * We can split this into vertical and horizontal
272 * scanout position.
273 */
274 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
275
276 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
277 *vpos = position / htotal;
278 *hpos = position - (*vpos * htotal);
279 }
280
281 /* Query vblank area. */
282 vbl = I915_READ(VBLANK(cpu_transcoder));
283
284 /* Test position against vblank region. */
285 vbl_start = vbl & 0x1fff;
286 vbl_end = (vbl >> 16) & 0x1fff;
287
288 if ((*vpos < vbl_start) || (*vpos > vbl_end))
289 in_vbl = false;
290
291 /* Inside "upper part" of vblank area? Apply corrective offset: */
292 if (in_vbl && (*vpos >= vbl_start))
293 *vpos = *vpos - vtotal;
294
295 /* Readouts valid? */
296 if (vbl > 0)
297 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
298
299 /* In vblank? */
300 if (in_vbl)
301 ret |= DRM_SCANOUTPOS_INVBL;
302
303 return ret;
304 }
305
306 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
307 int *max_error,
308 struct timeval *vblank_time,
309 unsigned flags)
310 {
311 struct drm_crtc *crtc;
312
313 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
314 DRM_ERROR("Invalid crtc %d\n", pipe);
315 return -EINVAL;
316 }
317
318 /* Get drm_crtc to timestamp: */
319 crtc = intel_get_crtc_for_pipe(dev, pipe);
320 if (crtc == NULL) {
321 DRM_ERROR("Invalid crtc %d\n", pipe);
322 return -EINVAL;
323 }
324
325 if (!crtc->enabled) {
326 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
327 return -EBUSY;
328 }
329
330 /* Helper routine in DRM core does all the work: */
331 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
332 vblank_time, flags,
333 crtc);
334 }
335
336 /*
337 * Handle hotplug events outside the interrupt handler proper.
338 */
339 static void i915_hotplug_work_func(struct work_struct *work)
340 {
341 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
342 hotplug_work);
343 struct drm_device *dev = dev_priv->dev;
344 struct drm_mode_config *mode_config = &dev->mode_config;
345 struct intel_encoder *encoder;
346
347 /* HPD irq before everything is fully set up. */
348 if (!dev_priv->enable_hotplug_processing)
349 return;
350
351 mutex_lock(&mode_config->mutex);
352 DRM_DEBUG_KMS("running encoder hotplug functions\n");
353
354 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
355 if (encoder->hot_plug)
356 encoder->hot_plug(encoder);
357
358 mutex_unlock(&mode_config->mutex);
359
360 /* Just fire off a uevent and let userspace tell us what to do */
361 drm_helper_hpd_irq_event(dev);
362 }
363
364 static void ironlake_handle_rps_change(struct drm_device *dev)
365 {
366 drm_i915_private_t *dev_priv = dev->dev_private;
367 u32 busy_up, busy_down, max_avg, min_avg;
368 u8 new_delay;
369 unsigned long flags;
370
371 spin_lock_irqsave(&mchdev_lock, flags);
372
373 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
374
375 new_delay = dev_priv->ips.cur_delay;
376
377 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
378 busy_up = I915_READ(RCPREVBSYTUPAVG);
379 busy_down = I915_READ(RCPREVBSYTDNAVG);
380 max_avg = I915_READ(RCBMAXAVG);
381 min_avg = I915_READ(RCBMINAVG);
382
383 /* Handle RCS change request from hw */
384 if (busy_up > max_avg) {
385 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
386 new_delay = dev_priv->ips.cur_delay - 1;
387 if (new_delay < dev_priv->ips.max_delay)
388 new_delay = dev_priv->ips.max_delay;
389 } else if (busy_down < min_avg) {
390 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
391 new_delay = dev_priv->ips.cur_delay + 1;
392 if (new_delay > dev_priv->ips.min_delay)
393 new_delay = dev_priv->ips.min_delay;
394 }
395
396 if (ironlake_set_drps(dev, new_delay))
397 dev_priv->ips.cur_delay = new_delay;
398
399 spin_unlock_irqrestore(&mchdev_lock, flags);
400
401 return;
402 }
403
404 static void notify_ring(struct drm_device *dev,
405 struct intel_ring_buffer *ring)
406 {
407 struct drm_i915_private *dev_priv = dev->dev_private;
408
409 if (ring->obj == NULL)
410 return;
411
412 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
413
414 wake_up_all(&ring->irq_queue);
415 if (i915_enable_hangcheck) {
416 dev_priv->gpu_error.hangcheck_count = 0;
417 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
418 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
419 }
420 }
421
422 static void gen6_pm_rps_work(struct work_struct *work)
423 {
424 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
425 rps.work);
426 u32 pm_iir, pm_imr;
427 u8 new_delay;
428
429 spin_lock_irq(&dev_priv->rps.lock);
430 pm_iir = dev_priv->rps.pm_iir;
431 dev_priv->rps.pm_iir = 0;
432 pm_imr = I915_READ(GEN6_PMIMR);
433 I915_WRITE(GEN6_PMIMR, 0);
434 spin_unlock_irq(&dev_priv->rps.lock);
435
436 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
437 return;
438
439 mutex_lock(&dev_priv->rps.hw_lock);
440
441 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
442 new_delay = dev_priv->rps.cur_delay + 1;
443 else
444 new_delay = dev_priv->rps.cur_delay - 1;
445
446 /* sysfs frequency interfaces may have snuck in while servicing the
447 * interrupt
448 */
449 if (!(new_delay > dev_priv->rps.max_delay ||
450 new_delay < dev_priv->rps.min_delay)) {
451 gen6_set_rps(dev_priv->dev, new_delay);
452 }
453
454 mutex_unlock(&dev_priv->rps.hw_lock);
455 }
456
457
458 /**
459 * ivybridge_parity_work - Workqueue called when a parity error interrupt
460 * occurred.
461 * @work: workqueue struct
462 *
463 * Doesn't actually do anything except notify userspace. As a consequence of
464 * this event, userspace should try to remap the bad rows since statistically
465 * it is likely the same row is more likely to go bad again.
466 */
467 static void ivybridge_parity_work(struct work_struct *work)
468 {
469 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
470 l3_parity.error_work);
471 u32 error_status, row, bank, subbank;
472 char *parity_event[5];
473 uint32_t misccpctl;
474 unsigned long flags;
475
476 /* We must turn off DOP level clock gating to access the L3 registers.
477 * In order to prevent a get/put style interface, acquire struct mutex
478 * any time we access those registers.
479 */
480 mutex_lock(&dev_priv->dev->struct_mutex);
481
482 misccpctl = I915_READ(GEN7_MISCCPCTL);
483 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
484 POSTING_READ(GEN7_MISCCPCTL);
485
486 error_status = I915_READ(GEN7_L3CDERRST1);
487 row = GEN7_PARITY_ERROR_ROW(error_status);
488 bank = GEN7_PARITY_ERROR_BANK(error_status);
489 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
490
491 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
492 GEN7_L3CDERRST1_ENABLE);
493 POSTING_READ(GEN7_L3CDERRST1);
494
495 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
496
497 spin_lock_irqsave(&dev_priv->irq_lock, flags);
498 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
499 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
500 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
501
502 mutex_unlock(&dev_priv->dev->struct_mutex);
503
504 parity_event[0] = "L3_PARITY_ERROR=1";
505 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
506 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
507 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
508 parity_event[4] = NULL;
509
510 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
511 KOBJ_CHANGE, parity_event);
512
513 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
514 row, bank, subbank);
515
516 kfree(parity_event[3]);
517 kfree(parity_event[2]);
518 kfree(parity_event[1]);
519 }
520
521 static void ivybridge_handle_parity_error(struct drm_device *dev)
522 {
523 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
524 unsigned long flags;
525
526 if (!HAS_L3_GPU_CACHE(dev))
527 return;
528
529 spin_lock_irqsave(&dev_priv->irq_lock, flags);
530 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
531 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
532 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
533
534 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
535 }
536
537 static void snb_gt_irq_handler(struct drm_device *dev,
538 struct drm_i915_private *dev_priv,
539 u32 gt_iir)
540 {
541
542 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
543 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
544 notify_ring(dev, &dev_priv->ring[RCS]);
545 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
546 notify_ring(dev, &dev_priv->ring[VCS]);
547 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
548 notify_ring(dev, &dev_priv->ring[BCS]);
549
550 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
551 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
552 GT_RENDER_CS_ERROR_INTERRUPT)) {
553 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
554 i915_handle_error(dev, false);
555 }
556
557 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
558 ivybridge_handle_parity_error(dev);
559 }
560
561 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
562 u32 pm_iir)
563 {
564 unsigned long flags;
565
566 /*
567 * IIR bits should never already be set because IMR should
568 * prevent an interrupt from being shown in IIR. The warning
569 * displays a case where we've unsafely cleared
570 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
571 * type is not a problem, it displays a problem in the logic.
572 *
573 * The mask bit in IMR is cleared by dev_priv->rps.work.
574 */
575
576 spin_lock_irqsave(&dev_priv->rps.lock, flags);
577 dev_priv->rps.pm_iir |= pm_iir;
578 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
579 POSTING_READ(GEN6_PMIMR);
580 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
581
582 queue_work(dev_priv->wq, &dev_priv->rps.work);
583 }
584
585 static void gmbus_irq_handler(struct drm_device *dev)
586 {
587 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
588
589 wake_up_all(&dev_priv->gmbus_wait_queue);
590 }
591
592 static void dp_aux_irq_handler(struct drm_device *dev)
593 {
594 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
595
596 wake_up_all(&dev_priv->gmbus_wait_queue);
597 }
598
599 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
600 {
601 struct drm_device *dev = (struct drm_device *) arg;
602 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
603 u32 iir, gt_iir, pm_iir;
604 irqreturn_t ret = IRQ_NONE;
605 unsigned long irqflags;
606 int pipe;
607 u32 pipe_stats[I915_MAX_PIPES];
608
609 atomic_inc(&dev_priv->irq_received);
610
611 while (true) {
612 iir = I915_READ(VLV_IIR);
613 gt_iir = I915_READ(GTIIR);
614 pm_iir = I915_READ(GEN6_PMIIR);
615
616 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
617 goto out;
618
619 ret = IRQ_HANDLED;
620
621 snb_gt_irq_handler(dev, dev_priv, gt_iir);
622
623 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
624 for_each_pipe(pipe) {
625 int reg = PIPESTAT(pipe);
626 pipe_stats[pipe] = I915_READ(reg);
627
628 /*
629 * Clear the PIPE*STAT regs before the IIR
630 */
631 if (pipe_stats[pipe] & 0x8000ffff) {
632 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
633 DRM_DEBUG_DRIVER("pipe %c underrun\n",
634 pipe_name(pipe));
635 I915_WRITE(reg, pipe_stats[pipe]);
636 }
637 }
638 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
639
640 for_each_pipe(pipe) {
641 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
642 drm_handle_vblank(dev, pipe);
643
644 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
645 intel_prepare_page_flip(dev, pipe);
646 intel_finish_page_flip(dev, pipe);
647 }
648 }
649
650 /* Consume port. Then clear IIR or we'll miss events */
651 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
652 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
653
654 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
655 hotplug_status);
656 if (hotplug_status & HOTPLUG_INT_STATUS_I915)
657 queue_work(dev_priv->wq,
658 &dev_priv->hotplug_work);
659
660 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
661 I915_READ(PORT_HOTPLUG_STAT);
662 }
663
664 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
665 gmbus_irq_handler(dev);
666
667 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
668 gen6_queue_rps_work(dev_priv, pm_iir);
669
670 I915_WRITE(GTIIR, gt_iir);
671 I915_WRITE(GEN6_PMIIR, pm_iir);
672 I915_WRITE(VLV_IIR, iir);
673 }
674
675 out:
676 return ret;
677 }
678
679 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
680 {
681 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
682 int pipe;
683
684 if (pch_iir & SDE_HOTPLUG_MASK)
685 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
686
687 if (pch_iir & SDE_AUDIO_POWER_MASK)
688 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
689 (pch_iir & SDE_AUDIO_POWER_MASK) >>
690 SDE_AUDIO_POWER_SHIFT);
691
692 if (pch_iir & SDE_AUX_MASK)
693 dp_aux_irq_handler(dev);
694
695 if (pch_iir & SDE_GMBUS)
696 gmbus_irq_handler(dev);
697
698 if (pch_iir & SDE_AUDIO_HDCP_MASK)
699 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
700
701 if (pch_iir & SDE_AUDIO_TRANS_MASK)
702 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
703
704 if (pch_iir & SDE_POISON)
705 DRM_ERROR("PCH poison interrupt\n");
706
707 if (pch_iir & SDE_FDI_MASK)
708 for_each_pipe(pipe)
709 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
710 pipe_name(pipe),
711 I915_READ(FDI_RX_IIR(pipe)));
712
713 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
714 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
715
716 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
717 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
718
719 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
720 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
721 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
722 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
723 }
724
725 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
726 {
727 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
728 int pipe;
729
730 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
731 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
732
733 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
734 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
735 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
736 SDE_AUDIO_POWER_SHIFT_CPT);
737
738 if (pch_iir & SDE_AUX_MASK_CPT)
739 dp_aux_irq_handler(dev);
740
741 if (pch_iir & SDE_GMBUS_CPT)
742 gmbus_irq_handler(dev);
743
744 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
745 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
746
747 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
748 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
749
750 if (pch_iir & SDE_FDI_MASK_CPT)
751 for_each_pipe(pipe)
752 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
753 pipe_name(pipe),
754 I915_READ(FDI_RX_IIR(pipe)));
755 }
756
757 static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
758 {
759 struct drm_device *dev = (struct drm_device *) arg;
760 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
761 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier = 0;
762 irqreturn_t ret = IRQ_NONE;
763 int i;
764
765 atomic_inc(&dev_priv->irq_received);
766
767 /* disable master interrupt before clearing iir */
768 de_ier = I915_READ(DEIER);
769 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
770
771 /* Disable south interrupts. We'll only write to SDEIIR once, so further
772 * interrupts will will be stored on its back queue, and then we'll be
773 * able to process them after we restore SDEIER (as soon as we restore
774 * it, we'll get an interrupt if SDEIIR still has something to process
775 * due to its back queue). */
776 if (!HAS_PCH_NOP(dev)) {
777 sde_ier = I915_READ(SDEIER);
778 I915_WRITE(SDEIER, 0);
779 POSTING_READ(SDEIER);
780 }
781
782 gt_iir = I915_READ(GTIIR);
783 if (gt_iir) {
784 snb_gt_irq_handler(dev, dev_priv, gt_iir);
785 I915_WRITE(GTIIR, gt_iir);
786 ret = IRQ_HANDLED;
787 }
788
789 de_iir = I915_READ(DEIIR);
790 if (de_iir) {
791 if (de_iir & DE_AUX_CHANNEL_A_IVB)
792 dp_aux_irq_handler(dev);
793
794 if (de_iir & DE_GSE_IVB)
795 intel_opregion_gse_intr(dev);
796
797 for (i = 0; i < 3; i++) {
798 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
799 drm_handle_vblank(dev, i);
800 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
801 intel_prepare_page_flip(dev, i);
802 intel_finish_page_flip_plane(dev, i);
803 }
804 }
805
806 /* check event from PCH */
807 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
808 u32 pch_iir = I915_READ(SDEIIR);
809
810 cpt_irq_handler(dev, pch_iir);
811
812 /* clear PCH hotplug event before clear CPU irq */
813 I915_WRITE(SDEIIR, pch_iir);
814 }
815
816 I915_WRITE(DEIIR, de_iir);
817 ret = IRQ_HANDLED;
818 }
819
820 pm_iir = I915_READ(GEN6_PMIIR);
821 if (pm_iir) {
822 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
823 gen6_queue_rps_work(dev_priv, pm_iir);
824 I915_WRITE(GEN6_PMIIR, pm_iir);
825 ret = IRQ_HANDLED;
826 }
827
828 I915_WRITE(DEIER, de_ier);
829 POSTING_READ(DEIER);
830 if (!HAS_PCH_NOP(dev)) {
831 I915_WRITE(SDEIER, sde_ier);
832 POSTING_READ(SDEIER);
833 }
834
835 return ret;
836 }
837
838 static void ilk_gt_irq_handler(struct drm_device *dev,
839 struct drm_i915_private *dev_priv,
840 u32 gt_iir)
841 {
842 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
843 notify_ring(dev, &dev_priv->ring[RCS]);
844 if (gt_iir & GT_BSD_USER_INTERRUPT)
845 notify_ring(dev, &dev_priv->ring[VCS]);
846 }
847
848 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
849 {
850 struct drm_device *dev = (struct drm_device *) arg;
851 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
852 int ret = IRQ_NONE;
853 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
854
855 atomic_inc(&dev_priv->irq_received);
856
857 /* disable master interrupt before clearing iir */
858 de_ier = I915_READ(DEIER);
859 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
860 POSTING_READ(DEIER);
861
862 /* Disable south interrupts. We'll only write to SDEIIR once, so further
863 * interrupts will will be stored on its back queue, and then we'll be
864 * able to process them after we restore SDEIER (as soon as we restore
865 * it, we'll get an interrupt if SDEIIR still has something to process
866 * due to its back queue). */
867 sde_ier = I915_READ(SDEIER);
868 I915_WRITE(SDEIER, 0);
869 POSTING_READ(SDEIER);
870
871 de_iir = I915_READ(DEIIR);
872 gt_iir = I915_READ(GTIIR);
873 pm_iir = I915_READ(GEN6_PMIIR);
874
875 if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
876 goto done;
877
878 ret = IRQ_HANDLED;
879
880 if (IS_GEN5(dev))
881 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
882 else
883 snb_gt_irq_handler(dev, dev_priv, gt_iir);
884
885 if (de_iir & DE_AUX_CHANNEL_A)
886 dp_aux_irq_handler(dev);
887
888 if (de_iir & DE_GSE)
889 intel_opregion_gse_intr(dev);
890
891 if (de_iir & DE_PIPEA_VBLANK)
892 drm_handle_vblank(dev, 0);
893
894 if (de_iir & DE_PIPEB_VBLANK)
895 drm_handle_vblank(dev, 1);
896
897 if (de_iir & DE_PLANEA_FLIP_DONE) {
898 intel_prepare_page_flip(dev, 0);
899 intel_finish_page_flip_plane(dev, 0);
900 }
901
902 if (de_iir & DE_PLANEB_FLIP_DONE) {
903 intel_prepare_page_flip(dev, 1);
904 intel_finish_page_flip_plane(dev, 1);
905 }
906
907 /* check event from PCH */
908 if (de_iir & DE_PCH_EVENT) {
909 u32 pch_iir = I915_READ(SDEIIR);
910
911 if (HAS_PCH_CPT(dev))
912 cpt_irq_handler(dev, pch_iir);
913 else
914 ibx_irq_handler(dev, pch_iir);
915
916 /* should clear PCH hotplug event before clear CPU irq */
917 I915_WRITE(SDEIIR, pch_iir);
918 }
919
920 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
921 ironlake_handle_rps_change(dev);
922
923 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
924 gen6_queue_rps_work(dev_priv, pm_iir);
925
926 I915_WRITE(GTIIR, gt_iir);
927 I915_WRITE(DEIIR, de_iir);
928 I915_WRITE(GEN6_PMIIR, pm_iir);
929
930 done:
931 I915_WRITE(DEIER, de_ier);
932 POSTING_READ(DEIER);
933 I915_WRITE(SDEIER, sde_ier);
934 POSTING_READ(SDEIER);
935
936 return ret;
937 }
938
939 /**
940 * i915_error_work_func - do process context error handling work
941 * @work: work struct
942 *
943 * Fire an error uevent so userspace can see that a hang or error
944 * was detected.
945 */
946 static void i915_error_work_func(struct work_struct *work)
947 {
948 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
949 work);
950 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
951 gpu_error);
952 struct drm_device *dev = dev_priv->dev;
953 struct intel_ring_buffer *ring;
954 char *error_event[] = { "ERROR=1", NULL };
955 char *reset_event[] = { "RESET=1", NULL };
956 char *reset_done_event[] = { "ERROR=0", NULL };
957 int i, ret;
958
959 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
960
961 /*
962 * Note that there's only one work item which does gpu resets, so we
963 * need not worry about concurrent gpu resets potentially incrementing
964 * error->reset_counter twice. We only need to take care of another
965 * racing irq/hangcheck declaring the gpu dead for a second time. A
966 * quick check for that is good enough: schedule_work ensures the
967 * correct ordering between hang detection and this work item, and since
968 * the reset in-progress bit is only ever set by code outside of this
969 * work we don't need to worry about any other races.
970 */
971 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
972 DRM_DEBUG_DRIVER("resetting chip\n");
973 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
974 reset_event);
975
976 ret = i915_reset(dev);
977
978 if (ret == 0) {
979 /*
980 * After all the gem state is reset, increment the reset
981 * counter and wake up everyone waiting for the reset to
982 * complete.
983 *
984 * Since unlock operations are a one-sided barrier only,
985 * we need to insert a barrier here to order any seqno
986 * updates before
987 * the counter increment.
988 */
989 smp_mb__before_atomic_inc();
990 atomic_inc(&dev_priv->gpu_error.reset_counter);
991
992 kobject_uevent_env(&dev->primary->kdev.kobj,
993 KOBJ_CHANGE, reset_done_event);
994 } else {
995 atomic_set(&error->reset_counter, I915_WEDGED);
996 }
997
998 for_each_ring(ring, dev_priv, i)
999 wake_up_all(&ring->irq_queue);
1000
1001 intel_display_handle_reset(dev);
1002
1003 wake_up_all(&dev_priv->gpu_error.reset_queue);
1004 }
1005 }
1006
1007 /* NB: please notice the memset */
1008 static void i915_get_extra_instdone(struct drm_device *dev,
1009 uint32_t *instdone)
1010 {
1011 struct drm_i915_private *dev_priv = dev->dev_private;
1012 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1013
1014 switch(INTEL_INFO(dev)->gen) {
1015 case 2:
1016 case 3:
1017 instdone[0] = I915_READ(INSTDONE);
1018 break;
1019 case 4:
1020 case 5:
1021 case 6:
1022 instdone[0] = I915_READ(INSTDONE_I965);
1023 instdone[1] = I915_READ(INSTDONE1);
1024 break;
1025 default:
1026 WARN_ONCE(1, "Unsupported platform\n");
1027 case 7:
1028 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1029 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1030 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1031 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1032 break;
1033 }
1034 }
1035
1036 #ifdef CONFIG_DEBUG_FS
1037 static struct drm_i915_error_object *
1038 i915_error_object_create_sized(struct drm_i915_private *dev_priv,
1039 struct drm_i915_gem_object *src,
1040 const int num_pages)
1041 {
1042 struct drm_i915_error_object *dst;
1043 int i;
1044 u32 reloc_offset;
1045
1046 if (src == NULL || src->pages == NULL)
1047 return NULL;
1048
1049 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
1050 if (dst == NULL)
1051 return NULL;
1052
1053 reloc_offset = src->gtt_offset;
1054 for (i = 0; i < num_pages; i++) {
1055 unsigned long flags;
1056 void *d;
1057
1058 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
1059 if (d == NULL)
1060 goto unwind;
1061
1062 local_irq_save(flags);
1063 if (reloc_offset < dev_priv->gtt.mappable_end &&
1064 src->has_global_gtt_mapping) {
1065 void __iomem *s;
1066
1067 /* Simply ignore tiling or any overlapping fence.
1068 * It's part of the error state, and this hopefully
1069 * captures what the GPU read.
1070 */
1071
1072 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
1073 reloc_offset);
1074 memcpy_fromio(d, s, PAGE_SIZE);
1075 io_mapping_unmap_atomic(s);
1076 } else if (src->stolen) {
1077 unsigned long offset;
1078
1079 offset = dev_priv->mm.stolen_base;
1080 offset += src->stolen->start;
1081 offset += i << PAGE_SHIFT;
1082
1083 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
1084 } else {
1085 struct page *page;
1086 void *s;
1087
1088 page = i915_gem_object_get_page(src, i);
1089
1090 drm_clflush_pages(&page, 1);
1091
1092 s = kmap_atomic(page);
1093 memcpy(d, s, PAGE_SIZE);
1094 kunmap_atomic(s);
1095
1096 drm_clflush_pages(&page, 1);
1097 }
1098 local_irq_restore(flags);
1099
1100 dst->pages[i] = d;
1101
1102 reloc_offset += PAGE_SIZE;
1103 }
1104 dst->page_count = num_pages;
1105 dst->gtt_offset = src->gtt_offset;
1106
1107 return dst;
1108
1109 unwind:
1110 while (i--)
1111 kfree(dst->pages[i]);
1112 kfree(dst);
1113 return NULL;
1114 }
1115 #define i915_error_object_create(dev_priv, src) \
1116 i915_error_object_create_sized((dev_priv), (src), \
1117 (src)->base.size>>PAGE_SHIFT)
1118
1119 static void
1120 i915_error_object_free(struct drm_i915_error_object *obj)
1121 {
1122 int page;
1123
1124 if (obj == NULL)
1125 return;
1126
1127 for (page = 0; page < obj->page_count; page++)
1128 kfree(obj->pages[page]);
1129
1130 kfree(obj);
1131 }
1132
1133 void
1134 i915_error_state_free(struct kref *error_ref)
1135 {
1136 struct drm_i915_error_state *error = container_of(error_ref,
1137 typeof(*error), ref);
1138 int i;
1139
1140 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1141 i915_error_object_free(error->ring[i].batchbuffer);
1142 i915_error_object_free(error->ring[i].ringbuffer);
1143 kfree(error->ring[i].requests);
1144 }
1145
1146 kfree(error->active_bo);
1147 kfree(error->overlay);
1148 kfree(error);
1149 }
1150 static void capture_bo(struct drm_i915_error_buffer *err,
1151 struct drm_i915_gem_object *obj)
1152 {
1153 err->size = obj->base.size;
1154 err->name = obj->base.name;
1155 err->rseqno = obj->last_read_seqno;
1156 err->wseqno = obj->last_write_seqno;
1157 err->gtt_offset = obj->gtt_offset;
1158 err->read_domains = obj->base.read_domains;
1159 err->write_domain = obj->base.write_domain;
1160 err->fence_reg = obj->fence_reg;
1161 err->pinned = 0;
1162 if (obj->pin_count > 0)
1163 err->pinned = 1;
1164 if (obj->user_pin_count > 0)
1165 err->pinned = -1;
1166 err->tiling = obj->tiling_mode;
1167 err->dirty = obj->dirty;
1168 err->purgeable = obj->madv != I915_MADV_WILLNEED;
1169 err->ring = obj->ring ? obj->ring->id : -1;
1170 err->cache_level = obj->cache_level;
1171 }
1172
1173 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1174 int count, struct list_head *head)
1175 {
1176 struct drm_i915_gem_object *obj;
1177 int i = 0;
1178
1179 list_for_each_entry(obj, head, mm_list) {
1180 capture_bo(err++, obj);
1181 if (++i == count)
1182 break;
1183 }
1184
1185 return i;
1186 }
1187
1188 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1189 int count, struct list_head *head)
1190 {
1191 struct drm_i915_gem_object *obj;
1192 int i = 0;
1193
1194 list_for_each_entry(obj, head, gtt_list) {
1195 if (obj->pin_count == 0)
1196 continue;
1197
1198 capture_bo(err++, obj);
1199 if (++i == count)
1200 break;
1201 }
1202
1203 return i;
1204 }
1205
1206 static void i915_gem_record_fences(struct drm_device *dev,
1207 struct drm_i915_error_state *error)
1208 {
1209 struct drm_i915_private *dev_priv = dev->dev_private;
1210 int i;
1211
1212 /* Fences */
1213 switch (INTEL_INFO(dev)->gen) {
1214 case 7:
1215 case 6:
1216 for (i = 0; i < 16; i++)
1217 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1218 break;
1219 case 5:
1220 case 4:
1221 for (i = 0; i < 16; i++)
1222 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1223 break;
1224 case 3:
1225 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1226 for (i = 0; i < 8; i++)
1227 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1228 case 2:
1229 for (i = 0; i < 8; i++)
1230 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1231 break;
1232
1233 default:
1234 BUG();
1235 }
1236 }
1237
1238 static struct drm_i915_error_object *
1239 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1240 struct intel_ring_buffer *ring)
1241 {
1242 struct drm_i915_gem_object *obj;
1243 u32 seqno;
1244
1245 if (!ring->get_seqno)
1246 return NULL;
1247
1248 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
1249 u32 acthd = I915_READ(ACTHD);
1250
1251 if (WARN_ON(ring->id != RCS))
1252 return NULL;
1253
1254 obj = ring->private;
1255 if (acthd >= obj->gtt_offset &&
1256 acthd < obj->gtt_offset + obj->base.size)
1257 return i915_error_object_create(dev_priv, obj);
1258 }
1259
1260 seqno = ring->get_seqno(ring, false);
1261 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1262 if (obj->ring != ring)
1263 continue;
1264
1265 if (i915_seqno_passed(seqno, obj->last_read_seqno))
1266 continue;
1267
1268 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1269 continue;
1270
1271 /* We need to copy these to an anonymous buffer as the simplest
1272 * method to avoid being overwritten by userspace.
1273 */
1274 return i915_error_object_create(dev_priv, obj);
1275 }
1276
1277 return NULL;
1278 }
1279
1280 static void i915_record_ring_state(struct drm_device *dev,
1281 struct drm_i915_error_state *error,
1282 struct intel_ring_buffer *ring)
1283 {
1284 struct drm_i915_private *dev_priv = dev->dev_private;
1285
1286 if (INTEL_INFO(dev)->gen >= 6) {
1287 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
1288 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
1289 error->semaphore_mboxes[ring->id][0]
1290 = I915_READ(RING_SYNC_0(ring->mmio_base));
1291 error->semaphore_mboxes[ring->id][1]
1292 = I915_READ(RING_SYNC_1(ring->mmio_base));
1293 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1294 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
1295 }
1296
1297 if (INTEL_INFO(dev)->gen >= 4) {
1298 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1299 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1300 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1301 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1302 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1303 if (ring->id == RCS)
1304 error->bbaddr = I915_READ64(BB_ADDR);
1305 } else {
1306 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1307 error->ipeir[ring->id] = I915_READ(IPEIR);
1308 error->ipehr[ring->id] = I915_READ(IPEHR);
1309 error->instdone[ring->id] = I915_READ(INSTDONE);
1310 }
1311
1312 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
1313 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1314 error->seqno[ring->id] = ring->get_seqno(ring, false);
1315 error->acthd[ring->id] = intel_ring_get_active_head(ring);
1316 error->head[ring->id] = I915_READ_HEAD(ring);
1317 error->tail[ring->id] = I915_READ_TAIL(ring);
1318 error->ctl[ring->id] = I915_READ_CTL(ring);
1319
1320 error->cpu_ring_head[ring->id] = ring->head;
1321 error->cpu_ring_tail[ring->id] = ring->tail;
1322 }
1323
1324
1325 static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
1326 struct drm_i915_error_state *error,
1327 struct drm_i915_error_ring *ering)
1328 {
1329 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1330 struct drm_i915_gem_object *obj;
1331
1332 /* Currently render ring is the only HW context user */
1333 if (ring->id != RCS || !error->ccid)
1334 return;
1335
1336 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
1337 if ((error->ccid & PAGE_MASK) == obj->gtt_offset) {
1338 ering->ctx = i915_error_object_create_sized(dev_priv,
1339 obj, 1);
1340 }
1341 }
1342 }
1343
1344 static void i915_gem_record_rings(struct drm_device *dev,
1345 struct drm_i915_error_state *error)
1346 {
1347 struct drm_i915_private *dev_priv = dev->dev_private;
1348 struct intel_ring_buffer *ring;
1349 struct drm_i915_gem_request *request;
1350 int i, count;
1351
1352 for_each_ring(ring, dev_priv, i) {
1353 i915_record_ring_state(dev, error, ring);
1354
1355 error->ring[i].batchbuffer =
1356 i915_error_first_batchbuffer(dev_priv, ring);
1357
1358 error->ring[i].ringbuffer =
1359 i915_error_object_create(dev_priv, ring->obj);
1360
1361
1362 i915_gem_record_active_context(ring, error, &error->ring[i]);
1363
1364 count = 0;
1365 list_for_each_entry(request, &ring->request_list, list)
1366 count++;
1367
1368 error->ring[i].num_requests = count;
1369 error->ring[i].requests =
1370 kmalloc(count*sizeof(struct drm_i915_error_request),
1371 GFP_ATOMIC);
1372 if (error->ring[i].requests == NULL) {
1373 error->ring[i].num_requests = 0;
1374 continue;
1375 }
1376
1377 count = 0;
1378 list_for_each_entry(request, &ring->request_list, list) {
1379 struct drm_i915_error_request *erq;
1380
1381 erq = &error->ring[i].requests[count++];
1382 erq->seqno = request->seqno;
1383 erq->jiffies = request->emitted_jiffies;
1384 erq->tail = request->tail;
1385 }
1386 }
1387 }
1388
1389 /**
1390 * i915_capture_error_state - capture an error record for later analysis
1391 * @dev: drm device
1392 *
1393 * Should be called when an error is detected (either a hang or an error
1394 * interrupt) to capture error state from the time of the error. Fills
1395 * out a structure which becomes available in debugfs for user level tools
1396 * to pick up.
1397 */
1398 static void i915_capture_error_state(struct drm_device *dev)
1399 {
1400 struct drm_i915_private *dev_priv = dev->dev_private;
1401 struct drm_i915_gem_object *obj;
1402 struct drm_i915_error_state *error;
1403 unsigned long flags;
1404 int i, pipe;
1405
1406 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1407 error = dev_priv->gpu_error.first_error;
1408 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1409 if (error)
1410 return;
1411
1412 /* Account for pipe specific data like PIPE*STAT */
1413 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1414 if (!error) {
1415 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1416 return;
1417 }
1418
1419 DRM_INFO("capturing error event; look for more information in "
1420 "/sys/kernel/debug/dri/%d/i915_error_state\n",
1421 dev->primary->index);
1422
1423 kref_init(&error->ref);
1424 error->eir = I915_READ(EIR);
1425 error->pgtbl_er = I915_READ(PGTBL_ER);
1426 if (HAS_HW_CONTEXTS(dev))
1427 error->ccid = I915_READ(CCID);
1428
1429 if (HAS_PCH_SPLIT(dev))
1430 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1431 else if (IS_VALLEYVIEW(dev))
1432 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1433 else if (IS_GEN2(dev))
1434 error->ier = I915_READ16(IER);
1435 else
1436 error->ier = I915_READ(IER);
1437
1438 if (INTEL_INFO(dev)->gen >= 6)
1439 error->derrmr = I915_READ(DERRMR);
1440
1441 if (IS_VALLEYVIEW(dev))
1442 error->forcewake = I915_READ(FORCEWAKE_VLV);
1443 else if (INTEL_INFO(dev)->gen >= 7)
1444 error->forcewake = I915_READ(FORCEWAKE_MT);
1445 else if (INTEL_INFO(dev)->gen == 6)
1446 error->forcewake = I915_READ(FORCEWAKE);
1447
1448 if (!HAS_PCH_SPLIT(dev))
1449 for_each_pipe(pipe)
1450 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1451
1452 if (INTEL_INFO(dev)->gen >= 6) {
1453 error->error = I915_READ(ERROR_GEN6);
1454 error->done_reg = I915_READ(DONE_REG);
1455 }
1456
1457 if (INTEL_INFO(dev)->gen == 7)
1458 error->err_int = I915_READ(GEN7_ERR_INT);
1459
1460 i915_get_extra_instdone(dev, error->extra_instdone);
1461
1462 i915_gem_record_fences(dev, error);
1463 i915_gem_record_rings(dev, error);
1464
1465 /* Record buffers on the active and pinned lists. */
1466 error->active_bo = NULL;
1467 error->pinned_bo = NULL;
1468
1469 i = 0;
1470 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1471 i++;
1472 error->active_bo_count = i;
1473 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1474 if (obj->pin_count)
1475 i++;
1476 error->pinned_bo_count = i - error->active_bo_count;
1477
1478 error->active_bo = NULL;
1479 error->pinned_bo = NULL;
1480 if (i) {
1481 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1482 GFP_ATOMIC);
1483 if (error->active_bo)
1484 error->pinned_bo =
1485 error->active_bo + error->active_bo_count;
1486 }
1487
1488 if (error->active_bo)
1489 error->active_bo_count =
1490 capture_active_bo(error->active_bo,
1491 error->active_bo_count,
1492 &dev_priv->mm.active_list);
1493
1494 if (error->pinned_bo)
1495 error->pinned_bo_count =
1496 capture_pinned_bo(error->pinned_bo,
1497 error->pinned_bo_count,
1498 &dev_priv->mm.bound_list);
1499
1500 do_gettimeofday(&error->time);
1501
1502 error->overlay = intel_overlay_capture_error_state(dev);
1503 error->display = intel_display_capture_error_state(dev);
1504
1505 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1506 if (dev_priv->gpu_error.first_error == NULL) {
1507 dev_priv->gpu_error.first_error = error;
1508 error = NULL;
1509 }
1510 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1511
1512 if (error)
1513 i915_error_state_free(&error->ref);
1514 }
1515
1516 void i915_destroy_error_state(struct drm_device *dev)
1517 {
1518 struct drm_i915_private *dev_priv = dev->dev_private;
1519 struct drm_i915_error_state *error;
1520 unsigned long flags;
1521
1522 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1523 error = dev_priv->gpu_error.first_error;
1524 dev_priv->gpu_error.first_error = NULL;
1525 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1526
1527 if (error)
1528 kref_put(&error->ref, i915_error_state_free);
1529 }
1530 #else
1531 #define i915_capture_error_state(x)
1532 #endif
1533
1534 static void i915_report_and_clear_eir(struct drm_device *dev)
1535 {
1536 struct drm_i915_private *dev_priv = dev->dev_private;
1537 uint32_t instdone[I915_NUM_INSTDONE_REG];
1538 u32 eir = I915_READ(EIR);
1539 int pipe, i;
1540
1541 if (!eir)
1542 return;
1543
1544 pr_err("render error detected, EIR: 0x%08x\n", eir);
1545
1546 i915_get_extra_instdone(dev, instdone);
1547
1548 if (IS_G4X(dev)) {
1549 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1550 u32 ipeir = I915_READ(IPEIR_I965);
1551
1552 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1553 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1554 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1555 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1556 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1557 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1558 I915_WRITE(IPEIR_I965, ipeir);
1559 POSTING_READ(IPEIR_I965);
1560 }
1561 if (eir & GM45_ERROR_PAGE_TABLE) {
1562 u32 pgtbl_err = I915_READ(PGTBL_ER);
1563 pr_err("page table error\n");
1564 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
1565 I915_WRITE(PGTBL_ER, pgtbl_err);
1566 POSTING_READ(PGTBL_ER);
1567 }
1568 }
1569
1570 if (!IS_GEN2(dev)) {
1571 if (eir & I915_ERROR_PAGE_TABLE) {
1572 u32 pgtbl_err = I915_READ(PGTBL_ER);
1573 pr_err("page table error\n");
1574 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
1575 I915_WRITE(PGTBL_ER, pgtbl_err);
1576 POSTING_READ(PGTBL_ER);
1577 }
1578 }
1579
1580 if (eir & I915_ERROR_MEMORY_REFRESH) {
1581 pr_err("memory refresh error:\n");
1582 for_each_pipe(pipe)
1583 pr_err("pipe %c stat: 0x%08x\n",
1584 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1585 /* pipestat has already been acked */
1586 }
1587 if (eir & I915_ERROR_INSTRUCTION) {
1588 pr_err("instruction error\n");
1589 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
1590 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1591 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1592 if (INTEL_INFO(dev)->gen < 4) {
1593 u32 ipeir = I915_READ(IPEIR);
1594
1595 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1596 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
1597 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
1598 I915_WRITE(IPEIR, ipeir);
1599 POSTING_READ(IPEIR);
1600 } else {
1601 u32 ipeir = I915_READ(IPEIR_I965);
1602
1603 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1604 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1605 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1606 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1607 I915_WRITE(IPEIR_I965, ipeir);
1608 POSTING_READ(IPEIR_I965);
1609 }
1610 }
1611
1612 I915_WRITE(EIR, eir);
1613 POSTING_READ(EIR);
1614 eir = I915_READ(EIR);
1615 if (eir) {
1616 /*
1617 * some errors might have become stuck,
1618 * mask them.
1619 */
1620 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1621 I915_WRITE(EMR, I915_READ(EMR) | eir);
1622 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1623 }
1624 }
1625
1626 /**
1627 * i915_handle_error - handle an error interrupt
1628 * @dev: drm device
1629 *
1630 * Do some basic checking of regsiter state at error interrupt time and
1631 * dump it to the syslog. Also call i915_capture_error_state() to make
1632 * sure we get a record and make it available in debugfs. Fire a uevent
1633 * so userspace knows something bad happened (should trigger collection
1634 * of a ring dump etc.).
1635 */
1636 void i915_handle_error(struct drm_device *dev, bool wedged)
1637 {
1638 struct drm_i915_private *dev_priv = dev->dev_private;
1639 struct intel_ring_buffer *ring;
1640 int i;
1641
1642 i915_capture_error_state(dev);
1643 i915_report_and_clear_eir(dev);
1644
1645 if (wedged) {
1646 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
1647 &dev_priv->gpu_error.reset_counter);
1648
1649 /*
1650 * Wakeup waiting processes so that the reset work item
1651 * doesn't deadlock trying to grab various locks.
1652 */
1653 for_each_ring(ring, dev_priv, i)
1654 wake_up_all(&ring->irq_queue);
1655 }
1656
1657 queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
1658 }
1659
1660 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1661 {
1662 drm_i915_private_t *dev_priv = dev->dev_private;
1663 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1665 struct drm_i915_gem_object *obj;
1666 struct intel_unpin_work *work;
1667 unsigned long flags;
1668 bool stall_detected;
1669
1670 /* Ignore early vblank irqs */
1671 if (intel_crtc == NULL)
1672 return;
1673
1674 spin_lock_irqsave(&dev->event_lock, flags);
1675 work = intel_crtc->unpin_work;
1676
1677 if (work == NULL ||
1678 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1679 !work->enable_stall_check) {
1680 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1681 spin_unlock_irqrestore(&dev->event_lock, flags);
1682 return;
1683 }
1684
1685 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1686 obj = work->pending_flip_obj;
1687 if (INTEL_INFO(dev)->gen >= 4) {
1688 int dspsurf = DSPSURF(intel_crtc->plane);
1689 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1690 obj->gtt_offset;
1691 } else {
1692 int dspaddr = DSPADDR(intel_crtc->plane);
1693 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1694 crtc->y * crtc->fb->pitches[0] +
1695 crtc->x * crtc->fb->bits_per_pixel/8);
1696 }
1697
1698 spin_unlock_irqrestore(&dev->event_lock, flags);
1699
1700 if (stall_detected) {
1701 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1702 intel_prepare_page_flip(dev, intel_crtc->plane);
1703 }
1704 }
1705
1706 /* Called from drm generic code, passed 'crtc' which
1707 * we use as a pipe index
1708 */
1709 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1710 {
1711 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1712 unsigned long irqflags;
1713
1714 if (!i915_pipe_enabled(dev, pipe))
1715 return -EINVAL;
1716
1717 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1718 if (INTEL_INFO(dev)->gen >= 4)
1719 i915_enable_pipestat(dev_priv, pipe,
1720 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1721 else
1722 i915_enable_pipestat(dev_priv, pipe,
1723 PIPE_VBLANK_INTERRUPT_ENABLE);
1724
1725 /* maintain vblank delivery even in deep C-states */
1726 if (dev_priv->info->gen == 3)
1727 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1728 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1729
1730 return 0;
1731 }
1732
1733 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1734 {
1735 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1736 unsigned long irqflags;
1737
1738 if (!i915_pipe_enabled(dev, pipe))
1739 return -EINVAL;
1740
1741 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1742 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1743 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1744 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1745
1746 return 0;
1747 }
1748
1749 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1750 {
1751 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1752 unsigned long irqflags;
1753
1754 if (!i915_pipe_enabled(dev, pipe))
1755 return -EINVAL;
1756
1757 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1758 ironlake_enable_display_irq(dev_priv,
1759 DE_PIPEA_VBLANK_IVB << (5 * pipe));
1760 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1761
1762 return 0;
1763 }
1764
1765 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1766 {
1767 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1768 unsigned long irqflags;
1769 u32 imr;
1770
1771 if (!i915_pipe_enabled(dev, pipe))
1772 return -EINVAL;
1773
1774 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1775 imr = I915_READ(VLV_IMR);
1776 if (pipe == 0)
1777 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1778 else
1779 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1780 I915_WRITE(VLV_IMR, imr);
1781 i915_enable_pipestat(dev_priv, pipe,
1782 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1783 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1784
1785 return 0;
1786 }
1787
1788 /* Called from drm generic code, passed 'crtc' which
1789 * we use as a pipe index
1790 */
1791 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1792 {
1793 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1794 unsigned long irqflags;
1795
1796 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1797 if (dev_priv->info->gen == 3)
1798 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1799
1800 i915_disable_pipestat(dev_priv, pipe,
1801 PIPE_VBLANK_INTERRUPT_ENABLE |
1802 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1803 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1804 }
1805
1806 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1807 {
1808 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1809 unsigned long irqflags;
1810
1811 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1812 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1813 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1814 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1815 }
1816
1817 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1818 {
1819 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1820 unsigned long irqflags;
1821
1822 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1823 ironlake_disable_display_irq(dev_priv,
1824 DE_PIPEA_VBLANK_IVB << (pipe * 5));
1825 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1826 }
1827
1828 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1829 {
1830 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1831 unsigned long irqflags;
1832 u32 imr;
1833
1834 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1835 i915_disable_pipestat(dev_priv, pipe,
1836 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1837 imr = I915_READ(VLV_IMR);
1838 if (pipe == 0)
1839 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1840 else
1841 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1842 I915_WRITE(VLV_IMR, imr);
1843 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1844 }
1845
1846 static u32
1847 ring_last_seqno(struct intel_ring_buffer *ring)
1848 {
1849 return list_entry(ring->request_list.prev,
1850 struct drm_i915_gem_request, list)->seqno;
1851 }
1852
1853 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1854 {
1855 if (list_empty(&ring->request_list) ||
1856 i915_seqno_passed(ring->get_seqno(ring, false),
1857 ring_last_seqno(ring))) {
1858 /* Issue a wake-up to catch stuck h/w. */
1859 if (waitqueue_active(&ring->irq_queue)) {
1860 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1861 ring->name);
1862 wake_up_all(&ring->irq_queue);
1863 *err = true;
1864 }
1865 return true;
1866 }
1867 return false;
1868 }
1869
1870 static bool semaphore_passed(struct intel_ring_buffer *ring)
1871 {
1872 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1873 u32 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
1874 struct intel_ring_buffer *signaller;
1875 u32 cmd, ipehr, acthd_min;
1876
1877 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
1878 if ((ipehr & ~(0x3 << 16)) !=
1879 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
1880 return false;
1881
1882 /* ACTHD is likely pointing to the dword after the actual command,
1883 * so scan backwards until we find the MBOX.
1884 */
1885 acthd_min = max((int)acthd - 3 * 4, 0);
1886 do {
1887 cmd = ioread32(ring->virtual_start + acthd);
1888 if (cmd == ipehr)
1889 break;
1890
1891 acthd -= 4;
1892 if (acthd < acthd_min)
1893 return false;
1894 } while (1);
1895
1896 signaller = &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
1897 return i915_seqno_passed(signaller->get_seqno(signaller, false),
1898 ioread32(ring->virtual_start+acthd+4)+1);
1899 }
1900
1901 static bool kick_ring(struct intel_ring_buffer *ring)
1902 {
1903 struct drm_device *dev = ring->dev;
1904 struct drm_i915_private *dev_priv = dev->dev_private;
1905 u32 tmp = I915_READ_CTL(ring);
1906 if (tmp & RING_WAIT) {
1907 DRM_ERROR("Kicking stuck wait on %s\n",
1908 ring->name);
1909 I915_WRITE_CTL(ring, tmp);
1910 return true;
1911 }
1912
1913 if (INTEL_INFO(dev)->gen >= 6 &&
1914 tmp & RING_WAIT_SEMAPHORE &&
1915 semaphore_passed(ring)) {
1916 DRM_ERROR("Kicking stuck semaphore on %s\n",
1917 ring->name);
1918 I915_WRITE_CTL(ring, tmp);
1919 return true;
1920 }
1921 return false;
1922 }
1923
1924 static bool i915_hangcheck_hung(struct drm_device *dev)
1925 {
1926 drm_i915_private_t *dev_priv = dev->dev_private;
1927
1928 if (dev_priv->gpu_error.hangcheck_count++ > 1) {
1929 bool hung = true;
1930
1931 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1932 i915_handle_error(dev, true);
1933
1934 if (!IS_GEN2(dev)) {
1935 struct intel_ring_buffer *ring;
1936 int i;
1937
1938 /* Is the chip hanging on a WAIT_FOR_EVENT?
1939 * If so we can simply poke the RB_WAIT bit
1940 * and break the hang. This should work on
1941 * all but the second generation chipsets.
1942 */
1943 for_each_ring(ring, dev_priv, i)
1944 hung &= !kick_ring(ring);
1945 }
1946
1947 return hung;
1948 }
1949
1950 return false;
1951 }
1952
1953 /**
1954 * This is called when the chip hasn't reported back with completed
1955 * batchbuffers in a long time. The first time this is called we simply record
1956 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1957 * again, we assume the chip is wedged and try to fix it.
1958 */
1959 void i915_hangcheck_elapsed(unsigned long data)
1960 {
1961 struct drm_device *dev = (struct drm_device *)data;
1962 drm_i915_private_t *dev_priv = dev->dev_private;
1963 uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
1964 struct intel_ring_buffer *ring;
1965 bool err = false, idle;
1966 int i;
1967
1968 if (!i915_enable_hangcheck)
1969 return;
1970
1971 memset(acthd, 0, sizeof(acthd));
1972 idle = true;
1973 for_each_ring(ring, dev_priv, i) {
1974 idle &= i915_hangcheck_ring_idle(ring, &err);
1975 acthd[i] = intel_ring_get_active_head(ring);
1976 }
1977
1978 /* If all work is done then ACTHD clearly hasn't advanced. */
1979 if (idle) {
1980 if (err) {
1981 if (i915_hangcheck_hung(dev))
1982 return;
1983
1984 goto repeat;
1985 }
1986
1987 dev_priv->gpu_error.hangcheck_count = 0;
1988 return;
1989 }
1990
1991 i915_get_extra_instdone(dev, instdone);
1992 if (memcmp(dev_priv->gpu_error.last_acthd, acthd,
1993 sizeof(acthd)) == 0 &&
1994 memcmp(dev_priv->gpu_error.prev_instdone, instdone,
1995 sizeof(instdone)) == 0) {
1996 if (i915_hangcheck_hung(dev))
1997 return;
1998 } else {
1999 dev_priv->gpu_error.hangcheck_count = 0;
2000
2001 memcpy(dev_priv->gpu_error.last_acthd, acthd,
2002 sizeof(acthd));
2003 memcpy(dev_priv->gpu_error.prev_instdone, instdone,
2004 sizeof(instdone));
2005 }
2006
2007 repeat:
2008 /* Reset timer case chip hangs without another request being added */
2009 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2010 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2011 }
2012
2013 /* drm_dma.h hooks
2014 */
2015 static void ironlake_irq_preinstall(struct drm_device *dev)
2016 {
2017 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2018
2019 atomic_set(&dev_priv->irq_received, 0);
2020
2021 I915_WRITE(HWSTAM, 0xeffe);
2022
2023 /* XXX hotplug from PCH */
2024
2025 I915_WRITE(DEIMR, 0xffffffff);
2026 I915_WRITE(DEIER, 0x0);
2027 POSTING_READ(DEIER);
2028
2029 /* and GT */
2030 I915_WRITE(GTIMR, 0xffffffff);
2031 I915_WRITE(GTIER, 0x0);
2032 POSTING_READ(GTIER);
2033
2034 if (HAS_PCH_NOP(dev))
2035 return;
2036
2037 /* south display irq */
2038 I915_WRITE(SDEIMR, 0xffffffff);
2039 /*
2040 * SDEIER is also touched by the interrupt handler to work around missed
2041 * PCH interrupts. Hence we can't update it after the interrupt handler
2042 * is enabled - instead we unconditionally enable all PCH interrupt
2043 * sources here, but then only unmask them as needed with SDEIMR.
2044 */
2045 I915_WRITE(SDEIER, 0xffffffff);
2046 POSTING_READ(SDEIER);
2047 }
2048
2049 static void valleyview_irq_preinstall(struct drm_device *dev)
2050 {
2051 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2052 int pipe;
2053
2054 atomic_set(&dev_priv->irq_received, 0);
2055
2056 /* VLV magic */
2057 I915_WRITE(VLV_IMR, 0);
2058 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2059 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2060 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2061
2062 /* and GT */
2063 I915_WRITE(GTIIR, I915_READ(GTIIR));
2064 I915_WRITE(GTIIR, I915_READ(GTIIR));
2065 I915_WRITE(GTIMR, 0xffffffff);
2066 I915_WRITE(GTIER, 0x0);
2067 POSTING_READ(GTIER);
2068
2069 I915_WRITE(DPINVGTT, 0xff);
2070
2071 I915_WRITE(PORT_HOTPLUG_EN, 0);
2072 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2073 for_each_pipe(pipe)
2074 I915_WRITE(PIPESTAT(pipe), 0xffff);
2075 I915_WRITE(VLV_IIR, 0xffffffff);
2076 I915_WRITE(VLV_IMR, 0xffffffff);
2077 I915_WRITE(VLV_IER, 0x0);
2078 POSTING_READ(VLV_IER);
2079 }
2080
2081 static void ibx_hpd_irq_setup(struct drm_device *dev)
2082 {
2083 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2084 struct drm_mode_config *mode_config = &dev->mode_config;
2085 struct intel_encoder *intel_encoder;
2086 u32 mask = ~I915_READ(SDEIMR);
2087 u32 hotplug;
2088
2089 if (HAS_PCH_IBX(dev)) {
2090 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2091 mask |= hpd_ibx[intel_encoder->hpd_pin];
2092 } else {
2093 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2094 mask |= hpd_cpt[intel_encoder->hpd_pin];
2095 }
2096
2097 I915_WRITE(SDEIMR, ~mask);
2098
2099 /*
2100 * Enable digital hotplug on the PCH, and configure the DP short pulse
2101 * duration to 2ms (which is the minimum in the Display Port spec)
2102 *
2103 * This register is the same on all known PCH chips.
2104 */
2105 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2106 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2107 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2108 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2109 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2110 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2111 }
2112
2113 static void ibx_irq_postinstall(struct drm_device *dev)
2114 {
2115 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2116 u32 mask;
2117
2118 if (HAS_PCH_IBX(dev))
2119 mask = SDE_GMBUS | SDE_AUX_MASK;
2120 else
2121 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
2122
2123 if (HAS_PCH_NOP(dev))
2124 return;
2125
2126 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2127 I915_WRITE(SDEIMR, ~mask);
2128 }
2129
2130 static int ironlake_irq_postinstall(struct drm_device *dev)
2131 {
2132 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2133 /* enable kind of interrupts always enabled */
2134 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2135 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2136 DE_AUX_CHANNEL_A;
2137 u32 render_irqs;
2138
2139 dev_priv->irq_mask = ~display_mask;
2140
2141 /* should always can generate irq */
2142 I915_WRITE(DEIIR, I915_READ(DEIIR));
2143 I915_WRITE(DEIMR, dev_priv->irq_mask);
2144 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
2145 POSTING_READ(DEIER);
2146
2147 dev_priv->gt_irq_mask = ~0;
2148
2149 I915_WRITE(GTIIR, I915_READ(GTIIR));
2150 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2151
2152 if (IS_GEN6(dev))
2153 render_irqs =
2154 GT_USER_INTERRUPT |
2155 GEN6_BSD_USER_INTERRUPT |
2156 GEN6_BLITTER_USER_INTERRUPT;
2157 else
2158 render_irqs =
2159 GT_USER_INTERRUPT |
2160 GT_PIPE_NOTIFY |
2161 GT_BSD_USER_INTERRUPT;
2162 I915_WRITE(GTIER, render_irqs);
2163 POSTING_READ(GTIER);
2164
2165 ibx_irq_postinstall(dev);
2166
2167 if (IS_IRONLAKE_M(dev)) {
2168 /* Clear & enable PCU event interrupts */
2169 I915_WRITE(DEIIR, DE_PCU_EVENT);
2170 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
2171 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2172 }
2173
2174 return 0;
2175 }
2176
2177 static int ivybridge_irq_postinstall(struct drm_device *dev)
2178 {
2179 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2180 /* enable kind of interrupts always enabled */
2181 u32 display_mask =
2182 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
2183 DE_PLANEC_FLIP_DONE_IVB |
2184 DE_PLANEB_FLIP_DONE_IVB |
2185 DE_PLANEA_FLIP_DONE_IVB |
2186 DE_AUX_CHANNEL_A_IVB;
2187 u32 render_irqs;
2188
2189 dev_priv->irq_mask = ~display_mask;
2190
2191 /* should always can generate irq */
2192 I915_WRITE(DEIIR, I915_READ(DEIIR));
2193 I915_WRITE(DEIMR, dev_priv->irq_mask);
2194 I915_WRITE(DEIER,
2195 display_mask |
2196 DE_PIPEC_VBLANK_IVB |
2197 DE_PIPEB_VBLANK_IVB |
2198 DE_PIPEA_VBLANK_IVB);
2199 POSTING_READ(DEIER);
2200
2201 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
2202
2203 I915_WRITE(GTIIR, I915_READ(GTIIR));
2204 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2205
2206 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2207 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
2208 I915_WRITE(GTIER, render_irqs);
2209 POSTING_READ(GTIER);
2210
2211 ibx_irq_postinstall(dev);
2212
2213 return 0;
2214 }
2215
2216 static int valleyview_irq_postinstall(struct drm_device *dev)
2217 {
2218 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2219 u32 enable_mask;
2220 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
2221 u32 render_irqs;
2222 u16 msid;
2223
2224 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2225 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2226 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2227 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2228 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2229
2230 /*
2231 *Leave vblank interrupts masked initially. enable/disable will
2232 * toggle them based on usage.
2233 */
2234 dev_priv->irq_mask = (~enable_mask) |
2235 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2236 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2237
2238 /* Hack for broken MSIs on VLV */
2239 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
2240 pci_read_config_word(dev->pdev, 0x98, &msid);
2241 msid &= 0xff; /* mask out delivery bits */
2242 msid |= (1<<14);
2243 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
2244
2245 I915_WRITE(PORT_HOTPLUG_EN, 0);
2246 POSTING_READ(PORT_HOTPLUG_EN);
2247
2248 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2249 I915_WRITE(VLV_IER, enable_mask);
2250 I915_WRITE(VLV_IIR, 0xffffffff);
2251 I915_WRITE(PIPESTAT(0), 0xffff);
2252 I915_WRITE(PIPESTAT(1), 0xffff);
2253 POSTING_READ(VLV_IER);
2254
2255 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
2256 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2257 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2258
2259 I915_WRITE(VLV_IIR, 0xffffffff);
2260 I915_WRITE(VLV_IIR, 0xffffffff);
2261
2262 I915_WRITE(GTIIR, I915_READ(GTIIR));
2263 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2264
2265 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2266 GEN6_BLITTER_USER_INTERRUPT;
2267 I915_WRITE(GTIER, render_irqs);
2268 POSTING_READ(GTIER);
2269
2270 /* ack & enable invalid PTE error interrupts */
2271 #if 0 /* FIXME: add support to irq handler for checking these bits */
2272 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2273 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2274 #endif
2275
2276 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2277
2278 return 0;
2279 }
2280
2281 static void valleyview_irq_uninstall(struct drm_device *dev)
2282 {
2283 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2284 int pipe;
2285
2286 if (!dev_priv)
2287 return;
2288
2289 for_each_pipe(pipe)
2290 I915_WRITE(PIPESTAT(pipe), 0xffff);
2291
2292 I915_WRITE(HWSTAM, 0xffffffff);
2293 I915_WRITE(PORT_HOTPLUG_EN, 0);
2294 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2295 for_each_pipe(pipe)
2296 I915_WRITE(PIPESTAT(pipe), 0xffff);
2297 I915_WRITE(VLV_IIR, 0xffffffff);
2298 I915_WRITE(VLV_IMR, 0xffffffff);
2299 I915_WRITE(VLV_IER, 0x0);
2300 POSTING_READ(VLV_IER);
2301 }
2302
2303 static void ironlake_irq_uninstall(struct drm_device *dev)
2304 {
2305 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2306
2307 if (!dev_priv)
2308 return;
2309
2310 I915_WRITE(HWSTAM, 0xffffffff);
2311
2312 I915_WRITE(DEIMR, 0xffffffff);
2313 I915_WRITE(DEIER, 0x0);
2314 I915_WRITE(DEIIR, I915_READ(DEIIR));
2315
2316 I915_WRITE(GTIMR, 0xffffffff);
2317 I915_WRITE(GTIER, 0x0);
2318 I915_WRITE(GTIIR, I915_READ(GTIIR));
2319
2320 if (HAS_PCH_NOP(dev))
2321 return;
2322
2323 I915_WRITE(SDEIMR, 0xffffffff);
2324 I915_WRITE(SDEIER, 0x0);
2325 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2326 }
2327
2328 static void i8xx_irq_preinstall(struct drm_device * dev)
2329 {
2330 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2331 int pipe;
2332
2333 atomic_set(&dev_priv->irq_received, 0);
2334
2335 for_each_pipe(pipe)
2336 I915_WRITE(PIPESTAT(pipe), 0);
2337 I915_WRITE16(IMR, 0xffff);
2338 I915_WRITE16(IER, 0x0);
2339 POSTING_READ16(IER);
2340 }
2341
2342 static int i8xx_irq_postinstall(struct drm_device *dev)
2343 {
2344 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2345
2346 I915_WRITE16(EMR,
2347 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2348
2349 /* Unmask the interrupts that we always want on. */
2350 dev_priv->irq_mask =
2351 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2352 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2353 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2354 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2355 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2356 I915_WRITE16(IMR, dev_priv->irq_mask);
2357
2358 I915_WRITE16(IER,
2359 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2360 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2361 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2362 I915_USER_INTERRUPT);
2363 POSTING_READ16(IER);
2364
2365 return 0;
2366 }
2367
2368 /*
2369 * Returns true when a page flip has completed.
2370 */
2371 static bool i8xx_handle_vblank(struct drm_device *dev,
2372 int pipe, u16 iir)
2373 {
2374 drm_i915_private_t *dev_priv = dev->dev_private;
2375 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2376
2377 if (!drm_handle_vblank(dev, pipe))
2378 return false;
2379
2380 if ((iir & flip_pending) == 0)
2381 return false;
2382
2383 intel_prepare_page_flip(dev, pipe);
2384
2385 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2386 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2387 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2388 * the flip is completed (no longer pending). Since this doesn't raise
2389 * an interrupt per se, we watch for the change at vblank.
2390 */
2391 if (I915_READ16(ISR) & flip_pending)
2392 return false;
2393
2394 intel_finish_page_flip(dev, pipe);
2395
2396 return true;
2397 }
2398
2399 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
2400 {
2401 struct drm_device *dev = (struct drm_device *) arg;
2402 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2403 u16 iir, new_iir;
2404 u32 pipe_stats[2];
2405 unsigned long irqflags;
2406 int irq_received;
2407 int pipe;
2408 u16 flip_mask =
2409 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2410 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2411
2412 atomic_inc(&dev_priv->irq_received);
2413
2414 iir = I915_READ16(IIR);
2415 if (iir == 0)
2416 return IRQ_NONE;
2417
2418 while (iir & ~flip_mask) {
2419 /* Can't rely on pipestat interrupt bit in iir as it might
2420 * have been cleared after the pipestat interrupt was received.
2421 * It doesn't set the bit in iir again, but it still produces
2422 * interrupts (for non-MSI).
2423 */
2424 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2425 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2426 i915_handle_error(dev, false);
2427
2428 for_each_pipe(pipe) {
2429 int reg = PIPESTAT(pipe);
2430 pipe_stats[pipe] = I915_READ(reg);
2431
2432 /*
2433 * Clear the PIPE*STAT regs before the IIR
2434 */
2435 if (pipe_stats[pipe] & 0x8000ffff) {
2436 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2437 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2438 pipe_name(pipe));
2439 I915_WRITE(reg, pipe_stats[pipe]);
2440 irq_received = 1;
2441 }
2442 }
2443 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2444
2445 I915_WRITE16(IIR, iir & ~flip_mask);
2446 new_iir = I915_READ16(IIR); /* Flush posted writes */
2447
2448 i915_update_dri1_breadcrumb(dev);
2449
2450 if (iir & I915_USER_INTERRUPT)
2451 notify_ring(dev, &dev_priv->ring[RCS]);
2452
2453 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2454 i8xx_handle_vblank(dev, 0, iir))
2455 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
2456
2457 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2458 i8xx_handle_vblank(dev, 1, iir))
2459 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
2460
2461 iir = new_iir;
2462 }
2463
2464 return IRQ_HANDLED;
2465 }
2466
2467 static void i8xx_irq_uninstall(struct drm_device * dev)
2468 {
2469 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2470 int pipe;
2471
2472 for_each_pipe(pipe) {
2473 /* Clear enable bits; then clear status bits */
2474 I915_WRITE(PIPESTAT(pipe), 0);
2475 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2476 }
2477 I915_WRITE16(IMR, 0xffff);
2478 I915_WRITE16(IER, 0x0);
2479 I915_WRITE16(IIR, I915_READ16(IIR));
2480 }
2481
2482 static void i915_irq_preinstall(struct drm_device * dev)
2483 {
2484 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2485 int pipe;
2486
2487 atomic_set(&dev_priv->irq_received, 0);
2488
2489 if (I915_HAS_HOTPLUG(dev)) {
2490 I915_WRITE(PORT_HOTPLUG_EN, 0);
2491 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2492 }
2493
2494 I915_WRITE16(HWSTAM, 0xeffe);
2495 for_each_pipe(pipe)
2496 I915_WRITE(PIPESTAT(pipe), 0);
2497 I915_WRITE(IMR, 0xffffffff);
2498 I915_WRITE(IER, 0x0);
2499 POSTING_READ(IER);
2500 }
2501
2502 static int i915_irq_postinstall(struct drm_device *dev)
2503 {
2504 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2505 u32 enable_mask;
2506
2507 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2508
2509 /* Unmask the interrupts that we always want on. */
2510 dev_priv->irq_mask =
2511 ~(I915_ASLE_INTERRUPT |
2512 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2513 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2514 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2515 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2516 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2517
2518 enable_mask =
2519 I915_ASLE_INTERRUPT |
2520 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2521 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2522 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2523 I915_USER_INTERRUPT;
2524
2525 if (I915_HAS_HOTPLUG(dev)) {
2526 I915_WRITE(PORT_HOTPLUG_EN, 0);
2527 POSTING_READ(PORT_HOTPLUG_EN);
2528
2529 /* Enable in IER... */
2530 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2531 /* and unmask in IMR */
2532 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2533 }
2534
2535 I915_WRITE(IMR, dev_priv->irq_mask);
2536 I915_WRITE(IER, enable_mask);
2537 POSTING_READ(IER);
2538
2539 intel_opregion_enable_asle(dev);
2540
2541 return 0;
2542 }
2543
2544 /*
2545 * Returns true when a page flip has completed.
2546 */
2547 static bool i915_handle_vblank(struct drm_device *dev,
2548 int plane, int pipe, u32 iir)
2549 {
2550 drm_i915_private_t *dev_priv = dev->dev_private;
2551 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
2552
2553 if (!drm_handle_vblank(dev, pipe))
2554 return false;
2555
2556 if ((iir & flip_pending) == 0)
2557 return false;
2558
2559 intel_prepare_page_flip(dev, plane);
2560
2561 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2562 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2563 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2564 * the flip is completed (no longer pending). Since this doesn't raise
2565 * an interrupt per se, we watch for the change at vblank.
2566 */
2567 if (I915_READ(ISR) & flip_pending)
2568 return false;
2569
2570 intel_finish_page_flip(dev, pipe);
2571
2572 return true;
2573 }
2574
2575 static irqreturn_t i915_irq_handler(int irq, void *arg)
2576 {
2577 struct drm_device *dev = (struct drm_device *) arg;
2578 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2579 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2580 unsigned long irqflags;
2581 u32 flip_mask =
2582 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2583 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2584 int pipe, ret = IRQ_NONE;
2585
2586 atomic_inc(&dev_priv->irq_received);
2587
2588 iir = I915_READ(IIR);
2589 do {
2590 bool irq_received = (iir & ~flip_mask) != 0;
2591 bool blc_event = false;
2592
2593 /* Can't rely on pipestat interrupt bit in iir as it might
2594 * have been cleared after the pipestat interrupt was received.
2595 * It doesn't set the bit in iir again, but it still produces
2596 * interrupts (for non-MSI).
2597 */
2598 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2599 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2600 i915_handle_error(dev, false);
2601
2602 for_each_pipe(pipe) {
2603 int reg = PIPESTAT(pipe);
2604 pipe_stats[pipe] = I915_READ(reg);
2605
2606 /* Clear the PIPE*STAT regs before the IIR */
2607 if (pipe_stats[pipe] & 0x8000ffff) {
2608 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2609 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2610 pipe_name(pipe));
2611 I915_WRITE(reg, pipe_stats[pipe]);
2612 irq_received = true;
2613 }
2614 }
2615 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2616
2617 if (!irq_received)
2618 break;
2619
2620 /* Consume port. Then clear IIR or we'll miss events */
2621 if ((I915_HAS_HOTPLUG(dev)) &&
2622 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2623 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2624
2625 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2626 hotplug_status);
2627 if (hotplug_status & HOTPLUG_INT_STATUS_I915)
2628 queue_work(dev_priv->wq,
2629 &dev_priv->hotplug_work);
2630
2631 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2632 POSTING_READ(PORT_HOTPLUG_STAT);
2633 }
2634
2635 I915_WRITE(IIR, iir & ~flip_mask);
2636 new_iir = I915_READ(IIR); /* Flush posted writes */
2637
2638 if (iir & I915_USER_INTERRUPT)
2639 notify_ring(dev, &dev_priv->ring[RCS]);
2640
2641 for_each_pipe(pipe) {
2642 int plane = pipe;
2643 if (IS_MOBILE(dev))
2644 plane = !plane;
2645
2646 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2647 i915_handle_vblank(dev, plane, pipe, iir))
2648 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
2649
2650 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2651 blc_event = true;
2652 }
2653
2654 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2655 intel_opregion_asle_intr(dev);
2656
2657 /* With MSI, interrupts are only generated when iir
2658 * transitions from zero to nonzero. If another bit got
2659 * set while we were handling the existing iir bits, then
2660 * we would never get another interrupt.
2661 *
2662 * This is fine on non-MSI as well, as if we hit this path
2663 * we avoid exiting the interrupt handler only to generate
2664 * another one.
2665 *
2666 * Note that for MSI this could cause a stray interrupt report
2667 * if an interrupt landed in the time between writing IIR and
2668 * the posting read. This should be rare enough to never
2669 * trigger the 99% of 100,000 interrupts test for disabling
2670 * stray interrupts.
2671 */
2672 ret = IRQ_HANDLED;
2673 iir = new_iir;
2674 } while (iir & ~flip_mask);
2675
2676 i915_update_dri1_breadcrumb(dev);
2677
2678 return ret;
2679 }
2680
2681 static void i915_irq_uninstall(struct drm_device * dev)
2682 {
2683 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2684 int pipe;
2685
2686 if (I915_HAS_HOTPLUG(dev)) {
2687 I915_WRITE(PORT_HOTPLUG_EN, 0);
2688 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2689 }
2690
2691 I915_WRITE16(HWSTAM, 0xffff);
2692 for_each_pipe(pipe) {
2693 /* Clear enable bits; then clear status bits */
2694 I915_WRITE(PIPESTAT(pipe), 0);
2695 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2696 }
2697 I915_WRITE(IMR, 0xffffffff);
2698 I915_WRITE(IER, 0x0);
2699
2700 I915_WRITE(IIR, I915_READ(IIR));
2701 }
2702
2703 static void i965_irq_preinstall(struct drm_device * dev)
2704 {
2705 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2706 int pipe;
2707
2708 atomic_set(&dev_priv->irq_received, 0);
2709
2710 I915_WRITE(PORT_HOTPLUG_EN, 0);
2711 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2712
2713 I915_WRITE(HWSTAM, 0xeffe);
2714 for_each_pipe(pipe)
2715 I915_WRITE(PIPESTAT(pipe), 0);
2716 I915_WRITE(IMR, 0xffffffff);
2717 I915_WRITE(IER, 0x0);
2718 POSTING_READ(IER);
2719 }
2720
2721 static int i965_irq_postinstall(struct drm_device *dev)
2722 {
2723 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2724 u32 enable_mask;
2725 u32 error_mask;
2726
2727 /* Unmask the interrupts that we always want on. */
2728 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2729 I915_DISPLAY_PORT_INTERRUPT |
2730 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2731 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2732 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2733 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2734 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2735
2736 enable_mask = ~dev_priv->irq_mask;
2737 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2738 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
2739 enable_mask |= I915_USER_INTERRUPT;
2740
2741 if (IS_G4X(dev))
2742 enable_mask |= I915_BSD_USER_INTERRUPT;
2743
2744 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2745
2746 /*
2747 * Enable some error detection, note the instruction error mask
2748 * bit is reserved, so we leave it masked.
2749 */
2750 if (IS_G4X(dev)) {
2751 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2752 GM45_ERROR_MEM_PRIV |
2753 GM45_ERROR_CP_PRIV |
2754 I915_ERROR_MEMORY_REFRESH);
2755 } else {
2756 error_mask = ~(I915_ERROR_PAGE_TABLE |
2757 I915_ERROR_MEMORY_REFRESH);
2758 }
2759 I915_WRITE(EMR, error_mask);
2760
2761 I915_WRITE(IMR, dev_priv->irq_mask);
2762 I915_WRITE(IER, enable_mask);
2763 POSTING_READ(IER);
2764
2765 I915_WRITE(PORT_HOTPLUG_EN, 0);
2766 POSTING_READ(PORT_HOTPLUG_EN);
2767
2768 intel_opregion_enable_asle(dev);
2769
2770 return 0;
2771 }
2772
2773 static void i915_hpd_irq_setup(struct drm_device *dev)
2774 {
2775 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2776 struct drm_mode_config *mode_config = &dev->mode_config;
2777 struct intel_encoder *encoder;
2778 u32 hotplug_en;
2779
2780 if (I915_HAS_HOTPLUG(dev)) {
2781 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2782 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
2783 /* Note HDMI and DP share hotplug bits */
2784 /* enable bits are the same for all generations */
2785 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
2786 hotplug_en |= hpd_mask_i915[encoder->hpd_pin];
2787 /* Programming the CRT detection parameters tends
2788 to generate a spurious hotplug event about three
2789 seconds later. So just do it once.
2790 */
2791 if (IS_G4X(dev))
2792 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2793 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
2794 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2795
2796 /* Ignore TV since it's buggy */
2797 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2798 }
2799 }
2800
2801 static irqreturn_t i965_irq_handler(int irq, void *arg)
2802 {
2803 struct drm_device *dev = (struct drm_device *) arg;
2804 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2805 u32 iir, new_iir;
2806 u32 pipe_stats[I915_MAX_PIPES];
2807 unsigned long irqflags;
2808 int irq_received;
2809 int ret = IRQ_NONE, pipe;
2810 u32 flip_mask =
2811 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2812 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2813
2814 atomic_inc(&dev_priv->irq_received);
2815
2816 iir = I915_READ(IIR);
2817
2818 for (;;) {
2819 bool blc_event = false;
2820
2821 irq_received = (iir & ~flip_mask) != 0;
2822
2823 /* Can't rely on pipestat interrupt bit in iir as it might
2824 * have been cleared after the pipestat interrupt was received.
2825 * It doesn't set the bit in iir again, but it still produces
2826 * interrupts (for non-MSI).
2827 */
2828 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2829 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2830 i915_handle_error(dev, false);
2831
2832 for_each_pipe(pipe) {
2833 int reg = PIPESTAT(pipe);
2834 pipe_stats[pipe] = I915_READ(reg);
2835
2836 /*
2837 * Clear the PIPE*STAT regs before the IIR
2838 */
2839 if (pipe_stats[pipe] & 0x8000ffff) {
2840 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2841 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2842 pipe_name(pipe));
2843 I915_WRITE(reg, pipe_stats[pipe]);
2844 irq_received = 1;
2845 }
2846 }
2847 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2848
2849 if (!irq_received)
2850 break;
2851
2852 ret = IRQ_HANDLED;
2853
2854 /* Consume port. Then clear IIR or we'll miss events */
2855 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
2856 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2857
2858 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2859 hotplug_status);
2860 if (hotplug_status & (IS_G4X(dev) ?
2861 HOTPLUG_INT_STATUS_G4X :
2862 HOTPLUG_INT_STATUS_I965))
2863 queue_work(dev_priv->wq,
2864 &dev_priv->hotplug_work);
2865
2866 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2867 I915_READ(PORT_HOTPLUG_STAT);
2868 }
2869
2870 I915_WRITE(IIR, iir & ~flip_mask);
2871 new_iir = I915_READ(IIR); /* Flush posted writes */
2872
2873 if (iir & I915_USER_INTERRUPT)
2874 notify_ring(dev, &dev_priv->ring[RCS]);
2875 if (iir & I915_BSD_USER_INTERRUPT)
2876 notify_ring(dev, &dev_priv->ring[VCS]);
2877
2878 for_each_pipe(pipe) {
2879 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2880 i915_handle_vblank(dev, pipe, pipe, iir))
2881 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
2882
2883 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2884 blc_event = true;
2885 }
2886
2887
2888 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2889 intel_opregion_asle_intr(dev);
2890
2891 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2892 gmbus_irq_handler(dev);
2893
2894 /* With MSI, interrupts are only generated when iir
2895 * transitions from zero to nonzero. If another bit got
2896 * set while we were handling the existing iir bits, then
2897 * we would never get another interrupt.
2898 *
2899 * This is fine on non-MSI as well, as if we hit this path
2900 * we avoid exiting the interrupt handler only to generate
2901 * another one.
2902 *
2903 * Note that for MSI this could cause a stray interrupt report
2904 * if an interrupt landed in the time between writing IIR and
2905 * the posting read. This should be rare enough to never
2906 * trigger the 99% of 100,000 interrupts test for disabling
2907 * stray interrupts.
2908 */
2909 iir = new_iir;
2910 }
2911
2912 i915_update_dri1_breadcrumb(dev);
2913
2914 return ret;
2915 }
2916
2917 static void i965_irq_uninstall(struct drm_device * dev)
2918 {
2919 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2920 int pipe;
2921
2922 if (!dev_priv)
2923 return;
2924
2925 I915_WRITE(PORT_HOTPLUG_EN, 0);
2926 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2927
2928 I915_WRITE(HWSTAM, 0xffffffff);
2929 for_each_pipe(pipe)
2930 I915_WRITE(PIPESTAT(pipe), 0);
2931 I915_WRITE(IMR, 0xffffffff);
2932 I915_WRITE(IER, 0x0);
2933
2934 for_each_pipe(pipe)
2935 I915_WRITE(PIPESTAT(pipe),
2936 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2937 I915_WRITE(IIR, I915_READ(IIR));
2938 }
2939
2940 void intel_irq_init(struct drm_device *dev)
2941 {
2942 struct drm_i915_private *dev_priv = dev->dev_private;
2943
2944 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2945 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
2946 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
2947 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
2948
2949 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
2950 i915_hangcheck_elapsed,
2951 (unsigned long) dev);
2952
2953 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
2954
2955 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2956 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2957 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
2958 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2959 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2960 }
2961
2962 if (drm_core_check_feature(dev, DRIVER_MODESET))
2963 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2964 else
2965 dev->driver->get_vblank_timestamp = NULL;
2966 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2967
2968 if (IS_VALLEYVIEW(dev)) {
2969 dev->driver->irq_handler = valleyview_irq_handler;
2970 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2971 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2972 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2973 dev->driver->enable_vblank = valleyview_enable_vblank;
2974 dev->driver->disable_vblank = valleyview_disable_vblank;
2975 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
2976 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2977 /* Share pre & uninstall handlers with ILK/SNB */
2978 dev->driver->irq_handler = ivybridge_irq_handler;
2979 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2980 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2981 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2982 dev->driver->enable_vblank = ivybridge_enable_vblank;
2983 dev->driver->disable_vblank = ivybridge_disable_vblank;
2984 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
2985 } else if (HAS_PCH_SPLIT(dev)) {
2986 dev->driver->irq_handler = ironlake_irq_handler;
2987 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2988 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2989 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2990 dev->driver->enable_vblank = ironlake_enable_vblank;
2991 dev->driver->disable_vblank = ironlake_disable_vblank;
2992 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
2993 } else {
2994 if (INTEL_INFO(dev)->gen == 2) {
2995 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2996 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2997 dev->driver->irq_handler = i8xx_irq_handler;
2998 dev->driver->irq_uninstall = i8xx_irq_uninstall;
2999 } else if (INTEL_INFO(dev)->gen == 3) {
3000 dev->driver->irq_preinstall = i915_irq_preinstall;
3001 dev->driver->irq_postinstall = i915_irq_postinstall;
3002 dev->driver->irq_uninstall = i915_irq_uninstall;
3003 dev->driver->irq_handler = i915_irq_handler;
3004 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3005 } else {
3006 dev->driver->irq_preinstall = i965_irq_preinstall;
3007 dev->driver->irq_postinstall = i965_irq_postinstall;
3008 dev->driver->irq_uninstall = i965_irq_uninstall;
3009 dev->driver->irq_handler = i965_irq_handler;
3010 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3011 }
3012 dev->driver->enable_vblank = i915_enable_vblank;
3013 dev->driver->disable_vblank = i915_disable_vblank;
3014 }
3015 }
3016
3017 void intel_hpd_init(struct drm_device *dev)
3018 {
3019 struct drm_i915_private *dev_priv = dev->dev_private;
3020
3021 if (dev_priv->display.hpd_irq_setup)
3022 dev_priv->display.hpd_irq_setup(dev);
3023 }
Linux kernel - Deliverables
This page took 0.107764 seconds and 5 git commands to generate.