1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
41 * DOC: interrupt handling
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
48 static const u32 hpd_ibx
[] = {
49 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
50 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
51 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
52 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
53 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
56 static const u32 hpd_cpt
[] = {
57 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
58 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
59 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
60 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
61 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
64 static const u32 hpd_mask_i915
[] = {
65 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
66 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
67 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
68 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
69 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
70 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
73 static const u32 hpd_status_g4x
[] = {
74 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
75 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
76 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
77 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
78 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
79 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
82 static const u32 hpd_status_i915
[] = { /* i915 and valleyview are the same */
83 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
84 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
85 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
86 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
87 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
88 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
91 /* IIR can theoretically queue up two events. Be paranoid. */
92 #define GEN8_IRQ_RESET_NDX(type, which) do { \
93 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
94 POSTING_READ(GEN8_##type##_IMR(which)); \
95 I915_WRITE(GEN8_##type##_IER(which), 0); \
96 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
97 POSTING_READ(GEN8_##type##_IIR(which)); \
98 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
99 POSTING_READ(GEN8_##type##_IIR(which)); \
102 #define GEN5_IRQ_RESET(type) do { \
103 I915_WRITE(type##IMR, 0xffffffff); \
104 POSTING_READ(type##IMR); \
105 I915_WRITE(type##IER, 0); \
106 I915_WRITE(type##IIR, 0xffffffff); \
107 POSTING_READ(type##IIR); \
108 I915_WRITE(type##IIR, 0xffffffff); \
109 POSTING_READ(type##IIR); \
113 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
115 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
116 u32 val = I915_READ(reg); \
118 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
120 I915_WRITE((reg), 0xffffffff); \
122 I915_WRITE((reg), 0xffffffff); \
127 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
128 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
129 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
130 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
131 POSTING_READ(GEN8_##type##_IMR(which)); \
134 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
135 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
136 I915_WRITE(type##IER, (ier_val)); \
137 I915_WRITE(type##IMR, (imr_val)); \
138 POSTING_READ(type##IMR); \
141 /* For display hotplug interrupt */
143 ironlake_enable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
)
145 assert_spin_locked(&dev_priv
->irq_lock
);
147 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
150 if ((dev_priv
->irq_mask
& mask
) != 0) {
151 dev_priv
->irq_mask
&= ~mask
;
152 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
158 ironlake_disable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
)
160 assert_spin_locked(&dev_priv
->irq_lock
);
162 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
165 if ((dev_priv
->irq_mask
& mask
) != mask
) {
166 dev_priv
->irq_mask
|= mask
;
167 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
173 * ilk_update_gt_irq - update GTIMR
174 * @dev_priv: driver private
175 * @interrupt_mask: mask of interrupt bits to update
176 * @enabled_irq_mask: mask of interrupt bits to enable
178 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
179 uint32_t interrupt_mask
,
180 uint32_t enabled_irq_mask
)
182 assert_spin_locked(&dev_priv
->irq_lock
);
184 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
187 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
188 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
189 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
193 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
195 ilk_update_gt_irq(dev_priv
, mask
, mask
);
198 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
200 ilk_update_gt_irq(dev_priv
, mask
, 0);
204 * snb_update_pm_irq - update GEN6_PMIMR
205 * @dev_priv: driver private
206 * @interrupt_mask: mask of interrupt bits to update
207 * @enabled_irq_mask: mask of interrupt bits to enable
209 static void snb_update_pm_irq(struct drm_i915_private
*dev_priv
,
210 uint32_t interrupt_mask
,
211 uint32_t enabled_irq_mask
)
215 assert_spin_locked(&dev_priv
->irq_lock
);
217 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
220 new_val
= dev_priv
->pm_irq_mask
;
221 new_val
&= ~interrupt_mask
;
222 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
224 if (new_val
!= dev_priv
->pm_irq_mask
) {
225 dev_priv
->pm_irq_mask
= new_val
;
226 I915_WRITE(GEN6_PMIMR
, dev_priv
->pm_irq_mask
);
227 POSTING_READ(GEN6_PMIMR
);
231 void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
233 snb_update_pm_irq(dev_priv
, mask
, mask
);
236 void gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
238 snb_update_pm_irq(dev_priv
, mask
, 0);
242 * bdw_update_pm_irq - update GT interrupt 2
243 * @dev_priv: driver private
244 * @interrupt_mask: mask of interrupt bits to update
245 * @enabled_irq_mask: mask of interrupt bits to enable
247 * Copied from the snb function, updated with relevant register offsets
249 static void bdw_update_pm_irq(struct drm_i915_private
*dev_priv
,
250 uint32_t interrupt_mask
,
251 uint32_t enabled_irq_mask
)
255 assert_spin_locked(&dev_priv
->irq_lock
);
257 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
260 new_val
= dev_priv
->pm_irq_mask
;
261 new_val
&= ~interrupt_mask
;
262 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
264 if (new_val
!= dev_priv
->pm_irq_mask
) {
265 dev_priv
->pm_irq_mask
= new_val
;
266 I915_WRITE(GEN8_GT_IMR(2), dev_priv
->pm_irq_mask
);
267 POSTING_READ(GEN8_GT_IMR(2));
271 void gen8_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
273 bdw_update_pm_irq(dev_priv
, mask
, mask
);
276 void gen8_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
278 bdw_update_pm_irq(dev_priv
, mask
, 0);
282 * ibx_display_interrupt_update - update SDEIMR
283 * @dev_priv: driver private
284 * @interrupt_mask: mask of interrupt bits to update
285 * @enabled_irq_mask: mask of interrupt bits to enable
287 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
288 uint32_t interrupt_mask
,
289 uint32_t enabled_irq_mask
)
291 uint32_t sdeimr
= I915_READ(SDEIMR
);
292 sdeimr
&= ~interrupt_mask
;
293 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
295 assert_spin_locked(&dev_priv
->irq_lock
);
297 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
300 I915_WRITE(SDEIMR
, sdeimr
);
301 POSTING_READ(SDEIMR
);
305 __i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
306 u32 enable_mask
, u32 status_mask
)
308 u32 reg
= PIPESTAT(pipe
);
309 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
311 assert_spin_locked(&dev_priv
->irq_lock
);
312 WARN_ON(!intel_irqs_enabled(dev_priv
));
314 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
315 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
316 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
317 pipe_name(pipe
), enable_mask
, status_mask
))
320 if ((pipestat
& enable_mask
) == enable_mask
)
323 dev_priv
->pipestat_irq_mask
[pipe
] |= status_mask
;
325 /* Enable the interrupt, clear any pending status */
326 pipestat
|= enable_mask
| status_mask
;
327 I915_WRITE(reg
, pipestat
);
332 __i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
333 u32 enable_mask
, u32 status_mask
)
335 u32 reg
= PIPESTAT(pipe
);
336 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
338 assert_spin_locked(&dev_priv
->irq_lock
);
339 WARN_ON(!intel_irqs_enabled(dev_priv
));
341 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
342 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
343 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
344 pipe_name(pipe
), enable_mask
, status_mask
))
347 if ((pipestat
& enable_mask
) == 0)
350 dev_priv
->pipestat_irq_mask
[pipe
] &= ~status_mask
;
352 pipestat
&= ~enable_mask
;
353 I915_WRITE(reg
, pipestat
);
357 static u32
vlv_get_pipestat_enable_mask(struct drm_device
*dev
, u32 status_mask
)
359 u32 enable_mask
= status_mask
<< 16;
362 * On pipe A we don't support the PSR interrupt yet,
363 * on pipe B and C the same bit MBZ.
365 if (WARN_ON_ONCE(status_mask
& PIPE_A_PSR_STATUS_VLV
))
368 * On pipe B and C we don't support the PSR interrupt yet, on pipe
369 * A the same bit is for perf counters which we don't use either.
371 if (WARN_ON_ONCE(status_mask
& PIPE_B_PSR_STATUS_VLV
))
374 enable_mask
&= ~(PIPE_FIFO_UNDERRUN_STATUS
|
375 SPRITE0_FLIP_DONE_INT_EN_VLV
|
376 SPRITE1_FLIP_DONE_INT_EN_VLV
);
377 if (status_mask
& SPRITE0_FLIP_DONE_INT_STATUS_VLV
)
378 enable_mask
|= SPRITE0_FLIP_DONE_INT_EN_VLV
;
379 if (status_mask
& SPRITE1_FLIP_DONE_INT_STATUS_VLV
)
380 enable_mask
|= SPRITE1_FLIP_DONE_INT_EN_VLV
;
386 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
391 if (IS_VALLEYVIEW(dev_priv
->dev
))
392 enable_mask
= vlv_get_pipestat_enable_mask(dev_priv
->dev
,
395 enable_mask
= status_mask
<< 16;
396 __i915_enable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
400 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
405 if (IS_VALLEYVIEW(dev_priv
->dev
))
406 enable_mask
= vlv_get_pipestat_enable_mask(dev_priv
->dev
,
409 enable_mask
= status_mask
<< 16;
410 __i915_disable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
414 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
416 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
418 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
420 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
423 spin_lock_irq(&dev_priv
->irq_lock
);
425 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_LEGACY_BLC_EVENT_STATUS
);
426 if (INTEL_INFO(dev
)->gen
>= 4)
427 i915_enable_pipestat(dev_priv
, PIPE_A
,
428 PIPE_LEGACY_BLC_EVENT_STATUS
);
430 spin_unlock_irq(&dev_priv
->irq_lock
);
434 * i915_pipe_enabled - check if a pipe is enabled
436 * @pipe: pipe to check
438 * Reading certain registers when the pipe is disabled can hang the chip.
439 * Use this routine to make sure the PLL is running and the pipe is active
440 * before reading such registers if unsure.
443 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
445 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
447 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
448 /* Locking is horribly broken here, but whatever. */
449 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
450 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
452 return intel_crtc
->active
;
454 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
459 * This timing diagram depicts the video signal in and
460 * around the vertical blanking period.
462 * Assumptions about the fictitious mode used in this example:
464 * vsync_start = vblank_start + 1
465 * vsync_end = vblank_start + 2
466 * vtotal = vblank_start + 3
469 * latch double buffered registers
470 * increment frame counter (ctg+)
471 * generate start of vblank interrupt (gen4+)
474 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
475 * | may be shifted forward 1-3 extra lines via PIPECONF
477 * | | start of vsync:
478 * | | generate vsync interrupt
480 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
481 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
482 * ----va---> <-----------------vb--------------------> <--------va-------------
483 * | | <----vs-----> |
484 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
485 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
486 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
488 * last visible pixel first visible pixel
489 * | increment frame counter (gen3/4)
490 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
492 * x = horizontal active
493 * _ = horizontal blanking
494 * hs = horizontal sync
495 * va = vertical active
496 * vb = vertical blanking
498 * vbs = vblank_start (number)
501 * - most events happen at the start of horizontal sync
502 * - frame start happens at the start of horizontal blank, 1-4 lines
503 * (depending on PIPECONF settings) after the start of vblank
504 * - gen3/4 pixel and frame counter are synchronized with the start
505 * of horizontal active on the first line of vertical active
508 static u32
i8xx_get_vblank_counter(struct drm_device
*dev
, int pipe
)
510 /* Gen2 doesn't have a hardware frame counter */
514 /* Called from drm generic code, passed a 'crtc', which
515 * we use as a pipe index
517 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
519 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
520 unsigned long high_frame
;
521 unsigned long low_frame
;
522 u32 high1
, high2
, low
, pixel
, vbl_start
, hsync_start
, htotal
;
524 if (!i915_pipe_enabled(dev
, pipe
)) {
525 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
526 "pipe %c\n", pipe_name(pipe
));
530 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
531 struct intel_crtc
*intel_crtc
=
532 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
533 const struct drm_display_mode
*mode
=
534 &intel_crtc
->config
.adjusted_mode
;
536 htotal
= mode
->crtc_htotal
;
537 hsync_start
= mode
->crtc_hsync_start
;
538 vbl_start
= mode
->crtc_vblank_start
;
539 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
540 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
542 enum transcoder cpu_transcoder
= (enum transcoder
) pipe
;
544 htotal
= ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff) + 1;
545 hsync_start
= (I915_READ(HSYNC(cpu_transcoder
)) & 0x1fff) + 1;
546 vbl_start
= (I915_READ(VBLANK(cpu_transcoder
)) & 0x1fff) + 1;
547 if ((I915_READ(PIPECONF(cpu_transcoder
)) &
548 PIPECONF_INTERLACE_MASK
) != PIPECONF_PROGRESSIVE
)
549 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
552 /* Convert to pixel count */
555 /* Start of vblank event occurs at start of hsync */
556 vbl_start
-= htotal
- hsync_start
;
558 high_frame
= PIPEFRAME(pipe
);
559 low_frame
= PIPEFRAMEPIXEL(pipe
);
562 * High & low register fields aren't synchronized, so make sure
563 * we get a low value that's stable across two reads of the high
567 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
568 low
= I915_READ(low_frame
);
569 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
570 } while (high1
!= high2
);
572 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
573 pixel
= low
& PIPE_PIXEL_MASK
;
574 low
>>= PIPE_FRAME_LOW_SHIFT
;
577 * The frame counter increments at beginning of active.
578 * Cook up a vblank counter by also checking the pixel
579 * counter against vblank start.
581 return (((high1
<< 8) | low
) + (pixel
>= vbl_start
)) & 0xffffff;
584 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
586 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
587 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
589 if (!i915_pipe_enabled(dev
, pipe
)) {
590 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
591 "pipe %c\n", pipe_name(pipe
));
595 return I915_READ(reg
);
598 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
599 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
601 static int __intel_get_crtc_scanline(struct intel_crtc
*crtc
)
603 struct drm_device
*dev
= crtc
->base
.dev
;
604 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
605 const struct drm_display_mode
*mode
= &crtc
->config
.adjusted_mode
;
606 enum pipe pipe
= crtc
->pipe
;
607 int position
, vtotal
;
609 vtotal
= mode
->crtc_vtotal
;
610 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
614 position
= __raw_i915_read32(dev_priv
, PIPEDSL(pipe
)) & DSL_LINEMASK_GEN2
;
616 position
= __raw_i915_read32(dev_priv
, PIPEDSL(pipe
)) & DSL_LINEMASK_GEN3
;
619 * See update_scanline_offset() for the details on the
620 * scanline_offset adjustment.
622 return (position
+ crtc
->scanline_offset
) % vtotal
;
625 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
626 unsigned int flags
, int *vpos
, int *hpos
,
627 ktime_t
*stime
, ktime_t
*etime
)
629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
630 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
631 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
632 const struct drm_display_mode
*mode
= &intel_crtc
->config
.adjusted_mode
;
634 int vbl_start
, vbl_end
, hsync_start
, htotal
, vtotal
;
637 unsigned long irqflags
;
639 if (!intel_crtc
->active
) {
640 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
641 "pipe %c\n", pipe_name(pipe
));
645 htotal
= mode
->crtc_htotal
;
646 hsync_start
= mode
->crtc_hsync_start
;
647 vtotal
= mode
->crtc_vtotal
;
648 vbl_start
= mode
->crtc_vblank_start
;
649 vbl_end
= mode
->crtc_vblank_end
;
651 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
652 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
657 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
660 * Lock uncore.lock, as we will do multiple timing critical raw
661 * register reads, potentially with preemption disabled, so the
662 * following code must not block on uncore.lock.
664 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
666 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
668 /* Get optional system timestamp before query. */
670 *stime
= ktime_get();
672 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
673 /* No obvious pixelcount register. Only query vertical
674 * scanout position from Display scan line register.
676 position
= __intel_get_crtc_scanline(intel_crtc
);
678 /* Have access to pixelcount since start of frame.
679 * We can split this into vertical and horizontal
682 position
= (__raw_i915_read32(dev_priv
, PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
684 /* convert to pixel counts */
690 * In interlaced modes, the pixel counter counts all pixels,
691 * so one field will have htotal more pixels. In order to avoid
692 * the reported position from jumping backwards when the pixel
693 * counter is beyond the length of the shorter field, just
694 * clamp the position the length of the shorter field. This
695 * matches how the scanline counter based position works since
696 * the scanline counter doesn't count the two half lines.
698 if (position
>= vtotal
)
699 position
= vtotal
- 1;
702 * Start of vblank interrupt is triggered at start of hsync,
703 * just prior to the first active line of vblank. However we
704 * consider lines to start at the leading edge of horizontal
705 * active. So, should we get here before we've crossed into
706 * the horizontal active of the first line in vblank, we would
707 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
708 * always add htotal-hsync_start to the current pixel position.
710 position
= (position
+ htotal
- hsync_start
) % vtotal
;
713 /* Get optional system timestamp after query. */
715 *etime
= ktime_get();
717 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
719 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
721 in_vbl
= position
>= vbl_start
&& position
< vbl_end
;
724 * While in vblank, position will be negative
725 * counting up towards 0 at vbl_end. And outside
726 * vblank, position will be positive counting
729 if (position
>= vbl_start
)
732 position
+= vtotal
- vbl_end
;
734 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
738 *vpos
= position
/ htotal
;
739 *hpos
= position
- (*vpos
* htotal
);
744 ret
|= DRM_SCANOUTPOS_IN_VBLANK
;
749 int intel_get_crtc_scanline(struct intel_crtc
*crtc
)
751 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
752 unsigned long irqflags
;
755 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
756 position
= __intel_get_crtc_scanline(crtc
);
757 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
762 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
764 struct timeval
*vblank_time
,
767 struct drm_crtc
*crtc
;
769 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
770 DRM_ERROR("Invalid crtc %d\n", pipe
);
774 /* Get drm_crtc to timestamp: */
775 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
777 DRM_ERROR("Invalid crtc %d\n", pipe
);
781 if (!crtc
->enabled
) {
782 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
786 /* Helper routine in DRM core does all the work: */
787 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
790 &to_intel_crtc(crtc
)->config
.adjusted_mode
);
793 static bool intel_hpd_irq_event(struct drm_device
*dev
,
794 struct drm_connector
*connector
)
796 enum drm_connector_status old_status
;
798 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
799 old_status
= connector
->status
;
801 connector
->status
= connector
->funcs
->detect(connector
, false);
802 if (old_status
== connector
->status
)
805 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
808 drm_get_connector_status_name(old_status
),
809 drm_get_connector_status_name(connector
->status
));
814 static void i915_digport_work_func(struct work_struct
*work
)
816 struct drm_i915_private
*dev_priv
=
817 container_of(work
, struct drm_i915_private
, dig_port_work
);
818 u32 long_port_mask
, short_port_mask
;
819 struct intel_digital_port
*intel_dig_port
;
823 spin_lock_irq(&dev_priv
->irq_lock
);
824 long_port_mask
= dev_priv
->long_hpd_port_mask
;
825 dev_priv
->long_hpd_port_mask
= 0;
826 short_port_mask
= dev_priv
->short_hpd_port_mask
;
827 dev_priv
->short_hpd_port_mask
= 0;
828 spin_unlock_irq(&dev_priv
->irq_lock
);
830 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
832 bool long_hpd
= false;
833 intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
834 if (!intel_dig_port
|| !intel_dig_port
->hpd_pulse
)
837 if (long_port_mask
& (1 << i
)) {
840 } else if (short_port_mask
& (1 << i
))
844 ret
= intel_dig_port
->hpd_pulse(intel_dig_port
, long_hpd
);
846 /* if we get true fallback to old school hpd */
847 old_bits
|= (1 << intel_dig_port
->base
.hpd_pin
);
853 spin_lock_irq(&dev_priv
->irq_lock
);
854 dev_priv
->hpd_event_bits
|= old_bits
;
855 spin_unlock_irq(&dev_priv
->irq_lock
);
856 schedule_work(&dev_priv
->hotplug_work
);
861 * Handle hotplug events outside the interrupt handler proper.
863 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
865 static void i915_hotplug_work_func(struct work_struct
*work
)
867 struct drm_i915_private
*dev_priv
=
868 container_of(work
, struct drm_i915_private
, hotplug_work
);
869 struct drm_device
*dev
= dev_priv
->dev
;
870 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
871 struct intel_connector
*intel_connector
;
872 struct intel_encoder
*intel_encoder
;
873 struct drm_connector
*connector
;
874 bool hpd_disabled
= false;
875 bool changed
= false;
878 mutex_lock(&mode_config
->mutex
);
879 DRM_DEBUG_KMS("running encoder hotplug functions\n");
881 spin_lock_irq(&dev_priv
->irq_lock
);
883 hpd_event_bits
= dev_priv
->hpd_event_bits
;
884 dev_priv
->hpd_event_bits
= 0;
885 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
886 intel_connector
= to_intel_connector(connector
);
887 if (!intel_connector
->encoder
)
889 intel_encoder
= intel_connector
->encoder
;
890 if (intel_encoder
->hpd_pin
> HPD_NONE
&&
891 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_MARK_DISABLED
&&
892 connector
->polled
== DRM_CONNECTOR_POLL_HPD
) {
893 DRM_INFO("HPD interrupt storm detected on connector %s: "
894 "switching from hotplug detection to polling\n",
896 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
= HPD_DISABLED
;
897 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
898 | DRM_CONNECTOR_POLL_DISCONNECT
;
901 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
902 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
903 connector
->name
, intel_encoder
->hpd_pin
);
906 /* if there were no outputs to poll, poll was disabled,
907 * therefore make sure it's enabled when disabling HPD on
910 drm_kms_helper_poll_enable(dev
);
911 mod_delayed_work(system_wq
, &dev_priv
->hotplug_reenable_work
,
912 msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY
));
915 spin_unlock_irq(&dev_priv
->irq_lock
);
917 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
918 intel_connector
= to_intel_connector(connector
);
919 if (!intel_connector
->encoder
)
921 intel_encoder
= intel_connector
->encoder
;
922 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
923 if (intel_encoder
->hot_plug
)
924 intel_encoder
->hot_plug(intel_encoder
);
925 if (intel_hpd_irq_event(dev
, connector
))
929 mutex_unlock(&mode_config
->mutex
);
932 drm_kms_helper_hotplug_event(dev
);
935 static void ironlake_rps_change_irq_handler(struct drm_device
*dev
)
937 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
938 u32 busy_up
, busy_down
, max_avg
, min_avg
;
941 spin_lock(&mchdev_lock
);
943 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
945 new_delay
= dev_priv
->ips
.cur_delay
;
947 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
948 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
949 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
950 max_avg
= I915_READ(RCBMAXAVG
);
951 min_avg
= I915_READ(RCBMINAVG
);
953 /* Handle RCS change request from hw */
954 if (busy_up
> max_avg
) {
955 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
956 new_delay
= dev_priv
->ips
.cur_delay
- 1;
957 if (new_delay
< dev_priv
->ips
.max_delay
)
958 new_delay
= dev_priv
->ips
.max_delay
;
959 } else if (busy_down
< min_avg
) {
960 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
961 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
962 if (new_delay
> dev_priv
->ips
.min_delay
)
963 new_delay
= dev_priv
->ips
.min_delay
;
966 if (ironlake_set_drps(dev
, new_delay
))
967 dev_priv
->ips
.cur_delay
= new_delay
;
969 spin_unlock(&mchdev_lock
);
974 static void notify_ring(struct drm_device
*dev
,
975 struct intel_engine_cs
*ring
)
977 if (!intel_ring_initialized(ring
))
980 trace_i915_gem_request_complete(ring
);
982 wake_up_all(&ring
->irq_queue
);
983 i915_queue_hangcheck(dev
);
986 static u32
vlv_c0_residency(struct drm_i915_private
*dev_priv
,
987 struct intel_rps_ei
*rps_ei
)
989 u32 cz_ts
, cz_freq_khz
;
990 u32 render_count
, media_count
;
991 u32 elapsed_render
, elapsed_media
, elapsed_time
;
994 cz_ts
= vlv_punit_read(dev_priv
, PUNIT_REG_CZ_TIMESTAMP
);
995 cz_freq_khz
= DIV_ROUND_CLOSEST(dev_priv
->mem_freq
* 1000, 4);
997 render_count
= I915_READ(VLV_RENDER_C0_COUNT_REG
);
998 media_count
= I915_READ(VLV_MEDIA_C0_COUNT_REG
);
1000 if (rps_ei
->cz_clock
== 0) {
1001 rps_ei
->cz_clock
= cz_ts
;
1002 rps_ei
->render_c0
= render_count
;
1003 rps_ei
->media_c0
= media_count
;
1005 return dev_priv
->rps
.cur_freq
;
1008 elapsed_time
= cz_ts
- rps_ei
->cz_clock
;
1009 rps_ei
->cz_clock
= cz_ts
;
1011 elapsed_render
= render_count
- rps_ei
->render_c0
;
1012 rps_ei
->render_c0
= render_count
;
1014 elapsed_media
= media_count
- rps_ei
->media_c0
;
1015 rps_ei
->media_c0
= media_count
;
1017 /* Convert all the counters into common unit of milli sec */
1018 elapsed_time
/= VLV_CZ_CLOCK_TO_MILLI_SEC
;
1019 elapsed_render
/= cz_freq_khz
;
1020 elapsed_media
/= cz_freq_khz
;
1023 * Calculate overall C0 residency percentage
1024 * only if elapsed time is non zero
1028 ((max(elapsed_render
, elapsed_media
) * 100)
1036 * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU
1037 * busy-ness calculated from C0 counters of render & media power wells
1038 * @dev_priv: DRM device private
1041 static int vlv_calc_delay_from_C0_counters(struct drm_i915_private
*dev_priv
)
1043 u32 residency_C0_up
= 0, residency_C0_down
= 0;
1046 dev_priv
->rps
.ei_interrupt_count
++;
1048 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
1051 if (dev_priv
->rps
.up_ei
.cz_clock
== 0) {
1052 vlv_c0_residency(dev_priv
, &dev_priv
->rps
.up_ei
);
1053 vlv_c0_residency(dev_priv
, &dev_priv
->rps
.down_ei
);
1054 return dev_priv
->rps
.cur_freq
;
1059 * To down throttle, C0 residency should be less than down threshold
1060 * for continous EI intervals. So calculate down EI counters
1061 * once in VLV_INT_COUNT_FOR_DOWN_EI
1063 if (dev_priv
->rps
.ei_interrupt_count
== VLV_INT_COUNT_FOR_DOWN_EI
) {
1065 dev_priv
->rps
.ei_interrupt_count
= 0;
1067 residency_C0_down
= vlv_c0_residency(dev_priv
,
1068 &dev_priv
->rps
.down_ei
);
1070 residency_C0_up
= vlv_c0_residency(dev_priv
,
1071 &dev_priv
->rps
.up_ei
);
1074 new_delay
= dev_priv
->rps
.cur_freq
;
1076 adj
= dev_priv
->rps
.last_adj
;
1077 /* C0 residency is greater than UP threshold. Increase Frequency */
1078 if (residency_C0_up
>= VLV_RP_UP_EI_THRESHOLD
) {
1084 if (dev_priv
->rps
.cur_freq
< dev_priv
->rps
.max_freq_softlimit
)
1085 new_delay
= dev_priv
->rps
.cur_freq
+ adj
;
1088 * For better performance, jump directly
1089 * to RPe if we're below it.
1091 if (new_delay
< dev_priv
->rps
.efficient_freq
)
1092 new_delay
= dev_priv
->rps
.efficient_freq
;
1094 } else if (!dev_priv
->rps
.ei_interrupt_count
&&
1095 (residency_C0_down
< VLV_RP_DOWN_EI_THRESHOLD
)) {
1101 * This means, C0 residency is less than down threshold over
1102 * a period of VLV_INT_COUNT_FOR_DOWN_EI. So, reduce the freq
1104 if (dev_priv
->rps
.cur_freq
> dev_priv
->rps
.min_freq_softlimit
)
1105 new_delay
= dev_priv
->rps
.cur_freq
+ adj
;
1111 static void gen6_pm_rps_work(struct work_struct
*work
)
1113 struct drm_i915_private
*dev_priv
=
1114 container_of(work
, struct drm_i915_private
, rps
.work
);
1118 spin_lock_irq(&dev_priv
->irq_lock
);
1119 pm_iir
= dev_priv
->rps
.pm_iir
;
1120 dev_priv
->rps
.pm_iir
= 0;
1121 if (INTEL_INFO(dev_priv
->dev
)->gen
>= 8)
1122 gen8_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
1124 /* Make sure not to corrupt PMIMR state used by ringbuffer */
1125 gen6_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
1127 spin_unlock_irq(&dev_priv
->irq_lock
);
1129 /* Make sure we didn't queue anything we're not going to process. */
1130 WARN_ON(pm_iir
& ~dev_priv
->pm_rps_events
);
1132 if ((pm_iir
& dev_priv
->pm_rps_events
) == 0)
1135 mutex_lock(&dev_priv
->rps
.hw_lock
);
1137 adj
= dev_priv
->rps
.last_adj
;
1138 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
1142 /* CHV needs even encode values */
1143 adj
= IS_CHERRYVIEW(dev_priv
->dev
) ? 2 : 1;
1145 new_delay
= dev_priv
->rps
.cur_freq
+ adj
;
1148 * For better performance, jump directly
1149 * to RPe if we're below it.
1151 if (new_delay
< dev_priv
->rps
.efficient_freq
)
1152 new_delay
= dev_priv
->rps
.efficient_freq
;
1153 } else if (pm_iir
& GEN6_PM_RP_DOWN_TIMEOUT
) {
1154 if (dev_priv
->rps
.cur_freq
> dev_priv
->rps
.efficient_freq
)
1155 new_delay
= dev_priv
->rps
.efficient_freq
;
1157 new_delay
= dev_priv
->rps
.min_freq_softlimit
;
1159 } else if (pm_iir
& GEN6_PM_RP_UP_EI_EXPIRED
) {
1160 new_delay
= vlv_calc_delay_from_C0_counters(dev_priv
);
1161 } else if (pm_iir
& GEN6_PM_RP_DOWN_THRESHOLD
) {
1165 /* CHV needs even encode values */
1166 adj
= IS_CHERRYVIEW(dev_priv
->dev
) ? -2 : -1;
1168 new_delay
= dev_priv
->rps
.cur_freq
+ adj
;
1169 } else { /* unknown event */
1170 new_delay
= dev_priv
->rps
.cur_freq
;
1173 /* sysfs frequency interfaces may have snuck in while servicing the
1176 new_delay
= clamp_t(int, new_delay
,
1177 dev_priv
->rps
.min_freq_softlimit
,
1178 dev_priv
->rps
.max_freq_softlimit
);
1180 dev_priv
->rps
.last_adj
= new_delay
- dev_priv
->rps
.cur_freq
;
1182 if (IS_VALLEYVIEW(dev_priv
->dev
))
1183 valleyview_set_rps(dev_priv
->dev
, new_delay
);
1185 gen6_set_rps(dev_priv
->dev
, new_delay
);
1187 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1192 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1194 * @work: workqueue struct
1196 * Doesn't actually do anything except notify userspace. As a consequence of
1197 * this event, userspace should try to remap the bad rows since statistically
1198 * it is likely the same row is more likely to go bad again.
1200 static void ivybridge_parity_work(struct work_struct
*work
)
1202 struct drm_i915_private
*dev_priv
=
1203 container_of(work
, struct drm_i915_private
, l3_parity
.error_work
);
1204 u32 error_status
, row
, bank
, subbank
;
1205 char *parity_event
[6];
1209 /* We must turn off DOP level clock gating to access the L3 registers.
1210 * In order to prevent a get/put style interface, acquire struct mutex
1211 * any time we access those registers.
1213 mutex_lock(&dev_priv
->dev
->struct_mutex
);
1215 /* If we've screwed up tracking, just let the interrupt fire again */
1216 if (WARN_ON(!dev_priv
->l3_parity
.which_slice
))
1219 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1220 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
1221 POSTING_READ(GEN7_MISCCPCTL
);
1223 while ((slice
= ffs(dev_priv
->l3_parity
.which_slice
)) != 0) {
1227 if (WARN_ON_ONCE(slice
>= NUM_L3_SLICES(dev_priv
->dev
)))
1230 dev_priv
->l3_parity
.which_slice
&= ~(1<<slice
);
1232 reg
= GEN7_L3CDERRST1
+ (slice
* 0x200);
1234 error_status
= I915_READ(reg
);
1235 row
= GEN7_PARITY_ERROR_ROW(error_status
);
1236 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
1237 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
1239 I915_WRITE(reg
, GEN7_PARITY_ERROR_VALID
| GEN7_L3CDERRST1_ENABLE
);
1242 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
1243 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
1244 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
1245 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
1246 parity_event
[4] = kasprintf(GFP_KERNEL
, "SLICE=%d", slice
);
1247 parity_event
[5] = NULL
;
1249 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
->kobj
,
1250 KOBJ_CHANGE
, parity_event
);
1252 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1253 slice
, row
, bank
, subbank
);
1255 kfree(parity_event
[4]);
1256 kfree(parity_event
[3]);
1257 kfree(parity_event
[2]);
1258 kfree(parity_event
[1]);
1261 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
1264 WARN_ON(dev_priv
->l3_parity
.which_slice
);
1265 spin_lock_irq(&dev_priv
->irq_lock
);
1266 gen5_enable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
->dev
));
1267 spin_unlock_irq(&dev_priv
->irq_lock
);
1269 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
1272 static void ivybridge_parity_error_irq_handler(struct drm_device
*dev
, u32 iir
)
1274 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1276 if (!HAS_L3_DPF(dev
))
1279 spin_lock(&dev_priv
->irq_lock
);
1280 gen5_disable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev
));
1281 spin_unlock(&dev_priv
->irq_lock
);
1283 iir
&= GT_PARITY_ERROR(dev
);
1284 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1
)
1285 dev_priv
->l3_parity
.which_slice
|= 1 << 1;
1287 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
1288 dev_priv
->l3_parity
.which_slice
|= 1 << 0;
1290 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
1293 static void ilk_gt_irq_handler(struct drm_device
*dev
,
1294 struct drm_i915_private
*dev_priv
,
1298 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1299 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1300 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
1301 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1304 static void snb_gt_irq_handler(struct drm_device
*dev
,
1305 struct drm_i915_private
*dev_priv
,
1310 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1311 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1312 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
1313 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1314 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
1315 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
1317 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
1318 GT_BSD_CS_ERROR_INTERRUPT
|
1319 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
)) {
1320 i915_handle_error(dev
, false, "GT error interrupt 0x%08x",
1324 if (gt_iir
& GT_PARITY_ERROR(dev
))
1325 ivybridge_parity_error_irq_handler(dev
, gt_iir
);
1328 static void gen8_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1330 if ((pm_iir
& dev_priv
->pm_rps_events
) == 0)
1333 spin_lock(&dev_priv
->irq_lock
);
1334 dev_priv
->rps
.pm_iir
|= pm_iir
& dev_priv
->pm_rps_events
;
1335 gen8_disable_pm_irq(dev_priv
, pm_iir
& dev_priv
->pm_rps_events
);
1336 spin_unlock(&dev_priv
->irq_lock
);
1338 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
1341 static irqreturn_t
gen8_gt_irq_handler(struct drm_device
*dev
,
1342 struct drm_i915_private
*dev_priv
,
1345 struct intel_engine_cs
*ring
;
1348 irqreturn_t ret
= IRQ_NONE
;
1350 if (master_ctl
& (GEN8_GT_RCS_IRQ
| GEN8_GT_BCS_IRQ
)) {
1351 tmp
= I915_READ(GEN8_GT_IIR(0));
1353 I915_WRITE(GEN8_GT_IIR(0), tmp
);
1356 rcs
= tmp
>> GEN8_RCS_IRQ_SHIFT
;
1357 ring
= &dev_priv
->ring
[RCS
];
1358 if (rcs
& GT_RENDER_USER_INTERRUPT
)
1359 notify_ring(dev
, ring
);
1360 if (rcs
& GT_CONTEXT_SWITCH_INTERRUPT
)
1361 intel_execlists_handle_ctx_events(ring
);
1363 bcs
= tmp
>> GEN8_BCS_IRQ_SHIFT
;
1364 ring
= &dev_priv
->ring
[BCS
];
1365 if (bcs
& GT_RENDER_USER_INTERRUPT
)
1366 notify_ring(dev
, ring
);
1367 if (bcs
& GT_CONTEXT_SWITCH_INTERRUPT
)
1368 intel_execlists_handle_ctx_events(ring
);
1370 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1373 if (master_ctl
& (GEN8_GT_VCS1_IRQ
| GEN8_GT_VCS2_IRQ
)) {
1374 tmp
= I915_READ(GEN8_GT_IIR(1));
1376 I915_WRITE(GEN8_GT_IIR(1), tmp
);
1379 vcs
= tmp
>> GEN8_VCS1_IRQ_SHIFT
;
1380 ring
= &dev_priv
->ring
[VCS
];
1381 if (vcs
& GT_RENDER_USER_INTERRUPT
)
1382 notify_ring(dev
, ring
);
1383 if (vcs
& GT_CONTEXT_SWITCH_INTERRUPT
)
1384 intel_execlists_handle_ctx_events(ring
);
1386 vcs
= tmp
>> GEN8_VCS2_IRQ_SHIFT
;
1387 ring
= &dev_priv
->ring
[VCS2
];
1388 if (vcs
& GT_RENDER_USER_INTERRUPT
)
1389 notify_ring(dev
, ring
);
1390 if (vcs
& GT_CONTEXT_SWITCH_INTERRUPT
)
1391 intel_execlists_handle_ctx_events(ring
);
1393 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1396 if (master_ctl
& GEN8_GT_PM_IRQ
) {
1397 tmp
= I915_READ(GEN8_GT_IIR(2));
1398 if (tmp
& dev_priv
->pm_rps_events
) {
1399 I915_WRITE(GEN8_GT_IIR(2),
1400 tmp
& dev_priv
->pm_rps_events
);
1402 gen8_rps_irq_handler(dev_priv
, tmp
);
1404 DRM_ERROR("The master control interrupt lied (PM)!\n");
1407 if (master_ctl
& GEN8_GT_VECS_IRQ
) {
1408 tmp
= I915_READ(GEN8_GT_IIR(3));
1410 I915_WRITE(GEN8_GT_IIR(3), tmp
);
1413 vcs
= tmp
>> GEN8_VECS_IRQ_SHIFT
;
1414 ring
= &dev_priv
->ring
[VECS
];
1415 if (vcs
& GT_RENDER_USER_INTERRUPT
)
1416 notify_ring(dev
, ring
);
1417 if (vcs
& GT_CONTEXT_SWITCH_INTERRUPT
)
1418 intel_execlists_handle_ctx_events(ring
);
1420 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1426 #define HPD_STORM_DETECT_PERIOD 1000
1427 #define HPD_STORM_THRESHOLD 5
1429 static int pch_port_to_hotplug_shift(enum port port
)
1445 static int i915_port_to_hotplug_shift(enum port port
)
1461 static inline enum port
get_port_from_pin(enum hpd_pin pin
)
1471 return PORT_A
; /* no hpd */
1475 static inline void intel_hpd_irq_handler(struct drm_device
*dev
,
1476 u32 hotplug_trigger
,
1477 u32 dig_hotplug_reg
,
1480 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1483 bool storm_detected
= false;
1484 bool queue_dig
= false, queue_hp
= false;
1486 u32 dig_port_mask
= 0;
1488 if (!hotplug_trigger
)
1491 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n",
1492 hotplug_trigger
, dig_hotplug_reg
);
1494 spin_lock(&dev_priv
->irq_lock
);
1495 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
1496 if (!(hpd
[i
] & hotplug_trigger
))
1499 port
= get_port_from_pin(i
);
1500 if (port
&& dev_priv
->hpd_irq_port
[port
]) {
1503 if (HAS_PCH_SPLIT(dev
)) {
1504 dig_shift
= pch_port_to_hotplug_shift(port
);
1505 long_hpd
= (dig_hotplug_reg
>> dig_shift
) & PORTB_HOTPLUG_LONG_DETECT
;
1507 dig_shift
= i915_port_to_hotplug_shift(port
);
1508 long_hpd
= (hotplug_trigger
>> dig_shift
) & PORTB_HOTPLUG_LONG_DETECT
;
1511 DRM_DEBUG_DRIVER("digital hpd port %c - %s\n",
1513 long_hpd
? "long" : "short");
1514 /* for long HPD pulses we want to have the digital queue happen,
1515 but we still want HPD storm detection to function. */
1517 dev_priv
->long_hpd_port_mask
|= (1 << port
);
1518 dig_port_mask
|= hpd
[i
];
1520 /* for short HPD just trigger the digital queue */
1521 dev_priv
->short_hpd_port_mask
|= (1 << port
);
1522 hotplug_trigger
&= ~hpd
[i
];
1528 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
1529 if (hpd
[i
] & hotplug_trigger
&&
1530 dev_priv
->hpd_stats
[i
].hpd_mark
== HPD_DISABLED
) {
1532 * On GMCH platforms the interrupt mask bits only
1533 * prevent irq generation, not the setting of the
1534 * hotplug bits itself. So only WARN about unexpected
1535 * interrupts on saner platforms.
1537 WARN_ONCE(INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
),
1538 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1539 hotplug_trigger
, i
, hpd
[i
]);
1544 if (!(hpd
[i
] & hotplug_trigger
) ||
1545 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
)
1548 if (!(dig_port_mask
& hpd
[i
])) {
1549 dev_priv
->hpd_event_bits
|= (1 << i
);
1553 if (!time_in_range(jiffies
, dev_priv
->hpd_stats
[i
].hpd_last_jiffies
,
1554 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
1555 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD
))) {
1556 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
= jiffies
;
1557 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
1558 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i
);
1559 } else if (dev_priv
->hpd_stats
[i
].hpd_cnt
> HPD_STORM_THRESHOLD
) {
1560 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_MARK_DISABLED
;
1561 dev_priv
->hpd_event_bits
&= ~(1 << i
);
1562 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i
);
1563 storm_detected
= true;
1565 dev_priv
->hpd_stats
[i
].hpd_cnt
++;
1566 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i
,
1567 dev_priv
->hpd_stats
[i
].hpd_cnt
);
1572 dev_priv
->display
.hpd_irq_setup(dev
);
1573 spin_unlock(&dev_priv
->irq_lock
);
1576 * Our hotplug handler can grab modeset locks (by calling down into the
1577 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1578 * queue for otherwise the flush_work in the pageflip code will
1582 queue_work(dev_priv
->dp_wq
, &dev_priv
->dig_port_work
);
1584 schedule_work(&dev_priv
->hotplug_work
);
1587 static void gmbus_irq_handler(struct drm_device
*dev
)
1589 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1591 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1594 static void dp_aux_irq_handler(struct drm_device
*dev
)
1596 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1598 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1601 #if defined(CONFIG_DEBUG_FS)
1602 static void display_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
,
1603 uint32_t crc0
, uint32_t crc1
,
1604 uint32_t crc2
, uint32_t crc3
,
1607 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1608 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
1609 struct intel_pipe_crc_entry
*entry
;
1612 spin_lock(&pipe_crc
->lock
);
1614 if (!pipe_crc
->entries
) {
1615 spin_unlock(&pipe_crc
->lock
);
1616 DRM_ERROR("spurious interrupt\n");
1620 head
= pipe_crc
->head
;
1621 tail
= pipe_crc
->tail
;
1623 if (CIRC_SPACE(head
, tail
, INTEL_PIPE_CRC_ENTRIES_NR
) < 1) {
1624 spin_unlock(&pipe_crc
->lock
);
1625 DRM_ERROR("CRC buffer overflowing\n");
1629 entry
= &pipe_crc
->entries
[head
];
1631 entry
->frame
= dev
->driver
->get_vblank_counter(dev
, pipe
);
1632 entry
->crc
[0] = crc0
;
1633 entry
->crc
[1] = crc1
;
1634 entry
->crc
[2] = crc2
;
1635 entry
->crc
[3] = crc3
;
1636 entry
->crc
[4] = crc4
;
1638 head
= (head
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
1639 pipe_crc
->head
= head
;
1641 spin_unlock(&pipe_crc
->lock
);
1643 wake_up_interruptible(&pipe_crc
->wq
);
1647 display_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
,
1648 uint32_t crc0
, uint32_t crc1
,
1649 uint32_t crc2
, uint32_t crc3
,
1654 static void hsw_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1656 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1658 display_pipe_crc_irq_handler(dev
, pipe
,
1659 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1663 static void ivb_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1665 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1667 display_pipe_crc_irq_handler(dev
, pipe
,
1668 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1669 I915_READ(PIPE_CRC_RES_2_IVB(pipe
)),
1670 I915_READ(PIPE_CRC_RES_3_IVB(pipe
)),
1671 I915_READ(PIPE_CRC_RES_4_IVB(pipe
)),
1672 I915_READ(PIPE_CRC_RES_5_IVB(pipe
)));
1675 static void i9xx_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1677 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1678 uint32_t res1
, res2
;
1680 if (INTEL_INFO(dev
)->gen
>= 3)
1681 res1
= I915_READ(PIPE_CRC_RES_RES1_I915(pipe
));
1685 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
1686 res2
= I915_READ(PIPE_CRC_RES_RES2_G4X(pipe
));
1690 display_pipe_crc_irq_handler(dev
, pipe
,
1691 I915_READ(PIPE_CRC_RES_RED(pipe
)),
1692 I915_READ(PIPE_CRC_RES_GREEN(pipe
)),
1693 I915_READ(PIPE_CRC_RES_BLUE(pipe
)),
1697 /* The RPS events need forcewake, so we add them to a work queue and mask their
1698 * IMR bits until the work is done. Other interrupts can be processed without
1699 * the work queue. */
1700 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1702 if (pm_iir
& dev_priv
->pm_rps_events
) {
1703 spin_lock(&dev_priv
->irq_lock
);
1704 dev_priv
->rps
.pm_iir
|= pm_iir
& dev_priv
->pm_rps_events
;
1705 gen6_disable_pm_irq(dev_priv
, pm_iir
& dev_priv
->pm_rps_events
);
1706 spin_unlock(&dev_priv
->irq_lock
);
1708 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
1711 if (HAS_VEBOX(dev_priv
->dev
)) {
1712 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1713 notify_ring(dev_priv
->dev
, &dev_priv
->ring
[VECS
]);
1715 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
) {
1716 i915_handle_error(dev_priv
->dev
, false,
1717 "VEBOX CS error interrupt 0x%08x",
1723 static bool intel_pipe_handle_vblank(struct drm_device
*dev
, enum pipe pipe
)
1725 if (!drm_handle_vblank(dev
, pipe
))
1731 static void valleyview_pipestat_irq_handler(struct drm_device
*dev
, u32 iir
)
1733 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1734 u32 pipe_stats
[I915_MAX_PIPES
] = { };
1737 spin_lock(&dev_priv
->irq_lock
);
1738 for_each_pipe(dev_priv
, pipe
) {
1740 u32 mask
, iir_bit
= 0;
1743 * PIPESTAT bits get signalled even when the interrupt is
1744 * disabled with the mask bits, and some of the status bits do
1745 * not generate interrupts at all (like the underrun bit). Hence
1746 * we need to be careful that we only handle what we want to
1750 /* fifo underruns are filterered in the underrun handler. */
1751 mask
= PIPE_FIFO_UNDERRUN_STATUS
;
1755 iir_bit
= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
;
1758 iir_bit
= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
1761 iir_bit
= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
1765 mask
|= dev_priv
->pipestat_irq_mask
[pipe
];
1770 reg
= PIPESTAT(pipe
);
1771 mask
|= PIPESTAT_INT_ENABLE_MASK
;
1772 pipe_stats
[pipe
] = I915_READ(reg
) & mask
;
1775 * Clear the PIPE*STAT regs before the IIR
1777 if (pipe_stats
[pipe
] & (PIPE_FIFO_UNDERRUN_STATUS
|
1778 PIPESTAT_INT_STATUS_MASK
))
1779 I915_WRITE(reg
, pipe_stats
[pipe
]);
1781 spin_unlock(&dev_priv
->irq_lock
);
1783 for_each_pipe(dev_priv
, pipe
) {
1784 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
1785 intel_pipe_handle_vblank(dev
, pipe
))
1786 intel_check_page_flip(dev
, pipe
);
1788 if (pipe_stats
[pipe
] & PLANE_FLIP_DONE_INT_STATUS_VLV
) {
1789 intel_prepare_page_flip(dev
, pipe
);
1790 intel_finish_page_flip(dev
, pipe
);
1793 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
1794 i9xx_pipe_crc_irq_handler(dev
, pipe
);
1796 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1797 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
1800 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1801 gmbus_irq_handler(dev
);
1804 static void i9xx_hpd_irq_handler(struct drm_device
*dev
)
1806 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1807 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1809 if (hotplug_status
) {
1810 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1812 * Make sure hotplug status is cleared before we clear IIR, or else we
1813 * may miss hotplug events.
1815 POSTING_READ(PORT_HOTPLUG_STAT
);
1818 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_G4X
;
1820 intel_hpd_irq_handler(dev
, hotplug_trigger
, 0, hpd_status_g4x
);
1822 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1824 intel_hpd_irq_handler(dev
, hotplug_trigger
, 0, hpd_status_i915
);
1827 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) &&
1828 hotplug_status
& DP_AUX_CHANNEL_MASK_INT_STATUS_G4X
)
1829 dp_aux_irq_handler(dev
);
1833 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1835 struct drm_device
*dev
= arg
;
1836 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1837 u32 iir
, gt_iir
, pm_iir
;
1838 irqreturn_t ret
= IRQ_NONE
;
1841 /* Find, clear, then process each source of interrupt */
1843 gt_iir
= I915_READ(GTIIR
);
1845 I915_WRITE(GTIIR
, gt_iir
);
1847 pm_iir
= I915_READ(GEN6_PMIIR
);
1849 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1851 iir
= I915_READ(VLV_IIR
);
1853 /* Consume port before clearing IIR or we'll miss events */
1854 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1855 i9xx_hpd_irq_handler(dev
);
1856 I915_WRITE(VLV_IIR
, iir
);
1859 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1865 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1867 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1868 /* Call regardless, as some status bits might not be
1869 * signalled in iir */
1870 valleyview_pipestat_irq_handler(dev
, iir
);
1877 static irqreturn_t
cherryview_irq_handler(int irq
, void *arg
)
1879 struct drm_device
*dev
= arg
;
1880 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1881 u32 master_ctl
, iir
;
1882 irqreturn_t ret
= IRQ_NONE
;
1885 master_ctl
= I915_READ(GEN8_MASTER_IRQ
) & ~GEN8_MASTER_IRQ_CONTROL
;
1886 iir
= I915_READ(VLV_IIR
);
1888 if (master_ctl
== 0 && iir
== 0)
1893 I915_WRITE(GEN8_MASTER_IRQ
, 0);
1895 /* Find, clear, then process each source of interrupt */
1898 /* Consume port before clearing IIR or we'll miss events */
1899 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1900 i9xx_hpd_irq_handler(dev
);
1901 I915_WRITE(VLV_IIR
, iir
);
1904 gen8_gt_irq_handler(dev
, dev_priv
, master_ctl
);
1906 /* Call regardless, as some status bits might not be
1907 * signalled in iir */
1908 valleyview_pipestat_irq_handler(dev
, iir
);
1910 I915_WRITE(GEN8_MASTER_IRQ
, DE_MASTER_IRQ_CONTROL
);
1911 POSTING_READ(GEN8_MASTER_IRQ
);
1917 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1919 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1921 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1922 u32 dig_hotplug_reg
;
1924 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
1925 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
1927 intel_hpd_irq_handler(dev
, hotplug_trigger
, dig_hotplug_reg
, hpd_ibx
);
1929 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1930 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1931 SDE_AUDIO_POWER_SHIFT
);
1932 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1936 if (pch_iir
& SDE_AUX_MASK
)
1937 dp_aux_irq_handler(dev
);
1939 if (pch_iir
& SDE_GMBUS
)
1940 gmbus_irq_handler(dev
);
1942 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1943 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1945 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1946 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1948 if (pch_iir
& SDE_POISON
)
1949 DRM_ERROR("PCH poison interrupt\n");
1951 if (pch_iir
& SDE_FDI_MASK
)
1952 for_each_pipe(dev_priv
, pipe
)
1953 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1955 I915_READ(FDI_RX_IIR(pipe
)));
1957 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1958 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1960 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1961 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1963 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1964 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_A
);
1966 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1967 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_B
);
1970 static void ivb_err_int_handler(struct drm_device
*dev
)
1972 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1973 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1976 if (err_int
& ERR_INT_POISON
)
1977 DRM_ERROR("Poison interrupt\n");
1979 for_each_pipe(dev_priv
, pipe
) {
1980 if (err_int
& ERR_INT_FIFO_UNDERRUN(pipe
))
1981 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
1983 if (err_int
& ERR_INT_PIPE_CRC_DONE(pipe
)) {
1984 if (IS_IVYBRIDGE(dev
))
1985 ivb_pipe_crc_irq_handler(dev
, pipe
);
1987 hsw_pipe_crc_irq_handler(dev
, pipe
);
1991 I915_WRITE(GEN7_ERR_INT
, err_int
);
1994 static void cpt_serr_int_handler(struct drm_device
*dev
)
1996 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1997 u32 serr_int
= I915_READ(SERR_INT
);
1999 if (serr_int
& SERR_INT_POISON
)
2000 DRM_ERROR("PCH poison interrupt\n");
2002 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
2003 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_A
);
2005 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
2006 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_B
);
2008 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
2009 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_C
);
2011 I915_WRITE(SERR_INT
, serr_int
);
2014 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
2016 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2018 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
2019 u32 dig_hotplug_reg
;
2021 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
2022 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
2024 intel_hpd_irq_handler(dev
, hotplug_trigger
, dig_hotplug_reg
, hpd_cpt
);
2026 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
2027 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
2028 SDE_AUDIO_POWER_SHIFT_CPT
);
2029 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2033 if (pch_iir
& SDE_AUX_MASK_CPT
)
2034 dp_aux_irq_handler(dev
);
2036 if (pch_iir
& SDE_GMBUS_CPT
)
2037 gmbus_irq_handler(dev
);
2039 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
2040 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2042 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
2043 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2045 if (pch_iir
& SDE_FDI_MASK_CPT
)
2046 for_each_pipe(dev_priv
, pipe
)
2047 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2049 I915_READ(FDI_RX_IIR(pipe
)));
2051 if (pch_iir
& SDE_ERROR_CPT
)
2052 cpt_serr_int_handler(dev
);
2055 static void ilk_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
2057 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2060 if (de_iir
& DE_AUX_CHANNEL_A
)
2061 dp_aux_irq_handler(dev
);
2063 if (de_iir
& DE_GSE
)
2064 intel_opregion_asle_intr(dev
);
2066 if (de_iir
& DE_POISON
)
2067 DRM_ERROR("Poison interrupt\n");
2069 for_each_pipe(dev_priv
, pipe
) {
2070 if (de_iir
& DE_PIPE_VBLANK(pipe
) &&
2071 intel_pipe_handle_vblank(dev
, pipe
))
2072 intel_check_page_flip(dev
, pipe
);
2074 if (de_iir
& DE_PIPE_FIFO_UNDERRUN(pipe
))
2075 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2077 if (de_iir
& DE_PIPE_CRC_DONE(pipe
))
2078 i9xx_pipe_crc_irq_handler(dev
, pipe
);
2080 /* plane/pipes map 1:1 on ilk+ */
2081 if (de_iir
& DE_PLANE_FLIP_DONE(pipe
)) {
2082 intel_prepare_page_flip(dev
, pipe
);
2083 intel_finish_page_flip_plane(dev
, pipe
);
2087 /* check event from PCH */
2088 if (de_iir
& DE_PCH_EVENT
) {
2089 u32 pch_iir
= I915_READ(SDEIIR
);
2091 if (HAS_PCH_CPT(dev
))
2092 cpt_irq_handler(dev
, pch_iir
);
2094 ibx_irq_handler(dev
, pch_iir
);
2096 /* should clear PCH hotplug event before clear CPU irq */
2097 I915_WRITE(SDEIIR
, pch_iir
);
2100 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
2101 ironlake_rps_change_irq_handler(dev
);
2104 static void ivb_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
2106 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2109 if (de_iir
& DE_ERR_INT_IVB
)
2110 ivb_err_int_handler(dev
);
2112 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
2113 dp_aux_irq_handler(dev
);
2115 if (de_iir
& DE_GSE_IVB
)
2116 intel_opregion_asle_intr(dev
);
2118 for_each_pipe(dev_priv
, pipe
) {
2119 if (de_iir
& (DE_PIPE_VBLANK_IVB(pipe
)) &&
2120 intel_pipe_handle_vblank(dev
, pipe
))
2121 intel_check_page_flip(dev
, pipe
);
2123 /* plane/pipes map 1:1 on ilk+ */
2124 if (de_iir
& DE_PLANE_FLIP_DONE_IVB(pipe
)) {
2125 intel_prepare_page_flip(dev
, pipe
);
2126 intel_finish_page_flip_plane(dev
, pipe
);
2130 /* check event from PCH */
2131 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
2132 u32 pch_iir
= I915_READ(SDEIIR
);
2134 cpt_irq_handler(dev
, pch_iir
);
2136 /* clear PCH hotplug event before clear CPU irq */
2137 I915_WRITE(SDEIIR
, pch_iir
);
2142 * To handle irqs with the minimum potential races with fresh interrupts, we:
2143 * 1 - Disable Master Interrupt Control.
2144 * 2 - Find the source(s) of the interrupt.
2145 * 3 - Clear the Interrupt Identity bits (IIR).
2146 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2147 * 5 - Re-enable Master Interrupt Control.
2149 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
2151 struct drm_device
*dev
= arg
;
2152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2153 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
2154 irqreturn_t ret
= IRQ_NONE
;
2156 /* We get interrupts on unclaimed registers, so check for this before we
2157 * do any I915_{READ,WRITE}. */
2158 intel_uncore_check_errors(dev
);
2160 /* disable master interrupt before clearing iir */
2161 de_ier
= I915_READ(DEIER
);
2162 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
2163 POSTING_READ(DEIER
);
2165 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2166 * interrupts will will be stored on its back queue, and then we'll be
2167 * able to process them after we restore SDEIER (as soon as we restore
2168 * it, we'll get an interrupt if SDEIIR still has something to process
2169 * due to its back queue). */
2170 if (!HAS_PCH_NOP(dev
)) {
2171 sde_ier
= I915_READ(SDEIER
);
2172 I915_WRITE(SDEIER
, 0);
2173 POSTING_READ(SDEIER
);
2176 /* Find, clear, then process each source of interrupt */
2178 gt_iir
= I915_READ(GTIIR
);
2180 I915_WRITE(GTIIR
, gt_iir
);
2182 if (INTEL_INFO(dev
)->gen
>= 6)
2183 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
2185 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
2188 de_iir
= I915_READ(DEIIR
);
2190 I915_WRITE(DEIIR
, de_iir
);
2192 if (INTEL_INFO(dev
)->gen
>= 7)
2193 ivb_display_irq_handler(dev
, de_iir
);
2195 ilk_display_irq_handler(dev
, de_iir
);
2198 if (INTEL_INFO(dev
)->gen
>= 6) {
2199 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
2201 I915_WRITE(GEN6_PMIIR
, pm_iir
);
2203 gen6_rps_irq_handler(dev_priv
, pm_iir
);
2207 I915_WRITE(DEIER
, de_ier
);
2208 POSTING_READ(DEIER
);
2209 if (!HAS_PCH_NOP(dev
)) {
2210 I915_WRITE(SDEIER
, sde_ier
);
2211 POSTING_READ(SDEIER
);
2217 static irqreturn_t
gen8_irq_handler(int irq
, void *arg
)
2219 struct drm_device
*dev
= arg
;
2220 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2222 irqreturn_t ret
= IRQ_NONE
;
2226 master_ctl
= I915_READ(GEN8_MASTER_IRQ
);
2227 master_ctl
&= ~GEN8_MASTER_IRQ_CONTROL
;
2231 I915_WRITE(GEN8_MASTER_IRQ
, 0);
2232 POSTING_READ(GEN8_MASTER_IRQ
);
2234 /* Find, clear, then process each source of interrupt */
2236 ret
= gen8_gt_irq_handler(dev
, dev_priv
, master_ctl
);
2238 if (master_ctl
& GEN8_DE_MISC_IRQ
) {
2239 tmp
= I915_READ(GEN8_DE_MISC_IIR
);
2241 I915_WRITE(GEN8_DE_MISC_IIR
, tmp
);
2243 if (tmp
& GEN8_DE_MISC_GSE
)
2244 intel_opregion_asle_intr(dev
);
2246 DRM_ERROR("Unexpected DE Misc interrupt\n");
2249 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2252 if (master_ctl
& GEN8_DE_PORT_IRQ
) {
2253 tmp
= I915_READ(GEN8_DE_PORT_IIR
);
2255 I915_WRITE(GEN8_DE_PORT_IIR
, tmp
);
2257 if (tmp
& GEN8_AUX_CHANNEL_A
)
2258 dp_aux_irq_handler(dev
);
2260 DRM_ERROR("Unexpected DE Port interrupt\n");
2263 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2266 for_each_pipe(dev_priv
, pipe
) {
2267 uint32_t pipe_iir
, flip_done
= 0, fault_errors
= 0;
2269 if (!(master_ctl
& GEN8_DE_PIPE_IRQ(pipe
)))
2272 pipe_iir
= I915_READ(GEN8_DE_PIPE_IIR(pipe
));
2275 I915_WRITE(GEN8_DE_PIPE_IIR(pipe
), pipe_iir
);
2277 if (pipe_iir
& GEN8_PIPE_VBLANK
&&
2278 intel_pipe_handle_vblank(dev
, pipe
))
2279 intel_check_page_flip(dev
, pipe
);
2282 flip_done
= pipe_iir
& GEN9_PIPE_PLANE1_FLIP_DONE
;
2284 flip_done
= pipe_iir
& GEN8_PIPE_PRIMARY_FLIP_DONE
;
2287 intel_prepare_page_flip(dev
, pipe
);
2288 intel_finish_page_flip_plane(dev
, pipe
);
2291 if (pipe_iir
& GEN8_PIPE_CDCLK_CRC_DONE
)
2292 hsw_pipe_crc_irq_handler(dev
, pipe
);
2294 if (pipe_iir
& GEN8_PIPE_FIFO_UNDERRUN
)
2295 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
2300 fault_errors
= pipe_iir
& GEN9_DE_PIPE_IRQ_FAULT_ERRORS
;
2302 fault_errors
= pipe_iir
& GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
2305 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2307 pipe_iir
& GEN8_DE_PIPE_IRQ_FAULT_ERRORS
);
2309 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2312 if (!HAS_PCH_NOP(dev
) && master_ctl
& GEN8_DE_PCH_IRQ
) {
2314 * FIXME(BDW): Assume for now that the new interrupt handling
2315 * scheme also closed the SDE interrupt handling race we've seen
2316 * on older pch-split platforms. But this needs testing.
2318 u32 pch_iir
= I915_READ(SDEIIR
);
2320 I915_WRITE(SDEIIR
, pch_iir
);
2322 cpt_irq_handler(dev
, pch_iir
);
2324 DRM_ERROR("The master control interrupt lied (SDE)!\n");
2328 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
2329 POSTING_READ(GEN8_MASTER_IRQ
);
2334 static void i915_error_wake_up(struct drm_i915_private
*dev_priv
,
2335 bool reset_completed
)
2337 struct intel_engine_cs
*ring
;
2341 * Notify all waiters for GPU completion events that reset state has
2342 * been changed, and that they need to restart their wait after
2343 * checking for potential errors (and bail out to drop locks if there is
2344 * a gpu reset pending so that i915_error_work_func can acquire them).
2347 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2348 for_each_ring(ring
, dev_priv
, i
)
2349 wake_up_all(&ring
->irq_queue
);
2351 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2352 wake_up_all(&dev_priv
->pending_flip_queue
);
2355 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2356 * reset state is cleared.
2358 if (reset_completed
)
2359 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
2363 * i915_error_work_func - do process context error handling work
2364 * @work: work struct
2366 * Fire an error uevent so userspace can see that a hang or error
2369 static void i915_error_work_func(struct work_struct
*work
)
2371 struct i915_gpu_error
*error
= container_of(work
, struct i915_gpu_error
,
2373 struct drm_i915_private
*dev_priv
=
2374 container_of(error
, struct drm_i915_private
, gpu_error
);
2375 struct drm_device
*dev
= dev_priv
->dev
;
2376 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
2377 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
2378 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
2381 kobject_uevent_env(&dev
->primary
->kdev
->kobj
, KOBJ_CHANGE
, error_event
);
2384 * Note that there's only one work item which does gpu resets, so we
2385 * need not worry about concurrent gpu resets potentially incrementing
2386 * error->reset_counter twice. We only need to take care of another
2387 * racing irq/hangcheck declaring the gpu dead for a second time. A
2388 * quick check for that is good enough: schedule_work ensures the
2389 * correct ordering between hang detection and this work item, and since
2390 * the reset in-progress bit is only ever set by code outside of this
2391 * work we don't need to worry about any other races.
2393 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
2394 DRM_DEBUG_DRIVER("resetting chip\n");
2395 kobject_uevent_env(&dev
->primary
->kdev
->kobj
, KOBJ_CHANGE
,
2399 * In most cases it's guaranteed that we get here with an RPM
2400 * reference held, for example because there is a pending GPU
2401 * request that won't finish until the reset is done. This
2402 * isn't the case at least when we get here by doing a
2403 * simulated reset via debugs, so get an RPM reference.
2405 intel_runtime_pm_get(dev_priv
);
2407 * All state reset _must_ be completed before we update the
2408 * reset counter, for otherwise waiters might miss the reset
2409 * pending state and not properly drop locks, resulting in
2410 * deadlocks with the reset work.
2412 ret
= i915_reset(dev
);
2414 intel_display_handle_reset(dev
);
2416 intel_runtime_pm_put(dev_priv
);
2420 * After all the gem state is reset, increment the reset
2421 * counter and wake up everyone waiting for the reset to
2424 * Since unlock operations are a one-sided barrier only,
2425 * we need to insert a barrier here to order any seqno
2427 * the counter increment.
2429 smp_mb__before_atomic();
2430 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
2432 kobject_uevent_env(&dev
->primary
->kdev
->kobj
,
2433 KOBJ_CHANGE
, reset_done_event
);
2435 atomic_set_mask(I915_WEDGED
, &error
->reset_counter
);
2439 * Note: The wake_up also serves as a memory barrier so that
2440 * waiters see the update value of the reset counter atomic_t.
2442 i915_error_wake_up(dev_priv
, true);
2446 static void i915_report_and_clear_eir(struct drm_device
*dev
)
2448 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2449 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
2450 u32 eir
= I915_READ(EIR
);
2456 pr_err("render error detected, EIR: 0x%08x\n", eir
);
2458 i915_get_extra_instdone(dev
, instdone
);
2461 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
2462 u32 ipeir
= I915_READ(IPEIR_I965
);
2464 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2465 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2466 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2467 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2468 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2469 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2470 I915_WRITE(IPEIR_I965
, ipeir
);
2471 POSTING_READ(IPEIR_I965
);
2473 if (eir
& GM45_ERROR_PAGE_TABLE
) {
2474 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2475 pr_err("page table error\n");
2476 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2477 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2478 POSTING_READ(PGTBL_ER
);
2482 if (!IS_GEN2(dev
)) {
2483 if (eir
& I915_ERROR_PAGE_TABLE
) {
2484 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2485 pr_err("page table error\n");
2486 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2487 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2488 POSTING_READ(PGTBL_ER
);
2492 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
2493 pr_err("memory refresh error:\n");
2494 for_each_pipe(dev_priv
, pipe
)
2495 pr_err("pipe %c stat: 0x%08x\n",
2496 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
2497 /* pipestat has already been acked */
2499 if (eir
& I915_ERROR_INSTRUCTION
) {
2500 pr_err("instruction error\n");
2501 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
2502 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2503 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2504 if (INTEL_INFO(dev
)->gen
< 4) {
2505 u32 ipeir
= I915_READ(IPEIR
);
2507 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
2508 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
2509 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
2510 I915_WRITE(IPEIR
, ipeir
);
2511 POSTING_READ(IPEIR
);
2513 u32 ipeir
= I915_READ(IPEIR_I965
);
2515 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2516 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2517 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2518 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2519 I915_WRITE(IPEIR_I965
, ipeir
);
2520 POSTING_READ(IPEIR_I965
);
2524 I915_WRITE(EIR
, eir
);
2526 eir
= I915_READ(EIR
);
2529 * some errors might have become stuck,
2532 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
2533 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
2534 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2539 * i915_handle_error - handle an error interrupt
2542 * Do some basic checking of regsiter state at error interrupt time and
2543 * dump it to the syslog. Also call i915_capture_error_state() to make
2544 * sure we get a record and make it available in debugfs. Fire a uevent
2545 * so userspace knows something bad happened (should trigger collection
2546 * of a ring dump etc.).
2548 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2549 const char *fmt
, ...)
2551 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2555 va_start(args
, fmt
);
2556 vscnprintf(error_msg
, sizeof(error_msg
), fmt
, args
);
2559 i915_capture_error_state(dev
, wedged
, error_msg
);
2560 i915_report_and_clear_eir(dev
);
2563 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
2564 &dev_priv
->gpu_error
.reset_counter
);
2567 * Wakeup waiting processes so that the reset work function
2568 * i915_error_work_func doesn't deadlock trying to grab various
2569 * locks. By bumping the reset counter first, the woken
2570 * processes will see a reset in progress and back off,
2571 * releasing their locks and then wait for the reset completion.
2572 * We must do this for _all_ gpu waiters that might hold locks
2573 * that the reset work needs to acquire.
2575 * Note: The wake_up serves as the required memory barrier to
2576 * ensure that the waiters see the updated value of the reset
2579 i915_error_wake_up(dev_priv
, false);
2583 * Our reset work can grab modeset locks (since it needs to reset the
2584 * state of outstanding pagelips). Hence it must not be run on our own
2585 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2586 * code will deadlock.
2588 schedule_work(&dev_priv
->gpu_error
.work
);
2591 /* Called from drm generic code, passed 'crtc' which
2592 * we use as a pipe index
2594 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
2596 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2597 unsigned long irqflags
;
2599 if (!i915_pipe_enabled(dev
, pipe
))
2602 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2603 if (INTEL_INFO(dev
)->gen
>= 4)
2604 i915_enable_pipestat(dev_priv
, pipe
,
2605 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2607 i915_enable_pipestat(dev_priv
, pipe
,
2608 PIPE_VBLANK_INTERRUPT_STATUS
);
2609 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2614 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
2616 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2617 unsigned long irqflags
;
2618 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2619 DE_PIPE_VBLANK(pipe
);
2621 if (!i915_pipe_enabled(dev
, pipe
))
2624 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2625 ironlake_enable_display_irq(dev_priv
, bit
);
2626 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2631 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
2633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2634 unsigned long irqflags
;
2636 if (!i915_pipe_enabled(dev
, pipe
))
2639 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2640 i915_enable_pipestat(dev_priv
, pipe
,
2641 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2642 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2647 static int gen8_enable_vblank(struct drm_device
*dev
, int pipe
)
2649 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2650 unsigned long irqflags
;
2652 if (!i915_pipe_enabled(dev
, pipe
))
2655 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2656 dev_priv
->de_irq_mask
[pipe
] &= ~GEN8_PIPE_VBLANK
;
2657 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
2658 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
2659 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2663 /* Called from drm generic code, passed 'crtc' which
2664 * we use as a pipe index
2666 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
2668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2669 unsigned long irqflags
;
2671 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2672 i915_disable_pipestat(dev_priv
, pipe
,
2673 PIPE_VBLANK_INTERRUPT_STATUS
|
2674 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2675 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2678 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
2680 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2681 unsigned long irqflags
;
2682 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2683 DE_PIPE_VBLANK(pipe
);
2685 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2686 ironlake_disable_display_irq(dev_priv
, bit
);
2687 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2690 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
2692 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2693 unsigned long irqflags
;
2695 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2696 i915_disable_pipestat(dev_priv
, pipe
,
2697 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2698 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2701 static void gen8_disable_vblank(struct drm_device
*dev
, int pipe
)
2703 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2704 unsigned long irqflags
;
2706 if (!i915_pipe_enabled(dev
, pipe
))
2709 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2710 dev_priv
->de_irq_mask
[pipe
] |= GEN8_PIPE_VBLANK
;
2711 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
2712 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
2713 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2717 ring_last_seqno(struct intel_engine_cs
*ring
)
2719 return list_entry(ring
->request_list
.prev
,
2720 struct drm_i915_gem_request
, list
)->seqno
;
2724 ring_idle(struct intel_engine_cs
*ring
, u32 seqno
)
2726 return (list_empty(&ring
->request_list
) ||
2727 i915_seqno_passed(seqno
, ring_last_seqno(ring
)));
2731 ipehr_is_semaphore_wait(struct drm_device
*dev
, u32 ipehr
)
2733 if (INTEL_INFO(dev
)->gen
>= 8) {
2734 return (ipehr
>> 23) == 0x1c;
2736 ipehr
&= ~MI_SEMAPHORE_SYNC_MASK
;
2737 return ipehr
== (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
|
2738 MI_SEMAPHORE_REGISTER
);
2742 static struct intel_engine_cs
*
2743 semaphore_wait_to_signaller_ring(struct intel_engine_cs
*ring
, u32 ipehr
, u64 offset
)
2745 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2746 struct intel_engine_cs
*signaller
;
2749 if (INTEL_INFO(dev_priv
->dev
)->gen
>= 8) {
2750 for_each_ring(signaller
, dev_priv
, i
) {
2751 if (ring
== signaller
)
2754 if (offset
== signaller
->semaphore
.signal_ggtt
[ring
->id
])
2758 u32 sync_bits
= ipehr
& MI_SEMAPHORE_SYNC_MASK
;
2760 for_each_ring(signaller
, dev_priv
, i
) {
2761 if(ring
== signaller
)
2764 if (sync_bits
== signaller
->semaphore
.mbox
.wait
[ring
->id
])
2769 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2770 ring
->id
, ipehr
, offset
);
2775 static struct intel_engine_cs
*
2776 semaphore_waits_for(struct intel_engine_cs
*ring
, u32
*seqno
)
2778 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2779 u32 cmd
, ipehr
, head
;
2783 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
2784 if (!ipehr_is_semaphore_wait(ring
->dev
, ipehr
))
2788 * HEAD is likely pointing to the dword after the actual command,
2789 * so scan backwards until we find the MBOX. But limit it to just 3
2790 * or 4 dwords depending on the semaphore wait command size.
2791 * Note that we don't care about ACTHD here since that might
2792 * point at at batch, and semaphores are always emitted into the
2793 * ringbuffer itself.
2795 head
= I915_READ_HEAD(ring
) & HEAD_ADDR
;
2796 backwards
= (INTEL_INFO(ring
->dev
)->gen
>= 8) ? 5 : 4;
2798 for (i
= backwards
; i
; --i
) {
2800 * Be paranoid and presume the hw has gone off into the wild -
2801 * our ring is smaller than what the hardware (and hence
2802 * HEAD_ADDR) allows. Also handles wrap-around.
2804 head
&= ring
->buffer
->size
- 1;
2806 /* This here seems to blow up */
2807 cmd
= ioread32(ring
->buffer
->virtual_start
+ head
);
2817 *seqno
= ioread32(ring
->buffer
->virtual_start
+ head
+ 4) + 1;
2818 if (INTEL_INFO(ring
->dev
)->gen
>= 8) {
2819 offset
= ioread32(ring
->buffer
->virtual_start
+ head
+ 12);
2821 offset
= ioread32(ring
->buffer
->virtual_start
+ head
+ 8);
2823 return semaphore_wait_to_signaller_ring(ring
, ipehr
, offset
);
2826 static int semaphore_passed(struct intel_engine_cs
*ring
)
2828 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2829 struct intel_engine_cs
*signaller
;
2832 ring
->hangcheck
.deadlock
++;
2834 signaller
= semaphore_waits_for(ring
, &seqno
);
2835 if (signaller
== NULL
)
2838 /* Prevent pathological recursion due to driver bugs */
2839 if (signaller
->hangcheck
.deadlock
>= I915_NUM_RINGS
)
2842 if (i915_seqno_passed(signaller
->get_seqno(signaller
, false), seqno
))
2845 /* cursory check for an unkickable deadlock */
2846 if (I915_READ_CTL(signaller
) & RING_WAIT_SEMAPHORE
&&
2847 semaphore_passed(signaller
) < 0)
2853 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
2855 struct intel_engine_cs
*ring
;
2858 for_each_ring(ring
, dev_priv
, i
)
2859 ring
->hangcheck
.deadlock
= 0;
2862 static enum intel_ring_hangcheck_action
2863 ring_stuck(struct intel_engine_cs
*ring
, u64 acthd
)
2865 struct drm_device
*dev
= ring
->dev
;
2866 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2869 if (acthd
!= ring
->hangcheck
.acthd
) {
2870 if (acthd
> ring
->hangcheck
.max_acthd
) {
2871 ring
->hangcheck
.max_acthd
= acthd
;
2872 return HANGCHECK_ACTIVE
;
2875 return HANGCHECK_ACTIVE_LOOP
;
2879 return HANGCHECK_HUNG
;
2881 /* Is the chip hanging on a WAIT_FOR_EVENT?
2882 * If so we can simply poke the RB_WAIT bit
2883 * and break the hang. This should work on
2884 * all but the second generation chipsets.
2886 tmp
= I915_READ_CTL(ring
);
2887 if (tmp
& RING_WAIT
) {
2888 i915_handle_error(dev
, false,
2889 "Kicking stuck wait on %s",
2891 I915_WRITE_CTL(ring
, tmp
);
2892 return HANGCHECK_KICK
;
2895 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
2896 switch (semaphore_passed(ring
)) {
2898 return HANGCHECK_HUNG
;
2900 i915_handle_error(dev
, false,
2901 "Kicking stuck semaphore on %s",
2903 I915_WRITE_CTL(ring
, tmp
);
2904 return HANGCHECK_KICK
;
2906 return HANGCHECK_WAIT
;
2910 return HANGCHECK_HUNG
;
2914 * This is called when the chip hasn't reported back with completed
2915 * batchbuffers in a long time. We keep track per ring seqno progress and
2916 * if there are no progress, hangcheck score for that ring is increased.
2917 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2918 * we kick the ring. If we see no progress on three subsequent calls
2919 * we assume chip is wedged and try to fix it by resetting the chip.
2921 static void i915_hangcheck_elapsed(unsigned long data
)
2923 struct drm_device
*dev
= (struct drm_device
*)data
;
2924 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2925 struct intel_engine_cs
*ring
;
2927 int busy_count
= 0, rings_hung
= 0;
2928 bool stuck
[I915_NUM_RINGS
] = { 0 };
2933 if (!i915
.enable_hangcheck
)
2936 for_each_ring(ring
, dev_priv
, i
) {
2941 semaphore_clear_deadlocks(dev_priv
);
2943 seqno
= ring
->get_seqno(ring
, false);
2944 acthd
= intel_ring_get_active_head(ring
);
2946 if (ring
->hangcheck
.seqno
== seqno
) {
2947 if (ring_idle(ring
, seqno
)) {
2948 ring
->hangcheck
.action
= HANGCHECK_IDLE
;
2950 if (waitqueue_active(&ring
->irq_queue
)) {
2951 /* Issue a wake-up to catch stuck h/w. */
2952 if (!test_and_set_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
)) {
2953 if (!(dev_priv
->gpu_error
.test_irq_rings
& intel_ring_flag(ring
)))
2954 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2957 DRM_INFO("Fake missed irq on %s\n",
2959 wake_up_all(&ring
->irq_queue
);
2961 /* Safeguard against driver failure */
2962 ring
->hangcheck
.score
+= BUSY
;
2966 /* We always increment the hangcheck score
2967 * if the ring is busy and still processing
2968 * the same request, so that no single request
2969 * can run indefinitely (such as a chain of
2970 * batches). The only time we do not increment
2971 * the hangcheck score on this ring, if this
2972 * ring is in a legitimate wait for another
2973 * ring. In that case the waiting ring is a
2974 * victim and we want to be sure we catch the
2975 * right culprit. Then every time we do kick
2976 * the ring, add a small increment to the
2977 * score so that we can catch a batch that is
2978 * being repeatedly kicked and so responsible
2979 * for stalling the machine.
2981 ring
->hangcheck
.action
= ring_stuck(ring
,
2984 switch (ring
->hangcheck
.action
) {
2985 case HANGCHECK_IDLE
:
2986 case HANGCHECK_WAIT
:
2987 case HANGCHECK_ACTIVE
:
2989 case HANGCHECK_ACTIVE_LOOP
:
2990 ring
->hangcheck
.score
+= BUSY
;
2992 case HANGCHECK_KICK
:
2993 ring
->hangcheck
.score
+= KICK
;
2995 case HANGCHECK_HUNG
:
2996 ring
->hangcheck
.score
+= HUNG
;
3002 ring
->hangcheck
.action
= HANGCHECK_ACTIVE
;
3004 /* Gradually reduce the count so that we catch DoS
3005 * attempts across multiple batches.
3007 if (ring
->hangcheck
.score
> 0)
3008 ring
->hangcheck
.score
--;
3010 ring
->hangcheck
.acthd
= ring
->hangcheck
.max_acthd
= 0;
3013 ring
->hangcheck
.seqno
= seqno
;
3014 ring
->hangcheck
.acthd
= acthd
;
3018 for_each_ring(ring
, dev_priv
, i
) {
3019 if (ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
) {
3020 DRM_INFO("%s on %s\n",
3021 stuck
[i
] ? "stuck" : "no progress",
3028 return i915_handle_error(dev
, true, "Ring hung");
3031 /* Reset timer case chip hangs without another request
3033 i915_queue_hangcheck(dev
);
3036 void i915_queue_hangcheck(struct drm_device
*dev
)
3038 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3039 if (!i915
.enable_hangcheck
)
3042 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
3043 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
3046 static void ibx_irq_reset(struct drm_device
*dev
)
3048 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3050 if (HAS_PCH_NOP(dev
))
3053 GEN5_IRQ_RESET(SDE
);
3055 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
3056 I915_WRITE(SERR_INT
, 0xffffffff);
3060 * SDEIER is also touched by the interrupt handler to work around missed PCH
3061 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3062 * instead we unconditionally enable all PCH interrupt sources here, but then
3063 * only unmask them as needed with SDEIMR.
3065 * This function needs to be called before interrupts are enabled.
3067 static void ibx_irq_pre_postinstall(struct drm_device
*dev
)
3069 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3071 if (HAS_PCH_NOP(dev
))
3074 WARN_ON(I915_READ(SDEIER
) != 0);
3075 I915_WRITE(SDEIER
, 0xffffffff);
3076 POSTING_READ(SDEIER
);
3079 static void gen5_gt_irq_reset(struct drm_device
*dev
)
3081 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3084 if (INTEL_INFO(dev
)->gen
>= 6)
3085 GEN5_IRQ_RESET(GEN6_PM
);
3090 static void ironlake_irq_reset(struct drm_device
*dev
)
3092 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3094 I915_WRITE(HWSTAM
, 0xffffffff);
3098 I915_WRITE(GEN7_ERR_INT
, 0xffffffff);
3100 gen5_gt_irq_reset(dev
);
3105 static void vlv_display_irq_reset(struct drm_i915_private
*dev_priv
)
3109 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3110 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3112 for_each_pipe(dev_priv
, pipe
)
3113 I915_WRITE(PIPESTAT(pipe
), 0xffff);
3115 GEN5_IRQ_RESET(VLV_
);
3118 static void valleyview_irq_preinstall(struct drm_device
*dev
)
3120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3123 I915_WRITE(VLV_IMR
, 0);
3124 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
3125 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
3126 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
3128 gen5_gt_irq_reset(dev
);
3130 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
3132 vlv_display_irq_reset(dev_priv
);
3135 static void gen8_gt_irq_reset(struct drm_i915_private
*dev_priv
)
3137 GEN8_IRQ_RESET_NDX(GT
, 0);
3138 GEN8_IRQ_RESET_NDX(GT
, 1);
3139 GEN8_IRQ_RESET_NDX(GT
, 2);
3140 GEN8_IRQ_RESET_NDX(GT
, 3);
3143 static void gen8_irq_reset(struct drm_device
*dev
)
3145 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3148 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3149 POSTING_READ(GEN8_MASTER_IRQ
);
3151 gen8_gt_irq_reset(dev_priv
);
3153 for_each_pipe(dev_priv
, pipe
)
3154 if (intel_display_power_is_enabled(dev_priv
,
3155 POWER_DOMAIN_PIPE(pipe
)))
3156 GEN8_IRQ_RESET_NDX(DE_PIPE
, pipe
);
3158 GEN5_IRQ_RESET(GEN8_DE_PORT_
);
3159 GEN5_IRQ_RESET(GEN8_DE_MISC_
);
3160 GEN5_IRQ_RESET(GEN8_PCU_
);
3165 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
)
3167 uint32_t extra_ier
= GEN8_PIPE_VBLANK
| GEN8_PIPE_FIFO_UNDERRUN
;
3169 spin_lock_irq(&dev_priv
->irq_lock
);
3170 GEN8_IRQ_INIT_NDX(DE_PIPE
, PIPE_B
, dev_priv
->de_irq_mask
[PIPE_B
],
3171 ~dev_priv
->de_irq_mask
[PIPE_B
] | extra_ier
);
3172 GEN8_IRQ_INIT_NDX(DE_PIPE
, PIPE_C
, dev_priv
->de_irq_mask
[PIPE_C
],
3173 ~dev_priv
->de_irq_mask
[PIPE_C
] | extra_ier
);
3174 spin_unlock_irq(&dev_priv
->irq_lock
);
3177 static void cherryview_irq_preinstall(struct drm_device
*dev
)
3179 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3181 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3182 POSTING_READ(GEN8_MASTER_IRQ
);
3184 gen8_gt_irq_reset(dev_priv
);
3186 GEN5_IRQ_RESET(GEN8_PCU_
);
3188 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK_CHV
);
3190 vlv_display_irq_reset(dev_priv
);
3193 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
3195 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3196 struct intel_encoder
*intel_encoder
;
3197 u32 hotplug_irqs
, hotplug
, enabled_irqs
= 0;
3199 if (HAS_PCH_IBX(dev
)) {
3200 hotplug_irqs
= SDE_HOTPLUG_MASK
;
3201 for_each_intel_encoder(dev
, intel_encoder
)
3202 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
3203 enabled_irqs
|= hpd_ibx
[intel_encoder
->hpd_pin
];
3205 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
3206 for_each_intel_encoder(dev
, intel_encoder
)
3207 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
3208 enabled_irqs
|= hpd_cpt
[intel_encoder
->hpd_pin
];
3211 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
3214 * Enable digital hotplug on the PCH, and configure the DP short pulse
3215 * duration to 2ms (which is the minimum in the Display Port spec)
3217 * This register is the same on all known PCH chips.
3219 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3220 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
3221 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
3222 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
3223 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
3224 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3227 static void ibx_irq_postinstall(struct drm_device
*dev
)
3229 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3232 if (HAS_PCH_NOP(dev
))
3235 if (HAS_PCH_IBX(dev
))
3236 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_POISON
;
3238 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
;
3240 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR
);
3241 I915_WRITE(SDEIMR
, ~mask
);
3244 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
3246 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3247 u32 pm_irqs
, gt_irqs
;
3249 pm_irqs
= gt_irqs
= 0;
3251 dev_priv
->gt_irq_mask
= ~0;
3252 if (HAS_L3_DPF(dev
)) {
3253 /* L3 parity interrupt is always unmasked. */
3254 dev_priv
->gt_irq_mask
= ~GT_PARITY_ERROR(dev
);
3255 gt_irqs
|= GT_PARITY_ERROR(dev
);
3258 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
3260 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
3261 ILK_BSD_USER_INTERRUPT
;
3263 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
3266 GEN5_IRQ_INIT(GT
, dev_priv
->gt_irq_mask
, gt_irqs
);
3268 if (INTEL_INFO(dev
)->gen
>= 6) {
3269 pm_irqs
|= dev_priv
->pm_rps_events
;
3272 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
3274 dev_priv
->pm_irq_mask
= 0xffffffff;
3275 GEN5_IRQ_INIT(GEN6_PM
, dev_priv
->pm_irq_mask
, pm_irqs
);
3279 static int ironlake_irq_postinstall(struct drm_device
*dev
)
3281 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3282 u32 display_mask
, extra_mask
;
3284 if (INTEL_INFO(dev
)->gen
>= 7) {
3285 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
3286 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
3287 DE_PLANEB_FLIP_DONE_IVB
|
3288 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
);
3289 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
3290 DE_PIPEA_VBLANK_IVB
| DE_ERR_INT_IVB
);
3292 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
3293 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
3295 DE_PIPEB_CRC_DONE
| DE_PIPEA_CRC_DONE
|
3297 extra_mask
= DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
|
3298 DE_PIPEB_FIFO_UNDERRUN
| DE_PIPEA_FIFO_UNDERRUN
;
3301 dev_priv
->irq_mask
= ~display_mask
;
3303 I915_WRITE(HWSTAM
, 0xeffe);
3305 ibx_irq_pre_postinstall(dev
);
3307 GEN5_IRQ_INIT(DE
, dev_priv
->irq_mask
, display_mask
| extra_mask
);
3309 gen5_gt_irq_postinstall(dev
);
3311 ibx_irq_postinstall(dev
);
3313 if (IS_IRONLAKE_M(dev
)) {
3314 /* Enable PCU event interrupts
3316 * spinlocking not required here for correctness since interrupt
3317 * setup is guaranteed to run in single-threaded context. But we
3318 * need it to make the assert_spin_locked happy. */
3319 spin_lock_irq(&dev_priv
->irq_lock
);
3320 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
3321 spin_unlock_irq(&dev_priv
->irq_lock
);
3327 static void valleyview_display_irqs_install(struct drm_i915_private
*dev_priv
)
3333 pipestat_mask
= PIPESTAT_INT_STATUS_MASK
|
3334 PIPE_FIFO_UNDERRUN_STATUS
;
3336 for_each_pipe(dev_priv
, pipe
)
3337 I915_WRITE(PIPESTAT(pipe
), pipestat_mask
);
3338 POSTING_READ(PIPESTAT(PIPE_A
));
3340 pipestat_mask
= PLANE_FLIP_DONE_INT_STATUS_VLV
|
3341 PIPE_CRC_DONE_INTERRUPT_STATUS
;
3343 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
3344 for_each_pipe(dev_priv
, pipe
)
3345 i915_enable_pipestat(dev_priv
, pipe
, pipestat_mask
);
3347 iir_mask
= I915_DISPLAY_PORT_INTERRUPT
|
3348 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3349 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
3350 if (IS_CHERRYVIEW(dev_priv
))
3351 iir_mask
|= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
3352 dev_priv
->irq_mask
&= ~iir_mask
;
3354 I915_WRITE(VLV_IIR
, iir_mask
);
3355 I915_WRITE(VLV_IIR
, iir_mask
);
3356 I915_WRITE(VLV_IER
, ~dev_priv
->irq_mask
);
3357 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3358 POSTING_READ(VLV_IMR
);
3361 static void valleyview_display_irqs_uninstall(struct drm_i915_private
*dev_priv
)
3367 iir_mask
= I915_DISPLAY_PORT_INTERRUPT
|
3368 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3369 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
3370 if (IS_CHERRYVIEW(dev_priv
))
3371 iir_mask
|= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
3373 dev_priv
->irq_mask
|= iir_mask
;
3374 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3375 I915_WRITE(VLV_IER
, ~dev_priv
->irq_mask
);
3376 I915_WRITE(VLV_IIR
, iir_mask
);
3377 I915_WRITE(VLV_IIR
, iir_mask
);
3378 POSTING_READ(VLV_IIR
);
3380 pipestat_mask
= PLANE_FLIP_DONE_INT_STATUS_VLV
|
3381 PIPE_CRC_DONE_INTERRUPT_STATUS
;
3383 i915_disable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
3384 for_each_pipe(dev_priv
, pipe
)
3385 i915_disable_pipestat(dev_priv
, pipe
, pipestat_mask
);
3387 pipestat_mask
= PIPESTAT_INT_STATUS_MASK
|
3388 PIPE_FIFO_UNDERRUN_STATUS
;
3390 for_each_pipe(dev_priv
, pipe
)
3391 I915_WRITE(PIPESTAT(pipe
), pipestat_mask
);
3392 POSTING_READ(PIPESTAT(PIPE_A
));
3395 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
)
3397 assert_spin_locked(&dev_priv
->irq_lock
);
3399 if (dev_priv
->display_irqs_enabled
)
3402 dev_priv
->display_irqs_enabled
= true;
3404 if (intel_irqs_enabled(dev_priv
))
3405 valleyview_display_irqs_install(dev_priv
);
3408 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
)
3410 assert_spin_locked(&dev_priv
->irq_lock
);
3412 if (!dev_priv
->display_irqs_enabled
)
3415 dev_priv
->display_irqs_enabled
= false;
3417 if (intel_irqs_enabled(dev_priv
))
3418 valleyview_display_irqs_uninstall(dev_priv
);
3421 static void vlv_display_irq_postinstall(struct drm_i915_private
*dev_priv
)
3423 dev_priv
->irq_mask
= ~0;
3425 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3426 POSTING_READ(PORT_HOTPLUG_EN
);
3428 I915_WRITE(VLV_IIR
, 0xffffffff);
3429 I915_WRITE(VLV_IIR
, 0xffffffff);
3430 I915_WRITE(VLV_IER
, ~dev_priv
->irq_mask
);
3431 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3432 POSTING_READ(VLV_IMR
);
3434 /* Interrupt setup is already guaranteed to be single-threaded, this is
3435 * just to make the assert_spin_locked check happy. */
3436 spin_lock_irq(&dev_priv
->irq_lock
);
3437 if (dev_priv
->display_irqs_enabled
)
3438 valleyview_display_irqs_install(dev_priv
);
3439 spin_unlock_irq(&dev_priv
->irq_lock
);
3442 static int valleyview_irq_postinstall(struct drm_device
*dev
)
3444 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3446 vlv_display_irq_postinstall(dev_priv
);
3448 gen5_gt_irq_postinstall(dev
);
3450 /* ack & enable invalid PTE error interrupts */
3451 #if 0 /* FIXME: add support to irq handler for checking these bits */
3452 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
3453 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
3456 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
3461 static void gen8_gt_irq_postinstall(struct drm_i915_private
*dev_priv
)
3463 /* These are interrupts we'll toggle with the ring mask register */
3464 uint32_t gt_interrupts
[] = {
3465 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3466 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3467 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
|
3468 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
|
3469 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
,
3470 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3471 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3472 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
|
3473 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
,
3475 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
|
3476 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
3479 dev_priv
->pm_irq_mask
= 0xffffffff;
3480 GEN8_IRQ_INIT_NDX(GT
, 0, ~gt_interrupts
[0], gt_interrupts
[0]);
3481 GEN8_IRQ_INIT_NDX(GT
, 1, ~gt_interrupts
[1], gt_interrupts
[1]);
3482 GEN8_IRQ_INIT_NDX(GT
, 2, dev_priv
->pm_irq_mask
, dev_priv
->pm_rps_events
);
3483 GEN8_IRQ_INIT_NDX(GT
, 3, ~gt_interrupts
[3], gt_interrupts
[3]);
3486 static void gen8_de_irq_postinstall(struct drm_i915_private
*dev_priv
)
3488 uint32_t de_pipe_masked
= GEN8_PIPE_CDCLK_CRC_DONE
;
3489 uint32_t de_pipe_enables
;
3492 if (IS_GEN9(dev_priv
))
3493 de_pipe_masked
|= GEN9_PIPE_PLANE1_FLIP_DONE
|
3494 GEN9_DE_PIPE_IRQ_FAULT_ERRORS
;
3496 de_pipe_masked
|= GEN8_PIPE_PRIMARY_FLIP_DONE
|
3497 GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
3499 de_pipe_enables
= de_pipe_masked
| GEN8_PIPE_VBLANK
|
3500 GEN8_PIPE_FIFO_UNDERRUN
;
3502 dev_priv
->de_irq_mask
[PIPE_A
] = ~de_pipe_masked
;
3503 dev_priv
->de_irq_mask
[PIPE_B
] = ~de_pipe_masked
;
3504 dev_priv
->de_irq_mask
[PIPE_C
] = ~de_pipe_masked
;
3506 for_each_pipe(dev_priv
, pipe
)
3507 if (intel_display_power_is_enabled(dev_priv
,
3508 POWER_DOMAIN_PIPE(pipe
)))
3509 GEN8_IRQ_INIT_NDX(DE_PIPE
, pipe
,
3510 dev_priv
->de_irq_mask
[pipe
],
3513 GEN5_IRQ_INIT(GEN8_DE_PORT_
, ~GEN8_AUX_CHANNEL_A
, GEN8_AUX_CHANNEL_A
);
3516 static int gen8_irq_postinstall(struct drm_device
*dev
)
3518 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3520 ibx_irq_pre_postinstall(dev
);
3522 gen8_gt_irq_postinstall(dev_priv
);
3523 gen8_de_irq_postinstall(dev_priv
);
3525 ibx_irq_postinstall(dev
);
3527 I915_WRITE(GEN8_MASTER_IRQ
, DE_MASTER_IRQ_CONTROL
);
3528 POSTING_READ(GEN8_MASTER_IRQ
);
3533 static int cherryview_irq_postinstall(struct drm_device
*dev
)
3535 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3536 u32 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
|
3537 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3538 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3539 I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
3540 u32 pipestat_enable
= PLANE_FLIP_DONE_INT_STATUS_VLV
|
3541 PIPE_CRC_DONE_INTERRUPT_STATUS
;
3545 * Leave vblank interrupts masked initially. enable/disable will
3546 * toggle them based on usage.
3548 dev_priv
->irq_mask
= ~enable_mask
;
3550 for_each_pipe(dev_priv
, pipe
)
3551 I915_WRITE(PIPESTAT(pipe
), 0xffff);
3553 spin_lock_irq(&dev_priv
->irq_lock
);
3554 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
3555 for_each_pipe(dev_priv
, pipe
)
3556 i915_enable_pipestat(dev_priv
, pipe
, pipestat_enable
);
3557 spin_unlock_irq(&dev_priv
->irq_lock
);
3559 I915_WRITE(VLV_IIR
, 0xffffffff);
3560 I915_WRITE(VLV_IIR
, 0xffffffff);
3561 I915_WRITE(VLV_IER
, enable_mask
);
3562 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3563 POSTING_READ(VLV_IMR
);
3565 gen8_gt_irq_postinstall(dev_priv
);
3567 I915_WRITE(GEN8_MASTER_IRQ
, MASTER_INTERRUPT_ENABLE
);
3568 POSTING_READ(GEN8_MASTER_IRQ
);
3573 static void gen8_irq_uninstall(struct drm_device
*dev
)
3575 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3580 gen8_irq_reset(dev
);
3583 static void valleyview_irq_uninstall(struct drm_device
*dev
)
3585 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3590 I915_WRITE(VLV_MASTER_IER
, 0);
3592 gen5_gt_irq_reset(dev
);
3594 I915_WRITE(HWSTAM
, 0xffffffff);
3596 /* Interrupt setup is already guaranteed to be single-threaded, this is
3597 * just to make the assert_spin_locked check happy. */
3598 spin_lock_irq(&dev_priv
->irq_lock
);
3599 if (dev_priv
->display_irqs_enabled
)
3600 valleyview_display_irqs_uninstall(dev_priv
);
3601 spin_unlock_irq(&dev_priv
->irq_lock
);
3603 vlv_display_irq_reset(dev_priv
);
3605 dev_priv
->irq_mask
= 0;
3608 static void cherryview_irq_uninstall(struct drm_device
*dev
)
3610 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3616 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3617 POSTING_READ(GEN8_MASTER_IRQ
);
3619 gen8_gt_irq_reset(dev_priv
);
3621 GEN5_IRQ_RESET(GEN8_PCU_
);
3623 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3624 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3626 for_each_pipe(dev_priv
, pipe
)
3627 I915_WRITE(PIPESTAT(pipe
), 0xffff);
3629 GEN5_IRQ_RESET(VLV_
);
3632 static void ironlake_irq_uninstall(struct drm_device
*dev
)
3634 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3639 ironlake_irq_reset(dev
);
3642 static void i8xx_irq_preinstall(struct drm_device
* dev
)
3644 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3647 for_each_pipe(dev_priv
, pipe
)
3648 I915_WRITE(PIPESTAT(pipe
), 0);
3649 I915_WRITE16(IMR
, 0xffff);
3650 I915_WRITE16(IER
, 0x0);
3651 POSTING_READ16(IER
);
3654 static int i8xx_irq_postinstall(struct drm_device
*dev
)
3656 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3659 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3661 /* Unmask the interrupts that we always want on. */
3662 dev_priv
->irq_mask
=
3663 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3664 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3665 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3666 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
3667 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
3668 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
3671 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3672 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3673 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
3674 I915_USER_INTERRUPT
);
3675 POSTING_READ16(IER
);
3677 /* Interrupt setup is already guaranteed to be single-threaded, this is
3678 * just to make the assert_spin_locked check happy. */
3679 spin_lock_irq(&dev_priv
->irq_lock
);
3680 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3681 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3682 spin_unlock_irq(&dev_priv
->irq_lock
);
3688 * Returns true when a page flip has completed.
3690 static bool i8xx_handle_vblank(struct drm_device
*dev
,
3691 int plane
, int pipe
, u32 iir
)
3693 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3694 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3696 if (!intel_pipe_handle_vblank(dev
, pipe
))
3699 if ((iir
& flip_pending
) == 0)
3700 goto check_page_flip
;
3702 intel_prepare_page_flip(dev
, plane
);
3704 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3705 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3706 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3707 * the flip is completed (no longer pending). Since this doesn't raise
3708 * an interrupt per se, we watch for the change at vblank.
3710 if (I915_READ16(ISR
) & flip_pending
)
3711 goto check_page_flip
;
3713 intel_finish_page_flip(dev
, pipe
);
3717 intel_check_page_flip(dev
, pipe
);
3721 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
3723 struct drm_device
*dev
= arg
;
3724 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3729 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3730 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3732 iir
= I915_READ16(IIR
);
3736 while (iir
& ~flip_mask
) {
3737 /* Can't rely on pipestat interrupt bit in iir as it might
3738 * have been cleared after the pipestat interrupt was received.
3739 * It doesn't set the bit in iir again, but it still produces
3740 * interrupts (for non-MSI).
3742 spin_lock(&dev_priv
->irq_lock
);
3743 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3744 i915_handle_error(dev
, false,
3745 "Command parser error, iir 0x%08x",
3748 for_each_pipe(dev_priv
, pipe
) {
3749 int reg
= PIPESTAT(pipe
);
3750 pipe_stats
[pipe
] = I915_READ(reg
);
3753 * Clear the PIPE*STAT regs before the IIR
3755 if (pipe_stats
[pipe
] & 0x8000ffff)
3756 I915_WRITE(reg
, pipe_stats
[pipe
]);
3758 spin_unlock(&dev_priv
->irq_lock
);
3760 I915_WRITE16(IIR
, iir
& ~flip_mask
);
3761 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
3763 i915_update_dri1_breadcrumb(dev
);
3765 if (iir
& I915_USER_INTERRUPT
)
3766 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3768 for_each_pipe(dev_priv
, pipe
) {
3773 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3774 i8xx_handle_vblank(dev
, plane
, pipe
, iir
))
3775 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
3777 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
3778 i9xx_pipe_crc_irq_handler(dev
, pipe
);
3780 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3781 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
3791 static void i8xx_irq_uninstall(struct drm_device
* dev
)
3793 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3796 for_each_pipe(dev_priv
, pipe
) {
3797 /* Clear enable bits; then clear status bits */
3798 I915_WRITE(PIPESTAT(pipe
), 0);
3799 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
3801 I915_WRITE16(IMR
, 0xffff);
3802 I915_WRITE16(IER
, 0x0);
3803 I915_WRITE16(IIR
, I915_READ16(IIR
));
3806 static void i915_irq_preinstall(struct drm_device
* dev
)
3808 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3811 if (I915_HAS_HOTPLUG(dev
)) {
3812 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3813 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3816 I915_WRITE16(HWSTAM
, 0xeffe);
3817 for_each_pipe(dev_priv
, pipe
)
3818 I915_WRITE(PIPESTAT(pipe
), 0);
3819 I915_WRITE(IMR
, 0xffffffff);
3820 I915_WRITE(IER
, 0x0);
3824 static int i915_irq_postinstall(struct drm_device
*dev
)
3826 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3829 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3831 /* Unmask the interrupts that we always want on. */
3832 dev_priv
->irq_mask
=
3833 ~(I915_ASLE_INTERRUPT
|
3834 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3835 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3836 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3837 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
3838 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
3841 I915_ASLE_INTERRUPT
|
3842 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3843 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3844 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
3845 I915_USER_INTERRUPT
;
3847 if (I915_HAS_HOTPLUG(dev
)) {
3848 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3849 POSTING_READ(PORT_HOTPLUG_EN
);
3851 /* Enable in IER... */
3852 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
3853 /* and unmask in IMR */
3854 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
3857 I915_WRITE(IMR
, dev_priv
->irq_mask
);
3858 I915_WRITE(IER
, enable_mask
);
3861 i915_enable_asle_pipestat(dev
);
3863 /* Interrupt setup is already guaranteed to be single-threaded, this is
3864 * just to make the assert_spin_locked check happy. */
3865 spin_lock_irq(&dev_priv
->irq_lock
);
3866 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3867 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3868 spin_unlock_irq(&dev_priv
->irq_lock
);
3874 * Returns true when a page flip has completed.
3876 static bool i915_handle_vblank(struct drm_device
*dev
,
3877 int plane
, int pipe
, u32 iir
)
3879 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3880 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3882 if (!intel_pipe_handle_vblank(dev
, pipe
))
3885 if ((iir
& flip_pending
) == 0)
3886 goto check_page_flip
;
3888 intel_prepare_page_flip(dev
, plane
);
3890 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3891 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3892 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3893 * the flip is completed (no longer pending). Since this doesn't raise
3894 * an interrupt per se, we watch for the change at vblank.
3896 if (I915_READ(ISR
) & flip_pending
)
3897 goto check_page_flip
;
3899 intel_finish_page_flip(dev
, pipe
);
3903 intel_check_page_flip(dev
, pipe
);
3907 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
3909 struct drm_device
*dev
= arg
;
3910 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3911 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
3913 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3914 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3915 int pipe
, ret
= IRQ_NONE
;
3917 iir
= I915_READ(IIR
);
3919 bool irq_received
= (iir
& ~flip_mask
) != 0;
3920 bool blc_event
= false;
3922 /* Can't rely on pipestat interrupt bit in iir as it might
3923 * have been cleared after the pipestat interrupt was received.
3924 * It doesn't set the bit in iir again, but it still produces
3925 * interrupts (for non-MSI).
3927 spin_lock(&dev_priv
->irq_lock
);
3928 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3929 i915_handle_error(dev
, false,
3930 "Command parser error, iir 0x%08x",
3933 for_each_pipe(dev_priv
, pipe
) {
3934 int reg
= PIPESTAT(pipe
);
3935 pipe_stats
[pipe
] = I915_READ(reg
);
3937 /* Clear the PIPE*STAT regs before the IIR */
3938 if (pipe_stats
[pipe
] & 0x8000ffff) {
3939 I915_WRITE(reg
, pipe_stats
[pipe
]);
3940 irq_received
= true;
3943 spin_unlock(&dev_priv
->irq_lock
);
3948 /* Consume port. Then clear IIR or we'll miss events */
3949 if (I915_HAS_HOTPLUG(dev
) &&
3950 iir
& I915_DISPLAY_PORT_INTERRUPT
)
3951 i9xx_hpd_irq_handler(dev
);
3953 I915_WRITE(IIR
, iir
& ~flip_mask
);
3954 new_iir
= I915_READ(IIR
); /* Flush posted writes */
3956 if (iir
& I915_USER_INTERRUPT
)
3957 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3959 for_each_pipe(dev_priv
, pipe
) {
3964 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3965 i915_handle_vblank(dev
, plane
, pipe
, iir
))
3966 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
3968 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
3971 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
3972 i9xx_pipe_crc_irq_handler(dev
, pipe
);
3974 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3975 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
3979 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
3980 intel_opregion_asle_intr(dev
);
3982 /* With MSI, interrupts are only generated when iir
3983 * transitions from zero to nonzero. If another bit got
3984 * set while we were handling the existing iir bits, then
3985 * we would never get another interrupt.
3987 * This is fine on non-MSI as well, as if we hit this path
3988 * we avoid exiting the interrupt handler only to generate
3991 * Note that for MSI this could cause a stray interrupt report
3992 * if an interrupt landed in the time between writing IIR and
3993 * the posting read. This should be rare enough to never
3994 * trigger the 99% of 100,000 interrupts test for disabling
3999 } while (iir
& ~flip_mask
);
4001 i915_update_dri1_breadcrumb(dev
);
4006 static void i915_irq_uninstall(struct drm_device
* dev
)
4008 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4011 if (I915_HAS_HOTPLUG(dev
)) {
4012 I915_WRITE(PORT_HOTPLUG_EN
, 0);
4013 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4016 I915_WRITE16(HWSTAM
, 0xffff);
4017 for_each_pipe(dev_priv
, pipe
) {
4018 /* Clear enable bits; then clear status bits */
4019 I915_WRITE(PIPESTAT(pipe
), 0);
4020 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
4022 I915_WRITE(IMR
, 0xffffffff);
4023 I915_WRITE(IER
, 0x0);
4025 I915_WRITE(IIR
, I915_READ(IIR
));
4028 static void i965_irq_preinstall(struct drm_device
* dev
)
4030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4033 I915_WRITE(PORT_HOTPLUG_EN
, 0);
4034 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4036 I915_WRITE(HWSTAM
, 0xeffe);
4037 for_each_pipe(dev_priv
, pipe
)
4038 I915_WRITE(PIPESTAT(pipe
), 0);
4039 I915_WRITE(IMR
, 0xffffffff);
4040 I915_WRITE(IER
, 0x0);
4044 static int i965_irq_postinstall(struct drm_device
*dev
)
4046 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4050 /* Unmask the interrupts that we always want on. */
4051 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
4052 I915_DISPLAY_PORT_INTERRUPT
|
4053 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
4054 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
4055 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4056 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
4057 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
4059 enable_mask
= ~dev_priv
->irq_mask
;
4060 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4061 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
4062 enable_mask
|= I915_USER_INTERRUPT
;
4065 enable_mask
|= I915_BSD_USER_INTERRUPT
;
4067 /* Interrupt setup is already guaranteed to be single-threaded, this is
4068 * just to make the assert_spin_locked check happy. */
4069 spin_lock_irq(&dev_priv
->irq_lock
);
4070 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
4071 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4072 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4073 spin_unlock_irq(&dev_priv
->irq_lock
);
4076 * Enable some error detection, note the instruction error mask
4077 * bit is reserved, so we leave it masked.
4080 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
4081 GM45_ERROR_MEM_PRIV
|
4082 GM45_ERROR_CP_PRIV
|
4083 I915_ERROR_MEMORY_REFRESH
);
4085 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
4086 I915_ERROR_MEMORY_REFRESH
);
4088 I915_WRITE(EMR
, error_mask
);
4090 I915_WRITE(IMR
, dev_priv
->irq_mask
);
4091 I915_WRITE(IER
, enable_mask
);
4094 I915_WRITE(PORT_HOTPLUG_EN
, 0);
4095 POSTING_READ(PORT_HOTPLUG_EN
);
4097 i915_enable_asle_pipestat(dev
);
4102 static void i915_hpd_irq_setup(struct drm_device
*dev
)
4104 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4105 struct intel_encoder
*intel_encoder
;
4108 assert_spin_locked(&dev_priv
->irq_lock
);
4110 if (I915_HAS_HOTPLUG(dev
)) {
4111 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
4112 hotplug_en
&= ~HOTPLUG_INT_EN_MASK
;
4113 /* Note HDMI and DP share hotplug bits */
4114 /* enable bits are the same for all generations */
4115 for_each_intel_encoder(dev
, intel_encoder
)
4116 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
4117 hotplug_en
|= hpd_mask_i915
[intel_encoder
->hpd_pin
];
4118 /* Programming the CRT detection parameters tends
4119 to generate a spurious hotplug event about three
4120 seconds later. So just do it once.
4123 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
4124 hotplug_en
&= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
;
4125 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
4127 /* Ignore TV since it's buggy */
4128 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
4132 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
4134 struct drm_device
*dev
= arg
;
4135 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4137 u32 pipe_stats
[I915_MAX_PIPES
];
4138 int ret
= IRQ_NONE
, pipe
;
4140 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4141 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
4143 iir
= I915_READ(IIR
);
4146 bool irq_received
= (iir
& ~flip_mask
) != 0;
4147 bool blc_event
= false;
4149 /* Can't rely on pipestat interrupt bit in iir as it might
4150 * have been cleared after the pipestat interrupt was received.
4151 * It doesn't set the bit in iir again, but it still produces
4152 * interrupts (for non-MSI).
4154 spin_lock(&dev_priv
->irq_lock
);
4155 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
4156 i915_handle_error(dev
, false,
4157 "Command parser error, iir 0x%08x",
4160 for_each_pipe(dev_priv
, pipe
) {
4161 int reg
= PIPESTAT(pipe
);
4162 pipe_stats
[pipe
] = I915_READ(reg
);
4165 * Clear the PIPE*STAT regs before the IIR
4167 if (pipe_stats
[pipe
] & 0x8000ffff) {
4168 I915_WRITE(reg
, pipe_stats
[pipe
]);
4169 irq_received
= true;
4172 spin_unlock(&dev_priv
->irq_lock
);
4179 /* Consume port. Then clear IIR or we'll miss events */
4180 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
4181 i9xx_hpd_irq_handler(dev
);
4183 I915_WRITE(IIR
, iir
& ~flip_mask
);
4184 new_iir
= I915_READ(IIR
); /* Flush posted writes */
4186 if (iir
& I915_USER_INTERRUPT
)
4187 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
4188 if (iir
& I915_BSD_USER_INTERRUPT
)
4189 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
4191 for_each_pipe(dev_priv
, pipe
) {
4192 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
4193 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
4194 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
4196 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
4199 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
4200 i9xx_pipe_crc_irq_handler(dev
, pipe
);
4202 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
4203 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
4206 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
4207 intel_opregion_asle_intr(dev
);
4209 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
4210 gmbus_irq_handler(dev
);
4212 /* With MSI, interrupts are only generated when iir
4213 * transitions from zero to nonzero. If another bit got
4214 * set while we were handling the existing iir bits, then
4215 * we would never get another interrupt.
4217 * This is fine on non-MSI as well, as if we hit this path
4218 * we avoid exiting the interrupt handler only to generate
4221 * Note that for MSI this could cause a stray interrupt report
4222 * if an interrupt landed in the time between writing IIR and
4223 * the posting read. This should be rare enough to never
4224 * trigger the 99% of 100,000 interrupts test for disabling
4230 i915_update_dri1_breadcrumb(dev
);
4235 static void i965_irq_uninstall(struct drm_device
* dev
)
4237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4243 I915_WRITE(PORT_HOTPLUG_EN
, 0);
4244 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4246 I915_WRITE(HWSTAM
, 0xffffffff);
4247 for_each_pipe(dev_priv
, pipe
)
4248 I915_WRITE(PIPESTAT(pipe
), 0);
4249 I915_WRITE(IMR
, 0xffffffff);
4250 I915_WRITE(IER
, 0x0);
4252 for_each_pipe(dev_priv
, pipe
)
4253 I915_WRITE(PIPESTAT(pipe
),
4254 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
4255 I915_WRITE(IIR
, I915_READ(IIR
));
4258 static void intel_hpd_irq_reenable_work(struct work_struct
*work
)
4260 struct drm_i915_private
*dev_priv
=
4261 container_of(work
, typeof(*dev_priv
),
4262 hotplug_reenable_work
.work
);
4263 struct drm_device
*dev
= dev_priv
->dev
;
4264 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4267 intel_runtime_pm_get(dev_priv
);
4269 spin_lock_irq(&dev_priv
->irq_lock
);
4270 for (i
= (HPD_NONE
+ 1); i
< HPD_NUM_PINS
; i
++) {
4271 struct drm_connector
*connector
;
4273 if (dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_DISABLED
)
4276 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
4278 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
4279 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4281 if (intel_connector
->encoder
->hpd_pin
== i
) {
4282 if (connector
->polled
!= intel_connector
->polled
)
4283 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4285 connector
->polled
= intel_connector
->polled
;
4286 if (!connector
->polled
)
4287 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
4291 if (dev_priv
->display
.hpd_irq_setup
)
4292 dev_priv
->display
.hpd_irq_setup(dev
);
4293 spin_unlock_irq(&dev_priv
->irq_lock
);
4295 intel_runtime_pm_put(dev_priv
);
4299 * intel_irq_init - initializes irq support
4300 * @dev_priv: i915 device instance
4302 * This function initializes all the irq support including work items, timers
4303 * and all the vtables. It does not setup the interrupt itself though.
4305 void intel_irq_init(struct drm_i915_private
*dev_priv
)
4307 struct drm_device
*dev
= dev_priv
->dev
;
4309 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
4310 INIT_WORK(&dev_priv
->dig_port_work
, i915_digport_work_func
);
4311 INIT_WORK(&dev_priv
->gpu_error
.work
, i915_error_work_func
);
4312 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
4313 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
4315 /* Let's track the enabled rps events */
4316 if (IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
4317 /* WaGsvRC0ResidencyMethod:vlv */
4318 dev_priv
->pm_rps_events
= GEN6_PM_RP_UP_EI_EXPIRED
;
4320 dev_priv
->pm_rps_events
= GEN6_PM_RPS_EVENTS
;
4322 setup_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
4323 i915_hangcheck_elapsed
,
4324 (unsigned long) dev
);
4325 INIT_DELAYED_WORK(&dev_priv
->hotplug_reenable_work
,
4326 intel_hpd_irq_reenable_work
);
4328 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
4330 if (IS_GEN2(dev_priv
)) {
4331 dev
->max_vblank_count
= 0;
4332 dev
->driver
->get_vblank_counter
= i8xx_get_vblank_counter
;
4333 } else if (IS_G4X(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 5) {
4334 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
4335 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
4337 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
4338 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
4342 * Opt out of the vblank disable timer on everything except gen2.
4343 * Gen2 doesn't have a hardware frame counter and so depends on
4344 * vblank interrupts to produce sane vblank seuquence numbers.
4346 if (!IS_GEN2(dev_priv
))
4347 dev
->vblank_disable_immediate
= true;
4349 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4350 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
4351 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
4354 if (IS_CHERRYVIEW(dev_priv
)) {
4355 dev
->driver
->irq_handler
= cherryview_irq_handler
;
4356 dev
->driver
->irq_preinstall
= cherryview_irq_preinstall
;
4357 dev
->driver
->irq_postinstall
= cherryview_irq_postinstall
;
4358 dev
->driver
->irq_uninstall
= cherryview_irq_uninstall
;
4359 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
4360 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
4361 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4362 } else if (IS_VALLEYVIEW(dev_priv
)) {
4363 dev
->driver
->irq_handler
= valleyview_irq_handler
;
4364 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
4365 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
4366 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
4367 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
4368 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
4369 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4370 } else if (INTEL_INFO(dev_priv
)->gen
>= 8) {
4371 dev
->driver
->irq_handler
= gen8_irq_handler
;
4372 dev
->driver
->irq_preinstall
= gen8_irq_reset
;
4373 dev
->driver
->irq_postinstall
= gen8_irq_postinstall
;
4374 dev
->driver
->irq_uninstall
= gen8_irq_uninstall
;
4375 dev
->driver
->enable_vblank
= gen8_enable_vblank
;
4376 dev
->driver
->disable_vblank
= gen8_disable_vblank
;
4377 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
4378 } else if (HAS_PCH_SPLIT(dev
)) {
4379 dev
->driver
->irq_handler
= ironlake_irq_handler
;
4380 dev
->driver
->irq_preinstall
= ironlake_irq_reset
;
4381 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
4382 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
4383 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
4384 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
4385 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
4387 if (INTEL_INFO(dev_priv
)->gen
== 2) {
4388 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
4389 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
4390 dev
->driver
->irq_handler
= i8xx_irq_handler
;
4391 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
4392 } else if (INTEL_INFO(dev_priv
)->gen
== 3) {
4393 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
4394 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
4395 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
4396 dev
->driver
->irq_handler
= i915_irq_handler
;
4397 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4399 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
4400 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
4401 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
4402 dev
->driver
->irq_handler
= i965_irq_handler
;
4403 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4405 dev
->driver
->enable_vblank
= i915_enable_vblank
;
4406 dev
->driver
->disable_vblank
= i915_disable_vblank
;
4411 * intel_hpd_init - initializes and enables hpd support
4412 * @dev_priv: i915 device instance
4414 * This function enables the hotplug support. It requires that interrupts have
4415 * already been enabled with intel_irq_init_hw(). From this point on hotplug and
4416 * poll request can run concurrently to other code, so locking rules must be
4419 * This is a separate step from interrupt enabling to simplify the locking rules
4420 * in the driver load and resume code.
4422 void intel_hpd_init(struct drm_i915_private
*dev_priv
)
4424 struct drm_device
*dev
= dev_priv
->dev
;
4425 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4426 struct drm_connector
*connector
;
4429 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
4430 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
4431 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
4433 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
4434 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4435 connector
->polled
= intel_connector
->polled
;
4436 if (connector
->encoder
&& !connector
->polled
&& I915_HAS_HOTPLUG(dev
) && intel_connector
->encoder
->hpd_pin
> HPD_NONE
)
4437 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
4438 if (intel_connector
->mst_port
)
4439 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
4442 /* Interrupt setup is already guaranteed to be single-threaded, this is
4443 * just to make the assert_spin_locked checks happy. */
4444 spin_lock_irq(&dev_priv
->irq_lock
);
4445 if (dev_priv
->display
.hpd_irq_setup
)
4446 dev_priv
->display
.hpd_irq_setup(dev
);
4447 spin_unlock_irq(&dev_priv
->irq_lock
);
4451 * intel_irq_install - enables the hardware interrupt
4452 * @dev_priv: i915 device instance
4454 * This function enables the hardware interrupt handling, but leaves the hotplug
4455 * handling still disabled. It is called after intel_irq_init().
4457 * In the driver load and resume code we need working interrupts in a few places
4458 * but don't want to deal with the hassle of concurrent probe and hotplug
4459 * workers. Hence the split into this two-stage approach.
4461 int intel_irq_install(struct drm_i915_private
*dev_priv
)
4464 * We enable some interrupt sources in our postinstall hooks, so mark
4465 * interrupts as enabled _before_ actually enabling them to avoid
4466 * special cases in our ordering checks.
4468 dev_priv
->pm
.irqs_enabled
= true;
4470 return drm_irq_install(dev_priv
->dev
, dev_priv
->dev
->pdev
->irq
);
4474 * intel_irq_uninstall - finilizes all irq handling
4475 * @dev_priv: i915 device instance
4477 * This stops interrupt and hotplug handling and unregisters and frees all
4478 * resources acquired in the init functions.
4480 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
)
4482 drm_irq_uninstall(dev_priv
->dev
);
4483 intel_hpd_cancel_work(dev_priv
);
4484 dev_priv
->pm
.irqs_enabled
= false;
4488 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4489 * @dev_priv: i915 device instance
4491 * This function is used to disable interrupts at runtime, both in the runtime
4492 * pm and the system suspend/resume code.
4494 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
)
4496 dev_priv
->dev
->driver
->irq_uninstall(dev_priv
->dev
);
4497 dev_priv
->pm
.irqs_enabled
= false;
4501 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4502 * @dev_priv: i915 device instance
4504 * This function is used to enable interrupts at runtime, both in the runtime
4505 * pm and the system suspend/resume code.
4507 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
)
4509 dev_priv
->pm
.irqs_enabled
= true;
4510 dev_priv
->dev
->driver
->irq_preinstall(dev_priv
->dev
);
4511 dev_priv
->dev
->driver
->irq_postinstall(dev_priv
->dev
);