1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
41 * DOC: interrupt handling
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
48 static const u32 hpd_ibx
[] = {
49 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
50 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
51 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
52 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
53 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
56 static const u32 hpd_cpt
[] = {
57 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
58 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
59 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
60 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
61 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
64 static const u32 hpd_mask_i915
[] = {
65 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
66 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
67 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
68 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
69 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
70 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
73 static const u32 hpd_status_g4x
[] = {
74 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
75 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
76 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
77 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
78 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
79 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
82 static const u32 hpd_status_i915
[] = { /* i915 and valleyview are the same */
83 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
84 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
85 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
86 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
87 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
88 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
91 /* IIR can theoretically queue up two events. Be paranoid. */
92 #define GEN8_IRQ_RESET_NDX(type, which) do { \
93 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
94 POSTING_READ(GEN8_##type##_IMR(which)); \
95 I915_WRITE(GEN8_##type##_IER(which), 0); \
96 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
97 POSTING_READ(GEN8_##type##_IIR(which)); \
98 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
99 POSTING_READ(GEN8_##type##_IIR(which)); \
102 #define GEN5_IRQ_RESET(type) do { \
103 I915_WRITE(type##IMR, 0xffffffff); \
104 POSTING_READ(type##IMR); \
105 I915_WRITE(type##IER, 0); \
106 I915_WRITE(type##IIR, 0xffffffff); \
107 POSTING_READ(type##IIR); \
108 I915_WRITE(type##IIR, 0xffffffff); \
109 POSTING_READ(type##IIR); \
113 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
115 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
116 u32 val = I915_READ(reg); \
118 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
120 I915_WRITE((reg), 0xffffffff); \
122 I915_WRITE((reg), 0xffffffff); \
127 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
128 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
129 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
130 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
131 POSTING_READ(GEN8_##type##_IMR(which)); \
134 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
135 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
136 I915_WRITE(type##IER, (ier_val)); \
137 I915_WRITE(type##IMR, (imr_val)); \
138 POSTING_READ(type##IMR); \
141 /* For display hotplug interrupt */
143 ironlake_enable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
)
145 assert_spin_locked(&dev_priv
->irq_lock
);
147 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
150 if ((dev_priv
->irq_mask
& mask
) != 0) {
151 dev_priv
->irq_mask
&= ~mask
;
152 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
158 ironlake_disable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
)
160 assert_spin_locked(&dev_priv
->irq_lock
);
162 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
165 if ((dev_priv
->irq_mask
& mask
) != mask
) {
166 dev_priv
->irq_mask
|= mask
;
167 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
173 * ilk_update_gt_irq - update GTIMR
174 * @dev_priv: driver private
175 * @interrupt_mask: mask of interrupt bits to update
176 * @enabled_irq_mask: mask of interrupt bits to enable
178 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
179 uint32_t interrupt_mask
,
180 uint32_t enabled_irq_mask
)
182 assert_spin_locked(&dev_priv
->irq_lock
);
184 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
187 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
188 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
189 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
193 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
195 ilk_update_gt_irq(dev_priv
, mask
, mask
);
198 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
200 ilk_update_gt_irq(dev_priv
, mask
, 0);
203 static u32
gen6_pm_imr(struct drm_i915_private
*dev_priv
)
205 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR
;
209 * snb_update_pm_irq - update GEN6_PMIMR
210 * @dev_priv: driver private
211 * @interrupt_mask: mask of interrupt bits to update
212 * @enabled_irq_mask: mask of interrupt bits to enable
214 static void snb_update_pm_irq(struct drm_i915_private
*dev_priv
,
215 uint32_t interrupt_mask
,
216 uint32_t enabled_irq_mask
)
220 assert_spin_locked(&dev_priv
->irq_lock
);
222 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
225 new_val
= dev_priv
->pm_irq_mask
;
226 new_val
&= ~interrupt_mask
;
227 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
229 if (new_val
!= dev_priv
->pm_irq_mask
) {
230 dev_priv
->pm_irq_mask
= new_val
;
231 I915_WRITE(gen6_pm_imr(dev_priv
), dev_priv
->pm_irq_mask
);
232 POSTING_READ(gen6_pm_imr(dev_priv
));
236 void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
238 snb_update_pm_irq(dev_priv
, mask
, mask
);
241 void gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
243 snb_update_pm_irq(dev_priv
, mask
, 0);
247 * ibx_display_interrupt_update - update SDEIMR
248 * @dev_priv: driver private
249 * @interrupt_mask: mask of interrupt bits to update
250 * @enabled_irq_mask: mask of interrupt bits to enable
252 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
253 uint32_t interrupt_mask
,
254 uint32_t enabled_irq_mask
)
256 uint32_t sdeimr
= I915_READ(SDEIMR
);
257 sdeimr
&= ~interrupt_mask
;
258 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
260 assert_spin_locked(&dev_priv
->irq_lock
);
262 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
265 I915_WRITE(SDEIMR
, sdeimr
);
266 POSTING_READ(SDEIMR
);
270 __i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
271 u32 enable_mask
, u32 status_mask
)
273 u32 reg
= PIPESTAT(pipe
);
274 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
276 assert_spin_locked(&dev_priv
->irq_lock
);
277 WARN_ON(!intel_irqs_enabled(dev_priv
));
279 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
280 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
281 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
282 pipe_name(pipe
), enable_mask
, status_mask
))
285 if ((pipestat
& enable_mask
) == enable_mask
)
288 dev_priv
->pipestat_irq_mask
[pipe
] |= status_mask
;
290 /* Enable the interrupt, clear any pending status */
291 pipestat
|= enable_mask
| status_mask
;
292 I915_WRITE(reg
, pipestat
);
297 __i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
298 u32 enable_mask
, u32 status_mask
)
300 u32 reg
= PIPESTAT(pipe
);
301 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
303 assert_spin_locked(&dev_priv
->irq_lock
);
304 WARN_ON(!intel_irqs_enabled(dev_priv
));
306 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
307 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
308 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
309 pipe_name(pipe
), enable_mask
, status_mask
))
312 if ((pipestat
& enable_mask
) == 0)
315 dev_priv
->pipestat_irq_mask
[pipe
] &= ~status_mask
;
317 pipestat
&= ~enable_mask
;
318 I915_WRITE(reg
, pipestat
);
322 static u32
vlv_get_pipestat_enable_mask(struct drm_device
*dev
, u32 status_mask
)
324 u32 enable_mask
= status_mask
<< 16;
327 * On pipe A we don't support the PSR interrupt yet,
328 * on pipe B and C the same bit MBZ.
330 if (WARN_ON_ONCE(status_mask
& PIPE_A_PSR_STATUS_VLV
))
333 * On pipe B and C we don't support the PSR interrupt yet, on pipe
334 * A the same bit is for perf counters which we don't use either.
336 if (WARN_ON_ONCE(status_mask
& PIPE_B_PSR_STATUS_VLV
))
339 enable_mask
&= ~(PIPE_FIFO_UNDERRUN_STATUS
|
340 SPRITE0_FLIP_DONE_INT_EN_VLV
|
341 SPRITE1_FLIP_DONE_INT_EN_VLV
);
342 if (status_mask
& SPRITE0_FLIP_DONE_INT_STATUS_VLV
)
343 enable_mask
|= SPRITE0_FLIP_DONE_INT_EN_VLV
;
344 if (status_mask
& SPRITE1_FLIP_DONE_INT_STATUS_VLV
)
345 enable_mask
|= SPRITE1_FLIP_DONE_INT_EN_VLV
;
351 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
356 if (IS_VALLEYVIEW(dev_priv
->dev
))
357 enable_mask
= vlv_get_pipestat_enable_mask(dev_priv
->dev
,
360 enable_mask
= status_mask
<< 16;
361 __i915_enable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
365 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
370 if (IS_VALLEYVIEW(dev_priv
->dev
))
371 enable_mask
= vlv_get_pipestat_enable_mask(dev_priv
->dev
,
374 enable_mask
= status_mask
<< 16;
375 __i915_disable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
379 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
381 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
383 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
385 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
388 spin_lock_irq(&dev_priv
->irq_lock
);
390 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_LEGACY_BLC_EVENT_STATUS
);
391 if (INTEL_INFO(dev
)->gen
>= 4)
392 i915_enable_pipestat(dev_priv
, PIPE_A
,
393 PIPE_LEGACY_BLC_EVENT_STATUS
);
395 spin_unlock_irq(&dev_priv
->irq_lock
);
399 * i915_pipe_enabled - check if a pipe is enabled
401 * @pipe: pipe to check
403 * Reading certain registers when the pipe is disabled can hang the chip.
404 * Use this routine to make sure the PLL is running and the pipe is active
405 * before reading such registers if unsure.
408 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
410 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
412 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
413 /* Locking is horribly broken here, but whatever. */
414 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
415 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
417 return intel_crtc
->active
;
419 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
424 * This timing diagram depicts the video signal in and
425 * around the vertical blanking period.
427 * Assumptions about the fictitious mode used in this example:
429 * vsync_start = vblank_start + 1
430 * vsync_end = vblank_start + 2
431 * vtotal = vblank_start + 3
434 * latch double buffered registers
435 * increment frame counter (ctg+)
436 * generate start of vblank interrupt (gen4+)
439 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
440 * | may be shifted forward 1-3 extra lines via PIPECONF
442 * | | start of vsync:
443 * | | generate vsync interrupt
445 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
446 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
447 * ----va---> <-----------------vb--------------------> <--------va-------------
448 * | | <----vs-----> |
449 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
450 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
451 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
453 * last visible pixel first visible pixel
454 * | increment frame counter (gen3/4)
455 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
457 * x = horizontal active
458 * _ = horizontal blanking
459 * hs = horizontal sync
460 * va = vertical active
461 * vb = vertical blanking
463 * vbs = vblank_start (number)
466 * - most events happen at the start of horizontal sync
467 * - frame start happens at the start of horizontal blank, 1-4 lines
468 * (depending on PIPECONF settings) after the start of vblank
469 * - gen3/4 pixel and frame counter are synchronized with the start
470 * of horizontal active on the first line of vertical active
473 static u32
i8xx_get_vblank_counter(struct drm_device
*dev
, int pipe
)
475 /* Gen2 doesn't have a hardware frame counter */
479 /* Called from drm generic code, passed a 'crtc', which
480 * we use as a pipe index
482 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
484 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
485 unsigned long high_frame
;
486 unsigned long low_frame
;
487 u32 high1
, high2
, low
, pixel
, vbl_start
, hsync_start
, htotal
;
489 if (!i915_pipe_enabled(dev
, pipe
)) {
490 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
491 "pipe %c\n", pipe_name(pipe
));
495 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
496 struct intel_crtc
*intel_crtc
=
497 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
498 const struct drm_display_mode
*mode
=
499 &intel_crtc
->config
.adjusted_mode
;
501 htotal
= mode
->crtc_htotal
;
502 hsync_start
= mode
->crtc_hsync_start
;
503 vbl_start
= mode
->crtc_vblank_start
;
504 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
505 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
507 enum transcoder cpu_transcoder
= (enum transcoder
) pipe
;
509 htotal
= ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff) + 1;
510 hsync_start
= (I915_READ(HSYNC(cpu_transcoder
)) & 0x1fff) + 1;
511 vbl_start
= (I915_READ(VBLANK(cpu_transcoder
)) & 0x1fff) + 1;
512 if ((I915_READ(PIPECONF(cpu_transcoder
)) &
513 PIPECONF_INTERLACE_MASK
) != PIPECONF_PROGRESSIVE
)
514 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
517 /* Convert to pixel count */
520 /* Start of vblank event occurs at start of hsync */
521 vbl_start
-= htotal
- hsync_start
;
523 high_frame
= PIPEFRAME(pipe
);
524 low_frame
= PIPEFRAMEPIXEL(pipe
);
527 * High & low register fields aren't synchronized, so make sure
528 * we get a low value that's stable across two reads of the high
532 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
533 low
= I915_READ(low_frame
);
534 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
535 } while (high1
!= high2
);
537 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
538 pixel
= low
& PIPE_PIXEL_MASK
;
539 low
>>= PIPE_FRAME_LOW_SHIFT
;
542 * The frame counter increments at beginning of active.
543 * Cook up a vblank counter by also checking the pixel
544 * counter against vblank start.
546 return (((high1
<< 8) | low
) + (pixel
>= vbl_start
)) & 0xffffff;
549 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
551 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
552 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
554 if (!i915_pipe_enabled(dev
, pipe
)) {
555 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
556 "pipe %c\n", pipe_name(pipe
));
560 return I915_READ(reg
);
563 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
564 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
566 static int __intel_get_crtc_scanline(struct intel_crtc
*crtc
)
568 struct drm_device
*dev
= crtc
->base
.dev
;
569 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
570 const struct drm_display_mode
*mode
= &crtc
->config
.adjusted_mode
;
571 enum pipe pipe
= crtc
->pipe
;
572 int position
, vtotal
;
574 vtotal
= mode
->crtc_vtotal
;
575 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
579 position
= __raw_i915_read32(dev_priv
, PIPEDSL(pipe
)) & DSL_LINEMASK_GEN2
;
581 position
= __raw_i915_read32(dev_priv
, PIPEDSL(pipe
)) & DSL_LINEMASK_GEN3
;
584 * See update_scanline_offset() for the details on the
585 * scanline_offset adjustment.
587 return (position
+ crtc
->scanline_offset
) % vtotal
;
590 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
591 unsigned int flags
, int *vpos
, int *hpos
,
592 ktime_t
*stime
, ktime_t
*etime
)
594 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
595 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
596 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
597 const struct drm_display_mode
*mode
= &intel_crtc
->config
.adjusted_mode
;
599 int vbl_start
, vbl_end
, hsync_start
, htotal
, vtotal
;
602 unsigned long irqflags
;
604 if (!intel_crtc
->active
) {
605 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
606 "pipe %c\n", pipe_name(pipe
));
610 htotal
= mode
->crtc_htotal
;
611 hsync_start
= mode
->crtc_hsync_start
;
612 vtotal
= mode
->crtc_vtotal
;
613 vbl_start
= mode
->crtc_vblank_start
;
614 vbl_end
= mode
->crtc_vblank_end
;
616 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
617 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
622 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
625 * Lock uncore.lock, as we will do multiple timing critical raw
626 * register reads, potentially with preemption disabled, so the
627 * following code must not block on uncore.lock.
629 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
631 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
633 /* Get optional system timestamp before query. */
635 *stime
= ktime_get();
637 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
638 /* No obvious pixelcount register. Only query vertical
639 * scanout position from Display scan line register.
641 position
= __intel_get_crtc_scanline(intel_crtc
);
643 /* Have access to pixelcount since start of frame.
644 * We can split this into vertical and horizontal
647 position
= (__raw_i915_read32(dev_priv
, PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
649 /* convert to pixel counts */
655 * In interlaced modes, the pixel counter counts all pixels,
656 * so one field will have htotal more pixels. In order to avoid
657 * the reported position from jumping backwards when the pixel
658 * counter is beyond the length of the shorter field, just
659 * clamp the position the length of the shorter field. This
660 * matches how the scanline counter based position works since
661 * the scanline counter doesn't count the two half lines.
663 if (position
>= vtotal
)
664 position
= vtotal
- 1;
667 * Start of vblank interrupt is triggered at start of hsync,
668 * just prior to the first active line of vblank. However we
669 * consider lines to start at the leading edge of horizontal
670 * active. So, should we get here before we've crossed into
671 * the horizontal active of the first line in vblank, we would
672 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
673 * always add htotal-hsync_start to the current pixel position.
675 position
= (position
+ htotal
- hsync_start
) % vtotal
;
678 /* Get optional system timestamp after query. */
680 *etime
= ktime_get();
682 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
684 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
686 in_vbl
= position
>= vbl_start
&& position
< vbl_end
;
689 * While in vblank, position will be negative
690 * counting up towards 0 at vbl_end. And outside
691 * vblank, position will be positive counting
694 if (position
>= vbl_start
)
697 position
+= vtotal
- vbl_end
;
699 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
703 *vpos
= position
/ htotal
;
704 *hpos
= position
- (*vpos
* htotal
);
709 ret
|= DRM_SCANOUTPOS_IN_VBLANK
;
714 int intel_get_crtc_scanline(struct intel_crtc
*crtc
)
716 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
717 unsigned long irqflags
;
720 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
721 position
= __intel_get_crtc_scanline(crtc
);
722 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
727 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
729 struct timeval
*vblank_time
,
732 struct drm_crtc
*crtc
;
734 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
735 DRM_ERROR("Invalid crtc %d\n", pipe
);
739 /* Get drm_crtc to timestamp: */
740 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
742 DRM_ERROR("Invalid crtc %d\n", pipe
);
746 if (!crtc
->enabled
) {
747 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
751 /* Helper routine in DRM core does all the work: */
752 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
755 &to_intel_crtc(crtc
)->config
.adjusted_mode
);
758 static bool intel_hpd_irq_event(struct drm_device
*dev
,
759 struct drm_connector
*connector
)
761 enum drm_connector_status old_status
;
763 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
764 old_status
= connector
->status
;
766 connector
->status
= connector
->funcs
->detect(connector
, false);
767 if (old_status
== connector
->status
)
770 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
773 drm_get_connector_status_name(old_status
),
774 drm_get_connector_status_name(connector
->status
));
779 static void i915_digport_work_func(struct work_struct
*work
)
781 struct drm_i915_private
*dev_priv
=
782 container_of(work
, struct drm_i915_private
, dig_port_work
);
783 u32 long_port_mask
, short_port_mask
;
784 struct intel_digital_port
*intel_dig_port
;
788 spin_lock_irq(&dev_priv
->irq_lock
);
789 long_port_mask
= dev_priv
->long_hpd_port_mask
;
790 dev_priv
->long_hpd_port_mask
= 0;
791 short_port_mask
= dev_priv
->short_hpd_port_mask
;
792 dev_priv
->short_hpd_port_mask
= 0;
793 spin_unlock_irq(&dev_priv
->irq_lock
);
795 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
797 bool long_hpd
= false;
798 intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
799 if (!intel_dig_port
|| !intel_dig_port
->hpd_pulse
)
802 if (long_port_mask
& (1 << i
)) {
805 } else if (short_port_mask
& (1 << i
))
809 ret
= intel_dig_port
->hpd_pulse(intel_dig_port
, long_hpd
);
811 /* if we get true fallback to old school hpd */
812 old_bits
|= (1 << intel_dig_port
->base
.hpd_pin
);
818 spin_lock_irq(&dev_priv
->irq_lock
);
819 dev_priv
->hpd_event_bits
|= old_bits
;
820 spin_unlock_irq(&dev_priv
->irq_lock
);
821 schedule_work(&dev_priv
->hotplug_work
);
826 * Handle hotplug events outside the interrupt handler proper.
828 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
830 static void i915_hotplug_work_func(struct work_struct
*work
)
832 struct drm_i915_private
*dev_priv
=
833 container_of(work
, struct drm_i915_private
, hotplug_work
);
834 struct drm_device
*dev
= dev_priv
->dev
;
835 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
836 struct intel_connector
*intel_connector
;
837 struct intel_encoder
*intel_encoder
;
838 struct drm_connector
*connector
;
839 bool hpd_disabled
= false;
840 bool changed
= false;
843 mutex_lock(&mode_config
->mutex
);
844 DRM_DEBUG_KMS("running encoder hotplug functions\n");
846 spin_lock_irq(&dev_priv
->irq_lock
);
848 hpd_event_bits
= dev_priv
->hpd_event_bits
;
849 dev_priv
->hpd_event_bits
= 0;
850 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
851 intel_connector
= to_intel_connector(connector
);
852 if (!intel_connector
->encoder
)
854 intel_encoder
= intel_connector
->encoder
;
855 if (intel_encoder
->hpd_pin
> HPD_NONE
&&
856 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_MARK_DISABLED
&&
857 connector
->polled
== DRM_CONNECTOR_POLL_HPD
) {
858 DRM_INFO("HPD interrupt storm detected on connector %s: "
859 "switching from hotplug detection to polling\n",
861 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
= HPD_DISABLED
;
862 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
863 | DRM_CONNECTOR_POLL_DISCONNECT
;
866 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
867 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
868 connector
->name
, intel_encoder
->hpd_pin
);
871 /* if there were no outputs to poll, poll was disabled,
872 * therefore make sure it's enabled when disabling HPD on
875 drm_kms_helper_poll_enable(dev
);
876 mod_delayed_work(system_wq
, &dev_priv
->hotplug_reenable_work
,
877 msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY
));
880 spin_unlock_irq(&dev_priv
->irq_lock
);
882 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
883 intel_connector
= to_intel_connector(connector
);
884 if (!intel_connector
->encoder
)
886 intel_encoder
= intel_connector
->encoder
;
887 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
888 if (intel_encoder
->hot_plug
)
889 intel_encoder
->hot_plug(intel_encoder
);
890 if (intel_hpd_irq_event(dev
, connector
))
894 mutex_unlock(&mode_config
->mutex
);
897 drm_kms_helper_hotplug_event(dev
);
900 static void ironlake_rps_change_irq_handler(struct drm_device
*dev
)
902 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
903 u32 busy_up
, busy_down
, max_avg
, min_avg
;
906 spin_lock(&mchdev_lock
);
908 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
910 new_delay
= dev_priv
->ips
.cur_delay
;
912 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
913 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
914 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
915 max_avg
= I915_READ(RCBMAXAVG
);
916 min_avg
= I915_READ(RCBMINAVG
);
918 /* Handle RCS change request from hw */
919 if (busy_up
> max_avg
) {
920 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
921 new_delay
= dev_priv
->ips
.cur_delay
- 1;
922 if (new_delay
< dev_priv
->ips
.max_delay
)
923 new_delay
= dev_priv
->ips
.max_delay
;
924 } else if (busy_down
< min_avg
) {
925 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
926 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
927 if (new_delay
> dev_priv
->ips
.min_delay
)
928 new_delay
= dev_priv
->ips
.min_delay
;
931 if (ironlake_set_drps(dev
, new_delay
))
932 dev_priv
->ips
.cur_delay
= new_delay
;
934 spin_unlock(&mchdev_lock
);
939 static void notify_ring(struct drm_device
*dev
,
940 struct intel_engine_cs
*ring
)
942 if (!intel_ring_initialized(ring
))
945 trace_i915_gem_request_complete(ring
);
947 wake_up_all(&ring
->irq_queue
);
948 i915_queue_hangcheck(dev
);
951 static u32
vlv_c0_residency(struct drm_i915_private
*dev_priv
,
952 struct intel_rps_ei
*rps_ei
)
954 u32 cz_ts
, cz_freq_khz
;
955 u32 render_count
, media_count
;
956 u32 elapsed_render
, elapsed_media
, elapsed_time
;
959 cz_ts
= vlv_punit_read(dev_priv
, PUNIT_REG_CZ_TIMESTAMP
);
960 cz_freq_khz
= DIV_ROUND_CLOSEST(dev_priv
->mem_freq
* 1000, 4);
962 render_count
= I915_READ(VLV_RENDER_C0_COUNT_REG
);
963 media_count
= I915_READ(VLV_MEDIA_C0_COUNT_REG
);
965 if (rps_ei
->cz_clock
== 0) {
966 rps_ei
->cz_clock
= cz_ts
;
967 rps_ei
->render_c0
= render_count
;
968 rps_ei
->media_c0
= media_count
;
970 return dev_priv
->rps
.cur_freq
;
973 elapsed_time
= cz_ts
- rps_ei
->cz_clock
;
974 rps_ei
->cz_clock
= cz_ts
;
976 elapsed_render
= render_count
- rps_ei
->render_c0
;
977 rps_ei
->render_c0
= render_count
;
979 elapsed_media
= media_count
- rps_ei
->media_c0
;
980 rps_ei
->media_c0
= media_count
;
982 /* Convert all the counters into common unit of milli sec */
983 elapsed_time
/= VLV_CZ_CLOCK_TO_MILLI_SEC
;
984 elapsed_render
/= cz_freq_khz
;
985 elapsed_media
/= cz_freq_khz
;
988 * Calculate overall C0 residency percentage
989 * only if elapsed time is non zero
993 ((max(elapsed_render
, elapsed_media
) * 100)
1001 * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU
1002 * busy-ness calculated from C0 counters of render & media power wells
1003 * @dev_priv: DRM device private
1006 static int vlv_calc_delay_from_C0_counters(struct drm_i915_private
*dev_priv
)
1008 u32 residency_C0_up
= 0, residency_C0_down
= 0;
1011 dev_priv
->rps
.ei_interrupt_count
++;
1013 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
1016 if (dev_priv
->rps
.up_ei
.cz_clock
== 0) {
1017 vlv_c0_residency(dev_priv
, &dev_priv
->rps
.up_ei
);
1018 vlv_c0_residency(dev_priv
, &dev_priv
->rps
.down_ei
);
1019 return dev_priv
->rps
.cur_freq
;
1024 * To down throttle, C0 residency should be less than down threshold
1025 * for continous EI intervals. So calculate down EI counters
1026 * once in VLV_INT_COUNT_FOR_DOWN_EI
1028 if (dev_priv
->rps
.ei_interrupt_count
== VLV_INT_COUNT_FOR_DOWN_EI
) {
1030 dev_priv
->rps
.ei_interrupt_count
= 0;
1032 residency_C0_down
= vlv_c0_residency(dev_priv
,
1033 &dev_priv
->rps
.down_ei
);
1035 residency_C0_up
= vlv_c0_residency(dev_priv
,
1036 &dev_priv
->rps
.up_ei
);
1039 new_delay
= dev_priv
->rps
.cur_freq
;
1041 adj
= dev_priv
->rps
.last_adj
;
1042 /* C0 residency is greater than UP threshold. Increase Frequency */
1043 if (residency_C0_up
>= VLV_RP_UP_EI_THRESHOLD
) {
1049 if (dev_priv
->rps
.cur_freq
< dev_priv
->rps
.max_freq_softlimit
)
1050 new_delay
= dev_priv
->rps
.cur_freq
+ adj
;
1053 * For better performance, jump directly
1054 * to RPe if we're below it.
1056 if (new_delay
< dev_priv
->rps
.efficient_freq
)
1057 new_delay
= dev_priv
->rps
.efficient_freq
;
1059 } else if (!dev_priv
->rps
.ei_interrupt_count
&&
1060 (residency_C0_down
< VLV_RP_DOWN_EI_THRESHOLD
)) {
1066 * This means, C0 residency is less than down threshold over
1067 * a period of VLV_INT_COUNT_FOR_DOWN_EI. So, reduce the freq
1069 if (dev_priv
->rps
.cur_freq
> dev_priv
->rps
.min_freq_softlimit
)
1070 new_delay
= dev_priv
->rps
.cur_freq
+ adj
;
1076 static void gen6_pm_rps_work(struct work_struct
*work
)
1078 struct drm_i915_private
*dev_priv
=
1079 container_of(work
, struct drm_i915_private
, rps
.work
);
1083 spin_lock_irq(&dev_priv
->irq_lock
);
1084 pm_iir
= dev_priv
->rps
.pm_iir
;
1085 dev_priv
->rps
.pm_iir
= 0;
1086 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1087 gen6_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
1088 spin_unlock_irq(&dev_priv
->irq_lock
);
1090 /* Make sure we didn't queue anything we're not going to process. */
1091 WARN_ON(pm_iir
& ~dev_priv
->pm_rps_events
);
1093 if ((pm_iir
& dev_priv
->pm_rps_events
) == 0)
1096 mutex_lock(&dev_priv
->rps
.hw_lock
);
1098 adj
= dev_priv
->rps
.last_adj
;
1099 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
1103 /* CHV needs even encode values */
1104 adj
= IS_CHERRYVIEW(dev_priv
->dev
) ? 2 : 1;
1106 new_delay
= dev_priv
->rps
.cur_freq
+ adj
;
1109 * For better performance, jump directly
1110 * to RPe if we're below it.
1112 if (new_delay
< dev_priv
->rps
.efficient_freq
)
1113 new_delay
= dev_priv
->rps
.efficient_freq
;
1114 } else if (pm_iir
& GEN6_PM_RP_DOWN_TIMEOUT
) {
1115 if (dev_priv
->rps
.cur_freq
> dev_priv
->rps
.efficient_freq
)
1116 new_delay
= dev_priv
->rps
.efficient_freq
;
1118 new_delay
= dev_priv
->rps
.min_freq_softlimit
;
1120 } else if (pm_iir
& GEN6_PM_RP_UP_EI_EXPIRED
) {
1121 new_delay
= vlv_calc_delay_from_C0_counters(dev_priv
);
1122 } else if (pm_iir
& GEN6_PM_RP_DOWN_THRESHOLD
) {
1126 /* CHV needs even encode values */
1127 adj
= IS_CHERRYVIEW(dev_priv
->dev
) ? -2 : -1;
1129 new_delay
= dev_priv
->rps
.cur_freq
+ adj
;
1130 } else { /* unknown event */
1131 new_delay
= dev_priv
->rps
.cur_freq
;
1134 /* sysfs frequency interfaces may have snuck in while servicing the
1137 new_delay
= clamp_t(int, new_delay
,
1138 dev_priv
->rps
.min_freq_softlimit
,
1139 dev_priv
->rps
.max_freq_softlimit
);
1141 dev_priv
->rps
.last_adj
= new_delay
- dev_priv
->rps
.cur_freq
;
1143 if (IS_VALLEYVIEW(dev_priv
->dev
))
1144 valleyview_set_rps(dev_priv
->dev
, new_delay
);
1146 gen6_set_rps(dev_priv
->dev
, new_delay
);
1148 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1153 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1155 * @work: workqueue struct
1157 * Doesn't actually do anything except notify userspace. As a consequence of
1158 * this event, userspace should try to remap the bad rows since statistically
1159 * it is likely the same row is more likely to go bad again.
1161 static void ivybridge_parity_work(struct work_struct
*work
)
1163 struct drm_i915_private
*dev_priv
=
1164 container_of(work
, struct drm_i915_private
, l3_parity
.error_work
);
1165 u32 error_status
, row
, bank
, subbank
;
1166 char *parity_event
[6];
1170 /* We must turn off DOP level clock gating to access the L3 registers.
1171 * In order to prevent a get/put style interface, acquire struct mutex
1172 * any time we access those registers.
1174 mutex_lock(&dev_priv
->dev
->struct_mutex
);
1176 /* If we've screwed up tracking, just let the interrupt fire again */
1177 if (WARN_ON(!dev_priv
->l3_parity
.which_slice
))
1180 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1181 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
1182 POSTING_READ(GEN7_MISCCPCTL
);
1184 while ((slice
= ffs(dev_priv
->l3_parity
.which_slice
)) != 0) {
1188 if (WARN_ON_ONCE(slice
>= NUM_L3_SLICES(dev_priv
->dev
)))
1191 dev_priv
->l3_parity
.which_slice
&= ~(1<<slice
);
1193 reg
= GEN7_L3CDERRST1
+ (slice
* 0x200);
1195 error_status
= I915_READ(reg
);
1196 row
= GEN7_PARITY_ERROR_ROW(error_status
);
1197 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
1198 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
1200 I915_WRITE(reg
, GEN7_PARITY_ERROR_VALID
| GEN7_L3CDERRST1_ENABLE
);
1203 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
1204 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
1205 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
1206 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
1207 parity_event
[4] = kasprintf(GFP_KERNEL
, "SLICE=%d", slice
);
1208 parity_event
[5] = NULL
;
1210 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
->kobj
,
1211 KOBJ_CHANGE
, parity_event
);
1213 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1214 slice
, row
, bank
, subbank
);
1216 kfree(parity_event
[4]);
1217 kfree(parity_event
[3]);
1218 kfree(parity_event
[2]);
1219 kfree(parity_event
[1]);
1222 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
1225 WARN_ON(dev_priv
->l3_parity
.which_slice
);
1226 spin_lock_irq(&dev_priv
->irq_lock
);
1227 gen5_enable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
->dev
));
1228 spin_unlock_irq(&dev_priv
->irq_lock
);
1230 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
1233 static void ivybridge_parity_error_irq_handler(struct drm_device
*dev
, u32 iir
)
1235 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1237 if (!HAS_L3_DPF(dev
))
1240 spin_lock(&dev_priv
->irq_lock
);
1241 gen5_disable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev
));
1242 spin_unlock(&dev_priv
->irq_lock
);
1244 iir
&= GT_PARITY_ERROR(dev
);
1245 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1
)
1246 dev_priv
->l3_parity
.which_slice
|= 1 << 1;
1248 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
1249 dev_priv
->l3_parity
.which_slice
|= 1 << 0;
1251 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
1254 static void ilk_gt_irq_handler(struct drm_device
*dev
,
1255 struct drm_i915_private
*dev_priv
,
1259 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1260 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1261 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
1262 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1265 static void snb_gt_irq_handler(struct drm_device
*dev
,
1266 struct drm_i915_private
*dev_priv
,
1271 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1272 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1273 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
1274 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1275 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
1276 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
1278 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
1279 GT_BSD_CS_ERROR_INTERRUPT
|
1280 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
)) {
1281 i915_handle_error(dev
, false, "GT error interrupt 0x%08x",
1285 if (gt_iir
& GT_PARITY_ERROR(dev
))
1286 ivybridge_parity_error_irq_handler(dev
, gt_iir
);
1289 static void gen8_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1291 if ((pm_iir
& dev_priv
->pm_rps_events
) == 0)
1294 spin_lock(&dev_priv
->irq_lock
);
1295 dev_priv
->rps
.pm_iir
|= pm_iir
& dev_priv
->pm_rps_events
;
1296 gen6_disable_pm_irq(dev_priv
, pm_iir
& dev_priv
->pm_rps_events
);
1297 spin_unlock(&dev_priv
->irq_lock
);
1299 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
1302 static irqreturn_t
gen8_gt_irq_handler(struct drm_device
*dev
,
1303 struct drm_i915_private
*dev_priv
,
1306 struct intel_engine_cs
*ring
;
1309 irqreturn_t ret
= IRQ_NONE
;
1311 if (master_ctl
& (GEN8_GT_RCS_IRQ
| GEN8_GT_BCS_IRQ
)) {
1312 tmp
= I915_READ(GEN8_GT_IIR(0));
1314 I915_WRITE(GEN8_GT_IIR(0), tmp
);
1317 rcs
= tmp
>> GEN8_RCS_IRQ_SHIFT
;
1318 ring
= &dev_priv
->ring
[RCS
];
1319 if (rcs
& GT_RENDER_USER_INTERRUPT
)
1320 notify_ring(dev
, ring
);
1321 if (rcs
& GT_CONTEXT_SWITCH_INTERRUPT
)
1322 intel_execlists_handle_ctx_events(ring
);
1324 bcs
= tmp
>> GEN8_BCS_IRQ_SHIFT
;
1325 ring
= &dev_priv
->ring
[BCS
];
1326 if (bcs
& GT_RENDER_USER_INTERRUPT
)
1327 notify_ring(dev
, ring
);
1328 if (bcs
& GT_CONTEXT_SWITCH_INTERRUPT
)
1329 intel_execlists_handle_ctx_events(ring
);
1331 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1334 if (master_ctl
& (GEN8_GT_VCS1_IRQ
| GEN8_GT_VCS2_IRQ
)) {
1335 tmp
= I915_READ(GEN8_GT_IIR(1));
1337 I915_WRITE(GEN8_GT_IIR(1), tmp
);
1340 vcs
= tmp
>> GEN8_VCS1_IRQ_SHIFT
;
1341 ring
= &dev_priv
->ring
[VCS
];
1342 if (vcs
& GT_RENDER_USER_INTERRUPT
)
1343 notify_ring(dev
, ring
);
1344 if (vcs
& GT_CONTEXT_SWITCH_INTERRUPT
)
1345 intel_execlists_handle_ctx_events(ring
);
1347 vcs
= tmp
>> GEN8_VCS2_IRQ_SHIFT
;
1348 ring
= &dev_priv
->ring
[VCS2
];
1349 if (vcs
& GT_RENDER_USER_INTERRUPT
)
1350 notify_ring(dev
, ring
);
1351 if (vcs
& GT_CONTEXT_SWITCH_INTERRUPT
)
1352 intel_execlists_handle_ctx_events(ring
);
1354 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1357 if (master_ctl
& GEN8_GT_PM_IRQ
) {
1358 tmp
= I915_READ(GEN8_GT_IIR(2));
1359 if (tmp
& dev_priv
->pm_rps_events
) {
1360 I915_WRITE(GEN8_GT_IIR(2),
1361 tmp
& dev_priv
->pm_rps_events
);
1363 gen8_rps_irq_handler(dev_priv
, tmp
);
1365 DRM_ERROR("The master control interrupt lied (PM)!\n");
1368 if (master_ctl
& GEN8_GT_VECS_IRQ
) {
1369 tmp
= I915_READ(GEN8_GT_IIR(3));
1371 I915_WRITE(GEN8_GT_IIR(3), tmp
);
1374 vcs
= tmp
>> GEN8_VECS_IRQ_SHIFT
;
1375 ring
= &dev_priv
->ring
[VECS
];
1376 if (vcs
& GT_RENDER_USER_INTERRUPT
)
1377 notify_ring(dev
, ring
);
1378 if (vcs
& GT_CONTEXT_SWITCH_INTERRUPT
)
1379 intel_execlists_handle_ctx_events(ring
);
1381 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1387 #define HPD_STORM_DETECT_PERIOD 1000
1388 #define HPD_STORM_THRESHOLD 5
1390 static int pch_port_to_hotplug_shift(enum port port
)
1406 static int i915_port_to_hotplug_shift(enum port port
)
1422 static inline enum port
get_port_from_pin(enum hpd_pin pin
)
1432 return PORT_A
; /* no hpd */
1436 static inline void intel_hpd_irq_handler(struct drm_device
*dev
,
1437 u32 hotplug_trigger
,
1438 u32 dig_hotplug_reg
,
1441 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1444 bool storm_detected
= false;
1445 bool queue_dig
= false, queue_hp
= false;
1447 u32 dig_port_mask
= 0;
1449 if (!hotplug_trigger
)
1452 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n",
1453 hotplug_trigger
, dig_hotplug_reg
);
1455 spin_lock(&dev_priv
->irq_lock
);
1456 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
1457 if (!(hpd
[i
] & hotplug_trigger
))
1460 port
= get_port_from_pin(i
);
1461 if (port
&& dev_priv
->hpd_irq_port
[port
]) {
1464 if (HAS_PCH_SPLIT(dev
)) {
1465 dig_shift
= pch_port_to_hotplug_shift(port
);
1466 long_hpd
= (dig_hotplug_reg
>> dig_shift
) & PORTB_HOTPLUG_LONG_DETECT
;
1468 dig_shift
= i915_port_to_hotplug_shift(port
);
1469 long_hpd
= (hotplug_trigger
>> dig_shift
) & PORTB_HOTPLUG_LONG_DETECT
;
1472 DRM_DEBUG_DRIVER("digital hpd port %c - %s\n",
1474 long_hpd
? "long" : "short");
1475 /* for long HPD pulses we want to have the digital queue happen,
1476 but we still want HPD storm detection to function. */
1478 dev_priv
->long_hpd_port_mask
|= (1 << port
);
1479 dig_port_mask
|= hpd
[i
];
1481 /* for short HPD just trigger the digital queue */
1482 dev_priv
->short_hpd_port_mask
|= (1 << port
);
1483 hotplug_trigger
&= ~hpd
[i
];
1489 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
1490 if (hpd
[i
] & hotplug_trigger
&&
1491 dev_priv
->hpd_stats
[i
].hpd_mark
== HPD_DISABLED
) {
1493 * On GMCH platforms the interrupt mask bits only
1494 * prevent irq generation, not the setting of the
1495 * hotplug bits itself. So only WARN about unexpected
1496 * interrupts on saner platforms.
1498 WARN_ONCE(INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
),
1499 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1500 hotplug_trigger
, i
, hpd
[i
]);
1505 if (!(hpd
[i
] & hotplug_trigger
) ||
1506 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
)
1509 if (!(dig_port_mask
& hpd
[i
])) {
1510 dev_priv
->hpd_event_bits
|= (1 << i
);
1514 if (!time_in_range(jiffies
, dev_priv
->hpd_stats
[i
].hpd_last_jiffies
,
1515 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
1516 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD
))) {
1517 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
= jiffies
;
1518 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
1519 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i
);
1520 } else if (dev_priv
->hpd_stats
[i
].hpd_cnt
> HPD_STORM_THRESHOLD
) {
1521 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_MARK_DISABLED
;
1522 dev_priv
->hpd_event_bits
&= ~(1 << i
);
1523 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i
);
1524 storm_detected
= true;
1526 dev_priv
->hpd_stats
[i
].hpd_cnt
++;
1527 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i
,
1528 dev_priv
->hpd_stats
[i
].hpd_cnt
);
1533 dev_priv
->display
.hpd_irq_setup(dev
);
1534 spin_unlock(&dev_priv
->irq_lock
);
1537 * Our hotplug handler can grab modeset locks (by calling down into the
1538 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1539 * queue for otherwise the flush_work in the pageflip code will
1543 queue_work(dev_priv
->dp_wq
, &dev_priv
->dig_port_work
);
1545 schedule_work(&dev_priv
->hotplug_work
);
1548 static void gmbus_irq_handler(struct drm_device
*dev
)
1550 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1552 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1555 static void dp_aux_irq_handler(struct drm_device
*dev
)
1557 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1559 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1562 #if defined(CONFIG_DEBUG_FS)
1563 static void display_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
,
1564 uint32_t crc0
, uint32_t crc1
,
1565 uint32_t crc2
, uint32_t crc3
,
1568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1569 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
1570 struct intel_pipe_crc_entry
*entry
;
1573 spin_lock(&pipe_crc
->lock
);
1575 if (!pipe_crc
->entries
) {
1576 spin_unlock(&pipe_crc
->lock
);
1577 DRM_ERROR("spurious interrupt\n");
1581 head
= pipe_crc
->head
;
1582 tail
= pipe_crc
->tail
;
1584 if (CIRC_SPACE(head
, tail
, INTEL_PIPE_CRC_ENTRIES_NR
) < 1) {
1585 spin_unlock(&pipe_crc
->lock
);
1586 DRM_ERROR("CRC buffer overflowing\n");
1590 entry
= &pipe_crc
->entries
[head
];
1592 entry
->frame
= dev
->driver
->get_vblank_counter(dev
, pipe
);
1593 entry
->crc
[0] = crc0
;
1594 entry
->crc
[1] = crc1
;
1595 entry
->crc
[2] = crc2
;
1596 entry
->crc
[3] = crc3
;
1597 entry
->crc
[4] = crc4
;
1599 head
= (head
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
1600 pipe_crc
->head
= head
;
1602 spin_unlock(&pipe_crc
->lock
);
1604 wake_up_interruptible(&pipe_crc
->wq
);
1608 display_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
,
1609 uint32_t crc0
, uint32_t crc1
,
1610 uint32_t crc2
, uint32_t crc3
,
1615 static void hsw_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1619 display_pipe_crc_irq_handler(dev
, pipe
,
1620 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1624 static void ivb_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1626 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1628 display_pipe_crc_irq_handler(dev
, pipe
,
1629 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1630 I915_READ(PIPE_CRC_RES_2_IVB(pipe
)),
1631 I915_READ(PIPE_CRC_RES_3_IVB(pipe
)),
1632 I915_READ(PIPE_CRC_RES_4_IVB(pipe
)),
1633 I915_READ(PIPE_CRC_RES_5_IVB(pipe
)));
1636 static void i9xx_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1638 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1639 uint32_t res1
, res2
;
1641 if (INTEL_INFO(dev
)->gen
>= 3)
1642 res1
= I915_READ(PIPE_CRC_RES_RES1_I915(pipe
));
1646 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
1647 res2
= I915_READ(PIPE_CRC_RES_RES2_G4X(pipe
));
1651 display_pipe_crc_irq_handler(dev
, pipe
,
1652 I915_READ(PIPE_CRC_RES_RED(pipe
)),
1653 I915_READ(PIPE_CRC_RES_GREEN(pipe
)),
1654 I915_READ(PIPE_CRC_RES_BLUE(pipe
)),
1658 /* The RPS events need forcewake, so we add them to a work queue and mask their
1659 * IMR bits until the work is done. Other interrupts can be processed without
1660 * the work queue. */
1661 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1663 if (pm_iir
& dev_priv
->pm_rps_events
) {
1664 spin_lock(&dev_priv
->irq_lock
);
1665 dev_priv
->rps
.pm_iir
|= pm_iir
& dev_priv
->pm_rps_events
;
1666 gen6_disable_pm_irq(dev_priv
, pm_iir
& dev_priv
->pm_rps_events
);
1667 spin_unlock(&dev_priv
->irq_lock
);
1669 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
1672 if (HAS_VEBOX(dev_priv
->dev
)) {
1673 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1674 notify_ring(dev_priv
->dev
, &dev_priv
->ring
[VECS
]);
1676 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
) {
1677 i915_handle_error(dev_priv
->dev
, false,
1678 "VEBOX CS error interrupt 0x%08x",
1684 static bool intel_pipe_handle_vblank(struct drm_device
*dev
, enum pipe pipe
)
1686 if (!drm_handle_vblank(dev
, pipe
))
1692 static void valleyview_pipestat_irq_handler(struct drm_device
*dev
, u32 iir
)
1694 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1695 u32 pipe_stats
[I915_MAX_PIPES
] = { };
1698 spin_lock(&dev_priv
->irq_lock
);
1699 for_each_pipe(dev_priv
, pipe
) {
1701 u32 mask
, iir_bit
= 0;
1704 * PIPESTAT bits get signalled even when the interrupt is
1705 * disabled with the mask bits, and some of the status bits do
1706 * not generate interrupts at all (like the underrun bit). Hence
1707 * we need to be careful that we only handle what we want to
1711 /* fifo underruns are filterered in the underrun handler. */
1712 mask
= PIPE_FIFO_UNDERRUN_STATUS
;
1716 iir_bit
= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
;
1719 iir_bit
= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
1722 iir_bit
= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
1726 mask
|= dev_priv
->pipestat_irq_mask
[pipe
];
1731 reg
= PIPESTAT(pipe
);
1732 mask
|= PIPESTAT_INT_ENABLE_MASK
;
1733 pipe_stats
[pipe
] = I915_READ(reg
) & mask
;
1736 * Clear the PIPE*STAT regs before the IIR
1738 if (pipe_stats
[pipe
] & (PIPE_FIFO_UNDERRUN_STATUS
|
1739 PIPESTAT_INT_STATUS_MASK
))
1740 I915_WRITE(reg
, pipe_stats
[pipe
]);
1742 spin_unlock(&dev_priv
->irq_lock
);
1744 for_each_pipe(dev_priv
, pipe
) {
1745 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
1746 intel_pipe_handle_vblank(dev
, pipe
))
1747 intel_check_page_flip(dev
, pipe
);
1749 if (pipe_stats
[pipe
] & PLANE_FLIP_DONE_INT_STATUS_VLV
) {
1750 intel_prepare_page_flip(dev
, pipe
);
1751 intel_finish_page_flip(dev
, pipe
);
1754 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
1755 i9xx_pipe_crc_irq_handler(dev
, pipe
);
1757 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1758 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
1761 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1762 gmbus_irq_handler(dev
);
1765 static void i9xx_hpd_irq_handler(struct drm_device
*dev
)
1767 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1768 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1770 if (hotplug_status
) {
1771 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1773 * Make sure hotplug status is cleared before we clear IIR, or else we
1774 * may miss hotplug events.
1776 POSTING_READ(PORT_HOTPLUG_STAT
);
1779 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_G4X
;
1781 intel_hpd_irq_handler(dev
, hotplug_trigger
, 0, hpd_status_g4x
);
1783 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1785 intel_hpd_irq_handler(dev
, hotplug_trigger
, 0, hpd_status_i915
);
1788 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) &&
1789 hotplug_status
& DP_AUX_CHANNEL_MASK_INT_STATUS_G4X
)
1790 dp_aux_irq_handler(dev
);
1794 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1796 struct drm_device
*dev
= arg
;
1797 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1798 u32 iir
, gt_iir
, pm_iir
;
1799 irqreturn_t ret
= IRQ_NONE
;
1802 /* Find, clear, then process each source of interrupt */
1804 gt_iir
= I915_READ(GTIIR
);
1806 I915_WRITE(GTIIR
, gt_iir
);
1808 pm_iir
= I915_READ(GEN6_PMIIR
);
1810 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1812 iir
= I915_READ(VLV_IIR
);
1814 /* Consume port before clearing IIR or we'll miss events */
1815 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1816 i9xx_hpd_irq_handler(dev
);
1817 I915_WRITE(VLV_IIR
, iir
);
1820 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1826 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1828 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1829 /* Call regardless, as some status bits might not be
1830 * signalled in iir */
1831 valleyview_pipestat_irq_handler(dev
, iir
);
1838 static irqreturn_t
cherryview_irq_handler(int irq
, void *arg
)
1840 struct drm_device
*dev
= arg
;
1841 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1842 u32 master_ctl
, iir
;
1843 irqreturn_t ret
= IRQ_NONE
;
1846 master_ctl
= I915_READ(GEN8_MASTER_IRQ
) & ~GEN8_MASTER_IRQ_CONTROL
;
1847 iir
= I915_READ(VLV_IIR
);
1849 if (master_ctl
== 0 && iir
== 0)
1854 I915_WRITE(GEN8_MASTER_IRQ
, 0);
1856 /* Find, clear, then process each source of interrupt */
1859 /* Consume port before clearing IIR or we'll miss events */
1860 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1861 i9xx_hpd_irq_handler(dev
);
1862 I915_WRITE(VLV_IIR
, iir
);
1865 gen8_gt_irq_handler(dev
, dev_priv
, master_ctl
);
1867 /* Call regardless, as some status bits might not be
1868 * signalled in iir */
1869 valleyview_pipestat_irq_handler(dev
, iir
);
1871 I915_WRITE(GEN8_MASTER_IRQ
, DE_MASTER_IRQ_CONTROL
);
1872 POSTING_READ(GEN8_MASTER_IRQ
);
1878 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1880 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1882 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1883 u32 dig_hotplug_reg
;
1885 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
1886 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
1888 intel_hpd_irq_handler(dev
, hotplug_trigger
, dig_hotplug_reg
, hpd_ibx
);
1890 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1891 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1892 SDE_AUDIO_POWER_SHIFT
);
1893 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1897 if (pch_iir
& SDE_AUX_MASK
)
1898 dp_aux_irq_handler(dev
);
1900 if (pch_iir
& SDE_GMBUS
)
1901 gmbus_irq_handler(dev
);
1903 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1904 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1906 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1907 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1909 if (pch_iir
& SDE_POISON
)
1910 DRM_ERROR("PCH poison interrupt\n");
1912 if (pch_iir
& SDE_FDI_MASK
)
1913 for_each_pipe(dev_priv
, pipe
)
1914 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1916 I915_READ(FDI_RX_IIR(pipe
)));
1918 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1919 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1921 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1922 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1924 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1925 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_A
);
1927 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1928 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_B
);
1931 static void ivb_err_int_handler(struct drm_device
*dev
)
1933 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1934 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1937 if (err_int
& ERR_INT_POISON
)
1938 DRM_ERROR("Poison interrupt\n");
1940 for_each_pipe(dev_priv
, pipe
) {
1941 if (err_int
& ERR_INT_FIFO_UNDERRUN(pipe
))
1942 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
1944 if (err_int
& ERR_INT_PIPE_CRC_DONE(pipe
)) {
1945 if (IS_IVYBRIDGE(dev
))
1946 ivb_pipe_crc_irq_handler(dev
, pipe
);
1948 hsw_pipe_crc_irq_handler(dev
, pipe
);
1952 I915_WRITE(GEN7_ERR_INT
, err_int
);
1955 static void cpt_serr_int_handler(struct drm_device
*dev
)
1957 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1958 u32 serr_int
= I915_READ(SERR_INT
);
1960 if (serr_int
& SERR_INT_POISON
)
1961 DRM_ERROR("PCH poison interrupt\n");
1963 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
1964 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_A
);
1966 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
1967 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_B
);
1969 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
1970 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_C
);
1972 I915_WRITE(SERR_INT
, serr_int
);
1975 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1977 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1979 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
1980 u32 dig_hotplug_reg
;
1982 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
1983 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
1985 intel_hpd_irq_handler(dev
, hotplug_trigger
, dig_hotplug_reg
, hpd_cpt
);
1987 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
1988 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
1989 SDE_AUDIO_POWER_SHIFT_CPT
);
1990 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1994 if (pch_iir
& SDE_AUX_MASK_CPT
)
1995 dp_aux_irq_handler(dev
);
1997 if (pch_iir
& SDE_GMBUS_CPT
)
1998 gmbus_irq_handler(dev
);
2000 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
2001 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2003 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
2004 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2006 if (pch_iir
& SDE_FDI_MASK_CPT
)
2007 for_each_pipe(dev_priv
, pipe
)
2008 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2010 I915_READ(FDI_RX_IIR(pipe
)));
2012 if (pch_iir
& SDE_ERROR_CPT
)
2013 cpt_serr_int_handler(dev
);
2016 static void ilk_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
2018 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2021 if (de_iir
& DE_AUX_CHANNEL_A
)
2022 dp_aux_irq_handler(dev
);
2024 if (de_iir
& DE_GSE
)
2025 intel_opregion_asle_intr(dev
);
2027 if (de_iir
& DE_POISON
)
2028 DRM_ERROR("Poison interrupt\n");
2030 for_each_pipe(dev_priv
, pipe
) {
2031 if (de_iir
& DE_PIPE_VBLANK(pipe
) &&
2032 intel_pipe_handle_vblank(dev
, pipe
))
2033 intel_check_page_flip(dev
, pipe
);
2035 if (de_iir
& DE_PIPE_FIFO_UNDERRUN(pipe
))
2036 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2038 if (de_iir
& DE_PIPE_CRC_DONE(pipe
))
2039 i9xx_pipe_crc_irq_handler(dev
, pipe
);
2041 /* plane/pipes map 1:1 on ilk+ */
2042 if (de_iir
& DE_PLANE_FLIP_DONE(pipe
)) {
2043 intel_prepare_page_flip(dev
, pipe
);
2044 intel_finish_page_flip_plane(dev
, pipe
);
2048 /* check event from PCH */
2049 if (de_iir
& DE_PCH_EVENT
) {
2050 u32 pch_iir
= I915_READ(SDEIIR
);
2052 if (HAS_PCH_CPT(dev
))
2053 cpt_irq_handler(dev
, pch_iir
);
2055 ibx_irq_handler(dev
, pch_iir
);
2057 /* should clear PCH hotplug event before clear CPU irq */
2058 I915_WRITE(SDEIIR
, pch_iir
);
2061 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
2062 ironlake_rps_change_irq_handler(dev
);
2065 static void ivb_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
2067 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2070 if (de_iir
& DE_ERR_INT_IVB
)
2071 ivb_err_int_handler(dev
);
2073 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
2074 dp_aux_irq_handler(dev
);
2076 if (de_iir
& DE_GSE_IVB
)
2077 intel_opregion_asle_intr(dev
);
2079 for_each_pipe(dev_priv
, pipe
) {
2080 if (de_iir
& (DE_PIPE_VBLANK_IVB(pipe
)) &&
2081 intel_pipe_handle_vblank(dev
, pipe
))
2082 intel_check_page_flip(dev
, pipe
);
2084 /* plane/pipes map 1:1 on ilk+ */
2085 if (de_iir
& DE_PLANE_FLIP_DONE_IVB(pipe
)) {
2086 intel_prepare_page_flip(dev
, pipe
);
2087 intel_finish_page_flip_plane(dev
, pipe
);
2091 /* check event from PCH */
2092 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
2093 u32 pch_iir
= I915_READ(SDEIIR
);
2095 cpt_irq_handler(dev
, pch_iir
);
2097 /* clear PCH hotplug event before clear CPU irq */
2098 I915_WRITE(SDEIIR
, pch_iir
);
2103 * To handle irqs with the minimum potential races with fresh interrupts, we:
2104 * 1 - Disable Master Interrupt Control.
2105 * 2 - Find the source(s) of the interrupt.
2106 * 3 - Clear the Interrupt Identity bits (IIR).
2107 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2108 * 5 - Re-enable Master Interrupt Control.
2110 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
2112 struct drm_device
*dev
= arg
;
2113 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2114 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
2115 irqreturn_t ret
= IRQ_NONE
;
2117 /* We get interrupts on unclaimed registers, so check for this before we
2118 * do any I915_{READ,WRITE}. */
2119 intel_uncore_check_errors(dev
);
2121 /* disable master interrupt before clearing iir */
2122 de_ier
= I915_READ(DEIER
);
2123 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
2124 POSTING_READ(DEIER
);
2126 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2127 * interrupts will will be stored on its back queue, and then we'll be
2128 * able to process them after we restore SDEIER (as soon as we restore
2129 * it, we'll get an interrupt if SDEIIR still has something to process
2130 * due to its back queue). */
2131 if (!HAS_PCH_NOP(dev
)) {
2132 sde_ier
= I915_READ(SDEIER
);
2133 I915_WRITE(SDEIER
, 0);
2134 POSTING_READ(SDEIER
);
2137 /* Find, clear, then process each source of interrupt */
2139 gt_iir
= I915_READ(GTIIR
);
2141 I915_WRITE(GTIIR
, gt_iir
);
2143 if (INTEL_INFO(dev
)->gen
>= 6)
2144 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
2146 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
2149 de_iir
= I915_READ(DEIIR
);
2151 I915_WRITE(DEIIR
, de_iir
);
2153 if (INTEL_INFO(dev
)->gen
>= 7)
2154 ivb_display_irq_handler(dev
, de_iir
);
2156 ilk_display_irq_handler(dev
, de_iir
);
2159 if (INTEL_INFO(dev
)->gen
>= 6) {
2160 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
2162 I915_WRITE(GEN6_PMIIR
, pm_iir
);
2164 gen6_rps_irq_handler(dev_priv
, pm_iir
);
2168 I915_WRITE(DEIER
, de_ier
);
2169 POSTING_READ(DEIER
);
2170 if (!HAS_PCH_NOP(dev
)) {
2171 I915_WRITE(SDEIER
, sde_ier
);
2172 POSTING_READ(SDEIER
);
2178 static irqreturn_t
gen8_irq_handler(int irq
, void *arg
)
2180 struct drm_device
*dev
= arg
;
2181 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2183 irqreturn_t ret
= IRQ_NONE
;
2187 master_ctl
= I915_READ(GEN8_MASTER_IRQ
);
2188 master_ctl
&= ~GEN8_MASTER_IRQ_CONTROL
;
2192 I915_WRITE(GEN8_MASTER_IRQ
, 0);
2193 POSTING_READ(GEN8_MASTER_IRQ
);
2195 /* Find, clear, then process each source of interrupt */
2197 ret
= gen8_gt_irq_handler(dev
, dev_priv
, master_ctl
);
2199 if (master_ctl
& GEN8_DE_MISC_IRQ
) {
2200 tmp
= I915_READ(GEN8_DE_MISC_IIR
);
2202 I915_WRITE(GEN8_DE_MISC_IIR
, tmp
);
2204 if (tmp
& GEN8_DE_MISC_GSE
)
2205 intel_opregion_asle_intr(dev
);
2207 DRM_ERROR("Unexpected DE Misc interrupt\n");
2210 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2213 if (master_ctl
& GEN8_DE_PORT_IRQ
) {
2214 tmp
= I915_READ(GEN8_DE_PORT_IIR
);
2216 I915_WRITE(GEN8_DE_PORT_IIR
, tmp
);
2218 if (tmp
& GEN8_AUX_CHANNEL_A
)
2219 dp_aux_irq_handler(dev
);
2221 DRM_ERROR("Unexpected DE Port interrupt\n");
2224 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2227 for_each_pipe(dev_priv
, pipe
) {
2228 uint32_t pipe_iir
, flip_done
= 0, fault_errors
= 0;
2230 if (!(master_ctl
& GEN8_DE_PIPE_IRQ(pipe
)))
2233 pipe_iir
= I915_READ(GEN8_DE_PIPE_IIR(pipe
));
2236 I915_WRITE(GEN8_DE_PIPE_IIR(pipe
), pipe_iir
);
2238 if (pipe_iir
& GEN8_PIPE_VBLANK
&&
2239 intel_pipe_handle_vblank(dev
, pipe
))
2240 intel_check_page_flip(dev
, pipe
);
2243 flip_done
= pipe_iir
& GEN9_PIPE_PLANE1_FLIP_DONE
;
2245 flip_done
= pipe_iir
& GEN8_PIPE_PRIMARY_FLIP_DONE
;
2248 intel_prepare_page_flip(dev
, pipe
);
2249 intel_finish_page_flip_plane(dev
, pipe
);
2252 if (pipe_iir
& GEN8_PIPE_CDCLK_CRC_DONE
)
2253 hsw_pipe_crc_irq_handler(dev
, pipe
);
2255 if (pipe_iir
& GEN8_PIPE_FIFO_UNDERRUN
)
2256 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
2261 fault_errors
= pipe_iir
& GEN9_DE_PIPE_IRQ_FAULT_ERRORS
;
2263 fault_errors
= pipe_iir
& GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
2266 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2268 pipe_iir
& GEN8_DE_PIPE_IRQ_FAULT_ERRORS
);
2270 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2273 if (!HAS_PCH_NOP(dev
) && master_ctl
& GEN8_DE_PCH_IRQ
) {
2275 * FIXME(BDW): Assume for now that the new interrupt handling
2276 * scheme also closed the SDE interrupt handling race we've seen
2277 * on older pch-split platforms. But this needs testing.
2279 u32 pch_iir
= I915_READ(SDEIIR
);
2281 I915_WRITE(SDEIIR
, pch_iir
);
2283 cpt_irq_handler(dev
, pch_iir
);
2285 DRM_ERROR("The master control interrupt lied (SDE)!\n");
2289 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
2290 POSTING_READ(GEN8_MASTER_IRQ
);
2295 static void i915_error_wake_up(struct drm_i915_private
*dev_priv
,
2296 bool reset_completed
)
2298 struct intel_engine_cs
*ring
;
2302 * Notify all waiters for GPU completion events that reset state has
2303 * been changed, and that they need to restart their wait after
2304 * checking for potential errors (and bail out to drop locks if there is
2305 * a gpu reset pending so that i915_error_work_func can acquire them).
2308 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2309 for_each_ring(ring
, dev_priv
, i
)
2310 wake_up_all(&ring
->irq_queue
);
2312 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2313 wake_up_all(&dev_priv
->pending_flip_queue
);
2316 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2317 * reset state is cleared.
2319 if (reset_completed
)
2320 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
2324 * i915_error_work_func - do process context error handling work
2325 * @work: work struct
2327 * Fire an error uevent so userspace can see that a hang or error
2330 static void i915_error_work_func(struct work_struct
*work
)
2332 struct i915_gpu_error
*error
= container_of(work
, struct i915_gpu_error
,
2334 struct drm_i915_private
*dev_priv
=
2335 container_of(error
, struct drm_i915_private
, gpu_error
);
2336 struct drm_device
*dev
= dev_priv
->dev
;
2337 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
2338 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
2339 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
2342 kobject_uevent_env(&dev
->primary
->kdev
->kobj
, KOBJ_CHANGE
, error_event
);
2345 * Note that there's only one work item which does gpu resets, so we
2346 * need not worry about concurrent gpu resets potentially incrementing
2347 * error->reset_counter twice. We only need to take care of another
2348 * racing irq/hangcheck declaring the gpu dead for a second time. A
2349 * quick check for that is good enough: schedule_work ensures the
2350 * correct ordering between hang detection and this work item, and since
2351 * the reset in-progress bit is only ever set by code outside of this
2352 * work we don't need to worry about any other races.
2354 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
2355 DRM_DEBUG_DRIVER("resetting chip\n");
2356 kobject_uevent_env(&dev
->primary
->kdev
->kobj
, KOBJ_CHANGE
,
2360 * In most cases it's guaranteed that we get here with an RPM
2361 * reference held, for example because there is a pending GPU
2362 * request that won't finish until the reset is done. This
2363 * isn't the case at least when we get here by doing a
2364 * simulated reset via debugs, so get an RPM reference.
2366 intel_runtime_pm_get(dev_priv
);
2368 * All state reset _must_ be completed before we update the
2369 * reset counter, for otherwise waiters might miss the reset
2370 * pending state and not properly drop locks, resulting in
2371 * deadlocks with the reset work.
2373 ret
= i915_reset(dev
);
2375 intel_display_handle_reset(dev
);
2377 intel_runtime_pm_put(dev_priv
);
2381 * After all the gem state is reset, increment the reset
2382 * counter and wake up everyone waiting for the reset to
2385 * Since unlock operations are a one-sided barrier only,
2386 * we need to insert a barrier here to order any seqno
2388 * the counter increment.
2390 smp_mb__before_atomic();
2391 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
2393 kobject_uevent_env(&dev
->primary
->kdev
->kobj
,
2394 KOBJ_CHANGE
, reset_done_event
);
2396 atomic_set_mask(I915_WEDGED
, &error
->reset_counter
);
2400 * Note: The wake_up also serves as a memory barrier so that
2401 * waiters see the update value of the reset counter atomic_t.
2403 i915_error_wake_up(dev_priv
, true);
2407 static void i915_report_and_clear_eir(struct drm_device
*dev
)
2409 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2410 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
2411 u32 eir
= I915_READ(EIR
);
2417 pr_err("render error detected, EIR: 0x%08x\n", eir
);
2419 i915_get_extra_instdone(dev
, instdone
);
2422 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
2423 u32 ipeir
= I915_READ(IPEIR_I965
);
2425 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2426 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2427 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2428 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2429 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2430 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2431 I915_WRITE(IPEIR_I965
, ipeir
);
2432 POSTING_READ(IPEIR_I965
);
2434 if (eir
& GM45_ERROR_PAGE_TABLE
) {
2435 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2436 pr_err("page table error\n");
2437 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2438 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2439 POSTING_READ(PGTBL_ER
);
2443 if (!IS_GEN2(dev
)) {
2444 if (eir
& I915_ERROR_PAGE_TABLE
) {
2445 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2446 pr_err("page table error\n");
2447 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2448 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2449 POSTING_READ(PGTBL_ER
);
2453 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
2454 pr_err("memory refresh error:\n");
2455 for_each_pipe(dev_priv
, pipe
)
2456 pr_err("pipe %c stat: 0x%08x\n",
2457 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
2458 /* pipestat has already been acked */
2460 if (eir
& I915_ERROR_INSTRUCTION
) {
2461 pr_err("instruction error\n");
2462 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
2463 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2464 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2465 if (INTEL_INFO(dev
)->gen
< 4) {
2466 u32 ipeir
= I915_READ(IPEIR
);
2468 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
2469 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
2470 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
2471 I915_WRITE(IPEIR
, ipeir
);
2472 POSTING_READ(IPEIR
);
2474 u32 ipeir
= I915_READ(IPEIR_I965
);
2476 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2477 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2478 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2479 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2480 I915_WRITE(IPEIR_I965
, ipeir
);
2481 POSTING_READ(IPEIR_I965
);
2485 I915_WRITE(EIR
, eir
);
2487 eir
= I915_READ(EIR
);
2490 * some errors might have become stuck,
2493 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
2494 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
2495 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2500 * i915_handle_error - handle an error interrupt
2503 * Do some basic checking of regsiter state at error interrupt time and
2504 * dump it to the syslog. Also call i915_capture_error_state() to make
2505 * sure we get a record and make it available in debugfs. Fire a uevent
2506 * so userspace knows something bad happened (should trigger collection
2507 * of a ring dump etc.).
2509 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2510 const char *fmt
, ...)
2512 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2516 va_start(args
, fmt
);
2517 vscnprintf(error_msg
, sizeof(error_msg
), fmt
, args
);
2520 i915_capture_error_state(dev
, wedged
, error_msg
);
2521 i915_report_and_clear_eir(dev
);
2524 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
2525 &dev_priv
->gpu_error
.reset_counter
);
2528 * Wakeup waiting processes so that the reset work function
2529 * i915_error_work_func doesn't deadlock trying to grab various
2530 * locks. By bumping the reset counter first, the woken
2531 * processes will see a reset in progress and back off,
2532 * releasing their locks and then wait for the reset completion.
2533 * We must do this for _all_ gpu waiters that might hold locks
2534 * that the reset work needs to acquire.
2536 * Note: The wake_up serves as the required memory barrier to
2537 * ensure that the waiters see the updated value of the reset
2540 i915_error_wake_up(dev_priv
, false);
2544 * Our reset work can grab modeset locks (since it needs to reset the
2545 * state of outstanding pagelips). Hence it must not be run on our own
2546 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2547 * code will deadlock.
2549 schedule_work(&dev_priv
->gpu_error
.work
);
2552 /* Called from drm generic code, passed 'crtc' which
2553 * we use as a pipe index
2555 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
2557 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2558 unsigned long irqflags
;
2560 if (!i915_pipe_enabled(dev
, pipe
))
2563 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2564 if (INTEL_INFO(dev
)->gen
>= 4)
2565 i915_enable_pipestat(dev_priv
, pipe
,
2566 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2568 i915_enable_pipestat(dev_priv
, pipe
,
2569 PIPE_VBLANK_INTERRUPT_STATUS
);
2570 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2575 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
2577 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2578 unsigned long irqflags
;
2579 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2580 DE_PIPE_VBLANK(pipe
);
2582 if (!i915_pipe_enabled(dev
, pipe
))
2585 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2586 ironlake_enable_display_irq(dev_priv
, bit
);
2587 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2592 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
2594 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2595 unsigned long irqflags
;
2597 if (!i915_pipe_enabled(dev
, pipe
))
2600 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2601 i915_enable_pipestat(dev_priv
, pipe
,
2602 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2603 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2608 static int gen8_enable_vblank(struct drm_device
*dev
, int pipe
)
2610 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2611 unsigned long irqflags
;
2613 if (!i915_pipe_enabled(dev
, pipe
))
2616 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2617 dev_priv
->de_irq_mask
[pipe
] &= ~GEN8_PIPE_VBLANK
;
2618 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
2619 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
2620 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2624 /* Called from drm generic code, passed 'crtc' which
2625 * we use as a pipe index
2627 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
2629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2630 unsigned long irqflags
;
2632 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2633 i915_disable_pipestat(dev_priv
, pipe
,
2634 PIPE_VBLANK_INTERRUPT_STATUS
|
2635 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2636 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2639 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
2641 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2642 unsigned long irqflags
;
2643 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2644 DE_PIPE_VBLANK(pipe
);
2646 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2647 ironlake_disable_display_irq(dev_priv
, bit
);
2648 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2651 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
2653 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2654 unsigned long irqflags
;
2656 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2657 i915_disable_pipestat(dev_priv
, pipe
,
2658 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2659 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2662 static void gen8_disable_vblank(struct drm_device
*dev
, int pipe
)
2664 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2665 unsigned long irqflags
;
2667 if (!i915_pipe_enabled(dev
, pipe
))
2670 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2671 dev_priv
->de_irq_mask
[pipe
] |= GEN8_PIPE_VBLANK
;
2672 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
2673 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
2674 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2678 ring_last_seqno(struct intel_engine_cs
*ring
)
2680 return list_entry(ring
->request_list
.prev
,
2681 struct drm_i915_gem_request
, list
)->seqno
;
2685 ring_idle(struct intel_engine_cs
*ring
, u32 seqno
)
2687 return (list_empty(&ring
->request_list
) ||
2688 i915_seqno_passed(seqno
, ring_last_seqno(ring
)));
2692 ipehr_is_semaphore_wait(struct drm_device
*dev
, u32 ipehr
)
2694 if (INTEL_INFO(dev
)->gen
>= 8) {
2695 return (ipehr
>> 23) == 0x1c;
2697 ipehr
&= ~MI_SEMAPHORE_SYNC_MASK
;
2698 return ipehr
== (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
|
2699 MI_SEMAPHORE_REGISTER
);
2703 static struct intel_engine_cs
*
2704 semaphore_wait_to_signaller_ring(struct intel_engine_cs
*ring
, u32 ipehr
, u64 offset
)
2706 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2707 struct intel_engine_cs
*signaller
;
2710 if (INTEL_INFO(dev_priv
->dev
)->gen
>= 8) {
2711 for_each_ring(signaller
, dev_priv
, i
) {
2712 if (ring
== signaller
)
2715 if (offset
== signaller
->semaphore
.signal_ggtt
[ring
->id
])
2719 u32 sync_bits
= ipehr
& MI_SEMAPHORE_SYNC_MASK
;
2721 for_each_ring(signaller
, dev_priv
, i
) {
2722 if(ring
== signaller
)
2725 if (sync_bits
== signaller
->semaphore
.mbox
.wait
[ring
->id
])
2730 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2731 ring
->id
, ipehr
, offset
);
2736 static struct intel_engine_cs
*
2737 semaphore_waits_for(struct intel_engine_cs
*ring
, u32
*seqno
)
2739 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2740 u32 cmd
, ipehr
, head
;
2744 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
2745 if (!ipehr_is_semaphore_wait(ring
->dev
, ipehr
))
2749 * HEAD is likely pointing to the dword after the actual command,
2750 * so scan backwards until we find the MBOX. But limit it to just 3
2751 * or 4 dwords depending on the semaphore wait command size.
2752 * Note that we don't care about ACTHD here since that might
2753 * point at at batch, and semaphores are always emitted into the
2754 * ringbuffer itself.
2756 head
= I915_READ_HEAD(ring
) & HEAD_ADDR
;
2757 backwards
= (INTEL_INFO(ring
->dev
)->gen
>= 8) ? 5 : 4;
2759 for (i
= backwards
; i
; --i
) {
2761 * Be paranoid and presume the hw has gone off into the wild -
2762 * our ring is smaller than what the hardware (and hence
2763 * HEAD_ADDR) allows. Also handles wrap-around.
2765 head
&= ring
->buffer
->size
- 1;
2767 /* This here seems to blow up */
2768 cmd
= ioread32(ring
->buffer
->virtual_start
+ head
);
2778 *seqno
= ioread32(ring
->buffer
->virtual_start
+ head
+ 4) + 1;
2779 if (INTEL_INFO(ring
->dev
)->gen
>= 8) {
2780 offset
= ioread32(ring
->buffer
->virtual_start
+ head
+ 12);
2782 offset
= ioread32(ring
->buffer
->virtual_start
+ head
+ 8);
2784 return semaphore_wait_to_signaller_ring(ring
, ipehr
, offset
);
2787 static int semaphore_passed(struct intel_engine_cs
*ring
)
2789 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2790 struct intel_engine_cs
*signaller
;
2793 ring
->hangcheck
.deadlock
++;
2795 signaller
= semaphore_waits_for(ring
, &seqno
);
2796 if (signaller
== NULL
)
2799 /* Prevent pathological recursion due to driver bugs */
2800 if (signaller
->hangcheck
.deadlock
>= I915_NUM_RINGS
)
2803 if (i915_seqno_passed(signaller
->get_seqno(signaller
, false), seqno
))
2806 /* cursory check for an unkickable deadlock */
2807 if (I915_READ_CTL(signaller
) & RING_WAIT_SEMAPHORE
&&
2808 semaphore_passed(signaller
) < 0)
2814 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
2816 struct intel_engine_cs
*ring
;
2819 for_each_ring(ring
, dev_priv
, i
)
2820 ring
->hangcheck
.deadlock
= 0;
2823 static enum intel_ring_hangcheck_action
2824 ring_stuck(struct intel_engine_cs
*ring
, u64 acthd
)
2826 struct drm_device
*dev
= ring
->dev
;
2827 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2830 if (acthd
!= ring
->hangcheck
.acthd
) {
2831 if (acthd
> ring
->hangcheck
.max_acthd
) {
2832 ring
->hangcheck
.max_acthd
= acthd
;
2833 return HANGCHECK_ACTIVE
;
2836 return HANGCHECK_ACTIVE_LOOP
;
2840 return HANGCHECK_HUNG
;
2842 /* Is the chip hanging on a WAIT_FOR_EVENT?
2843 * If so we can simply poke the RB_WAIT bit
2844 * and break the hang. This should work on
2845 * all but the second generation chipsets.
2847 tmp
= I915_READ_CTL(ring
);
2848 if (tmp
& RING_WAIT
) {
2849 i915_handle_error(dev
, false,
2850 "Kicking stuck wait on %s",
2852 I915_WRITE_CTL(ring
, tmp
);
2853 return HANGCHECK_KICK
;
2856 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
2857 switch (semaphore_passed(ring
)) {
2859 return HANGCHECK_HUNG
;
2861 i915_handle_error(dev
, false,
2862 "Kicking stuck semaphore on %s",
2864 I915_WRITE_CTL(ring
, tmp
);
2865 return HANGCHECK_KICK
;
2867 return HANGCHECK_WAIT
;
2871 return HANGCHECK_HUNG
;
2875 * This is called when the chip hasn't reported back with completed
2876 * batchbuffers in a long time. We keep track per ring seqno progress and
2877 * if there are no progress, hangcheck score for that ring is increased.
2878 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2879 * we kick the ring. If we see no progress on three subsequent calls
2880 * we assume chip is wedged and try to fix it by resetting the chip.
2882 static void i915_hangcheck_elapsed(unsigned long data
)
2884 struct drm_device
*dev
= (struct drm_device
*)data
;
2885 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2886 struct intel_engine_cs
*ring
;
2888 int busy_count
= 0, rings_hung
= 0;
2889 bool stuck
[I915_NUM_RINGS
] = { 0 };
2894 if (!i915
.enable_hangcheck
)
2897 for_each_ring(ring
, dev_priv
, i
) {
2902 semaphore_clear_deadlocks(dev_priv
);
2904 seqno
= ring
->get_seqno(ring
, false);
2905 acthd
= intel_ring_get_active_head(ring
);
2907 if (ring
->hangcheck
.seqno
== seqno
) {
2908 if (ring_idle(ring
, seqno
)) {
2909 ring
->hangcheck
.action
= HANGCHECK_IDLE
;
2911 if (waitqueue_active(&ring
->irq_queue
)) {
2912 /* Issue a wake-up to catch stuck h/w. */
2913 if (!test_and_set_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
)) {
2914 if (!(dev_priv
->gpu_error
.test_irq_rings
& intel_ring_flag(ring
)))
2915 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2918 DRM_INFO("Fake missed irq on %s\n",
2920 wake_up_all(&ring
->irq_queue
);
2922 /* Safeguard against driver failure */
2923 ring
->hangcheck
.score
+= BUSY
;
2927 /* We always increment the hangcheck score
2928 * if the ring is busy and still processing
2929 * the same request, so that no single request
2930 * can run indefinitely (such as a chain of
2931 * batches). The only time we do not increment
2932 * the hangcheck score on this ring, if this
2933 * ring is in a legitimate wait for another
2934 * ring. In that case the waiting ring is a
2935 * victim and we want to be sure we catch the
2936 * right culprit. Then every time we do kick
2937 * the ring, add a small increment to the
2938 * score so that we can catch a batch that is
2939 * being repeatedly kicked and so responsible
2940 * for stalling the machine.
2942 ring
->hangcheck
.action
= ring_stuck(ring
,
2945 switch (ring
->hangcheck
.action
) {
2946 case HANGCHECK_IDLE
:
2947 case HANGCHECK_WAIT
:
2948 case HANGCHECK_ACTIVE
:
2950 case HANGCHECK_ACTIVE_LOOP
:
2951 ring
->hangcheck
.score
+= BUSY
;
2953 case HANGCHECK_KICK
:
2954 ring
->hangcheck
.score
+= KICK
;
2956 case HANGCHECK_HUNG
:
2957 ring
->hangcheck
.score
+= HUNG
;
2963 ring
->hangcheck
.action
= HANGCHECK_ACTIVE
;
2965 /* Gradually reduce the count so that we catch DoS
2966 * attempts across multiple batches.
2968 if (ring
->hangcheck
.score
> 0)
2969 ring
->hangcheck
.score
--;
2971 ring
->hangcheck
.acthd
= ring
->hangcheck
.max_acthd
= 0;
2974 ring
->hangcheck
.seqno
= seqno
;
2975 ring
->hangcheck
.acthd
= acthd
;
2979 for_each_ring(ring
, dev_priv
, i
) {
2980 if (ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
) {
2981 DRM_INFO("%s on %s\n",
2982 stuck
[i
] ? "stuck" : "no progress",
2989 return i915_handle_error(dev
, true, "Ring hung");
2992 /* Reset timer case chip hangs without another request
2994 i915_queue_hangcheck(dev
);
2997 void i915_queue_hangcheck(struct drm_device
*dev
)
2999 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3000 if (!i915
.enable_hangcheck
)
3003 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
3004 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
3007 static void ibx_irq_reset(struct drm_device
*dev
)
3009 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3011 if (HAS_PCH_NOP(dev
))
3014 GEN5_IRQ_RESET(SDE
);
3016 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
3017 I915_WRITE(SERR_INT
, 0xffffffff);
3021 * SDEIER is also touched by the interrupt handler to work around missed PCH
3022 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3023 * instead we unconditionally enable all PCH interrupt sources here, but then
3024 * only unmask them as needed with SDEIMR.
3026 * This function needs to be called before interrupts are enabled.
3028 static void ibx_irq_pre_postinstall(struct drm_device
*dev
)
3030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3032 if (HAS_PCH_NOP(dev
))
3035 WARN_ON(I915_READ(SDEIER
) != 0);
3036 I915_WRITE(SDEIER
, 0xffffffff);
3037 POSTING_READ(SDEIER
);
3040 static void gen5_gt_irq_reset(struct drm_device
*dev
)
3042 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3045 if (INTEL_INFO(dev
)->gen
>= 6)
3046 GEN5_IRQ_RESET(GEN6_PM
);
3051 static void ironlake_irq_reset(struct drm_device
*dev
)
3053 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3055 I915_WRITE(HWSTAM
, 0xffffffff);
3059 I915_WRITE(GEN7_ERR_INT
, 0xffffffff);
3061 gen5_gt_irq_reset(dev
);
3066 static void vlv_display_irq_reset(struct drm_i915_private
*dev_priv
)
3070 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3071 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3073 for_each_pipe(dev_priv
, pipe
)
3074 I915_WRITE(PIPESTAT(pipe
), 0xffff);
3076 GEN5_IRQ_RESET(VLV_
);
3079 static void valleyview_irq_preinstall(struct drm_device
*dev
)
3081 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3084 I915_WRITE(VLV_IMR
, 0);
3085 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
3086 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
3087 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
3089 gen5_gt_irq_reset(dev
);
3091 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
3093 vlv_display_irq_reset(dev_priv
);
3096 static void gen8_gt_irq_reset(struct drm_i915_private
*dev_priv
)
3098 GEN8_IRQ_RESET_NDX(GT
, 0);
3099 GEN8_IRQ_RESET_NDX(GT
, 1);
3100 GEN8_IRQ_RESET_NDX(GT
, 2);
3101 GEN8_IRQ_RESET_NDX(GT
, 3);
3104 static void gen8_irq_reset(struct drm_device
*dev
)
3106 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3109 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3110 POSTING_READ(GEN8_MASTER_IRQ
);
3112 gen8_gt_irq_reset(dev_priv
);
3114 for_each_pipe(dev_priv
, pipe
)
3115 if (intel_display_power_is_enabled(dev_priv
,
3116 POWER_DOMAIN_PIPE(pipe
)))
3117 GEN8_IRQ_RESET_NDX(DE_PIPE
, pipe
);
3119 GEN5_IRQ_RESET(GEN8_DE_PORT_
);
3120 GEN5_IRQ_RESET(GEN8_DE_MISC_
);
3121 GEN5_IRQ_RESET(GEN8_PCU_
);
3126 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
)
3128 uint32_t extra_ier
= GEN8_PIPE_VBLANK
| GEN8_PIPE_FIFO_UNDERRUN
;
3130 spin_lock_irq(&dev_priv
->irq_lock
);
3131 GEN8_IRQ_INIT_NDX(DE_PIPE
, PIPE_B
, dev_priv
->de_irq_mask
[PIPE_B
],
3132 ~dev_priv
->de_irq_mask
[PIPE_B
] | extra_ier
);
3133 GEN8_IRQ_INIT_NDX(DE_PIPE
, PIPE_C
, dev_priv
->de_irq_mask
[PIPE_C
],
3134 ~dev_priv
->de_irq_mask
[PIPE_C
] | extra_ier
);
3135 spin_unlock_irq(&dev_priv
->irq_lock
);
3138 static void cherryview_irq_preinstall(struct drm_device
*dev
)
3140 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3142 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3143 POSTING_READ(GEN8_MASTER_IRQ
);
3145 gen8_gt_irq_reset(dev_priv
);
3147 GEN5_IRQ_RESET(GEN8_PCU_
);
3149 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK_CHV
);
3151 vlv_display_irq_reset(dev_priv
);
3154 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
3156 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3157 struct intel_encoder
*intel_encoder
;
3158 u32 hotplug_irqs
, hotplug
, enabled_irqs
= 0;
3160 if (HAS_PCH_IBX(dev
)) {
3161 hotplug_irqs
= SDE_HOTPLUG_MASK
;
3162 for_each_intel_encoder(dev
, intel_encoder
)
3163 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
3164 enabled_irqs
|= hpd_ibx
[intel_encoder
->hpd_pin
];
3166 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
3167 for_each_intel_encoder(dev
, intel_encoder
)
3168 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
3169 enabled_irqs
|= hpd_cpt
[intel_encoder
->hpd_pin
];
3172 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
3175 * Enable digital hotplug on the PCH, and configure the DP short pulse
3176 * duration to 2ms (which is the minimum in the Display Port spec)
3178 * This register is the same on all known PCH chips.
3180 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3181 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
3182 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
3183 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
3184 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
3185 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3188 static void ibx_irq_postinstall(struct drm_device
*dev
)
3190 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3193 if (HAS_PCH_NOP(dev
))
3196 if (HAS_PCH_IBX(dev
))
3197 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_POISON
;
3199 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
;
3201 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR
);
3202 I915_WRITE(SDEIMR
, ~mask
);
3205 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
3207 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3208 u32 pm_irqs
, gt_irqs
;
3210 pm_irqs
= gt_irqs
= 0;
3212 dev_priv
->gt_irq_mask
= ~0;
3213 if (HAS_L3_DPF(dev
)) {
3214 /* L3 parity interrupt is always unmasked. */
3215 dev_priv
->gt_irq_mask
= ~GT_PARITY_ERROR(dev
);
3216 gt_irqs
|= GT_PARITY_ERROR(dev
);
3219 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
3221 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
3222 ILK_BSD_USER_INTERRUPT
;
3224 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
3227 GEN5_IRQ_INIT(GT
, dev_priv
->gt_irq_mask
, gt_irqs
);
3229 if (INTEL_INFO(dev
)->gen
>= 6) {
3230 pm_irqs
|= dev_priv
->pm_rps_events
;
3233 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
3235 dev_priv
->pm_irq_mask
= 0xffffffff;
3236 GEN5_IRQ_INIT(GEN6_PM
, dev_priv
->pm_irq_mask
, pm_irqs
);
3240 static int ironlake_irq_postinstall(struct drm_device
*dev
)
3242 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3243 u32 display_mask
, extra_mask
;
3245 if (INTEL_INFO(dev
)->gen
>= 7) {
3246 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
3247 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
3248 DE_PLANEB_FLIP_DONE_IVB
|
3249 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
);
3250 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
3251 DE_PIPEA_VBLANK_IVB
| DE_ERR_INT_IVB
);
3253 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
3254 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
3256 DE_PIPEB_CRC_DONE
| DE_PIPEA_CRC_DONE
|
3258 extra_mask
= DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
|
3259 DE_PIPEB_FIFO_UNDERRUN
| DE_PIPEA_FIFO_UNDERRUN
;
3262 dev_priv
->irq_mask
= ~display_mask
;
3264 I915_WRITE(HWSTAM
, 0xeffe);
3266 ibx_irq_pre_postinstall(dev
);
3268 GEN5_IRQ_INIT(DE
, dev_priv
->irq_mask
, display_mask
| extra_mask
);
3270 gen5_gt_irq_postinstall(dev
);
3272 ibx_irq_postinstall(dev
);
3274 if (IS_IRONLAKE_M(dev
)) {
3275 /* Enable PCU event interrupts
3277 * spinlocking not required here for correctness since interrupt
3278 * setup is guaranteed to run in single-threaded context. But we
3279 * need it to make the assert_spin_locked happy. */
3280 spin_lock_irq(&dev_priv
->irq_lock
);
3281 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
3282 spin_unlock_irq(&dev_priv
->irq_lock
);
3288 static void valleyview_display_irqs_install(struct drm_i915_private
*dev_priv
)
3294 pipestat_mask
= PIPESTAT_INT_STATUS_MASK
|
3295 PIPE_FIFO_UNDERRUN_STATUS
;
3297 for_each_pipe(dev_priv
, pipe
)
3298 I915_WRITE(PIPESTAT(pipe
), pipestat_mask
);
3299 POSTING_READ(PIPESTAT(PIPE_A
));
3301 pipestat_mask
= PLANE_FLIP_DONE_INT_STATUS_VLV
|
3302 PIPE_CRC_DONE_INTERRUPT_STATUS
;
3304 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
3305 for_each_pipe(dev_priv
, pipe
)
3306 i915_enable_pipestat(dev_priv
, pipe
, pipestat_mask
);
3308 iir_mask
= I915_DISPLAY_PORT_INTERRUPT
|
3309 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3310 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
3311 if (IS_CHERRYVIEW(dev_priv
))
3312 iir_mask
|= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
3313 dev_priv
->irq_mask
&= ~iir_mask
;
3315 I915_WRITE(VLV_IIR
, iir_mask
);
3316 I915_WRITE(VLV_IIR
, iir_mask
);
3317 I915_WRITE(VLV_IER
, ~dev_priv
->irq_mask
);
3318 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3319 POSTING_READ(VLV_IMR
);
3322 static void valleyview_display_irqs_uninstall(struct drm_i915_private
*dev_priv
)
3328 iir_mask
= I915_DISPLAY_PORT_INTERRUPT
|
3329 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3330 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
3331 if (IS_CHERRYVIEW(dev_priv
))
3332 iir_mask
|= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
3334 dev_priv
->irq_mask
|= iir_mask
;
3335 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3336 I915_WRITE(VLV_IER
, ~dev_priv
->irq_mask
);
3337 I915_WRITE(VLV_IIR
, iir_mask
);
3338 I915_WRITE(VLV_IIR
, iir_mask
);
3339 POSTING_READ(VLV_IIR
);
3341 pipestat_mask
= PLANE_FLIP_DONE_INT_STATUS_VLV
|
3342 PIPE_CRC_DONE_INTERRUPT_STATUS
;
3344 i915_disable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
3345 for_each_pipe(dev_priv
, pipe
)
3346 i915_disable_pipestat(dev_priv
, pipe
, pipestat_mask
);
3348 pipestat_mask
= PIPESTAT_INT_STATUS_MASK
|
3349 PIPE_FIFO_UNDERRUN_STATUS
;
3351 for_each_pipe(dev_priv
, pipe
)
3352 I915_WRITE(PIPESTAT(pipe
), pipestat_mask
);
3353 POSTING_READ(PIPESTAT(PIPE_A
));
3356 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
)
3358 assert_spin_locked(&dev_priv
->irq_lock
);
3360 if (dev_priv
->display_irqs_enabled
)
3363 dev_priv
->display_irqs_enabled
= true;
3365 if (intel_irqs_enabled(dev_priv
))
3366 valleyview_display_irqs_install(dev_priv
);
3369 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
)
3371 assert_spin_locked(&dev_priv
->irq_lock
);
3373 if (!dev_priv
->display_irqs_enabled
)
3376 dev_priv
->display_irqs_enabled
= false;
3378 if (intel_irqs_enabled(dev_priv
))
3379 valleyview_display_irqs_uninstall(dev_priv
);
3382 static void vlv_display_irq_postinstall(struct drm_i915_private
*dev_priv
)
3384 dev_priv
->irq_mask
= ~0;
3386 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3387 POSTING_READ(PORT_HOTPLUG_EN
);
3389 I915_WRITE(VLV_IIR
, 0xffffffff);
3390 I915_WRITE(VLV_IIR
, 0xffffffff);
3391 I915_WRITE(VLV_IER
, ~dev_priv
->irq_mask
);
3392 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3393 POSTING_READ(VLV_IMR
);
3395 /* Interrupt setup is already guaranteed to be single-threaded, this is
3396 * just to make the assert_spin_locked check happy. */
3397 spin_lock_irq(&dev_priv
->irq_lock
);
3398 if (dev_priv
->display_irqs_enabled
)
3399 valleyview_display_irqs_install(dev_priv
);
3400 spin_unlock_irq(&dev_priv
->irq_lock
);
3403 static int valleyview_irq_postinstall(struct drm_device
*dev
)
3405 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3407 vlv_display_irq_postinstall(dev_priv
);
3409 gen5_gt_irq_postinstall(dev
);
3411 /* ack & enable invalid PTE error interrupts */
3412 #if 0 /* FIXME: add support to irq handler for checking these bits */
3413 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
3414 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
3417 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
3422 static void gen8_gt_irq_postinstall(struct drm_i915_private
*dev_priv
)
3424 /* These are interrupts we'll toggle with the ring mask register */
3425 uint32_t gt_interrupts
[] = {
3426 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3427 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3428 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
|
3429 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
|
3430 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
,
3431 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3432 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3433 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
|
3434 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
,
3436 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
|
3437 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
3440 dev_priv
->pm_irq_mask
= 0xffffffff;
3441 GEN8_IRQ_INIT_NDX(GT
, 0, ~gt_interrupts
[0], gt_interrupts
[0]);
3442 GEN8_IRQ_INIT_NDX(GT
, 1, ~gt_interrupts
[1], gt_interrupts
[1]);
3443 GEN8_IRQ_INIT_NDX(GT
, 2, dev_priv
->pm_irq_mask
, dev_priv
->pm_rps_events
);
3444 GEN8_IRQ_INIT_NDX(GT
, 3, ~gt_interrupts
[3], gt_interrupts
[3]);
3447 static void gen8_de_irq_postinstall(struct drm_i915_private
*dev_priv
)
3449 uint32_t de_pipe_masked
= GEN8_PIPE_CDCLK_CRC_DONE
;
3450 uint32_t de_pipe_enables
;
3453 if (IS_GEN9(dev_priv
))
3454 de_pipe_masked
|= GEN9_PIPE_PLANE1_FLIP_DONE
|
3455 GEN9_DE_PIPE_IRQ_FAULT_ERRORS
;
3457 de_pipe_masked
|= GEN8_PIPE_PRIMARY_FLIP_DONE
|
3458 GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
3460 de_pipe_enables
= de_pipe_masked
| GEN8_PIPE_VBLANK
|
3461 GEN8_PIPE_FIFO_UNDERRUN
;
3463 dev_priv
->de_irq_mask
[PIPE_A
] = ~de_pipe_masked
;
3464 dev_priv
->de_irq_mask
[PIPE_B
] = ~de_pipe_masked
;
3465 dev_priv
->de_irq_mask
[PIPE_C
] = ~de_pipe_masked
;
3467 for_each_pipe(dev_priv
, pipe
)
3468 if (intel_display_power_is_enabled(dev_priv
,
3469 POWER_DOMAIN_PIPE(pipe
)))
3470 GEN8_IRQ_INIT_NDX(DE_PIPE
, pipe
,
3471 dev_priv
->de_irq_mask
[pipe
],
3474 GEN5_IRQ_INIT(GEN8_DE_PORT_
, ~GEN8_AUX_CHANNEL_A
, GEN8_AUX_CHANNEL_A
);
3477 static int gen8_irq_postinstall(struct drm_device
*dev
)
3479 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3481 ibx_irq_pre_postinstall(dev
);
3483 gen8_gt_irq_postinstall(dev_priv
);
3484 gen8_de_irq_postinstall(dev_priv
);
3486 ibx_irq_postinstall(dev
);
3488 I915_WRITE(GEN8_MASTER_IRQ
, DE_MASTER_IRQ_CONTROL
);
3489 POSTING_READ(GEN8_MASTER_IRQ
);
3494 static int cherryview_irq_postinstall(struct drm_device
*dev
)
3496 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3497 u32 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
|
3498 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3499 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3500 I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
3501 u32 pipestat_enable
= PLANE_FLIP_DONE_INT_STATUS_VLV
|
3502 PIPE_CRC_DONE_INTERRUPT_STATUS
;
3506 * Leave vblank interrupts masked initially. enable/disable will
3507 * toggle them based on usage.
3509 dev_priv
->irq_mask
= ~enable_mask
;
3511 for_each_pipe(dev_priv
, pipe
)
3512 I915_WRITE(PIPESTAT(pipe
), 0xffff);
3514 spin_lock_irq(&dev_priv
->irq_lock
);
3515 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
3516 for_each_pipe(dev_priv
, pipe
)
3517 i915_enable_pipestat(dev_priv
, pipe
, pipestat_enable
);
3518 spin_unlock_irq(&dev_priv
->irq_lock
);
3520 I915_WRITE(VLV_IIR
, 0xffffffff);
3521 I915_WRITE(VLV_IIR
, 0xffffffff);
3522 I915_WRITE(VLV_IER
, enable_mask
);
3523 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3524 POSTING_READ(VLV_IMR
);
3526 gen8_gt_irq_postinstall(dev_priv
);
3528 I915_WRITE(GEN8_MASTER_IRQ
, MASTER_INTERRUPT_ENABLE
);
3529 POSTING_READ(GEN8_MASTER_IRQ
);
3534 static void gen8_irq_uninstall(struct drm_device
*dev
)
3536 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3541 gen8_irq_reset(dev
);
3544 static void valleyview_irq_uninstall(struct drm_device
*dev
)
3546 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3551 I915_WRITE(VLV_MASTER_IER
, 0);
3553 gen5_gt_irq_reset(dev
);
3555 I915_WRITE(HWSTAM
, 0xffffffff);
3557 /* Interrupt setup is already guaranteed to be single-threaded, this is
3558 * just to make the assert_spin_locked check happy. */
3559 spin_lock_irq(&dev_priv
->irq_lock
);
3560 if (dev_priv
->display_irqs_enabled
)
3561 valleyview_display_irqs_uninstall(dev_priv
);
3562 spin_unlock_irq(&dev_priv
->irq_lock
);
3564 vlv_display_irq_reset(dev_priv
);
3566 dev_priv
->irq_mask
= 0;
3569 static void cherryview_irq_uninstall(struct drm_device
*dev
)
3571 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3577 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3578 POSTING_READ(GEN8_MASTER_IRQ
);
3580 gen8_gt_irq_reset(dev_priv
);
3582 GEN5_IRQ_RESET(GEN8_PCU_
);
3584 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3585 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3587 for_each_pipe(dev_priv
, pipe
)
3588 I915_WRITE(PIPESTAT(pipe
), 0xffff);
3590 GEN5_IRQ_RESET(VLV_
);
3593 static void ironlake_irq_uninstall(struct drm_device
*dev
)
3595 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3600 ironlake_irq_reset(dev
);
3603 static void i8xx_irq_preinstall(struct drm_device
* dev
)
3605 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3608 for_each_pipe(dev_priv
, pipe
)
3609 I915_WRITE(PIPESTAT(pipe
), 0);
3610 I915_WRITE16(IMR
, 0xffff);
3611 I915_WRITE16(IER
, 0x0);
3612 POSTING_READ16(IER
);
3615 static int i8xx_irq_postinstall(struct drm_device
*dev
)
3617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3620 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3622 /* Unmask the interrupts that we always want on. */
3623 dev_priv
->irq_mask
=
3624 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3625 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3626 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3627 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
3628 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
3629 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
3632 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3633 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3634 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
3635 I915_USER_INTERRUPT
);
3636 POSTING_READ16(IER
);
3638 /* Interrupt setup is already guaranteed to be single-threaded, this is
3639 * just to make the assert_spin_locked check happy. */
3640 spin_lock_irq(&dev_priv
->irq_lock
);
3641 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3642 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3643 spin_unlock_irq(&dev_priv
->irq_lock
);
3649 * Returns true when a page flip has completed.
3651 static bool i8xx_handle_vblank(struct drm_device
*dev
,
3652 int plane
, int pipe
, u32 iir
)
3654 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3655 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3657 if (!intel_pipe_handle_vblank(dev
, pipe
))
3660 if ((iir
& flip_pending
) == 0)
3661 goto check_page_flip
;
3663 intel_prepare_page_flip(dev
, plane
);
3665 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3666 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3667 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3668 * the flip is completed (no longer pending). Since this doesn't raise
3669 * an interrupt per se, we watch for the change at vblank.
3671 if (I915_READ16(ISR
) & flip_pending
)
3672 goto check_page_flip
;
3674 intel_finish_page_flip(dev
, pipe
);
3678 intel_check_page_flip(dev
, pipe
);
3682 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
3684 struct drm_device
*dev
= arg
;
3685 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3690 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3691 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3693 iir
= I915_READ16(IIR
);
3697 while (iir
& ~flip_mask
) {
3698 /* Can't rely on pipestat interrupt bit in iir as it might
3699 * have been cleared after the pipestat interrupt was received.
3700 * It doesn't set the bit in iir again, but it still produces
3701 * interrupts (for non-MSI).
3703 spin_lock(&dev_priv
->irq_lock
);
3704 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3705 i915_handle_error(dev
, false,
3706 "Command parser error, iir 0x%08x",
3709 for_each_pipe(dev_priv
, pipe
) {
3710 int reg
= PIPESTAT(pipe
);
3711 pipe_stats
[pipe
] = I915_READ(reg
);
3714 * Clear the PIPE*STAT regs before the IIR
3716 if (pipe_stats
[pipe
] & 0x8000ffff)
3717 I915_WRITE(reg
, pipe_stats
[pipe
]);
3719 spin_unlock(&dev_priv
->irq_lock
);
3721 I915_WRITE16(IIR
, iir
& ~flip_mask
);
3722 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
3724 i915_update_dri1_breadcrumb(dev
);
3726 if (iir
& I915_USER_INTERRUPT
)
3727 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3729 for_each_pipe(dev_priv
, pipe
) {
3734 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3735 i8xx_handle_vblank(dev
, plane
, pipe
, iir
))
3736 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
3738 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
3739 i9xx_pipe_crc_irq_handler(dev
, pipe
);
3741 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3742 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
3752 static void i8xx_irq_uninstall(struct drm_device
* dev
)
3754 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3757 for_each_pipe(dev_priv
, pipe
) {
3758 /* Clear enable bits; then clear status bits */
3759 I915_WRITE(PIPESTAT(pipe
), 0);
3760 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
3762 I915_WRITE16(IMR
, 0xffff);
3763 I915_WRITE16(IER
, 0x0);
3764 I915_WRITE16(IIR
, I915_READ16(IIR
));
3767 static void i915_irq_preinstall(struct drm_device
* dev
)
3769 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3772 if (I915_HAS_HOTPLUG(dev
)) {
3773 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3774 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3777 I915_WRITE16(HWSTAM
, 0xeffe);
3778 for_each_pipe(dev_priv
, pipe
)
3779 I915_WRITE(PIPESTAT(pipe
), 0);
3780 I915_WRITE(IMR
, 0xffffffff);
3781 I915_WRITE(IER
, 0x0);
3785 static int i915_irq_postinstall(struct drm_device
*dev
)
3787 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3790 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3792 /* Unmask the interrupts that we always want on. */
3793 dev_priv
->irq_mask
=
3794 ~(I915_ASLE_INTERRUPT
|
3795 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3796 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3797 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3798 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
3799 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
3802 I915_ASLE_INTERRUPT
|
3803 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3804 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3805 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
3806 I915_USER_INTERRUPT
;
3808 if (I915_HAS_HOTPLUG(dev
)) {
3809 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3810 POSTING_READ(PORT_HOTPLUG_EN
);
3812 /* Enable in IER... */
3813 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
3814 /* and unmask in IMR */
3815 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
3818 I915_WRITE(IMR
, dev_priv
->irq_mask
);
3819 I915_WRITE(IER
, enable_mask
);
3822 i915_enable_asle_pipestat(dev
);
3824 /* Interrupt setup is already guaranteed to be single-threaded, this is
3825 * just to make the assert_spin_locked check happy. */
3826 spin_lock_irq(&dev_priv
->irq_lock
);
3827 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3828 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3829 spin_unlock_irq(&dev_priv
->irq_lock
);
3835 * Returns true when a page flip has completed.
3837 static bool i915_handle_vblank(struct drm_device
*dev
,
3838 int plane
, int pipe
, u32 iir
)
3840 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3841 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3843 if (!intel_pipe_handle_vblank(dev
, pipe
))
3846 if ((iir
& flip_pending
) == 0)
3847 goto check_page_flip
;
3849 intel_prepare_page_flip(dev
, plane
);
3851 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3852 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3853 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3854 * the flip is completed (no longer pending). Since this doesn't raise
3855 * an interrupt per se, we watch for the change at vblank.
3857 if (I915_READ(ISR
) & flip_pending
)
3858 goto check_page_flip
;
3860 intel_finish_page_flip(dev
, pipe
);
3864 intel_check_page_flip(dev
, pipe
);
3868 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
3870 struct drm_device
*dev
= arg
;
3871 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3872 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
3874 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3875 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3876 int pipe
, ret
= IRQ_NONE
;
3878 iir
= I915_READ(IIR
);
3880 bool irq_received
= (iir
& ~flip_mask
) != 0;
3881 bool blc_event
= false;
3883 /* Can't rely on pipestat interrupt bit in iir as it might
3884 * have been cleared after the pipestat interrupt was received.
3885 * It doesn't set the bit in iir again, but it still produces
3886 * interrupts (for non-MSI).
3888 spin_lock(&dev_priv
->irq_lock
);
3889 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3890 i915_handle_error(dev
, false,
3891 "Command parser error, iir 0x%08x",
3894 for_each_pipe(dev_priv
, pipe
) {
3895 int reg
= PIPESTAT(pipe
);
3896 pipe_stats
[pipe
] = I915_READ(reg
);
3898 /* Clear the PIPE*STAT regs before the IIR */
3899 if (pipe_stats
[pipe
] & 0x8000ffff) {
3900 I915_WRITE(reg
, pipe_stats
[pipe
]);
3901 irq_received
= true;
3904 spin_unlock(&dev_priv
->irq_lock
);
3909 /* Consume port. Then clear IIR or we'll miss events */
3910 if (I915_HAS_HOTPLUG(dev
) &&
3911 iir
& I915_DISPLAY_PORT_INTERRUPT
)
3912 i9xx_hpd_irq_handler(dev
);
3914 I915_WRITE(IIR
, iir
& ~flip_mask
);
3915 new_iir
= I915_READ(IIR
); /* Flush posted writes */
3917 if (iir
& I915_USER_INTERRUPT
)
3918 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3920 for_each_pipe(dev_priv
, pipe
) {
3925 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3926 i915_handle_vblank(dev
, plane
, pipe
, iir
))
3927 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
3929 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
3932 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
3933 i9xx_pipe_crc_irq_handler(dev
, pipe
);
3935 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3936 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
3940 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
3941 intel_opregion_asle_intr(dev
);
3943 /* With MSI, interrupts are only generated when iir
3944 * transitions from zero to nonzero. If another bit got
3945 * set while we were handling the existing iir bits, then
3946 * we would never get another interrupt.
3948 * This is fine on non-MSI as well, as if we hit this path
3949 * we avoid exiting the interrupt handler only to generate
3952 * Note that for MSI this could cause a stray interrupt report
3953 * if an interrupt landed in the time between writing IIR and
3954 * the posting read. This should be rare enough to never
3955 * trigger the 99% of 100,000 interrupts test for disabling
3960 } while (iir
& ~flip_mask
);
3962 i915_update_dri1_breadcrumb(dev
);
3967 static void i915_irq_uninstall(struct drm_device
* dev
)
3969 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3972 if (I915_HAS_HOTPLUG(dev
)) {
3973 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3974 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3977 I915_WRITE16(HWSTAM
, 0xffff);
3978 for_each_pipe(dev_priv
, pipe
) {
3979 /* Clear enable bits; then clear status bits */
3980 I915_WRITE(PIPESTAT(pipe
), 0);
3981 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
3983 I915_WRITE(IMR
, 0xffffffff);
3984 I915_WRITE(IER
, 0x0);
3986 I915_WRITE(IIR
, I915_READ(IIR
));
3989 static void i965_irq_preinstall(struct drm_device
* dev
)
3991 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3994 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3995 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3997 I915_WRITE(HWSTAM
, 0xeffe);
3998 for_each_pipe(dev_priv
, pipe
)
3999 I915_WRITE(PIPESTAT(pipe
), 0);
4000 I915_WRITE(IMR
, 0xffffffff);
4001 I915_WRITE(IER
, 0x0);
4005 static int i965_irq_postinstall(struct drm_device
*dev
)
4007 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4011 /* Unmask the interrupts that we always want on. */
4012 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
4013 I915_DISPLAY_PORT_INTERRUPT
|
4014 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
4015 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
4016 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4017 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
4018 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
4020 enable_mask
= ~dev_priv
->irq_mask
;
4021 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4022 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
4023 enable_mask
|= I915_USER_INTERRUPT
;
4026 enable_mask
|= I915_BSD_USER_INTERRUPT
;
4028 /* Interrupt setup is already guaranteed to be single-threaded, this is
4029 * just to make the assert_spin_locked check happy. */
4030 spin_lock_irq(&dev_priv
->irq_lock
);
4031 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
4032 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4033 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4034 spin_unlock_irq(&dev_priv
->irq_lock
);
4037 * Enable some error detection, note the instruction error mask
4038 * bit is reserved, so we leave it masked.
4041 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
4042 GM45_ERROR_MEM_PRIV
|
4043 GM45_ERROR_CP_PRIV
|
4044 I915_ERROR_MEMORY_REFRESH
);
4046 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
4047 I915_ERROR_MEMORY_REFRESH
);
4049 I915_WRITE(EMR
, error_mask
);
4051 I915_WRITE(IMR
, dev_priv
->irq_mask
);
4052 I915_WRITE(IER
, enable_mask
);
4055 I915_WRITE(PORT_HOTPLUG_EN
, 0);
4056 POSTING_READ(PORT_HOTPLUG_EN
);
4058 i915_enable_asle_pipestat(dev
);
4063 static void i915_hpd_irq_setup(struct drm_device
*dev
)
4065 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4066 struct intel_encoder
*intel_encoder
;
4069 assert_spin_locked(&dev_priv
->irq_lock
);
4071 if (I915_HAS_HOTPLUG(dev
)) {
4072 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
4073 hotplug_en
&= ~HOTPLUG_INT_EN_MASK
;
4074 /* Note HDMI and DP share hotplug bits */
4075 /* enable bits are the same for all generations */
4076 for_each_intel_encoder(dev
, intel_encoder
)
4077 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
4078 hotplug_en
|= hpd_mask_i915
[intel_encoder
->hpd_pin
];
4079 /* Programming the CRT detection parameters tends
4080 to generate a spurious hotplug event about three
4081 seconds later. So just do it once.
4084 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
4085 hotplug_en
&= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
;
4086 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
4088 /* Ignore TV since it's buggy */
4089 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
4093 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
4095 struct drm_device
*dev
= arg
;
4096 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4098 u32 pipe_stats
[I915_MAX_PIPES
];
4099 int ret
= IRQ_NONE
, pipe
;
4101 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4102 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
4104 iir
= I915_READ(IIR
);
4107 bool irq_received
= (iir
& ~flip_mask
) != 0;
4108 bool blc_event
= false;
4110 /* Can't rely on pipestat interrupt bit in iir as it might
4111 * have been cleared after the pipestat interrupt was received.
4112 * It doesn't set the bit in iir again, but it still produces
4113 * interrupts (for non-MSI).
4115 spin_lock(&dev_priv
->irq_lock
);
4116 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
4117 i915_handle_error(dev
, false,
4118 "Command parser error, iir 0x%08x",
4121 for_each_pipe(dev_priv
, pipe
) {
4122 int reg
= PIPESTAT(pipe
);
4123 pipe_stats
[pipe
] = I915_READ(reg
);
4126 * Clear the PIPE*STAT regs before the IIR
4128 if (pipe_stats
[pipe
] & 0x8000ffff) {
4129 I915_WRITE(reg
, pipe_stats
[pipe
]);
4130 irq_received
= true;
4133 spin_unlock(&dev_priv
->irq_lock
);
4140 /* Consume port. Then clear IIR or we'll miss events */
4141 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
4142 i9xx_hpd_irq_handler(dev
);
4144 I915_WRITE(IIR
, iir
& ~flip_mask
);
4145 new_iir
= I915_READ(IIR
); /* Flush posted writes */
4147 if (iir
& I915_USER_INTERRUPT
)
4148 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
4149 if (iir
& I915_BSD_USER_INTERRUPT
)
4150 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
4152 for_each_pipe(dev_priv
, pipe
) {
4153 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
4154 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
4155 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
4157 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
4160 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
4161 i9xx_pipe_crc_irq_handler(dev
, pipe
);
4163 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
4164 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
4167 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
4168 intel_opregion_asle_intr(dev
);
4170 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
4171 gmbus_irq_handler(dev
);
4173 /* With MSI, interrupts are only generated when iir
4174 * transitions from zero to nonzero. If another bit got
4175 * set while we were handling the existing iir bits, then
4176 * we would never get another interrupt.
4178 * This is fine on non-MSI as well, as if we hit this path
4179 * we avoid exiting the interrupt handler only to generate
4182 * Note that for MSI this could cause a stray interrupt report
4183 * if an interrupt landed in the time between writing IIR and
4184 * the posting read. This should be rare enough to never
4185 * trigger the 99% of 100,000 interrupts test for disabling
4191 i915_update_dri1_breadcrumb(dev
);
4196 static void i965_irq_uninstall(struct drm_device
* dev
)
4198 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4204 I915_WRITE(PORT_HOTPLUG_EN
, 0);
4205 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4207 I915_WRITE(HWSTAM
, 0xffffffff);
4208 for_each_pipe(dev_priv
, pipe
)
4209 I915_WRITE(PIPESTAT(pipe
), 0);
4210 I915_WRITE(IMR
, 0xffffffff);
4211 I915_WRITE(IER
, 0x0);
4213 for_each_pipe(dev_priv
, pipe
)
4214 I915_WRITE(PIPESTAT(pipe
),
4215 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
4216 I915_WRITE(IIR
, I915_READ(IIR
));
4219 static void intel_hpd_irq_reenable_work(struct work_struct
*work
)
4221 struct drm_i915_private
*dev_priv
=
4222 container_of(work
, typeof(*dev_priv
),
4223 hotplug_reenable_work
.work
);
4224 struct drm_device
*dev
= dev_priv
->dev
;
4225 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4228 intel_runtime_pm_get(dev_priv
);
4230 spin_lock_irq(&dev_priv
->irq_lock
);
4231 for (i
= (HPD_NONE
+ 1); i
< HPD_NUM_PINS
; i
++) {
4232 struct drm_connector
*connector
;
4234 if (dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_DISABLED
)
4237 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
4239 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
4240 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4242 if (intel_connector
->encoder
->hpd_pin
== i
) {
4243 if (connector
->polled
!= intel_connector
->polled
)
4244 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4246 connector
->polled
= intel_connector
->polled
;
4247 if (!connector
->polled
)
4248 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
4252 if (dev_priv
->display
.hpd_irq_setup
)
4253 dev_priv
->display
.hpd_irq_setup(dev
);
4254 spin_unlock_irq(&dev_priv
->irq_lock
);
4256 intel_runtime_pm_put(dev_priv
);
4260 * intel_irq_init - initializes irq support
4261 * @dev_priv: i915 device instance
4263 * This function initializes all the irq support including work items, timers
4264 * and all the vtables. It does not setup the interrupt itself though.
4266 void intel_irq_init(struct drm_i915_private
*dev_priv
)
4268 struct drm_device
*dev
= dev_priv
->dev
;
4270 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
4271 INIT_WORK(&dev_priv
->dig_port_work
, i915_digport_work_func
);
4272 INIT_WORK(&dev_priv
->gpu_error
.work
, i915_error_work_func
);
4273 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
4274 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
4276 /* Let's track the enabled rps events */
4277 if (IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
4278 /* WaGsvRC0ResidencyMethod:vlv */
4279 dev_priv
->pm_rps_events
= GEN6_PM_RP_UP_EI_EXPIRED
;
4281 dev_priv
->pm_rps_events
= GEN6_PM_RPS_EVENTS
;
4283 setup_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
4284 i915_hangcheck_elapsed
,
4285 (unsigned long) dev
);
4286 INIT_DELAYED_WORK(&dev_priv
->hotplug_reenable_work
,
4287 intel_hpd_irq_reenable_work
);
4289 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
4291 if (IS_GEN2(dev_priv
)) {
4292 dev
->max_vblank_count
= 0;
4293 dev
->driver
->get_vblank_counter
= i8xx_get_vblank_counter
;
4294 } else if (IS_G4X(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 5) {
4295 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
4296 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
4298 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
4299 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
4303 * Opt out of the vblank disable timer on everything except gen2.
4304 * Gen2 doesn't have a hardware frame counter and so depends on
4305 * vblank interrupts to produce sane vblank seuquence numbers.
4307 if (!IS_GEN2(dev_priv
))
4308 dev
->vblank_disable_immediate
= true;
4310 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4311 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
4312 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
4315 if (IS_CHERRYVIEW(dev_priv
)) {
4316 dev
->driver
->irq_handler
= cherryview_irq_handler
;
4317 dev
->driver
->irq_preinstall
= cherryview_irq_preinstall
;
4318 dev
->driver
->irq_postinstall
= cherryview_irq_postinstall
;
4319 dev
->driver
->irq_uninstall
= cherryview_irq_uninstall
;
4320 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
4321 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
4322 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4323 } else if (IS_VALLEYVIEW(dev_priv
)) {
4324 dev
->driver
->irq_handler
= valleyview_irq_handler
;
4325 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
4326 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
4327 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
4328 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
4329 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
4330 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4331 } else if (INTEL_INFO(dev_priv
)->gen
>= 8) {
4332 dev
->driver
->irq_handler
= gen8_irq_handler
;
4333 dev
->driver
->irq_preinstall
= gen8_irq_reset
;
4334 dev
->driver
->irq_postinstall
= gen8_irq_postinstall
;
4335 dev
->driver
->irq_uninstall
= gen8_irq_uninstall
;
4336 dev
->driver
->enable_vblank
= gen8_enable_vblank
;
4337 dev
->driver
->disable_vblank
= gen8_disable_vblank
;
4338 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
4339 } else if (HAS_PCH_SPLIT(dev
)) {
4340 dev
->driver
->irq_handler
= ironlake_irq_handler
;
4341 dev
->driver
->irq_preinstall
= ironlake_irq_reset
;
4342 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
4343 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
4344 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
4345 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
4346 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
4348 if (INTEL_INFO(dev_priv
)->gen
== 2) {
4349 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
4350 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
4351 dev
->driver
->irq_handler
= i8xx_irq_handler
;
4352 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
4353 } else if (INTEL_INFO(dev_priv
)->gen
== 3) {
4354 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
4355 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
4356 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
4357 dev
->driver
->irq_handler
= i915_irq_handler
;
4358 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4360 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
4361 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
4362 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
4363 dev
->driver
->irq_handler
= i965_irq_handler
;
4364 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4366 dev
->driver
->enable_vblank
= i915_enable_vblank
;
4367 dev
->driver
->disable_vblank
= i915_disable_vblank
;
4372 * intel_hpd_init - initializes and enables hpd support
4373 * @dev_priv: i915 device instance
4375 * This function enables the hotplug support. It requires that interrupts have
4376 * already been enabled with intel_irq_init_hw(). From this point on hotplug and
4377 * poll request can run concurrently to other code, so locking rules must be
4380 * This is a separate step from interrupt enabling to simplify the locking rules
4381 * in the driver load and resume code.
4383 void intel_hpd_init(struct drm_i915_private
*dev_priv
)
4385 struct drm_device
*dev
= dev_priv
->dev
;
4386 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4387 struct drm_connector
*connector
;
4390 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
4391 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
4392 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
4394 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
4395 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4396 connector
->polled
= intel_connector
->polled
;
4397 if (connector
->encoder
&& !connector
->polled
&& I915_HAS_HOTPLUG(dev
) && intel_connector
->encoder
->hpd_pin
> HPD_NONE
)
4398 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
4399 if (intel_connector
->mst_port
)
4400 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
4403 /* Interrupt setup is already guaranteed to be single-threaded, this is
4404 * just to make the assert_spin_locked checks happy. */
4405 spin_lock_irq(&dev_priv
->irq_lock
);
4406 if (dev_priv
->display
.hpd_irq_setup
)
4407 dev_priv
->display
.hpd_irq_setup(dev
);
4408 spin_unlock_irq(&dev_priv
->irq_lock
);
4412 * intel_irq_install - enables the hardware interrupt
4413 * @dev_priv: i915 device instance
4415 * This function enables the hardware interrupt handling, but leaves the hotplug
4416 * handling still disabled. It is called after intel_irq_init().
4418 * In the driver load and resume code we need working interrupts in a few places
4419 * but don't want to deal with the hassle of concurrent probe and hotplug
4420 * workers. Hence the split into this two-stage approach.
4422 int intel_irq_install(struct drm_i915_private
*dev_priv
)
4425 * We enable some interrupt sources in our postinstall hooks, so mark
4426 * interrupts as enabled _before_ actually enabling them to avoid
4427 * special cases in our ordering checks.
4429 dev_priv
->pm
.irqs_enabled
= true;
4431 return drm_irq_install(dev_priv
->dev
, dev_priv
->dev
->pdev
->irq
);
4435 * intel_irq_uninstall - finilizes all irq handling
4436 * @dev_priv: i915 device instance
4438 * This stops interrupt and hotplug handling and unregisters and frees all
4439 * resources acquired in the init functions.
4441 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
)
4443 drm_irq_uninstall(dev_priv
->dev
);
4444 intel_hpd_cancel_work(dev_priv
);
4445 dev_priv
->pm
.irqs_enabled
= false;
4449 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4450 * @dev_priv: i915 device instance
4452 * This function is used to disable interrupts at runtime, both in the runtime
4453 * pm and the system suspend/resume code.
4455 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
)
4457 dev_priv
->dev
->driver
->irq_uninstall(dev_priv
->dev
);
4458 dev_priv
->pm
.irqs_enabled
= false;
4462 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4463 * @dev_priv: i915 device instance
4465 * This function is used to enable interrupts at runtime, both in the runtime
4466 * pm and the system suspend/resume code.
4468 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
)
4470 dev_priv
->pm
.irqs_enabled
= true;
4471 dev_priv
->dev
->driver
->irq_preinstall(dev_priv
->dev
);
4472 dev_priv
->dev
->driver
->irq_postinstall(dev_priv
->dev
);