1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
34 #include <drm/i915_drm.h>
36 #include "i915_trace.h"
37 #include "intel_drv.h"
39 static const u32 hpd_ibx
[] = {
40 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
41 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
42 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
43 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
44 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
47 static const u32 hpd_cpt
[] = {
48 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
49 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
50 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
51 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
52 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
55 static const u32 hpd_mask_i915
[] = {
56 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
57 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
58 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
59 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
60 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
61 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
64 static const u32 hpd_status_gen4
[] = {
65 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
66 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
67 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
68 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
69 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
70 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
73 static const u32 hpd_status_i915
[] = { /* i915 and valleyview are the same */
74 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
75 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
76 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
77 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
78 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
79 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
82 /* For display hotplug interrupt */
84 ironlake_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
86 assert_spin_locked(&dev_priv
->irq_lock
);
88 if (dev_priv
->pc8
.irqs_disabled
) {
89 WARN(1, "IRQs disabled\n");
90 dev_priv
->pc8
.regsave
.deimr
&= ~mask
;
94 if ((dev_priv
->irq_mask
& mask
) != 0) {
95 dev_priv
->irq_mask
&= ~mask
;
96 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
102 ironlake_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
104 assert_spin_locked(&dev_priv
->irq_lock
);
106 if (dev_priv
->pc8
.irqs_disabled
) {
107 WARN(1, "IRQs disabled\n");
108 dev_priv
->pc8
.regsave
.deimr
|= mask
;
112 if ((dev_priv
->irq_mask
& mask
) != mask
) {
113 dev_priv
->irq_mask
|= mask
;
114 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
120 * ilk_update_gt_irq - update GTIMR
121 * @dev_priv: driver private
122 * @interrupt_mask: mask of interrupt bits to update
123 * @enabled_irq_mask: mask of interrupt bits to enable
125 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
126 uint32_t interrupt_mask
,
127 uint32_t enabled_irq_mask
)
129 assert_spin_locked(&dev_priv
->irq_lock
);
131 if (dev_priv
->pc8
.irqs_disabled
) {
132 WARN(1, "IRQs disabled\n");
133 dev_priv
->pc8
.regsave
.gtimr
&= ~interrupt_mask
;
134 dev_priv
->pc8
.regsave
.gtimr
|= (~enabled_irq_mask
&
139 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
140 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
141 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
145 void ilk_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
147 ilk_update_gt_irq(dev_priv
, mask
, mask
);
150 void ilk_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
152 ilk_update_gt_irq(dev_priv
, mask
, 0);
156 * snb_update_pm_irq - update GEN6_PMIMR
157 * @dev_priv: driver private
158 * @interrupt_mask: mask of interrupt bits to update
159 * @enabled_irq_mask: mask of interrupt bits to enable
161 static void snb_update_pm_irq(struct drm_i915_private
*dev_priv
,
162 uint32_t interrupt_mask
,
163 uint32_t enabled_irq_mask
)
167 assert_spin_locked(&dev_priv
->irq_lock
);
169 if (dev_priv
->pc8
.irqs_disabled
) {
170 WARN(1, "IRQs disabled\n");
171 dev_priv
->pc8
.regsave
.gen6_pmimr
&= ~interrupt_mask
;
172 dev_priv
->pc8
.regsave
.gen6_pmimr
|= (~enabled_irq_mask
&
177 new_val
= dev_priv
->pm_irq_mask
;
178 new_val
&= ~interrupt_mask
;
179 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
181 if (new_val
!= dev_priv
->pm_irq_mask
) {
182 dev_priv
->pm_irq_mask
= new_val
;
183 I915_WRITE(GEN6_PMIMR
, dev_priv
->pm_irq_mask
);
184 POSTING_READ(GEN6_PMIMR
);
188 void snb_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
190 snb_update_pm_irq(dev_priv
, mask
, mask
);
193 void snb_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
195 snb_update_pm_irq(dev_priv
, mask
, 0);
198 static bool ivb_can_enable_err_int(struct drm_device
*dev
)
200 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
201 struct intel_crtc
*crtc
;
204 assert_spin_locked(&dev_priv
->irq_lock
);
206 for_each_pipe(pipe
) {
207 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
209 if (crtc
->cpu_fifo_underrun_disabled
)
216 static bool cpt_can_enable_serr_int(struct drm_device
*dev
)
218 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
220 struct intel_crtc
*crtc
;
222 assert_spin_locked(&dev_priv
->irq_lock
);
224 for_each_pipe(pipe
) {
225 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
227 if (crtc
->pch_fifo_underrun_disabled
)
234 static void ironlake_set_fifo_underrun_reporting(struct drm_device
*dev
,
235 enum pipe pipe
, bool enable
)
237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
238 uint32_t bit
= (pipe
== PIPE_A
) ? DE_PIPEA_FIFO_UNDERRUN
:
239 DE_PIPEB_FIFO_UNDERRUN
;
242 ironlake_enable_display_irq(dev_priv
, bit
);
244 ironlake_disable_display_irq(dev_priv
, bit
);
247 static void ivybridge_set_fifo_underrun_reporting(struct drm_device
*dev
,
248 enum pipe pipe
, bool enable
)
250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
252 I915_WRITE(GEN7_ERR_INT
, ERR_INT_FIFO_UNDERRUN(pipe
));
254 if (!ivb_can_enable_err_int(dev
))
257 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
259 bool was_enabled
= !(I915_READ(DEIMR
) & DE_ERR_INT_IVB
);
261 /* Change the state _after_ we've read out the current one. */
262 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
265 (I915_READ(GEN7_ERR_INT
) & ERR_INT_FIFO_UNDERRUN(pipe
))) {
266 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
273 * ibx_display_interrupt_update - update SDEIMR
274 * @dev_priv: driver private
275 * @interrupt_mask: mask of interrupt bits to update
276 * @enabled_irq_mask: mask of interrupt bits to enable
278 static void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
279 uint32_t interrupt_mask
,
280 uint32_t enabled_irq_mask
)
282 uint32_t sdeimr
= I915_READ(SDEIMR
);
283 sdeimr
&= ~interrupt_mask
;
284 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
286 assert_spin_locked(&dev_priv
->irq_lock
);
288 if (dev_priv
->pc8
.irqs_disabled
&&
289 (interrupt_mask
& SDE_HOTPLUG_MASK_CPT
)) {
290 WARN(1, "IRQs disabled\n");
291 dev_priv
->pc8
.regsave
.sdeimr
&= ~interrupt_mask
;
292 dev_priv
->pc8
.regsave
.sdeimr
|= (~enabled_irq_mask
&
297 I915_WRITE(SDEIMR
, sdeimr
);
298 POSTING_READ(SDEIMR
);
300 #define ibx_enable_display_interrupt(dev_priv, bits) \
301 ibx_display_interrupt_update((dev_priv), (bits), (bits))
302 #define ibx_disable_display_interrupt(dev_priv, bits) \
303 ibx_display_interrupt_update((dev_priv), (bits), 0)
305 static void ibx_set_fifo_underrun_reporting(struct drm_device
*dev
,
306 enum transcoder pch_transcoder
,
309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
310 uint32_t bit
= (pch_transcoder
== TRANSCODER_A
) ?
311 SDE_TRANSA_FIFO_UNDER
: SDE_TRANSB_FIFO_UNDER
;
314 ibx_enable_display_interrupt(dev_priv
, bit
);
316 ibx_disable_display_interrupt(dev_priv
, bit
);
319 static void cpt_set_fifo_underrun_reporting(struct drm_device
*dev
,
320 enum transcoder pch_transcoder
,
323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
327 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
));
329 if (!cpt_can_enable_serr_int(dev
))
332 ibx_enable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
334 uint32_t tmp
= I915_READ(SERR_INT
);
335 bool was_enabled
= !(I915_READ(SDEIMR
) & SDE_ERROR_CPT
);
337 /* Change the state _after_ we've read out the current one. */
338 ibx_disable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
341 (tmp
& SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
))) {
342 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
343 transcoder_name(pch_transcoder
));
349 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
352 * @enable: true if we want to report FIFO underrun errors, false otherwise
354 * This function makes us disable or enable CPU fifo underruns for a specific
355 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
356 * reporting for one pipe may also disable all the other CPU error interruts for
357 * the other pipes, due to the fact that there's just one interrupt mask/enable
358 * bit for all the pipes.
360 * Returns the previous state of underrun reporting.
362 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
363 enum pipe pipe
, bool enable
)
365 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
366 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
367 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
371 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
373 ret
= !intel_crtc
->cpu_fifo_underrun_disabled
;
378 intel_crtc
->cpu_fifo_underrun_disabled
= !enable
;
380 if (IS_GEN5(dev
) || IS_GEN6(dev
))
381 ironlake_set_fifo_underrun_reporting(dev
, pipe
, enable
);
382 else if (IS_GEN7(dev
))
383 ivybridge_set_fifo_underrun_reporting(dev
, pipe
, enable
);
386 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
391 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
393 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
394 * @enable: true if we want to report FIFO underrun errors, false otherwise
396 * This function makes us disable or enable PCH fifo underruns for a specific
397 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
398 * underrun reporting for one transcoder may also disable all the other PCH
399 * error interruts for the other transcoders, due to the fact that there's just
400 * one interrupt mask/enable bit for all the transcoders.
402 * Returns the previous state of underrun reporting.
404 bool intel_set_pch_fifo_underrun_reporting(struct drm_device
*dev
,
405 enum transcoder pch_transcoder
,
408 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
409 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pch_transcoder
];
410 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
415 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
416 * has only one pch transcoder A that all pipes can use. To avoid racy
417 * pch transcoder -> pipe lookups from interrupt code simply store the
418 * underrun statistics in crtc A. Since we never expose this anywhere
419 * nor use it outside of the fifo underrun code here using the "wrong"
420 * crtc on LPT won't cause issues.
423 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
425 ret
= !intel_crtc
->pch_fifo_underrun_disabled
;
430 intel_crtc
->pch_fifo_underrun_disabled
= !enable
;
432 if (HAS_PCH_IBX(dev
))
433 ibx_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
435 cpt_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
438 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
444 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
446 u32 reg
= PIPESTAT(pipe
);
447 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
449 assert_spin_locked(&dev_priv
->irq_lock
);
451 if ((pipestat
& mask
) == mask
)
454 /* Enable the interrupt, clear any pending status */
455 pipestat
|= mask
| (mask
>> 16);
456 I915_WRITE(reg
, pipestat
);
461 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
463 u32 reg
= PIPESTAT(pipe
);
464 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
466 assert_spin_locked(&dev_priv
->irq_lock
);
468 if ((pipestat
& mask
) == 0)
472 I915_WRITE(reg
, pipestat
);
477 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
479 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
481 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
482 unsigned long irqflags
;
484 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
487 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
489 i915_enable_pipestat(dev_priv
, 1, PIPE_LEGACY_BLC_EVENT_ENABLE
);
490 if (INTEL_INFO(dev
)->gen
>= 4)
491 i915_enable_pipestat(dev_priv
, 0, PIPE_LEGACY_BLC_EVENT_ENABLE
);
493 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
497 * i915_pipe_enabled - check if a pipe is enabled
499 * @pipe: pipe to check
501 * Reading certain registers when the pipe is disabled can hang the chip.
502 * Use this routine to make sure the PLL is running and the pipe is active
503 * before reading such registers if unsure.
506 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
508 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
510 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
511 /* Locking is horribly broken here, but whatever. */
512 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
513 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
515 return intel_crtc
->active
;
517 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
521 /* Called from drm generic code, passed a 'crtc', which
522 * we use as a pipe index
524 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
526 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
527 unsigned long high_frame
;
528 unsigned long low_frame
;
529 u32 high1
, high2
, low
;
531 if (!i915_pipe_enabled(dev
, pipe
)) {
532 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
533 "pipe %c\n", pipe_name(pipe
));
537 high_frame
= PIPEFRAME(pipe
);
538 low_frame
= PIPEFRAMEPIXEL(pipe
);
541 * High & low register fields aren't synchronized, so make sure
542 * we get a low value that's stable across two reads of the high
546 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
547 low
= I915_READ(low_frame
) & PIPE_FRAME_LOW_MASK
;
548 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
549 } while (high1
!= high2
);
551 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
552 low
>>= PIPE_FRAME_LOW_SHIFT
;
553 return (high1
<< 8) | low
;
556 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
558 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
559 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
561 if (!i915_pipe_enabled(dev
, pipe
)) {
562 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
563 "pipe %c\n", pipe_name(pipe
));
567 return I915_READ(reg
);
570 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
571 int *vpos
, int *hpos
)
573 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
574 u32 vbl
= 0, position
= 0;
575 int vbl_start
, vbl_end
, htotal
, vtotal
;
578 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
581 if (!i915_pipe_enabled(dev
, pipe
)) {
582 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
583 "pipe %c\n", pipe_name(pipe
));
588 vtotal
= 1 + ((I915_READ(VTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
590 if (INTEL_INFO(dev
)->gen
>= 4) {
591 /* No obvious pixelcount register. Only query vertical
592 * scanout position from Display scan line register.
594 position
= I915_READ(PIPEDSL(pipe
));
596 /* Decode into vertical scanout position. Don't have
597 * horizontal scanout position.
599 *vpos
= position
& 0x1fff;
602 /* Have access to pixelcount since start of frame.
603 * We can split this into vertical and horizontal
606 position
= (I915_READ(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
608 htotal
= 1 + ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
609 *vpos
= position
/ htotal
;
610 *hpos
= position
- (*vpos
* htotal
);
613 /* Query vblank area. */
614 vbl
= I915_READ(VBLANK(cpu_transcoder
));
616 /* Test position against vblank region. */
617 vbl_start
= vbl
& 0x1fff;
618 vbl_end
= (vbl
>> 16) & 0x1fff;
620 if ((*vpos
< vbl_start
) || (*vpos
> vbl_end
))
623 /* Inside "upper part" of vblank area? Apply corrective offset: */
624 if (in_vbl
&& (*vpos
>= vbl_start
))
625 *vpos
= *vpos
- vtotal
;
627 /* Readouts valid? */
629 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
633 ret
|= DRM_SCANOUTPOS_INVBL
;
638 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
640 struct timeval
*vblank_time
,
643 struct drm_crtc
*crtc
;
645 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
646 DRM_ERROR("Invalid crtc %d\n", pipe
);
650 /* Get drm_crtc to timestamp: */
651 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
653 DRM_ERROR("Invalid crtc %d\n", pipe
);
657 if (!crtc
->enabled
) {
658 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
662 /* Helper routine in DRM core does all the work: */
663 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
668 static int intel_hpd_irq_event(struct drm_device
*dev
, struct drm_connector
*connector
)
670 enum drm_connector_status old_status
;
672 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
673 old_status
= connector
->status
;
675 connector
->status
= connector
->funcs
->detect(connector
, false);
676 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
678 drm_get_connector_name(connector
),
679 old_status
, connector
->status
);
680 return (old_status
!= connector
->status
);
684 * Handle hotplug events outside the interrupt handler proper.
686 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
688 static void i915_hotplug_work_func(struct work_struct
*work
)
690 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
692 struct drm_device
*dev
= dev_priv
->dev
;
693 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
694 struct intel_connector
*intel_connector
;
695 struct intel_encoder
*intel_encoder
;
696 struct drm_connector
*connector
;
697 unsigned long irqflags
;
698 bool hpd_disabled
= false;
699 bool changed
= false;
702 /* HPD irq before everything is fully set up. */
703 if (!dev_priv
->enable_hotplug_processing
)
706 mutex_lock(&mode_config
->mutex
);
707 DRM_DEBUG_KMS("running encoder hotplug functions\n");
709 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
711 hpd_event_bits
= dev_priv
->hpd_event_bits
;
712 dev_priv
->hpd_event_bits
= 0;
713 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
714 intel_connector
= to_intel_connector(connector
);
715 intel_encoder
= intel_connector
->encoder
;
716 if (intel_encoder
->hpd_pin
> HPD_NONE
&&
717 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_MARK_DISABLED
&&
718 connector
->polled
== DRM_CONNECTOR_POLL_HPD
) {
719 DRM_INFO("HPD interrupt storm detected on connector %s: "
720 "switching from hotplug detection to polling\n",
721 drm_get_connector_name(connector
));
722 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
= HPD_DISABLED
;
723 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
724 | DRM_CONNECTOR_POLL_DISCONNECT
;
727 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
728 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
729 drm_get_connector_name(connector
), intel_encoder
->hpd_pin
);
732 /* if there were no outputs to poll, poll was disabled,
733 * therefore make sure it's enabled when disabling HPD on
736 drm_kms_helper_poll_enable(dev
);
737 mod_timer(&dev_priv
->hotplug_reenable_timer
,
738 jiffies
+ msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY
));
741 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
743 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
744 intel_connector
= to_intel_connector(connector
);
745 intel_encoder
= intel_connector
->encoder
;
746 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
747 if (intel_encoder
->hot_plug
)
748 intel_encoder
->hot_plug(intel_encoder
);
749 if (intel_hpd_irq_event(dev
, connector
))
753 mutex_unlock(&mode_config
->mutex
);
756 drm_kms_helper_hotplug_event(dev
);
759 static void ironlake_rps_change_irq_handler(struct drm_device
*dev
)
761 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
762 u32 busy_up
, busy_down
, max_avg
, min_avg
;
765 spin_lock(&mchdev_lock
);
767 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
769 new_delay
= dev_priv
->ips
.cur_delay
;
771 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
772 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
773 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
774 max_avg
= I915_READ(RCBMAXAVG
);
775 min_avg
= I915_READ(RCBMINAVG
);
777 /* Handle RCS change request from hw */
778 if (busy_up
> max_avg
) {
779 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
780 new_delay
= dev_priv
->ips
.cur_delay
- 1;
781 if (new_delay
< dev_priv
->ips
.max_delay
)
782 new_delay
= dev_priv
->ips
.max_delay
;
783 } else if (busy_down
< min_avg
) {
784 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
785 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
786 if (new_delay
> dev_priv
->ips
.min_delay
)
787 new_delay
= dev_priv
->ips
.min_delay
;
790 if (ironlake_set_drps(dev
, new_delay
))
791 dev_priv
->ips
.cur_delay
= new_delay
;
793 spin_unlock(&mchdev_lock
);
798 static void notify_ring(struct drm_device
*dev
,
799 struct intel_ring_buffer
*ring
)
801 if (ring
->obj
== NULL
)
804 trace_i915_gem_request_complete(ring
, ring
->get_seqno(ring
, false));
806 wake_up_all(&ring
->irq_queue
);
807 i915_queue_hangcheck(dev
);
810 static void gen6_pm_rps_work(struct work_struct
*work
)
812 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
817 spin_lock_irq(&dev_priv
->irq_lock
);
818 pm_iir
= dev_priv
->rps
.pm_iir
;
819 dev_priv
->rps
.pm_iir
= 0;
820 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
821 snb_enable_pm_irq(dev_priv
, GEN6_PM_RPS_EVENTS
);
822 spin_unlock_irq(&dev_priv
->irq_lock
);
824 /* Make sure we didn't queue anything we're not going to process. */
825 WARN_ON(pm_iir
& ~GEN6_PM_RPS_EVENTS
);
827 if ((pm_iir
& GEN6_PM_RPS_EVENTS
) == 0)
830 mutex_lock(&dev_priv
->rps
.hw_lock
);
832 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
833 new_delay
= dev_priv
->rps
.cur_delay
+ 1;
836 * For better performance, jump directly
837 * to RPe if we're below it.
839 if (IS_VALLEYVIEW(dev_priv
->dev
) &&
840 dev_priv
->rps
.cur_delay
< dev_priv
->rps
.rpe_delay
)
841 new_delay
= dev_priv
->rps
.rpe_delay
;
843 new_delay
= dev_priv
->rps
.cur_delay
- 1;
845 /* sysfs frequency interfaces may have snuck in while servicing the
848 if (new_delay
>= dev_priv
->rps
.min_delay
&&
849 new_delay
<= dev_priv
->rps
.max_delay
) {
850 if (IS_VALLEYVIEW(dev_priv
->dev
))
851 valleyview_set_rps(dev_priv
->dev
, new_delay
);
853 gen6_set_rps(dev_priv
->dev
, new_delay
);
856 if (IS_VALLEYVIEW(dev_priv
->dev
)) {
858 * On VLV, when we enter RC6 we may not be at the minimum
859 * voltage level, so arm a timer to check. It should only
860 * fire when there's activity or once after we've entered
861 * RC6, and then won't be re-armed until the next RPS interrupt.
863 mod_delayed_work(dev_priv
->wq
, &dev_priv
->rps
.vlv_work
,
864 msecs_to_jiffies(100));
867 mutex_unlock(&dev_priv
->rps
.hw_lock
);
872 * ivybridge_parity_work - Workqueue called when a parity error interrupt
874 * @work: workqueue struct
876 * Doesn't actually do anything except notify userspace. As a consequence of
877 * this event, userspace should try to remap the bad rows since statistically
878 * it is likely the same row is more likely to go bad again.
880 static void ivybridge_parity_work(struct work_struct
*work
)
882 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
883 l3_parity
.error_work
);
884 u32 error_status
, row
, bank
, subbank
;
885 char *parity_event
[5];
889 /* We must turn off DOP level clock gating to access the L3 registers.
890 * In order to prevent a get/put style interface, acquire struct mutex
891 * any time we access those registers.
893 mutex_lock(&dev_priv
->dev
->struct_mutex
);
895 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
896 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
897 POSTING_READ(GEN7_MISCCPCTL
);
899 error_status
= I915_READ(GEN7_L3CDERRST1
);
900 row
= GEN7_PARITY_ERROR_ROW(error_status
);
901 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
902 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
904 I915_WRITE(GEN7_L3CDERRST1
, GEN7_PARITY_ERROR_VALID
|
905 GEN7_L3CDERRST1_ENABLE
);
906 POSTING_READ(GEN7_L3CDERRST1
);
908 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
910 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
911 ilk_enable_gt_irq(dev_priv
, GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
912 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
914 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
916 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
917 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
918 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
919 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
920 parity_event
[4] = NULL
;
922 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
.kobj
,
923 KOBJ_CHANGE
, parity_event
);
925 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
928 kfree(parity_event
[3]);
929 kfree(parity_event
[2]);
930 kfree(parity_event
[1]);
933 static void ivybridge_parity_error_irq_handler(struct drm_device
*dev
)
935 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
937 if (!HAS_L3_GPU_CACHE(dev
))
940 spin_lock(&dev_priv
->irq_lock
);
941 ilk_disable_gt_irq(dev_priv
, GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
942 spin_unlock(&dev_priv
->irq_lock
);
944 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
947 static void ilk_gt_irq_handler(struct drm_device
*dev
,
948 struct drm_i915_private
*dev_priv
,
952 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
953 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
954 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
955 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
958 static void snb_gt_irq_handler(struct drm_device
*dev
,
959 struct drm_i915_private
*dev_priv
,
964 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
965 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
966 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
967 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
968 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
969 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
971 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
972 GT_BSD_CS_ERROR_INTERRUPT
|
973 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
)) {
974 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir
);
975 i915_handle_error(dev
, false);
978 if (gt_iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
979 ivybridge_parity_error_irq_handler(dev
);
982 #define HPD_STORM_DETECT_PERIOD 1000
983 #define HPD_STORM_THRESHOLD 5
985 static inline void intel_hpd_irq_handler(struct drm_device
*dev
,
989 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
991 bool storm_detected
= false;
993 if (!hotplug_trigger
)
996 spin_lock(&dev_priv
->irq_lock
);
997 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
999 WARN(((hpd
[i
] & hotplug_trigger
) &&
1000 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
),
1001 "Received HPD interrupt although disabled\n");
1003 if (!(hpd
[i
] & hotplug_trigger
) ||
1004 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
)
1007 dev_priv
->hpd_event_bits
|= (1 << i
);
1008 if (!time_in_range(jiffies
, dev_priv
->hpd_stats
[i
].hpd_last_jiffies
,
1009 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
1010 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD
))) {
1011 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
= jiffies
;
1012 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
1013 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i
);
1014 } else if (dev_priv
->hpd_stats
[i
].hpd_cnt
> HPD_STORM_THRESHOLD
) {
1015 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_MARK_DISABLED
;
1016 dev_priv
->hpd_event_bits
&= ~(1 << i
);
1017 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i
);
1018 storm_detected
= true;
1020 dev_priv
->hpd_stats
[i
].hpd_cnt
++;
1021 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i
,
1022 dev_priv
->hpd_stats
[i
].hpd_cnt
);
1027 dev_priv
->display
.hpd_irq_setup(dev
);
1028 spin_unlock(&dev_priv
->irq_lock
);
1031 * Our hotplug handler can grab modeset locks (by calling down into the
1032 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1033 * queue for otherwise the flush_work in the pageflip code will
1036 schedule_work(&dev_priv
->hotplug_work
);
1039 static void gmbus_irq_handler(struct drm_device
*dev
)
1041 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1043 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1046 static void dp_aux_irq_handler(struct drm_device
*dev
)
1048 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1050 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1053 /* The RPS events need forcewake, so we add them to a work queue and mask their
1054 * IMR bits until the work is done. Other interrupts can be processed without
1055 * the work queue. */
1056 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1058 if (pm_iir
& GEN6_PM_RPS_EVENTS
) {
1059 spin_lock(&dev_priv
->irq_lock
);
1060 dev_priv
->rps
.pm_iir
|= pm_iir
& GEN6_PM_RPS_EVENTS
;
1061 snb_disable_pm_irq(dev_priv
, pm_iir
& GEN6_PM_RPS_EVENTS
);
1062 spin_unlock(&dev_priv
->irq_lock
);
1064 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
1067 if (HAS_VEBOX(dev_priv
->dev
)) {
1068 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1069 notify_ring(dev_priv
->dev
, &dev_priv
->ring
[VECS
]);
1071 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
) {
1072 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir
);
1073 i915_handle_error(dev_priv
->dev
, false);
1078 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1080 struct drm_device
*dev
= (struct drm_device
*) arg
;
1081 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1082 u32 iir
, gt_iir
, pm_iir
;
1083 irqreturn_t ret
= IRQ_NONE
;
1084 unsigned long irqflags
;
1086 u32 pipe_stats
[I915_MAX_PIPES
];
1088 atomic_inc(&dev_priv
->irq_received
);
1091 iir
= I915_READ(VLV_IIR
);
1092 gt_iir
= I915_READ(GTIIR
);
1093 pm_iir
= I915_READ(GEN6_PMIIR
);
1095 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1100 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1102 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1103 for_each_pipe(pipe
) {
1104 int reg
= PIPESTAT(pipe
);
1105 pipe_stats
[pipe
] = I915_READ(reg
);
1108 * Clear the PIPE*STAT regs before the IIR
1110 if (pipe_stats
[pipe
] & 0x8000ffff) {
1111 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1112 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1114 I915_WRITE(reg
, pipe_stats
[pipe
]);
1117 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1119 for_each_pipe(pipe
) {
1120 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
)
1121 drm_handle_vblank(dev
, pipe
);
1123 if (pipe_stats
[pipe
] & PLANE_FLIPDONE_INT_STATUS_VLV
) {
1124 intel_prepare_page_flip(dev
, pipe
);
1125 intel_finish_page_flip(dev
, pipe
);
1129 /* Consume port. Then clear IIR or we'll miss events */
1130 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
1131 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1132 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1134 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1137 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
1139 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1140 I915_READ(PORT_HOTPLUG_STAT
);
1143 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1144 gmbus_irq_handler(dev
);
1147 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1149 I915_WRITE(GTIIR
, gt_iir
);
1150 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1151 I915_WRITE(VLV_IIR
, iir
);
1158 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1160 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1162 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1164 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ibx
);
1166 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1167 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1168 SDE_AUDIO_POWER_SHIFT
);
1169 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1173 if (pch_iir
& SDE_AUX_MASK
)
1174 dp_aux_irq_handler(dev
);
1176 if (pch_iir
& SDE_GMBUS
)
1177 gmbus_irq_handler(dev
);
1179 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1180 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1182 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1183 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1185 if (pch_iir
& SDE_POISON
)
1186 DRM_ERROR("PCH poison interrupt\n");
1188 if (pch_iir
& SDE_FDI_MASK
)
1190 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1192 I915_READ(FDI_RX_IIR(pipe
)));
1194 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1195 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1197 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1198 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1200 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1201 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1203 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1205 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1206 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1208 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1211 static void ivb_err_int_handler(struct drm_device
*dev
)
1213 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1214 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1216 if (err_int
& ERR_INT_POISON
)
1217 DRM_ERROR("Poison interrupt\n");
1219 if (err_int
& ERR_INT_FIFO_UNDERRUN_A
)
1220 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1221 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1223 if (err_int
& ERR_INT_FIFO_UNDERRUN_B
)
1224 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1225 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1227 if (err_int
& ERR_INT_FIFO_UNDERRUN_C
)
1228 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_C
, false))
1229 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1231 I915_WRITE(GEN7_ERR_INT
, err_int
);
1234 static void cpt_serr_int_handler(struct drm_device
*dev
)
1236 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1237 u32 serr_int
= I915_READ(SERR_INT
);
1239 if (serr_int
& SERR_INT_POISON
)
1240 DRM_ERROR("PCH poison interrupt\n");
1242 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
1243 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1245 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1247 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
1248 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1250 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1252 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
1253 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_C
,
1255 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1257 I915_WRITE(SERR_INT
, serr_int
);
1260 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1262 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1264 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
1266 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_cpt
);
1268 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
1269 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
1270 SDE_AUDIO_POWER_SHIFT_CPT
);
1271 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1275 if (pch_iir
& SDE_AUX_MASK_CPT
)
1276 dp_aux_irq_handler(dev
);
1278 if (pch_iir
& SDE_GMBUS_CPT
)
1279 gmbus_irq_handler(dev
);
1281 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
1282 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1284 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
1285 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1287 if (pch_iir
& SDE_FDI_MASK_CPT
)
1289 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1291 I915_READ(FDI_RX_IIR(pipe
)));
1293 if (pch_iir
& SDE_ERROR_CPT
)
1294 cpt_serr_int_handler(dev
);
1297 static void ilk_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1299 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1301 if (de_iir
& DE_AUX_CHANNEL_A
)
1302 dp_aux_irq_handler(dev
);
1304 if (de_iir
& DE_GSE
)
1305 intel_opregion_asle_intr(dev
);
1307 if (de_iir
& DE_PIPEA_VBLANK
)
1308 drm_handle_vblank(dev
, 0);
1310 if (de_iir
& DE_PIPEB_VBLANK
)
1311 drm_handle_vblank(dev
, 1);
1313 if (de_iir
& DE_POISON
)
1314 DRM_ERROR("Poison interrupt\n");
1316 if (de_iir
& DE_PIPEA_FIFO_UNDERRUN
)
1317 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1318 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1320 if (de_iir
& DE_PIPEB_FIFO_UNDERRUN
)
1321 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1322 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1324 if (de_iir
& DE_PLANEA_FLIP_DONE
) {
1325 intel_prepare_page_flip(dev
, 0);
1326 intel_finish_page_flip_plane(dev
, 0);
1329 if (de_iir
& DE_PLANEB_FLIP_DONE
) {
1330 intel_prepare_page_flip(dev
, 1);
1331 intel_finish_page_flip_plane(dev
, 1);
1334 /* check event from PCH */
1335 if (de_iir
& DE_PCH_EVENT
) {
1336 u32 pch_iir
= I915_READ(SDEIIR
);
1338 if (HAS_PCH_CPT(dev
))
1339 cpt_irq_handler(dev
, pch_iir
);
1341 ibx_irq_handler(dev
, pch_iir
);
1343 /* should clear PCH hotplug event before clear CPU irq */
1344 I915_WRITE(SDEIIR
, pch_iir
);
1347 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
1348 ironlake_rps_change_irq_handler(dev
);
1351 static void ivb_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1353 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1356 if (de_iir
& DE_ERR_INT_IVB
)
1357 ivb_err_int_handler(dev
);
1359 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
1360 dp_aux_irq_handler(dev
);
1362 if (de_iir
& DE_GSE_IVB
)
1363 intel_opregion_asle_intr(dev
);
1365 for (i
= 0; i
< 3; i
++) {
1366 if (de_iir
& (DE_PIPEA_VBLANK_IVB
<< (5 * i
)))
1367 drm_handle_vblank(dev
, i
);
1368 if (de_iir
& (DE_PLANEA_FLIP_DONE_IVB
<< (5 * i
))) {
1369 intel_prepare_page_flip(dev
, i
);
1370 intel_finish_page_flip_plane(dev
, i
);
1374 /* check event from PCH */
1375 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
1376 u32 pch_iir
= I915_READ(SDEIIR
);
1378 cpt_irq_handler(dev
, pch_iir
);
1380 /* clear PCH hotplug event before clear CPU irq */
1381 I915_WRITE(SDEIIR
, pch_iir
);
1385 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
1387 struct drm_device
*dev
= (struct drm_device
*) arg
;
1388 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1389 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
1390 irqreturn_t ret
= IRQ_NONE
;
1391 bool err_int_reenable
= false;
1393 atomic_inc(&dev_priv
->irq_received
);
1395 /* We get interrupts on unclaimed registers, so check for this before we
1396 * do any I915_{READ,WRITE}. */
1397 intel_uncore_check_errors(dev
);
1399 /* disable master interrupt before clearing iir */
1400 de_ier
= I915_READ(DEIER
);
1401 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
1402 POSTING_READ(DEIER
);
1404 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1405 * interrupts will will be stored on its back queue, and then we'll be
1406 * able to process them after we restore SDEIER (as soon as we restore
1407 * it, we'll get an interrupt if SDEIIR still has something to process
1408 * due to its back queue). */
1409 if (!HAS_PCH_NOP(dev
)) {
1410 sde_ier
= I915_READ(SDEIER
);
1411 I915_WRITE(SDEIER
, 0);
1412 POSTING_READ(SDEIER
);
1415 /* On Haswell, also mask ERR_INT because we don't want to risk
1416 * generating "unclaimed register" interrupts from inside the interrupt
1418 if (IS_HASWELL(dev
)) {
1419 spin_lock(&dev_priv
->irq_lock
);
1420 err_int_reenable
= ~dev_priv
->irq_mask
& DE_ERR_INT_IVB
;
1421 if (err_int_reenable
)
1422 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
1423 spin_unlock(&dev_priv
->irq_lock
);
1426 gt_iir
= I915_READ(GTIIR
);
1428 if (INTEL_INFO(dev
)->gen
>= 6)
1429 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1431 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1432 I915_WRITE(GTIIR
, gt_iir
);
1436 de_iir
= I915_READ(DEIIR
);
1438 if (INTEL_INFO(dev
)->gen
>= 7)
1439 ivb_display_irq_handler(dev
, de_iir
);
1441 ilk_display_irq_handler(dev
, de_iir
);
1442 I915_WRITE(DEIIR
, de_iir
);
1446 if (INTEL_INFO(dev
)->gen
>= 6) {
1447 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
1449 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1450 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1455 if (err_int_reenable
) {
1456 spin_lock(&dev_priv
->irq_lock
);
1457 if (ivb_can_enable_err_int(dev
))
1458 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
1459 spin_unlock(&dev_priv
->irq_lock
);
1462 I915_WRITE(DEIER
, de_ier
);
1463 POSTING_READ(DEIER
);
1464 if (!HAS_PCH_NOP(dev
)) {
1465 I915_WRITE(SDEIER
, sde_ier
);
1466 POSTING_READ(SDEIER
);
1473 * i915_error_work_func - do process context error handling work
1474 * @work: work struct
1476 * Fire an error uevent so userspace can see that a hang or error
1479 static void i915_error_work_func(struct work_struct
*work
)
1481 struct i915_gpu_error
*error
= container_of(work
, struct i915_gpu_error
,
1483 drm_i915_private_t
*dev_priv
= container_of(error
, drm_i915_private_t
,
1485 struct drm_device
*dev
= dev_priv
->dev
;
1486 struct intel_ring_buffer
*ring
;
1487 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
1488 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
1489 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
1492 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, error_event
);
1495 * Note that there's only one work item which does gpu resets, so we
1496 * need not worry about concurrent gpu resets potentially incrementing
1497 * error->reset_counter twice. We only need to take care of another
1498 * racing irq/hangcheck declaring the gpu dead for a second time. A
1499 * quick check for that is good enough: schedule_work ensures the
1500 * correct ordering between hang detection and this work item, and since
1501 * the reset in-progress bit is only ever set by code outside of this
1502 * work we don't need to worry about any other races.
1504 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
1505 DRM_DEBUG_DRIVER("resetting chip\n");
1506 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
,
1509 ret
= i915_reset(dev
);
1513 * After all the gem state is reset, increment the reset
1514 * counter and wake up everyone waiting for the reset to
1517 * Since unlock operations are a one-sided barrier only,
1518 * we need to insert a barrier here to order any seqno
1520 * the counter increment.
1522 smp_mb__before_atomic_inc();
1523 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
1525 kobject_uevent_env(&dev
->primary
->kdev
.kobj
,
1526 KOBJ_CHANGE
, reset_done_event
);
1528 atomic_set(&error
->reset_counter
, I915_WEDGED
);
1531 for_each_ring(ring
, dev_priv
, i
)
1532 wake_up_all(&ring
->irq_queue
);
1534 intel_display_handle_reset(dev
);
1536 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
1540 static void i915_report_and_clear_eir(struct drm_device
*dev
)
1542 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1543 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
1544 u32 eir
= I915_READ(EIR
);
1550 pr_err("render error detected, EIR: 0x%08x\n", eir
);
1552 i915_get_extra_instdone(dev
, instdone
);
1555 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
1556 u32 ipeir
= I915_READ(IPEIR_I965
);
1558 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1559 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1560 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1561 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1562 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1563 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1564 I915_WRITE(IPEIR_I965
, ipeir
);
1565 POSTING_READ(IPEIR_I965
);
1567 if (eir
& GM45_ERROR_PAGE_TABLE
) {
1568 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1569 pr_err("page table error\n");
1570 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1571 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1572 POSTING_READ(PGTBL_ER
);
1576 if (!IS_GEN2(dev
)) {
1577 if (eir
& I915_ERROR_PAGE_TABLE
) {
1578 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1579 pr_err("page table error\n");
1580 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1581 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1582 POSTING_READ(PGTBL_ER
);
1586 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
1587 pr_err("memory refresh error:\n");
1589 pr_err("pipe %c stat: 0x%08x\n",
1590 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
1591 /* pipestat has already been acked */
1593 if (eir
& I915_ERROR_INSTRUCTION
) {
1594 pr_err("instruction error\n");
1595 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
1596 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1597 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1598 if (INTEL_INFO(dev
)->gen
< 4) {
1599 u32 ipeir
= I915_READ(IPEIR
);
1601 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
1602 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
1603 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
1604 I915_WRITE(IPEIR
, ipeir
);
1605 POSTING_READ(IPEIR
);
1607 u32 ipeir
= I915_READ(IPEIR_I965
);
1609 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1610 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1611 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1612 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1613 I915_WRITE(IPEIR_I965
, ipeir
);
1614 POSTING_READ(IPEIR_I965
);
1618 I915_WRITE(EIR
, eir
);
1620 eir
= I915_READ(EIR
);
1623 * some errors might have become stuck,
1626 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
1627 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
1628 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
1633 * i915_handle_error - handle an error interrupt
1636 * Do some basic checking of regsiter state at error interrupt time and
1637 * dump it to the syslog. Also call i915_capture_error_state() to make
1638 * sure we get a record and make it available in debugfs. Fire a uevent
1639 * so userspace knows something bad happened (should trigger collection
1640 * of a ring dump etc.).
1642 void i915_handle_error(struct drm_device
*dev
, bool wedged
)
1644 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1645 struct intel_ring_buffer
*ring
;
1648 i915_capture_error_state(dev
);
1649 i915_report_and_clear_eir(dev
);
1652 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
1653 &dev_priv
->gpu_error
.reset_counter
);
1656 * Wakeup waiting processes so that the reset work item
1657 * doesn't deadlock trying to grab various locks.
1659 for_each_ring(ring
, dev_priv
, i
)
1660 wake_up_all(&ring
->irq_queue
);
1664 * Our reset work can grab modeset locks (since it needs to reset the
1665 * state of outstanding pagelips). Hence it must not be run on our own
1666 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
1667 * code will deadlock.
1669 schedule_work(&dev_priv
->gpu_error
.work
);
1672 static void __always_unused
i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
1674 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1675 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1676 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1677 struct drm_i915_gem_object
*obj
;
1678 struct intel_unpin_work
*work
;
1679 unsigned long flags
;
1680 bool stall_detected
;
1682 /* Ignore early vblank irqs */
1683 if (intel_crtc
== NULL
)
1686 spin_lock_irqsave(&dev
->event_lock
, flags
);
1687 work
= intel_crtc
->unpin_work
;
1690 atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
||
1691 !work
->enable_stall_check
) {
1692 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1693 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1697 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1698 obj
= work
->pending_flip_obj
;
1699 if (INTEL_INFO(dev
)->gen
>= 4) {
1700 int dspsurf
= DSPSURF(intel_crtc
->plane
);
1701 stall_detected
= I915_HI_DISPBASE(I915_READ(dspsurf
)) ==
1702 i915_gem_obj_ggtt_offset(obj
);
1704 int dspaddr
= DSPADDR(intel_crtc
->plane
);
1705 stall_detected
= I915_READ(dspaddr
) == (i915_gem_obj_ggtt_offset(obj
) +
1706 crtc
->y
* crtc
->fb
->pitches
[0] +
1707 crtc
->x
* crtc
->fb
->bits_per_pixel
/8);
1710 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1712 if (stall_detected
) {
1713 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1714 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
1718 /* Called from drm generic code, passed 'crtc' which
1719 * we use as a pipe index
1721 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
1723 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1724 unsigned long irqflags
;
1726 if (!i915_pipe_enabled(dev
, pipe
))
1729 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1730 if (INTEL_INFO(dev
)->gen
>= 4)
1731 i915_enable_pipestat(dev_priv
, pipe
,
1732 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1734 i915_enable_pipestat(dev_priv
, pipe
,
1735 PIPE_VBLANK_INTERRUPT_ENABLE
);
1737 /* maintain vblank delivery even in deep C-states */
1738 if (dev_priv
->info
->gen
== 3)
1739 I915_WRITE(INSTPM
, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS
));
1740 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1745 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
1747 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1748 unsigned long irqflags
;
1749 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
1750 DE_PIPE_VBLANK_ILK(pipe
);
1752 if (!i915_pipe_enabled(dev
, pipe
))
1755 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1756 ironlake_enable_display_irq(dev_priv
, bit
);
1757 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1762 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
1764 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1765 unsigned long irqflags
;
1768 if (!i915_pipe_enabled(dev
, pipe
))
1771 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1772 imr
= I915_READ(VLV_IMR
);
1774 imr
&= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1776 imr
&= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1777 I915_WRITE(VLV_IMR
, imr
);
1778 i915_enable_pipestat(dev_priv
, pipe
,
1779 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1780 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1785 /* Called from drm generic code, passed 'crtc' which
1786 * we use as a pipe index
1788 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
1790 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1791 unsigned long irqflags
;
1793 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1794 if (dev_priv
->info
->gen
== 3)
1795 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS
));
1797 i915_disable_pipestat(dev_priv
, pipe
,
1798 PIPE_VBLANK_INTERRUPT_ENABLE
|
1799 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1800 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1803 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
1805 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1806 unsigned long irqflags
;
1807 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
1808 DE_PIPE_VBLANK_ILK(pipe
);
1810 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1811 ironlake_disable_display_irq(dev_priv
, bit
);
1812 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1815 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
1817 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1818 unsigned long irqflags
;
1821 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1822 i915_disable_pipestat(dev_priv
, pipe
,
1823 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1824 imr
= I915_READ(VLV_IMR
);
1826 imr
|= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1828 imr
|= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1829 I915_WRITE(VLV_IMR
, imr
);
1830 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1834 ring_last_seqno(struct intel_ring_buffer
*ring
)
1836 return list_entry(ring
->request_list
.prev
,
1837 struct drm_i915_gem_request
, list
)->seqno
;
1841 ring_idle(struct intel_ring_buffer
*ring
, u32 seqno
)
1843 return (list_empty(&ring
->request_list
) ||
1844 i915_seqno_passed(seqno
, ring_last_seqno(ring
)));
1847 static struct intel_ring_buffer
*
1848 semaphore_waits_for(struct intel_ring_buffer
*ring
, u32
*seqno
)
1850 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1851 u32 cmd
, ipehr
, acthd
, acthd_min
;
1853 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
1854 if ((ipehr
& ~(0x3 << 16)) !=
1855 (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
| MI_SEMAPHORE_REGISTER
))
1858 /* ACTHD is likely pointing to the dword after the actual command,
1859 * so scan backwards until we find the MBOX.
1861 acthd
= intel_ring_get_active_head(ring
) & HEAD_ADDR
;
1862 acthd_min
= max((int)acthd
- 3 * 4, 0);
1864 cmd
= ioread32(ring
->virtual_start
+ acthd
);
1869 if (acthd
< acthd_min
)
1873 *seqno
= ioread32(ring
->virtual_start
+acthd
+4)+1;
1874 return &dev_priv
->ring
[(ring
->id
+ (((ipehr
>> 17) & 1) + 1)) % 3];
1877 static int semaphore_passed(struct intel_ring_buffer
*ring
)
1879 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1880 struct intel_ring_buffer
*signaller
;
1883 ring
->hangcheck
.deadlock
= true;
1885 signaller
= semaphore_waits_for(ring
, &seqno
);
1886 if (signaller
== NULL
|| signaller
->hangcheck
.deadlock
)
1889 /* cursory check for an unkickable deadlock */
1890 ctl
= I915_READ_CTL(signaller
);
1891 if (ctl
& RING_WAIT_SEMAPHORE
&& semaphore_passed(signaller
) < 0)
1894 return i915_seqno_passed(signaller
->get_seqno(signaller
, false), seqno
);
1897 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
1899 struct intel_ring_buffer
*ring
;
1902 for_each_ring(ring
, dev_priv
, i
)
1903 ring
->hangcheck
.deadlock
= false;
1906 static enum intel_ring_hangcheck_action
1907 ring_stuck(struct intel_ring_buffer
*ring
, u32 acthd
)
1909 struct drm_device
*dev
= ring
->dev
;
1910 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1913 if (ring
->hangcheck
.acthd
!= acthd
)
1914 return HANGCHECK_ACTIVE
;
1917 return HANGCHECK_HUNG
;
1919 /* Is the chip hanging on a WAIT_FOR_EVENT?
1920 * If so we can simply poke the RB_WAIT bit
1921 * and break the hang. This should work on
1922 * all but the second generation chipsets.
1924 tmp
= I915_READ_CTL(ring
);
1925 if (tmp
& RING_WAIT
) {
1926 DRM_ERROR("Kicking stuck wait on %s\n",
1928 I915_WRITE_CTL(ring
, tmp
);
1929 return HANGCHECK_KICK
;
1932 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
1933 switch (semaphore_passed(ring
)) {
1935 return HANGCHECK_HUNG
;
1937 DRM_ERROR("Kicking stuck semaphore on %s\n",
1939 I915_WRITE_CTL(ring
, tmp
);
1940 return HANGCHECK_KICK
;
1942 return HANGCHECK_WAIT
;
1946 return HANGCHECK_HUNG
;
1950 * This is called when the chip hasn't reported back with completed
1951 * batchbuffers in a long time. We keep track per ring seqno progress and
1952 * if there are no progress, hangcheck score for that ring is increased.
1953 * Further, acthd is inspected to see if the ring is stuck. On stuck case
1954 * we kick the ring. If we see no progress on three subsequent calls
1955 * we assume chip is wedged and try to fix it by resetting the chip.
1957 static void i915_hangcheck_elapsed(unsigned long data
)
1959 struct drm_device
*dev
= (struct drm_device
*)data
;
1960 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1961 struct intel_ring_buffer
*ring
;
1963 int busy_count
= 0, rings_hung
= 0;
1964 bool stuck
[I915_NUM_RINGS
] = { 0 };
1970 if (!i915_enable_hangcheck
)
1973 for_each_ring(ring
, dev_priv
, i
) {
1977 semaphore_clear_deadlocks(dev_priv
);
1979 seqno
= ring
->get_seqno(ring
, false);
1980 acthd
= intel_ring_get_active_head(ring
);
1982 if (ring
->hangcheck
.seqno
== seqno
) {
1983 if (ring_idle(ring
, seqno
)) {
1984 if (waitqueue_active(&ring
->irq_queue
)) {
1985 /* Issue a wake-up to catch stuck h/w. */
1986 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1988 wake_up_all(&ring
->irq_queue
);
1989 ring
->hangcheck
.score
+= HUNG
;
1993 /* We always increment the hangcheck score
1994 * if the ring is busy and still processing
1995 * the same request, so that no single request
1996 * can run indefinitely (such as a chain of
1997 * batches). The only time we do not increment
1998 * the hangcheck score on this ring, if this
1999 * ring is in a legitimate wait for another
2000 * ring. In that case the waiting ring is a
2001 * victim and we want to be sure we catch the
2002 * right culprit. Then every time we do kick
2003 * the ring, add a small increment to the
2004 * score so that we can catch a batch that is
2005 * being repeatedly kicked and so responsible
2006 * for stalling the machine.
2008 ring
->hangcheck
.action
= ring_stuck(ring
,
2011 switch (ring
->hangcheck
.action
) {
2012 case HANGCHECK_WAIT
:
2014 case HANGCHECK_ACTIVE
:
2015 ring
->hangcheck
.score
+= BUSY
;
2017 case HANGCHECK_KICK
:
2018 ring
->hangcheck
.score
+= KICK
;
2020 case HANGCHECK_HUNG
:
2021 ring
->hangcheck
.score
+= HUNG
;
2027 /* Gradually reduce the count so that we catch DoS
2028 * attempts across multiple batches.
2030 if (ring
->hangcheck
.score
> 0)
2031 ring
->hangcheck
.score
--;
2034 ring
->hangcheck
.seqno
= seqno
;
2035 ring
->hangcheck
.acthd
= acthd
;
2039 for_each_ring(ring
, dev_priv
, i
) {
2040 if (ring
->hangcheck
.score
> FIRE
) {
2041 DRM_INFO("%s on %s\n",
2042 stuck
[i
] ? "stuck" : "no progress",
2049 return i915_handle_error(dev
, true);
2052 /* Reset timer case chip hangs without another request
2054 i915_queue_hangcheck(dev
);
2057 void i915_queue_hangcheck(struct drm_device
*dev
)
2059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2060 if (!i915_enable_hangcheck
)
2063 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2064 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2067 static void ibx_irq_preinstall(struct drm_device
*dev
)
2069 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2071 if (HAS_PCH_NOP(dev
))
2074 /* south display irq */
2075 I915_WRITE(SDEIMR
, 0xffffffff);
2077 * SDEIER is also touched by the interrupt handler to work around missed
2078 * PCH interrupts. Hence we can't update it after the interrupt handler
2079 * is enabled - instead we unconditionally enable all PCH interrupt
2080 * sources here, but then only unmask them as needed with SDEIMR.
2082 I915_WRITE(SDEIER
, 0xffffffff);
2083 POSTING_READ(SDEIER
);
2086 static void gen5_gt_irq_preinstall(struct drm_device
*dev
)
2088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2091 I915_WRITE(GTIMR
, 0xffffffff);
2092 I915_WRITE(GTIER
, 0x0);
2093 POSTING_READ(GTIER
);
2095 if (INTEL_INFO(dev
)->gen
>= 6) {
2097 I915_WRITE(GEN6_PMIMR
, 0xffffffff);
2098 I915_WRITE(GEN6_PMIER
, 0x0);
2099 POSTING_READ(GEN6_PMIER
);
2105 static void ironlake_irq_preinstall(struct drm_device
*dev
)
2107 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2109 atomic_set(&dev_priv
->irq_received
, 0);
2111 I915_WRITE(HWSTAM
, 0xeffe);
2113 I915_WRITE(DEIMR
, 0xffffffff);
2114 I915_WRITE(DEIER
, 0x0);
2115 POSTING_READ(DEIER
);
2117 gen5_gt_irq_preinstall(dev
);
2119 ibx_irq_preinstall(dev
);
2122 static void valleyview_irq_preinstall(struct drm_device
*dev
)
2124 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2127 atomic_set(&dev_priv
->irq_received
, 0);
2130 I915_WRITE(VLV_IMR
, 0);
2131 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
2132 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
2133 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
2136 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2137 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2139 gen5_gt_irq_preinstall(dev
);
2141 I915_WRITE(DPINVGTT
, 0xff);
2143 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2144 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2146 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2147 I915_WRITE(VLV_IIR
, 0xffffffff);
2148 I915_WRITE(VLV_IMR
, 0xffffffff);
2149 I915_WRITE(VLV_IER
, 0x0);
2150 POSTING_READ(VLV_IER
);
2153 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
2155 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2156 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2157 struct intel_encoder
*intel_encoder
;
2158 u32 hotplug_irqs
, hotplug
, enabled_irqs
= 0;
2160 if (HAS_PCH_IBX(dev
)) {
2161 hotplug_irqs
= SDE_HOTPLUG_MASK
;
2162 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2163 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2164 enabled_irqs
|= hpd_ibx
[intel_encoder
->hpd_pin
];
2166 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
2167 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2168 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2169 enabled_irqs
|= hpd_cpt
[intel_encoder
->hpd_pin
];
2172 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
2175 * Enable digital hotplug on the PCH, and configure the DP short pulse
2176 * duration to 2ms (which is the minimum in the Display Port spec)
2178 * This register is the same on all known PCH chips.
2180 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
2181 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
2182 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
2183 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
2184 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
2185 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
2188 static void ibx_irq_postinstall(struct drm_device
*dev
)
2190 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2193 if (HAS_PCH_NOP(dev
))
2196 if (HAS_PCH_IBX(dev
)) {
2197 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_TRANSB_FIFO_UNDER
|
2198 SDE_TRANSA_FIFO_UNDER
| SDE_POISON
;
2200 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
| SDE_ERROR_CPT
;
2202 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2205 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2206 I915_WRITE(SDEIMR
, ~mask
);
2209 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
2211 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2212 u32 pm_irqs
, gt_irqs
;
2214 pm_irqs
= gt_irqs
= 0;
2216 dev_priv
->gt_irq_mask
= ~0;
2217 if (HAS_L3_GPU_CACHE(dev
)) {
2218 /* L3 parity interrupt is always unmasked. */
2219 dev_priv
->gt_irq_mask
= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2220 gt_irqs
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2223 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
2225 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
2226 ILK_BSD_USER_INTERRUPT
;
2228 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
2231 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2232 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2233 I915_WRITE(GTIER
, gt_irqs
);
2234 POSTING_READ(GTIER
);
2236 if (INTEL_INFO(dev
)->gen
>= 6) {
2237 pm_irqs
|= GEN6_PM_RPS_EVENTS
;
2240 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
2242 dev_priv
->pm_irq_mask
= 0xffffffff;
2243 I915_WRITE(GEN6_PMIIR
, I915_READ(GEN6_PMIIR
));
2244 I915_WRITE(GEN6_PMIMR
, dev_priv
->pm_irq_mask
);
2245 I915_WRITE(GEN6_PMIER
, pm_irqs
);
2246 POSTING_READ(GEN6_PMIER
);
2250 static int ironlake_irq_postinstall(struct drm_device
*dev
)
2252 unsigned long irqflags
;
2253 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2254 u32 display_mask
, extra_mask
;
2256 if (INTEL_INFO(dev
)->gen
>= 7) {
2257 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
2258 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
2259 DE_PLANEB_FLIP_DONE_IVB
|
2260 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
|
2262 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
2263 DE_PIPEA_VBLANK_IVB
);
2265 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2267 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
2268 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
2269 DE_AUX_CHANNEL_A
| DE_PIPEB_FIFO_UNDERRUN
|
2270 DE_PIPEA_FIFO_UNDERRUN
| DE_POISON
);
2271 extra_mask
= DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
;
2274 dev_priv
->irq_mask
= ~display_mask
;
2276 /* should always can generate irq */
2277 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2278 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2279 I915_WRITE(DEIER
, display_mask
| extra_mask
);
2280 POSTING_READ(DEIER
);
2282 gen5_gt_irq_postinstall(dev
);
2284 ibx_irq_postinstall(dev
);
2286 if (IS_IRONLAKE_M(dev
)) {
2287 /* Enable PCU event interrupts
2289 * spinlocking not required here for correctness since interrupt
2290 * setup is guaranteed to run in single-threaded context. But we
2291 * need it to make the assert_spin_locked happy. */
2292 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2293 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
2294 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2300 static int valleyview_irq_postinstall(struct drm_device
*dev
)
2302 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2304 u32 pipestat_enable
= PLANE_FLIP_DONE_INT_EN_VLV
;
2305 unsigned long irqflags
;
2307 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
;
2308 enable_mask
|= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2309 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2310 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2311 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2314 *Leave vblank interrupts masked initially. enable/disable will
2315 * toggle them based on usage.
2317 dev_priv
->irq_mask
= (~enable_mask
) |
2318 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2319 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2321 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2322 POSTING_READ(PORT_HOTPLUG_EN
);
2324 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
2325 I915_WRITE(VLV_IER
, enable_mask
);
2326 I915_WRITE(VLV_IIR
, 0xffffffff);
2327 I915_WRITE(PIPESTAT(0), 0xffff);
2328 I915_WRITE(PIPESTAT(1), 0xffff);
2329 POSTING_READ(VLV_IER
);
2331 /* Interrupt setup is already guaranteed to be single-threaded, this is
2332 * just to make the assert_spin_locked check happy. */
2333 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2334 i915_enable_pipestat(dev_priv
, 0, pipestat_enable
);
2335 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2336 i915_enable_pipestat(dev_priv
, 1, pipestat_enable
);
2337 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2339 I915_WRITE(VLV_IIR
, 0xffffffff);
2340 I915_WRITE(VLV_IIR
, 0xffffffff);
2342 gen5_gt_irq_postinstall(dev
);
2344 /* ack & enable invalid PTE error interrupts */
2345 #if 0 /* FIXME: add support to irq handler for checking these bits */
2346 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
2347 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
2350 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
2355 static void valleyview_irq_uninstall(struct drm_device
*dev
)
2357 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2363 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2366 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2368 I915_WRITE(HWSTAM
, 0xffffffff);
2369 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2370 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2372 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2373 I915_WRITE(VLV_IIR
, 0xffffffff);
2374 I915_WRITE(VLV_IMR
, 0xffffffff);
2375 I915_WRITE(VLV_IER
, 0x0);
2376 POSTING_READ(VLV_IER
);
2379 static void ironlake_irq_uninstall(struct drm_device
*dev
)
2381 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2386 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2388 I915_WRITE(HWSTAM
, 0xffffffff);
2390 I915_WRITE(DEIMR
, 0xffffffff);
2391 I915_WRITE(DEIER
, 0x0);
2392 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2394 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2396 I915_WRITE(GTIMR
, 0xffffffff);
2397 I915_WRITE(GTIER
, 0x0);
2398 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2400 if (HAS_PCH_NOP(dev
))
2403 I915_WRITE(SDEIMR
, 0xffffffff);
2404 I915_WRITE(SDEIER
, 0x0);
2405 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2406 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
2407 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2410 static void i8xx_irq_preinstall(struct drm_device
* dev
)
2412 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2415 atomic_set(&dev_priv
->irq_received
, 0);
2418 I915_WRITE(PIPESTAT(pipe
), 0);
2419 I915_WRITE16(IMR
, 0xffff);
2420 I915_WRITE16(IER
, 0x0);
2421 POSTING_READ16(IER
);
2424 static int i8xx_irq_postinstall(struct drm_device
*dev
)
2426 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2429 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2431 /* Unmask the interrupts that we always want on. */
2432 dev_priv
->irq_mask
=
2433 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2434 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2435 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2436 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2437 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2438 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
2441 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2442 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2443 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2444 I915_USER_INTERRUPT
);
2445 POSTING_READ16(IER
);
2451 * Returns true when a page flip has completed.
2453 static bool i8xx_handle_vblank(struct drm_device
*dev
,
2456 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2457 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(pipe
);
2459 if (!drm_handle_vblank(dev
, pipe
))
2462 if ((iir
& flip_pending
) == 0)
2465 intel_prepare_page_flip(dev
, pipe
);
2467 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2468 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2469 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2470 * the flip is completed (no longer pending). Since this doesn't raise
2471 * an interrupt per se, we watch for the change at vblank.
2473 if (I915_READ16(ISR
) & flip_pending
)
2476 intel_finish_page_flip(dev
, pipe
);
2481 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
2483 struct drm_device
*dev
= (struct drm_device
*) arg
;
2484 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2487 unsigned long irqflags
;
2490 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2491 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2493 atomic_inc(&dev_priv
->irq_received
);
2495 iir
= I915_READ16(IIR
);
2499 while (iir
& ~flip_mask
) {
2500 /* Can't rely on pipestat interrupt bit in iir as it might
2501 * have been cleared after the pipestat interrupt was received.
2502 * It doesn't set the bit in iir again, but it still produces
2503 * interrupts (for non-MSI).
2505 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2506 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2507 i915_handle_error(dev
, false);
2509 for_each_pipe(pipe
) {
2510 int reg
= PIPESTAT(pipe
);
2511 pipe_stats
[pipe
] = I915_READ(reg
);
2514 * Clear the PIPE*STAT regs before the IIR
2516 if (pipe_stats
[pipe
] & 0x8000ffff) {
2517 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2518 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2520 I915_WRITE(reg
, pipe_stats
[pipe
]);
2523 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2525 I915_WRITE16(IIR
, iir
& ~flip_mask
);
2526 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
2528 i915_update_dri1_breadcrumb(dev
);
2530 if (iir
& I915_USER_INTERRUPT
)
2531 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2533 if (pipe_stats
[0] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2534 i8xx_handle_vblank(dev
, 0, iir
))
2535 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(0);
2537 if (pipe_stats
[1] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2538 i8xx_handle_vblank(dev
, 1, iir
))
2539 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(1);
2547 static void i8xx_irq_uninstall(struct drm_device
* dev
)
2549 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2552 for_each_pipe(pipe
) {
2553 /* Clear enable bits; then clear status bits */
2554 I915_WRITE(PIPESTAT(pipe
), 0);
2555 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2557 I915_WRITE16(IMR
, 0xffff);
2558 I915_WRITE16(IER
, 0x0);
2559 I915_WRITE16(IIR
, I915_READ16(IIR
));
2562 static void i915_irq_preinstall(struct drm_device
* dev
)
2564 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2567 atomic_set(&dev_priv
->irq_received
, 0);
2569 if (I915_HAS_HOTPLUG(dev
)) {
2570 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2571 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2574 I915_WRITE16(HWSTAM
, 0xeffe);
2576 I915_WRITE(PIPESTAT(pipe
), 0);
2577 I915_WRITE(IMR
, 0xffffffff);
2578 I915_WRITE(IER
, 0x0);
2582 static int i915_irq_postinstall(struct drm_device
*dev
)
2584 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2587 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2589 /* Unmask the interrupts that we always want on. */
2590 dev_priv
->irq_mask
=
2591 ~(I915_ASLE_INTERRUPT
|
2592 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2593 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2594 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2595 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2596 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2599 I915_ASLE_INTERRUPT
|
2600 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2601 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2602 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2603 I915_USER_INTERRUPT
;
2605 if (I915_HAS_HOTPLUG(dev
)) {
2606 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2607 POSTING_READ(PORT_HOTPLUG_EN
);
2609 /* Enable in IER... */
2610 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
2611 /* and unmask in IMR */
2612 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
2615 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2616 I915_WRITE(IER
, enable_mask
);
2619 i915_enable_asle_pipestat(dev
);
2625 * Returns true when a page flip has completed.
2627 static bool i915_handle_vblank(struct drm_device
*dev
,
2628 int plane
, int pipe
, u32 iir
)
2630 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2631 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
2633 if (!drm_handle_vblank(dev
, pipe
))
2636 if ((iir
& flip_pending
) == 0)
2639 intel_prepare_page_flip(dev
, plane
);
2641 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2642 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2643 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2644 * the flip is completed (no longer pending). Since this doesn't raise
2645 * an interrupt per se, we watch for the change at vblank.
2647 if (I915_READ(ISR
) & flip_pending
)
2650 intel_finish_page_flip(dev
, pipe
);
2655 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
2657 struct drm_device
*dev
= (struct drm_device
*) arg
;
2658 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2659 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
2660 unsigned long irqflags
;
2662 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2663 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2664 int pipe
, ret
= IRQ_NONE
;
2666 atomic_inc(&dev_priv
->irq_received
);
2668 iir
= I915_READ(IIR
);
2670 bool irq_received
= (iir
& ~flip_mask
) != 0;
2671 bool blc_event
= false;
2673 /* Can't rely on pipestat interrupt bit in iir as it might
2674 * have been cleared after the pipestat interrupt was received.
2675 * It doesn't set the bit in iir again, but it still produces
2676 * interrupts (for non-MSI).
2678 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2679 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2680 i915_handle_error(dev
, false);
2682 for_each_pipe(pipe
) {
2683 int reg
= PIPESTAT(pipe
);
2684 pipe_stats
[pipe
] = I915_READ(reg
);
2686 /* Clear the PIPE*STAT regs before the IIR */
2687 if (pipe_stats
[pipe
] & 0x8000ffff) {
2688 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2689 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2691 I915_WRITE(reg
, pipe_stats
[pipe
]);
2692 irq_received
= true;
2695 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2700 /* Consume port. Then clear IIR or we'll miss events */
2701 if ((I915_HAS_HOTPLUG(dev
)) &&
2702 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
2703 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2704 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
2706 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2709 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
2711 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2712 POSTING_READ(PORT_HOTPLUG_STAT
);
2715 I915_WRITE(IIR
, iir
& ~flip_mask
);
2716 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2718 if (iir
& I915_USER_INTERRUPT
)
2719 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2721 for_each_pipe(pipe
) {
2726 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2727 i915_handle_vblank(dev
, plane
, pipe
, iir
))
2728 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
2730 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2734 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2735 intel_opregion_asle_intr(dev
);
2737 /* With MSI, interrupts are only generated when iir
2738 * transitions from zero to nonzero. If another bit got
2739 * set while we were handling the existing iir bits, then
2740 * we would never get another interrupt.
2742 * This is fine on non-MSI as well, as if we hit this path
2743 * we avoid exiting the interrupt handler only to generate
2746 * Note that for MSI this could cause a stray interrupt report
2747 * if an interrupt landed in the time between writing IIR and
2748 * the posting read. This should be rare enough to never
2749 * trigger the 99% of 100,000 interrupts test for disabling
2754 } while (iir
& ~flip_mask
);
2756 i915_update_dri1_breadcrumb(dev
);
2761 static void i915_irq_uninstall(struct drm_device
* dev
)
2763 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2766 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2768 if (I915_HAS_HOTPLUG(dev
)) {
2769 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2770 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2773 I915_WRITE16(HWSTAM
, 0xffff);
2774 for_each_pipe(pipe
) {
2775 /* Clear enable bits; then clear status bits */
2776 I915_WRITE(PIPESTAT(pipe
), 0);
2777 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2779 I915_WRITE(IMR
, 0xffffffff);
2780 I915_WRITE(IER
, 0x0);
2782 I915_WRITE(IIR
, I915_READ(IIR
));
2785 static void i965_irq_preinstall(struct drm_device
* dev
)
2787 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2790 atomic_set(&dev_priv
->irq_received
, 0);
2792 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2793 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2795 I915_WRITE(HWSTAM
, 0xeffe);
2797 I915_WRITE(PIPESTAT(pipe
), 0);
2798 I915_WRITE(IMR
, 0xffffffff);
2799 I915_WRITE(IER
, 0x0);
2803 static int i965_irq_postinstall(struct drm_device
*dev
)
2805 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2808 unsigned long irqflags
;
2810 /* Unmask the interrupts that we always want on. */
2811 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
2812 I915_DISPLAY_PORT_INTERRUPT
|
2813 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2814 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2815 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2816 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2817 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2819 enable_mask
= ~dev_priv
->irq_mask
;
2820 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2821 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
2822 enable_mask
|= I915_USER_INTERRUPT
;
2825 enable_mask
|= I915_BSD_USER_INTERRUPT
;
2827 /* Interrupt setup is already guaranteed to be single-threaded, this is
2828 * just to make the assert_spin_locked check happy. */
2829 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2830 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2831 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2834 * Enable some error detection, note the instruction error mask
2835 * bit is reserved, so we leave it masked.
2838 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
2839 GM45_ERROR_MEM_PRIV
|
2840 GM45_ERROR_CP_PRIV
|
2841 I915_ERROR_MEMORY_REFRESH
);
2843 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
2844 I915_ERROR_MEMORY_REFRESH
);
2846 I915_WRITE(EMR
, error_mask
);
2848 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2849 I915_WRITE(IER
, enable_mask
);
2852 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2853 POSTING_READ(PORT_HOTPLUG_EN
);
2855 i915_enable_asle_pipestat(dev
);
2860 static void i915_hpd_irq_setup(struct drm_device
*dev
)
2862 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2863 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2864 struct intel_encoder
*intel_encoder
;
2867 assert_spin_locked(&dev_priv
->irq_lock
);
2869 if (I915_HAS_HOTPLUG(dev
)) {
2870 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
2871 hotplug_en
&= ~HOTPLUG_INT_EN_MASK
;
2872 /* Note HDMI and DP share hotplug bits */
2873 /* enable bits are the same for all generations */
2874 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2875 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2876 hotplug_en
|= hpd_mask_i915
[intel_encoder
->hpd_pin
];
2877 /* Programming the CRT detection parameters tends
2878 to generate a spurious hotplug event about three
2879 seconds later. So just do it once.
2882 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
2883 hotplug_en
&= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
;
2884 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
2886 /* Ignore TV since it's buggy */
2887 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
2891 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
2893 struct drm_device
*dev
= (struct drm_device
*) arg
;
2894 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2896 u32 pipe_stats
[I915_MAX_PIPES
];
2897 unsigned long irqflags
;
2899 int ret
= IRQ_NONE
, pipe
;
2901 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2902 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2904 atomic_inc(&dev_priv
->irq_received
);
2906 iir
= I915_READ(IIR
);
2909 bool blc_event
= false;
2911 irq_received
= (iir
& ~flip_mask
) != 0;
2913 /* Can't rely on pipestat interrupt bit in iir as it might
2914 * have been cleared after the pipestat interrupt was received.
2915 * It doesn't set the bit in iir again, but it still produces
2916 * interrupts (for non-MSI).
2918 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2919 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2920 i915_handle_error(dev
, false);
2922 for_each_pipe(pipe
) {
2923 int reg
= PIPESTAT(pipe
);
2924 pipe_stats
[pipe
] = I915_READ(reg
);
2927 * Clear the PIPE*STAT regs before the IIR
2929 if (pipe_stats
[pipe
] & 0x8000ffff) {
2930 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2931 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2933 I915_WRITE(reg
, pipe_stats
[pipe
]);
2937 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2944 /* Consume port. Then clear IIR or we'll miss events */
2945 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
2946 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2947 u32 hotplug_trigger
= hotplug_status
& (IS_G4X(dev
) ?
2948 HOTPLUG_INT_STATUS_G4X
:
2949 HOTPLUG_INT_STATUS_I915
);
2951 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2954 intel_hpd_irq_handler(dev
, hotplug_trigger
,
2955 IS_G4X(dev
) ? hpd_status_gen4
: hpd_status_i915
);
2957 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2958 I915_READ(PORT_HOTPLUG_STAT
);
2961 I915_WRITE(IIR
, iir
& ~flip_mask
);
2962 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2964 if (iir
& I915_USER_INTERRUPT
)
2965 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2966 if (iir
& I915_BSD_USER_INTERRUPT
)
2967 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
2969 for_each_pipe(pipe
) {
2970 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
2971 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
2972 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
2974 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2979 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2980 intel_opregion_asle_intr(dev
);
2982 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
2983 gmbus_irq_handler(dev
);
2985 /* With MSI, interrupts are only generated when iir
2986 * transitions from zero to nonzero. If another bit got
2987 * set while we were handling the existing iir bits, then
2988 * we would never get another interrupt.
2990 * This is fine on non-MSI as well, as if we hit this path
2991 * we avoid exiting the interrupt handler only to generate
2994 * Note that for MSI this could cause a stray interrupt report
2995 * if an interrupt landed in the time between writing IIR and
2996 * the posting read. This should be rare enough to never
2997 * trigger the 99% of 100,000 interrupts test for disabling
3003 i915_update_dri1_breadcrumb(dev
);
3008 static void i965_irq_uninstall(struct drm_device
* dev
)
3010 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3016 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
3018 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3019 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3021 I915_WRITE(HWSTAM
, 0xffffffff);
3023 I915_WRITE(PIPESTAT(pipe
), 0);
3024 I915_WRITE(IMR
, 0xffffffff);
3025 I915_WRITE(IER
, 0x0);
3028 I915_WRITE(PIPESTAT(pipe
),
3029 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
3030 I915_WRITE(IIR
, I915_READ(IIR
));
3033 static void i915_reenable_hotplug_timer_func(unsigned long data
)
3035 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*)data
;
3036 struct drm_device
*dev
= dev_priv
->dev
;
3037 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3038 unsigned long irqflags
;
3041 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3042 for (i
= (HPD_NONE
+ 1); i
< HPD_NUM_PINS
; i
++) {
3043 struct drm_connector
*connector
;
3045 if (dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_DISABLED
)
3048 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3050 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3051 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3053 if (intel_connector
->encoder
->hpd_pin
== i
) {
3054 if (connector
->polled
!= intel_connector
->polled
)
3055 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3056 drm_get_connector_name(connector
));
3057 connector
->polled
= intel_connector
->polled
;
3058 if (!connector
->polled
)
3059 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3063 if (dev_priv
->display
.hpd_irq_setup
)
3064 dev_priv
->display
.hpd_irq_setup(dev
);
3065 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3068 void intel_irq_init(struct drm_device
*dev
)
3070 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3072 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
3073 INIT_WORK(&dev_priv
->gpu_error
.work
, i915_error_work_func
);
3074 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
3075 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
3077 setup_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
3078 i915_hangcheck_elapsed
,
3079 (unsigned long) dev
);
3080 setup_timer(&dev_priv
->hotplug_reenable_timer
, i915_reenable_hotplug_timer_func
,
3081 (unsigned long) dev_priv
);
3083 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
3085 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
3086 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
3087 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
3088 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
3089 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
3092 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3093 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
3095 dev
->driver
->get_vblank_timestamp
= NULL
;
3096 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
3098 if (IS_VALLEYVIEW(dev
)) {
3099 dev
->driver
->irq_handler
= valleyview_irq_handler
;
3100 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
3101 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
3102 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
3103 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
3104 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
3105 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3106 } else if (HAS_PCH_SPLIT(dev
)) {
3107 dev
->driver
->irq_handler
= ironlake_irq_handler
;
3108 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
3109 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
3110 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
3111 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
3112 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
3113 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
3115 if (INTEL_INFO(dev
)->gen
== 2) {
3116 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
3117 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
3118 dev
->driver
->irq_handler
= i8xx_irq_handler
;
3119 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
3120 } else if (INTEL_INFO(dev
)->gen
== 3) {
3121 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
3122 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
3123 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
3124 dev
->driver
->irq_handler
= i915_irq_handler
;
3125 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3127 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
3128 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
3129 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
3130 dev
->driver
->irq_handler
= i965_irq_handler
;
3131 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3133 dev
->driver
->enable_vblank
= i915_enable_vblank
;
3134 dev
->driver
->disable_vblank
= i915_disable_vblank
;
3138 void intel_hpd_init(struct drm_device
*dev
)
3140 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3141 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3142 struct drm_connector
*connector
;
3143 unsigned long irqflags
;
3146 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
3147 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
3148 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3150 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3151 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3152 connector
->polled
= intel_connector
->polled
;
3153 if (!connector
->polled
&& I915_HAS_HOTPLUG(dev
) && intel_connector
->encoder
->hpd_pin
> HPD_NONE
)
3154 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3157 /* Interrupt setup is already guaranteed to be single-threaded, this is
3158 * just to make the assert_spin_locked checks happy. */
3159 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3160 if (dev_priv
->display
.hpd_irq_setup
)
3161 dev_priv
->display
.hpd_irq_setup(dev
);
3162 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3165 /* Disable interrupts so we can allow Package C8+. */
3166 void hsw_pc8_disable_interrupts(struct drm_device
*dev
)
3168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3169 unsigned long irqflags
;
3171 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3173 dev_priv
->pc8
.regsave
.deimr
= I915_READ(DEIMR
);
3174 dev_priv
->pc8
.regsave
.sdeimr
= I915_READ(SDEIMR
);
3175 dev_priv
->pc8
.regsave
.gtimr
= I915_READ(GTIMR
);
3176 dev_priv
->pc8
.regsave
.gtier
= I915_READ(GTIER
);
3177 dev_priv
->pc8
.regsave
.gen6_pmimr
= I915_READ(GEN6_PMIMR
);
3179 ironlake_disable_display_irq(dev_priv
, ~DE_PCH_EVENT_IVB
);
3180 ibx_disable_display_interrupt(dev_priv
, ~SDE_HOTPLUG_MASK_CPT
);
3181 ilk_disable_gt_irq(dev_priv
, 0xffffffff);
3182 snb_disable_pm_irq(dev_priv
, 0xffffffff);
3184 dev_priv
->pc8
.irqs_disabled
= true;
3186 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3189 /* Restore interrupts so we can recover from Package C8+. */
3190 void hsw_pc8_restore_interrupts(struct drm_device
*dev
)
3192 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3193 unsigned long irqflags
;
3194 uint32_t val
, expected
;
3196 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3198 val
= I915_READ(DEIMR
);
3199 expected
= ~DE_PCH_EVENT_IVB
;
3200 WARN(val
!= expected
, "DEIMR is 0x%08x, not 0x%08x\n", val
, expected
);
3202 val
= I915_READ(SDEIMR
) & ~SDE_HOTPLUG_MASK_CPT
;
3203 expected
= ~SDE_HOTPLUG_MASK_CPT
;
3204 WARN(val
!= expected
, "SDEIMR non-HPD bits are 0x%08x, not 0x%08x\n",
3207 val
= I915_READ(GTIMR
);
3208 expected
= 0xffffffff;
3209 WARN(val
!= expected
, "GTIMR is 0x%08x, not 0x%08x\n", val
, expected
);
3211 val
= I915_READ(GEN6_PMIMR
);
3212 expected
= 0xffffffff;
3213 WARN(val
!= expected
, "GEN6_PMIMR is 0x%08x, not 0x%08x\n", val
,
3216 dev_priv
->pc8
.irqs_disabled
= false;
3218 ironlake_enable_display_irq(dev_priv
, ~dev_priv
->pc8
.regsave
.deimr
);
3219 ibx_enable_display_interrupt(dev_priv
,
3220 ~dev_priv
->pc8
.regsave
.sdeimr
&
3221 ~SDE_HOTPLUG_MASK_CPT
);
3222 ilk_enable_gt_irq(dev_priv
, ~dev_priv
->pc8
.regsave
.gtimr
);
3223 snb_enable_pm_irq(dev_priv
, ~dev_priv
->pc8
.regsave
.gen6_pmimr
);
3224 I915_WRITE(GTIER
, dev_priv
->pc8
.regsave
.gtier
);
3226 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);