2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <linux/console.h>
26 #include <linux/vgaarb.h>
27 #include <linux/vga_switcheroo.h>
31 #define GEN_DEFAULT_PIPEOFFSETS \
32 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
33 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
34 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
35 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
36 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
38 #define GEN_CHV_PIPEOFFSETS \
39 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
40 CHV_PIPE_C_OFFSET }, \
41 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
42 CHV_TRANSCODER_C_OFFSET, }, \
43 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
44 CHV_PALETTE_C_OFFSET }
46 #define CURSOR_OFFSETS \
47 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
49 #define IVB_CURSOR_OFFSETS \
50 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
53 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
55 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
57 #define GEN2_FEATURES \
58 .gen = 2, .num_pipes = 1, \
59 .has_overlay = 1, .overlay_needs_physical = 1, \
60 .has_gmch_display = 1, \
61 .hws_needs_physical = 1, \
62 .ring_mask = RENDER_RING, \
63 GEN_DEFAULT_PIPEOFFSETS, \
66 static const struct intel_device_info intel_i830_info
= {
68 .is_mobile
= 1, .cursor_needs_physical
= 1,
69 .num_pipes
= 2, /* legal, last one wins */
72 static const struct intel_device_info intel_845g_info
= {
76 static const struct intel_device_info intel_i85x_info
= {
78 .is_i85x
= 1, .is_mobile
= 1,
79 .num_pipes
= 2, /* legal, last one wins */
80 .cursor_needs_physical
= 1,
84 static const struct intel_device_info intel_i865g_info
= {
88 #define GEN3_FEATURES \
89 .gen = 3, .num_pipes = 2, \
90 .has_gmch_display = 1, \
91 .ring_mask = RENDER_RING, \
92 GEN_DEFAULT_PIPEOFFSETS, \
95 static const struct intel_device_info intel_i915g_info
= {
97 .is_i915g
= 1, .cursor_needs_physical
= 1,
98 .has_overlay
= 1, .overlay_needs_physical
= 1,
99 .hws_needs_physical
= 1,
101 static const struct intel_device_info intel_i915gm_info
= {
104 .cursor_needs_physical
= 1,
105 .has_overlay
= 1, .overlay_needs_physical
= 1,
108 .hws_needs_physical
= 1,
110 static const struct intel_device_info intel_i945g_info
= {
112 .has_hotplug
= 1, .cursor_needs_physical
= 1,
113 .has_overlay
= 1, .overlay_needs_physical
= 1,
114 .hws_needs_physical
= 1,
116 static const struct intel_device_info intel_i945gm_info
= {
118 .is_i945gm
= 1, .is_mobile
= 1,
119 .has_hotplug
= 1, .cursor_needs_physical
= 1,
120 .has_overlay
= 1, .overlay_needs_physical
= 1,
123 .hws_needs_physical
= 1,
126 #define GEN4_FEATURES \
127 .gen = 4, .num_pipes = 2, \
129 .has_gmch_display = 1, \
130 .ring_mask = RENDER_RING, \
131 GEN_DEFAULT_PIPEOFFSETS, \
134 static const struct intel_device_info intel_i965g_info
= {
138 .hws_needs_physical
= 1,
141 static const struct intel_device_info intel_i965gm_info
= {
144 .is_mobile
= 1, .has_fbc
= 1,
147 .hws_needs_physical
= 1,
150 static const struct intel_device_info intel_g33_info
= {
157 static const struct intel_device_info intel_g45_info
= {
161 .ring_mask
= RENDER_RING
| BSD_RING
,
164 static const struct intel_device_info intel_gm45_info
= {
167 .is_mobile
= 1, .has_fbc
= 1,
170 .ring_mask
= RENDER_RING
| BSD_RING
,
173 static const struct intel_device_info intel_pineview_info
= {
175 .is_g33
= 1, .is_pineview
= 1, .is_mobile
= 1,
180 #define GEN5_FEATURES \
181 .gen = 5, .num_pipes = 2, \
183 .has_gmbus_irq = 1, \
184 .ring_mask = RENDER_RING | BSD_RING, \
185 GEN_DEFAULT_PIPEOFFSETS, \
188 static const struct intel_device_info intel_ironlake_d_info
= {
192 static const struct intel_device_info intel_ironlake_m_info
= {
197 #define GEN6_FEATURES \
198 .gen = 6, .num_pipes = 2, \
201 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
205 .has_gmbus_irq = 1, \
206 .has_hw_contexts = 1, \
207 GEN_DEFAULT_PIPEOFFSETS, \
210 static const struct intel_device_info intel_sandybridge_d_info
= {
214 static const struct intel_device_info intel_sandybridge_m_info
= {
219 #define GEN7_FEATURES \
220 .gen = 7, .num_pipes = 3, \
223 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
227 .has_gmbus_irq = 1, \
228 .has_hw_contexts = 1, \
229 GEN_DEFAULT_PIPEOFFSETS, \
232 static const struct intel_device_info intel_ivybridge_d_info
= {
238 static const struct intel_device_info intel_ivybridge_m_info
= {
245 static const struct intel_device_info intel_ivybridge_q_info
= {
248 .num_pipes
= 0, /* legal, last one wins */
252 #define VLV_FEATURES \
253 .gen = 7, .num_pipes = 2, \
255 .has_runtime_pm = 1, \
257 .has_gmbus_irq = 1, \
258 .has_hw_contexts = 1, \
259 .has_gmch_display = 1, \
261 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
262 .display_mmio_offset = VLV_DISPLAY_BASE, \
263 GEN_DEFAULT_PIPEOFFSETS, \
266 static const struct intel_device_info intel_valleyview_info
= {
271 #define HSW_FEATURES \
273 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
277 .has_resource_streamer = 1, \
279 .has_rc6p = 0 /* RC6p removed-by HSW */, \
282 static const struct intel_device_info intel_haswell_info
= {
288 #define BDW_FEATURES \
291 .has_logical_ring_contexts = 1
293 static const struct intel_device_info intel_broadwell_info
= {
299 static const struct intel_device_info intel_broadwell_gt3_info
= {
303 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
306 static const struct intel_device_info intel_cherryview_info
= {
307 .gen
= 8, .num_pipes
= 3,
309 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
313 .has_resource_streamer
= 1,
316 .has_hw_contexts
= 1,
317 .has_logical_ring_contexts
= 1,
318 .has_gmch_display
= 1,
319 .display_mmio_offset
= VLV_DISPLAY_BASE
,
325 static const struct intel_device_info intel_skylake_info
= {
333 static const struct intel_device_info intel_skylake_gt3_info
= {
339 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
342 static const struct intel_device_info intel_broxton_info
= {
346 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
354 .has_resource_streamer
= 1,
358 .has_hw_contexts
= 1,
359 .has_logical_ring_contexts
= 1,
361 GEN_DEFAULT_PIPEOFFSETS
,
366 static const struct intel_device_info intel_kabylake_info
= {
374 static const struct intel_device_info intel_kabylake_gt3_info
= {
380 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
384 * Make sure any device matches here are from most specific to most
385 * general. For example, since the Quanta match is based on the subsystem
386 * and subvendor IDs, we need it to come before the more general IVB
387 * PCI ID matches, otherwise we'll use the wrong info struct above.
389 static const struct pci_device_id pciidlist
[] = {
390 INTEL_I830_IDS(&intel_i830_info
),
391 INTEL_I845G_IDS(&intel_845g_info
),
392 INTEL_I85X_IDS(&intel_i85x_info
),
393 INTEL_I865G_IDS(&intel_i865g_info
),
394 INTEL_I915G_IDS(&intel_i915g_info
),
395 INTEL_I915GM_IDS(&intel_i915gm_info
),
396 INTEL_I945G_IDS(&intel_i945g_info
),
397 INTEL_I945GM_IDS(&intel_i945gm_info
),
398 INTEL_I965G_IDS(&intel_i965g_info
),
399 INTEL_G33_IDS(&intel_g33_info
),
400 INTEL_I965GM_IDS(&intel_i965gm_info
),
401 INTEL_GM45_IDS(&intel_gm45_info
),
402 INTEL_G45_IDS(&intel_g45_info
),
403 INTEL_PINEVIEW_IDS(&intel_pineview_info
),
404 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info
),
405 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info
),
406 INTEL_SNB_D_IDS(&intel_sandybridge_d_info
),
407 INTEL_SNB_M_IDS(&intel_sandybridge_m_info
),
408 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info
), /* must be first IVB */
409 INTEL_IVB_M_IDS(&intel_ivybridge_m_info
),
410 INTEL_IVB_D_IDS(&intel_ivybridge_d_info
),
411 INTEL_HSW_IDS(&intel_haswell_info
),
412 INTEL_VLV_IDS(&intel_valleyview_info
),
413 INTEL_BDW_GT12_IDS(&intel_broadwell_info
),
414 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info
),
415 INTEL_CHV_IDS(&intel_cherryview_info
),
416 INTEL_SKL_GT1_IDS(&intel_skylake_info
),
417 INTEL_SKL_GT2_IDS(&intel_skylake_info
),
418 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info
),
419 INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info
),
420 INTEL_BXT_IDS(&intel_broxton_info
),
421 INTEL_KBL_GT1_IDS(&intel_kabylake_info
),
422 INTEL_KBL_GT2_IDS(&intel_kabylake_info
),
423 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info
),
424 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info
),
427 MODULE_DEVICE_TABLE(pci
, pciidlist
);
429 extern int i915_driver_load(struct pci_dev
*pdev
,
430 const struct pci_device_id
*ent
);
432 static int i915_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
434 struct intel_device_info
*intel_info
=
435 (struct intel_device_info
*) ent
->driver_data
;
437 if (IS_PRELIMINARY_HW(intel_info
) && !i915
.preliminary_hw_support
) {
438 DRM_INFO("This hardware requires preliminary hardware support.\n"
439 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
443 /* Only bind to function 0 of the device. Early generations
444 * used function 1 as a placeholder for multi-head. This causes
445 * us confusion instead, especially on the systems where both
446 * functions have the same PCI-ID!
448 if (PCI_FUNC(pdev
->devfn
))
452 * apple-gmux is needed on dual GPU MacBook Pro
453 * to probe the panel if we're the inactive GPU.
455 if (vga_switcheroo_client_probe_defer(pdev
))
456 return -EPROBE_DEFER
;
458 return i915_driver_load(pdev
, ent
);
461 extern void i915_driver_unload(struct drm_device
*dev
);
463 static void i915_pci_remove(struct pci_dev
*pdev
)
465 struct drm_device
*dev
= pci_get_drvdata(pdev
);
467 i915_driver_unload(dev
);
471 extern const struct dev_pm_ops i915_pm_ops
;
473 static struct pci_driver i915_pci_driver
= {
475 .id_table
= pciidlist
,
476 .probe
= i915_pci_probe
,
477 .remove
= i915_pci_remove
,
478 .driver
.pm
= &i915_pm_ops
,
481 static int __init
i915_init(void)
486 * Enable KMS by default, unless explicitly overriden by
487 * either the i915.modeset prarameter or by the
488 * vga_text_mode_force boot option.
491 if (i915
.modeset
== 0)
494 if (vgacon_text_force() && i915
.modeset
== -1)
498 /* Silently fail loading to not upset userspace. */
499 DRM_DEBUG_DRIVER("KMS disabled.\n");
503 return pci_register_driver(&i915_pci_driver
);
506 static void __exit
i915_exit(void)
508 if (!i915_pci_driver
.driver
.owner
)
511 pci_unregister_driver(&i915_pci_driver
);
514 module_init(i915_init
);
515 module_exit(i915_exit
);
517 MODULE_AUTHOR("Tungsten Graphics, Inc.");
518 MODULE_AUTHOR("Intel Corporation");
520 MODULE_DESCRIPTION(DRIVER_DESC
);
521 MODULE_LICENSE("GPL and additional rights");