1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
31 * The Bridge device's PCI config space has information about the
32 * fb aperture size and the amount of pre-reserved memory.
33 * This is all handled in the intel-gtt.ko module. i915.ko only
34 * cares about the vga bit for the vga rbiter.
36 #define INTEL_GMCH_CTRL 0x52
37 #define INTEL_GMCH_VGA_DISABLE (1 << 1)
39 /* PCI config space */
41 #define HPLLCC 0xc0 /* 855 only */
42 #define GC_CLOCK_CONTROL_MASK (0xf << 0)
43 #define GC_CLOCK_133_200 (0 << 0)
44 #define GC_CLOCK_100_200 (1 << 0)
45 #define GC_CLOCK_100_133 (2 << 0)
46 #define GC_CLOCK_166_250 (3 << 0)
48 #define GCFGC 0xf0 /* 915+ only */
49 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
50 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
51 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
52 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
53 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
54 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
55 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
56 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
57 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
58 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
59 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
60 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
61 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
62 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
63 #define I945_GC_RENDER_CLOCK_MASK (7 << 0)
64 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
65 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
66 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
67 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
68 #define I915_GC_RENDER_CLOCK_MASK (7 << 0)
69 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
70 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
71 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
74 /* Graphics reset regs */
75 #define I965_GDRST 0xc0 /* PCI config register */
76 #define ILK_GDSR 0x2ca4 /* MCHBAR offset */
77 #define GRDOM_FULL (0<<2)
78 #define GRDOM_RENDER (1<<2)
79 #define GRDOM_MEDIA (3<<2)
81 #define GEN6_GDRST 0x941c
82 #define GEN6_GRDOM_FULL (1 << 0)
83 #define GEN6_GRDOM_RENDER (1 << 1)
84 #define GEN6_GRDOM_MEDIA (1 << 2)
85 #define GEN6_GRDOM_BLT (1 << 3)
89 #define VGA_ST01_MDA 0x3ba
90 #define VGA_ST01_CGA 0x3da
92 #define VGA_MSR_WRITE 0x3c2
93 #define VGA_MSR_READ 0x3cc
94 #define VGA_MSR_MEM_EN (1<<1)
95 #define VGA_MSR_CGA_MODE (1<<0)
97 #define VGA_SR_INDEX 0x3c4
98 #define VGA_SR_DATA 0x3c5
100 #define VGA_AR_INDEX 0x3c0
101 #define VGA_AR_VID_EN (1<<5)
102 #define VGA_AR_DATA_WRITE 0x3c0
103 #define VGA_AR_DATA_READ 0x3c1
105 #define VGA_GR_INDEX 0x3ce
106 #define VGA_GR_DATA 0x3cf
108 #define VGA_GR_MEM_READ_MODE_SHIFT 3
109 #define VGA_GR_MEM_READ_MODE_PLANE 1
111 #define VGA_GR_MEM_MODE_MASK 0xc
112 #define VGA_GR_MEM_MODE_SHIFT 2
113 #define VGA_GR_MEM_A0000_AFFFF 0
114 #define VGA_GR_MEM_A0000_BFFFF 1
115 #define VGA_GR_MEM_B0000_B7FFF 2
116 #define VGA_GR_MEM_B0000_BFFFF 3
118 #define VGA_DACMASK 0x3c6
119 #define VGA_DACRX 0x3c7
120 #define VGA_DACWX 0x3c8
121 #define VGA_DACDATA 0x3c9
123 #define VGA_CR_INDEX_MDA 0x3b4
124 #define VGA_CR_DATA_MDA 0x3b5
125 #define VGA_CR_INDEX_CGA 0x3d4
126 #define VGA_CR_DATA_CGA 0x3d5
129 * Memory interface instructions used by the kernel
131 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
133 #define MI_NOOP MI_INSTR(0, 0)
134 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
135 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
136 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
137 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
138 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
139 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
140 #define MI_FLUSH MI_INSTR(0x04, 0)
141 #define MI_READ_FLUSH (1 << 0)
142 #define MI_EXE_FLUSH (1 << 1)
143 #define MI_NO_WRITE_FLUSH (1 << 2)
144 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
145 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
146 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
147 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
148 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
149 #define MI_SUSPEND_FLUSH_EN (1<<0)
150 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
151 #define MI_OVERLAY_FLIP MI_INSTR(0x11,0)
152 #define MI_OVERLAY_CONTINUE (0x0<<21)
153 #define MI_OVERLAY_ON (0x1<<21)
154 #define MI_OVERLAY_OFF (0x2<<21)
155 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
156 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
157 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
158 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
159 #define MI_SET_CONTEXT MI_INSTR(0x18, 0)
160 #define MI_MM_SPACE_GTT (1<<8)
161 #define MI_MM_SPACE_PHYSICAL (0<<8)
162 #define MI_SAVE_EXT_STATE_EN (1<<3)
163 #define MI_RESTORE_EXT_STATE_EN (1<<2)
164 #define MI_FORCE_RESTORE (1<<1)
165 #define MI_RESTORE_INHIBIT (1<<0)
166 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
167 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
168 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
169 #define MI_STORE_DWORD_INDEX_SHIFT 2
170 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
171 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
172 * simply ignores the register load under certain conditions.
173 * - One can actually load arbitrary many arbitrary registers: Simply issue x
174 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
176 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
177 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
178 #define MI_INVALIDATE_TLB (1<<18)
179 #define MI_INVALIDATE_BSD (1<<7)
180 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
181 #define MI_BATCH_NON_SECURE (1)
182 #define MI_BATCH_NON_SECURE_I965 (1<<8)
183 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
184 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */
185 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
186 #define MI_SEMAPHORE_UPDATE (1<<21)
187 #define MI_SEMAPHORE_COMPARE (1<<20)
188 #define MI_SEMAPHORE_REGISTER (1<<18)
190 * 3D instructions used by the kernel
192 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
194 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
195 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
196 #define SC_UPDATE_SCISSOR (0x1<<1)
197 #define SC_ENABLE_MASK (0x1<<0)
198 #define SC_ENABLE (0x1<<0)
199 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
200 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
201 #define SCI_YMIN_MASK (0xffff<<16)
202 #define SCI_XMIN_MASK (0xffff<<0)
203 #define SCI_YMAX_MASK (0xffff<<16)
204 #define SCI_XMAX_MASK (0xffff<<0)
205 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
206 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
207 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
208 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
209 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
210 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
211 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
212 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
213 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
214 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
215 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
216 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
217 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
218 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
219 #define BLT_DEPTH_8 (0<<24)
220 #define BLT_DEPTH_16_565 (1<<24)
221 #define BLT_DEPTH_16_1555 (2<<24)
222 #define BLT_DEPTH_32 (3<<24)
223 #define BLT_ROP_GXCOPY (0xcc<<16)
224 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
225 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
226 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
227 #define ASYNC_FLIP (1<<22)
228 #define DISPLAY_PLANE_A (0<<20)
229 #define DISPLAY_PLANE_B (1<<20)
230 #define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
231 #define PIPE_CONTROL_QW_WRITE (1<<14)
232 #define PIPE_CONTROL_DEPTH_STALL (1<<13)
233 #define PIPE_CONTROL_WC_FLUSH (1<<12)
234 #define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */
235 #define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */
236 #define PIPE_CONTROL_ISP_DIS (1<<9)
237 #define PIPE_CONTROL_NOTIFY (1<<8)
238 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
239 #define PIPE_CONTROL_STALL_EN (1<<1) /* in addr word, Ironlake+ only */
245 #define DEBUG_RESET_I830 0x6070
246 #define DEBUG_RESET_FULL (1<<7)
247 #define DEBUG_RESET_RENDER (1<<8)
248 #define DEBUG_RESET_DISPLAY (1<<9)
254 #define FENCE_REG_830_0 0x2000
255 #define FENCE_REG_945_8 0x3000
256 #define I830_FENCE_START_MASK 0x07f80000
257 #define I830_FENCE_TILING_Y_SHIFT 12
258 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
259 #define I830_FENCE_PITCH_SHIFT 4
260 #define I830_FENCE_REG_VALID (1<<0)
261 #define I915_FENCE_MAX_PITCH_VAL 4
262 #define I830_FENCE_MAX_PITCH_VAL 6
263 #define I830_FENCE_MAX_SIZE_VAL (1<<8)
265 #define I915_FENCE_START_MASK 0x0ff00000
266 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
268 #define FENCE_REG_965_0 0x03000
269 #define I965_FENCE_PITCH_SHIFT 2
270 #define I965_FENCE_TILING_Y_SHIFT 1
271 #define I965_FENCE_REG_VALID (1<<0)
272 #define I965_FENCE_MAX_PITCH_VAL 0x0400
274 #define FENCE_REG_SANDYBRIDGE_0 0x100000
275 #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
278 * Instruction and interrupt control regs
280 #define PGTBL_ER 0x02024
281 #define RENDER_RING_BASE 0x02000
282 #define BSD_RING_BASE 0x04000
283 #define GEN6_BSD_RING_BASE 0x12000
284 #define BLT_RING_BASE 0x22000
285 #define RING_TAIL(base) ((base)+0x30)
286 #define RING_HEAD(base) ((base)+0x34)
287 #define RING_START(base) ((base)+0x38)
288 #define RING_CTL(base) ((base)+0x3c)
289 #define RING_SYNC_0(base) ((base)+0x40)
290 #define RING_SYNC_1(base) ((base)+0x44)
291 #define RING_MAX_IDLE(base) ((base)+0x54)
292 #define RING_HWS_PGA(base) ((base)+0x80)
293 #define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
294 #define RING_ACTHD(base) ((base)+0x74)
295 #define RING_NOPID(base) ((base)+0x94)
296 #define RING_IMR(base) ((base)+0xa8)
297 #define TAIL_ADDR 0x001FFFF8
298 #define HEAD_WRAP_COUNT 0xFFE00000
299 #define HEAD_WRAP_ONE 0x00200000
300 #define HEAD_ADDR 0x001FFFFC
301 #define RING_NR_PAGES 0x001FF000
302 #define RING_REPORT_MASK 0x00000006
303 #define RING_REPORT_64K 0x00000002
304 #define RING_REPORT_128K 0x00000004
305 #define RING_NO_REPORT 0x00000000
306 #define RING_VALID_MASK 0x00000001
307 #define RING_VALID 0x00000001
308 #define RING_INVALID 0x00000000
309 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
310 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
311 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
313 #define PRB0_TAIL 0x02030
314 #define PRB0_HEAD 0x02034
315 #define PRB0_START 0x02038
316 #define PRB0_CTL 0x0203c
317 #define PRB1_TAIL 0x02040 /* 915+ only */
318 #define PRB1_HEAD 0x02044 /* 915+ only */
319 #define PRB1_START 0x02048 /* 915+ only */
320 #define PRB1_CTL 0x0204c /* 915+ only */
322 #define IPEIR_I965 0x02064
323 #define IPEHR_I965 0x02068
324 #define INSTDONE_I965 0x0206c
325 #define INSTPS 0x02070 /* 965+ only */
326 #define INSTDONE1 0x0207c /* 965+ only */
327 #define ACTHD_I965 0x02074
328 #define HWS_PGA 0x02080
329 #define HWS_ADDRESS_MASK 0xfffff000
330 #define HWS_START_ADDRESS_SHIFT 4
331 #define PWRCTXA 0x2088 /* 965GM+ only */
332 #define PWRCTX_EN (1<<0)
333 #define IPEIR 0x02088
334 #define IPEHR 0x0208c
335 #define INSTDONE 0x02090
336 #define NOPID 0x02094
337 #define HWSTAM 0x02098
338 #define VCS_INSTDONE 0x1206C
339 #define VCS_IPEIR 0x12064
340 #define VCS_IPEHR 0x12068
341 #define VCS_ACTHD 0x12074
342 #define BCS_INSTDONE 0x2206C
343 #define BCS_IPEIR 0x22064
344 #define BCS_IPEHR 0x22068
345 #define BCS_ACTHD 0x22074
347 #define ERROR_GEN6 0x040a0
349 /* GM45+ chicken bits -- debug workaround bits that may be required
350 * for various sorts of correct behavior. The top 16 bits of each are
351 * the enables for writing to the corresponding low bit.
353 #define _3D_CHICKEN 0x02084
354 #define _3D_CHICKEN2 0x0208c
355 /* Disables pipelining of read flushes past the SF-WIZ interface.
356 * Required on all Ironlake steppings according to the B-Spec, but the
357 * particular danger of not doing so is not specified.
359 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
360 #define _3D_CHICKEN3 0x02090
362 #define MI_MODE 0x0209c
363 # define VS_TIMER_DISPATCH (1 << 6)
364 # define MI_FLUSH_ENABLE (1 << 11)
366 #define GFX_MODE 0x02520
367 #define GFX_RUN_LIST_ENABLE (1<<15)
368 #define GFX_TLB_INVALIDATE_ALWAYS (1<<13)
369 #define GFX_SURFACE_FAULT_ENABLE (1<<12)
370 #define GFX_REPLAY_MODE (1<<11)
371 #define GFX_PSMI_GRANULARITY (1<<10)
372 #define GFX_PPGTT_ENABLE (1<<9)
374 #define SCPD0 0x0209c /* 915+ only */
379 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
380 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
381 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
382 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
383 #define I915_HWB_OOM_INTERRUPT (1<<13)
384 #define I915_SYNC_STATUS_INTERRUPT (1<<12)
385 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
386 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
387 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
388 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
389 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
390 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
391 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
392 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
393 #define I915_DEBUG_INTERRUPT (1<<2)
394 #define I915_USER_INTERRUPT (1<<1)
395 #define I915_ASLE_INTERRUPT (1<<0)
396 #define I915_BSD_USER_INTERRUPT (1<<25)
400 #define GM45_ERROR_PAGE_TABLE (1<<5)
401 #define GM45_ERROR_MEM_PRIV (1<<4)
402 #define I915_ERROR_PAGE_TABLE (1<<4)
403 #define GM45_ERROR_CP_PRIV (1<<3)
404 #define I915_ERROR_MEMORY_REFRESH (1<<1)
405 #define I915_ERROR_INSTRUCTION (1<<0)
406 #define INSTPM 0x020c0
407 #define INSTPM_SELF_EN (1<<12) /* 915GM only */
408 #define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
409 will not assert AGPBUSY# and will only
410 be delivered when out of C3. */
411 #define ACTHD 0x020c8
412 #define FW_BLC 0x020d8
413 #define FW_BLC2 0x020dc
414 #define FW_BLC_SELF 0x020e0 /* 915+ only */
415 #define FW_BLC_SELF_EN_MASK (1<<31)
416 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
417 #define FW_BLC_SELF_EN (1<<15) /* 945 only */
418 #define MM_BURST_LENGTH 0x00700000
419 #define MM_FIFO_WATERMARK 0x0001F000
420 #define LM_BURST_LENGTH 0x00000700
421 #define LM_FIFO_WATERMARK 0x0000001F
422 #define MI_ARB_STATE 0x020e4 /* 915+ only */
423 #define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */
425 /* Make render/texture TLB fetches lower priorty than associated data
426 * fetches. This is not turned on by default
428 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
430 /* Isoch request wait on GTT enable (Display A/B/C streams).
431 * Make isoch requests stall on the TLB update. May cause
432 * display underruns (test mode only)
434 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
436 /* Block grant count for isoch requests when block count is
437 * set to a finite value.
439 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
440 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
441 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
442 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
443 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
445 /* Enable render writes to complete in C2/C3/C4 power states.
446 * If this isn't enabled, render writes are prevented in low
447 * power states. That seems bad to me.
449 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
451 /* This acknowledges an async flip immediately instead
452 * of waiting for 2TLB fetches.
454 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
456 /* Enables non-sequential data reads through arbiter
458 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
460 /* Disable FSB snooping of cacheable write cycles from binner/render
463 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
465 /* Arbiter time slice for non-isoch streams */
466 #define MI_ARB_TIME_SLICE_MASK (7 << 5)
467 #define MI_ARB_TIME_SLICE_1 (0 << 5)
468 #define MI_ARB_TIME_SLICE_2 (1 << 5)
469 #define MI_ARB_TIME_SLICE_4 (2 << 5)
470 #define MI_ARB_TIME_SLICE_6 (3 << 5)
471 #define MI_ARB_TIME_SLICE_8 (4 << 5)
472 #define MI_ARB_TIME_SLICE_10 (5 << 5)
473 #define MI_ARB_TIME_SLICE_14 (6 << 5)
474 #define MI_ARB_TIME_SLICE_16 (7 << 5)
476 /* Low priority grace period page size */
477 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
478 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
480 /* Disable display A/B trickle feed */
481 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
483 /* Set display plane priority */
484 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
485 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
487 #define CACHE_MODE_0 0x02120 /* 915+ only */
488 #define CM0_MASK_SHIFT 16
489 #define CM0_IZ_OPT_DISABLE (1<<6)
490 #define CM0_ZR_OPT_DISABLE (1<<5)
491 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
492 #define CM0_COLOR_EVICT_DISABLE (1<<3)
493 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
494 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
495 #define BB_ADDR 0x02140 /* 8 bytes */
496 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */
497 #define ECOSKPD 0x021d0
498 #define ECO_GATING_CX_ONLY (1<<3)
499 #define ECO_FLIP_DONE (1<<0)
501 /* GEN6 interrupt control */
502 #define GEN6_RENDER_HWSTAM 0x2098
503 #define GEN6_RENDER_IMR 0x20a8
504 #define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8)
505 #define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7)
506 #define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6)
507 #define GEN6_RENDER_L3_PARITY_ERROR (1 << 5)
508 #define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4)
509 #define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3)
510 #define GEN6_RENDER_SYNC_STATUS (1 << 2)
511 #define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1)
512 #define GEN6_RENDER_USER_INTERRUPT (1 << 0)
514 #define GEN6_BLITTER_HWSTAM 0x22098
515 #define GEN6_BLITTER_IMR 0x220a8
516 #define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26)
517 #define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25)
518 #define GEN6_BLITTER_SYNC_STATUS (1 << 24)
519 #define GEN6_BLITTER_USER_INTERRUPT (1 << 22)
521 #define GEN6_BLITTER_ECOSKPD 0x221d0
522 #define GEN6_BLITTER_LOCK_SHIFT 16
523 #define GEN6_BLITTER_FBC_NOTIFY (1<<3)
525 #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
526 #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16)
527 #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0)
528 #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0
529 #define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3)
531 #define GEN6_BSD_IMR 0x120a8
532 #define GEN6_BSD_USER_INTERRUPT (1 << 12)
534 #define GEN6_BSD_RNCID 0x12198
537 * Framebuffer compression (915+ only)
540 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
541 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
542 #define FBC_CONTROL 0x03208
543 #define FBC_CTL_EN (1<<31)
544 #define FBC_CTL_PERIODIC (1<<30)
545 #define FBC_CTL_INTERVAL_SHIFT (16)
546 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
547 #define FBC_CTL_C3_IDLE (1<<13)
548 #define FBC_CTL_STRIDE_SHIFT (5)
549 #define FBC_CTL_FENCENO (1<<0)
550 #define FBC_COMMAND 0x0320c
551 #define FBC_CMD_COMPRESS (1<<0)
552 #define FBC_STATUS 0x03210
553 #define FBC_STAT_COMPRESSING (1<<31)
554 #define FBC_STAT_COMPRESSED (1<<30)
555 #define FBC_STAT_MODIFIED (1<<29)
556 #define FBC_STAT_CURRENT_LINE (1<<0)
557 #define FBC_CONTROL2 0x03214
558 #define FBC_CTL_FENCE_DBL (0<<4)
559 #define FBC_CTL_IDLE_IMM (0<<2)
560 #define FBC_CTL_IDLE_FULL (1<<2)
561 #define FBC_CTL_IDLE_LINE (2<<2)
562 #define FBC_CTL_IDLE_DEBUG (3<<2)
563 #define FBC_CTL_CPU_FENCE (1<<1)
564 #define FBC_CTL_PLANEA (0<<0)
565 #define FBC_CTL_PLANEB (1<<0)
566 #define FBC_FENCE_OFF 0x0321b
567 #define FBC_TAG 0x03300
569 #define FBC_LL_SIZE (1536)
571 /* Framebuffer compression for GM45+ */
572 #define DPFC_CB_BASE 0x3200
573 #define DPFC_CONTROL 0x3208
574 #define DPFC_CTL_EN (1<<31)
575 #define DPFC_CTL_PLANEA (0<<30)
576 #define DPFC_CTL_PLANEB (1<<30)
577 #define DPFC_CTL_FENCE_EN (1<<29)
578 #define DPFC_SR_EN (1<<10)
579 #define DPFC_CTL_LIMIT_1X (0<<6)
580 #define DPFC_CTL_LIMIT_2X (1<<6)
581 #define DPFC_CTL_LIMIT_4X (2<<6)
582 #define DPFC_RECOMP_CTL 0x320c
583 #define DPFC_RECOMP_STALL_EN (1<<27)
584 #define DPFC_RECOMP_STALL_WM_SHIFT (16)
585 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
586 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
587 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
588 #define DPFC_STATUS 0x3210
589 #define DPFC_INVAL_SEG_SHIFT (16)
590 #define DPFC_INVAL_SEG_MASK (0x07ff0000)
591 #define DPFC_COMP_SEG_SHIFT (0)
592 #define DPFC_COMP_SEG_MASK (0x000003ff)
593 #define DPFC_STATUS2 0x3214
594 #define DPFC_FENCE_YOFF 0x3218
595 #define DPFC_CHICKEN 0x3224
596 #define DPFC_HT_MODIFY (1<<31)
598 /* Framebuffer compression for Ironlake */
599 #define ILK_DPFC_CB_BASE 0x43200
600 #define ILK_DPFC_CONTROL 0x43208
601 /* The bit 28-8 is reserved */
602 #define DPFC_RESERVED (0x1FFFFF00)
603 #define ILK_DPFC_RECOMP_CTL 0x4320c
604 #define ILK_DPFC_STATUS 0x43210
605 #define ILK_DPFC_FENCE_YOFF 0x43218
606 #define ILK_DPFC_CHICKEN 0x43224
607 #define ILK_FBC_RT_BASE 0x2128
608 #define ILK_FBC_RT_VALID (1<<0)
610 #define ILK_DISPLAY_CHICKEN1 0x42000
611 #define ILK_FBCQ_DIS (1<<22)
612 #define ILK_PABSTRETCH_DIS (1<<21)
616 * Framebuffer compression for Sandybridge
618 * The following two registers are of type GTTMMADR
620 #define SNB_DPFC_CTL_SA 0x100100
621 #define SNB_CPU_FENCE_ENABLE (1<<29)
622 #define DPFC_CPU_FENCE_OFFSET 0x100104
636 # define GPIO_CLOCK_DIR_MASK (1 << 0)
637 # define GPIO_CLOCK_DIR_IN (0 << 1)
638 # define GPIO_CLOCK_DIR_OUT (1 << 1)
639 # define GPIO_CLOCK_VAL_MASK (1 << 2)
640 # define GPIO_CLOCK_VAL_OUT (1 << 3)
641 # define GPIO_CLOCK_VAL_IN (1 << 4)
642 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
643 # define GPIO_DATA_DIR_MASK (1 << 8)
644 # define GPIO_DATA_DIR_IN (0 << 9)
645 # define GPIO_DATA_DIR_OUT (1 << 9)
646 # define GPIO_DATA_VAL_MASK (1 << 10)
647 # define GPIO_DATA_VAL_OUT (1 << 11)
648 # define GPIO_DATA_VAL_IN (1 << 12)
649 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
651 #define GMBUS0 0x5100 /* clock/port select */
652 #define GMBUS_RATE_100KHZ (0<<8)
653 #define GMBUS_RATE_50KHZ (1<<8)
654 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
655 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
656 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
657 #define GMBUS_PORT_DISABLED 0
658 #define GMBUS_PORT_SSC 1
659 #define GMBUS_PORT_VGADDC 2
660 #define GMBUS_PORT_PANEL 3
661 #define GMBUS_PORT_DPC 4 /* HDMIC */
662 #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
664 #define GMBUS_PORT_DPD 7 /* HDMID */
665 #define GMBUS_NUM_PORTS 8
666 #define GMBUS1 0x5104 /* command/status */
667 #define GMBUS_SW_CLR_INT (1<<31)
668 #define GMBUS_SW_RDY (1<<30)
669 #define GMBUS_ENT (1<<29) /* enable timeout */
670 #define GMBUS_CYCLE_NONE (0<<25)
671 #define GMBUS_CYCLE_WAIT (1<<25)
672 #define GMBUS_CYCLE_INDEX (2<<25)
673 #define GMBUS_CYCLE_STOP (4<<25)
674 #define GMBUS_BYTE_COUNT_SHIFT 16
675 #define GMBUS_SLAVE_INDEX_SHIFT 8
676 #define GMBUS_SLAVE_ADDR_SHIFT 1
677 #define GMBUS_SLAVE_READ (1<<0)
678 #define GMBUS_SLAVE_WRITE (0<<0)
679 #define GMBUS2 0x5108 /* status */
680 #define GMBUS_INUSE (1<<15)
681 #define GMBUS_HW_WAIT_PHASE (1<<14)
682 #define GMBUS_STALL_TIMEOUT (1<<13)
683 #define GMBUS_INT (1<<12)
684 #define GMBUS_HW_RDY (1<<11)
685 #define GMBUS_SATOER (1<<10)
686 #define GMBUS_ACTIVE (1<<9)
687 #define GMBUS3 0x510c /* data buffer bytes 3-0 */
688 #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
689 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
690 #define GMBUS_NAK_EN (1<<3)
691 #define GMBUS_IDLE_EN (1<<2)
692 #define GMBUS_HW_WAIT_EN (1<<1)
693 #define GMBUS_HW_RDY_EN (1<<0)
694 #define GMBUS5 0x5120 /* byte index */
695 #define GMBUS_2BYTE_INDEX_EN (1<<31)
698 * Clock control & power management
703 #define VGA_PD 0x6010
704 #define VGA0_PD_P2_DIV_4 (1 << 7)
705 #define VGA0_PD_P1_DIV_2 (1 << 5)
706 #define VGA0_PD_P1_SHIFT 0
707 #define VGA0_PD_P1_MASK (0x1f << 0)
708 #define VGA1_PD_P2_DIV_4 (1 << 15)
709 #define VGA1_PD_P1_DIV_2 (1 << 13)
710 #define VGA1_PD_P1_SHIFT 8
711 #define VGA1_PD_P1_MASK (0x1f << 8)
712 #define _DPLL_A 0x06014
713 #define _DPLL_B 0x06018
714 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
715 #define DPLL_VCO_ENABLE (1 << 31)
716 #define DPLL_DVO_HIGH_SPEED (1 << 30)
717 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
718 #define DPLL_VGA_MODE_DIS (1 << 28)
719 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
720 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
721 #define DPLL_MODE_MASK (3 << 26)
722 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
723 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
724 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
725 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
726 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
727 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
728 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
730 #define SRX_INDEX 0x3c4
731 #define SRX_DATA 0x3c5
733 #define SR01_SCREEN_OFF (1<<5)
736 #define PPCR_ON (1<<0)
739 #define DVOB_ON (1<<31)
741 #define DVOC_ON (1<<31)
743 #define LVDS_ON (1<<31)
745 /* Scratch pad debug 0 reg:
747 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
749 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
750 * this field (only one bit may be set).
752 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
753 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
754 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
755 /* i830, required in DVO non-gang */
756 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
757 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
758 #define PLL_REF_INPUT_DREFCLK (0 << 13)
759 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
760 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
761 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
762 #define PLL_REF_INPUT_MASK (3 << 13)
763 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
765 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
766 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
767 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
768 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
769 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
772 * Parallel to Serial Load Pulse phase selection.
773 * Selects the phase for the 10X DPLL clock for the PCIe
774 * digital display port. The range is 4 to 13; 10 or more
775 * is just a flip delay. The default is 6
777 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
778 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
780 * SDVO multiplier for 945G/GM. Not used on 965.
782 #define SDVO_MULTIPLIER_MASK 0x000000ff
783 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
784 #define SDVO_MULTIPLIER_SHIFT_VGA 0
785 #define _DPLL_A_MD 0x0601c /* 965+ only */
787 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
789 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
791 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
792 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
793 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
794 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
795 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
797 * SDVO/UDI pixel multiplier.
799 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
800 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
801 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
802 * dummy bytes in the datastream at an increased clock rate, with both sides of
803 * the link knowing how many bytes are fill.
805 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
806 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
807 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
808 * through an SDVO command.
810 * This register field has values of multiplication factor minus 1, with
811 * a maximum multiplier of 5 for SDVO.
813 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
814 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
816 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
817 * This best be set to the default value (3) or the CRT won't work. No,
818 * I don't entirely understand what this does...
820 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
821 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
822 #define _DPLL_B_MD 0x06020 /* 965+ only */
823 #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
824 #define _FPA0 0x06040
825 #define _FPA1 0x06044
826 #define _FPB0 0x06048
827 #define _FPB1 0x0604c
828 #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
829 #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
830 #define FP_N_DIV_MASK 0x003f0000
831 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
832 #define FP_N_DIV_SHIFT 16
833 #define FP_M1_DIV_MASK 0x00003f00
834 #define FP_M1_DIV_SHIFT 8
835 #define FP_M2_DIV_MASK 0x0000003f
836 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
837 #define FP_M2_DIV_SHIFT 0
838 #define DPLL_TEST 0x606c
839 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
840 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
841 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
842 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
843 #define DPLLB_TEST_N_BYPASS (1 << 19)
844 #define DPLLB_TEST_M_BYPASS (1 << 18)
845 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
846 #define DPLLA_TEST_N_BYPASS (1 << 3)
847 #define DPLLA_TEST_M_BYPASS (1 << 2)
848 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
849 #define D_STATE 0x6104
850 #define DSTATE_GFX_RESET_I830 (1<<6)
851 #define DSTATE_PLL_D3_OFF (1<<3)
852 #define DSTATE_GFX_CLOCK_GATING (1<<1)
853 #define DSTATE_DOT_CLOCK_GATING (1<<0)
854 #define DSPCLK_GATE_D 0x6200
855 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
856 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
857 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
858 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
859 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
860 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
861 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
862 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
863 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
864 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
865 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
866 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
867 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
868 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
869 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
870 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
871 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
872 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
873 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
874 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
875 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
876 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
877 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
878 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
879 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
880 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
881 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
882 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
884 * This bit must be set on the 830 to prevent hangs when turning off the
887 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
888 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
889 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
890 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
891 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
893 #define RENCLK_GATE_D1 0x6204
894 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
895 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
896 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
897 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
898 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
899 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
900 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
901 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
902 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
903 /** This bit must be unset on 855,865 */
904 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
905 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
906 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
907 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
908 /** This bit must be set on 855,865. */
909 # define SV_CLOCK_GATE_DISABLE (1 << 0)
910 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
911 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
912 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
913 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
914 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
915 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
916 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
917 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
918 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
919 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
920 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
921 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
922 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
923 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
924 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
925 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
926 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
928 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
929 /** This bit must always be set on 965G/965GM */
930 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
931 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
932 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
933 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
934 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
935 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
936 /** This bit must always be set on 965G */
937 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
938 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
939 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
940 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
941 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
942 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
943 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
944 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
945 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
946 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
947 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
948 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
949 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
950 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
951 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
952 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
953 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
954 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
955 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
957 #define RENCLK_GATE_D2 0x6208
958 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
959 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
960 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
961 #define RAMCLK_GATE_D 0x6210 /* CRL only */
962 #define DEUC 0x6214 /* CRL only */
968 #define _PALETTE_A 0x0a000
969 #define _PALETTE_B 0x0a800
970 #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
977 * This mirrors the MCHBAR MMIO space whose location is determined by
978 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
979 * every way. It is not accessible from the CP register read instructions.
982 #define MCHBAR_MIRROR_BASE 0x10000
984 #define MCHBAR_MIRROR_BASE_SNB 0x140000
986 /** 915-945 and GM965 MCH register controlling DRAM channel access */
988 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
989 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
990 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
991 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
992 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
993 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
995 /** Pineview MCH register contains DDR3 setting */
996 #define CSHRDDR3CTL 0x101a8
997 #define CSHRDDR3CTL_DDR3 (1 << 2)
999 /** 965 MCH register controlling DRAM channel configuration */
1000 #define C0DRB3 0x10206
1001 #define C1DRB3 0x10606
1003 /* Clocking configuration register */
1004 #define CLKCFG 0x10c00
1005 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
1006 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
1007 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
1008 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
1009 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
1010 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
1011 /* Note, below two are guess */
1012 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
1013 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
1014 #define CLKCFG_FSB_MASK (7 << 0)
1015 #define CLKCFG_MEM_533 (1 << 4)
1016 #define CLKCFG_MEM_667 (2 << 4)
1017 #define CLKCFG_MEM_800 (3 << 4)
1018 #define CLKCFG_MEM_MASK (7 << 4)
1020 #define TSC1 0x11001
1023 #define TSFS 0x11020
1024 #define TSFS_SLOPE_MASK 0x0000ff00
1025 #define TSFS_SLOPE_SHIFT 8
1026 #define TSFS_INTR_MASK 0x000000ff
1028 #define CRSTANDVID 0x11100
1029 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
1030 #define PXVFREQ_PX_MASK 0x7f000000
1031 #define PXVFREQ_PX_SHIFT 24
1032 #define VIDFREQ_BASE 0x11110
1033 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
1034 #define VIDFREQ2 0x11114
1035 #define VIDFREQ3 0x11118
1036 #define VIDFREQ4 0x1111c
1037 #define VIDFREQ_P0_MASK 0x1f000000
1038 #define VIDFREQ_P0_SHIFT 24
1039 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000
1040 #define VIDFREQ_P0_CSCLK_SHIFT 20
1041 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000
1042 #define VIDFREQ_P0_CRCLK_SHIFT 16
1043 #define VIDFREQ_P1_MASK 0x00001f00
1044 #define VIDFREQ_P1_SHIFT 8
1045 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0
1046 #define VIDFREQ_P1_CSCLK_SHIFT 4
1047 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f
1048 #define INTTOEXT_BASE_ILK 0x11300
1049 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
1050 #define INTTOEXT_MAP3_SHIFT 24
1051 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
1052 #define INTTOEXT_MAP2_SHIFT 16
1053 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
1054 #define INTTOEXT_MAP1_SHIFT 8
1055 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
1056 #define INTTOEXT_MAP0_SHIFT 0
1057 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
1058 #define MEMSWCTL 0x11170 /* Ironlake only */
1059 #define MEMCTL_CMD_MASK 0xe000
1060 #define MEMCTL_CMD_SHIFT 13
1061 #define MEMCTL_CMD_RCLK_OFF 0
1062 #define MEMCTL_CMD_RCLK_ON 1
1063 #define MEMCTL_CMD_CHFREQ 2
1064 #define MEMCTL_CMD_CHVID 3
1065 #define MEMCTL_CMD_VMMOFF 4
1066 #define MEMCTL_CMD_VMMON 5
1067 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
1068 when command complete */
1069 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
1070 #define MEMCTL_FREQ_SHIFT 8
1071 #define MEMCTL_SFCAVM (1<<7)
1072 #define MEMCTL_TGT_VID_MASK 0x007f
1073 #define MEMIHYST 0x1117c
1074 #define MEMINTREN 0x11180 /* 16 bits */
1075 #define MEMINT_RSEXIT_EN (1<<8)
1076 #define MEMINT_CX_SUPR_EN (1<<7)
1077 #define MEMINT_CONT_BUSY_EN (1<<6)
1078 #define MEMINT_AVG_BUSY_EN (1<<5)
1079 #define MEMINT_EVAL_CHG_EN (1<<4)
1080 #define MEMINT_MON_IDLE_EN (1<<3)
1081 #define MEMINT_UP_EVAL_EN (1<<2)
1082 #define MEMINT_DOWN_EVAL_EN (1<<1)
1083 #define MEMINT_SW_CMD_EN (1<<0)
1084 #define MEMINTRSTR 0x11182 /* 16 bits */
1085 #define MEM_RSEXIT_MASK 0xc000
1086 #define MEM_RSEXIT_SHIFT 14
1087 #define MEM_CONT_BUSY_MASK 0x3000
1088 #define MEM_CONT_BUSY_SHIFT 12
1089 #define MEM_AVG_BUSY_MASK 0x0c00
1090 #define MEM_AVG_BUSY_SHIFT 10
1091 #define MEM_EVAL_CHG_MASK 0x0300
1092 #define MEM_EVAL_BUSY_SHIFT 8
1093 #define MEM_MON_IDLE_MASK 0x00c0
1094 #define MEM_MON_IDLE_SHIFT 6
1095 #define MEM_UP_EVAL_MASK 0x0030
1096 #define MEM_UP_EVAL_SHIFT 4
1097 #define MEM_DOWN_EVAL_MASK 0x000c
1098 #define MEM_DOWN_EVAL_SHIFT 2
1099 #define MEM_SW_CMD_MASK 0x0003
1100 #define MEM_INT_STEER_GFX 0
1101 #define MEM_INT_STEER_CMR 1
1102 #define MEM_INT_STEER_SMI 2
1103 #define MEM_INT_STEER_SCI 3
1104 #define MEMINTRSTS 0x11184
1105 #define MEMINT_RSEXIT (1<<7)
1106 #define MEMINT_CONT_BUSY (1<<6)
1107 #define MEMINT_AVG_BUSY (1<<5)
1108 #define MEMINT_EVAL_CHG (1<<4)
1109 #define MEMINT_MON_IDLE (1<<3)
1110 #define MEMINT_UP_EVAL (1<<2)
1111 #define MEMINT_DOWN_EVAL (1<<1)
1112 #define MEMINT_SW_CMD (1<<0)
1113 #define MEMMODECTL 0x11190
1114 #define MEMMODE_BOOST_EN (1<<31)
1115 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
1116 #define MEMMODE_BOOST_FREQ_SHIFT 24
1117 #define MEMMODE_IDLE_MODE_MASK 0x00030000
1118 #define MEMMODE_IDLE_MODE_SHIFT 16
1119 #define MEMMODE_IDLE_MODE_EVAL 0
1120 #define MEMMODE_IDLE_MODE_CONT 1
1121 #define MEMMODE_HWIDLE_EN (1<<15)
1122 #define MEMMODE_SWMODE_EN (1<<14)
1123 #define MEMMODE_RCLK_GATE (1<<13)
1124 #define MEMMODE_HW_UPDATE (1<<12)
1125 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
1126 #define MEMMODE_FSTART_SHIFT 8
1127 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
1128 #define MEMMODE_FMAX_SHIFT 4
1129 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
1130 #define RCBMAXAVG 0x1119c
1131 #define MEMSWCTL2 0x1119e /* Cantiga only */
1132 #define SWMEMCMD_RENDER_OFF (0 << 13)
1133 #define SWMEMCMD_RENDER_ON (1 << 13)
1134 #define SWMEMCMD_SWFREQ (2 << 13)
1135 #define SWMEMCMD_TARVID (3 << 13)
1136 #define SWMEMCMD_VRM_OFF (4 << 13)
1137 #define SWMEMCMD_VRM_ON (5 << 13)
1138 #define CMDSTS (1<<12)
1139 #define SFCAVM (1<<11)
1140 #define SWFREQ_MASK 0x0380 /* P0-7 */
1141 #define SWFREQ_SHIFT 7
1142 #define TARVID_MASK 0x001f
1143 #define MEMSTAT_CTG 0x111a0
1144 #define RCBMINAVG 0x111a0
1145 #define RCUPEI 0x111b0
1146 #define RCDNEI 0x111b4
1147 #define RSTDBYCTL 0x111b8
1148 #define RS1EN (1<<31)
1149 #define RS2EN (1<<30)
1150 #define RS3EN (1<<29)
1151 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
1152 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
1153 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
1154 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
1155 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
1156 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
1157 #define RSX_STATUS_MASK (7<<20)
1158 #define RSX_STATUS_ON (0<<20)
1159 #define RSX_STATUS_RC1 (1<<20)
1160 #define RSX_STATUS_RC1E (2<<20)
1161 #define RSX_STATUS_RS1 (3<<20)
1162 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
1163 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
1164 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
1165 #define RSX_STATUS_RSVD2 (7<<20)
1166 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
1167 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
1168 #define JRSC (1<<17) /* rsx coupled to cpu c-state */
1169 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
1170 #define RS1CONTSAV_MASK (3<<14)
1171 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
1172 #define RS1CONTSAV_RSVD (1<<14)
1173 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
1174 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
1175 #define NORMSLEXLAT_MASK (3<<12)
1176 #define SLOW_RS123 (0<<12)
1177 #define SLOW_RS23 (1<<12)
1178 #define SLOW_RS3 (2<<12)
1179 #define NORMAL_RS123 (3<<12)
1180 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
1181 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
1182 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
1183 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
1184 #define RS_CSTATE_MASK (3<<4)
1185 #define RS_CSTATE_C367_RS1 (0<<4)
1186 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
1187 #define RS_CSTATE_RSVD (2<<4)
1188 #define RS_CSTATE_C367_RS2 (3<<4)
1189 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */
1190 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
1191 #define VIDCTL 0x111c0
1192 #define VIDSTS 0x111c8
1193 #define VIDSTART 0x111cc /* 8 bits */
1194 #define MEMSTAT_ILK 0x111f8
1195 #define MEMSTAT_VID_MASK 0x7f00
1196 #define MEMSTAT_VID_SHIFT 8
1197 #define MEMSTAT_PSTATE_MASK 0x00f8
1198 #define MEMSTAT_PSTATE_SHIFT 3
1199 #define MEMSTAT_MON_ACTV (1<<2)
1200 #define MEMSTAT_SRC_CTL_MASK 0x0003
1201 #define MEMSTAT_SRC_CTL_CORE 0
1202 #define MEMSTAT_SRC_CTL_TRB 1
1203 #define MEMSTAT_SRC_CTL_THM 2
1204 #define MEMSTAT_SRC_CTL_STDBY 3
1205 #define RCPREVBSYTUPAVG 0x113b8
1206 #define RCPREVBSYTDNAVG 0x113bc
1207 #define PMMISC 0x11214
1208 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
1209 #define SDEW 0x1124c
1210 #define CSIEW0 0x11250
1211 #define CSIEW1 0x11254
1212 #define CSIEW2 0x11258
1215 #define MCHAFE 0x112c0
1216 #define CSIEC 0x112e0
1217 #define DMIEC 0x112e4
1218 #define DDREC 0x112e8
1219 #define PEG0EC 0x112ec
1220 #define PEG1EC 0x112f0
1221 #define GFXEC 0x112f4
1222 #define RPPREVBSYTUPAVG 0x113b8
1223 #define RPPREVBSYTDNAVG 0x113bc
1225 #define ECR_GPFE (1<<31)
1226 #define ECR_IMONE (1<<30)
1227 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
1228 #define OGW0 0x11608
1229 #define OGW1 0x1160c
1239 #define PXWL 0x11680
1240 #define LCFUSE02 0x116c0
1241 #define LCFUSE_HIV_MASK 0x000000ff
1242 #define CSIPLL0 0x12c10
1243 #define DDRMPLL1 0X12c20
1244 #define PEG_BAND_GAP_DATA 0x14d68
1246 #define GEN6_GT_PERF_STATUS 0x145948
1247 #define GEN6_RP_STATE_LIMITS 0x145994
1248 #define GEN6_RP_STATE_CAP 0x145998
1251 * Logical Context regs
1254 #define CCID_EN (1<<0)
1259 #define OVADD 0x30000
1260 #define DOVSTA 0x30008
1261 #define OC_BUF (0x3<<20)
1262 #define OGAMC5 0x30010
1263 #define OGAMC4 0x30014
1264 #define OGAMC3 0x30018
1265 #define OGAMC2 0x3001c
1266 #define OGAMC1 0x30020
1267 #define OGAMC0 0x30024
1270 * Display engine regs
1273 /* Pipe A timing regs */
1274 #define _HTOTAL_A 0x60000
1275 #define _HBLANK_A 0x60004
1276 #define _HSYNC_A 0x60008
1277 #define _VTOTAL_A 0x6000c
1278 #define _VBLANK_A 0x60010
1279 #define _VSYNC_A 0x60014
1280 #define _PIPEASRC 0x6001c
1281 #define _BCLRPAT_A 0x60020
1283 /* Pipe B timing regs */
1284 #define _HTOTAL_B 0x61000
1285 #define _HBLANK_B 0x61004
1286 #define _HSYNC_B 0x61008
1287 #define _VTOTAL_B 0x6100c
1288 #define _VBLANK_B 0x61010
1289 #define _VSYNC_B 0x61014
1290 #define _PIPEBSRC 0x6101c
1291 #define _BCLRPAT_B 0x61020
1293 #define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
1294 #define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
1295 #define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B)
1296 #define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B)
1297 #define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
1298 #define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
1299 #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
1301 /* VGA port control */
1302 #define ADPA 0x61100
1303 #define ADPA_DAC_ENABLE (1<<31)
1304 #define ADPA_DAC_DISABLE 0
1305 #define ADPA_PIPE_SELECT_MASK (1<<30)
1306 #define ADPA_PIPE_A_SELECT 0
1307 #define ADPA_PIPE_B_SELECT (1<<30)
1308 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
1309 #define ADPA_SETS_HVPOLARITY 0
1310 #define ADPA_VSYNC_CNTL_DISABLE (1<<11)
1311 #define ADPA_VSYNC_CNTL_ENABLE 0
1312 #define ADPA_HSYNC_CNTL_DISABLE (1<<10)
1313 #define ADPA_HSYNC_CNTL_ENABLE 0
1314 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
1315 #define ADPA_VSYNC_ACTIVE_LOW 0
1316 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
1317 #define ADPA_HSYNC_ACTIVE_LOW 0
1318 #define ADPA_DPMS_MASK (~(3<<10))
1319 #define ADPA_DPMS_ON (0<<10)
1320 #define ADPA_DPMS_SUSPEND (1<<10)
1321 #define ADPA_DPMS_STANDBY (2<<10)
1322 #define ADPA_DPMS_OFF (3<<10)
1325 /* Hotplug control (945+ only) */
1326 #define PORT_HOTPLUG_EN 0x61110
1327 #define HDMIB_HOTPLUG_INT_EN (1 << 29)
1328 #define DPB_HOTPLUG_INT_EN (1 << 29)
1329 #define HDMIC_HOTPLUG_INT_EN (1 << 28)
1330 #define DPC_HOTPLUG_INT_EN (1 << 28)
1331 #define HDMID_HOTPLUG_INT_EN (1 << 27)
1332 #define DPD_HOTPLUG_INT_EN (1 << 27)
1333 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
1334 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
1335 #define TV_HOTPLUG_INT_EN (1 << 18)
1336 #define CRT_HOTPLUG_INT_EN (1 << 9)
1337 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
1338 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
1339 /* must use period 64 on GM45 according to docs */
1340 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
1341 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
1342 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
1343 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
1344 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
1345 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
1346 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
1347 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
1348 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
1349 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
1350 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
1351 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
1353 #define PORT_HOTPLUG_STAT 0x61114
1354 #define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
1355 #define DPB_HOTPLUG_INT_STATUS (1 << 29)
1356 #define HDMIC_HOTPLUG_INT_STATUS (1 << 28)
1357 #define DPC_HOTPLUG_INT_STATUS (1 << 28)
1358 #define HDMID_HOTPLUG_INT_STATUS (1 << 27)
1359 #define DPD_HOTPLUG_INT_STATUS (1 << 27)
1360 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
1361 #define TV_HOTPLUG_INT_STATUS (1 << 10)
1362 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
1363 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
1364 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
1365 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
1366 #define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
1367 #define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
1369 /* SDVO port control */
1370 #define SDVOB 0x61140
1371 #define SDVOC 0x61160
1372 #define SDVO_ENABLE (1 << 31)
1373 #define SDVO_PIPE_B_SELECT (1 << 30)
1374 #define SDVO_STALL_SELECT (1 << 29)
1375 #define SDVO_INTERRUPT_ENABLE (1 << 26)
1377 * 915G/GM SDVO pixel multiplier.
1379 * Programmed value is multiplier - 1, up to 5x.
1381 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
1383 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
1384 #define SDVO_PORT_MULTIPLY_SHIFT 23
1385 #define SDVO_PHASE_SELECT_MASK (15 << 19)
1386 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
1387 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
1388 #define SDVOC_GANG_MODE (1 << 16)
1389 #define SDVO_ENCODING_SDVO (0x0 << 10)
1390 #define SDVO_ENCODING_HDMI (0x2 << 10)
1391 /** Requird for HDMI operation */
1392 #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
1393 #define SDVO_COLOR_RANGE_16_235 (1 << 8)
1394 #define SDVO_BORDER_ENABLE (1 << 7)
1395 #define SDVO_AUDIO_ENABLE (1 << 6)
1396 /** New with 965, default is to be set */
1397 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
1398 /** New with 965, default is to be set */
1399 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
1400 #define SDVOB_PCIE_CONCURRENCY (1 << 3)
1401 #define SDVO_DETECTED (1 << 2)
1402 /* Bits to be preserved when writing */
1403 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
1404 #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
1406 /* DVO port control */
1407 #define DVOA 0x61120
1408 #define DVOB 0x61140
1409 #define DVOC 0x61160
1410 #define DVO_ENABLE (1 << 31)
1411 #define DVO_PIPE_B_SELECT (1 << 30)
1412 #define DVO_PIPE_STALL_UNUSED (0 << 28)
1413 #define DVO_PIPE_STALL (1 << 28)
1414 #define DVO_PIPE_STALL_TV (2 << 28)
1415 #define DVO_PIPE_STALL_MASK (3 << 28)
1416 #define DVO_USE_VGA_SYNC (1 << 15)
1417 #define DVO_DATA_ORDER_I740 (0 << 14)
1418 #define DVO_DATA_ORDER_FP (1 << 14)
1419 #define DVO_VSYNC_DISABLE (1 << 11)
1420 #define DVO_HSYNC_DISABLE (1 << 10)
1421 #define DVO_VSYNC_TRISTATE (1 << 9)
1422 #define DVO_HSYNC_TRISTATE (1 << 8)
1423 #define DVO_BORDER_ENABLE (1 << 7)
1424 #define DVO_DATA_ORDER_GBRG (1 << 6)
1425 #define DVO_DATA_ORDER_RGGB (0 << 6)
1426 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
1427 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
1428 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
1429 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
1430 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
1431 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
1432 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
1433 #define DVO_PRESERVE_MASK (0x7<<24)
1434 #define DVOA_SRCDIM 0x61124
1435 #define DVOB_SRCDIM 0x61144
1436 #define DVOC_SRCDIM 0x61164
1437 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
1438 #define DVO_SRCDIM_VERTICAL_SHIFT 0
1440 /* LVDS port control */
1441 #define LVDS 0x61180
1443 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
1444 * the DPLL semantics change when the LVDS is assigned to that pipe.
1446 #define LVDS_PORT_EN (1 << 31)
1447 /* Selects pipe B for LVDS data. Must be set on pre-965. */
1448 #define LVDS_PIPEB_SELECT (1 << 30)
1449 #define LVDS_PIPE_MASK (1 << 30)
1450 /* LVDS dithering flag on 965/g4x platform */
1451 #define LVDS_ENABLE_DITHER (1 << 25)
1452 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
1453 #define LVDS_VSYNC_POLARITY (1 << 21)
1454 #define LVDS_HSYNC_POLARITY (1 << 20)
1456 /* Enable border for unscaled (or aspect-scaled) display */
1457 #define LVDS_BORDER_ENABLE (1 << 15)
1459 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
1462 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
1463 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
1464 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
1466 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
1467 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
1470 #define LVDS_A3_POWER_MASK (3 << 6)
1471 #define LVDS_A3_POWER_DOWN (0 << 6)
1472 #define LVDS_A3_POWER_UP (3 << 6)
1474 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
1477 #define LVDS_CLKB_POWER_MASK (3 << 4)
1478 #define LVDS_CLKB_POWER_DOWN (0 << 4)
1479 #define LVDS_CLKB_POWER_UP (3 << 4)
1481 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
1482 * setting for whether we are in dual-channel mode. The B3 pair will
1483 * additionally only be powered up when LVDS_A3_POWER_UP is set.
1485 #define LVDS_B0B3_POWER_MASK (3 << 2)
1486 #define LVDS_B0B3_POWER_DOWN (0 << 2)
1487 #define LVDS_B0B3_POWER_UP (3 << 2)
1489 #define LVDS_PIPE_ENABLED(V, P) \
1490 (((V) & (LVDS_PIPE_MASK | LVDS_PORT_EN)) == ((P) << 30 | LVDS_PORT_EN))
1492 /* Video Data Island Packet control */
1493 #define VIDEO_DIP_DATA 0x61178
1494 #define VIDEO_DIP_CTL 0x61170
1495 #define VIDEO_DIP_ENABLE (1 << 31)
1496 #define VIDEO_DIP_PORT_B (1 << 29)
1497 #define VIDEO_DIP_PORT_C (2 << 29)
1498 #define VIDEO_DIP_ENABLE_AVI (1 << 21)
1499 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
1500 #define VIDEO_DIP_ENABLE_SPD (8 << 21)
1501 #define VIDEO_DIP_SELECT_AVI (0 << 19)
1502 #define VIDEO_DIP_SELECT_VENDOR (1 << 19)
1503 #define VIDEO_DIP_SELECT_SPD (3 << 19)
1504 #define VIDEO_DIP_FREQ_ONCE (0 << 16)
1505 #define VIDEO_DIP_FREQ_VSYNC (1 << 16)
1506 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
1508 /* Panel power sequencing */
1509 #define PP_STATUS 0x61200
1510 #define PP_ON (1 << 31)
1512 * Indicates that all dependencies of the panel are on:
1516 * - LVDS/DVOB/DVOC on
1518 #define PP_READY (1 << 30)
1519 #define PP_SEQUENCE_NONE (0 << 28)
1520 #define PP_SEQUENCE_ON (1 << 28)
1521 #define PP_SEQUENCE_OFF (2 << 28)
1522 #define PP_SEQUENCE_MASK 0x30000000
1523 #define PP_CYCLE_DELAY_ACTIVE (1 << 27)
1524 #define PP_SEQUENCE_STATE_ON_IDLE (1 << 3)
1525 #define PP_SEQUENCE_STATE_MASK 0x0000000f
1526 #define PP_CONTROL 0x61204
1527 #define POWER_TARGET_ON (1 << 0)
1528 #define PP_ON_DELAYS 0x61208
1529 #define PP_OFF_DELAYS 0x6120c
1530 #define PP_DIVISOR 0x61210
1533 #define PFIT_CONTROL 0x61230
1534 #define PFIT_ENABLE (1 << 31)
1535 #define PFIT_PIPE_MASK (3 << 29)
1536 #define PFIT_PIPE_SHIFT 29
1537 #define VERT_INTERP_DISABLE (0 << 10)
1538 #define VERT_INTERP_BILINEAR (1 << 10)
1539 #define VERT_INTERP_MASK (3 << 10)
1540 #define VERT_AUTO_SCALE (1 << 9)
1541 #define HORIZ_INTERP_DISABLE (0 << 6)
1542 #define HORIZ_INTERP_BILINEAR (1 << 6)
1543 #define HORIZ_INTERP_MASK (3 << 6)
1544 #define HORIZ_AUTO_SCALE (1 << 5)
1545 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
1546 #define PFIT_FILTER_FUZZY (0 << 24)
1547 #define PFIT_SCALING_AUTO (0 << 26)
1548 #define PFIT_SCALING_PROGRAMMED (1 << 26)
1549 #define PFIT_SCALING_PILLAR (2 << 26)
1550 #define PFIT_SCALING_LETTER (3 << 26)
1551 #define PFIT_PGM_RATIOS 0x61234
1552 #define PFIT_VERT_SCALE_MASK 0xfff00000
1553 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1555 #define PFIT_VERT_SCALE_SHIFT 20
1556 #define PFIT_VERT_SCALE_MASK 0xfff00000
1557 #define PFIT_HORIZ_SCALE_SHIFT 4
1558 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1560 #define PFIT_VERT_SCALE_SHIFT_965 16
1561 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
1562 #define PFIT_HORIZ_SCALE_SHIFT_965 0
1563 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
1565 #define PFIT_AUTO_RATIOS 0x61238
1567 /* Backlight control */
1568 #define BLC_PWM_CTL 0x61254
1569 #define BLC_PWM_CTL2 0x61250 /* 965+ only */
1571 * This is the number of cycles out of the backlight modulation cycle for which
1572 * the backlight is on.
1574 * This field must be no greater than the number of cycles in the complete
1575 * backlight modulation cycle.
1577 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
1578 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
1580 #define BLC_HIST_CTL 0x61260
1582 /* TV port control */
1583 #define TV_CTL 0x68000
1584 /** Enables the TV encoder */
1585 # define TV_ENC_ENABLE (1 << 31)
1586 /** Sources the TV encoder input from pipe B instead of A. */
1587 # define TV_ENC_PIPEB_SELECT (1 << 30)
1588 /** Outputs composite video (DAC A only) */
1589 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
1590 /** Outputs SVideo video (DAC B/C) */
1591 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
1592 /** Outputs Component video (DAC A/B/C) */
1593 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
1594 /** Outputs Composite and SVideo (DAC A/B/C) */
1595 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
1596 # define TV_TRILEVEL_SYNC (1 << 21)
1597 /** Enables slow sync generation (945GM only) */
1598 # define TV_SLOW_SYNC (1 << 20)
1599 /** Selects 4x oversampling for 480i and 576p */
1600 # define TV_OVERSAMPLE_4X (0 << 18)
1601 /** Selects 2x oversampling for 720p and 1080i */
1602 # define TV_OVERSAMPLE_2X (1 << 18)
1603 /** Selects no oversampling for 1080p */
1604 # define TV_OVERSAMPLE_NONE (2 << 18)
1605 /** Selects 8x oversampling */
1606 # define TV_OVERSAMPLE_8X (3 << 18)
1607 /** Selects progressive mode rather than interlaced */
1608 # define TV_PROGRESSIVE (1 << 17)
1609 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
1610 # define TV_PAL_BURST (1 << 16)
1611 /** Field for setting delay of Y compared to C */
1612 # define TV_YC_SKEW_MASK (7 << 12)
1613 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */
1614 # define TV_ENC_SDP_FIX (1 << 11)
1616 * Enables a fix for the 915GM only.
1618 * Not sure what it does.
1620 # define TV_ENC_C0_FIX (1 << 10)
1621 /** Bits that must be preserved by software */
1622 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
1623 # define TV_FUSE_STATE_MASK (3 << 4)
1624 /** Read-only state that reports all features enabled */
1625 # define TV_FUSE_STATE_ENABLED (0 << 4)
1626 /** Read-only state that reports that Macrovision is disabled in hardware*/
1627 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
1628 /** Read-only state that reports that TV-out is disabled in hardware. */
1629 # define TV_FUSE_STATE_DISABLED (2 << 4)
1630 /** Normal operation */
1631 # define TV_TEST_MODE_NORMAL (0 << 0)
1632 /** Encoder test pattern 1 - combo pattern */
1633 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
1634 /** Encoder test pattern 2 - full screen vertical 75% color bars */
1635 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
1636 /** Encoder test pattern 3 - full screen horizontal 75% color bars */
1637 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
1638 /** Encoder test pattern 4 - random noise */
1639 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
1640 /** Encoder test pattern 5 - linear color ramps */
1641 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
1643 * This test mode forces the DACs to 50% of full output.
1645 * This is used for load detection in combination with TVDAC_SENSE_MASK
1647 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
1648 # define TV_TEST_MODE_MASK (7 << 0)
1650 #define TV_DAC 0x68004
1651 # define TV_DAC_SAVE 0x00ffff00
1653 * Reports that DAC state change logic has reported change (RO).
1655 * This gets cleared when TV_DAC_STATE_EN is cleared
1657 # define TVDAC_STATE_CHG (1 << 31)
1658 # define TVDAC_SENSE_MASK (7 << 28)
1659 /** Reports that DAC A voltage is above the detect threshold */
1660 # define TVDAC_A_SENSE (1 << 30)
1661 /** Reports that DAC B voltage is above the detect threshold */
1662 # define TVDAC_B_SENSE (1 << 29)
1663 /** Reports that DAC C voltage is above the detect threshold */
1664 # define TVDAC_C_SENSE (1 << 28)
1666 * Enables DAC state detection logic, for load-based TV detection.
1668 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
1669 * to off, for load detection to work.
1671 # define TVDAC_STATE_CHG_EN (1 << 27)
1672 /** Sets the DAC A sense value to high */
1673 # define TVDAC_A_SENSE_CTL (1 << 26)
1674 /** Sets the DAC B sense value to high */
1675 # define TVDAC_B_SENSE_CTL (1 << 25)
1676 /** Sets the DAC C sense value to high */
1677 # define TVDAC_C_SENSE_CTL (1 << 24)
1678 /** Overrides the ENC_ENABLE and DAC voltage levels */
1679 # define DAC_CTL_OVERRIDE (1 << 7)
1680 /** Sets the slew rate. Must be preserved in software */
1681 # define ENC_TVDAC_SLEW_FAST (1 << 6)
1682 # define DAC_A_1_3_V (0 << 4)
1683 # define DAC_A_1_1_V (1 << 4)
1684 # define DAC_A_0_7_V (2 << 4)
1685 # define DAC_A_MASK (3 << 4)
1686 # define DAC_B_1_3_V (0 << 2)
1687 # define DAC_B_1_1_V (1 << 2)
1688 # define DAC_B_0_7_V (2 << 2)
1689 # define DAC_B_MASK (3 << 2)
1690 # define DAC_C_1_3_V (0 << 0)
1691 # define DAC_C_1_1_V (1 << 0)
1692 # define DAC_C_0_7_V (2 << 0)
1693 # define DAC_C_MASK (3 << 0)
1696 * CSC coefficients are stored in a floating point format with 9 bits of
1697 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
1698 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
1699 * -1 (0x3) being the only legal negative value.
1701 #define TV_CSC_Y 0x68010
1702 # define TV_RY_MASK 0x07ff0000
1703 # define TV_RY_SHIFT 16
1704 # define TV_GY_MASK 0x00000fff
1705 # define TV_GY_SHIFT 0
1707 #define TV_CSC_Y2 0x68014
1708 # define TV_BY_MASK 0x07ff0000
1709 # define TV_BY_SHIFT 16
1711 * Y attenuation for component video.
1713 * Stored in 1.9 fixed point.
1715 # define TV_AY_MASK 0x000003ff
1716 # define TV_AY_SHIFT 0
1718 #define TV_CSC_U 0x68018
1719 # define TV_RU_MASK 0x07ff0000
1720 # define TV_RU_SHIFT 16
1721 # define TV_GU_MASK 0x000007ff
1722 # define TV_GU_SHIFT 0
1724 #define TV_CSC_U2 0x6801c
1725 # define TV_BU_MASK 0x07ff0000
1726 # define TV_BU_SHIFT 16
1728 * U attenuation for component video.
1730 * Stored in 1.9 fixed point.
1732 # define TV_AU_MASK 0x000003ff
1733 # define TV_AU_SHIFT 0
1735 #define TV_CSC_V 0x68020
1736 # define TV_RV_MASK 0x0fff0000
1737 # define TV_RV_SHIFT 16
1738 # define TV_GV_MASK 0x000007ff
1739 # define TV_GV_SHIFT 0
1741 #define TV_CSC_V2 0x68024
1742 # define TV_BV_MASK 0x07ff0000
1743 # define TV_BV_SHIFT 16
1745 * V attenuation for component video.
1747 * Stored in 1.9 fixed point.
1749 # define TV_AV_MASK 0x000007ff
1750 # define TV_AV_SHIFT 0
1752 #define TV_CLR_KNOBS 0x68028
1753 /** 2s-complement brightness adjustment */
1754 # define TV_BRIGHTNESS_MASK 0xff000000
1755 # define TV_BRIGHTNESS_SHIFT 24
1756 /** Contrast adjustment, as a 2.6 unsigned floating point number */
1757 # define TV_CONTRAST_MASK 0x00ff0000
1758 # define TV_CONTRAST_SHIFT 16
1759 /** Saturation adjustment, as a 2.6 unsigned floating point number */
1760 # define TV_SATURATION_MASK 0x0000ff00
1761 # define TV_SATURATION_SHIFT 8
1762 /** Hue adjustment, as an integer phase angle in degrees */
1763 # define TV_HUE_MASK 0x000000ff
1764 # define TV_HUE_SHIFT 0
1766 #define TV_CLR_LEVEL 0x6802c
1767 /** Controls the DAC level for black */
1768 # define TV_BLACK_LEVEL_MASK 0x01ff0000
1769 # define TV_BLACK_LEVEL_SHIFT 16
1770 /** Controls the DAC level for blanking */
1771 # define TV_BLANK_LEVEL_MASK 0x000001ff
1772 # define TV_BLANK_LEVEL_SHIFT 0
1774 #define TV_H_CTL_1 0x68030
1775 /** Number of pixels in the hsync. */
1776 # define TV_HSYNC_END_MASK 0x1fff0000
1777 # define TV_HSYNC_END_SHIFT 16
1778 /** Total number of pixels minus one in the line (display and blanking). */
1779 # define TV_HTOTAL_MASK 0x00001fff
1780 # define TV_HTOTAL_SHIFT 0
1782 #define TV_H_CTL_2 0x68034
1783 /** Enables the colorburst (needed for non-component color) */
1784 # define TV_BURST_ENA (1 << 31)
1785 /** Offset of the colorburst from the start of hsync, in pixels minus one. */
1786 # define TV_HBURST_START_SHIFT 16
1787 # define TV_HBURST_START_MASK 0x1fff0000
1788 /** Length of the colorburst */
1789 # define TV_HBURST_LEN_SHIFT 0
1790 # define TV_HBURST_LEN_MASK 0x0001fff
1792 #define TV_H_CTL_3 0x68038
1793 /** End of hblank, measured in pixels minus one from start of hsync */
1794 # define TV_HBLANK_END_SHIFT 16
1795 # define TV_HBLANK_END_MASK 0x1fff0000
1796 /** Start of hblank, measured in pixels minus one from start of hsync */
1797 # define TV_HBLANK_START_SHIFT 0
1798 # define TV_HBLANK_START_MASK 0x0001fff
1800 #define TV_V_CTL_1 0x6803c
1802 # define TV_NBR_END_SHIFT 16
1803 # define TV_NBR_END_MASK 0x07ff0000
1805 # define TV_VI_END_F1_SHIFT 8
1806 # define TV_VI_END_F1_MASK 0x00003f00
1808 # define TV_VI_END_F2_SHIFT 0
1809 # define TV_VI_END_F2_MASK 0x0000003f
1811 #define TV_V_CTL_2 0x68040
1812 /** Length of vsync, in half lines */
1813 # define TV_VSYNC_LEN_MASK 0x07ff0000
1814 # define TV_VSYNC_LEN_SHIFT 16
1815 /** Offset of the start of vsync in field 1, measured in one less than the
1816 * number of half lines.
1818 # define TV_VSYNC_START_F1_MASK 0x00007f00
1819 # define TV_VSYNC_START_F1_SHIFT 8
1821 * Offset of the start of vsync in field 2, measured in one less than the
1822 * number of half lines.
1824 # define TV_VSYNC_START_F2_MASK 0x0000007f
1825 # define TV_VSYNC_START_F2_SHIFT 0
1827 #define TV_V_CTL_3 0x68044
1828 /** Enables generation of the equalization signal */
1829 # define TV_EQUAL_ENA (1 << 31)
1830 /** Length of vsync, in half lines */
1831 # define TV_VEQ_LEN_MASK 0x007f0000
1832 # define TV_VEQ_LEN_SHIFT 16
1833 /** Offset of the start of equalization in field 1, measured in one less than
1834 * the number of half lines.
1836 # define TV_VEQ_START_F1_MASK 0x0007f00
1837 # define TV_VEQ_START_F1_SHIFT 8
1839 * Offset of the start of equalization in field 2, measured in one less than
1840 * the number of half lines.
1842 # define TV_VEQ_START_F2_MASK 0x000007f
1843 # define TV_VEQ_START_F2_SHIFT 0
1845 #define TV_V_CTL_4 0x68048
1847 * Offset to start of vertical colorburst, measured in one less than the
1848 * number of lines from vertical start.
1850 # define TV_VBURST_START_F1_MASK 0x003f0000
1851 # define TV_VBURST_START_F1_SHIFT 16
1853 * Offset to the end of vertical colorburst, measured in one less than the
1854 * number of lines from the start of NBR.
1856 # define TV_VBURST_END_F1_MASK 0x000000ff
1857 # define TV_VBURST_END_F1_SHIFT 0
1859 #define TV_V_CTL_5 0x6804c
1861 * Offset to start of vertical colorburst, measured in one less than the
1862 * number of lines from vertical start.
1864 # define TV_VBURST_START_F2_MASK 0x003f0000
1865 # define TV_VBURST_START_F2_SHIFT 16
1867 * Offset to the end of vertical colorburst, measured in one less than the
1868 * number of lines from the start of NBR.
1870 # define TV_VBURST_END_F2_MASK 0x000000ff
1871 # define TV_VBURST_END_F2_SHIFT 0
1873 #define TV_V_CTL_6 0x68050
1875 * Offset to start of vertical colorburst, measured in one less than the
1876 * number of lines from vertical start.
1878 # define TV_VBURST_START_F3_MASK 0x003f0000
1879 # define TV_VBURST_START_F3_SHIFT 16
1881 * Offset to the end of vertical colorburst, measured in one less than the
1882 * number of lines from the start of NBR.
1884 # define TV_VBURST_END_F3_MASK 0x000000ff
1885 # define TV_VBURST_END_F3_SHIFT 0
1887 #define TV_V_CTL_7 0x68054
1889 * Offset to start of vertical colorburst, measured in one less than the
1890 * number of lines from vertical start.
1892 # define TV_VBURST_START_F4_MASK 0x003f0000
1893 # define TV_VBURST_START_F4_SHIFT 16
1895 * Offset to the end of vertical colorburst, measured in one less than the
1896 * number of lines from the start of NBR.
1898 # define TV_VBURST_END_F4_MASK 0x000000ff
1899 # define TV_VBURST_END_F4_SHIFT 0
1901 #define TV_SC_CTL_1 0x68060
1902 /** Turns on the first subcarrier phase generation DDA */
1903 # define TV_SC_DDA1_EN (1 << 31)
1904 /** Turns on the first subcarrier phase generation DDA */
1905 # define TV_SC_DDA2_EN (1 << 30)
1906 /** Turns on the first subcarrier phase generation DDA */
1907 # define TV_SC_DDA3_EN (1 << 29)
1908 /** Sets the subcarrier DDA to reset frequency every other field */
1909 # define TV_SC_RESET_EVERY_2 (0 << 24)
1910 /** Sets the subcarrier DDA to reset frequency every fourth field */
1911 # define TV_SC_RESET_EVERY_4 (1 << 24)
1912 /** Sets the subcarrier DDA to reset frequency every eighth field */
1913 # define TV_SC_RESET_EVERY_8 (2 << 24)
1914 /** Sets the subcarrier DDA to never reset the frequency */
1915 # define TV_SC_RESET_NEVER (3 << 24)
1916 /** Sets the peak amplitude of the colorburst.*/
1917 # define TV_BURST_LEVEL_MASK 0x00ff0000
1918 # define TV_BURST_LEVEL_SHIFT 16
1919 /** Sets the increment of the first subcarrier phase generation DDA */
1920 # define TV_SCDDA1_INC_MASK 0x00000fff
1921 # define TV_SCDDA1_INC_SHIFT 0
1923 #define TV_SC_CTL_2 0x68064
1924 /** Sets the rollover for the second subcarrier phase generation DDA */
1925 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
1926 # define TV_SCDDA2_SIZE_SHIFT 16
1927 /** Sets the increent of the second subcarrier phase generation DDA */
1928 # define TV_SCDDA2_INC_MASK 0x00007fff
1929 # define TV_SCDDA2_INC_SHIFT 0
1931 #define TV_SC_CTL_3 0x68068
1932 /** Sets the rollover for the third subcarrier phase generation DDA */
1933 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
1934 # define TV_SCDDA3_SIZE_SHIFT 16
1935 /** Sets the increent of the third subcarrier phase generation DDA */
1936 # define TV_SCDDA3_INC_MASK 0x00007fff
1937 # define TV_SCDDA3_INC_SHIFT 0
1939 #define TV_WIN_POS 0x68070
1940 /** X coordinate of the display from the start of horizontal active */
1941 # define TV_XPOS_MASK 0x1fff0000
1942 # define TV_XPOS_SHIFT 16
1943 /** Y coordinate of the display from the start of vertical active (NBR) */
1944 # define TV_YPOS_MASK 0x00000fff
1945 # define TV_YPOS_SHIFT 0
1947 #define TV_WIN_SIZE 0x68074
1948 /** Horizontal size of the display window, measured in pixels*/
1949 # define TV_XSIZE_MASK 0x1fff0000
1950 # define TV_XSIZE_SHIFT 16
1952 * Vertical size of the display window, measured in pixels.
1954 * Must be even for interlaced modes.
1956 # define TV_YSIZE_MASK 0x00000fff
1957 # define TV_YSIZE_SHIFT 0
1959 #define TV_FILTER_CTL_1 0x68080
1961 * Enables automatic scaling calculation.
1963 * If set, the rest of the registers are ignored, and the calculated values can
1964 * be read back from the register.
1966 # define TV_AUTO_SCALE (1 << 31)
1968 * Disables the vertical filter.
1970 * This is required on modes more than 1024 pixels wide */
1971 # define TV_V_FILTER_BYPASS (1 << 29)
1972 /** Enables adaptive vertical filtering */
1973 # define TV_VADAPT (1 << 28)
1974 # define TV_VADAPT_MODE_MASK (3 << 26)
1975 /** Selects the least adaptive vertical filtering mode */
1976 # define TV_VADAPT_MODE_LEAST (0 << 26)
1977 /** Selects the moderately adaptive vertical filtering mode */
1978 # define TV_VADAPT_MODE_MODERATE (1 << 26)
1979 /** Selects the most adaptive vertical filtering mode */
1980 # define TV_VADAPT_MODE_MOST (3 << 26)
1982 * Sets the horizontal scaling factor.
1984 * This should be the fractional part of the horizontal scaling factor divided
1985 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
1987 * (src width - 1) / ((oversample * dest width) - 1)
1989 # define TV_HSCALE_FRAC_MASK 0x00003fff
1990 # define TV_HSCALE_FRAC_SHIFT 0
1992 #define TV_FILTER_CTL_2 0x68084
1994 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1996 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
1998 # define TV_VSCALE_INT_MASK 0x00038000
1999 # define TV_VSCALE_INT_SHIFT 15
2001 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2003 * \sa TV_VSCALE_INT_MASK
2005 # define TV_VSCALE_FRAC_MASK 0x00007fff
2006 # define TV_VSCALE_FRAC_SHIFT 0
2008 #define TV_FILTER_CTL_3 0x68088
2010 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2012 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
2014 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2016 # define TV_VSCALE_IP_INT_MASK 0x00038000
2017 # define TV_VSCALE_IP_INT_SHIFT 15
2019 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2021 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2023 * \sa TV_VSCALE_IP_INT_MASK
2025 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
2026 # define TV_VSCALE_IP_FRAC_SHIFT 0
2028 #define TV_CC_CONTROL 0x68090
2029 # define TV_CC_ENABLE (1 << 31)
2031 * Specifies which field to send the CC data in.
2033 * CC data is usually sent in field 0.
2035 # define TV_CC_FID_MASK (1 << 27)
2036 # define TV_CC_FID_SHIFT 27
2037 /** Sets the horizontal position of the CC data. Usually 135. */
2038 # define TV_CC_HOFF_MASK 0x03ff0000
2039 # define TV_CC_HOFF_SHIFT 16
2040 /** Sets the vertical position of the CC data. Usually 21 */
2041 # define TV_CC_LINE_MASK 0x0000003f
2042 # define TV_CC_LINE_SHIFT 0
2044 #define TV_CC_DATA 0x68094
2045 # define TV_CC_RDY (1 << 31)
2046 /** Second word of CC data to be transmitted. */
2047 # define TV_CC_DATA_2_MASK 0x007f0000
2048 # define TV_CC_DATA_2_SHIFT 16
2049 /** First word of CC data to be transmitted. */
2050 # define TV_CC_DATA_1_MASK 0x0000007f
2051 # define TV_CC_DATA_1_SHIFT 0
2053 #define TV_H_LUMA_0 0x68100
2054 #define TV_H_LUMA_59 0x681ec
2055 #define TV_H_CHROMA_0 0x68200
2056 #define TV_H_CHROMA_59 0x682ec
2057 #define TV_V_LUMA_0 0x68300
2058 #define TV_V_LUMA_42 0x683a8
2059 #define TV_V_CHROMA_0 0x68400
2060 #define TV_V_CHROMA_42 0x684a8
2063 #define DP_A 0x64000 /* eDP */
2064 #define DP_B 0x64100
2065 #define DP_C 0x64200
2066 #define DP_D 0x64300
2068 #define DP_PORT_EN (1 << 31)
2069 #define DP_PIPEB_SELECT (1 << 30)
2070 #define DP_PIPE_MASK (1 << 30)
2072 #define DP_PIPE_ENABLED(V, P) \
2073 (((V) & (DP_PIPE_MASK | DP_PORT_EN)) == ((P) << 30 | DP_PORT_EN))
2075 /* Link training mode - select a suitable mode for each stage */
2076 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
2077 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
2078 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
2079 #define DP_LINK_TRAIN_OFF (3 << 28)
2080 #define DP_LINK_TRAIN_MASK (3 << 28)
2081 #define DP_LINK_TRAIN_SHIFT 28
2083 /* CPT Link training mode */
2084 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
2085 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
2086 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
2087 #define DP_LINK_TRAIN_OFF_CPT (3 << 8)
2088 #define DP_LINK_TRAIN_MASK_CPT (7 << 8)
2089 #define DP_LINK_TRAIN_SHIFT_CPT 8
2091 /* Signal voltages. These are mostly controlled by the other end */
2092 #define DP_VOLTAGE_0_4 (0 << 25)
2093 #define DP_VOLTAGE_0_6 (1 << 25)
2094 #define DP_VOLTAGE_0_8 (2 << 25)
2095 #define DP_VOLTAGE_1_2 (3 << 25)
2096 #define DP_VOLTAGE_MASK (7 << 25)
2097 #define DP_VOLTAGE_SHIFT 25
2099 /* Signal pre-emphasis levels, like voltages, the other end tells us what
2102 #define DP_PRE_EMPHASIS_0 (0 << 22)
2103 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
2104 #define DP_PRE_EMPHASIS_6 (2 << 22)
2105 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
2106 #define DP_PRE_EMPHASIS_MASK (7 << 22)
2107 #define DP_PRE_EMPHASIS_SHIFT 22
2109 /* How many wires to use. I guess 3 was too hard */
2110 #define DP_PORT_WIDTH_1 (0 << 19)
2111 #define DP_PORT_WIDTH_2 (1 << 19)
2112 #define DP_PORT_WIDTH_4 (3 << 19)
2113 #define DP_PORT_WIDTH_MASK (7 << 19)
2115 /* Mystic DPCD version 1.1 special mode */
2116 #define DP_ENHANCED_FRAMING (1 << 18)
2119 #define DP_PLL_FREQ_270MHZ (0 << 16)
2120 #define DP_PLL_FREQ_160MHZ (1 << 16)
2121 #define DP_PLL_FREQ_MASK (3 << 16)
2123 /** locked once port is enabled */
2124 #define DP_PORT_REVERSAL (1 << 15)
2127 #define DP_PLL_ENABLE (1 << 14)
2129 /** sends the clock on lane 15 of the PEG for debug */
2130 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
2132 #define DP_SCRAMBLING_DISABLE (1 << 12)
2133 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
2135 /** limit RGB values to avoid confusing TVs */
2136 #define DP_COLOR_RANGE_16_235 (1 << 8)
2138 /** Turn on the audio link */
2139 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
2141 /** vs and hs sync polarity */
2142 #define DP_SYNC_VS_HIGH (1 << 4)
2143 #define DP_SYNC_HS_HIGH (1 << 3)
2146 #define DP_DETECTED (1 << 2)
2148 /** The aux channel provides a way to talk to the
2149 * signal sink for DDC etc. Max packet size supported
2150 * is 20 bytes in each direction, hence the 5 fixed
2153 #define DPA_AUX_CH_CTL 0x64010
2154 #define DPA_AUX_CH_DATA1 0x64014
2155 #define DPA_AUX_CH_DATA2 0x64018
2156 #define DPA_AUX_CH_DATA3 0x6401c
2157 #define DPA_AUX_CH_DATA4 0x64020
2158 #define DPA_AUX_CH_DATA5 0x64024
2160 #define DPB_AUX_CH_CTL 0x64110
2161 #define DPB_AUX_CH_DATA1 0x64114
2162 #define DPB_AUX_CH_DATA2 0x64118
2163 #define DPB_AUX_CH_DATA3 0x6411c
2164 #define DPB_AUX_CH_DATA4 0x64120
2165 #define DPB_AUX_CH_DATA5 0x64124
2167 #define DPC_AUX_CH_CTL 0x64210
2168 #define DPC_AUX_CH_DATA1 0x64214
2169 #define DPC_AUX_CH_DATA2 0x64218
2170 #define DPC_AUX_CH_DATA3 0x6421c
2171 #define DPC_AUX_CH_DATA4 0x64220
2172 #define DPC_AUX_CH_DATA5 0x64224
2174 #define DPD_AUX_CH_CTL 0x64310
2175 #define DPD_AUX_CH_DATA1 0x64314
2176 #define DPD_AUX_CH_DATA2 0x64318
2177 #define DPD_AUX_CH_DATA3 0x6431c
2178 #define DPD_AUX_CH_DATA4 0x64320
2179 #define DPD_AUX_CH_DATA5 0x64324
2181 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
2182 #define DP_AUX_CH_CTL_DONE (1 << 30)
2183 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
2184 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
2185 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
2186 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
2187 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
2188 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
2189 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
2190 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
2191 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
2192 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
2193 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
2194 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
2195 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
2196 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
2197 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
2198 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
2199 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
2200 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
2201 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
2204 * Computing GMCH M and N values for the Display Port link
2206 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
2208 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
2210 * The GMCH value is used internally
2212 * bytes_per_pixel is the number of bytes coming out of the plane,
2213 * which is after the LUTs, so we want the bytes for our color format.
2214 * For our current usage, this is always 3, one byte for R, G and B.
2216 #define _PIPEA_GMCH_DATA_M 0x70050
2217 #define _PIPEB_GMCH_DATA_M 0x71050
2219 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
2220 #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
2221 #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
2223 #define PIPE_GMCH_DATA_M_MASK (0xffffff)
2225 #define _PIPEA_GMCH_DATA_N 0x70054
2226 #define _PIPEB_GMCH_DATA_N 0x71054
2227 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
2230 * Computing Link M and N values for the Display Port link
2232 * Link M / N = pixel_clock / ls_clk
2234 * (the DP spec calls pixel_clock the 'strm_clk')
2236 * The Link value is transmitted in the Main Stream
2237 * Attributes and VB-ID.
2240 #define _PIPEA_DP_LINK_M 0x70060
2241 #define _PIPEB_DP_LINK_M 0x71060
2242 #define PIPEA_DP_LINK_M_MASK (0xffffff)
2244 #define _PIPEA_DP_LINK_N 0x70064
2245 #define _PIPEB_DP_LINK_N 0x71064
2246 #define PIPEA_DP_LINK_N_MASK (0xffffff)
2248 #define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
2249 #define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
2250 #define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
2251 #define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
2253 /* Display & cursor control */
2256 #define _PIPEADSL 0x70000
2257 #define DSL_LINEMASK 0x00000fff
2258 #define _PIPEACONF 0x70008
2259 #define PIPECONF_ENABLE (1<<31)
2260 #define PIPECONF_DISABLE 0
2261 #define PIPECONF_DOUBLE_WIDE (1<<30)
2262 #define I965_PIPECONF_ACTIVE (1<<30)
2263 #define PIPECONF_SINGLE_WIDE 0
2264 #define PIPECONF_PIPE_UNLOCKED 0
2265 #define PIPECONF_PIPE_LOCKED (1<<25)
2266 #define PIPECONF_PALETTE 0
2267 #define PIPECONF_GAMMA (1<<24)
2268 #define PIPECONF_FORCE_BORDER (1<<25)
2269 #define PIPECONF_PROGRESSIVE (0 << 21)
2270 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
2271 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
2272 #define PIPECONF_CXSR_DOWNCLOCK (1<<16)
2273 #define PIPECONF_BPP_MASK (0x000000e0)
2274 #define PIPECONF_BPP_8 (0<<5)
2275 #define PIPECONF_BPP_10 (1<<5)
2276 #define PIPECONF_BPP_6 (2<<5)
2277 #define PIPECONF_BPP_12 (3<<5)
2278 #define PIPECONF_DITHER_EN (1<<4)
2279 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
2280 #define PIPECONF_DITHER_TYPE_SP (0<<2)
2281 #define PIPECONF_DITHER_TYPE_ST1 (1<<2)
2282 #define PIPECONF_DITHER_TYPE_ST2 (2<<2)
2283 #define PIPECONF_DITHER_TYPE_TEMP (3<<2)
2284 #define _PIPEASTAT 0x70024
2285 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
2286 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)
2287 #define PIPE_CRC_DONE_ENABLE (1UL<<28)
2288 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
2289 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
2290 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
2291 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
2292 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)
2293 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
2294 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
2295 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
2296 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
2297 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
2298 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
2299 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
2300 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
2301 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
2302 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
2303 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
2304 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
2305 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
2306 #define PIPE_DPST_EVENT_STATUS (1UL<<7)
2307 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
2308 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
2309 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
2310 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
2311 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
2312 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
2313 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
2314 #define PIPE_BPC_MASK (7 << 5) /* Ironlake */
2315 #define PIPE_8BPC (0 << 5)
2316 #define PIPE_10BPC (1 << 5)
2317 #define PIPE_6BPC (2 << 5)
2318 #define PIPE_12BPC (3 << 5)
2320 #define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
2321 #define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF)
2322 #define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
2323 #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
2324 #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
2325 #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
2327 #define DSPARB 0x70030
2328 #define DSPARB_CSTART_MASK (0x7f << 7)
2329 #define DSPARB_CSTART_SHIFT 7
2330 #define DSPARB_BSTART_MASK (0x7f)
2331 #define DSPARB_BSTART_SHIFT 0
2332 #define DSPARB_BEND_SHIFT 9 /* on 855 */
2333 #define DSPARB_AEND_SHIFT 0
2335 #define DSPFW1 0x70034
2336 #define DSPFW_SR_SHIFT 23
2337 #define DSPFW_SR_MASK (0x1ff<<23)
2338 #define DSPFW_CURSORB_SHIFT 16
2339 #define DSPFW_CURSORB_MASK (0x3f<<16)
2340 #define DSPFW_PLANEB_SHIFT 8
2341 #define DSPFW_PLANEB_MASK (0x7f<<8)
2342 #define DSPFW_PLANEA_MASK (0x7f)
2343 #define DSPFW2 0x70038
2344 #define DSPFW_CURSORA_MASK 0x00003f00
2345 #define DSPFW_CURSORA_SHIFT 8
2346 #define DSPFW_PLANEC_MASK (0x7f)
2347 #define DSPFW3 0x7003c
2348 #define DSPFW_HPLL_SR_EN (1<<31)
2349 #define DSPFW_CURSOR_SR_SHIFT 24
2350 #define PINEVIEW_SELF_REFRESH_EN (1<<30)
2351 #define DSPFW_CURSOR_SR_MASK (0x3f<<24)
2352 #define DSPFW_HPLL_CURSOR_SHIFT 16
2353 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
2354 #define DSPFW_HPLL_SR_MASK (0x1ff)
2356 /* FIFO watermark sizes etc */
2357 #define G4X_FIFO_LINE_SIZE 64
2358 #define I915_FIFO_LINE_SIZE 64
2359 #define I830_FIFO_LINE_SIZE 32
2361 #define G4X_FIFO_SIZE 127
2362 #define I965_FIFO_SIZE 512
2363 #define I945_FIFO_SIZE 127
2364 #define I915_FIFO_SIZE 95
2365 #define I855GM_FIFO_SIZE 127 /* In cachelines */
2366 #define I830_FIFO_SIZE 95
2368 #define G4X_MAX_WM 0x3f
2369 #define I915_MAX_WM 0x3f
2371 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
2372 #define PINEVIEW_FIFO_LINE_SIZE 64
2373 #define PINEVIEW_MAX_WM 0x1ff
2374 #define PINEVIEW_DFT_WM 0x3f
2375 #define PINEVIEW_DFT_HPLLOFF_WM 0
2376 #define PINEVIEW_GUARD_WM 10
2377 #define PINEVIEW_CURSOR_FIFO 64
2378 #define PINEVIEW_CURSOR_MAX_WM 0x3f
2379 #define PINEVIEW_CURSOR_DFT_WM 0
2380 #define PINEVIEW_CURSOR_GUARD_WM 5
2382 #define I965_CURSOR_FIFO 64
2383 #define I965_CURSOR_MAX_WM 32
2384 #define I965_CURSOR_DFT_WM 8
2386 /* define the Watermark register on Ironlake */
2387 #define WM0_PIPEA_ILK 0x45100
2388 #define WM0_PIPE_PLANE_MASK (0x7f<<16)
2389 #define WM0_PIPE_PLANE_SHIFT 16
2390 #define WM0_PIPE_SPRITE_MASK (0x3f<<8)
2391 #define WM0_PIPE_SPRITE_SHIFT 8
2392 #define WM0_PIPE_CURSOR_MASK (0x1f)
2394 #define WM0_PIPEB_ILK 0x45104
2395 #define WM1_LP_ILK 0x45108
2396 #define WM1_LP_SR_EN (1<<31)
2397 #define WM1_LP_LATENCY_SHIFT 24
2398 #define WM1_LP_LATENCY_MASK (0x7f<<24)
2399 #define WM1_LP_FBC_MASK (0xf<<20)
2400 #define WM1_LP_FBC_SHIFT 20
2401 #define WM1_LP_SR_MASK (0x1ff<<8)
2402 #define WM1_LP_SR_SHIFT 8
2403 #define WM1_LP_CURSOR_MASK (0x3f)
2404 #define WM2_LP_ILK 0x4510c
2405 #define WM2_LP_EN (1<<31)
2406 #define WM3_LP_ILK 0x45110
2407 #define WM3_LP_EN (1<<31)
2408 #define WM1S_LP_ILK 0x45120
2409 #define WM1S_LP_EN (1<<31)
2411 /* Memory latency timer register */
2412 #define MLTR_ILK 0x11222
2413 #define MLTR_WM1_SHIFT 0
2414 #define MLTR_WM2_SHIFT 8
2415 /* the unit of memory self-refresh latency time is 0.5us */
2416 #define ILK_SRLT_MASK 0x3f
2417 #define ILK_LATENCY(shift) (I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK)
2418 #define ILK_READ_WM1_LATENCY() ILK_LATENCY(MLTR_WM1_SHIFT)
2419 #define ILK_READ_WM2_LATENCY() ILK_LATENCY(MLTR_WM2_SHIFT)
2421 /* define the fifo size on Ironlake */
2422 #define ILK_DISPLAY_FIFO 128
2423 #define ILK_DISPLAY_MAXWM 64
2424 #define ILK_DISPLAY_DFTWM 8
2425 #define ILK_CURSOR_FIFO 32
2426 #define ILK_CURSOR_MAXWM 16
2427 #define ILK_CURSOR_DFTWM 8
2429 #define ILK_DISPLAY_SR_FIFO 512
2430 #define ILK_DISPLAY_MAX_SRWM 0x1ff
2431 #define ILK_DISPLAY_DFT_SRWM 0x3f
2432 #define ILK_CURSOR_SR_FIFO 64
2433 #define ILK_CURSOR_MAX_SRWM 0x3f
2434 #define ILK_CURSOR_DFT_SRWM 8
2436 #define ILK_FIFO_LINE_SIZE 64
2438 /* define the WM info on Sandybridge */
2439 #define SNB_DISPLAY_FIFO 128
2440 #define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */
2441 #define SNB_DISPLAY_DFTWM 8
2442 #define SNB_CURSOR_FIFO 32
2443 #define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */
2444 #define SNB_CURSOR_DFTWM 8
2446 #define SNB_DISPLAY_SR_FIFO 512
2447 #define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */
2448 #define SNB_DISPLAY_DFT_SRWM 0x3f
2449 #define SNB_CURSOR_SR_FIFO 64
2450 #define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */
2451 #define SNB_CURSOR_DFT_SRWM 8
2453 #define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */
2455 #define SNB_FIFO_LINE_SIZE 64
2458 /* the address where we get all kinds of latency value */
2459 #define SSKPD 0x5d10
2460 #define SSKPD_WM_MASK 0x3f
2461 #define SSKPD_WM0_SHIFT 0
2462 #define SSKPD_WM1_SHIFT 8
2463 #define SSKPD_WM2_SHIFT 16
2464 #define SSKPD_WM3_SHIFT 24
2466 #define SNB_LATENCY(shift) (I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK)
2467 #define SNB_READ_WM0_LATENCY() SNB_LATENCY(SSKPD_WM0_SHIFT)
2468 #define SNB_READ_WM1_LATENCY() SNB_LATENCY(SSKPD_WM1_SHIFT)
2469 #define SNB_READ_WM2_LATENCY() SNB_LATENCY(SSKPD_WM2_SHIFT)
2470 #define SNB_READ_WM3_LATENCY() SNB_LATENCY(SSKPD_WM3_SHIFT)
2473 * The two pipe frame counter registers are not synchronized, so
2474 * reading a stable value is somewhat tricky. The following code
2478 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2479 * PIPE_FRAME_HIGH_SHIFT;
2480 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
2481 * PIPE_FRAME_LOW_SHIFT);
2482 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2483 * PIPE_FRAME_HIGH_SHIFT);
2484 * } while (high1 != high2);
2485 * frame = (high1 << 8) | low1;
2487 #define _PIPEAFRAMEHIGH 0x70040
2488 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
2489 #define PIPE_FRAME_HIGH_SHIFT 0
2490 #define _PIPEAFRAMEPIXEL 0x70044
2491 #define PIPE_FRAME_LOW_MASK 0xff000000
2492 #define PIPE_FRAME_LOW_SHIFT 24
2493 #define PIPE_PIXEL_MASK 0x00ffffff
2494 #define PIPE_PIXEL_SHIFT 0
2495 /* GM45+ just has to be different */
2496 #define _PIPEA_FRMCOUNT_GM45 0x70040
2497 #define _PIPEA_FLIPCOUNT_GM45 0x70044
2498 #define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
2500 /* Cursor A & B regs */
2501 #define _CURACNTR 0x70080
2502 /* Old style CUR*CNTR flags (desktop 8xx) */
2503 #define CURSOR_ENABLE 0x80000000
2504 #define CURSOR_GAMMA_ENABLE 0x40000000
2505 #define CURSOR_STRIDE_MASK 0x30000000
2506 #define CURSOR_FORMAT_SHIFT 24
2507 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
2508 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
2509 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
2510 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
2511 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
2512 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
2513 /* New style CUR*CNTR flags */
2514 #define CURSOR_MODE 0x27
2515 #define CURSOR_MODE_DISABLE 0x00
2516 #define CURSOR_MODE_64_32B_AX 0x07
2517 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
2518 #define MCURSOR_PIPE_SELECT (1 << 28)
2519 #define MCURSOR_PIPE_A 0x00
2520 #define MCURSOR_PIPE_B (1 << 28)
2521 #define MCURSOR_GAMMA_ENABLE (1 << 26)
2522 #define _CURABASE 0x70084
2523 #define _CURAPOS 0x70088
2524 #define CURSOR_POS_MASK 0x007FF
2525 #define CURSOR_POS_SIGN 0x8000
2526 #define CURSOR_X_SHIFT 0
2527 #define CURSOR_Y_SHIFT 16
2528 #define CURSIZE 0x700a0
2529 #define _CURBCNTR 0x700c0
2530 #define _CURBBASE 0x700c4
2531 #define _CURBPOS 0x700c8
2533 #define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
2534 #define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
2535 #define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
2537 /* Display A control */
2538 #define _DSPACNTR 0x70180
2539 #define DISPLAY_PLANE_ENABLE (1<<31)
2540 #define DISPLAY_PLANE_DISABLE 0
2541 #define DISPPLANE_GAMMA_ENABLE (1<<30)
2542 #define DISPPLANE_GAMMA_DISABLE 0
2543 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
2544 #define DISPPLANE_8BPP (0x2<<26)
2545 #define DISPPLANE_15_16BPP (0x4<<26)
2546 #define DISPPLANE_16BPP (0x5<<26)
2547 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
2548 #define DISPPLANE_32BPP (0x7<<26)
2549 #define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26)
2550 #define DISPPLANE_STEREO_ENABLE (1<<25)
2551 #define DISPPLANE_STEREO_DISABLE 0
2552 #define DISPPLANE_SEL_PIPE_SHIFT 24
2553 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
2554 #define DISPPLANE_SEL_PIPE_A 0
2555 #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
2556 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
2557 #define DISPPLANE_SRC_KEY_DISABLE 0
2558 #define DISPPLANE_LINE_DOUBLE (1<<20)
2559 #define DISPPLANE_NO_LINE_DOUBLE 0
2560 #define DISPPLANE_STEREO_POLARITY_FIRST 0
2561 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
2562 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
2563 #define DISPPLANE_TILED (1<<10)
2564 #define _DSPAADDR 0x70184
2565 #define _DSPASTRIDE 0x70188
2566 #define _DSPAPOS 0x7018C /* reserved */
2567 #define _DSPASIZE 0x70190
2568 #define _DSPASURF 0x7019C /* 965+ only */
2569 #define _DSPATILEOFF 0x701A4 /* 965+ only */
2571 #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
2572 #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
2573 #define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE)
2574 #define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS)
2575 #define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
2576 #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
2577 #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
2580 #define SWF00 0x71410
2581 #define SWF01 0x71414
2582 #define SWF02 0x71418
2583 #define SWF03 0x7141c
2584 #define SWF04 0x71420
2585 #define SWF05 0x71424
2586 #define SWF06 0x71428
2587 #define SWF10 0x70410
2588 #define SWF11 0x70414
2589 #define SWF14 0x71420
2590 #define SWF30 0x72414
2591 #define SWF31 0x72418
2592 #define SWF32 0x7241c
2595 #define _PIPEBDSL 0x71000
2596 #define _PIPEBCONF 0x71008
2597 #define _PIPEBSTAT 0x71024
2598 #define _PIPEBFRAMEHIGH 0x71040
2599 #define _PIPEBFRAMEPIXEL 0x71044
2600 #define _PIPEB_FRMCOUNT_GM45 0x71040
2601 #define _PIPEB_FLIPCOUNT_GM45 0x71044
2604 /* Display B control */
2605 #define _DSPBCNTR 0x71180
2606 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
2607 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
2608 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
2609 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
2610 #define _DSPBADDR 0x71184
2611 #define _DSPBSTRIDE 0x71188
2612 #define _DSPBPOS 0x7118C
2613 #define _DSPBSIZE 0x71190
2614 #define _DSPBSURF 0x7119C
2615 #define _DSPBTILEOFF 0x711A4
2618 #define VGACNTRL 0x71400
2619 # define VGA_DISP_DISABLE (1 << 31)
2620 # define VGA_2X_MODE (1 << 30)
2621 # define VGA_PIPE_B_SELECT (1 << 29)
2625 #define CPU_VGACNTRL 0x41000
2627 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
2628 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
2629 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
2630 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
2631 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
2632 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
2633 #define DIGITAL_PORTA_NO_DETECT (0 << 0)
2634 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
2635 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
2637 /* refresh rate hardware control */
2638 #define RR_HW_CTL 0x45300
2639 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
2640 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
2642 #define FDI_PLL_BIOS_0 0x46000
2643 #define FDI_PLL_FB_CLOCK_MASK 0xff
2644 #define FDI_PLL_BIOS_1 0x46004
2645 #define FDI_PLL_BIOS_2 0x46008
2646 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c
2647 #define DISPLAY_PORT_PLL_BIOS_1 0x46010
2648 #define DISPLAY_PORT_PLL_BIOS_2 0x46014
2650 #define PCH_DSPCLK_GATE_D 0x42020
2651 # define DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
2652 # define DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
2653 # define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7)
2654 # define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5)
2656 #define PCH_3DCGDIS0 0x46020
2657 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
2658 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
2660 #define PCH_3DCGDIS1 0x46024
2661 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
2663 #define FDI_PLL_FREQ_CTL 0x46030
2664 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
2665 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
2666 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
2669 #define _PIPEA_DATA_M1 0x60030
2670 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
2671 #define TU_SIZE_MASK 0x7e000000
2672 #define PIPE_DATA_M1_OFFSET 0
2673 #define _PIPEA_DATA_N1 0x60034
2674 #define PIPE_DATA_N1_OFFSET 0
2676 #define _PIPEA_DATA_M2 0x60038
2677 #define PIPE_DATA_M2_OFFSET 0
2678 #define _PIPEA_DATA_N2 0x6003c
2679 #define PIPE_DATA_N2_OFFSET 0
2681 #define _PIPEA_LINK_M1 0x60040
2682 #define PIPE_LINK_M1_OFFSET 0
2683 #define _PIPEA_LINK_N1 0x60044
2684 #define PIPE_LINK_N1_OFFSET 0
2686 #define _PIPEA_LINK_M2 0x60048
2687 #define PIPE_LINK_M2_OFFSET 0
2688 #define _PIPEA_LINK_N2 0x6004c
2689 #define PIPE_LINK_N2_OFFSET 0
2691 /* PIPEB timing regs are same start from 0x61000 */
2693 #define _PIPEB_DATA_M1 0x61030
2694 #define _PIPEB_DATA_N1 0x61034
2696 #define _PIPEB_DATA_M2 0x61038
2697 #define _PIPEB_DATA_N2 0x6103c
2699 #define _PIPEB_LINK_M1 0x61040
2700 #define _PIPEB_LINK_N1 0x61044
2702 #define _PIPEB_LINK_M2 0x61048
2703 #define _PIPEB_LINK_N2 0x6104c
2705 #define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
2706 #define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
2707 #define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
2708 #define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
2709 #define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
2710 #define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
2711 #define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
2712 #define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
2714 /* CPU panel fitter */
2715 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
2716 #define _PFA_CTL_1 0x68080
2717 #define _PFB_CTL_1 0x68880
2718 #define PF_ENABLE (1<<31)
2719 #define PF_FILTER_MASK (3<<23)
2720 #define PF_FILTER_PROGRAMMED (0<<23)
2721 #define PF_FILTER_MED_3x3 (1<<23)
2722 #define PF_FILTER_EDGE_ENHANCE (2<<23)
2723 #define PF_FILTER_EDGE_SOFTEN (3<<23)
2724 #define _PFA_WIN_SZ 0x68074
2725 #define _PFB_WIN_SZ 0x68874
2726 #define _PFA_WIN_POS 0x68070
2727 #define _PFB_WIN_POS 0x68870
2728 #define _PFA_VSCALE 0x68084
2729 #define _PFB_VSCALE 0x68884
2730 #define _PFA_HSCALE 0x68090
2731 #define _PFB_HSCALE 0x68890
2733 #define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
2734 #define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
2735 #define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
2736 #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
2737 #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
2739 /* legacy palette */
2740 #define _LGC_PALETTE_A 0x4a000
2741 #define _LGC_PALETTE_B 0x4a800
2742 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
2745 #define DE_MASTER_IRQ_CONTROL (1 << 31)
2746 #define DE_SPRITEB_FLIP_DONE (1 << 29)
2747 #define DE_SPRITEA_FLIP_DONE (1 << 28)
2748 #define DE_PLANEB_FLIP_DONE (1 << 27)
2749 #define DE_PLANEA_FLIP_DONE (1 << 26)
2750 #define DE_PCU_EVENT (1 << 25)
2751 #define DE_GTT_FAULT (1 << 24)
2752 #define DE_POISON (1 << 23)
2753 #define DE_PERFORM_COUNTER (1 << 22)
2754 #define DE_PCH_EVENT (1 << 21)
2755 #define DE_AUX_CHANNEL_A (1 << 20)
2756 #define DE_DP_A_HOTPLUG (1 << 19)
2757 #define DE_GSE (1 << 18)
2758 #define DE_PIPEB_VBLANK (1 << 15)
2759 #define DE_PIPEB_EVEN_FIELD (1 << 14)
2760 #define DE_PIPEB_ODD_FIELD (1 << 13)
2761 #define DE_PIPEB_LINE_COMPARE (1 << 12)
2762 #define DE_PIPEB_VSYNC (1 << 11)
2763 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
2764 #define DE_PIPEA_VBLANK (1 << 7)
2765 #define DE_PIPEA_EVEN_FIELD (1 << 6)
2766 #define DE_PIPEA_ODD_FIELD (1 << 5)
2767 #define DE_PIPEA_LINE_COMPARE (1 << 4)
2768 #define DE_PIPEA_VSYNC (1 << 3)
2769 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
2771 #define DEISR 0x44000
2772 #define DEIMR 0x44004
2773 #define DEIIR 0x44008
2774 #define DEIER 0x4400c
2777 #define GT_PIPE_NOTIFY (1 << 4)
2778 #define GT_SYNC_STATUS (1 << 2)
2779 #define GT_USER_INTERRUPT (1 << 0)
2780 #define GT_BSD_USER_INTERRUPT (1 << 5)
2781 #define GT_GEN6_BSD_USER_INTERRUPT (1 << 12)
2782 #define GT_BLT_USER_INTERRUPT (1 << 22)
2784 #define GTISR 0x44010
2785 #define GTIMR 0x44014
2786 #define GTIIR 0x44018
2787 #define GTIER 0x4401c
2789 #define ILK_DISPLAY_CHICKEN2 0x42004
2790 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
2791 #define ILK_ELPIN_409_SELECT (1 << 25)
2792 #define ILK_DPARB_GATE (1<<22)
2793 #define ILK_VSDPFD_FULL (1<<21)
2794 #define ILK_DISPLAY_CHICKEN_FUSES 0x42014
2795 #define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31)
2796 #define ILK_INTERNAL_DISPLAY_DISABLE (1<<30)
2797 #define ILK_DISPLAY_DEBUG_DISABLE (1<<29)
2798 #define ILK_HDCP_DISABLE (1<<25)
2799 #define ILK_eDP_A_DISABLE (1<<24)
2800 #define ILK_DESKTOP (1<<23)
2801 #define ILK_DSPCLK_GATE 0x42020
2802 #define ILK_DPARB_CLK_GATE (1<<5)
2803 #define ILK_DPFD_CLK_GATE (1<<7)
2805 /* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */
2806 #define ILK_CLK_FBC (1<<7)
2807 #define ILK_DPFC_DIS1 (1<<8)
2808 #define ILK_DPFC_DIS2 (1<<9)
2810 #define DISP_ARB_CTL 0x45000
2811 #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
2812 #define DISP_FBC_WM_DIS (1<<15)
2816 /* south display engine interrupt */
2817 #define SDE_AUDIO_POWER_D (1 << 27)
2818 #define SDE_AUDIO_POWER_C (1 << 26)
2819 #define SDE_AUDIO_POWER_B (1 << 25)
2820 #define SDE_AUDIO_POWER_SHIFT (25)
2821 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
2822 #define SDE_GMBUS (1 << 24)
2823 #define SDE_AUDIO_HDCP_TRANSB (1 << 23)
2824 #define SDE_AUDIO_HDCP_TRANSA (1 << 22)
2825 #define SDE_AUDIO_HDCP_MASK (3 << 22)
2826 #define SDE_AUDIO_TRANSB (1 << 21)
2827 #define SDE_AUDIO_TRANSA (1 << 20)
2828 #define SDE_AUDIO_TRANS_MASK (3 << 20)
2829 #define SDE_POISON (1 << 19)
2831 #define SDE_FDI_RXB (1 << 17)
2832 #define SDE_FDI_RXA (1 << 16)
2833 #define SDE_FDI_MASK (3 << 16)
2834 #define SDE_AUXD (1 << 15)
2835 #define SDE_AUXC (1 << 14)
2836 #define SDE_AUXB (1 << 13)
2837 #define SDE_AUX_MASK (7 << 13)
2839 #define SDE_CRT_HOTPLUG (1 << 11)
2840 #define SDE_PORTD_HOTPLUG (1 << 10)
2841 #define SDE_PORTC_HOTPLUG (1 << 9)
2842 #define SDE_PORTB_HOTPLUG (1 << 8)
2843 #define SDE_SDVOB_HOTPLUG (1 << 6)
2844 #define SDE_HOTPLUG_MASK (0xf << 8)
2845 #define SDE_TRANSB_CRC_DONE (1 << 5)
2846 #define SDE_TRANSB_CRC_ERR (1 << 4)
2847 #define SDE_TRANSB_FIFO_UNDER (1 << 3)
2848 #define SDE_TRANSA_CRC_DONE (1 << 2)
2849 #define SDE_TRANSA_CRC_ERR (1 << 1)
2850 #define SDE_TRANSA_FIFO_UNDER (1 << 0)
2851 #define SDE_TRANS_MASK (0x3f)
2853 #define SDE_CRT_HOTPLUG_CPT (1 << 19)
2854 #define SDE_PORTD_HOTPLUG_CPT (1 << 23)
2855 #define SDE_PORTC_HOTPLUG_CPT (1 << 22)
2856 #define SDE_PORTB_HOTPLUG_CPT (1 << 21)
2857 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
2858 SDE_PORTD_HOTPLUG_CPT | \
2859 SDE_PORTC_HOTPLUG_CPT | \
2860 SDE_PORTB_HOTPLUG_CPT)
2862 #define SDEISR 0xc4000
2863 #define SDEIMR 0xc4004
2864 #define SDEIIR 0xc4008
2865 #define SDEIER 0xc400c
2867 /* digital port hotplug */
2868 #define PCH_PORT_HOTPLUG 0xc4030
2869 #define PORTD_HOTPLUG_ENABLE (1 << 20)
2870 #define PORTD_PULSE_DURATION_2ms (0)
2871 #define PORTD_PULSE_DURATION_4_5ms (1 << 18)
2872 #define PORTD_PULSE_DURATION_6ms (2 << 18)
2873 #define PORTD_PULSE_DURATION_100ms (3 << 18)
2874 #define PORTD_HOTPLUG_NO_DETECT (0)
2875 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
2876 #define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
2877 #define PORTC_HOTPLUG_ENABLE (1 << 12)
2878 #define PORTC_PULSE_DURATION_2ms (0)
2879 #define PORTC_PULSE_DURATION_4_5ms (1 << 10)
2880 #define PORTC_PULSE_DURATION_6ms (2 << 10)
2881 #define PORTC_PULSE_DURATION_100ms (3 << 10)
2882 #define PORTC_HOTPLUG_NO_DETECT (0)
2883 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
2884 #define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
2885 #define PORTB_HOTPLUG_ENABLE (1 << 4)
2886 #define PORTB_PULSE_DURATION_2ms (0)
2887 #define PORTB_PULSE_DURATION_4_5ms (1 << 2)
2888 #define PORTB_PULSE_DURATION_6ms (2 << 2)
2889 #define PORTB_PULSE_DURATION_100ms (3 << 2)
2890 #define PORTB_HOTPLUG_NO_DETECT (0)
2891 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
2892 #define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
2894 #define PCH_GPIOA 0xc5010
2895 #define PCH_GPIOB 0xc5014
2896 #define PCH_GPIOC 0xc5018
2897 #define PCH_GPIOD 0xc501c
2898 #define PCH_GPIOE 0xc5020
2899 #define PCH_GPIOF 0xc5024
2901 #define PCH_GMBUS0 0xc5100
2902 #define PCH_GMBUS1 0xc5104
2903 #define PCH_GMBUS2 0xc5108
2904 #define PCH_GMBUS3 0xc510c
2905 #define PCH_GMBUS4 0xc5110
2906 #define PCH_GMBUS5 0xc5120
2908 #define _PCH_DPLL_A 0xc6014
2909 #define _PCH_DPLL_B 0xc6018
2910 #define PCH_DPLL(pipe) _PIPE(pipe, _PCH_DPLL_A, _PCH_DPLL_B)
2912 #define _PCH_FPA0 0xc6040
2913 #define FP_CB_TUNE (0x3<<22)
2914 #define _PCH_FPA1 0xc6044
2915 #define _PCH_FPB0 0xc6048
2916 #define _PCH_FPB1 0xc604c
2917 #define PCH_FP0(pipe) _PIPE(pipe, _PCH_FPA0, _PCH_FPB0)
2918 #define PCH_FP1(pipe) _PIPE(pipe, _PCH_FPA1, _PCH_FPB1)
2920 #define PCH_DPLL_TEST 0xc606c
2922 #define PCH_DREF_CONTROL 0xC6200
2923 #define DREF_CONTROL_MASK 0x7fc3
2924 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
2925 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
2926 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
2927 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
2928 #define DREF_SSC_SOURCE_DISABLE (0<<11)
2929 #define DREF_SSC_SOURCE_ENABLE (2<<11)
2930 #define DREF_SSC_SOURCE_MASK (3<<11)
2931 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
2932 #define DREF_NONSPREAD_CK505_ENABLE (1<<9)
2933 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
2934 #define DREF_NONSPREAD_SOURCE_MASK (3<<9)
2935 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
2936 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
2937 #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
2938 #define DREF_SSC4_DOWNSPREAD (0<<6)
2939 #define DREF_SSC4_CENTERSPREAD (1<<6)
2940 #define DREF_SSC1_DISABLE (0<<1)
2941 #define DREF_SSC1_ENABLE (1<<1)
2942 #define DREF_SSC4_DISABLE (0)
2943 #define DREF_SSC4_ENABLE (1)
2945 #define PCH_RAWCLK_FREQ 0xc6204
2946 #define FDL_TP1_TIMER_SHIFT 12
2947 #define FDL_TP1_TIMER_MASK (3<<12)
2948 #define FDL_TP2_TIMER_SHIFT 10
2949 #define FDL_TP2_TIMER_MASK (3<<10)
2950 #define RAWCLK_FREQ_MASK 0x3ff
2952 #define PCH_DPLL_TMR_CFG 0xc6208
2954 #define PCH_SSC4_PARMS 0xc6210
2955 #define PCH_SSC4_AUX_PARMS 0xc6214
2957 #define PCH_DPLL_SEL 0xc7000
2958 #define TRANSA_DPLL_ENABLE (1<<3)
2959 #define TRANSA_DPLLB_SEL (1<<0)
2960 #define TRANSA_DPLLA_SEL 0
2961 #define TRANSB_DPLL_ENABLE (1<<7)
2962 #define TRANSB_DPLLB_SEL (1<<4)
2963 #define TRANSB_DPLLA_SEL (0)
2964 #define TRANSC_DPLL_ENABLE (1<<11)
2965 #define TRANSC_DPLLB_SEL (1<<8)
2966 #define TRANSC_DPLLA_SEL (0)
2970 #define _TRANS_HTOTAL_A 0xe0000
2971 #define TRANS_HTOTAL_SHIFT 16
2972 #define TRANS_HACTIVE_SHIFT 0
2973 #define _TRANS_HBLANK_A 0xe0004
2974 #define TRANS_HBLANK_END_SHIFT 16
2975 #define TRANS_HBLANK_START_SHIFT 0
2976 #define _TRANS_HSYNC_A 0xe0008
2977 #define TRANS_HSYNC_END_SHIFT 16
2978 #define TRANS_HSYNC_START_SHIFT 0
2979 #define _TRANS_VTOTAL_A 0xe000c
2980 #define TRANS_VTOTAL_SHIFT 16
2981 #define TRANS_VACTIVE_SHIFT 0
2982 #define _TRANS_VBLANK_A 0xe0010
2983 #define TRANS_VBLANK_END_SHIFT 16
2984 #define TRANS_VBLANK_START_SHIFT 0
2985 #define _TRANS_VSYNC_A 0xe0014
2986 #define TRANS_VSYNC_END_SHIFT 16
2987 #define TRANS_VSYNC_START_SHIFT 0
2989 #define _TRANSA_DATA_M1 0xe0030
2990 #define _TRANSA_DATA_N1 0xe0034
2991 #define _TRANSA_DATA_M2 0xe0038
2992 #define _TRANSA_DATA_N2 0xe003c
2993 #define _TRANSA_DP_LINK_M1 0xe0040
2994 #define _TRANSA_DP_LINK_N1 0xe0044
2995 #define _TRANSA_DP_LINK_M2 0xe0048
2996 #define _TRANSA_DP_LINK_N2 0xe004c
2998 #define _TRANS_HTOTAL_B 0xe1000
2999 #define _TRANS_HBLANK_B 0xe1004
3000 #define _TRANS_HSYNC_B 0xe1008
3001 #define _TRANS_VTOTAL_B 0xe100c
3002 #define _TRANS_VBLANK_B 0xe1010
3003 #define _TRANS_VSYNC_B 0xe1014
3005 #define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B)
3006 #define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B)
3007 #define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B)
3008 #define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B)
3009 #define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B)
3010 #define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B)
3012 #define _TRANSB_DATA_M1 0xe1030
3013 #define _TRANSB_DATA_N1 0xe1034
3014 #define _TRANSB_DATA_M2 0xe1038
3015 #define _TRANSB_DATA_N2 0xe103c
3016 #define _TRANSB_DP_LINK_M1 0xe1040
3017 #define _TRANSB_DP_LINK_N1 0xe1044
3018 #define _TRANSB_DP_LINK_M2 0xe1048
3019 #define _TRANSB_DP_LINK_N2 0xe104c
3021 #define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1)
3022 #define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1)
3023 #define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2)
3024 #define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2)
3025 #define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1)
3026 #define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1)
3027 #define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2)
3028 #define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2)
3030 #define _TRANSACONF 0xf0008
3031 #define _TRANSBCONF 0xf1008
3032 #define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF)
3033 #define TRANS_DISABLE (0<<31)
3034 #define TRANS_ENABLE (1<<31)
3035 #define TRANS_STATE_MASK (1<<30)
3036 #define TRANS_STATE_DISABLE (0<<30)
3037 #define TRANS_STATE_ENABLE (1<<30)
3038 #define TRANS_FSYNC_DELAY_HB1 (0<<27)
3039 #define TRANS_FSYNC_DELAY_HB2 (1<<27)
3040 #define TRANS_FSYNC_DELAY_HB3 (2<<27)
3041 #define TRANS_FSYNC_DELAY_HB4 (3<<27)
3042 #define TRANS_DP_AUDIO_ONLY (1<<26)
3043 #define TRANS_DP_VIDEO_AUDIO (0<<26)
3044 #define TRANS_PROGRESSIVE (0<<21)
3045 #define TRANS_8BPC (0<<5)
3046 #define TRANS_10BPC (1<<5)
3047 #define TRANS_6BPC (2<<5)
3048 #define TRANS_12BPC (3<<5)
3050 #define _FDI_RXA_CHICKEN 0xc200c
3051 #define _FDI_RXB_CHICKEN 0xc2010
3052 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
3053 #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
3054 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
3056 #define SOUTH_DSPCLK_GATE_D 0xc2020
3057 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
3060 #define _FDI_TXA_CTL 0x60100
3061 #define _FDI_TXB_CTL 0x61100
3062 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
3063 #define FDI_TX_DISABLE (0<<31)
3064 #define FDI_TX_ENABLE (1<<31)
3065 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
3066 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
3067 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
3068 #define FDI_LINK_TRAIN_NONE (3<<28)
3069 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
3070 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
3071 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
3072 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
3073 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
3074 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
3075 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
3076 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
3077 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
3078 SNB has different settings. */
3079 /* SNB A-stepping */
3080 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
3081 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
3082 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
3083 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
3084 /* SNB B-stepping */
3085 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
3086 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
3087 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
3088 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
3089 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
3090 #define FDI_DP_PORT_WIDTH_X1 (0<<19)
3091 #define FDI_DP_PORT_WIDTH_X2 (1<<19)
3092 #define FDI_DP_PORT_WIDTH_X3 (2<<19)
3093 #define FDI_DP_PORT_WIDTH_X4 (3<<19)
3094 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
3095 /* Ironlake: hardwired to 1 */
3096 #define FDI_TX_PLL_ENABLE (1<<14)
3097 /* both Tx and Rx */
3098 #define FDI_SCRAMBLING_ENABLE (0<<7)
3099 #define FDI_SCRAMBLING_DISABLE (1<<7)
3101 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
3102 #define _FDI_RXA_CTL 0xf000c
3103 #define _FDI_RXB_CTL 0xf100c
3104 #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
3105 #define FDI_RX_ENABLE (1<<31)
3106 /* train, dp width same as FDI_TX */
3107 #define FDI_DP_PORT_WIDTH_X8 (7<<19)
3108 #define FDI_8BPC (0<<16)
3109 #define FDI_10BPC (1<<16)
3110 #define FDI_6BPC (2<<16)
3111 #define FDI_12BPC (3<<16)
3112 #define FDI_LINK_REVERSE_OVERWRITE (1<<15)
3113 #define FDI_DMI_LINK_REVERSE_MASK (1<<14)
3114 #define FDI_RX_PLL_ENABLE (1<<13)
3115 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
3116 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
3117 #define FDI_FS_ERR_REPORT_ENABLE (1<<9)
3118 #define FDI_FE_ERR_REPORT_ENABLE (1<<8)
3119 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
3120 #define FDI_PCDCLK (1<<4)
3122 #define FDI_AUTO_TRAINING (1<<10)
3123 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
3124 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
3125 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
3126 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
3127 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
3129 #define _FDI_RXA_MISC 0xf0010
3130 #define _FDI_RXB_MISC 0xf1010
3131 #define _FDI_RXA_TUSIZE1 0xf0030
3132 #define _FDI_RXA_TUSIZE2 0xf0038
3133 #define _FDI_RXB_TUSIZE1 0xf1030
3134 #define _FDI_RXB_TUSIZE2 0xf1038
3135 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
3136 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
3137 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
3139 /* FDI_RX interrupt register format */
3140 #define FDI_RX_INTER_LANE_ALIGN (1<<10)
3141 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
3142 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
3143 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
3144 #define FDI_RX_FS_CODE_ERR (1<<6)
3145 #define FDI_RX_FE_CODE_ERR (1<<5)
3146 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
3147 #define FDI_RX_HDCP_LINK_FAIL (1<<3)
3148 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
3149 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
3150 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
3152 #define _FDI_RXA_IIR 0xf0014
3153 #define _FDI_RXA_IMR 0xf0018
3154 #define _FDI_RXB_IIR 0xf1014
3155 #define _FDI_RXB_IMR 0xf1018
3156 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
3157 #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
3159 #define FDI_PLL_CTL_1 0xfe000
3160 #define FDI_PLL_CTL_2 0xfe004
3163 #define PCH_ADPA 0xe1100
3164 #define ADPA_TRANS_SELECT_MASK (1<<30)
3165 #define ADPA_TRANS_A_SELECT 0
3166 #define ADPA_TRANS_B_SELECT (1<<30)
3167 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
3168 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
3169 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
3170 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
3171 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
3172 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
3173 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
3174 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
3175 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
3176 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
3177 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
3178 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
3179 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
3180 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
3181 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
3182 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
3183 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
3184 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
3185 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
3187 #define ADPA_PIPE_ENABLED(V, P) \
3188 (((V) & (ADPA_TRANS_SELECT_MASK | ADPA_DAC_ENABLE)) == ((P) << 30 | ADPA_DAC_ENABLE))
3191 #define HDMIB 0xe1140
3192 #define PORT_ENABLE (1 << 31)
3193 #define TRANSCODER_A (0)
3194 #define TRANSCODER_B (1 << 30)
3195 #define TRANSCODER_MASK (1 << 30)
3196 #define COLOR_FORMAT_8bpc (0)
3197 #define COLOR_FORMAT_12bpc (3 << 26)
3198 #define SDVOB_HOTPLUG_ENABLE (1 << 23)
3199 #define SDVO_ENCODING (0)
3200 #define TMDS_ENCODING (2 << 10)
3201 #define NULL_PACKET_VSYNC_ENABLE (1 << 9)
3203 #define HDMI_MODE_SELECT (1 << 9)
3204 #define DVI_MODE_SELECT (0)
3205 #define SDVOB_BORDER_ENABLE (1 << 7)
3206 #define AUDIO_ENABLE (1 << 6)
3207 #define VSYNC_ACTIVE_HIGH (1 << 4)
3208 #define HSYNC_ACTIVE_HIGH (1 << 3)
3209 #define PORT_DETECTED (1 << 2)
3211 #define HDMI_PIPE_ENABLED(V, P) \
3212 (((V) & (TRANSCODER_MASK | PORT_ENABLE)) == ((P) << 30 | PORT_ENABLE))
3214 /* PCH SDVOB multiplex with HDMIB */
3215 #define PCH_SDVOB HDMIB
3217 #define HDMIC 0xe1150
3218 #define HDMID 0xe1160
3220 #define PCH_LVDS 0xe1180
3221 #define LVDS_DETECTED (1 << 1)
3223 #define BLC_PWM_CPU_CTL2 0x48250
3224 #define PWM_ENABLE (1 << 31)
3225 #define PWM_PIPE_A (0 << 29)
3226 #define PWM_PIPE_B (1 << 29)
3227 #define BLC_PWM_CPU_CTL 0x48254
3229 #define BLC_PWM_PCH_CTL1 0xc8250
3230 #define PWM_PCH_ENABLE (1 << 31)
3231 #define PWM_POLARITY_ACTIVE_LOW (1 << 29)
3232 #define PWM_POLARITY_ACTIVE_HIGH (0 << 29)
3233 #define PWM_POLARITY_ACTIVE_LOW2 (1 << 28)
3234 #define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
3236 #define BLC_PWM_PCH_CTL2 0xc8254
3238 #define PCH_PP_STATUS 0xc7200
3239 #define PCH_PP_CONTROL 0xc7204
3240 #define PANEL_UNLOCK_REGS (0xabcd << 16)
3241 #define EDP_FORCE_VDD (1 << 3)
3242 #define EDP_BLC_ENABLE (1 << 2)
3243 #define PANEL_POWER_RESET (1 << 1)
3244 #define PANEL_POWER_OFF (0 << 0)
3245 #define PANEL_POWER_ON (1 << 0)
3246 #define PCH_PP_ON_DELAYS 0xc7208
3247 #define EDP_PANEL (1 << 30)
3248 #define PCH_PP_OFF_DELAYS 0xc720c
3249 #define PCH_PP_DIVISOR 0xc7210
3251 #define PCH_DP_B 0xe4100
3252 #define PCH_DPB_AUX_CH_CTL 0xe4110
3253 #define PCH_DPB_AUX_CH_DATA1 0xe4114
3254 #define PCH_DPB_AUX_CH_DATA2 0xe4118
3255 #define PCH_DPB_AUX_CH_DATA3 0xe411c
3256 #define PCH_DPB_AUX_CH_DATA4 0xe4120
3257 #define PCH_DPB_AUX_CH_DATA5 0xe4124
3259 #define PCH_DP_C 0xe4200
3260 #define PCH_DPC_AUX_CH_CTL 0xe4210
3261 #define PCH_DPC_AUX_CH_DATA1 0xe4214
3262 #define PCH_DPC_AUX_CH_DATA2 0xe4218
3263 #define PCH_DPC_AUX_CH_DATA3 0xe421c
3264 #define PCH_DPC_AUX_CH_DATA4 0xe4220
3265 #define PCH_DPC_AUX_CH_DATA5 0xe4224
3267 #define PCH_DP_D 0xe4300
3268 #define PCH_DPD_AUX_CH_CTL 0xe4310
3269 #define PCH_DPD_AUX_CH_DATA1 0xe4314
3270 #define PCH_DPD_AUX_CH_DATA2 0xe4318
3271 #define PCH_DPD_AUX_CH_DATA3 0xe431c
3272 #define PCH_DPD_AUX_CH_DATA4 0xe4320
3273 #define PCH_DPD_AUX_CH_DATA5 0xe4324
3276 #define PORT_TRANS_A_SEL_CPT 0
3277 #define PORT_TRANS_B_SEL_CPT (1<<29)
3278 #define PORT_TRANS_C_SEL_CPT (2<<29)
3279 #define PORT_TRANS_SEL_MASK (3<<29)
3281 #define TRANS_DP_CTL_A 0xe0300
3282 #define TRANS_DP_CTL_B 0xe1300
3283 #define TRANS_DP_CTL_C 0xe2300
3284 #define TRANS_DP_CTL(pipe) (TRANS_DP_CTL_A + (pipe) * 0x01000)
3285 #define TRANS_DP_OUTPUT_ENABLE (1<<31)
3286 #define TRANS_DP_PORT_SEL_B (0<<29)
3287 #define TRANS_DP_PORT_SEL_C (1<<29)
3288 #define TRANS_DP_PORT_SEL_D (2<<29)
3289 #define TRANS_DP_PORT_SEL_NONE (3<<29)
3290 #define TRANS_DP_PORT_SEL_MASK (3<<29)
3291 #define TRANS_DP_AUDIO_ONLY (1<<26)
3292 #define TRANS_DP_ENH_FRAMING (1<<18)
3293 #define TRANS_DP_8BPC (0<<9)
3294 #define TRANS_DP_10BPC (1<<9)
3295 #define TRANS_DP_6BPC (2<<9)
3296 #define TRANS_DP_12BPC (3<<9)
3297 #define TRANS_DP_BPC_MASK (3<<9)
3298 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
3299 #define TRANS_DP_VSYNC_ACTIVE_LOW 0
3300 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
3301 #define TRANS_DP_HSYNC_ACTIVE_LOW 0
3302 #define TRANS_DP_SYNC_MASK (3<<3)
3304 /* SNB eDP training params */
3305 /* SNB A-stepping */
3306 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
3307 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
3308 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
3309 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
3310 /* SNB B-stepping */
3311 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
3312 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
3313 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
3314 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
3315 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
3316 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
3318 #define FORCEWAKE 0xA18C
3319 #define FORCEWAKE_ACK 0x130090
3321 #define GT_FIFO_FREE_ENTRIES 0x120008
3323 #define GEN6_RPNSWREQ 0xA008
3324 #define GEN6_TURBO_DISABLE (1<<31)
3325 #define GEN6_FREQUENCY(x) ((x)<<25)
3326 #define GEN6_OFFSET(x) ((x)<<19)
3327 #define GEN6_AGGRESSIVE_TURBO (0<<15)
3328 #define GEN6_RC_VIDEO_FREQ 0xA00C
3329 #define GEN6_RC_CONTROL 0xA090
3330 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
3331 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
3332 #define GEN6_RC_CTL_RC6_ENABLE (1<<18)
3333 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
3334 #define GEN6_RC_CTL_RC7_ENABLE (1<<22)
3335 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
3336 #define GEN6_RC_CTL_HW_ENABLE (1<<31)
3337 #define GEN6_RP_DOWN_TIMEOUT 0xA010
3338 #define GEN6_RP_INTERRUPT_LIMITS 0xA014
3339 #define GEN6_RPSTAT1 0xA01C
3340 #define GEN6_CAGF_SHIFT 8
3341 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
3342 #define GEN6_RP_CONTROL 0xA024
3343 #define GEN6_RP_MEDIA_TURBO (1<<11)
3344 #define GEN6_RP_USE_NORMAL_FREQ (1<<9)
3345 #define GEN6_RP_MEDIA_IS_GFX (1<<8)
3346 #define GEN6_RP_ENABLE (1<<7)
3347 #define GEN6_RP_UP_IDLE_MIN (0x1<<3)
3348 #define GEN6_RP_UP_BUSY_AVG (0x2<<3)
3349 #define GEN6_RP_UP_BUSY_CONT (0x4<<3)
3350 #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
3351 #define GEN6_RP_UP_THRESHOLD 0xA02C
3352 #define GEN6_RP_DOWN_THRESHOLD 0xA030
3353 #define GEN6_RP_CUR_UP_EI 0xA050
3354 #define GEN6_CURICONT_MASK 0xffffff
3355 #define GEN6_RP_CUR_UP 0xA054
3356 #define GEN6_CURBSYTAVG_MASK 0xffffff
3357 #define GEN6_RP_PREV_UP 0xA058
3358 #define GEN6_RP_CUR_DOWN_EI 0xA05C
3359 #define GEN6_CURIAVG_MASK 0xffffff
3360 #define GEN6_RP_CUR_DOWN 0xA060
3361 #define GEN6_RP_PREV_DOWN 0xA064
3362 #define GEN6_RP_UP_EI 0xA068
3363 #define GEN6_RP_DOWN_EI 0xA06C
3364 #define GEN6_RP_IDLE_HYSTERSIS 0xA070
3365 #define GEN6_RC_STATE 0xA094
3366 #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
3367 #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
3368 #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
3369 #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
3370 #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
3371 #define GEN6_RC_SLEEP 0xA0B0
3372 #define GEN6_RC1e_THRESHOLD 0xA0B4
3373 #define GEN6_RC6_THRESHOLD 0xA0B8
3374 #define GEN6_RC6p_THRESHOLD 0xA0BC
3375 #define GEN6_RC6pp_THRESHOLD 0xA0C0
3376 #define GEN6_PMINTRMSK 0xA168
3378 #define GEN6_PMISR 0x44020
3379 #define GEN6_PMIMR 0x44024
3380 #define GEN6_PMIIR 0x44028
3381 #define GEN6_PMIER 0x4402C
3382 #define GEN6_PM_MBOX_EVENT (1<<25)
3383 #define GEN6_PM_THERMAL_EVENT (1<<24)
3384 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
3385 #define GEN6_PM_RP_UP_THRESHOLD (1<<5)
3386 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
3387 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
3388 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
3390 #define GEN6_PCODE_MAILBOX 0x138124
3391 #define GEN6_PCODE_READY (1<<31)
3392 #define GEN6_READ_OC_PARAMS 0xc
3393 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x9
3394 #define GEN6_PCODE_DATA 0x138128
3396 #endif /* _I915_REG_H_ */
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