2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include <linux/firmware.h>
29 * DOC: csr support for dmc
31 * Display Context Save and Restore (CSR) firmware support added from gen9
32 * onwards to drive newly added DMC (Display microcontroller) in display
33 * engine to save and restore the state of display engine when it enter into
34 * low-power state and comes back to normal.
36 * Firmware loading status will be one of the below states: FW_UNINITIALIZED,
37 * FW_LOADED, FW_FAILED.
39 * Once the firmware is written into the registers status will be moved from
40 * FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will
41 * be moved to FW_FAILED.
44 #define I915_CSR_KBL "i915/kbl_dmc_ver1.bin"
45 MODULE_FIRMWARE(I915_CSR_KBL
);
46 #define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 1)
48 #define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
49 MODULE_FIRMWARE(I915_CSR_SKL
);
50 #define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 23)
52 #define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
53 MODULE_FIRMWARE(I915_CSR_BXT
);
54 #define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
56 #define FIRMWARE_URL "https://01.org/linuxgraphics/intel-linux-graphics-firmwares"
61 #define CSR_MAX_FW_SIZE 0x2FFF
62 #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
64 struct intel_css_header
{
68 /* Includes the DMC specific header in dwords */
71 /* always value would be 0x10000 */
78 uint32_t module_vendor
;
80 /* in YYYYMMDD format */
83 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
90 uint32_t modulus_size
;
93 uint32_t exponent_size
;
96 uint32_t reserved1
[12];
102 uint32_t reserved2
[8];
105 uint32_t kernel_header_info
;
108 struct intel_fw_info
{
111 /* Stepping (A, B, C, ..., *). * is a wildcard */
114 /* Sub-stepping (0, 1, ..., *). * is a wildcard */
121 struct intel_package_header
{
122 /* DMC container header length in dwords */
123 unsigned char header_len
;
125 /* always value would be 0x01 */
126 unsigned char header_ver
;
128 unsigned char reserved
[10];
130 /* Number of valid entries in the FWInfo array below */
131 uint32_t num_entries
;
133 struct intel_fw_info fw_info
[20];
136 struct intel_dmc_header
{
137 /* always value would be 0x40403E3E */
140 /* DMC binary header length */
141 unsigned char header_len
;
144 unsigned char header_ver
;
152 /* Firmware program size (excluding header) in dwords */
155 /* Major Minor version */
158 /* Number of valid MMIO cycles present. */
162 uint32_t mmioaddr
[8];
165 uint32_t mmiodata
[8];
168 unsigned char dfile
[32];
170 uint32_t reserved1
[2];
173 struct stepping_info
{
178 static const struct stepping_info kbl_stepping_info
[] = {
179 {'A', '0'}, {'B', '0'}, {'C', '0'},
180 {'D', '0'}, {'E', '0'}, {'F', '0'},
181 {'G', '0'}, {'H', '0'}, {'I', '0'},
184 static const struct stepping_info skl_stepping_info
[] = {
185 {'A', '0'}, {'B', '0'}, {'C', '0'},
186 {'D', '0'}, {'E', '0'}, {'F', '0'},
187 {'G', '0'}, {'H', '0'}, {'I', '0'},
188 {'J', '0'}, {'K', '0'}
191 static const struct stepping_info bxt_stepping_info
[] = {
192 {'A', '0'}, {'A', '1'}, {'A', '2'},
193 {'B', '0'}, {'B', '1'}, {'B', '2'}
196 static const struct stepping_info no_stepping_info
= { '*', '*' };
198 static const struct stepping_info
*
199 intel_get_stepping_info(struct drm_i915_private
*dev_priv
)
201 const struct stepping_info
*si
;
204 if (IS_KABYLAKE(dev_priv
)) {
205 size
= ARRAY_SIZE(kbl_stepping_info
);
206 si
= kbl_stepping_info
;
207 } else if (IS_SKYLAKE(dev_priv
)) {
208 size
= ARRAY_SIZE(skl_stepping_info
);
209 si
= skl_stepping_info
;
210 } else if (IS_BROXTON(dev_priv
)) {
211 size
= ARRAY_SIZE(bxt_stepping_info
);
212 si
= bxt_stepping_info
;
217 if (INTEL_REVID(dev_priv
) < size
)
218 return si
+ INTEL_REVID(dev_priv
);
220 return &no_stepping_info
;
223 static void gen9_set_dc_state_debugmask(struct drm_i915_private
*dev_priv
)
227 mask
= DC_STATE_DEBUG_MASK_MEMORY_UP
;
229 if (IS_BROXTON(dev_priv
))
230 mask
|= DC_STATE_DEBUG_MASK_CORES
;
232 /* The below bit doesn't need to be cleared ever afterwards */
233 val
= I915_READ(DC_STATE_DEBUG
);
234 if ((val
& mask
) != mask
) {
236 I915_WRITE(DC_STATE_DEBUG
, val
);
237 POSTING_READ(DC_STATE_DEBUG
);
242 * intel_csr_load_program() - write the firmware from memory to register.
243 * @dev_priv: i915 drm device.
245 * CSR firmware is read from a .bin file and kept in internal memory one time.
246 * Everytime display comes back from low power state this function is called to
247 * copy the firmware from internal memory to registers.
249 void intel_csr_load_program(struct drm_i915_private
*dev_priv
)
251 u32
*payload
= dev_priv
->csr
.dmc_payload
;
254 if (!IS_GEN9(dev_priv
)) {
255 DRM_ERROR("No CSR support available for this platform\n");
259 if (!dev_priv
->csr
.dmc_payload
) {
260 DRM_ERROR("Tried to program CSR with empty payload\n");
264 fw_size
= dev_priv
->csr
.dmc_fw_size
;
265 for (i
= 0; i
< fw_size
; i
++)
266 I915_WRITE(CSR_PROGRAM(i
), payload
[i
]);
268 for (i
= 0; i
< dev_priv
->csr
.mmio_count
; i
++) {
269 I915_WRITE(dev_priv
->csr
.mmioaddr
[i
],
270 dev_priv
->csr
.mmiodata
[i
]);
273 dev_priv
->csr
.dc_state
= 0;
275 gen9_set_dc_state_debugmask(dev_priv
);
278 static uint32_t *parse_csr_fw(struct drm_i915_private
*dev_priv
,
279 const struct firmware
*fw
)
281 struct intel_css_header
*css_header
;
282 struct intel_package_header
*package_header
;
283 struct intel_dmc_header
*dmc_header
;
284 struct intel_csr
*csr
= &dev_priv
->csr
;
285 const struct stepping_info
*si
= intel_get_stepping_info(dev_priv
);
286 uint32_t dmc_offset
= CSR_DEFAULT_FW_OFFSET
, readcount
= 0, nbytes
;
288 uint32_t *dmc_payload
;
289 uint32_t required_version
;
294 /* Extract CSS Header information*/
295 css_header
= (struct intel_css_header
*)fw
->data
;
296 if (sizeof(struct intel_css_header
) !=
297 (css_header
->header_len
* 4)) {
298 DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
299 (css_header
->header_len
* 4));
303 csr
->version
= css_header
->version
;
305 if (IS_KABYLAKE(dev_priv
)) {
306 required_version
= KBL_CSR_VERSION_REQUIRED
;
307 } else if (IS_SKYLAKE(dev_priv
)) {
308 required_version
= SKL_CSR_VERSION_REQUIRED
;
309 } else if (IS_BROXTON(dev_priv
)) {
310 required_version
= BXT_CSR_VERSION_REQUIRED
;
312 MISSING_CASE(INTEL_REVID(dev_priv
));
313 required_version
= 0;
316 if (csr
->version
!= required_version
) {
317 DRM_INFO("Refusing to load DMC firmware v%u.%u,"
318 " please use v%u.%u [" FIRMWARE_URL
"].\n",
319 CSR_VERSION_MAJOR(csr
->version
),
320 CSR_VERSION_MINOR(csr
->version
),
321 CSR_VERSION_MAJOR(required_version
),
322 CSR_VERSION_MINOR(required_version
));
326 readcount
+= sizeof(struct intel_css_header
);
328 /* Extract Package Header information*/
329 package_header
= (struct intel_package_header
*)
330 &fw
->data
[readcount
];
331 if (sizeof(struct intel_package_header
) !=
332 (package_header
->header_len
* 4)) {
333 DRM_ERROR("Firmware has wrong package header length %u bytes\n",
334 (package_header
->header_len
* 4));
337 readcount
+= sizeof(struct intel_package_header
);
339 /* Search for dmc_offset to find firware binary. */
340 for (i
= 0; i
< package_header
->num_entries
; i
++) {
341 if (package_header
->fw_info
[i
].substepping
== '*' &&
342 si
->stepping
== package_header
->fw_info
[i
].stepping
) {
343 dmc_offset
= package_header
->fw_info
[i
].offset
;
345 } else if (si
->stepping
== package_header
->fw_info
[i
].stepping
&&
346 si
->substepping
== package_header
->fw_info
[i
].substepping
) {
347 dmc_offset
= package_header
->fw_info
[i
].offset
;
349 } else if (package_header
->fw_info
[i
].stepping
== '*' &&
350 package_header
->fw_info
[i
].substepping
== '*')
351 dmc_offset
= package_header
->fw_info
[i
].offset
;
353 if (dmc_offset
== CSR_DEFAULT_FW_OFFSET
) {
354 DRM_ERROR("Firmware not supported for %c stepping\n",
358 readcount
+= dmc_offset
;
360 /* Extract dmc_header information. */
361 dmc_header
= (struct intel_dmc_header
*)&fw
->data
[readcount
];
362 if (sizeof(struct intel_dmc_header
) != (dmc_header
->header_len
)) {
363 DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
364 (dmc_header
->header_len
));
367 readcount
+= sizeof(struct intel_dmc_header
);
369 /* Cache the dmc header info. */
370 if (dmc_header
->mmio_count
> ARRAY_SIZE(csr
->mmioaddr
)) {
371 DRM_ERROR("Firmware has wrong mmio count %u\n",
372 dmc_header
->mmio_count
);
375 csr
->mmio_count
= dmc_header
->mmio_count
;
376 for (i
= 0; i
< dmc_header
->mmio_count
; i
++) {
377 if (dmc_header
->mmioaddr
[i
] < CSR_MMIO_START_RANGE
||
378 dmc_header
->mmioaddr
[i
] > CSR_MMIO_END_RANGE
) {
379 DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
380 dmc_header
->mmioaddr
[i
]);
383 csr
->mmioaddr
[i
] = _MMIO(dmc_header
->mmioaddr
[i
]);
384 csr
->mmiodata
[i
] = dmc_header
->mmiodata
[i
];
387 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
388 nbytes
= dmc_header
->fw_size
* 4;
389 if (nbytes
> CSR_MAX_FW_SIZE
) {
390 DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes
);
393 csr
->dmc_fw_size
= dmc_header
->fw_size
;
395 dmc_payload
= kmalloc(nbytes
, GFP_KERNEL
);
397 DRM_ERROR("Memory allocation failed for dmc payload\n");
401 return memcpy(dmc_payload
, &fw
->data
[readcount
], nbytes
);
404 static void csr_load_work_fn(struct work_struct
*work
)
406 struct drm_i915_private
*dev_priv
;
407 struct intel_csr
*csr
;
408 const struct firmware
*fw
;
411 dev_priv
= container_of(work
, typeof(*dev_priv
), csr
.work
);
412 csr
= &dev_priv
->csr
;
414 ret
= request_firmware(&fw
, dev_priv
->csr
.fw_path
,
415 &dev_priv
->drm
.pdev
->dev
);
417 dev_priv
->csr
.dmc_payload
= parse_csr_fw(dev_priv
, fw
);
419 if (dev_priv
->csr
.dmc_payload
) {
420 intel_csr_load_program(dev_priv
);
422 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
424 DRM_INFO("Finished loading %s (v%u.%u)\n",
425 dev_priv
->csr
.fw_path
,
426 CSR_VERSION_MAJOR(csr
->version
),
427 CSR_VERSION_MINOR(csr
->version
));
429 dev_notice(dev_priv
->drm
.dev
,
430 "Failed to load DMC firmware"
431 " [" FIRMWARE_URL
"],"
432 " disabling runtime power management.\n");
435 release_firmware(fw
);
439 * intel_csr_ucode_init() - initialize the firmware loading.
440 * @dev_priv: i915 drm device.
442 * This function is called at the time of loading the display driver to read
443 * firmware from a .bin file and copied into a internal memory.
445 void intel_csr_ucode_init(struct drm_i915_private
*dev_priv
)
447 struct intel_csr
*csr
= &dev_priv
->csr
;
449 INIT_WORK(&dev_priv
->csr
.work
, csr_load_work_fn
);
451 if (!HAS_CSR(dev_priv
))
454 if (IS_KABYLAKE(dev_priv
))
455 csr
->fw_path
= I915_CSR_KBL
;
456 else if (IS_SKYLAKE(dev_priv
))
457 csr
->fw_path
= I915_CSR_SKL
;
458 else if (IS_BROXTON(dev_priv
))
459 csr
->fw_path
= I915_CSR_BXT
;
461 DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
465 DRM_DEBUG_KMS("Loading %s\n", csr
->fw_path
);
468 * Obtain a runtime pm reference, until CSR is loaded,
469 * to avoid entering runtime-suspend.
471 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
473 schedule_work(&dev_priv
->csr
.work
);
477 * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
478 * @dev_priv: i915 drm device
480 * Prepare the DMC firmware before entering system suspend. This includes
481 * flushing pending work items and releasing any resources acquired during
484 void intel_csr_ucode_suspend(struct drm_i915_private
*dev_priv
)
486 if (!HAS_CSR(dev_priv
))
489 flush_work(&dev_priv
->csr
.work
);
491 /* Drop the reference held in case DMC isn't loaded. */
492 if (!dev_priv
->csr
.dmc_payload
)
493 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
497 * intel_csr_ucode_resume() - init CSR firmware during system resume
498 * @dev_priv: i915 drm device
500 * Reinitialize the DMC firmware during system resume, reacquiring any
501 * resources released in intel_csr_ucode_suspend().
503 void intel_csr_ucode_resume(struct drm_i915_private
*dev_priv
)
505 if (!HAS_CSR(dev_priv
))
509 * Reacquire the reference to keep RPM disabled in case DMC isn't
512 if (!dev_priv
->csr
.dmc_payload
)
513 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
517 * intel_csr_ucode_fini() - unload the CSR firmware.
518 * @dev_priv: i915 drm device.
520 * Firmmware unloading includes freeing the internal memory and reset the
521 * firmware loading status.
523 void intel_csr_ucode_fini(struct drm_i915_private
*dev_priv
)
525 if (!HAS_CSR(dev_priv
))
528 intel_csr_ucode_suspend(dev_priv
);
530 kfree(dev_priv
->csr
.dmc_payload
);