2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 struct ddi_buf_trans
{
32 u32 trans1
; /* balance leg enable, de-emph level */
33 u32 trans2
; /* vref sel, vswing */
34 u8 i_boost
; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
37 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
41 static const struct ddi_buf_trans hsw_ddi_translations_dp
[] = {
42 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
53 static const struct ddi_buf_trans hsw_ddi_translations_fdi
[] = {
54 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
65 static const struct ddi_buf_trans hsw_ddi_translations_hdmi
[] = {
66 /* Idx NT mV d T mV d db */
67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
81 static const struct ddi_buf_trans bdw_ddi_translations_edp
[] = {
82 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
93 static const struct ddi_buf_trans bdw_ddi_translations_dp
[] = {
94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
105 static const struct ddi_buf_trans bdw_ddi_translations_fdi
[] = {
106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
117 static const struct ddi_buf_trans bdw_ddi_translations_hdmi
[] = {
118 /* Idx NT mV d T mV df db */
119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
131 /* Skylake H, S, and Skylake Y with 0.95V VccIO */
132 static const struct ddi_buf_trans skl_ddi_translations_dp
[] = {
133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
136 { 0x00009010, 0x000000C7, 0x0 },
137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
139 { 0x00007011, 0x000000C7, 0x0 },
140 { 0x00002016, 0x000000DF, 0x0 },
141 { 0x00005012, 0x000000C7, 0x0 },
145 static const struct ddi_buf_trans skl_u_ddi_translations_dp
[] = {
146 { 0x00002016, 0x000000A2, 0x0 },
147 { 0x00005012, 0x00000088, 0x0 },
148 { 0x00007011, 0x00000087, 0x0 },
149 { 0x80009010, 0x000000C7, 0x1 }, /* Uses I_boost */
150 { 0x00002016, 0x0000009D, 0x0 },
151 { 0x00005012, 0x000000C7, 0x0 },
152 { 0x00007011, 0x000000C7, 0x0 },
153 { 0x00002016, 0x00000088, 0x0 },
154 { 0x00005012, 0x000000C7, 0x0 },
157 /* Skylake Y with 0.85V VccIO */
158 static const struct ddi_buf_trans skl_y_085v_ddi_translations_dp
[] = {
159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
161 { 0x00007011, 0x00000087, 0x0 },
162 { 0x80009010, 0x000000C7, 0x1 }, /* Uses I_boost */
163 { 0x00000018, 0x0000009D, 0x0 },
164 { 0x00005012, 0x000000C7, 0x0 },
165 { 0x00007011, 0x000000C7, 0x0 },
166 { 0x00000018, 0x00000088, 0x0 },
167 { 0x00005012, 0x000000C7, 0x0 },
171 * Skylake H and S, and Skylake Y with 0.95V VccIO
172 * eDP 1.4 low vswing translation parameters
174 static const struct ddi_buf_trans skl_ddi_translations_edp
[] = {
175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
189 * eDP 1.4 low vswing translation parameters
191 static const struct ddi_buf_trans skl_u_ddi_translations_edp
[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
205 * Skylake Y with 0.95V VccIO
206 * eDP 1.4 low vswing translation parameters
208 static const struct ddi_buf_trans skl_y_085v_ddi_translations_edp
[] = {
209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
221 /* Skylake H, S and U, and Skylake Y with 0.95V VccIO */
222 static const struct ddi_buf_trans skl_ddi_translations_hdmi
[] = {
223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
229 { 0x00006012, 0x00000087, 0x0 },
230 { 0x00000018, 0x000000DF, 0x0 },
231 { 0x00003015, 0x00000087, 0x0 }, /* Default */
232 { 0x00003015, 0x000000C7, 0x0 },
233 { 0x00000018, 0x000000C7, 0x0 },
236 /* Skylake Y with 0.85V VccIO */
237 static const struct ddi_buf_trans skl_y_085v_ddi_translations_hdmi
[] = {
238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
240 { 0x00007011, 0x00000084, 0x0 },
241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
244 { 0x00006013, 0x000000C7, 0x0 },
245 { 0x00000018, 0x0000008A, 0x0 },
246 { 0x00003015, 0x000000C7, 0x0 }, /* Default */
247 { 0x80003015, 0x000000C7, 0x7 }, /* Uses I_boost */
248 { 0x00000018, 0x000000C7, 0x0 },
251 struct bxt_ddi_buf_trans
{
252 u32 margin
; /* swing value */
253 u32 scale
; /* scale value */
254 u32 enable
; /* scale enable */
256 bool default_index
; /* true if the entry represents default value */
259 /* BSpec does not define separate vswing/pre-emphasis values for eDP.
260 * Using DP values for eDP as well.
262 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp
[] = {
263 /* Idx NT mV diff db */
264 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
265 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
266 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
267 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
268 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
269 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
270 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
271 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
272 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
273 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
276 /* BSpec has 2 recommended values - entries 0 and 8.
277 * Using the entry with higher vswing.
279 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi
[] = {
280 /* Idx NT mV diff db */
281 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
282 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
283 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
284 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
285 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
286 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
287 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
288 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
289 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
290 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
293 static void bxt_ddi_vswing_sequence(struct drm_device
*dev
, u32 level
,
294 enum port port
, int type
);
296 static void ddi_get_encoder_port(struct intel_encoder
*intel_encoder
,
297 struct intel_digital_port
**dig_port
,
300 struct drm_encoder
*encoder
= &intel_encoder
->base
;
301 int type
= intel_encoder
->type
;
303 if (type
== INTEL_OUTPUT_DP_MST
) {
304 *dig_port
= enc_to_mst(encoder
)->primary
;
305 *port
= (*dig_port
)->port
;
306 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
||
307 type
== INTEL_OUTPUT_HDMI
|| type
== INTEL_OUTPUT_UNKNOWN
) {
308 *dig_port
= enc_to_dig_port(encoder
);
309 *port
= (*dig_port
)->port
;
310 } else if (type
== INTEL_OUTPUT_ANALOG
) {
314 DRM_ERROR("Invalid DDI encoder type %d\n", type
);
319 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
)
321 struct intel_digital_port
*dig_port
;
324 ddi_get_encoder_port(intel_encoder
, &dig_port
, &port
);
330 intel_dig_port_supports_hdmi(const struct intel_digital_port
*intel_dig_port
)
332 return intel_dig_port
->hdmi
.hdmi_reg
;
335 static const struct ddi_buf_trans
*skl_get_buf_trans_dp(struct drm_device
*dev
,
338 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
339 const struct ddi_buf_trans
*ddi_translations
;
340 static int is_095v
= -1;
343 u32 spr1
= I915_READ(UAIMI_SPR1
);
345 is_095v
= spr1
& SKL_VCCIO_MASK
;
348 if (IS_SKL_ULX(dev
) && !is_095v
) {
349 ddi_translations
= skl_y_085v_ddi_translations_dp
;
350 *n_entries
= ARRAY_SIZE(skl_y_085v_ddi_translations_dp
);
351 } else if (IS_SKL_ULT(dev
)) {
352 ddi_translations
= skl_u_ddi_translations_dp
;
353 *n_entries
= ARRAY_SIZE(skl_u_ddi_translations_dp
);
355 ddi_translations
= skl_ddi_translations_dp
;
356 *n_entries
= ARRAY_SIZE(skl_ddi_translations_dp
);
359 return ddi_translations
;
362 static const struct ddi_buf_trans
*skl_get_buf_trans_edp(struct drm_device
*dev
,
365 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
366 const struct ddi_buf_trans
*ddi_translations
;
367 static int is_095v
= -1;
370 u32 spr1
= I915_READ(UAIMI_SPR1
);
372 is_095v
= spr1
& SKL_VCCIO_MASK
;
375 if (IS_SKL_ULX(dev
) && !is_095v
) {
376 if (dev_priv
->edp_low_vswing
) {
377 ddi_translations
= skl_y_085v_ddi_translations_edp
;
379 ARRAY_SIZE(skl_y_085v_ddi_translations_edp
);
381 ddi_translations
= skl_y_085v_ddi_translations_dp
;
383 ARRAY_SIZE(skl_y_085v_ddi_translations_dp
);
385 } else if (IS_SKL_ULT(dev
)) {
386 if (dev_priv
->edp_low_vswing
) {
387 ddi_translations
= skl_u_ddi_translations_edp
;
388 *n_entries
= ARRAY_SIZE(skl_u_ddi_translations_edp
);
390 ddi_translations
= skl_u_ddi_translations_dp
;
391 *n_entries
= ARRAY_SIZE(skl_u_ddi_translations_dp
);
394 if (dev_priv
->edp_low_vswing
) {
395 ddi_translations
= skl_ddi_translations_edp
;
396 *n_entries
= ARRAY_SIZE(skl_ddi_translations_edp
);
398 ddi_translations
= skl_ddi_translations_dp
;
399 *n_entries
= ARRAY_SIZE(skl_ddi_translations_dp
);
403 return ddi_translations
;
406 static const struct ddi_buf_trans
*
407 skl_get_buf_trans_hdmi(struct drm_device
*dev
,
410 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
411 const struct ddi_buf_trans
*ddi_translations
;
412 static int is_095v
= -1;
415 u32 spr1
= I915_READ(UAIMI_SPR1
);
417 is_095v
= spr1
& SKL_VCCIO_MASK
;
420 if (IS_SKL_ULX(dev
) && !is_095v
) {
421 ddi_translations
= skl_y_085v_ddi_translations_hdmi
;
422 *n_entries
= ARRAY_SIZE(skl_y_085v_ddi_translations_hdmi
);
424 ddi_translations
= skl_ddi_translations_hdmi
;
425 *n_entries
= ARRAY_SIZE(skl_ddi_translations_hdmi
);
428 return ddi_translations
;
432 * Starting with Haswell, DDI port buffers must be programmed with correct
433 * values in advance. The buffer values are different for FDI and DP modes,
434 * but the HDMI/DVI fields are shared among those. So we program the DDI
435 * in either FDI or DP modes only, as HDMI connections will work with both
438 static void intel_prepare_ddi_buffers(struct drm_device
*dev
, enum port port
,
441 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
443 int i
, n_hdmi_entries
, n_dp_entries
, n_edp_entries
, hdmi_default_entry
,
445 int hdmi_level
= dev_priv
->vbt
.ddi_port_info
[port
].hdmi_level_shift
;
446 const struct ddi_buf_trans
*ddi_translations_fdi
;
447 const struct ddi_buf_trans
*ddi_translations_dp
;
448 const struct ddi_buf_trans
*ddi_translations_edp
;
449 const struct ddi_buf_trans
*ddi_translations_hdmi
;
450 const struct ddi_buf_trans
*ddi_translations
;
452 if (IS_BROXTON(dev
)) {
456 /* Vswing programming for HDMI */
457 bxt_ddi_vswing_sequence(dev
, hdmi_level
, port
,
460 } else if (IS_SKYLAKE(dev
)) {
461 ddi_translations_dp
=
462 skl_get_buf_trans_dp(dev
, &n_dp_entries
);
463 ddi_translations_edp
=
464 skl_get_buf_trans_edp(dev
, &n_edp_entries
);
465 ddi_translations_hdmi
=
466 skl_get_buf_trans_hdmi(dev
, &n_hdmi_entries
);
467 hdmi_default_entry
= 8;
468 } else if (IS_BROADWELL(dev
)) {
469 ddi_translations_fdi
= bdw_ddi_translations_fdi
;
470 ddi_translations_dp
= bdw_ddi_translations_dp
;
471 ddi_translations_edp
= bdw_ddi_translations_edp
;
472 ddi_translations_hdmi
= bdw_ddi_translations_hdmi
;
473 n_edp_entries
= ARRAY_SIZE(bdw_ddi_translations_edp
);
474 n_dp_entries
= ARRAY_SIZE(bdw_ddi_translations_dp
);
475 n_hdmi_entries
= ARRAY_SIZE(bdw_ddi_translations_hdmi
);
476 hdmi_default_entry
= 7;
477 } else if (IS_HASWELL(dev
)) {
478 ddi_translations_fdi
= hsw_ddi_translations_fdi
;
479 ddi_translations_dp
= hsw_ddi_translations_dp
;
480 ddi_translations_edp
= hsw_ddi_translations_dp
;
481 ddi_translations_hdmi
= hsw_ddi_translations_hdmi
;
482 n_dp_entries
= n_edp_entries
= ARRAY_SIZE(hsw_ddi_translations_dp
);
483 n_hdmi_entries
= ARRAY_SIZE(hsw_ddi_translations_hdmi
);
484 hdmi_default_entry
= 6;
486 WARN(1, "ddi translation table missing\n");
487 ddi_translations_edp
= bdw_ddi_translations_dp
;
488 ddi_translations_fdi
= bdw_ddi_translations_fdi
;
489 ddi_translations_dp
= bdw_ddi_translations_dp
;
490 ddi_translations_hdmi
= bdw_ddi_translations_hdmi
;
491 n_edp_entries
= ARRAY_SIZE(bdw_ddi_translations_edp
);
492 n_dp_entries
= ARRAY_SIZE(bdw_ddi_translations_dp
);
493 n_hdmi_entries
= ARRAY_SIZE(bdw_ddi_translations_hdmi
);
494 hdmi_default_entry
= 7;
499 ddi_translations
= ddi_translations_edp
;
500 size
= n_edp_entries
;
504 ddi_translations
= ddi_translations_dp
;
508 if (intel_dp_is_edp(dev
, PORT_D
)) {
509 ddi_translations
= ddi_translations_edp
;
510 size
= n_edp_entries
;
512 ddi_translations
= ddi_translations_dp
;
517 if (ddi_translations_fdi
)
518 ddi_translations
= ddi_translations_fdi
;
520 ddi_translations
= ddi_translations_dp
;
527 for (i
= 0, reg
= DDI_BUF_TRANS(port
); i
< size
; i
++) {
528 I915_WRITE(reg
, ddi_translations
[i
].trans1
);
530 I915_WRITE(reg
, ddi_translations
[i
].trans2
);
537 /* Choose a good default if VBT is badly populated */
538 if (hdmi_level
== HDMI_LEVEL_SHIFT_UNKNOWN
||
539 hdmi_level
>= n_hdmi_entries
)
540 hdmi_level
= hdmi_default_entry
;
542 /* Entry 9 is for HDMI: */
543 I915_WRITE(reg
, ddi_translations_hdmi
[hdmi_level
].trans1
);
545 I915_WRITE(reg
, ddi_translations_hdmi
[hdmi_level
].trans2
);
549 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
550 * mode and port E for FDI.
552 void intel_prepare_ddi(struct drm_device
*dev
)
554 struct intel_encoder
*intel_encoder
;
555 bool visited
[I915_MAX_PORTS
] = { 0, };
560 for_each_intel_encoder(dev
, intel_encoder
) {
561 struct intel_digital_port
*intel_dig_port
;
565 ddi_get_encoder_port(intel_encoder
, &intel_dig_port
, &port
);
570 supports_hdmi
= intel_dig_port
&&
571 intel_dig_port_supports_hdmi(intel_dig_port
);
573 intel_prepare_ddi_buffers(dev
, port
, supports_hdmi
);
574 visited
[port
] = true;
578 static void intel_wait_ddi_buf_idle(struct drm_i915_private
*dev_priv
,
581 uint32_t reg
= DDI_BUF_CTL(port
);
584 for (i
= 0; i
< 16; i
++) {
586 if (I915_READ(reg
) & DDI_BUF_IS_IDLE
)
589 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port
));
592 /* Starting with Haswell, different DDI ports can work in FDI mode for
593 * connection to the PCH-located connectors. For this, it is necessary to train
594 * both the DDI port and PCH receiver for the desired DDI buffer settings.
596 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
597 * please note that when FDI mode is active on DDI E, it shares 2 lines with
598 * DDI A (which is used for eDP)
601 void hsw_fdi_link_train(struct drm_crtc
*crtc
)
603 struct drm_device
*dev
= crtc
->dev
;
604 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
605 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
606 u32 temp
, i
, rx_ctl_val
;
608 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
609 * mode set "sequence for CRT port" document:
610 * - TP1 to TP2 time with the default value
613 * WaFDIAutoLinkSetTimingOverrride:hsw
615 I915_WRITE(_FDI_RXA_MISC
, FDI_RX_PWRDN_LANE1_VAL(2) |
616 FDI_RX_PWRDN_LANE0_VAL(2) |
617 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
619 /* Enable the PCH Receiver FDI PLL */
620 rx_ctl_val
= dev_priv
->fdi_rx_config
| FDI_RX_ENHANCE_FRAME_ENABLE
|
622 FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
623 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
624 POSTING_READ(_FDI_RXA_CTL
);
627 /* Switch from Rawclk to PCDclk */
628 rx_ctl_val
|= FDI_PCDCLK
;
629 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
631 /* Configure Port Clock Select */
632 I915_WRITE(PORT_CLK_SEL(PORT_E
), intel_crtc
->config
->ddi_pll_sel
);
633 WARN_ON(intel_crtc
->config
->ddi_pll_sel
!= PORT_CLK_SEL_SPLL
);
635 /* Start the training iterating through available voltages and emphasis,
636 * testing each value twice. */
637 for (i
= 0; i
< ARRAY_SIZE(hsw_ddi_translations_fdi
) * 2; i
++) {
638 /* Configure DP_TP_CTL with auto-training */
639 I915_WRITE(DP_TP_CTL(PORT_E
),
640 DP_TP_CTL_FDI_AUTOTRAIN
|
641 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
642 DP_TP_CTL_LINK_TRAIN_PAT1
|
645 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
646 * DDI E does not support port reversal, the functionality is
647 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
648 * port reversal bit */
649 I915_WRITE(DDI_BUF_CTL(PORT_E
),
651 ((intel_crtc
->config
->fdi_lanes
- 1) << 1) |
652 DDI_BUF_TRANS_SELECT(i
/ 2));
653 POSTING_READ(DDI_BUF_CTL(PORT_E
));
657 /* Program PCH FDI Receiver TU */
658 I915_WRITE(_FDI_RXA_TUSIZE1
, TU_SIZE(64));
660 /* Enable PCH FDI Receiver with auto-training */
661 rx_ctl_val
|= FDI_RX_ENABLE
| FDI_LINK_TRAIN_AUTO
;
662 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
663 POSTING_READ(_FDI_RXA_CTL
);
665 /* Wait for FDI receiver lane calibration */
668 /* Unset FDI_RX_MISC pwrdn lanes */
669 temp
= I915_READ(_FDI_RXA_MISC
);
670 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
671 I915_WRITE(_FDI_RXA_MISC
, temp
);
672 POSTING_READ(_FDI_RXA_MISC
);
674 /* Wait for FDI auto training time */
677 temp
= I915_READ(DP_TP_STATUS(PORT_E
));
678 if (temp
& DP_TP_STATUS_AUTOTRAIN_DONE
) {
679 DRM_DEBUG_KMS("FDI link training done on step %d\n", i
);
681 /* Enable normal pixel sending for FDI */
682 I915_WRITE(DP_TP_CTL(PORT_E
),
683 DP_TP_CTL_FDI_AUTOTRAIN
|
684 DP_TP_CTL_LINK_TRAIN_NORMAL
|
685 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
691 temp
= I915_READ(DDI_BUF_CTL(PORT_E
));
692 temp
&= ~DDI_BUF_CTL_ENABLE
;
693 I915_WRITE(DDI_BUF_CTL(PORT_E
), temp
);
694 POSTING_READ(DDI_BUF_CTL(PORT_E
));
696 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
697 temp
= I915_READ(DP_TP_CTL(PORT_E
));
698 temp
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
699 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
700 I915_WRITE(DP_TP_CTL(PORT_E
), temp
);
701 POSTING_READ(DP_TP_CTL(PORT_E
));
703 intel_wait_ddi_buf_idle(dev_priv
, PORT_E
);
705 rx_ctl_val
&= ~FDI_RX_ENABLE
;
706 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
707 POSTING_READ(_FDI_RXA_CTL
);
709 /* Reset FDI_RX_MISC pwrdn lanes */
710 temp
= I915_READ(_FDI_RXA_MISC
);
711 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
712 temp
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
713 I915_WRITE(_FDI_RXA_MISC
, temp
);
714 POSTING_READ(_FDI_RXA_MISC
);
717 DRM_ERROR("FDI link training failed!\n");
720 void intel_ddi_init_dp_buf_reg(struct intel_encoder
*encoder
)
722 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
723 struct intel_digital_port
*intel_dig_port
=
724 enc_to_dig_port(&encoder
->base
);
726 intel_dp
->DP
= intel_dig_port
->saved_port_bits
|
727 DDI_BUF_CTL_ENABLE
| DDI_BUF_TRANS_SELECT(0);
728 intel_dp
->DP
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
732 static struct intel_encoder
*
733 intel_ddi_get_crtc_encoder(struct drm_crtc
*crtc
)
735 struct drm_device
*dev
= crtc
->dev
;
736 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
737 struct intel_encoder
*intel_encoder
, *ret
= NULL
;
738 int num_encoders
= 0;
740 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
745 if (num_encoders
!= 1)
746 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders
,
747 pipe_name(intel_crtc
->pipe
));
753 struct intel_encoder
*
754 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state
*crtc_state
)
756 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
757 struct intel_encoder
*ret
= NULL
;
758 struct drm_atomic_state
*state
;
759 struct drm_connector
*connector
;
760 struct drm_connector_state
*connector_state
;
761 int num_encoders
= 0;
764 state
= crtc_state
->base
.state
;
766 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
767 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
770 ret
= to_intel_encoder(connector_state
->best_encoder
);
774 WARN(num_encoders
!= 1, "%d encoders on crtc for pipe %c\n", num_encoders
,
775 pipe_name(crtc
->pipe
));
782 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
788 /* Constraints for PLL good behavior */
794 #define abs_diff(a, b) ({ \
795 typeof(a) __a = (a); \
796 typeof(b) __b = (b); \
797 (void) (&__a == &__b); \
798 __a > __b ? (__a - __b) : (__b - __a); })
800 struct hsw_wrpll_rnp
{
804 static unsigned hsw_wrpll_get_budget_for_freq(int clock
)
878 static void hsw_wrpll_update_rnp(uint64_t freq2k
, unsigned budget
,
879 unsigned r2
, unsigned n2
, unsigned p
,
880 struct hsw_wrpll_rnp
*best
)
882 uint64_t a
, b
, c
, d
, diff
, diff_best
;
884 /* No best (r,n,p) yet */
893 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
897 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
900 * and we would like delta <= budget.
902 * If the discrepancy is above the PPM-based budget, always prefer to
903 * improve upon the previous solution. However, if you're within the
904 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
906 a
= freq2k
* budget
* p
* r2
;
907 b
= freq2k
* budget
* best
->p
* best
->r2
;
908 diff
= abs_diff(freq2k
* p
* r2
, LC_FREQ_2K
* n2
);
909 diff_best
= abs_diff(freq2k
* best
->p
* best
->r2
,
910 LC_FREQ_2K
* best
->n2
);
912 d
= 1000000 * diff_best
;
914 if (a
< c
&& b
< d
) {
915 /* If both are above the budget, pick the closer */
916 if (best
->p
* best
->r2
* diff
< p
* r2
* diff_best
) {
921 } else if (a
>= c
&& b
< d
) {
922 /* If A is below the threshold but B is above it? Update. */
926 } else if (a
>= c
&& b
>= d
) {
927 /* Both are below the limit, so pick the higher n2/(r2*r2) */
928 if (n2
* best
->r2
* best
->r2
> best
->n2
* r2
* r2
) {
934 /* Otherwise a < c && b >= d, do nothing */
937 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private
*dev_priv
, int reg
)
939 int refclk
= LC_FREQ
;
943 wrpll
= I915_READ(reg
);
944 switch (wrpll
& WRPLL_PLL_REF_MASK
) {
946 case WRPLL_PLL_NON_SSC
:
948 * We could calculate spread here, but our checking
949 * code only cares about 5% accuracy, and spread is a max of
954 case WRPLL_PLL_LCPLL
:
958 WARN(1, "bad wrpll refclk\n");
962 r
= wrpll
& WRPLL_DIVIDER_REF_MASK
;
963 p
= (wrpll
& WRPLL_DIVIDER_POST_MASK
) >> WRPLL_DIVIDER_POST_SHIFT
;
964 n
= (wrpll
& WRPLL_DIVIDER_FB_MASK
) >> WRPLL_DIVIDER_FB_SHIFT
;
966 /* Convert to KHz, p & r have a fixed point portion */
967 return (refclk
* n
* 100) / (p
* r
);
970 static int skl_calc_wrpll_link(struct drm_i915_private
*dev_priv
,
973 uint32_t cfgcr1_reg
, cfgcr2_reg
;
974 uint32_t cfgcr1_val
, cfgcr2_val
;
975 uint32_t p0
, p1
, p2
, dco_freq
;
977 cfgcr1_reg
= GET_CFG_CR1_REG(dpll
);
978 cfgcr2_reg
= GET_CFG_CR2_REG(dpll
);
980 cfgcr1_val
= I915_READ(cfgcr1_reg
);
981 cfgcr2_val
= I915_READ(cfgcr2_reg
);
983 p0
= cfgcr2_val
& DPLL_CFGCR2_PDIV_MASK
;
984 p2
= cfgcr2_val
& DPLL_CFGCR2_KDIV_MASK
;
986 if (cfgcr2_val
& DPLL_CFGCR2_QDIV_MODE(1))
987 p1
= (cfgcr2_val
& DPLL_CFGCR2_QDIV_RATIO_MASK
) >> 8;
993 case DPLL_CFGCR2_PDIV_1
:
996 case DPLL_CFGCR2_PDIV_2
:
999 case DPLL_CFGCR2_PDIV_3
:
1002 case DPLL_CFGCR2_PDIV_7
:
1008 case DPLL_CFGCR2_KDIV_5
:
1011 case DPLL_CFGCR2_KDIV_2
:
1014 case DPLL_CFGCR2_KDIV_3
:
1017 case DPLL_CFGCR2_KDIV_1
:
1022 dco_freq
= (cfgcr1_val
& DPLL_CFGCR1_DCO_INTEGER_MASK
) * 24 * 1000;
1024 dco_freq
+= (((cfgcr1_val
& DPLL_CFGCR1_DCO_FRACTION_MASK
) >> 9) * 24 *
1027 return dco_freq
/ (p0
* p1
* p2
* 5);
1031 static void skl_ddi_clock_get(struct intel_encoder
*encoder
,
1032 struct intel_crtc_state
*pipe_config
)
1034 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
1036 uint32_t dpll_ctl1
, dpll
;
1038 dpll
= pipe_config
->ddi_pll_sel
;
1040 dpll_ctl1
= I915_READ(DPLL_CTRL1
);
1042 if (dpll_ctl1
& DPLL_CTRL1_HDMI_MODE(dpll
)) {
1043 link_clock
= skl_calc_wrpll_link(dev_priv
, dpll
);
1045 link_clock
= dpll_ctl1
& DPLL_CTRL1_LINK_RATE_MASK(dpll
);
1046 link_clock
>>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll
);
1048 switch (link_clock
) {
1049 case DPLL_CTRL1_LINK_RATE_810
:
1052 case DPLL_CTRL1_LINK_RATE_1080
:
1053 link_clock
= 108000;
1055 case DPLL_CTRL1_LINK_RATE_1350
:
1056 link_clock
= 135000;
1058 case DPLL_CTRL1_LINK_RATE_1620
:
1059 link_clock
= 162000;
1061 case DPLL_CTRL1_LINK_RATE_2160
:
1062 link_clock
= 216000;
1064 case DPLL_CTRL1_LINK_RATE_2700
:
1065 link_clock
= 270000;
1068 WARN(1, "Unsupported link rate\n");
1074 pipe_config
->port_clock
= link_clock
;
1076 if (pipe_config
->has_dp_encoder
)
1077 pipe_config
->base
.adjusted_mode
.crtc_clock
=
1078 intel_dotclock_calculate(pipe_config
->port_clock
,
1079 &pipe_config
->dp_m_n
);
1081 pipe_config
->base
.adjusted_mode
.crtc_clock
= pipe_config
->port_clock
;
1084 static void hsw_ddi_clock_get(struct intel_encoder
*encoder
,
1085 struct intel_crtc_state
*pipe_config
)
1087 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
1091 val
= pipe_config
->ddi_pll_sel
;
1092 switch (val
& PORT_CLK_SEL_MASK
) {
1093 case PORT_CLK_SEL_LCPLL_810
:
1096 case PORT_CLK_SEL_LCPLL_1350
:
1097 link_clock
= 135000;
1099 case PORT_CLK_SEL_LCPLL_2700
:
1100 link_clock
= 270000;
1102 case PORT_CLK_SEL_WRPLL1
:
1103 link_clock
= hsw_ddi_calc_wrpll_link(dev_priv
, WRPLL_CTL1
);
1105 case PORT_CLK_SEL_WRPLL2
:
1106 link_clock
= hsw_ddi_calc_wrpll_link(dev_priv
, WRPLL_CTL2
);
1108 case PORT_CLK_SEL_SPLL
:
1109 pll
= I915_READ(SPLL_CTL
) & SPLL_PLL_FREQ_MASK
;
1110 if (pll
== SPLL_PLL_FREQ_810MHz
)
1112 else if (pll
== SPLL_PLL_FREQ_1350MHz
)
1113 link_clock
= 135000;
1114 else if (pll
== SPLL_PLL_FREQ_2700MHz
)
1115 link_clock
= 270000;
1117 WARN(1, "bad spll freq\n");
1122 WARN(1, "bad port clock sel\n");
1126 pipe_config
->port_clock
= link_clock
* 2;
1128 if (pipe_config
->has_pch_encoder
)
1129 pipe_config
->base
.adjusted_mode
.crtc_clock
=
1130 intel_dotclock_calculate(pipe_config
->port_clock
,
1131 &pipe_config
->fdi_m_n
);
1132 else if (pipe_config
->has_dp_encoder
)
1133 pipe_config
->base
.adjusted_mode
.crtc_clock
=
1134 intel_dotclock_calculate(pipe_config
->port_clock
,
1135 &pipe_config
->dp_m_n
);
1137 pipe_config
->base
.adjusted_mode
.crtc_clock
= pipe_config
->port_clock
;
1140 static int bxt_calc_pll_link(struct drm_i915_private
*dev_priv
,
1141 enum intel_dpll_id dpll
)
1143 struct intel_shared_dpll
*pll
;
1144 struct intel_dpll_hw_state
*state
;
1145 intel_clock_t clock
;
1147 /* For DDI ports we always use a shared PLL. */
1148 if (WARN_ON(dpll
== DPLL_ID_PRIVATE
))
1151 pll
= &dev_priv
->shared_dplls
[dpll
];
1152 state
= &pll
->config
.hw_state
;
1155 clock
.m2
= (state
->pll0
& PORT_PLL_M2_MASK
) << 22;
1156 if (state
->pll3
& PORT_PLL_M2_FRAC_ENABLE
)
1157 clock
.m2
|= state
->pll2
& PORT_PLL_M2_FRAC_MASK
;
1158 clock
.n
= (state
->pll1
& PORT_PLL_N_MASK
) >> PORT_PLL_N_SHIFT
;
1159 clock
.p1
= (state
->ebb0
& PORT_PLL_P1_MASK
) >> PORT_PLL_P1_SHIFT
;
1160 clock
.p2
= (state
->ebb0
& PORT_PLL_P2_MASK
) >> PORT_PLL_P2_SHIFT
;
1162 return chv_calc_dpll_params(100000, &clock
);
1165 static void bxt_ddi_clock_get(struct intel_encoder
*encoder
,
1166 struct intel_crtc_state
*pipe_config
)
1168 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
1169 enum port port
= intel_ddi_get_encoder_port(encoder
);
1170 uint32_t dpll
= port
;
1172 pipe_config
->port_clock
=
1173 bxt_calc_pll_link(dev_priv
, dpll
);
1175 if (pipe_config
->has_dp_encoder
)
1176 pipe_config
->base
.adjusted_mode
.crtc_clock
=
1177 intel_dotclock_calculate(pipe_config
->port_clock
,
1178 &pipe_config
->dp_m_n
);
1180 pipe_config
->base
.adjusted_mode
.crtc_clock
=
1181 pipe_config
->port_clock
;
1184 void intel_ddi_clock_get(struct intel_encoder
*encoder
,
1185 struct intel_crtc_state
*pipe_config
)
1187 struct drm_device
*dev
= encoder
->base
.dev
;
1189 if (INTEL_INFO(dev
)->gen
<= 8)
1190 hsw_ddi_clock_get(encoder
, pipe_config
);
1191 else if (IS_SKYLAKE(dev
))
1192 skl_ddi_clock_get(encoder
, pipe_config
);
1193 else if (IS_BROXTON(dev
))
1194 bxt_ddi_clock_get(encoder
, pipe_config
);
1198 hsw_ddi_calculate_wrpll(int clock
/* in Hz */,
1199 unsigned *r2_out
, unsigned *n2_out
, unsigned *p_out
)
1203 struct hsw_wrpll_rnp best
= { 0, 0, 0 };
1206 freq2k
= clock
/ 100;
1208 budget
= hsw_wrpll_get_budget_for_freq(clock
);
1210 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1211 * and directly pass the LC PLL to it. */
1212 if (freq2k
== 5400000) {
1220 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1223 * We want R so that REF_MIN <= Ref <= REF_MAX.
1224 * Injecting R2 = 2 * R gives:
1225 * REF_MAX * r2 > LC_FREQ * 2 and
1226 * REF_MIN * r2 < LC_FREQ * 2
1228 * Which means the desired boundaries for r2 are:
1229 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1232 for (r2
= LC_FREQ
* 2 / REF_MAX
+ 1;
1233 r2
<= LC_FREQ
* 2 / REF_MIN
;
1237 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1239 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1240 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1241 * VCO_MAX * r2 > n2 * LC_FREQ and
1242 * VCO_MIN * r2 < n2 * LC_FREQ)
1244 * Which means the desired boundaries for n2 are:
1245 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1247 for (n2
= VCO_MIN
* r2
/ LC_FREQ
+ 1;
1248 n2
<= VCO_MAX
* r2
/ LC_FREQ
;
1251 for (p
= P_MIN
; p
<= P_MAX
; p
+= P_INC
)
1252 hsw_wrpll_update_rnp(freq2k
, budget
,
1263 hsw_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1264 struct intel_crtc_state
*crtc_state
,
1265 struct intel_encoder
*intel_encoder
,
1268 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
1269 struct intel_shared_dpll
*pll
;
1273 hsw_ddi_calculate_wrpll(clock
* 1000, &r2
, &n2
, &p
);
1275 val
= WRPLL_PLL_ENABLE
| WRPLL_PLL_LCPLL
|
1276 WRPLL_DIVIDER_REFERENCE(r2
) | WRPLL_DIVIDER_FEEDBACK(n2
) |
1277 WRPLL_DIVIDER_POST(p
);
1279 memset(&crtc_state
->dpll_hw_state
, 0,
1280 sizeof(crtc_state
->dpll_hw_state
));
1282 crtc_state
->dpll_hw_state
.wrpll
= val
;
1284 pll
= intel_get_shared_dpll(intel_crtc
, crtc_state
);
1286 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1287 pipe_name(intel_crtc
->pipe
));
1291 crtc_state
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL(pll
->id
);
1297 struct skl_wrpll_context
{
1298 uint64_t min_deviation
; /* current minimal deviation */
1299 uint64_t central_freq
; /* chosen central freq */
1300 uint64_t dco_freq
; /* chosen dco freq */
1301 unsigned int p
; /* chosen divider */
1304 static void skl_wrpll_context_init(struct skl_wrpll_context
*ctx
)
1306 memset(ctx
, 0, sizeof(*ctx
));
1308 ctx
->min_deviation
= U64_MAX
;
1311 /* DCO freq must be within +1%/-6% of the DCO central freq */
1312 #define SKL_DCO_MAX_PDEVIATION 100
1313 #define SKL_DCO_MAX_NDEVIATION 600
1315 static void skl_wrpll_try_divider(struct skl_wrpll_context
*ctx
,
1316 uint64_t central_freq
,
1318 unsigned int divider
)
1322 deviation
= div64_u64(10000 * abs_diff(dco_freq
, central_freq
),
1325 /* positive deviation */
1326 if (dco_freq
>= central_freq
) {
1327 if (deviation
< SKL_DCO_MAX_PDEVIATION
&&
1328 deviation
< ctx
->min_deviation
) {
1329 ctx
->min_deviation
= deviation
;
1330 ctx
->central_freq
= central_freq
;
1331 ctx
->dco_freq
= dco_freq
;
1334 /* negative deviation */
1335 } else if (deviation
< SKL_DCO_MAX_NDEVIATION
&&
1336 deviation
< ctx
->min_deviation
) {
1337 ctx
->min_deviation
= deviation
;
1338 ctx
->central_freq
= central_freq
;
1339 ctx
->dco_freq
= dco_freq
;
1344 static void skl_wrpll_get_multipliers(unsigned int p
,
1345 unsigned int *p0
/* out */,
1346 unsigned int *p1
/* out */,
1347 unsigned int *p2
/* out */)
1351 unsigned int half
= p
/ 2;
1353 if (half
== 1 || half
== 2 || half
== 3 || half
== 5) {
1357 } else if (half
% 2 == 0) {
1361 } else if (half
% 3 == 0) {
1365 } else if (half
% 7 == 0) {
1370 } else if (p
== 3 || p
== 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1374 } else if (p
== 5 || p
== 7) {
1378 } else if (p
== 15) {
1382 } else if (p
== 21) {
1386 } else if (p
== 35) {
1393 struct skl_wrpll_params
{
1394 uint32_t dco_fraction
;
1395 uint32_t dco_integer
;
1396 uint32_t qdiv_ratio
;
1400 uint32_t central_freq
;
1403 static void skl_wrpll_params_populate(struct skl_wrpll_params
*params
,
1405 uint64_t central_freq
,
1406 uint32_t p0
, uint32_t p1
, uint32_t p2
)
1410 switch (central_freq
) {
1412 params
->central_freq
= 0;
1415 params
->central_freq
= 1;
1418 params
->central_freq
= 3;
1435 WARN(1, "Incorrect PDiv\n");
1452 WARN(1, "Incorrect KDiv\n");
1455 params
->qdiv_ratio
= p1
;
1456 params
->qdiv_mode
= (params
->qdiv_ratio
== 1) ? 0 : 1;
1458 dco_freq
= p0
* p1
* p2
* afe_clock
;
1461 * Intermediate values are in Hz.
1462 * Divide by MHz to match bsepc
1464 params
->dco_integer
= div_u64(dco_freq
, 24 * MHz(1));
1465 params
->dco_fraction
=
1466 div_u64((div_u64(dco_freq
, 24) -
1467 params
->dco_integer
* MHz(1)) * 0x8000, MHz(1));
1471 skl_ddi_calculate_wrpll(int clock
/* in Hz */,
1472 struct skl_wrpll_params
*wrpll_params
)
1474 uint64_t afe_clock
= clock
* 5; /* AFE Clock is 5x Pixel clock */
1475 uint64_t dco_central_freq
[3] = {8400000000ULL,
1478 static const int even_dividers
[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1479 24, 28, 30, 32, 36, 40, 42, 44,
1480 48, 52, 54, 56, 60, 64, 66, 68,
1481 70, 72, 76, 78, 80, 84, 88, 90,
1483 static const int odd_dividers
[] = { 3, 5, 7, 9, 15, 21, 35 };
1484 static const struct {
1488 { even_dividers
, ARRAY_SIZE(even_dividers
) },
1489 { odd_dividers
, ARRAY_SIZE(odd_dividers
) },
1491 struct skl_wrpll_context ctx
;
1492 unsigned int dco
, d
, i
;
1493 unsigned int p0
, p1
, p2
;
1495 skl_wrpll_context_init(&ctx
);
1497 for (d
= 0; d
< ARRAY_SIZE(dividers
); d
++) {
1498 for (dco
= 0; dco
< ARRAY_SIZE(dco_central_freq
); dco
++) {
1499 for (i
= 0; i
< dividers
[d
].n_dividers
; i
++) {
1500 unsigned int p
= dividers
[d
].list
[i
];
1501 uint64_t dco_freq
= p
* afe_clock
;
1503 skl_wrpll_try_divider(&ctx
,
1504 dco_central_freq
[dco
],
1508 * Skip the remaining dividers if we're sure to
1509 * have found the definitive divider, we can't
1510 * improve a 0 deviation.
1512 if (ctx
.min_deviation
== 0)
1513 goto skip_remaining_dividers
;
1517 skip_remaining_dividers
:
1519 * If a solution is found with an even divider, prefer
1522 if (d
== 0 && ctx
.p
)
1527 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock
);
1532 * gcc incorrectly analyses that these can be used without being
1533 * initialized. To be fair, it's hard to guess.
1536 skl_wrpll_get_multipliers(ctx
.p
, &p0
, &p1
, &p2
);
1537 skl_wrpll_params_populate(wrpll_params
, afe_clock
, ctx
.central_freq
,
1544 skl_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1545 struct intel_crtc_state
*crtc_state
,
1546 struct intel_encoder
*intel_encoder
,
1549 struct intel_shared_dpll
*pll
;
1550 uint32_t ctrl1
, cfgcr1
, cfgcr2
;
1553 * See comment in intel_dpll_hw_state to understand why we always use 0
1554 * as the DPLL id in this function.
1557 ctrl1
= DPLL_CTRL1_OVERRIDE(0);
1559 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
1560 struct skl_wrpll_params wrpll_params
= { 0, };
1562 ctrl1
|= DPLL_CTRL1_HDMI_MODE(0);
1564 if (!skl_ddi_calculate_wrpll(clock
* 1000, &wrpll_params
))
1567 cfgcr1
= DPLL_CFGCR1_FREQ_ENABLE
|
1568 DPLL_CFGCR1_DCO_FRACTION(wrpll_params
.dco_fraction
) |
1569 wrpll_params
.dco_integer
;
1571 cfgcr2
= DPLL_CFGCR2_QDIV_RATIO(wrpll_params
.qdiv_ratio
) |
1572 DPLL_CFGCR2_QDIV_MODE(wrpll_params
.qdiv_mode
) |
1573 DPLL_CFGCR2_KDIV(wrpll_params
.kdiv
) |
1574 DPLL_CFGCR2_PDIV(wrpll_params
.pdiv
) |
1575 wrpll_params
.central_freq
;
1576 } else if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
) {
1577 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1578 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1580 switch (intel_dp
->link_bw
) {
1581 case DP_LINK_BW_1_62
:
1582 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
, 0);
1584 case DP_LINK_BW_2_7
:
1585 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350
, 0);
1587 case DP_LINK_BW_5_4
:
1588 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700
, 0);
1592 cfgcr1
= cfgcr2
= 0;
1596 memset(&crtc_state
->dpll_hw_state
, 0,
1597 sizeof(crtc_state
->dpll_hw_state
));
1599 crtc_state
->dpll_hw_state
.ctrl1
= ctrl1
;
1600 crtc_state
->dpll_hw_state
.cfgcr1
= cfgcr1
;
1601 crtc_state
->dpll_hw_state
.cfgcr2
= cfgcr2
;
1603 pll
= intel_get_shared_dpll(intel_crtc
, crtc_state
);
1605 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1606 pipe_name(intel_crtc
->pipe
));
1610 /* shared DPLL id 0 is DPLL 1 */
1611 crtc_state
->ddi_pll_sel
= pll
->id
+ 1;
1616 /* bxt clock parameters */
1617 struct bxt_clk_div
{
1627 /* pre-calculated values for DP linkrates */
1628 static const struct bxt_clk_div bxt_dp_clk_val
[] = {
1629 {162000, 4, 2, 32, 1677722, 1, 1},
1630 {270000, 4, 1, 27, 0, 0, 1},
1631 {540000, 2, 1, 27, 0, 0, 1},
1632 {216000, 3, 2, 32, 1677722, 1, 1},
1633 {243000, 4, 1, 24, 1258291, 1, 1},
1634 {324000, 4, 1, 32, 1677722, 1, 1},
1635 {432000, 3, 1, 32, 1677722, 1, 1}
1639 bxt_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1640 struct intel_crtc_state
*crtc_state
,
1641 struct intel_encoder
*intel_encoder
,
1644 struct intel_shared_dpll
*pll
;
1645 struct bxt_clk_div clk_div
= {0};
1647 uint32_t prop_coef
, int_coef
, gain_ctl
, targ_cnt
;
1648 uint32_t dcoampovr_en_h
, dco_amp
, lanestagger
;
1650 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
1651 intel_clock_t best_clock
;
1653 /* Calculate HDMI div */
1655 * FIXME: tie the following calculation into
1656 * i9xx_crtc_compute_clock
1658 if (!bxt_find_best_dpll(crtc_state
, clock
, &best_clock
)) {
1659 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1660 clock
, pipe_name(intel_crtc
->pipe
));
1664 clk_div
.p1
= best_clock
.p1
;
1665 clk_div
.p2
= best_clock
.p2
;
1666 WARN_ON(best_clock
.m1
!= 2);
1667 clk_div
.n
= best_clock
.n
;
1668 clk_div
.m2_int
= best_clock
.m2
>> 22;
1669 clk_div
.m2_frac
= best_clock
.m2
& ((1 << 22) - 1);
1670 clk_div
.m2_frac_en
= clk_div
.m2_frac
!= 0;
1672 vco
= best_clock
.vco
;
1673 } else if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
1674 intel_encoder
->type
== INTEL_OUTPUT_EDP
) {
1677 clk_div
= bxt_dp_clk_val
[0];
1678 for (i
= 0; i
< ARRAY_SIZE(bxt_dp_clk_val
); ++i
) {
1679 if (bxt_dp_clk_val
[i
].clock
== clock
) {
1680 clk_div
= bxt_dp_clk_val
[i
];
1684 vco
= clock
* 10 / 2 * clk_div
.p1
* clk_div
.p2
;
1689 if (vco
>= 6200000 && vco
<= 6480000) {
1694 } else if ((vco
> 5400000 && vco
< 6200000) ||
1695 (vco
>= 4800000 && vco
< 5400000)) {
1700 if (vco
>= 4800000 && vco
< 5400000)
1702 } else if (vco
== 5400000) {
1708 DRM_ERROR("Invalid VCO\n");
1712 memset(&crtc_state
->dpll_hw_state
, 0,
1713 sizeof(crtc_state
->dpll_hw_state
));
1717 else if (clock
> 135000)
1719 else if (clock
> 67000)
1721 else if (clock
> 33000)
1726 crtc_state
->dpll_hw_state
.ebb0
=
1727 PORT_PLL_P1(clk_div
.p1
) | PORT_PLL_P2(clk_div
.p2
);
1728 crtc_state
->dpll_hw_state
.pll0
= clk_div
.m2_int
;
1729 crtc_state
->dpll_hw_state
.pll1
= PORT_PLL_N(clk_div
.n
);
1730 crtc_state
->dpll_hw_state
.pll2
= clk_div
.m2_frac
;
1732 if (clk_div
.m2_frac_en
)
1733 crtc_state
->dpll_hw_state
.pll3
=
1734 PORT_PLL_M2_FRAC_ENABLE
;
1736 crtc_state
->dpll_hw_state
.pll6
=
1737 prop_coef
| PORT_PLL_INT_COEFF(int_coef
);
1738 crtc_state
->dpll_hw_state
.pll6
|=
1739 PORT_PLL_GAIN_CTL(gain_ctl
);
1741 crtc_state
->dpll_hw_state
.pll8
= targ_cnt
;
1743 crtc_state
->dpll_hw_state
.pll9
= 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT
;
1746 crtc_state
->dpll_hw_state
.pll10
= PORT_PLL_DCO_AMP_OVR_EN_H
;
1748 crtc_state
->dpll_hw_state
.pll10
|= PORT_PLL_DCO_AMP(dco_amp
);
1750 crtc_state
->dpll_hw_state
.ebb4
= PORT_PLL_10BIT_CLK_ENABLE
;
1752 crtc_state
->dpll_hw_state
.pcsdw12
=
1753 LANESTAGGER_STRAP_OVRD
| lanestagger
;
1755 pll
= intel_get_shared_dpll(intel_crtc
, crtc_state
);
1757 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1758 pipe_name(intel_crtc
->pipe
));
1762 /* shared DPLL id 0 is DPLL A */
1763 crtc_state
->ddi_pll_sel
= pll
->id
;
1769 * Tries to find a *shared* PLL for the CRTC and store it in
1770 * intel_crtc->ddi_pll_sel.
1772 * For private DPLLs, compute_config() should do the selection for us. This
1773 * function should be folded into compute_config() eventually.
1775 bool intel_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1776 struct intel_crtc_state
*crtc_state
)
1778 struct drm_device
*dev
= intel_crtc
->base
.dev
;
1779 struct intel_encoder
*intel_encoder
=
1780 intel_ddi_get_crtc_new_encoder(crtc_state
);
1781 int clock
= crtc_state
->port_clock
;
1783 if (IS_SKYLAKE(dev
))
1784 return skl_ddi_pll_select(intel_crtc
, crtc_state
,
1785 intel_encoder
, clock
);
1786 else if (IS_BROXTON(dev
))
1787 return bxt_ddi_pll_select(intel_crtc
, crtc_state
,
1788 intel_encoder
, clock
);
1790 return hsw_ddi_pll_select(intel_crtc
, crtc_state
,
1791 intel_encoder
, clock
);
1794 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
)
1796 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1797 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1798 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1799 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1800 int type
= intel_encoder
->type
;
1803 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
|| type
== INTEL_OUTPUT_DP_MST
) {
1804 temp
= TRANS_MSA_SYNC_CLK
;
1805 switch (intel_crtc
->config
->pipe_bpp
) {
1807 temp
|= TRANS_MSA_6_BPC
;
1810 temp
|= TRANS_MSA_8_BPC
;
1813 temp
|= TRANS_MSA_10_BPC
;
1816 temp
|= TRANS_MSA_12_BPC
;
1821 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder
), temp
);
1825 void intel_ddi_set_vc_payload_alloc(struct drm_crtc
*crtc
, bool state
)
1827 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1828 struct drm_device
*dev
= crtc
->dev
;
1829 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1830 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1832 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1834 temp
|= TRANS_DDI_DP_VC_PAYLOAD_ALLOC
;
1836 temp
&= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC
;
1837 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1840 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
)
1842 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1843 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1844 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1845 struct drm_device
*dev
= crtc
->dev
;
1846 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1847 enum pipe pipe
= intel_crtc
->pipe
;
1848 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1849 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1850 int type
= intel_encoder
->type
;
1853 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1854 temp
= TRANS_DDI_FUNC_ENABLE
;
1855 temp
|= TRANS_DDI_SELECT_PORT(port
);
1857 switch (intel_crtc
->config
->pipe_bpp
) {
1859 temp
|= TRANS_DDI_BPC_6
;
1862 temp
|= TRANS_DDI_BPC_8
;
1865 temp
|= TRANS_DDI_BPC_10
;
1868 temp
|= TRANS_DDI_BPC_12
;
1874 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
1875 temp
|= TRANS_DDI_PVSYNC
;
1876 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
1877 temp
|= TRANS_DDI_PHSYNC
;
1879 if (cpu_transcoder
== TRANSCODER_EDP
) {
1882 /* On Haswell, can only use the always-on power well for
1883 * eDP when not using the panel fitter, and when not
1884 * using motion blur mitigation (which we don't
1886 if (IS_HASWELL(dev
) &&
1887 (intel_crtc
->config
->pch_pfit
.enabled
||
1888 intel_crtc
->config
->pch_pfit
.force_thru
))
1889 temp
|= TRANS_DDI_EDP_INPUT_A_ONOFF
;
1891 temp
|= TRANS_DDI_EDP_INPUT_A_ON
;
1894 temp
|= TRANS_DDI_EDP_INPUT_B_ONOFF
;
1897 temp
|= TRANS_DDI_EDP_INPUT_C_ONOFF
;
1905 if (type
== INTEL_OUTPUT_HDMI
) {
1906 if (intel_crtc
->config
->has_hdmi_sink
)
1907 temp
|= TRANS_DDI_MODE_SELECT_HDMI
;
1909 temp
|= TRANS_DDI_MODE_SELECT_DVI
;
1911 } else if (type
== INTEL_OUTPUT_ANALOG
) {
1912 temp
|= TRANS_DDI_MODE_SELECT_FDI
;
1913 temp
|= (intel_crtc
->config
->fdi_lanes
- 1) << 1;
1915 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
||
1916 type
== INTEL_OUTPUT_EDP
) {
1917 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1919 if (intel_dp
->is_mst
) {
1920 temp
|= TRANS_DDI_MODE_SELECT_DP_MST
;
1922 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
1924 temp
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
1925 } else if (type
== INTEL_OUTPUT_DP_MST
) {
1926 struct intel_dp
*intel_dp
= &enc_to_mst(encoder
)->primary
->dp
;
1928 if (intel_dp
->is_mst
) {
1929 temp
|= TRANS_DDI_MODE_SELECT_DP_MST
;
1931 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
1933 temp
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
1935 WARN(1, "Invalid encoder type %d for pipe %c\n",
1936 intel_encoder
->type
, pipe_name(pipe
));
1939 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1942 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1943 enum transcoder cpu_transcoder
)
1945 uint32_t reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1946 uint32_t val
= I915_READ(reg
);
1948 val
&= ~(TRANS_DDI_FUNC_ENABLE
| TRANS_DDI_PORT_MASK
| TRANS_DDI_DP_VC_PAYLOAD_ALLOC
);
1949 val
|= TRANS_DDI_PORT_NONE
;
1950 I915_WRITE(reg
, val
);
1953 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
)
1955 struct drm_device
*dev
= intel_connector
->base
.dev
;
1956 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1957 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
1958 int type
= intel_connector
->base
.connector_type
;
1959 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1961 enum transcoder cpu_transcoder
;
1962 enum intel_display_power_domain power_domain
;
1965 power_domain
= intel_display_port_power_domain(intel_encoder
);
1966 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
1969 if (!intel_encoder
->get_hw_state(intel_encoder
, &pipe
))
1973 cpu_transcoder
= TRANSCODER_EDP
;
1975 cpu_transcoder
= (enum transcoder
) pipe
;
1977 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1979 switch (tmp
& TRANS_DDI_MODE_SELECT_MASK
) {
1980 case TRANS_DDI_MODE_SELECT_HDMI
:
1981 case TRANS_DDI_MODE_SELECT_DVI
:
1982 return (type
== DRM_MODE_CONNECTOR_HDMIA
);
1984 case TRANS_DDI_MODE_SELECT_DP_SST
:
1985 if (type
== DRM_MODE_CONNECTOR_eDP
)
1987 return (type
== DRM_MODE_CONNECTOR_DisplayPort
);
1988 case TRANS_DDI_MODE_SELECT_DP_MST
:
1989 /* if the transcoder is in MST state then
1990 * connector isn't connected */
1993 case TRANS_DDI_MODE_SELECT_FDI
:
1994 return (type
== DRM_MODE_CONNECTOR_VGA
);
2001 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
,
2004 struct drm_device
*dev
= encoder
->base
.dev
;
2005 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2006 enum port port
= intel_ddi_get_encoder_port(encoder
);
2007 enum intel_display_power_domain power_domain
;
2011 power_domain
= intel_display_port_power_domain(encoder
);
2012 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
2015 tmp
= I915_READ(DDI_BUF_CTL(port
));
2017 if (!(tmp
& DDI_BUF_CTL_ENABLE
))
2020 if (port
== PORT_A
) {
2021 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
2023 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
2024 case TRANS_DDI_EDP_INPUT_A_ON
:
2025 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
2028 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
2031 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
2038 for (i
= TRANSCODER_A
; i
<= TRANSCODER_C
; i
++) {
2039 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(i
));
2041 if ((tmp
& TRANS_DDI_PORT_MASK
)
2042 == TRANS_DDI_SELECT_PORT(port
)) {
2043 if ((tmp
& TRANS_DDI_MODE_SELECT_MASK
) == TRANS_DDI_MODE_SELECT_DP_MST
)
2052 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port
));
2057 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
)
2059 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2060 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
2061 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
2062 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
2063 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
2065 if (cpu_transcoder
!= TRANSCODER_EDP
)
2066 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
2067 TRANS_CLK_SEL_PORT(port
));
2070 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
)
2072 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
2073 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
2075 if (cpu_transcoder
!= TRANSCODER_EDP
)
2076 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
2077 TRANS_CLK_SEL_DISABLED
);
2080 static void skl_ddi_set_iboost(struct drm_device
*dev
, u32 level
,
2081 enum port port
, int type
)
2083 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2084 const struct ddi_buf_trans
*ddi_translations
;
2089 if (type
== INTEL_OUTPUT_DISPLAYPORT
) {
2090 ddi_translations
= skl_get_buf_trans_dp(dev
, &n_entries
);
2091 iboost
= ddi_translations
[port
].i_boost
;
2092 } else if (type
== INTEL_OUTPUT_EDP
) {
2093 ddi_translations
= skl_get_buf_trans_edp(dev
, &n_entries
);
2094 iboost
= ddi_translations
[port
].i_boost
;
2095 } else if (type
== INTEL_OUTPUT_HDMI
) {
2096 ddi_translations
= skl_get_buf_trans_hdmi(dev
, &n_entries
);
2097 iboost
= ddi_translations
[port
].i_boost
;
2102 /* Make sure that the requested I_boost is valid */
2103 if (iboost
&& iboost
!= 0x1 && iboost
!= 0x3 && iboost
!= 0x7) {
2104 DRM_ERROR("Invalid I_boost value %u\n", iboost
);
2108 reg
= I915_READ(DISPIO_CR_TX_BMU_CR0
);
2109 reg
&= ~BALANCE_LEG_MASK(port
);
2110 reg
&= ~(1 << (BALANCE_LEG_DISABLE_SHIFT
+ port
));
2113 reg
|= iboost
<< BALANCE_LEG_SHIFT(port
);
2115 reg
|= 1 << (BALANCE_LEG_DISABLE_SHIFT
+ port
);
2117 I915_WRITE(DISPIO_CR_TX_BMU_CR0
, reg
);
2120 static void bxt_ddi_vswing_sequence(struct drm_device
*dev
, u32 level
,
2121 enum port port
, int type
)
2123 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2124 const struct bxt_ddi_buf_trans
*ddi_translations
;
2128 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
2129 n_entries
= ARRAY_SIZE(bxt_ddi_translations_dp
);
2130 ddi_translations
= bxt_ddi_translations_dp
;
2131 } else if (type
== INTEL_OUTPUT_HDMI
) {
2132 n_entries
= ARRAY_SIZE(bxt_ddi_translations_hdmi
);
2133 ddi_translations
= bxt_ddi_translations_hdmi
;
2135 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
2140 /* Check if default value has to be used */
2141 if (level
>= n_entries
||
2142 (type
== INTEL_OUTPUT_HDMI
&& level
== HDMI_LEVEL_SHIFT_UNKNOWN
)) {
2143 for (i
= 0; i
< n_entries
; i
++) {
2144 if (ddi_translations
[i
].default_index
) {
2152 * While we write to the group register to program all lanes at once we
2153 * can read only lane registers and we pick lanes 0/1 for that.
2155 val
= I915_READ(BXT_PORT_PCS_DW10_LN01(port
));
2156 val
&= ~(TX2_SWING_CALC_INIT
| TX1_SWING_CALC_INIT
);
2157 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port
), val
);
2159 val
= I915_READ(BXT_PORT_TX_DW2_LN0(port
));
2160 val
&= ~(MARGIN_000
| UNIQ_TRANS_SCALE
);
2161 val
|= ddi_translations
[level
].margin
<< MARGIN_000_SHIFT
|
2162 ddi_translations
[level
].scale
<< UNIQ_TRANS_SCALE_SHIFT
;
2163 I915_WRITE(BXT_PORT_TX_DW2_GRP(port
), val
);
2165 val
= I915_READ(BXT_PORT_TX_DW3_LN0(port
));
2166 val
&= ~UNIQE_TRANGE_EN_METHOD
;
2167 if (ddi_translations
[level
].enable
)
2168 val
|= UNIQE_TRANGE_EN_METHOD
;
2169 I915_WRITE(BXT_PORT_TX_DW3_GRP(port
), val
);
2171 val
= I915_READ(BXT_PORT_TX_DW4_LN0(port
));
2172 val
&= ~DE_EMPHASIS
;
2173 val
|= ddi_translations
[level
].deemphasis
<< DEEMPH_SHIFT
;
2174 I915_WRITE(BXT_PORT_TX_DW4_GRP(port
), val
);
2176 val
= I915_READ(BXT_PORT_PCS_DW10_LN01(port
));
2177 val
|= TX2_SWING_CALC_INIT
| TX1_SWING_CALC_INIT
;
2178 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port
), val
);
2181 static uint32_t translate_signal_level(int signal_levels
)
2185 switch (signal_levels
) {
2187 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2189 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
2192 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
2195 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
2198 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_3
:
2202 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
2205 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
2208 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
2212 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
2215 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
2219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
2227 uint32_t ddi_signal_levels(struct intel_dp
*intel_dp
)
2229 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2230 struct drm_device
*dev
= dport
->base
.base
.dev
;
2231 struct intel_encoder
*encoder
= &dport
->base
;
2232 uint8_t train_set
= intel_dp
->train_set
[0];
2233 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2234 DP_TRAIN_PRE_EMPHASIS_MASK
);
2235 enum port port
= dport
->port
;
2238 level
= translate_signal_level(signal_levels
);
2240 if (IS_SKYLAKE(dev
))
2241 skl_ddi_set_iboost(dev
, level
, port
, encoder
->type
);
2242 else if (IS_BROXTON(dev
))
2243 bxt_ddi_vswing_sequence(dev
, level
, port
, encoder
->type
);
2245 return DDI_BUF_TRANS_SELECT(level
);
2248 static void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder
)
2250 struct drm_encoder
*encoder
= &intel_encoder
->base
;
2251 struct drm_device
*dev
= encoder
->dev
;
2252 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2253 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->crtc
);
2254 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
2255 int type
= intel_encoder
->type
;
2258 if (type
== INTEL_OUTPUT_EDP
) {
2259 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2260 intel_edp_panel_on(intel_dp
);
2263 if (IS_SKYLAKE(dev
)) {
2264 uint32_t dpll
= crtc
->config
->ddi_pll_sel
;
2268 * DPLL0 is used for eDP and is the only "private" DPLL (as
2269 * opposed to shared) on SKL
2271 if (type
== INTEL_OUTPUT_EDP
) {
2272 WARN_ON(dpll
!= SKL_DPLL0
);
2274 val
= I915_READ(DPLL_CTRL1
);
2276 val
&= ~(DPLL_CTRL1_HDMI_MODE(dpll
) |
2277 DPLL_CTRL1_SSC(dpll
) |
2278 DPLL_CTRL1_LINK_RATE_MASK(dpll
));
2279 val
|= crtc
->config
->dpll_hw_state
.ctrl1
<< (dpll
* 6);
2281 I915_WRITE(DPLL_CTRL1
, val
);
2282 POSTING_READ(DPLL_CTRL1
);
2285 /* DDI -> PLL mapping */
2286 val
= I915_READ(DPLL_CTRL2
);
2288 val
&= ~(DPLL_CTRL2_DDI_CLK_OFF(port
) |
2289 DPLL_CTRL2_DDI_CLK_SEL_MASK(port
));
2290 val
|= (DPLL_CTRL2_DDI_CLK_SEL(dpll
, port
) |
2291 DPLL_CTRL2_DDI_SEL_OVERRIDE(port
));
2293 I915_WRITE(DPLL_CTRL2
, val
);
2295 } else if (INTEL_INFO(dev
)->gen
< 9) {
2296 WARN_ON(crtc
->config
->ddi_pll_sel
== PORT_CLK_SEL_NONE
);
2297 I915_WRITE(PORT_CLK_SEL(port
), crtc
->config
->ddi_pll_sel
);
2300 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
2301 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2303 intel_ddi_init_dp_buf_reg(intel_encoder
);
2305 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2306 intel_dp_start_link_train(intel_dp
);
2307 intel_dp_complete_link_train(intel_dp
);
2308 if (port
!= PORT_A
|| INTEL_INFO(dev
)->gen
>= 9)
2309 intel_dp_stop_link_train(intel_dp
);
2310 } else if (type
== INTEL_OUTPUT_HDMI
) {
2311 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
2313 if (IS_BROXTON(dev
)) {
2314 hdmi_level
= dev_priv
->vbt
.
2315 ddi_port_info
[port
].hdmi_level_shift
;
2316 bxt_ddi_vswing_sequence(dev
, hdmi_level
, port
,
2319 intel_hdmi
->set_infoframes(encoder
,
2320 crtc
->config
->has_hdmi_sink
,
2321 &crtc
->config
->base
.adjusted_mode
);
2325 static void intel_ddi_post_disable(struct intel_encoder
*intel_encoder
)
2327 struct drm_encoder
*encoder
= &intel_encoder
->base
;
2328 struct drm_device
*dev
= encoder
->dev
;
2329 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2330 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
2331 int type
= intel_encoder
->type
;
2335 val
= I915_READ(DDI_BUF_CTL(port
));
2336 if (val
& DDI_BUF_CTL_ENABLE
) {
2337 val
&= ~DDI_BUF_CTL_ENABLE
;
2338 I915_WRITE(DDI_BUF_CTL(port
), val
);
2342 val
= I915_READ(DP_TP_CTL(port
));
2343 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
2344 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2345 I915_WRITE(DP_TP_CTL(port
), val
);
2348 intel_wait_ddi_buf_idle(dev_priv
, port
);
2350 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
2351 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2352 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2353 intel_edp_panel_vdd_on(intel_dp
);
2354 intel_edp_panel_off(intel_dp
);
2357 if (IS_SKYLAKE(dev
))
2358 I915_WRITE(DPLL_CTRL2
, (I915_READ(DPLL_CTRL2
) |
2359 DPLL_CTRL2_DDI_CLK_OFF(port
)));
2360 else if (INTEL_INFO(dev
)->gen
< 9)
2361 I915_WRITE(PORT_CLK_SEL(port
), PORT_CLK_SEL_NONE
);
2364 static void intel_enable_ddi(struct intel_encoder
*intel_encoder
)
2366 struct drm_encoder
*encoder
= &intel_encoder
->base
;
2367 struct drm_crtc
*crtc
= encoder
->crtc
;
2368 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2369 struct drm_device
*dev
= encoder
->dev
;
2370 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2371 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
2372 int type
= intel_encoder
->type
;
2374 if (type
== INTEL_OUTPUT_HDMI
) {
2375 struct intel_digital_port
*intel_dig_port
=
2376 enc_to_dig_port(encoder
);
2378 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2379 * are ignored so nothing special needs to be done besides
2380 * enabling the port.
2382 I915_WRITE(DDI_BUF_CTL(port
),
2383 intel_dig_port
->saved_port_bits
|
2384 DDI_BUF_CTL_ENABLE
);
2385 } else if (type
== INTEL_OUTPUT_EDP
) {
2386 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2388 if (port
== PORT_A
&& INTEL_INFO(dev
)->gen
< 9)
2389 intel_dp_stop_link_train(intel_dp
);
2391 intel_edp_backlight_on(intel_dp
);
2392 intel_psr_enable(intel_dp
);
2393 intel_edp_drrs_enable(intel_dp
);
2396 if (intel_crtc
->config
->has_audio
) {
2397 intel_display_power_get(dev_priv
, POWER_DOMAIN_AUDIO
);
2398 intel_audio_codec_enable(intel_encoder
);
2402 static void intel_disable_ddi(struct intel_encoder
*intel_encoder
)
2404 struct drm_encoder
*encoder
= &intel_encoder
->base
;
2405 struct drm_crtc
*crtc
= encoder
->crtc
;
2406 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2407 int type
= intel_encoder
->type
;
2408 struct drm_device
*dev
= encoder
->dev
;
2409 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2411 if (intel_crtc
->config
->has_audio
) {
2412 intel_audio_codec_disable(intel_encoder
);
2413 intel_display_power_put(dev_priv
, POWER_DOMAIN_AUDIO
);
2416 if (type
== INTEL_OUTPUT_EDP
) {
2417 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2419 intel_edp_drrs_disable(intel_dp
);
2420 intel_psr_disable(intel_dp
);
2421 intel_edp_backlight_off(intel_dp
);
2425 static void hsw_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
2426 struct intel_shared_dpll
*pll
)
2428 I915_WRITE(WRPLL_CTL(pll
->id
), pll
->config
.hw_state
.wrpll
);
2429 POSTING_READ(WRPLL_CTL(pll
->id
));
2433 static void hsw_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
2434 struct intel_shared_dpll
*pll
)
2438 val
= I915_READ(WRPLL_CTL(pll
->id
));
2439 I915_WRITE(WRPLL_CTL(pll
->id
), val
& ~WRPLL_PLL_ENABLE
);
2440 POSTING_READ(WRPLL_CTL(pll
->id
));
2443 static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
2444 struct intel_shared_dpll
*pll
,
2445 struct intel_dpll_hw_state
*hw_state
)
2449 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
2452 val
= I915_READ(WRPLL_CTL(pll
->id
));
2453 hw_state
->wrpll
= val
;
2455 return val
& WRPLL_PLL_ENABLE
;
2458 static const char * const hsw_ddi_pll_names
[] = {
2463 static void hsw_shared_dplls_init(struct drm_i915_private
*dev_priv
)
2467 dev_priv
->num_shared_dpll
= 2;
2469 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
2470 dev_priv
->shared_dplls
[i
].id
= i
;
2471 dev_priv
->shared_dplls
[i
].name
= hsw_ddi_pll_names
[i
];
2472 dev_priv
->shared_dplls
[i
].disable
= hsw_ddi_pll_disable
;
2473 dev_priv
->shared_dplls
[i
].enable
= hsw_ddi_pll_enable
;
2474 dev_priv
->shared_dplls
[i
].get_hw_state
=
2475 hsw_ddi_pll_get_hw_state
;
2479 static const char * const skl_ddi_pll_names
[] = {
2485 struct skl_dpll_regs
{
2486 u32 ctl
, cfgcr1
, cfgcr2
;
2489 /* this array is indexed by the *shared* pll id */
2490 static const struct skl_dpll_regs skl_dpll_regs
[3] = {
2494 .cfgcr1
= DPLL1_CFGCR1
,
2495 .cfgcr2
= DPLL1_CFGCR2
,
2500 .cfgcr1
= DPLL2_CFGCR1
,
2501 .cfgcr2
= DPLL2_CFGCR2
,
2506 .cfgcr1
= DPLL3_CFGCR1
,
2507 .cfgcr2
= DPLL3_CFGCR2
,
2511 static void skl_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
2512 struct intel_shared_dpll
*pll
)
2516 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
2518 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2521 val
= I915_READ(DPLL_CTRL1
);
2523 val
&= ~(DPLL_CTRL1_HDMI_MODE(dpll
) | DPLL_CTRL1_SSC(dpll
) |
2524 DPLL_CTRL1_LINK_RATE_MASK(dpll
));
2525 val
|= pll
->config
.hw_state
.ctrl1
<< (dpll
* 6);
2527 I915_WRITE(DPLL_CTRL1
, val
);
2528 POSTING_READ(DPLL_CTRL1
);
2530 I915_WRITE(regs
[pll
->id
].cfgcr1
, pll
->config
.hw_state
.cfgcr1
);
2531 I915_WRITE(regs
[pll
->id
].cfgcr2
, pll
->config
.hw_state
.cfgcr2
);
2532 POSTING_READ(regs
[pll
->id
].cfgcr1
);
2533 POSTING_READ(regs
[pll
->id
].cfgcr2
);
2535 /* the enable bit is always bit 31 */
2536 I915_WRITE(regs
[pll
->id
].ctl
,
2537 I915_READ(regs
[pll
->id
].ctl
) | LCPLL_PLL_ENABLE
);
2539 if (wait_for(I915_READ(DPLL_STATUS
) & DPLL_LOCK(dpll
), 5))
2540 DRM_ERROR("DPLL %d not locked\n", dpll
);
2543 static void skl_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
2544 struct intel_shared_dpll
*pll
)
2546 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
2548 /* the enable bit is always bit 31 */
2549 I915_WRITE(regs
[pll
->id
].ctl
,
2550 I915_READ(regs
[pll
->id
].ctl
) & ~LCPLL_PLL_ENABLE
);
2551 POSTING_READ(regs
[pll
->id
].ctl
);
2554 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
2555 struct intel_shared_dpll
*pll
,
2556 struct intel_dpll_hw_state
*hw_state
)
2560 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
2562 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
2565 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2568 val
= I915_READ(regs
[pll
->id
].ctl
);
2569 if (!(val
& LCPLL_PLL_ENABLE
))
2572 val
= I915_READ(DPLL_CTRL1
);
2573 hw_state
->ctrl1
= (val
>> (dpll
* 6)) & 0x3f;
2575 /* avoid reading back stale values if HDMI mode is not enabled */
2576 if (val
& DPLL_CTRL1_HDMI_MODE(dpll
)) {
2577 hw_state
->cfgcr1
= I915_READ(regs
[pll
->id
].cfgcr1
);
2578 hw_state
->cfgcr2
= I915_READ(regs
[pll
->id
].cfgcr2
);
2584 static void skl_shared_dplls_init(struct drm_i915_private
*dev_priv
)
2588 dev_priv
->num_shared_dpll
= 3;
2590 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
2591 dev_priv
->shared_dplls
[i
].id
= i
;
2592 dev_priv
->shared_dplls
[i
].name
= skl_ddi_pll_names
[i
];
2593 dev_priv
->shared_dplls
[i
].disable
= skl_ddi_pll_disable
;
2594 dev_priv
->shared_dplls
[i
].enable
= skl_ddi_pll_enable
;
2595 dev_priv
->shared_dplls
[i
].get_hw_state
=
2596 skl_ddi_pll_get_hw_state
;
2600 static void broxton_phy_init(struct drm_i915_private
*dev_priv
,
2606 val
= I915_READ(BXT_P_CR_GT_DISP_PWRON
);
2607 val
|= GT_DISPLAY_POWER_ON(phy
);
2608 I915_WRITE(BXT_P_CR_GT_DISP_PWRON
, val
);
2610 /* Considering 10ms timeout until BSpec is updated */
2611 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy
)) & PHY_POWER_GOOD
, 10))
2612 DRM_ERROR("timeout during PHY%d power on\n", phy
);
2614 for (port
= (phy
== DPIO_PHY0
? PORT_B
: PORT_A
);
2615 port
<= (phy
== DPIO_PHY0
? PORT_C
: PORT_A
); port
++) {
2618 for (lane
= 0; lane
< 4; lane
++) {
2619 val
= I915_READ(BXT_PORT_TX_DW14_LN(port
, lane
));
2621 * Note that on CHV this flag is called UPAR, but has
2622 * the same function.
2624 val
&= ~LATENCY_OPTIM
;
2626 val
|= LATENCY_OPTIM
;
2628 I915_WRITE(BXT_PORT_TX_DW14_LN(port
, lane
), val
);
2632 /* Program PLL Rcomp code offset */
2633 val
= I915_READ(BXT_PORT_CL1CM_DW9(phy
));
2634 val
&= ~IREF0RC_OFFSET_MASK
;
2635 val
|= 0xE4 << IREF0RC_OFFSET_SHIFT
;
2636 I915_WRITE(BXT_PORT_CL1CM_DW9(phy
), val
);
2638 val
= I915_READ(BXT_PORT_CL1CM_DW10(phy
));
2639 val
&= ~IREF1RC_OFFSET_MASK
;
2640 val
|= 0xE4 << IREF1RC_OFFSET_SHIFT
;
2641 I915_WRITE(BXT_PORT_CL1CM_DW10(phy
), val
);
2643 /* Program power gating */
2644 val
= I915_READ(BXT_PORT_CL1CM_DW28(phy
));
2645 val
|= OCL1_POWER_DOWN_EN
| DW28_OLDO_DYN_PWR_DOWN_EN
|
2647 I915_WRITE(BXT_PORT_CL1CM_DW28(phy
), val
);
2649 if (phy
== DPIO_PHY0
) {
2650 val
= I915_READ(BXT_PORT_CL2CM_DW6_BC
);
2651 val
|= DW6_OLDO_DYN_PWR_DOWN_EN
;
2652 I915_WRITE(BXT_PORT_CL2CM_DW6_BC
, val
);
2655 val
= I915_READ(BXT_PORT_CL1CM_DW30(phy
));
2656 val
&= ~OCL2_LDOFUSE_PWR_DIS
;
2658 * On PHY1 disable power on the second channel, since no port is
2659 * connected there. On PHY0 both channels have a port, so leave it
2661 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2662 * power down the second channel on PHY0 as well.
2664 if (phy
== DPIO_PHY1
)
2665 val
|= OCL2_LDOFUSE_PWR_DIS
;
2666 I915_WRITE(BXT_PORT_CL1CM_DW30(phy
), val
);
2668 if (phy
== DPIO_PHY0
) {
2671 * PHY0 isn't connected to an RCOMP resistor so copy over
2672 * the corresponding calibrated value from PHY1, and disable
2673 * the automatic calibration on PHY0.
2675 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1
)) & GRC_DONE
,
2677 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2679 val
= I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1
));
2680 val
= (val
& GRC_CODE_MASK
) >> GRC_CODE_SHIFT
;
2681 grc_code
= val
<< GRC_CODE_FAST_SHIFT
|
2682 val
<< GRC_CODE_SLOW_SHIFT
|
2684 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0
), grc_code
);
2686 val
= I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0
));
2687 val
|= GRC_DIS
| GRC_RDY_OVRD
;
2688 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0
), val
);
2691 val
= I915_READ(BXT_PHY_CTL_FAMILY(phy
));
2692 val
|= COMMON_RESET_DIS
;
2693 I915_WRITE(BXT_PHY_CTL_FAMILY(phy
), val
);
2696 void broxton_ddi_phy_init(struct drm_device
*dev
)
2698 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2699 broxton_phy_init(dev
->dev_private
, DPIO_PHY1
);
2700 broxton_phy_init(dev
->dev_private
, DPIO_PHY0
);
2703 static void broxton_phy_uninit(struct drm_i915_private
*dev_priv
,
2708 val
= I915_READ(BXT_PHY_CTL_FAMILY(phy
));
2709 val
&= ~COMMON_RESET_DIS
;
2710 I915_WRITE(BXT_PHY_CTL_FAMILY(phy
), val
);
2713 void broxton_ddi_phy_uninit(struct drm_device
*dev
)
2715 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2717 broxton_phy_uninit(dev_priv
, DPIO_PHY1
);
2718 broxton_phy_uninit(dev_priv
, DPIO_PHY0
);
2720 /* FIXME: do this in broxton_phy_uninit per phy */
2721 I915_WRITE(BXT_P_CR_GT_DISP_PWRON
, 0);
2724 static const char * const bxt_ddi_pll_names
[] = {
2730 static void bxt_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
2731 struct intel_shared_dpll
*pll
)
2734 enum port port
= (enum port
)pll
->id
; /* 1:1 port->PLL mapping */
2736 temp
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
2737 temp
&= ~PORT_PLL_REF_SEL
;
2738 /* Non-SSC reference */
2739 I915_WRITE(BXT_PORT_PLL_ENABLE(port
), temp
);
2741 /* Disable 10 bit clock */
2742 temp
= I915_READ(BXT_PORT_PLL_EBB_4(port
));
2743 temp
&= ~PORT_PLL_10BIT_CLK_ENABLE
;
2744 I915_WRITE(BXT_PORT_PLL_EBB_4(port
), temp
);
2747 temp
= I915_READ(BXT_PORT_PLL_EBB_0(port
));
2748 temp
&= ~(PORT_PLL_P1_MASK
| PORT_PLL_P2_MASK
);
2749 temp
|= pll
->config
.hw_state
.ebb0
;
2750 I915_WRITE(BXT_PORT_PLL_EBB_0(port
), temp
);
2752 /* Write M2 integer */
2753 temp
= I915_READ(BXT_PORT_PLL(port
, 0));
2754 temp
&= ~PORT_PLL_M2_MASK
;
2755 temp
|= pll
->config
.hw_state
.pll0
;
2756 I915_WRITE(BXT_PORT_PLL(port
, 0), temp
);
2759 temp
= I915_READ(BXT_PORT_PLL(port
, 1));
2760 temp
&= ~PORT_PLL_N_MASK
;
2761 temp
|= pll
->config
.hw_state
.pll1
;
2762 I915_WRITE(BXT_PORT_PLL(port
, 1), temp
);
2764 /* Write M2 fraction */
2765 temp
= I915_READ(BXT_PORT_PLL(port
, 2));
2766 temp
&= ~PORT_PLL_M2_FRAC_MASK
;
2767 temp
|= pll
->config
.hw_state
.pll2
;
2768 I915_WRITE(BXT_PORT_PLL(port
, 2), temp
);
2770 /* Write M2 fraction enable */
2771 temp
= I915_READ(BXT_PORT_PLL(port
, 3));
2772 temp
&= ~PORT_PLL_M2_FRAC_ENABLE
;
2773 temp
|= pll
->config
.hw_state
.pll3
;
2774 I915_WRITE(BXT_PORT_PLL(port
, 3), temp
);
2777 temp
= I915_READ(BXT_PORT_PLL(port
, 6));
2778 temp
&= ~PORT_PLL_PROP_COEFF_MASK
;
2779 temp
&= ~PORT_PLL_INT_COEFF_MASK
;
2780 temp
&= ~PORT_PLL_GAIN_CTL_MASK
;
2781 temp
|= pll
->config
.hw_state
.pll6
;
2782 I915_WRITE(BXT_PORT_PLL(port
, 6), temp
);
2784 /* Write calibration val */
2785 temp
= I915_READ(BXT_PORT_PLL(port
, 8));
2786 temp
&= ~PORT_PLL_TARGET_CNT_MASK
;
2787 temp
|= pll
->config
.hw_state
.pll8
;
2788 I915_WRITE(BXT_PORT_PLL(port
, 8), temp
);
2790 temp
= I915_READ(BXT_PORT_PLL(port
, 9));
2791 temp
&= ~PORT_PLL_LOCK_THRESHOLD_MASK
;
2792 temp
|= pll
->config
.hw_state
.pll9
;
2793 I915_WRITE(BXT_PORT_PLL(port
, 9), temp
);
2795 temp
= I915_READ(BXT_PORT_PLL(port
, 10));
2796 temp
&= ~PORT_PLL_DCO_AMP_OVR_EN_H
;
2797 temp
&= ~PORT_PLL_DCO_AMP_MASK
;
2798 temp
|= pll
->config
.hw_state
.pll10
;
2799 I915_WRITE(BXT_PORT_PLL(port
, 10), temp
);
2801 /* Recalibrate with new settings */
2802 temp
= I915_READ(BXT_PORT_PLL_EBB_4(port
));
2803 temp
|= PORT_PLL_RECALIBRATE
;
2804 I915_WRITE(BXT_PORT_PLL_EBB_4(port
), temp
);
2805 temp
&= ~PORT_PLL_10BIT_CLK_ENABLE
;
2806 temp
|= pll
->config
.hw_state
.ebb4
;
2807 I915_WRITE(BXT_PORT_PLL_EBB_4(port
), temp
);
2810 temp
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
2811 temp
|= PORT_PLL_ENABLE
;
2812 I915_WRITE(BXT_PORT_PLL_ENABLE(port
), temp
);
2813 POSTING_READ(BXT_PORT_PLL_ENABLE(port
));
2815 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port
)) &
2816 PORT_PLL_LOCK
), 200))
2817 DRM_ERROR("PLL %d not locked\n", port
);
2820 * While we write to the group register to program all lanes at once we
2821 * can read only lane registers and we pick lanes 0/1 for that.
2823 temp
= I915_READ(BXT_PORT_PCS_DW12_LN01(port
));
2824 temp
&= ~LANE_STAGGER_MASK
;
2825 temp
&= ~LANESTAGGER_STRAP_OVRD
;
2826 temp
|= pll
->config
.hw_state
.pcsdw12
;
2827 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port
), temp
);
2830 static void bxt_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
2831 struct intel_shared_dpll
*pll
)
2833 enum port port
= (enum port
)pll
->id
; /* 1:1 port->PLL mapping */
2836 temp
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
2837 temp
&= ~PORT_PLL_ENABLE
;
2838 I915_WRITE(BXT_PORT_PLL_ENABLE(port
), temp
);
2839 POSTING_READ(BXT_PORT_PLL_ENABLE(port
));
2842 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
2843 struct intel_shared_dpll
*pll
,
2844 struct intel_dpll_hw_state
*hw_state
)
2846 enum port port
= (enum port
)pll
->id
; /* 1:1 port->PLL mapping */
2849 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
2852 val
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
2853 if (!(val
& PORT_PLL_ENABLE
))
2856 hw_state
->ebb0
= I915_READ(BXT_PORT_PLL_EBB_0(port
));
2857 hw_state
->ebb0
&= PORT_PLL_P1_MASK
| PORT_PLL_P2_MASK
;
2859 hw_state
->ebb4
= I915_READ(BXT_PORT_PLL_EBB_4(port
));
2860 hw_state
->ebb4
&= PORT_PLL_10BIT_CLK_ENABLE
;
2862 hw_state
->pll0
= I915_READ(BXT_PORT_PLL(port
, 0));
2863 hw_state
->pll0
&= PORT_PLL_M2_MASK
;
2865 hw_state
->pll1
= I915_READ(BXT_PORT_PLL(port
, 1));
2866 hw_state
->pll1
&= PORT_PLL_N_MASK
;
2868 hw_state
->pll2
= I915_READ(BXT_PORT_PLL(port
, 2));
2869 hw_state
->pll2
&= PORT_PLL_M2_FRAC_MASK
;
2871 hw_state
->pll3
= I915_READ(BXT_PORT_PLL(port
, 3));
2872 hw_state
->pll3
&= PORT_PLL_M2_FRAC_ENABLE
;
2874 hw_state
->pll6
= I915_READ(BXT_PORT_PLL(port
, 6));
2875 hw_state
->pll6
&= PORT_PLL_PROP_COEFF_MASK
|
2876 PORT_PLL_INT_COEFF_MASK
|
2877 PORT_PLL_GAIN_CTL_MASK
;
2879 hw_state
->pll8
= I915_READ(BXT_PORT_PLL(port
, 8));
2880 hw_state
->pll8
&= PORT_PLL_TARGET_CNT_MASK
;
2882 hw_state
->pll9
= I915_READ(BXT_PORT_PLL(port
, 9));
2883 hw_state
->pll9
&= PORT_PLL_LOCK_THRESHOLD_MASK
;
2885 hw_state
->pll10
= I915_READ(BXT_PORT_PLL(port
, 10));
2886 hw_state
->pll10
&= PORT_PLL_DCO_AMP_OVR_EN_H
|
2887 PORT_PLL_DCO_AMP_MASK
;
2890 * While we write to the group register to program all lanes at once we
2891 * can read only lane registers. We configure all lanes the same way, so
2892 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2894 hw_state
->pcsdw12
= I915_READ(BXT_PORT_PCS_DW12_LN01(port
));
2895 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port
) != hw_state
->pcsdw12
))
2896 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2898 I915_READ(BXT_PORT_PCS_DW12_LN23(port
)));
2899 hw_state
->pcsdw12
&= LANE_STAGGER_MASK
| LANESTAGGER_STRAP_OVRD
;
2904 static void bxt_shared_dplls_init(struct drm_i915_private
*dev_priv
)
2908 dev_priv
->num_shared_dpll
= 3;
2910 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
2911 dev_priv
->shared_dplls
[i
].id
= i
;
2912 dev_priv
->shared_dplls
[i
].name
= bxt_ddi_pll_names
[i
];
2913 dev_priv
->shared_dplls
[i
].disable
= bxt_ddi_pll_disable
;
2914 dev_priv
->shared_dplls
[i
].enable
= bxt_ddi_pll_enable
;
2915 dev_priv
->shared_dplls
[i
].get_hw_state
=
2916 bxt_ddi_pll_get_hw_state
;
2920 void intel_ddi_pll_init(struct drm_device
*dev
)
2922 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2923 uint32_t val
= I915_READ(LCPLL_CTL
);
2925 if (IS_SKYLAKE(dev
))
2926 skl_shared_dplls_init(dev_priv
);
2927 else if (IS_BROXTON(dev
))
2928 bxt_shared_dplls_init(dev_priv
);
2930 hsw_shared_dplls_init(dev_priv
);
2932 if (IS_SKYLAKE(dev
)) {
2935 cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
2936 dev_priv
->skl_boot_cdclk
= cdclk_freq
;
2937 if (!(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_ENABLE
))
2938 DRM_ERROR("LCPLL1 is disabled\n");
2940 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
2941 } else if (IS_BROXTON(dev
)) {
2942 broxton_init_cdclk(dev
);
2943 broxton_ddi_phy_init(dev
);
2946 * The LCPLL register should be turned on by the BIOS. For now
2947 * let's just check its state and print errors in case
2948 * something is wrong. Don't even try to turn it on.
2951 if (val
& LCPLL_CD_SOURCE_FCLK
)
2952 DRM_ERROR("CDCLK source is not LCPLL\n");
2954 if (val
& LCPLL_PLL_DISABLE
)
2955 DRM_ERROR("LCPLL is disabled\n");
2959 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
)
2961 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
2962 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
2963 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
2964 enum port port
= intel_dig_port
->port
;
2968 if (I915_READ(DP_TP_CTL(port
)) & DP_TP_CTL_ENABLE
) {
2969 val
= I915_READ(DDI_BUF_CTL(port
));
2970 if (val
& DDI_BUF_CTL_ENABLE
) {
2971 val
&= ~DDI_BUF_CTL_ENABLE
;
2972 I915_WRITE(DDI_BUF_CTL(port
), val
);
2976 val
= I915_READ(DP_TP_CTL(port
));
2977 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
2978 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2979 I915_WRITE(DP_TP_CTL(port
), val
);
2980 POSTING_READ(DP_TP_CTL(port
));
2983 intel_wait_ddi_buf_idle(dev_priv
, port
);
2986 val
= DP_TP_CTL_ENABLE
|
2987 DP_TP_CTL_LINK_TRAIN_PAT1
| DP_TP_CTL_SCRAMBLE_DISABLE
;
2988 if (intel_dp
->is_mst
)
2989 val
|= DP_TP_CTL_MODE_MST
;
2991 val
|= DP_TP_CTL_MODE_SST
;
2992 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
2993 val
|= DP_TP_CTL_ENHANCED_FRAME_ENABLE
;
2995 I915_WRITE(DP_TP_CTL(port
), val
);
2996 POSTING_READ(DP_TP_CTL(port
));
2998 intel_dp
->DP
|= DDI_BUF_CTL_ENABLE
;
2999 I915_WRITE(DDI_BUF_CTL(port
), intel_dp
->DP
);
3000 POSTING_READ(DDI_BUF_CTL(port
));
3005 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
)
3007 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
3008 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
3011 intel_ddi_post_disable(intel_encoder
);
3013 val
= I915_READ(_FDI_RXA_CTL
);
3014 val
&= ~FDI_RX_ENABLE
;
3015 I915_WRITE(_FDI_RXA_CTL
, val
);
3017 val
= I915_READ(_FDI_RXA_MISC
);
3018 val
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
3019 val
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3020 I915_WRITE(_FDI_RXA_MISC
, val
);
3022 val
= I915_READ(_FDI_RXA_CTL
);
3024 I915_WRITE(_FDI_RXA_CTL
, val
);
3026 val
= I915_READ(_FDI_RXA_CTL
);
3027 val
&= ~FDI_RX_PLL_ENABLE
;
3028 I915_WRITE(_FDI_RXA_CTL
, val
);
3031 void intel_ddi_get_config(struct intel_encoder
*encoder
,
3032 struct intel_crtc_state
*pipe_config
)
3034 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
3035 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
3036 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
3037 struct intel_hdmi
*intel_hdmi
;
3038 u32 temp
, flags
= 0;
3040 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
3041 if (temp
& TRANS_DDI_PHSYNC
)
3042 flags
|= DRM_MODE_FLAG_PHSYNC
;
3044 flags
|= DRM_MODE_FLAG_NHSYNC
;
3045 if (temp
& TRANS_DDI_PVSYNC
)
3046 flags
|= DRM_MODE_FLAG_PVSYNC
;
3048 flags
|= DRM_MODE_FLAG_NVSYNC
;
3050 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
3052 switch (temp
& TRANS_DDI_BPC_MASK
) {
3053 case TRANS_DDI_BPC_6
:
3054 pipe_config
->pipe_bpp
= 18;
3056 case TRANS_DDI_BPC_8
:
3057 pipe_config
->pipe_bpp
= 24;
3059 case TRANS_DDI_BPC_10
:
3060 pipe_config
->pipe_bpp
= 30;
3062 case TRANS_DDI_BPC_12
:
3063 pipe_config
->pipe_bpp
= 36;
3069 switch (temp
& TRANS_DDI_MODE_SELECT_MASK
) {
3070 case TRANS_DDI_MODE_SELECT_HDMI
:
3071 pipe_config
->has_hdmi_sink
= true;
3072 intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
3074 if (intel_hdmi
->infoframe_enabled(&encoder
->base
))
3075 pipe_config
->has_infoframe
= true;
3077 case TRANS_DDI_MODE_SELECT_DVI
:
3078 case TRANS_DDI_MODE_SELECT_FDI
:
3080 case TRANS_DDI_MODE_SELECT_DP_SST
:
3081 case TRANS_DDI_MODE_SELECT_DP_MST
:
3082 pipe_config
->has_dp_encoder
= true;
3083 intel_dp_get_m_n(intel_crtc
, pipe_config
);
3089 if (intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_AUDIO
)) {
3090 temp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
3091 if (temp
& AUDIO_OUTPUT_ENABLE(intel_crtc
->pipe
))
3092 pipe_config
->has_audio
= true;
3095 if (encoder
->type
== INTEL_OUTPUT_EDP
&& dev_priv
->vbt
.edp_bpp
&&
3096 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
3098 * This is a big fat ugly hack.
3100 * Some machines in UEFI boot mode provide us a VBT that has 18
3101 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3102 * unknown we fail to light up. Yet the same BIOS boots up with
3103 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3104 * max, not what it tells us to use.
3106 * Note: This will still be broken if the eDP panel is not lit
3107 * up by the BIOS, and thus we can't get the mode at module
3110 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3111 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
3112 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
3115 intel_ddi_clock_get(encoder
, pipe_config
);
3118 static void intel_ddi_destroy(struct drm_encoder
*encoder
)
3120 /* HDMI has nothing special to destroy, so we can go with this. */
3121 intel_dp_encoder_destroy(encoder
);
3124 static bool intel_ddi_compute_config(struct intel_encoder
*encoder
,
3125 struct intel_crtc_state
*pipe_config
)
3127 int type
= encoder
->type
;
3128 int port
= intel_ddi_get_encoder_port(encoder
);
3130 WARN(type
== INTEL_OUTPUT_UNKNOWN
, "compute_config() on unknown output!\n");
3133 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
3135 if (type
== INTEL_OUTPUT_HDMI
)
3136 return intel_hdmi_compute_config(encoder
, pipe_config
);
3138 return intel_dp_compute_config(encoder
, pipe_config
);
3141 static const struct drm_encoder_funcs intel_ddi_funcs
= {
3142 .destroy
= intel_ddi_destroy
,
3145 static struct intel_connector
*
3146 intel_ddi_init_dp_connector(struct intel_digital_port
*intel_dig_port
)
3148 struct intel_connector
*connector
;
3149 enum port port
= intel_dig_port
->port
;
3151 connector
= intel_connector_alloc();
3155 intel_dig_port
->dp
.output_reg
= DDI_BUF_CTL(port
);
3156 if (!intel_dp_init_connector(intel_dig_port
, connector
)) {
3164 static struct intel_connector
*
3165 intel_ddi_init_hdmi_connector(struct intel_digital_port
*intel_dig_port
)
3167 struct intel_connector
*connector
;
3168 enum port port
= intel_dig_port
->port
;
3170 connector
= intel_connector_alloc();
3174 intel_dig_port
->hdmi
.hdmi_reg
= DDI_BUF_CTL(port
);
3175 intel_hdmi_init_connector(intel_dig_port
, connector
);
3180 void intel_ddi_init(struct drm_device
*dev
, enum port port
)
3182 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3183 struct intel_digital_port
*intel_dig_port
;
3184 struct intel_encoder
*intel_encoder
;
3185 struct drm_encoder
*encoder
;
3186 bool init_hdmi
, init_dp
;
3188 init_hdmi
= (dev_priv
->vbt
.ddi_port_info
[port
].supports_dvi
||
3189 dev_priv
->vbt
.ddi_port_info
[port
].supports_hdmi
);
3190 init_dp
= dev_priv
->vbt
.ddi_port_info
[port
].supports_dp
;
3191 if (!init_dp
&& !init_hdmi
) {
3192 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
3198 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
3199 if (!intel_dig_port
)
3202 intel_encoder
= &intel_dig_port
->base
;
3203 encoder
= &intel_encoder
->base
;
3205 drm_encoder_init(dev
, encoder
, &intel_ddi_funcs
,
3206 DRM_MODE_ENCODER_TMDS
);
3208 intel_encoder
->compute_config
= intel_ddi_compute_config
;
3209 intel_encoder
->enable
= intel_enable_ddi
;
3210 intel_encoder
->pre_enable
= intel_ddi_pre_enable
;
3211 intel_encoder
->disable
= intel_disable_ddi
;
3212 intel_encoder
->post_disable
= intel_ddi_post_disable
;
3213 intel_encoder
->get_hw_state
= intel_ddi_get_hw_state
;
3214 intel_encoder
->get_config
= intel_ddi_get_config
;
3216 intel_dig_port
->port
= port
;
3217 intel_dig_port
->saved_port_bits
= I915_READ(DDI_BUF_CTL(port
)) &
3218 (DDI_BUF_PORT_REVERSAL
|
3221 intel_encoder
->type
= INTEL_OUTPUT_UNKNOWN
;
3222 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
3223 intel_encoder
->cloneable
= 0;
3226 if (!intel_ddi_init_dp_connector(intel_dig_port
))
3229 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
3230 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
3233 /* In theory we don't need the encoder->type check, but leave it just in
3234 * case we have some really bad VBTs... */
3235 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
&& init_hdmi
) {
3236 if (!intel_ddi_init_hdmi_connector(intel_dig_port
))
3243 drm_encoder_cleanup(encoder
);
3244 kfree(intel_dig_port
);