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spi/build: Remove SPI_SIRF from compile test
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include "i915_drv.h"
29 #include "intel_drv.h"
30
31 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
32 * them for both DP and FDI transports, allowing those ports to
33 * automatically adapt to HDMI connections as well
34 */
35 static const u32 hsw_ddi_translations_dp[] = {
36 0x00FFFFFF, 0x0006000E, /* DP parameters */
37 0x00D75FFF, 0x0005000A,
38 0x00C30FFF, 0x00040006,
39 0x80AAAFFF, 0x000B0000,
40 0x00FFFFFF, 0x0005000A,
41 0x00D75FFF, 0x000C0004,
42 0x80C30FFF, 0x000B0000,
43 0x00FFFFFF, 0x00040006,
44 0x80D75FFF, 0x000B0000,
45 0x00FFFFFF, 0x00040006 /* HDMI parameters */
46 };
47
48 static const u32 hsw_ddi_translations_fdi[] = {
49 0x00FFFFFF, 0x0007000E, /* FDI parameters */
50 0x00D75FFF, 0x000F000A,
51 0x00C30FFF, 0x00060006,
52 0x00AAAFFF, 0x001E0000,
53 0x00FFFFFF, 0x000F000A,
54 0x00D75FFF, 0x00160004,
55 0x00C30FFF, 0x001E0000,
56 0x00FFFFFF, 0x00060006,
57 0x00D75FFF, 0x001E0000,
58 0x00FFFFFF, 0x00040006 /* HDMI parameters */
59 };
60
61 static enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
62 {
63 struct drm_encoder *encoder = &intel_encoder->base;
64 int type = intel_encoder->type;
65
66 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
67 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
68 struct intel_digital_port *intel_dig_port =
69 enc_to_dig_port(encoder);
70 return intel_dig_port->port;
71
72 } else if (type == INTEL_OUTPUT_ANALOG) {
73 return PORT_E;
74
75 } else {
76 DRM_ERROR("Invalid DDI encoder type %d\n", type);
77 BUG();
78 }
79 }
80
81 /* On Haswell, DDI port buffers must be programmed with correct values
82 * in advance. The buffer values are different for FDI and DP modes,
83 * but the HDMI/DVI fields are shared among those. So we program the DDI
84 * in either FDI or DP modes only, as HDMI connections will work with both
85 * of those
86 */
87 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
88 bool use_fdi_mode)
89 {
90 struct drm_i915_private *dev_priv = dev->dev_private;
91 u32 reg;
92 int i;
93 const u32 *ddi_translations = ((use_fdi_mode) ?
94 hsw_ddi_translations_fdi :
95 hsw_ddi_translations_dp);
96
97 DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
98 port_name(port),
99 use_fdi_mode ? "FDI" : "DP");
100
101 WARN((use_fdi_mode && (port != PORT_E)),
102 "Programming port %c in FDI mode, this probably will not work.\n",
103 port_name(port));
104
105 for (i=0, reg=DDI_BUF_TRANS(port); i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
106 I915_WRITE(reg, ddi_translations[i]);
107 reg += 4;
108 }
109 }
110
111 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
112 * mode and port E for FDI.
113 */
114 void intel_prepare_ddi(struct drm_device *dev)
115 {
116 int port;
117
118 if (!HAS_DDI(dev))
119 return;
120
121 for (port = PORT_A; port < PORT_E; port++)
122 intel_prepare_ddi_buffers(dev, port, false);
123
124 /* DDI E is the suggested one to work in FDI mode, so program is as such
125 * by default. It will have to be re-programmed in case a digital DP
126 * output will be detected on it
127 */
128 intel_prepare_ddi_buffers(dev, PORT_E, true);
129 }
130
131 static const long hsw_ddi_buf_ctl_values[] = {
132 DDI_BUF_EMP_400MV_0DB_HSW,
133 DDI_BUF_EMP_400MV_3_5DB_HSW,
134 DDI_BUF_EMP_400MV_6DB_HSW,
135 DDI_BUF_EMP_400MV_9_5DB_HSW,
136 DDI_BUF_EMP_600MV_0DB_HSW,
137 DDI_BUF_EMP_600MV_3_5DB_HSW,
138 DDI_BUF_EMP_600MV_6DB_HSW,
139 DDI_BUF_EMP_800MV_0DB_HSW,
140 DDI_BUF_EMP_800MV_3_5DB_HSW
141 };
142
143 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
144 enum port port)
145 {
146 uint32_t reg = DDI_BUF_CTL(port);
147 int i;
148
149 for (i = 0; i < 8; i++) {
150 udelay(1);
151 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
152 return;
153 }
154 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
155 }
156
157 /* Starting with Haswell, different DDI ports can work in FDI mode for
158 * connection to the PCH-located connectors. For this, it is necessary to train
159 * both the DDI port and PCH receiver for the desired DDI buffer settings.
160 *
161 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
162 * please note that when FDI mode is active on DDI E, it shares 2 lines with
163 * DDI A (which is used for eDP)
164 */
165
166 void hsw_fdi_link_train(struct drm_crtc *crtc)
167 {
168 struct drm_device *dev = crtc->dev;
169 struct drm_i915_private *dev_priv = dev->dev_private;
170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
171 u32 temp, i, rx_ctl_val;
172
173 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
174 * mode set "sequence for CRT port" document:
175 * - TP1 to TP2 time with the default value
176 * - FDI delay to 90h
177 *
178 * WaFDIAutoLinkSetTimingOverrride:hsw
179 */
180 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
181 FDI_RX_PWRDN_LANE0_VAL(2) |
182 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
183
184 /* Enable the PCH Receiver FDI PLL */
185 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
186 FDI_RX_PLL_ENABLE |
187 FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
188 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
189 POSTING_READ(_FDI_RXA_CTL);
190 udelay(220);
191
192 /* Switch from Rawclk to PCDclk */
193 rx_ctl_val |= FDI_PCDCLK;
194 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
195
196 /* Configure Port Clock Select */
197 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
198
199 /* Start the training iterating through available voltages and emphasis,
200 * testing each value twice. */
201 for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
202 /* Configure DP_TP_CTL with auto-training */
203 I915_WRITE(DP_TP_CTL(PORT_E),
204 DP_TP_CTL_FDI_AUTOTRAIN |
205 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
206 DP_TP_CTL_LINK_TRAIN_PAT1 |
207 DP_TP_CTL_ENABLE);
208
209 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
210 * DDI E does not support port reversal, the functionality is
211 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
212 * port reversal bit */
213 I915_WRITE(DDI_BUF_CTL(PORT_E),
214 DDI_BUF_CTL_ENABLE |
215 ((intel_crtc->config.fdi_lanes - 1) << 1) |
216 hsw_ddi_buf_ctl_values[i / 2]);
217 POSTING_READ(DDI_BUF_CTL(PORT_E));
218
219 udelay(600);
220
221 /* Program PCH FDI Receiver TU */
222 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
223
224 /* Enable PCH FDI Receiver with auto-training */
225 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
226 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
227 POSTING_READ(_FDI_RXA_CTL);
228
229 /* Wait for FDI receiver lane calibration */
230 udelay(30);
231
232 /* Unset FDI_RX_MISC pwrdn lanes */
233 temp = I915_READ(_FDI_RXA_MISC);
234 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
235 I915_WRITE(_FDI_RXA_MISC, temp);
236 POSTING_READ(_FDI_RXA_MISC);
237
238 /* Wait for FDI auto training time */
239 udelay(5);
240
241 temp = I915_READ(DP_TP_STATUS(PORT_E));
242 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
243 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
244
245 /* Enable normal pixel sending for FDI */
246 I915_WRITE(DP_TP_CTL(PORT_E),
247 DP_TP_CTL_FDI_AUTOTRAIN |
248 DP_TP_CTL_LINK_TRAIN_NORMAL |
249 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
250 DP_TP_CTL_ENABLE);
251
252 return;
253 }
254
255 temp = I915_READ(DDI_BUF_CTL(PORT_E));
256 temp &= ~DDI_BUF_CTL_ENABLE;
257 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
258 POSTING_READ(DDI_BUF_CTL(PORT_E));
259
260 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
261 temp = I915_READ(DP_TP_CTL(PORT_E));
262 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
263 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
264 I915_WRITE(DP_TP_CTL(PORT_E), temp);
265 POSTING_READ(DP_TP_CTL(PORT_E));
266
267 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
268
269 rx_ctl_val &= ~FDI_RX_ENABLE;
270 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
271 POSTING_READ(_FDI_RXA_CTL);
272
273 /* Reset FDI_RX_MISC pwrdn lanes */
274 temp = I915_READ(_FDI_RXA_MISC);
275 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
276 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
277 I915_WRITE(_FDI_RXA_MISC, temp);
278 POSTING_READ(_FDI_RXA_MISC);
279 }
280
281 DRM_ERROR("FDI link training failed!\n");
282 }
283
284 static void intel_ddi_mode_set(struct drm_encoder *encoder,
285 struct drm_display_mode *mode,
286 struct drm_display_mode *adjusted_mode)
287 {
288 struct drm_crtc *crtc = encoder->crtc;
289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
290 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
291 int port = intel_ddi_get_encoder_port(intel_encoder);
292 int pipe = intel_crtc->pipe;
293 int type = intel_encoder->type;
294
295 DRM_DEBUG_KMS("Preparing DDI mode on port %c, pipe %c\n",
296 port_name(port), pipe_name(pipe));
297
298 intel_crtc->eld_vld = false;
299 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
300 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
301 struct intel_digital_port *intel_dig_port =
302 enc_to_dig_port(encoder);
303
304 intel_dp->DP = intel_dig_port->port_reversal |
305 DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
306 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
307
308 if (intel_dp->has_audio) {
309 DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
310 pipe_name(intel_crtc->pipe));
311
312 /* write eld */
313 DRM_DEBUG_DRIVER("DP audio: write eld information\n");
314 intel_write_eld(encoder, adjusted_mode);
315 }
316
317 intel_dp_init_link_config(intel_dp);
318
319 } else if (type == INTEL_OUTPUT_HDMI) {
320 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
321
322 if (intel_hdmi->has_audio) {
323 /* Proper support for digital audio needs a new logic
324 * and a new set of registers, so we leave it for future
325 * patch bombing.
326 */
327 DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
328 pipe_name(intel_crtc->pipe));
329
330 /* write eld */
331 DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
332 intel_write_eld(encoder, adjusted_mode);
333 }
334
335 intel_hdmi->set_infoframes(encoder, adjusted_mode);
336 }
337 }
338
339 static struct intel_encoder *
340 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
341 {
342 struct drm_device *dev = crtc->dev;
343 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
344 struct intel_encoder *intel_encoder, *ret = NULL;
345 int num_encoders = 0;
346
347 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
348 ret = intel_encoder;
349 num_encoders++;
350 }
351
352 if (num_encoders != 1)
353 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
354 pipe_name(intel_crtc->pipe));
355
356 BUG_ON(ret == NULL);
357 return ret;
358 }
359
360 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
361 {
362 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
363 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
365 uint32_t val;
366
367 switch (intel_crtc->ddi_pll_sel) {
368 case PORT_CLK_SEL_SPLL:
369 plls->spll_refcount--;
370 if (plls->spll_refcount == 0) {
371 DRM_DEBUG_KMS("Disabling SPLL\n");
372 val = I915_READ(SPLL_CTL);
373 WARN_ON(!(val & SPLL_PLL_ENABLE));
374 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
375 POSTING_READ(SPLL_CTL);
376 }
377 break;
378 case PORT_CLK_SEL_WRPLL1:
379 plls->wrpll1_refcount--;
380 if (plls->wrpll1_refcount == 0) {
381 DRM_DEBUG_KMS("Disabling WRPLL 1\n");
382 val = I915_READ(WRPLL_CTL1);
383 WARN_ON(!(val & WRPLL_PLL_ENABLE));
384 I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
385 POSTING_READ(WRPLL_CTL1);
386 }
387 break;
388 case PORT_CLK_SEL_WRPLL2:
389 plls->wrpll2_refcount--;
390 if (plls->wrpll2_refcount == 0) {
391 DRM_DEBUG_KMS("Disabling WRPLL 2\n");
392 val = I915_READ(WRPLL_CTL2);
393 WARN_ON(!(val & WRPLL_PLL_ENABLE));
394 I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
395 POSTING_READ(WRPLL_CTL2);
396 }
397 break;
398 }
399
400 WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n");
401 WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
402 WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
403
404 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
405 }
406
407 #define LC_FREQ 2700
408 #define LC_FREQ_2K (LC_FREQ * 2000)
409
410 #define P_MIN 2
411 #define P_MAX 64
412 #define P_INC 2
413
414 /* Constraints for PLL good behavior */
415 #define REF_MIN 48
416 #define REF_MAX 400
417 #define VCO_MIN 2400
418 #define VCO_MAX 4800
419
420 #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a))
421
422 struct wrpll_rnp {
423 unsigned p, n2, r2;
424 };
425
426 static unsigned wrpll_get_budget_for_freq(int clock)
427 {
428 unsigned budget;
429
430 switch (clock) {
431 case 25175000:
432 case 25200000:
433 case 27000000:
434 case 27027000:
435 case 37762500:
436 case 37800000:
437 case 40500000:
438 case 40541000:
439 case 54000000:
440 case 54054000:
441 case 59341000:
442 case 59400000:
443 case 72000000:
444 case 74176000:
445 case 74250000:
446 case 81000000:
447 case 81081000:
448 case 89012000:
449 case 89100000:
450 case 108000000:
451 case 108108000:
452 case 111264000:
453 case 111375000:
454 case 148352000:
455 case 148500000:
456 case 162000000:
457 case 162162000:
458 case 222525000:
459 case 222750000:
460 case 296703000:
461 case 297000000:
462 budget = 0;
463 break;
464 case 233500000:
465 case 245250000:
466 case 247750000:
467 case 253250000:
468 case 298000000:
469 budget = 1500;
470 break;
471 case 169128000:
472 case 169500000:
473 case 179500000:
474 case 202000000:
475 budget = 2000;
476 break;
477 case 256250000:
478 case 262500000:
479 case 270000000:
480 case 272500000:
481 case 273750000:
482 case 280750000:
483 case 281250000:
484 case 286000000:
485 case 291750000:
486 budget = 4000;
487 break;
488 case 267250000:
489 case 268500000:
490 budget = 5000;
491 break;
492 default:
493 budget = 1000;
494 break;
495 }
496
497 return budget;
498 }
499
500 static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
501 unsigned r2, unsigned n2, unsigned p,
502 struct wrpll_rnp *best)
503 {
504 uint64_t a, b, c, d, diff, diff_best;
505
506 /* No best (r,n,p) yet */
507 if (best->p == 0) {
508 best->p = p;
509 best->n2 = n2;
510 best->r2 = r2;
511 return;
512 }
513
514 /*
515 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
516 * freq2k.
517 *
518 * delta = 1e6 *
519 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
520 * freq2k;
521 *
522 * and we would like delta <= budget.
523 *
524 * If the discrepancy is above the PPM-based budget, always prefer to
525 * improve upon the previous solution. However, if you're within the
526 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
527 */
528 a = freq2k * budget * p * r2;
529 b = freq2k * budget * best->p * best->r2;
530 diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2));
531 diff_best = ABS_DIFF((freq2k * best->p * best->r2),
532 (LC_FREQ_2K * best->n2));
533 c = 1000000 * diff;
534 d = 1000000 * diff_best;
535
536 if (a < c && b < d) {
537 /* If both are above the budget, pick the closer */
538 if (best->p * best->r2 * diff < p * r2 * diff_best) {
539 best->p = p;
540 best->n2 = n2;
541 best->r2 = r2;
542 }
543 } else if (a >= c && b < d) {
544 /* If A is below the threshold but B is above it? Update. */
545 best->p = p;
546 best->n2 = n2;
547 best->r2 = r2;
548 } else if (a >= c && b >= d) {
549 /* Both are below the limit, so pick the higher n2/(r2*r2) */
550 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
551 best->p = p;
552 best->n2 = n2;
553 best->r2 = r2;
554 }
555 }
556 /* Otherwise a < c && b >= d, do nothing */
557 }
558
559 static void
560 intel_ddi_calculate_wrpll(int clock /* in Hz */,
561 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
562 {
563 uint64_t freq2k;
564 unsigned p, n2, r2;
565 struct wrpll_rnp best = { 0, 0, 0 };
566 unsigned budget;
567
568 freq2k = clock / 100;
569
570 budget = wrpll_get_budget_for_freq(clock);
571
572 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
573 * and directly pass the LC PLL to it. */
574 if (freq2k == 5400000) {
575 *n2_out = 2;
576 *p_out = 1;
577 *r2_out = 2;
578 return;
579 }
580
581 /*
582 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
583 * the WR PLL.
584 *
585 * We want R so that REF_MIN <= Ref <= REF_MAX.
586 * Injecting R2 = 2 * R gives:
587 * REF_MAX * r2 > LC_FREQ * 2 and
588 * REF_MIN * r2 < LC_FREQ * 2
589 *
590 * Which means the desired boundaries for r2 are:
591 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
592 *
593 */
594 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
595 r2 <= LC_FREQ * 2 / REF_MIN;
596 r2++) {
597
598 /*
599 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
600 *
601 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
602 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
603 * VCO_MAX * r2 > n2 * LC_FREQ and
604 * VCO_MIN * r2 < n2 * LC_FREQ)
605 *
606 * Which means the desired boundaries for n2 are:
607 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
608 */
609 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
610 n2 <= VCO_MAX * r2 / LC_FREQ;
611 n2++) {
612
613 for (p = P_MIN; p <= P_MAX; p += P_INC)
614 wrpll_update_rnp(freq2k, budget,
615 r2, n2, p, &best);
616 }
617 }
618
619 *n2_out = best.n2;
620 *p_out = best.p;
621 *r2_out = best.r2;
622
623 DRM_DEBUG_KMS("WRPLL: %dHz refresh rate with p=%d, n2=%d r2=%d\n",
624 clock, *p_out, *n2_out, *r2_out);
625 }
626
627 bool intel_ddi_pll_mode_set(struct drm_crtc *crtc)
628 {
629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
630 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
631 struct drm_encoder *encoder = &intel_encoder->base;
632 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
633 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
634 int type = intel_encoder->type;
635 enum pipe pipe = intel_crtc->pipe;
636 uint32_t reg, val;
637 int clock = intel_crtc->config.port_clock;
638
639 /* TODO: reuse PLLs when possible (compare values) */
640
641 intel_ddi_put_crtc_pll(crtc);
642
643 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
644 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
645
646 switch (intel_dp->link_bw) {
647 case DP_LINK_BW_1_62:
648 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
649 break;
650 case DP_LINK_BW_2_7:
651 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
652 break;
653 case DP_LINK_BW_5_4:
654 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
655 break;
656 default:
657 DRM_ERROR("Link bandwidth %d unsupported\n",
658 intel_dp->link_bw);
659 return false;
660 }
661
662 /* We don't need to turn any PLL on because we'll use LCPLL. */
663 return true;
664
665 } else if (type == INTEL_OUTPUT_HDMI) {
666 unsigned p, n2, r2;
667
668 if (plls->wrpll1_refcount == 0) {
669 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
670 pipe_name(pipe));
671 plls->wrpll1_refcount++;
672 reg = WRPLL_CTL1;
673 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
674 } else if (plls->wrpll2_refcount == 0) {
675 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
676 pipe_name(pipe));
677 plls->wrpll2_refcount++;
678 reg = WRPLL_CTL2;
679 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
680 } else {
681 DRM_ERROR("No WRPLLs available!\n");
682 return false;
683 }
684
685 WARN(I915_READ(reg) & WRPLL_PLL_ENABLE,
686 "WRPLL already enabled\n");
687
688 intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
689
690 val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
691 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
692 WRPLL_DIVIDER_POST(p);
693
694 } else if (type == INTEL_OUTPUT_ANALOG) {
695 if (plls->spll_refcount == 0) {
696 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
697 pipe_name(pipe));
698 plls->spll_refcount++;
699 reg = SPLL_CTL;
700 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
701 } else {
702 DRM_ERROR("SPLL already in use\n");
703 return false;
704 }
705
706 WARN(I915_READ(reg) & SPLL_PLL_ENABLE,
707 "SPLL already enabled\n");
708
709 val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
710
711 } else {
712 WARN(1, "Invalid DDI encoder type %d\n", type);
713 return false;
714 }
715
716 I915_WRITE(reg, val);
717 udelay(20);
718
719 return true;
720 }
721
722 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
723 {
724 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
726 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
727 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
728 int type = intel_encoder->type;
729 uint32_t temp;
730
731 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
732
733 temp = TRANS_MSA_SYNC_CLK;
734 switch (intel_crtc->config.pipe_bpp) {
735 case 18:
736 temp |= TRANS_MSA_6_BPC;
737 break;
738 case 24:
739 temp |= TRANS_MSA_8_BPC;
740 break;
741 case 30:
742 temp |= TRANS_MSA_10_BPC;
743 break;
744 case 36:
745 temp |= TRANS_MSA_12_BPC;
746 break;
747 default:
748 BUG();
749 }
750 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
751 }
752 }
753
754 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
755 {
756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
757 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
758 struct drm_encoder *encoder = &intel_encoder->base;
759 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
760 enum pipe pipe = intel_crtc->pipe;
761 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
762 enum port port = intel_ddi_get_encoder_port(intel_encoder);
763 int type = intel_encoder->type;
764 uint32_t temp;
765
766 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
767 temp = TRANS_DDI_FUNC_ENABLE;
768 temp |= TRANS_DDI_SELECT_PORT(port);
769
770 switch (intel_crtc->config.pipe_bpp) {
771 case 18:
772 temp |= TRANS_DDI_BPC_6;
773 break;
774 case 24:
775 temp |= TRANS_DDI_BPC_8;
776 break;
777 case 30:
778 temp |= TRANS_DDI_BPC_10;
779 break;
780 case 36:
781 temp |= TRANS_DDI_BPC_12;
782 break;
783 default:
784 BUG();
785 }
786
787 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
788 temp |= TRANS_DDI_PVSYNC;
789 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
790 temp |= TRANS_DDI_PHSYNC;
791
792 if (cpu_transcoder == TRANSCODER_EDP) {
793 switch (pipe) {
794 case PIPE_A:
795 /* Can only use the always-on power well for eDP when
796 * not using the panel fitter, and when not using motion
797 * blur mitigation (which we don't support). */
798 if (intel_crtc->config.pch_pfit.size)
799 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
800 else
801 temp |= TRANS_DDI_EDP_INPUT_A_ON;
802 break;
803 case PIPE_B:
804 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
805 break;
806 case PIPE_C:
807 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
808 break;
809 default:
810 BUG();
811 break;
812 }
813 }
814
815 if (type == INTEL_OUTPUT_HDMI) {
816 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
817
818 if (intel_hdmi->has_hdmi_sink)
819 temp |= TRANS_DDI_MODE_SELECT_HDMI;
820 else
821 temp |= TRANS_DDI_MODE_SELECT_DVI;
822
823 } else if (type == INTEL_OUTPUT_ANALOG) {
824 temp |= TRANS_DDI_MODE_SELECT_FDI;
825 temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
826
827 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
828 type == INTEL_OUTPUT_EDP) {
829 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
830
831 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
832
833 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
834 } else {
835 WARN(1, "Invalid encoder type %d for pipe %c\n",
836 intel_encoder->type, pipe_name(pipe));
837 }
838
839 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
840 }
841
842 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
843 enum transcoder cpu_transcoder)
844 {
845 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
846 uint32_t val = I915_READ(reg);
847
848 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
849 val |= TRANS_DDI_PORT_NONE;
850 I915_WRITE(reg, val);
851 }
852
853 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
854 {
855 struct drm_device *dev = intel_connector->base.dev;
856 struct drm_i915_private *dev_priv = dev->dev_private;
857 struct intel_encoder *intel_encoder = intel_connector->encoder;
858 int type = intel_connector->base.connector_type;
859 enum port port = intel_ddi_get_encoder_port(intel_encoder);
860 enum pipe pipe = 0;
861 enum transcoder cpu_transcoder;
862 uint32_t tmp;
863
864 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
865 return false;
866
867 if (port == PORT_A)
868 cpu_transcoder = TRANSCODER_EDP;
869 else
870 cpu_transcoder = (enum transcoder) pipe;
871
872 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
873
874 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
875 case TRANS_DDI_MODE_SELECT_HDMI:
876 case TRANS_DDI_MODE_SELECT_DVI:
877 return (type == DRM_MODE_CONNECTOR_HDMIA);
878
879 case TRANS_DDI_MODE_SELECT_DP_SST:
880 if (type == DRM_MODE_CONNECTOR_eDP)
881 return true;
882 case TRANS_DDI_MODE_SELECT_DP_MST:
883 return (type == DRM_MODE_CONNECTOR_DisplayPort);
884
885 case TRANS_DDI_MODE_SELECT_FDI:
886 return (type == DRM_MODE_CONNECTOR_VGA);
887
888 default:
889 return false;
890 }
891 }
892
893 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
894 enum pipe *pipe)
895 {
896 struct drm_device *dev = encoder->base.dev;
897 struct drm_i915_private *dev_priv = dev->dev_private;
898 enum port port = intel_ddi_get_encoder_port(encoder);
899 u32 tmp;
900 int i;
901
902 tmp = I915_READ(DDI_BUF_CTL(port));
903
904 if (!(tmp & DDI_BUF_CTL_ENABLE))
905 return false;
906
907 if (port == PORT_A) {
908 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
909
910 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
911 case TRANS_DDI_EDP_INPUT_A_ON:
912 case TRANS_DDI_EDP_INPUT_A_ONOFF:
913 *pipe = PIPE_A;
914 break;
915 case TRANS_DDI_EDP_INPUT_B_ONOFF:
916 *pipe = PIPE_B;
917 break;
918 case TRANS_DDI_EDP_INPUT_C_ONOFF:
919 *pipe = PIPE_C;
920 break;
921 }
922
923 return true;
924 } else {
925 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
926 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
927
928 if ((tmp & TRANS_DDI_PORT_MASK)
929 == TRANS_DDI_SELECT_PORT(port)) {
930 *pipe = i;
931 return true;
932 }
933 }
934 }
935
936 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
937
938 return false;
939 }
940
941 static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
942 enum pipe pipe)
943 {
944 uint32_t temp, ret;
945 enum port port = I915_MAX_PORTS;
946 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
947 pipe);
948 int i;
949
950 if (cpu_transcoder == TRANSCODER_EDP) {
951 port = PORT_A;
952 } else {
953 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
954 temp &= TRANS_DDI_PORT_MASK;
955
956 for (i = PORT_B; i <= PORT_E; i++)
957 if (temp == TRANS_DDI_SELECT_PORT(i))
958 port = i;
959 }
960
961 if (port == I915_MAX_PORTS) {
962 WARN(1, "Pipe %c enabled on an unknown port\n",
963 pipe_name(pipe));
964 ret = PORT_CLK_SEL_NONE;
965 } else {
966 ret = I915_READ(PORT_CLK_SEL(port));
967 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
968 "0x%08x\n", pipe_name(pipe), port_name(port),
969 ret);
970 }
971
972 return ret;
973 }
974
975 void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
976 {
977 struct drm_i915_private *dev_priv = dev->dev_private;
978 enum pipe pipe;
979 struct intel_crtc *intel_crtc;
980
981 for_each_pipe(pipe) {
982 intel_crtc =
983 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
984
985 if (!intel_crtc->active)
986 continue;
987
988 intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
989 pipe);
990
991 switch (intel_crtc->ddi_pll_sel) {
992 case PORT_CLK_SEL_SPLL:
993 dev_priv->ddi_plls.spll_refcount++;
994 break;
995 case PORT_CLK_SEL_WRPLL1:
996 dev_priv->ddi_plls.wrpll1_refcount++;
997 break;
998 case PORT_CLK_SEL_WRPLL2:
999 dev_priv->ddi_plls.wrpll2_refcount++;
1000 break;
1001 }
1002 }
1003 }
1004
1005 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1006 {
1007 struct drm_crtc *crtc = &intel_crtc->base;
1008 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1009 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1010 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1011 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1012
1013 if (cpu_transcoder != TRANSCODER_EDP)
1014 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1015 TRANS_CLK_SEL_PORT(port));
1016 }
1017
1018 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1019 {
1020 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1021 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1022
1023 if (cpu_transcoder != TRANSCODER_EDP)
1024 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1025 TRANS_CLK_SEL_DISABLED);
1026 }
1027
1028 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1029 {
1030 struct drm_encoder *encoder = &intel_encoder->base;
1031 struct drm_crtc *crtc = encoder->crtc;
1032 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1034 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1035 int type = intel_encoder->type;
1036
1037 if (type == INTEL_OUTPUT_EDP) {
1038 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1039 ironlake_edp_panel_vdd_on(intel_dp);
1040 ironlake_edp_panel_on(intel_dp);
1041 ironlake_edp_panel_vdd_off(intel_dp, true);
1042 }
1043
1044 WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
1045 I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
1046
1047 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1048 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1049
1050 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1051 intel_dp_start_link_train(intel_dp);
1052 intel_dp_complete_link_train(intel_dp);
1053 if (port != PORT_A)
1054 intel_dp_stop_link_train(intel_dp);
1055 }
1056 }
1057
1058 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1059 {
1060 struct drm_encoder *encoder = &intel_encoder->base;
1061 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1062 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1063 int type = intel_encoder->type;
1064 uint32_t val;
1065 bool wait = false;
1066
1067 val = I915_READ(DDI_BUF_CTL(port));
1068 if (val & DDI_BUF_CTL_ENABLE) {
1069 val &= ~DDI_BUF_CTL_ENABLE;
1070 I915_WRITE(DDI_BUF_CTL(port), val);
1071 wait = true;
1072 }
1073
1074 val = I915_READ(DP_TP_CTL(port));
1075 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1076 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1077 I915_WRITE(DP_TP_CTL(port), val);
1078
1079 if (wait)
1080 intel_wait_ddi_buf_idle(dev_priv, port);
1081
1082 if (type == INTEL_OUTPUT_EDP) {
1083 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1084 ironlake_edp_panel_vdd_on(intel_dp);
1085 ironlake_edp_panel_off(intel_dp);
1086 }
1087
1088 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1089 }
1090
1091 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1092 {
1093 struct drm_encoder *encoder = &intel_encoder->base;
1094 struct drm_crtc *crtc = encoder->crtc;
1095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1096 int pipe = intel_crtc->pipe;
1097 struct drm_device *dev = encoder->dev;
1098 struct drm_i915_private *dev_priv = dev->dev_private;
1099 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1100 int type = intel_encoder->type;
1101 uint32_t tmp;
1102
1103 if (type == INTEL_OUTPUT_HDMI) {
1104 struct intel_digital_port *intel_dig_port =
1105 enc_to_dig_port(encoder);
1106
1107 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1108 * are ignored so nothing special needs to be done besides
1109 * enabling the port.
1110 */
1111 I915_WRITE(DDI_BUF_CTL(port),
1112 intel_dig_port->port_reversal | DDI_BUF_CTL_ENABLE);
1113 } else if (type == INTEL_OUTPUT_EDP) {
1114 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1115
1116 if (port == PORT_A)
1117 intel_dp_stop_link_train(intel_dp);
1118
1119 ironlake_edp_backlight_on(intel_dp);
1120 }
1121
1122 if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
1123 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1124 tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1125 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1126 }
1127 }
1128
1129 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1130 {
1131 struct drm_encoder *encoder = &intel_encoder->base;
1132 struct drm_crtc *crtc = encoder->crtc;
1133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1134 int pipe = intel_crtc->pipe;
1135 int type = intel_encoder->type;
1136 struct drm_device *dev = encoder->dev;
1137 struct drm_i915_private *dev_priv = dev->dev_private;
1138 uint32_t tmp;
1139
1140 if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
1141 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1142 tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) <<
1143 (pipe * 4));
1144 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1145 }
1146
1147 if (type == INTEL_OUTPUT_EDP) {
1148 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1149
1150 ironlake_edp_backlight_off(intel_dp);
1151 }
1152 }
1153
1154 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1155 {
1156 if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
1157 return 450000;
1158 else if ((I915_READ(LCPLL_CTL) & LCPLL_CLK_FREQ_MASK) ==
1159 LCPLL_CLK_FREQ_450)
1160 return 450000;
1161 else if (IS_ULT(dev_priv->dev))
1162 return 337500;
1163 else
1164 return 540000;
1165 }
1166
1167 void intel_ddi_pll_init(struct drm_device *dev)
1168 {
1169 struct drm_i915_private *dev_priv = dev->dev_private;
1170 uint32_t val = I915_READ(LCPLL_CTL);
1171
1172 /* The LCPLL register should be turned on by the BIOS. For now let's
1173 * just check its state and print errors in case something is wrong.
1174 * Don't even try to turn it on.
1175 */
1176
1177 DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1178 intel_ddi_get_cdclk_freq(dev_priv));
1179
1180 if (val & LCPLL_CD_SOURCE_FCLK)
1181 DRM_ERROR("CDCLK source is not LCPLL\n");
1182
1183 if (val & LCPLL_PLL_DISABLE)
1184 DRM_ERROR("LCPLL is disabled\n");
1185 }
1186
1187 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1188 {
1189 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1190 struct intel_dp *intel_dp = &intel_dig_port->dp;
1191 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1192 enum port port = intel_dig_port->port;
1193 uint32_t val;
1194 bool wait = false;
1195
1196 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1197 val = I915_READ(DDI_BUF_CTL(port));
1198 if (val & DDI_BUF_CTL_ENABLE) {
1199 val &= ~DDI_BUF_CTL_ENABLE;
1200 I915_WRITE(DDI_BUF_CTL(port), val);
1201 wait = true;
1202 }
1203
1204 val = I915_READ(DP_TP_CTL(port));
1205 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1206 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1207 I915_WRITE(DP_TP_CTL(port), val);
1208 POSTING_READ(DP_TP_CTL(port));
1209
1210 if (wait)
1211 intel_wait_ddi_buf_idle(dev_priv, port);
1212 }
1213
1214 val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
1215 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1216 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
1217 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1218 I915_WRITE(DP_TP_CTL(port), val);
1219 POSTING_READ(DP_TP_CTL(port));
1220
1221 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1222 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1223 POSTING_READ(DDI_BUF_CTL(port));
1224
1225 udelay(600);
1226 }
1227
1228 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1229 {
1230 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1231 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1232 uint32_t val;
1233
1234 intel_ddi_post_disable(intel_encoder);
1235
1236 val = I915_READ(_FDI_RXA_CTL);
1237 val &= ~FDI_RX_ENABLE;
1238 I915_WRITE(_FDI_RXA_CTL, val);
1239
1240 val = I915_READ(_FDI_RXA_MISC);
1241 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1242 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1243 I915_WRITE(_FDI_RXA_MISC, val);
1244
1245 val = I915_READ(_FDI_RXA_CTL);
1246 val &= ~FDI_PCDCLK;
1247 I915_WRITE(_FDI_RXA_CTL, val);
1248
1249 val = I915_READ(_FDI_RXA_CTL);
1250 val &= ~FDI_RX_PLL_ENABLE;
1251 I915_WRITE(_FDI_RXA_CTL, val);
1252 }
1253
1254 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1255 {
1256 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
1257 int type = intel_encoder->type;
1258
1259 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP)
1260 intel_dp_check_link_status(intel_dp);
1261 }
1262
1263 static void intel_ddi_get_config(struct intel_encoder *encoder,
1264 struct intel_crtc_config *pipe_config)
1265 {
1266 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1267 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1268 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1269 u32 temp, flags = 0;
1270
1271 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1272 if (temp & TRANS_DDI_PHSYNC)
1273 flags |= DRM_MODE_FLAG_PHSYNC;
1274 else
1275 flags |= DRM_MODE_FLAG_NHSYNC;
1276 if (temp & TRANS_DDI_PVSYNC)
1277 flags |= DRM_MODE_FLAG_PVSYNC;
1278 else
1279 flags |= DRM_MODE_FLAG_NVSYNC;
1280
1281 pipe_config->adjusted_mode.flags |= flags;
1282 }
1283
1284 static void intel_ddi_destroy(struct drm_encoder *encoder)
1285 {
1286 /* HDMI has nothing special to destroy, so we can go with this. */
1287 intel_dp_encoder_destroy(encoder);
1288 }
1289
1290 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
1291 struct intel_crtc_config *pipe_config)
1292 {
1293 int type = encoder->type;
1294 int port = intel_ddi_get_encoder_port(encoder);
1295
1296 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
1297
1298 if (port == PORT_A)
1299 pipe_config->cpu_transcoder = TRANSCODER_EDP;
1300
1301 if (type == INTEL_OUTPUT_HDMI)
1302 return intel_hdmi_compute_config(encoder, pipe_config);
1303 else
1304 return intel_dp_compute_config(encoder, pipe_config);
1305 }
1306
1307 static const struct drm_encoder_funcs intel_ddi_funcs = {
1308 .destroy = intel_ddi_destroy,
1309 };
1310
1311 static const struct drm_encoder_helper_funcs intel_ddi_helper_funcs = {
1312 .mode_set = intel_ddi_mode_set,
1313 };
1314
1315 void intel_ddi_init(struct drm_device *dev, enum port port)
1316 {
1317 struct drm_i915_private *dev_priv = dev->dev_private;
1318 struct intel_digital_port *intel_dig_port;
1319 struct intel_encoder *intel_encoder;
1320 struct drm_encoder *encoder;
1321 struct intel_connector *hdmi_connector = NULL;
1322 struct intel_connector *dp_connector = NULL;
1323
1324 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
1325 if (!intel_dig_port)
1326 return;
1327
1328 dp_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1329 if (!dp_connector) {
1330 kfree(intel_dig_port);
1331 return;
1332 }
1333
1334 intel_encoder = &intel_dig_port->base;
1335 encoder = &intel_encoder->base;
1336
1337 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1338 DRM_MODE_ENCODER_TMDS);
1339 drm_encoder_helper_add(encoder, &intel_ddi_helper_funcs);
1340
1341 intel_encoder->compute_config = intel_ddi_compute_config;
1342 intel_encoder->enable = intel_enable_ddi;
1343 intel_encoder->pre_enable = intel_ddi_pre_enable;
1344 intel_encoder->disable = intel_disable_ddi;
1345 intel_encoder->post_disable = intel_ddi_post_disable;
1346 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1347 intel_encoder->get_config = intel_ddi_get_config;
1348
1349 intel_dig_port->port = port;
1350 intel_dig_port->port_reversal = I915_READ(DDI_BUF_CTL(port)) &
1351 DDI_BUF_PORT_REVERSAL;
1352 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1353
1354 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1355 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1356 intel_encoder->cloneable = false;
1357 intel_encoder->hot_plug = intel_ddi_hot_plug;
1358
1359 if (!intel_dp_init_connector(intel_dig_port, dp_connector)) {
1360 drm_encoder_cleanup(encoder);
1361 kfree(intel_dig_port);
1362 kfree(dp_connector);
1363 return;
1364 }
1365
1366 if (intel_encoder->type != INTEL_OUTPUT_EDP) {
1367 hdmi_connector = kzalloc(sizeof(struct intel_connector),
1368 GFP_KERNEL);
1369 if (!hdmi_connector) {
1370 return;
1371 }
1372
1373 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
1374 intel_hdmi_init_connector(intel_dig_port, hdmi_connector);
1375 }
1376 }
Linux kernel - Deliverables
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