2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 struct ddi_buf_trans
{
32 u32 trans1
; /* balance leg enable, de-emph level */
33 u32 trans2
; /* vref sel, vswing */
36 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
37 * them for both DP and FDI transports, allowing those ports to
38 * automatically adapt to HDMI connections as well
40 static const struct ddi_buf_trans hsw_ddi_translations_dp
[] = {
41 { 0x00FFFFFF, 0x0006000E },
42 { 0x00D75FFF, 0x0005000A },
43 { 0x00C30FFF, 0x00040006 },
44 { 0x80AAAFFF, 0x000B0000 },
45 { 0x00FFFFFF, 0x0005000A },
46 { 0x00D75FFF, 0x000C0004 },
47 { 0x80C30FFF, 0x000B0000 },
48 { 0x00FFFFFF, 0x00040006 },
49 { 0x80D75FFF, 0x000B0000 },
52 static const struct ddi_buf_trans hsw_ddi_translations_fdi
[] = {
53 { 0x00FFFFFF, 0x0007000E },
54 { 0x00D75FFF, 0x000F000A },
55 { 0x00C30FFF, 0x00060006 },
56 { 0x00AAAFFF, 0x001E0000 },
57 { 0x00FFFFFF, 0x000F000A },
58 { 0x00D75FFF, 0x00160004 },
59 { 0x00C30FFF, 0x001E0000 },
60 { 0x00FFFFFF, 0x00060006 },
61 { 0x00D75FFF, 0x001E0000 },
64 static const struct ddi_buf_trans hsw_ddi_translations_hdmi
[] = {
65 /* Idx NT mV d T mV d db */
66 { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */
67 { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */
68 { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */
69 { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */
70 { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */
71 { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */
72 { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */
73 { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */
74 { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */
75 { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */
76 { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */
77 { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */
80 static const struct ddi_buf_trans bdw_ddi_translations_edp
[] = {
81 { 0x00FFFFFF, 0x00000012 },
82 { 0x00EBAFFF, 0x00020011 },
83 { 0x00C71FFF, 0x0006000F },
84 { 0x00AAAFFF, 0x000E000A },
85 { 0x00FFFFFF, 0x00020011 },
86 { 0x00DB6FFF, 0x0005000F },
87 { 0x00BEEFFF, 0x000A000C },
88 { 0x00FFFFFF, 0x0005000F },
89 { 0x00DB6FFF, 0x000A000C },
92 static const struct ddi_buf_trans bdw_ddi_translations_dp
[] = {
93 { 0x00FFFFFF, 0x0007000E },
94 { 0x00D75FFF, 0x000E000A },
95 { 0x00BEFFFF, 0x00140006 },
96 { 0x80B2CFFF, 0x001B0002 },
97 { 0x00FFFFFF, 0x000E000A },
98 { 0x00DB6FFF, 0x00160005 },
99 { 0x80C71FFF, 0x001A0002 },
100 { 0x00F7DFFF, 0x00180004 },
101 { 0x80D75FFF, 0x001B0002 },
104 static const struct ddi_buf_trans bdw_ddi_translations_fdi
[] = {
105 { 0x00FFFFFF, 0x0001000E },
106 { 0x00D75FFF, 0x0004000A },
107 { 0x00C30FFF, 0x00070006 },
108 { 0x00AAAFFF, 0x000C0000 },
109 { 0x00FFFFFF, 0x0004000A },
110 { 0x00D75FFF, 0x00090004 },
111 { 0x00C30FFF, 0x000C0000 },
112 { 0x00FFFFFF, 0x00070006 },
113 { 0x00D75FFF, 0x000C0000 },
116 static const struct ddi_buf_trans bdw_ddi_translations_hdmi
[] = {
117 /* Idx NT mV d T mV df db */
118 { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */
119 { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */
120 { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */
121 { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */
122 { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */
123 { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */
124 { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */
125 { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */
126 { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */
127 { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */
130 static const struct ddi_buf_trans skl_ddi_translations_dp
[] = {
131 { 0x00000018, 0x000000a0 },
132 { 0x00004014, 0x00000098 },
133 { 0x00006012, 0x00000088 },
134 { 0x00008010, 0x00000080 },
135 { 0x00000018, 0x00000098 },
136 { 0x00004014, 0x00000088 },
137 { 0x00006012, 0x00000080 },
138 { 0x00000018, 0x00000088 },
139 { 0x00004014, 0x00000080 },
142 static const struct ddi_buf_trans skl_ddi_translations_hdmi
[] = {
143 /* Idx NT mV T mV db */
144 { 0x00000018, 0x000000a0 }, /* 0: 400 400 0 */
145 { 0x00004014, 0x00000098 }, /* 1: 400 600 3.5 */
146 { 0x00006012, 0x00000088 }, /* 2: 400 800 6 */
147 { 0x00000018, 0x0000003c }, /* 3: 450 450 0 */
148 { 0x00000018, 0x00000098 }, /* 4: 600 600 0 */
149 { 0x00003015, 0x00000088 }, /* 5: 600 800 2.5 */
150 { 0x00005013, 0x00000080 }, /* 6: 600 1000 4.5 */
151 { 0x00000018, 0x00000088 }, /* 7: 800 800 0 */
152 { 0x00000096, 0x00000080 }, /* 8: 800 1000 2 */
153 { 0x00000018, 0x00000080 }, /* 9: 1200 1200 0 */
156 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
)
158 struct drm_encoder
*encoder
= &intel_encoder
->base
;
159 int type
= intel_encoder
->type
;
161 if (type
== INTEL_OUTPUT_DP_MST
) {
162 struct intel_digital_port
*intel_dig_port
= enc_to_mst(encoder
)->primary
;
163 return intel_dig_port
->port
;
164 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
||
165 type
== INTEL_OUTPUT_HDMI
|| type
== INTEL_OUTPUT_UNKNOWN
) {
166 struct intel_digital_port
*intel_dig_port
=
167 enc_to_dig_port(encoder
);
168 return intel_dig_port
->port
;
170 } else if (type
== INTEL_OUTPUT_ANALOG
) {
174 DRM_ERROR("Invalid DDI encoder type %d\n", type
);
180 * Starting with Haswell, DDI port buffers must be programmed with correct
181 * values in advance. The buffer values are different for FDI and DP modes,
182 * but the HDMI/DVI fields are shared among those. So we program the DDI
183 * in either FDI or DP modes only, as HDMI connections will work with both
186 static void intel_prepare_ddi_buffers(struct drm_device
*dev
, enum port port
)
188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
190 int i
, n_hdmi_entries
, hdmi_800mV_0dB
;
191 int hdmi_level
= dev_priv
->vbt
.ddi_port_info
[port
].hdmi_level_shift
;
192 const struct ddi_buf_trans
*ddi_translations_fdi
;
193 const struct ddi_buf_trans
*ddi_translations_dp
;
194 const struct ddi_buf_trans
*ddi_translations_edp
;
195 const struct ddi_buf_trans
*ddi_translations_hdmi
;
196 const struct ddi_buf_trans
*ddi_translations
;
198 if (IS_SKYLAKE(dev
)) {
199 ddi_translations_fdi
= NULL
;
200 ddi_translations_dp
= skl_ddi_translations_dp
;
201 ddi_translations_edp
= skl_ddi_translations_dp
;
202 ddi_translations_hdmi
= skl_ddi_translations_hdmi
;
203 n_hdmi_entries
= ARRAY_SIZE(skl_ddi_translations_hdmi
);
205 } else if (IS_BROADWELL(dev
)) {
206 ddi_translations_fdi
= bdw_ddi_translations_fdi
;
207 ddi_translations_dp
= bdw_ddi_translations_dp
;
208 ddi_translations_edp
= bdw_ddi_translations_edp
;
209 ddi_translations_hdmi
= bdw_ddi_translations_hdmi
;
210 n_hdmi_entries
= ARRAY_SIZE(bdw_ddi_translations_hdmi
);
212 } else if (IS_HASWELL(dev
)) {
213 ddi_translations_fdi
= hsw_ddi_translations_fdi
;
214 ddi_translations_dp
= hsw_ddi_translations_dp
;
215 ddi_translations_edp
= hsw_ddi_translations_dp
;
216 ddi_translations_hdmi
= hsw_ddi_translations_hdmi
;
217 n_hdmi_entries
= ARRAY_SIZE(hsw_ddi_translations_hdmi
);
220 WARN(1, "ddi translation table missing\n");
221 ddi_translations_edp
= bdw_ddi_translations_dp
;
222 ddi_translations_fdi
= bdw_ddi_translations_fdi
;
223 ddi_translations_dp
= bdw_ddi_translations_dp
;
224 ddi_translations_hdmi
= bdw_ddi_translations_hdmi
;
225 n_hdmi_entries
= ARRAY_SIZE(bdw_ddi_translations_hdmi
);
231 ddi_translations
= ddi_translations_edp
;
235 ddi_translations
= ddi_translations_dp
;
238 if (intel_dp_is_edp(dev
, PORT_D
))
239 ddi_translations
= ddi_translations_edp
;
241 ddi_translations
= ddi_translations_dp
;
244 if (ddi_translations_fdi
)
245 ddi_translations
= ddi_translations_fdi
;
247 ddi_translations
= ddi_translations_dp
;
253 for (i
= 0, reg
= DDI_BUF_TRANS(port
);
254 i
< ARRAY_SIZE(hsw_ddi_translations_fdi
); i
++) {
255 I915_WRITE(reg
, ddi_translations
[i
].trans1
);
257 I915_WRITE(reg
, ddi_translations
[i
].trans2
);
261 /* Choose a good default if VBT is badly populated */
262 if (hdmi_level
== HDMI_LEVEL_SHIFT_UNKNOWN
||
263 hdmi_level
>= n_hdmi_entries
)
264 hdmi_level
= hdmi_800mV_0dB
;
266 /* Entry 9 is for HDMI: */
267 I915_WRITE(reg
, ddi_translations_hdmi
[hdmi_level
].trans1
);
269 I915_WRITE(reg
, ddi_translations_hdmi
[hdmi_level
].trans2
);
273 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
274 * mode and port E for FDI.
276 void intel_prepare_ddi(struct drm_device
*dev
)
283 for (port
= PORT_A
; port
<= PORT_E
; port
++)
284 intel_prepare_ddi_buffers(dev
, port
);
287 static void intel_wait_ddi_buf_idle(struct drm_i915_private
*dev_priv
,
290 uint32_t reg
= DDI_BUF_CTL(port
);
293 for (i
= 0; i
< 8; i
++) {
295 if (I915_READ(reg
) & DDI_BUF_IS_IDLE
)
298 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port
));
301 /* Starting with Haswell, different DDI ports can work in FDI mode for
302 * connection to the PCH-located connectors. For this, it is necessary to train
303 * both the DDI port and PCH receiver for the desired DDI buffer settings.
305 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
306 * please note that when FDI mode is active on DDI E, it shares 2 lines with
307 * DDI A (which is used for eDP)
310 void hsw_fdi_link_train(struct drm_crtc
*crtc
)
312 struct drm_device
*dev
= crtc
->dev
;
313 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
314 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
315 u32 temp
, i
, rx_ctl_val
;
317 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
318 * mode set "sequence for CRT port" document:
319 * - TP1 to TP2 time with the default value
322 * WaFDIAutoLinkSetTimingOverrride:hsw
324 I915_WRITE(_FDI_RXA_MISC
, FDI_RX_PWRDN_LANE1_VAL(2) |
325 FDI_RX_PWRDN_LANE0_VAL(2) |
326 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
328 /* Enable the PCH Receiver FDI PLL */
329 rx_ctl_val
= dev_priv
->fdi_rx_config
| FDI_RX_ENHANCE_FRAME_ENABLE
|
331 FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
332 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
333 POSTING_READ(_FDI_RXA_CTL
);
336 /* Switch from Rawclk to PCDclk */
337 rx_ctl_val
|= FDI_PCDCLK
;
338 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
340 /* Configure Port Clock Select */
341 I915_WRITE(PORT_CLK_SEL(PORT_E
), intel_crtc
->config
.ddi_pll_sel
);
342 WARN_ON(intel_crtc
->config
.ddi_pll_sel
!= PORT_CLK_SEL_SPLL
);
344 /* Start the training iterating through available voltages and emphasis,
345 * testing each value twice. */
346 for (i
= 0; i
< ARRAY_SIZE(hsw_ddi_translations_fdi
) * 2; i
++) {
347 /* Configure DP_TP_CTL with auto-training */
348 I915_WRITE(DP_TP_CTL(PORT_E
),
349 DP_TP_CTL_FDI_AUTOTRAIN
|
350 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
351 DP_TP_CTL_LINK_TRAIN_PAT1
|
354 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
355 * DDI E does not support port reversal, the functionality is
356 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
357 * port reversal bit */
358 I915_WRITE(DDI_BUF_CTL(PORT_E
),
360 ((intel_crtc
->config
.fdi_lanes
- 1) << 1) |
361 DDI_BUF_TRANS_SELECT(i
/ 2));
362 POSTING_READ(DDI_BUF_CTL(PORT_E
));
366 /* Program PCH FDI Receiver TU */
367 I915_WRITE(_FDI_RXA_TUSIZE1
, TU_SIZE(64));
369 /* Enable PCH FDI Receiver with auto-training */
370 rx_ctl_val
|= FDI_RX_ENABLE
| FDI_LINK_TRAIN_AUTO
;
371 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
372 POSTING_READ(_FDI_RXA_CTL
);
374 /* Wait for FDI receiver lane calibration */
377 /* Unset FDI_RX_MISC pwrdn lanes */
378 temp
= I915_READ(_FDI_RXA_MISC
);
379 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
380 I915_WRITE(_FDI_RXA_MISC
, temp
);
381 POSTING_READ(_FDI_RXA_MISC
);
383 /* Wait for FDI auto training time */
386 temp
= I915_READ(DP_TP_STATUS(PORT_E
));
387 if (temp
& DP_TP_STATUS_AUTOTRAIN_DONE
) {
388 DRM_DEBUG_KMS("FDI link training done on step %d\n", i
);
390 /* Enable normal pixel sending for FDI */
391 I915_WRITE(DP_TP_CTL(PORT_E
),
392 DP_TP_CTL_FDI_AUTOTRAIN
|
393 DP_TP_CTL_LINK_TRAIN_NORMAL
|
394 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
400 temp
= I915_READ(DDI_BUF_CTL(PORT_E
));
401 temp
&= ~DDI_BUF_CTL_ENABLE
;
402 I915_WRITE(DDI_BUF_CTL(PORT_E
), temp
);
403 POSTING_READ(DDI_BUF_CTL(PORT_E
));
405 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
406 temp
= I915_READ(DP_TP_CTL(PORT_E
));
407 temp
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
408 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
409 I915_WRITE(DP_TP_CTL(PORT_E
), temp
);
410 POSTING_READ(DP_TP_CTL(PORT_E
));
412 intel_wait_ddi_buf_idle(dev_priv
, PORT_E
);
414 rx_ctl_val
&= ~FDI_RX_ENABLE
;
415 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
416 POSTING_READ(_FDI_RXA_CTL
);
418 /* Reset FDI_RX_MISC pwrdn lanes */
419 temp
= I915_READ(_FDI_RXA_MISC
);
420 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
421 temp
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
422 I915_WRITE(_FDI_RXA_MISC
, temp
);
423 POSTING_READ(_FDI_RXA_MISC
);
426 DRM_ERROR("FDI link training failed!\n");
429 void intel_ddi_init_dp_buf_reg(struct intel_encoder
*encoder
)
431 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
432 struct intel_digital_port
*intel_dig_port
=
433 enc_to_dig_port(&encoder
->base
);
435 intel_dp
->DP
= intel_dig_port
->saved_port_bits
|
436 DDI_BUF_CTL_ENABLE
| DDI_BUF_TRANS_SELECT(0);
437 intel_dp
->DP
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
441 static struct intel_encoder
*
442 intel_ddi_get_crtc_encoder(struct drm_crtc
*crtc
)
444 struct drm_device
*dev
= crtc
->dev
;
445 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
446 struct intel_encoder
*intel_encoder
, *ret
= NULL
;
447 int num_encoders
= 0;
449 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
454 if (num_encoders
!= 1)
455 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders
,
456 pipe_name(intel_crtc
->pipe
));
463 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
469 /* Constraints for PLL good behavior */
475 #define abs_diff(a, b) ({ \
476 typeof(a) __a = (a); \
477 typeof(b) __b = (b); \
478 (void) (&__a == &__b); \
479 __a > __b ? (__a - __b) : (__b - __a); })
485 static unsigned wrpll_get_budget_for_freq(int clock
)
559 static void wrpll_update_rnp(uint64_t freq2k
, unsigned budget
,
560 unsigned r2
, unsigned n2
, unsigned p
,
561 struct wrpll_rnp
*best
)
563 uint64_t a
, b
, c
, d
, diff
, diff_best
;
565 /* No best (r,n,p) yet */
574 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
578 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
581 * and we would like delta <= budget.
583 * If the discrepancy is above the PPM-based budget, always prefer to
584 * improve upon the previous solution. However, if you're within the
585 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
587 a
= freq2k
* budget
* p
* r2
;
588 b
= freq2k
* budget
* best
->p
* best
->r2
;
589 diff
= abs_diff(freq2k
* p
* r2
, LC_FREQ_2K
* n2
);
590 diff_best
= abs_diff(freq2k
* best
->p
* best
->r2
,
591 LC_FREQ_2K
* best
->n2
);
593 d
= 1000000 * diff_best
;
595 if (a
< c
&& b
< d
) {
596 /* If both are above the budget, pick the closer */
597 if (best
->p
* best
->r2
* diff
< p
* r2
* diff_best
) {
602 } else if (a
>= c
&& b
< d
) {
603 /* If A is below the threshold but B is above it? Update. */
607 } else if (a
>= c
&& b
>= d
) {
608 /* Both are below the limit, so pick the higher n2/(r2*r2) */
609 if (n2
* best
->r2
* best
->r2
> best
->n2
* r2
* r2
) {
615 /* Otherwise a < c && b >= d, do nothing */
618 static int intel_ddi_calc_wrpll_link(struct drm_i915_private
*dev_priv
,
621 int refclk
= LC_FREQ
;
625 wrpll
= I915_READ(reg
);
626 switch (wrpll
& WRPLL_PLL_REF_MASK
) {
628 case WRPLL_PLL_NON_SSC
:
630 * We could calculate spread here, but our checking
631 * code only cares about 5% accuracy, and spread is a max of
636 case WRPLL_PLL_LCPLL
:
640 WARN(1, "bad wrpll refclk\n");
644 r
= wrpll
& WRPLL_DIVIDER_REF_MASK
;
645 p
= (wrpll
& WRPLL_DIVIDER_POST_MASK
) >> WRPLL_DIVIDER_POST_SHIFT
;
646 n
= (wrpll
& WRPLL_DIVIDER_FB_MASK
) >> WRPLL_DIVIDER_FB_SHIFT
;
648 /* Convert to KHz, p & r have a fixed point portion */
649 return (refclk
* n
* 100) / (p
* r
);
652 static void hsw_ddi_clock_get(struct intel_encoder
*encoder
,
653 struct intel_crtc_config
*pipe_config
)
655 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
659 val
= pipe_config
->ddi_pll_sel
;
660 switch (val
& PORT_CLK_SEL_MASK
) {
661 case PORT_CLK_SEL_LCPLL_810
:
664 case PORT_CLK_SEL_LCPLL_1350
:
667 case PORT_CLK_SEL_LCPLL_2700
:
670 case PORT_CLK_SEL_WRPLL1
:
671 link_clock
= intel_ddi_calc_wrpll_link(dev_priv
, WRPLL_CTL1
);
673 case PORT_CLK_SEL_WRPLL2
:
674 link_clock
= intel_ddi_calc_wrpll_link(dev_priv
, WRPLL_CTL2
);
676 case PORT_CLK_SEL_SPLL
:
677 pll
= I915_READ(SPLL_CTL
) & SPLL_PLL_FREQ_MASK
;
678 if (pll
== SPLL_PLL_FREQ_810MHz
)
680 else if (pll
== SPLL_PLL_FREQ_1350MHz
)
682 else if (pll
== SPLL_PLL_FREQ_2700MHz
)
685 WARN(1, "bad spll freq\n");
690 WARN(1, "bad port clock sel\n");
694 pipe_config
->port_clock
= link_clock
* 2;
696 if (pipe_config
->has_pch_encoder
)
697 pipe_config
->adjusted_mode
.crtc_clock
=
698 intel_dotclock_calculate(pipe_config
->port_clock
,
699 &pipe_config
->fdi_m_n
);
700 else if (pipe_config
->has_dp_encoder
)
701 pipe_config
->adjusted_mode
.crtc_clock
=
702 intel_dotclock_calculate(pipe_config
->port_clock
,
703 &pipe_config
->dp_m_n
);
705 pipe_config
->adjusted_mode
.crtc_clock
= pipe_config
->port_clock
;
708 void intel_ddi_clock_get(struct intel_encoder
*encoder
,
709 struct intel_crtc_config
*pipe_config
)
711 hsw_ddi_clock_get(encoder
, pipe_config
);
715 hsw_ddi_calculate_wrpll(int clock
/* in Hz */,
716 unsigned *r2_out
, unsigned *n2_out
, unsigned *p_out
)
720 struct wrpll_rnp best
= { 0, 0, 0 };
723 freq2k
= clock
/ 100;
725 budget
= wrpll_get_budget_for_freq(clock
);
727 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
728 * and directly pass the LC PLL to it. */
729 if (freq2k
== 5400000) {
737 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
740 * We want R so that REF_MIN <= Ref <= REF_MAX.
741 * Injecting R2 = 2 * R gives:
742 * REF_MAX * r2 > LC_FREQ * 2 and
743 * REF_MIN * r2 < LC_FREQ * 2
745 * Which means the desired boundaries for r2 are:
746 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
749 for (r2
= LC_FREQ
* 2 / REF_MAX
+ 1;
750 r2
<= LC_FREQ
* 2 / REF_MIN
;
754 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
756 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
757 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
758 * VCO_MAX * r2 > n2 * LC_FREQ and
759 * VCO_MIN * r2 < n2 * LC_FREQ)
761 * Which means the desired boundaries for n2 are:
762 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
764 for (n2
= VCO_MIN
* r2
/ LC_FREQ
+ 1;
765 n2
<= VCO_MAX
* r2
/ LC_FREQ
;
768 for (p
= P_MIN
; p
<= P_MAX
; p
+= P_INC
)
769 wrpll_update_rnp(freq2k
, budget
,
780 hsw_ddi_pll_select(struct intel_crtc
*intel_crtc
,
781 struct intel_encoder
*intel_encoder
,
784 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
785 struct intel_shared_dpll
*pll
;
789 hsw_ddi_calculate_wrpll(clock
* 1000, &r2
, &n2
, &p
);
791 val
= WRPLL_PLL_ENABLE
| WRPLL_PLL_LCPLL
|
792 WRPLL_DIVIDER_REFERENCE(r2
) | WRPLL_DIVIDER_FEEDBACK(n2
) |
793 WRPLL_DIVIDER_POST(p
);
795 intel_crtc
->config
.dpll_hw_state
.wrpll
= val
;
797 pll
= intel_get_shared_dpll(intel_crtc
);
799 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
800 pipe_name(intel_crtc
->pipe
));
804 intel_crtc
->config
.ddi_pll_sel
= PORT_CLK_SEL_WRPLL(pll
->id
);
812 * Tries to find a *shared* PLL for the CRTC and store it in
813 * intel_crtc->ddi_pll_sel.
815 * For private DPLLs, compute_config() should do the selection for us. This
816 * function should be folded into compute_config() eventually.
818 bool intel_ddi_pll_select(struct intel_crtc
*intel_crtc
)
820 struct drm_crtc
*crtc
= &intel_crtc
->base
;
821 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
822 int clock
= intel_crtc
->config
.port_clock
;
824 intel_put_shared_dpll(intel_crtc
);
826 return hsw_ddi_pll_select(intel_crtc
, intel_encoder
, clock
);
829 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
)
831 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
832 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
833 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
834 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
835 int type
= intel_encoder
->type
;
838 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
|| type
== INTEL_OUTPUT_DP_MST
) {
839 temp
= TRANS_MSA_SYNC_CLK
;
840 switch (intel_crtc
->config
.pipe_bpp
) {
842 temp
|= TRANS_MSA_6_BPC
;
845 temp
|= TRANS_MSA_8_BPC
;
848 temp
|= TRANS_MSA_10_BPC
;
851 temp
|= TRANS_MSA_12_BPC
;
856 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder
), temp
);
860 void intel_ddi_set_vc_payload_alloc(struct drm_crtc
*crtc
, bool state
)
862 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
863 struct drm_device
*dev
= crtc
->dev
;
864 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
865 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
867 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
869 temp
|= TRANS_DDI_DP_VC_PAYLOAD_ALLOC
;
871 temp
&= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC
;
872 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
875 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
)
877 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
878 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
879 struct drm_encoder
*encoder
= &intel_encoder
->base
;
880 struct drm_device
*dev
= crtc
->dev
;
881 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
882 enum pipe pipe
= intel_crtc
->pipe
;
883 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
884 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
885 int type
= intel_encoder
->type
;
888 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
889 temp
= TRANS_DDI_FUNC_ENABLE
;
890 temp
|= TRANS_DDI_SELECT_PORT(port
);
892 switch (intel_crtc
->config
.pipe_bpp
) {
894 temp
|= TRANS_DDI_BPC_6
;
897 temp
|= TRANS_DDI_BPC_8
;
900 temp
|= TRANS_DDI_BPC_10
;
903 temp
|= TRANS_DDI_BPC_12
;
909 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
910 temp
|= TRANS_DDI_PVSYNC
;
911 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
912 temp
|= TRANS_DDI_PHSYNC
;
914 if (cpu_transcoder
== TRANSCODER_EDP
) {
917 /* On Haswell, can only use the always-on power well for
918 * eDP when not using the panel fitter, and when not
919 * using motion blur mitigation (which we don't
921 if (IS_HASWELL(dev
) &&
922 (intel_crtc
->config
.pch_pfit
.enabled
||
923 intel_crtc
->config
.pch_pfit
.force_thru
))
924 temp
|= TRANS_DDI_EDP_INPUT_A_ONOFF
;
926 temp
|= TRANS_DDI_EDP_INPUT_A_ON
;
929 temp
|= TRANS_DDI_EDP_INPUT_B_ONOFF
;
932 temp
|= TRANS_DDI_EDP_INPUT_C_ONOFF
;
940 if (type
== INTEL_OUTPUT_HDMI
) {
941 if (intel_crtc
->config
.has_hdmi_sink
)
942 temp
|= TRANS_DDI_MODE_SELECT_HDMI
;
944 temp
|= TRANS_DDI_MODE_SELECT_DVI
;
946 } else if (type
== INTEL_OUTPUT_ANALOG
) {
947 temp
|= TRANS_DDI_MODE_SELECT_FDI
;
948 temp
|= (intel_crtc
->config
.fdi_lanes
- 1) << 1;
950 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
||
951 type
== INTEL_OUTPUT_EDP
) {
952 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
954 if (intel_dp
->is_mst
) {
955 temp
|= TRANS_DDI_MODE_SELECT_DP_MST
;
957 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
959 temp
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
960 } else if (type
== INTEL_OUTPUT_DP_MST
) {
961 struct intel_dp
*intel_dp
= &enc_to_mst(encoder
)->primary
->dp
;
963 if (intel_dp
->is_mst
) {
964 temp
|= TRANS_DDI_MODE_SELECT_DP_MST
;
966 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
968 temp
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
970 WARN(1, "Invalid encoder type %d for pipe %c\n",
971 intel_encoder
->type
, pipe_name(pipe
));
974 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
977 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
978 enum transcoder cpu_transcoder
)
980 uint32_t reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
981 uint32_t val
= I915_READ(reg
);
983 val
&= ~(TRANS_DDI_FUNC_ENABLE
| TRANS_DDI_PORT_MASK
| TRANS_DDI_DP_VC_PAYLOAD_ALLOC
);
984 val
|= TRANS_DDI_PORT_NONE
;
985 I915_WRITE(reg
, val
);
988 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
)
990 struct drm_device
*dev
= intel_connector
->base
.dev
;
991 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
992 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
993 int type
= intel_connector
->base
.connector_type
;
994 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
996 enum transcoder cpu_transcoder
;
997 enum intel_display_power_domain power_domain
;
1000 power_domain
= intel_display_port_power_domain(intel_encoder
);
1001 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
1004 if (!intel_encoder
->get_hw_state(intel_encoder
, &pipe
))
1008 cpu_transcoder
= TRANSCODER_EDP
;
1010 cpu_transcoder
= (enum transcoder
) pipe
;
1012 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1014 switch (tmp
& TRANS_DDI_MODE_SELECT_MASK
) {
1015 case TRANS_DDI_MODE_SELECT_HDMI
:
1016 case TRANS_DDI_MODE_SELECT_DVI
:
1017 return (type
== DRM_MODE_CONNECTOR_HDMIA
);
1019 case TRANS_DDI_MODE_SELECT_DP_SST
:
1020 if (type
== DRM_MODE_CONNECTOR_eDP
)
1022 return (type
== DRM_MODE_CONNECTOR_DisplayPort
);
1023 case TRANS_DDI_MODE_SELECT_DP_MST
:
1024 /* if the transcoder is in MST state then
1025 * connector isn't connected */
1028 case TRANS_DDI_MODE_SELECT_FDI
:
1029 return (type
== DRM_MODE_CONNECTOR_VGA
);
1036 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
,
1039 struct drm_device
*dev
= encoder
->base
.dev
;
1040 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1041 enum port port
= intel_ddi_get_encoder_port(encoder
);
1042 enum intel_display_power_domain power_domain
;
1046 power_domain
= intel_display_port_power_domain(encoder
);
1047 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
1050 tmp
= I915_READ(DDI_BUF_CTL(port
));
1052 if (!(tmp
& DDI_BUF_CTL_ENABLE
))
1055 if (port
== PORT_A
) {
1056 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
1058 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
1059 case TRANS_DDI_EDP_INPUT_A_ON
:
1060 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
1063 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
1066 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
1073 for (i
= TRANSCODER_A
; i
<= TRANSCODER_C
; i
++) {
1074 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(i
));
1076 if ((tmp
& TRANS_DDI_PORT_MASK
)
1077 == TRANS_DDI_SELECT_PORT(port
)) {
1078 if ((tmp
& TRANS_DDI_MODE_SELECT_MASK
) == TRANS_DDI_MODE_SELECT_DP_MST
)
1087 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port
));
1092 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
)
1094 struct drm_crtc
*crtc
= &intel_crtc
->base
;
1095 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1096 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1097 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1098 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
1100 if (cpu_transcoder
!= TRANSCODER_EDP
)
1101 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1102 TRANS_CLK_SEL_PORT(port
));
1105 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
)
1107 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1108 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
1110 if (cpu_transcoder
!= TRANSCODER_EDP
)
1111 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1112 TRANS_CLK_SEL_DISABLED
);
1115 static void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder
)
1117 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1118 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1119 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->crtc
);
1120 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1121 int type
= intel_encoder
->type
;
1123 if (type
== INTEL_OUTPUT_EDP
) {
1124 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1125 intel_edp_panel_on(intel_dp
);
1128 WARN_ON(crtc
->config
.ddi_pll_sel
== PORT_CLK_SEL_NONE
);
1129 I915_WRITE(PORT_CLK_SEL(port
), crtc
->config
.ddi_pll_sel
);
1131 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
1132 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1134 intel_ddi_init_dp_buf_reg(intel_encoder
);
1136 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1137 intel_dp_start_link_train(intel_dp
);
1138 intel_dp_complete_link_train(intel_dp
);
1140 intel_dp_stop_link_train(intel_dp
);
1141 } else if (type
== INTEL_OUTPUT_HDMI
) {
1142 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1144 intel_hdmi
->set_infoframes(encoder
,
1145 crtc
->config
.has_hdmi_sink
,
1146 &crtc
->config
.adjusted_mode
);
1150 static void intel_ddi_post_disable(struct intel_encoder
*intel_encoder
)
1152 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1153 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1154 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1155 int type
= intel_encoder
->type
;
1159 val
= I915_READ(DDI_BUF_CTL(port
));
1160 if (val
& DDI_BUF_CTL_ENABLE
) {
1161 val
&= ~DDI_BUF_CTL_ENABLE
;
1162 I915_WRITE(DDI_BUF_CTL(port
), val
);
1166 val
= I915_READ(DP_TP_CTL(port
));
1167 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1168 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1169 I915_WRITE(DP_TP_CTL(port
), val
);
1172 intel_wait_ddi_buf_idle(dev_priv
, port
);
1174 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
1175 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1176 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
1177 intel_edp_panel_vdd_on(intel_dp
);
1178 intel_edp_panel_off(intel_dp
);
1181 I915_WRITE(PORT_CLK_SEL(port
), PORT_CLK_SEL_NONE
);
1184 static void intel_enable_ddi(struct intel_encoder
*intel_encoder
)
1186 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1187 struct drm_crtc
*crtc
= encoder
->crtc
;
1188 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1189 int pipe
= intel_crtc
->pipe
;
1190 struct drm_device
*dev
= encoder
->dev
;
1191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1192 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1193 int type
= intel_encoder
->type
;
1196 if (type
== INTEL_OUTPUT_HDMI
) {
1197 struct intel_digital_port
*intel_dig_port
=
1198 enc_to_dig_port(encoder
);
1200 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1201 * are ignored so nothing special needs to be done besides
1202 * enabling the port.
1204 I915_WRITE(DDI_BUF_CTL(port
),
1205 intel_dig_port
->saved_port_bits
|
1206 DDI_BUF_CTL_ENABLE
);
1207 } else if (type
== INTEL_OUTPUT_EDP
) {
1208 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1211 intel_dp_stop_link_train(intel_dp
);
1213 intel_edp_backlight_on(intel_dp
);
1214 intel_edp_psr_enable(intel_dp
);
1217 if (intel_crtc
->config
.has_audio
) {
1218 intel_display_power_get(dev_priv
, POWER_DOMAIN_AUDIO
);
1219 intel_write_eld(intel_encoder
);
1221 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
1222 tmp
|= ((AUDIO_OUTPUT_ENABLE_A
| AUDIO_ELD_VALID_A
) << (pipe
* 4));
1223 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
1227 static void intel_disable_ddi(struct intel_encoder
*intel_encoder
)
1229 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1230 struct drm_crtc
*crtc
= encoder
->crtc
;
1231 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1232 int pipe
= intel_crtc
->pipe
;
1233 int type
= intel_encoder
->type
;
1234 struct drm_device
*dev
= encoder
->dev
;
1235 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1238 /* We can't touch HSW_AUD_PIN_ELD_CP_VLD uncionditionally because this
1239 * register is part of the power well on Haswell. */
1240 if (intel_crtc
->config
.has_audio
) {
1241 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
1242 tmp
&= ~((AUDIO_OUTPUT_ENABLE_A
| AUDIO_ELD_VALID_A
) <<
1244 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
1245 intel_display_power_put(dev_priv
, POWER_DOMAIN_AUDIO
);
1248 if (type
== INTEL_OUTPUT_EDP
) {
1249 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1251 intel_edp_psr_disable(intel_dp
);
1252 intel_edp_backlight_off(intel_dp
);
1256 static int bdw_get_cdclk_freq(struct drm_i915_private
*dev_priv
)
1258 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
1259 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
1261 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
1263 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
1265 else if (freq
== LCPLL_CLK_FREQ_450
)
1267 else if (freq
== LCPLL_CLK_FREQ_54O_BDW
)
1269 else if (freq
== LCPLL_CLK_FREQ_337_5_BDW
)
1275 static int hsw_get_cdclk_freq(struct drm_i915_private
*dev_priv
)
1277 struct drm_device
*dev
= dev_priv
->dev
;
1278 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
1279 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
1281 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
1283 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
1285 else if (freq
== LCPLL_CLK_FREQ_450
)
1287 else if (IS_HSW_ULT(dev
))
1293 int intel_ddi_get_cdclk_freq(struct drm_i915_private
*dev_priv
)
1295 struct drm_device
*dev
= dev_priv
->dev
;
1297 if (IS_BROADWELL(dev
))
1298 return bdw_get_cdclk_freq(dev_priv
);
1301 return hsw_get_cdclk_freq(dev_priv
);
1304 static void hsw_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
1305 struct intel_shared_dpll
*pll
)
1307 I915_WRITE(WRPLL_CTL(pll
->id
), pll
->hw_state
.wrpll
);
1308 POSTING_READ(WRPLL_CTL(pll
->id
));
1312 static void hsw_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
1313 struct intel_shared_dpll
*pll
)
1317 val
= I915_READ(WRPLL_CTL(pll
->id
));
1318 I915_WRITE(WRPLL_CTL(pll
->id
), val
& ~WRPLL_PLL_ENABLE
);
1319 POSTING_READ(WRPLL_CTL(pll
->id
));
1322 static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
1323 struct intel_shared_dpll
*pll
,
1324 struct intel_dpll_hw_state
*hw_state
)
1328 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
1331 val
= I915_READ(WRPLL_CTL(pll
->id
));
1332 hw_state
->wrpll
= val
;
1334 return val
& WRPLL_PLL_ENABLE
;
1337 static const char * const hsw_ddi_pll_names
[] = {
1342 static void hsw_shared_dplls_init(struct drm_i915_private
*dev_priv
)
1346 dev_priv
->num_shared_dpll
= 2;
1348 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
1349 dev_priv
->shared_dplls
[i
].id
= i
;
1350 dev_priv
->shared_dplls
[i
].name
= hsw_ddi_pll_names
[i
];
1351 dev_priv
->shared_dplls
[i
].disable
= hsw_ddi_pll_disable
;
1352 dev_priv
->shared_dplls
[i
].enable
= hsw_ddi_pll_enable
;
1353 dev_priv
->shared_dplls
[i
].get_hw_state
=
1354 hsw_ddi_pll_get_hw_state
;
1358 void intel_ddi_pll_init(struct drm_device
*dev
)
1360 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1361 uint32_t val
= I915_READ(LCPLL_CTL
);
1363 hsw_shared_dplls_init(dev_priv
);
1365 /* The LCPLL register should be turned on by the BIOS. For now let's
1366 * just check its state and print errors in case something is wrong.
1367 * Don't even try to turn it on.
1370 DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1371 intel_ddi_get_cdclk_freq(dev_priv
));
1373 if (val
& LCPLL_CD_SOURCE_FCLK
)
1374 DRM_ERROR("CDCLK source is not LCPLL\n");
1376 if (val
& LCPLL_PLL_DISABLE
)
1377 DRM_ERROR("LCPLL is disabled\n");
1380 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
)
1382 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
1383 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
1384 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1385 enum port port
= intel_dig_port
->port
;
1389 if (I915_READ(DP_TP_CTL(port
)) & DP_TP_CTL_ENABLE
) {
1390 val
= I915_READ(DDI_BUF_CTL(port
));
1391 if (val
& DDI_BUF_CTL_ENABLE
) {
1392 val
&= ~DDI_BUF_CTL_ENABLE
;
1393 I915_WRITE(DDI_BUF_CTL(port
), val
);
1397 val
= I915_READ(DP_TP_CTL(port
));
1398 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1399 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1400 I915_WRITE(DP_TP_CTL(port
), val
);
1401 POSTING_READ(DP_TP_CTL(port
));
1404 intel_wait_ddi_buf_idle(dev_priv
, port
);
1407 val
= DP_TP_CTL_ENABLE
|
1408 DP_TP_CTL_LINK_TRAIN_PAT1
| DP_TP_CTL_SCRAMBLE_DISABLE
;
1409 if (intel_dp
->is_mst
)
1410 val
|= DP_TP_CTL_MODE_MST
;
1412 val
|= DP_TP_CTL_MODE_SST
;
1413 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1414 val
|= DP_TP_CTL_ENHANCED_FRAME_ENABLE
;
1416 I915_WRITE(DP_TP_CTL(port
), val
);
1417 POSTING_READ(DP_TP_CTL(port
));
1419 intel_dp
->DP
|= DDI_BUF_CTL_ENABLE
;
1420 I915_WRITE(DDI_BUF_CTL(port
), intel_dp
->DP
);
1421 POSTING_READ(DDI_BUF_CTL(port
));
1426 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
)
1428 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1429 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1432 intel_ddi_post_disable(intel_encoder
);
1434 val
= I915_READ(_FDI_RXA_CTL
);
1435 val
&= ~FDI_RX_ENABLE
;
1436 I915_WRITE(_FDI_RXA_CTL
, val
);
1438 val
= I915_READ(_FDI_RXA_MISC
);
1439 val
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
1440 val
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1441 I915_WRITE(_FDI_RXA_MISC
, val
);
1443 val
= I915_READ(_FDI_RXA_CTL
);
1445 I915_WRITE(_FDI_RXA_CTL
, val
);
1447 val
= I915_READ(_FDI_RXA_CTL
);
1448 val
&= ~FDI_RX_PLL_ENABLE
;
1449 I915_WRITE(_FDI_RXA_CTL
, val
);
1452 static void intel_ddi_hot_plug(struct intel_encoder
*intel_encoder
)
1454 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
1455 int type
= intel_dig_port
->base
.type
;
1457 if (type
!= INTEL_OUTPUT_DISPLAYPORT
&&
1458 type
!= INTEL_OUTPUT_EDP
&&
1459 type
!= INTEL_OUTPUT_UNKNOWN
) {
1463 intel_dp_hot_plug(intel_encoder
);
1466 void intel_ddi_get_config(struct intel_encoder
*encoder
,
1467 struct intel_crtc_config
*pipe_config
)
1469 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
1470 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
1471 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
1472 u32 temp
, flags
= 0;
1474 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1475 if (temp
& TRANS_DDI_PHSYNC
)
1476 flags
|= DRM_MODE_FLAG_PHSYNC
;
1478 flags
|= DRM_MODE_FLAG_NHSYNC
;
1479 if (temp
& TRANS_DDI_PVSYNC
)
1480 flags
|= DRM_MODE_FLAG_PVSYNC
;
1482 flags
|= DRM_MODE_FLAG_NVSYNC
;
1484 pipe_config
->adjusted_mode
.flags
|= flags
;
1486 switch (temp
& TRANS_DDI_BPC_MASK
) {
1487 case TRANS_DDI_BPC_6
:
1488 pipe_config
->pipe_bpp
= 18;
1490 case TRANS_DDI_BPC_8
:
1491 pipe_config
->pipe_bpp
= 24;
1493 case TRANS_DDI_BPC_10
:
1494 pipe_config
->pipe_bpp
= 30;
1496 case TRANS_DDI_BPC_12
:
1497 pipe_config
->pipe_bpp
= 36;
1503 switch (temp
& TRANS_DDI_MODE_SELECT_MASK
) {
1504 case TRANS_DDI_MODE_SELECT_HDMI
:
1505 pipe_config
->has_hdmi_sink
= true;
1506 case TRANS_DDI_MODE_SELECT_DVI
:
1507 case TRANS_DDI_MODE_SELECT_FDI
:
1509 case TRANS_DDI_MODE_SELECT_DP_SST
:
1510 case TRANS_DDI_MODE_SELECT_DP_MST
:
1511 pipe_config
->has_dp_encoder
= true;
1512 intel_dp_get_m_n(intel_crtc
, pipe_config
);
1518 if (intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_AUDIO
)) {
1519 temp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
1520 if (temp
& (AUDIO_OUTPUT_ENABLE_A
<< (intel_crtc
->pipe
* 4)))
1521 pipe_config
->has_audio
= true;
1524 if (encoder
->type
== INTEL_OUTPUT_EDP
&& dev_priv
->vbt
.edp_bpp
&&
1525 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
1527 * This is a big fat ugly hack.
1529 * Some machines in UEFI boot mode provide us a VBT that has 18
1530 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1531 * unknown we fail to light up. Yet the same BIOS boots up with
1532 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1533 * max, not what it tells us to use.
1535 * Note: This will still be broken if the eDP panel is not lit
1536 * up by the BIOS, and thus we can't get the mode at module
1539 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1540 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
1541 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
1544 hsw_ddi_clock_get(encoder
, pipe_config
);
1547 static void intel_ddi_destroy(struct drm_encoder
*encoder
)
1549 /* HDMI has nothing special to destroy, so we can go with this. */
1550 intel_dp_encoder_destroy(encoder
);
1553 static bool intel_ddi_compute_config(struct intel_encoder
*encoder
,
1554 struct intel_crtc_config
*pipe_config
)
1556 int type
= encoder
->type
;
1557 int port
= intel_ddi_get_encoder_port(encoder
);
1559 WARN(type
== INTEL_OUTPUT_UNKNOWN
, "compute_config() on unknown output!\n");
1562 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
1564 if (type
== INTEL_OUTPUT_HDMI
)
1565 return intel_hdmi_compute_config(encoder
, pipe_config
);
1567 return intel_dp_compute_config(encoder
, pipe_config
);
1570 static const struct drm_encoder_funcs intel_ddi_funcs
= {
1571 .destroy
= intel_ddi_destroy
,
1574 static struct intel_connector
*
1575 intel_ddi_init_dp_connector(struct intel_digital_port
*intel_dig_port
)
1577 struct intel_connector
*connector
;
1578 enum port port
= intel_dig_port
->port
;
1580 connector
= kzalloc(sizeof(*connector
), GFP_KERNEL
);
1584 intel_dig_port
->dp
.output_reg
= DDI_BUF_CTL(port
);
1585 if (!intel_dp_init_connector(intel_dig_port
, connector
)) {
1593 static struct intel_connector
*
1594 intel_ddi_init_hdmi_connector(struct intel_digital_port
*intel_dig_port
)
1596 struct intel_connector
*connector
;
1597 enum port port
= intel_dig_port
->port
;
1599 connector
= kzalloc(sizeof(*connector
), GFP_KERNEL
);
1603 intel_dig_port
->hdmi
.hdmi_reg
= DDI_BUF_CTL(port
);
1604 intel_hdmi_init_connector(intel_dig_port
, connector
);
1609 void intel_ddi_init(struct drm_device
*dev
, enum port port
)
1611 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1612 struct intel_digital_port
*intel_dig_port
;
1613 struct intel_encoder
*intel_encoder
;
1614 struct drm_encoder
*encoder
;
1615 bool init_hdmi
, init_dp
;
1617 init_hdmi
= (dev_priv
->vbt
.ddi_port_info
[port
].supports_dvi
||
1618 dev_priv
->vbt
.ddi_port_info
[port
].supports_hdmi
);
1619 init_dp
= dev_priv
->vbt
.ddi_port_info
[port
].supports_dp
;
1620 if (!init_dp
&& !init_hdmi
) {
1621 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
1627 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
1628 if (!intel_dig_port
)
1631 intel_encoder
= &intel_dig_port
->base
;
1632 encoder
= &intel_encoder
->base
;
1634 drm_encoder_init(dev
, encoder
, &intel_ddi_funcs
,
1635 DRM_MODE_ENCODER_TMDS
);
1637 intel_encoder
->compute_config
= intel_ddi_compute_config
;
1638 intel_encoder
->enable
= intel_enable_ddi
;
1639 intel_encoder
->pre_enable
= intel_ddi_pre_enable
;
1640 intel_encoder
->disable
= intel_disable_ddi
;
1641 intel_encoder
->post_disable
= intel_ddi_post_disable
;
1642 intel_encoder
->get_hw_state
= intel_ddi_get_hw_state
;
1643 intel_encoder
->get_config
= intel_ddi_get_config
;
1645 intel_dig_port
->port
= port
;
1646 intel_dig_port
->saved_port_bits
= I915_READ(DDI_BUF_CTL(port
)) &
1647 (DDI_BUF_PORT_REVERSAL
|
1650 intel_encoder
->type
= INTEL_OUTPUT_UNKNOWN
;
1651 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
1652 intel_encoder
->cloneable
= 0;
1653 intel_encoder
->hot_plug
= intel_ddi_hot_plug
;
1656 if (!intel_ddi_init_dp_connector(intel_dig_port
))
1659 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
1660 dev_priv
->hpd_irq_port
[port
] = intel_dig_port
;
1663 /* In theory we don't need the encoder->type check, but leave it just in
1664 * case we have some really bad VBTs... */
1665 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
&& init_hdmi
) {
1666 if (!intel_ddi_init_hdmi_connector(intel_dig_port
))
1673 drm_encoder_cleanup(encoder
);
1674 kfree(intel_dig_port
);