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Merge branch 'perf/rbtree_copy' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include "i915_drv.h"
29 #include "intel_drv.h"
30
31 struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
34 };
35
36 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
37 * them for both DP and FDI transports, allowing those ports to
38 * automatically adapt to HDMI connections as well
39 */
40 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
41 { 0x00FFFFFF, 0x0006000E },
42 { 0x00D75FFF, 0x0005000A },
43 { 0x00C30FFF, 0x00040006 },
44 { 0x80AAAFFF, 0x000B0000 },
45 { 0x00FFFFFF, 0x0005000A },
46 { 0x00D75FFF, 0x000C0004 },
47 { 0x80C30FFF, 0x000B0000 },
48 { 0x00FFFFFF, 0x00040006 },
49 { 0x80D75FFF, 0x000B0000 },
50 };
51
52 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
53 { 0x00FFFFFF, 0x0007000E },
54 { 0x00D75FFF, 0x000F000A },
55 { 0x00C30FFF, 0x00060006 },
56 { 0x00AAAFFF, 0x001E0000 },
57 { 0x00FFFFFF, 0x000F000A },
58 { 0x00D75FFF, 0x00160004 },
59 { 0x00C30FFF, 0x001E0000 },
60 { 0x00FFFFFF, 0x00060006 },
61 { 0x00D75FFF, 0x001E0000 },
62 };
63
64 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
65 /* Idx NT mV d T mV d db */
66 { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */
67 { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */
68 { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */
69 { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */
70 { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */
71 { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */
72 { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */
73 { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */
74 { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */
75 { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */
76 { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */
77 { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */
78 };
79
80 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
81 { 0x00FFFFFF, 0x00000012 },
82 { 0x00EBAFFF, 0x00020011 },
83 { 0x00C71FFF, 0x0006000F },
84 { 0x00AAAFFF, 0x000E000A },
85 { 0x00FFFFFF, 0x00020011 },
86 { 0x00DB6FFF, 0x0005000F },
87 { 0x00BEEFFF, 0x000A000C },
88 { 0x00FFFFFF, 0x0005000F },
89 { 0x00DB6FFF, 0x000A000C },
90 };
91
92 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
93 { 0x00FFFFFF, 0x0007000E },
94 { 0x00D75FFF, 0x000E000A },
95 { 0x00BEFFFF, 0x00140006 },
96 { 0x80B2CFFF, 0x001B0002 },
97 { 0x00FFFFFF, 0x000E000A },
98 { 0x00DB6FFF, 0x00160005 },
99 { 0x80C71FFF, 0x001A0002 },
100 { 0x00F7DFFF, 0x00180004 },
101 { 0x80D75FFF, 0x001B0002 },
102 };
103
104 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
105 { 0x00FFFFFF, 0x0001000E },
106 { 0x00D75FFF, 0x0004000A },
107 { 0x00C30FFF, 0x00070006 },
108 { 0x00AAAFFF, 0x000C0000 },
109 { 0x00FFFFFF, 0x0004000A },
110 { 0x00D75FFF, 0x00090004 },
111 { 0x00C30FFF, 0x000C0000 },
112 { 0x00FFFFFF, 0x00070006 },
113 { 0x00D75FFF, 0x000C0000 },
114 };
115
116 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
117 /* Idx NT mV d T mV df db */
118 { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */
119 { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */
120 { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */
121 { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */
122 { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */
123 { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */
124 { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */
125 { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */
126 { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */
127 { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */
128 };
129
130 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
131 { 0x00000018, 0x000000a2 },
132 { 0x00004014, 0x0000009B },
133 { 0x00006012, 0x00000088 },
134 { 0x00008010, 0x00000087 },
135 { 0x00000018, 0x0000009B },
136 { 0x00004014, 0x00000088 },
137 { 0x00006012, 0x00000087 },
138 { 0x00000018, 0x00000088 },
139 { 0x00004014, 0x00000087 },
140 };
141
142 /* eDP 1.4 low vswing translation parameters */
143 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
144 { 0x00000018, 0x000000a8 },
145 { 0x00002016, 0x000000ab },
146 { 0x00006012, 0x000000a2 },
147 { 0x00008010, 0x00000088 },
148 { 0x00000018, 0x000000ab },
149 { 0x00004014, 0x000000a2 },
150 { 0x00006012, 0x000000a6 },
151 { 0x00000018, 0x000000a2 },
152 { 0x00005013, 0x0000009c },
153 { 0x00000018, 0x00000088 },
154 };
155
156
157 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
158 { 0x00000018, 0x000000ac },
159 { 0x00005012, 0x0000009d },
160 { 0x00007011, 0x00000088 },
161 { 0x00000018, 0x000000a1 },
162 { 0x00000018, 0x00000098 },
163 { 0x00004013, 0x00000088 },
164 { 0x00006012, 0x00000087 },
165 { 0x00000018, 0x000000df },
166 { 0x00003015, 0x00000087 },
167 { 0x00003015, 0x000000c7 },
168 { 0x00000018, 0x000000c7 },
169 };
170
171 struct bxt_ddi_buf_trans {
172 u32 margin; /* swing value */
173 u32 scale; /* scale value */
174 u32 enable; /* scale enable */
175 u32 deemphasis;
176 bool default_index; /* true if the entry represents default value */
177 };
178
179 /* BSpec does not define separate vswing/pre-emphasis values for eDP.
180 * Using DP values for eDP as well.
181 */
182 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
183 /* Idx NT mV diff db */
184 { 52, 0, 0, 128, true }, /* 0: 400 0 */
185 { 78, 0, 0, 85, false }, /* 1: 400 3.5 */
186 { 104, 0, 0, 64, false }, /* 2: 400 6 */
187 { 154, 0, 0, 43, false }, /* 3: 400 9.5 */
188 { 77, 0, 0, 128, false }, /* 4: 600 0 */
189 { 116, 0, 0, 85, false }, /* 5: 600 3.5 */
190 { 154, 0, 0, 64, false }, /* 6: 600 6 */
191 { 102, 0, 0, 128, false }, /* 7: 800 0 */
192 { 154, 0, 0, 85, false }, /* 8: 800 3.5 */
193 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
194 };
195
196 /* BSpec has 2 recommended values - entries 0 and 8.
197 * Using the entry with higher vswing.
198 */
199 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
200 /* Idx NT mV diff db */
201 { 52, 0, 0, 128, false }, /* 0: 400 0 */
202 { 52, 0, 0, 85, false }, /* 1: 400 3.5 */
203 { 52, 0, 0, 64, false }, /* 2: 400 6 */
204 { 42, 0, 0, 43, false }, /* 3: 400 9.5 */
205 { 77, 0, 0, 128, false }, /* 4: 600 0 */
206 { 77, 0, 0, 85, false }, /* 5: 600 3.5 */
207 { 77, 0, 0, 64, false }, /* 6: 600 6 */
208 { 102, 0, 0, 128, false }, /* 7: 800 0 */
209 { 102, 0, 0, 85, false }, /* 8: 800 3.5 */
210 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
211 };
212
213 static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
214 struct intel_digital_port **dig_port,
215 enum port *port)
216 {
217 struct drm_encoder *encoder = &intel_encoder->base;
218 int type = intel_encoder->type;
219
220 if (type == INTEL_OUTPUT_DP_MST) {
221 *dig_port = enc_to_mst(encoder)->primary;
222 *port = (*dig_port)->port;
223 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
224 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
225 *dig_port = enc_to_dig_port(encoder);
226 *port = (*dig_port)->port;
227 } else if (type == INTEL_OUTPUT_ANALOG) {
228 *dig_port = NULL;
229 *port = PORT_E;
230 } else {
231 DRM_ERROR("Invalid DDI encoder type %d\n", type);
232 BUG();
233 }
234 }
235
236 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
237 {
238 struct intel_digital_port *dig_port;
239 enum port port;
240
241 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
242
243 return port;
244 }
245
246 static bool
247 intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
248 {
249 return intel_dig_port->hdmi.hdmi_reg;
250 }
251
252 /*
253 * Starting with Haswell, DDI port buffers must be programmed with correct
254 * values in advance. The buffer values are different for FDI and DP modes,
255 * but the HDMI/DVI fields are shared among those. So we program the DDI
256 * in either FDI or DP modes only, as HDMI connections will work with both
257 * of those
258 */
259 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
260 bool supports_hdmi)
261 {
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 u32 reg;
264 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
265 size;
266 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
267 const struct ddi_buf_trans *ddi_translations_fdi;
268 const struct ddi_buf_trans *ddi_translations_dp;
269 const struct ddi_buf_trans *ddi_translations_edp;
270 const struct ddi_buf_trans *ddi_translations_hdmi;
271 const struct ddi_buf_trans *ddi_translations;
272
273 if (IS_BROXTON(dev)) {
274 if (!supports_hdmi)
275 return;
276
277 /* Vswing programming for HDMI */
278 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
279 INTEL_OUTPUT_HDMI);
280 return;
281 } else if (IS_SKYLAKE(dev)) {
282 ddi_translations_fdi = NULL;
283 ddi_translations_dp = skl_ddi_translations_dp;
284 n_dp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
285 if (dev_priv->edp_low_vswing) {
286 ddi_translations_edp = skl_ddi_translations_edp;
287 n_edp_entries = ARRAY_SIZE(skl_ddi_translations_edp);
288 } else {
289 ddi_translations_edp = skl_ddi_translations_dp;
290 n_edp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
291 }
292
293 ddi_translations_hdmi = skl_ddi_translations_hdmi;
294 n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
295 hdmi_default_entry = 7;
296 } else if (IS_BROADWELL(dev)) {
297 ddi_translations_fdi = bdw_ddi_translations_fdi;
298 ddi_translations_dp = bdw_ddi_translations_dp;
299 ddi_translations_edp = bdw_ddi_translations_edp;
300 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
301 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
302 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
303 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
304 hdmi_default_entry = 7;
305 } else if (IS_HASWELL(dev)) {
306 ddi_translations_fdi = hsw_ddi_translations_fdi;
307 ddi_translations_dp = hsw_ddi_translations_dp;
308 ddi_translations_edp = hsw_ddi_translations_dp;
309 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
310 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
311 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
312 hdmi_default_entry = 6;
313 } else {
314 WARN(1, "ddi translation table missing\n");
315 ddi_translations_edp = bdw_ddi_translations_dp;
316 ddi_translations_fdi = bdw_ddi_translations_fdi;
317 ddi_translations_dp = bdw_ddi_translations_dp;
318 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
319 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
320 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
321 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
322 hdmi_default_entry = 7;
323 }
324
325 switch (port) {
326 case PORT_A:
327 ddi_translations = ddi_translations_edp;
328 size = n_edp_entries;
329 break;
330 case PORT_B:
331 case PORT_C:
332 ddi_translations = ddi_translations_dp;
333 size = n_dp_entries;
334 break;
335 case PORT_D:
336 if (intel_dp_is_edp(dev, PORT_D)) {
337 ddi_translations = ddi_translations_edp;
338 size = n_edp_entries;
339 } else {
340 ddi_translations = ddi_translations_dp;
341 size = n_dp_entries;
342 }
343 break;
344 case PORT_E:
345 if (ddi_translations_fdi)
346 ddi_translations = ddi_translations_fdi;
347 else
348 ddi_translations = ddi_translations_dp;
349 size = n_dp_entries;
350 break;
351 default:
352 BUG();
353 }
354
355 for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) {
356 I915_WRITE(reg, ddi_translations[i].trans1);
357 reg += 4;
358 I915_WRITE(reg, ddi_translations[i].trans2);
359 reg += 4;
360 }
361
362 if (!supports_hdmi)
363 return;
364
365 /* Choose a good default if VBT is badly populated */
366 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
367 hdmi_level >= n_hdmi_entries)
368 hdmi_level = hdmi_default_entry;
369
370 /* Entry 9 is for HDMI: */
371 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
372 reg += 4;
373 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
374 reg += 4;
375 }
376
377 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
378 * mode and port E for FDI.
379 */
380 void intel_prepare_ddi(struct drm_device *dev)
381 {
382 struct intel_encoder *intel_encoder;
383 bool visited[I915_MAX_PORTS] = { 0, };
384
385 if (!HAS_DDI(dev))
386 return;
387
388 for_each_intel_encoder(dev, intel_encoder) {
389 struct intel_digital_port *intel_dig_port;
390 enum port port;
391 bool supports_hdmi;
392
393 ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
394
395 if (visited[port])
396 continue;
397
398 supports_hdmi = intel_dig_port &&
399 intel_dig_port_supports_hdmi(intel_dig_port);
400
401 intel_prepare_ddi_buffers(dev, port, supports_hdmi);
402 visited[port] = true;
403 }
404 }
405
406 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
407 enum port port)
408 {
409 uint32_t reg = DDI_BUF_CTL(port);
410 int i;
411
412 for (i = 0; i < 16; i++) {
413 udelay(1);
414 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
415 return;
416 }
417 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
418 }
419
420 /* Starting with Haswell, different DDI ports can work in FDI mode for
421 * connection to the PCH-located connectors. For this, it is necessary to train
422 * both the DDI port and PCH receiver for the desired DDI buffer settings.
423 *
424 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
425 * please note that when FDI mode is active on DDI E, it shares 2 lines with
426 * DDI A (which is used for eDP)
427 */
428
429 void hsw_fdi_link_train(struct drm_crtc *crtc)
430 {
431 struct drm_device *dev = crtc->dev;
432 struct drm_i915_private *dev_priv = dev->dev_private;
433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
434 u32 temp, i, rx_ctl_val;
435
436 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
437 * mode set "sequence for CRT port" document:
438 * - TP1 to TP2 time with the default value
439 * - FDI delay to 90h
440 *
441 * WaFDIAutoLinkSetTimingOverrride:hsw
442 */
443 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
444 FDI_RX_PWRDN_LANE0_VAL(2) |
445 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
446
447 /* Enable the PCH Receiver FDI PLL */
448 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
449 FDI_RX_PLL_ENABLE |
450 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
451 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
452 POSTING_READ(_FDI_RXA_CTL);
453 udelay(220);
454
455 /* Switch from Rawclk to PCDclk */
456 rx_ctl_val |= FDI_PCDCLK;
457 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
458
459 /* Configure Port Clock Select */
460 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
461 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
462
463 /* Start the training iterating through available voltages and emphasis,
464 * testing each value twice. */
465 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
466 /* Configure DP_TP_CTL with auto-training */
467 I915_WRITE(DP_TP_CTL(PORT_E),
468 DP_TP_CTL_FDI_AUTOTRAIN |
469 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
470 DP_TP_CTL_LINK_TRAIN_PAT1 |
471 DP_TP_CTL_ENABLE);
472
473 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
474 * DDI E does not support port reversal, the functionality is
475 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
476 * port reversal bit */
477 I915_WRITE(DDI_BUF_CTL(PORT_E),
478 DDI_BUF_CTL_ENABLE |
479 ((intel_crtc->config->fdi_lanes - 1) << 1) |
480 DDI_BUF_TRANS_SELECT(i / 2));
481 POSTING_READ(DDI_BUF_CTL(PORT_E));
482
483 udelay(600);
484
485 /* Program PCH FDI Receiver TU */
486 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
487
488 /* Enable PCH FDI Receiver with auto-training */
489 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
490 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
491 POSTING_READ(_FDI_RXA_CTL);
492
493 /* Wait for FDI receiver lane calibration */
494 udelay(30);
495
496 /* Unset FDI_RX_MISC pwrdn lanes */
497 temp = I915_READ(_FDI_RXA_MISC);
498 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
499 I915_WRITE(_FDI_RXA_MISC, temp);
500 POSTING_READ(_FDI_RXA_MISC);
501
502 /* Wait for FDI auto training time */
503 udelay(5);
504
505 temp = I915_READ(DP_TP_STATUS(PORT_E));
506 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
507 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
508
509 /* Enable normal pixel sending for FDI */
510 I915_WRITE(DP_TP_CTL(PORT_E),
511 DP_TP_CTL_FDI_AUTOTRAIN |
512 DP_TP_CTL_LINK_TRAIN_NORMAL |
513 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
514 DP_TP_CTL_ENABLE);
515
516 return;
517 }
518
519 temp = I915_READ(DDI_BUF_CTL(PORT_E));
520 temp &= ~DDI_BUF_CTL_ENABLE;
521 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
522 POSTING_READ(DDI_BUF_CTL(PORT_E));
523
524 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
525 temp = I915_READ(DP_TP_CTL(PORT_E));
526 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
527 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
528 I915_WRITE(DP_TP_CTL(PORT_E), temp);
529 POSTING_READ(DP_TP_CTL(PORT_E));
530
531 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
532
533 rx_ctl_val &= ~FDI_RX_ENABLE;
534 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
535 POSTING_READ(_FDI_RXA_CTL);
536
537 /* Reset FDI_RX_MISC pwrdn lanes */
538 temp = I915_READ(_FDI_RXA_MISC);
539 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
540 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
541 I915_WRITE(_FDI_RXA_MISC, temp);
542 POSTING_READ(_FDI_RXA_MISC);
543 }
544
545 DRM_ERROR("FDI link training failed!\n");
546 }
547
548 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
549 {
550 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
551 struct intel_digital_port *intel_dig_port =
552 enc_to_dig_port(&encoder->base);
553
554 intel_dp->DP = intel_dig_port->saved_port_bits |
555 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
556 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
557
558 }
559
560 static struct intel_encoder *
561 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
562 {
563 struct drm_device *dev = crtc->dev;
564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
565 struct intel_encoder *intel_encoder, *ret = NULL;
566 int num_encoders = 0;
567
568 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
569 ret = intel_encoder;
570 num_encoders++;
571 }
572
573 if (num_encoders != 1)
574 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
575 pipe_name(intel_crtc->pipe));
576
577 BUG_ON(ret == NULL);
578 return ret;
579 }
580
581 struct intel_encoder *
582 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
583 {
584 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
585 struct intel_encoder *ret = NULL;
586 struct drm_atomic_state *state;
587 struct drm_connector *connector;
588 struct drm_connector_state *connector_state;
589 int num_encoders = 0;
590 int i;
591
592 state = crtc_state->base.state;
593
594 for_each_connector_in_state(state, connector, connector_state, i) {
595 if (connector_state->crtc != crtc_state->base.crtc)
596 continue;
597
598 ret = to_intel_encoder(connector_state->best_encoder);
599 num_encoders++;
600 }
601
602 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
603 pipe_name(crtc->pipe));
604
605 BUG_ON(ret == NULL);
606 return ret;
607 }
608
609 #define LC_FREQ 2700
610 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
611
612 #define P_MIN 2
613 #define P_MAX 64
614 #define P_INC 2
615
616 /* Constraints for PLL good behavior */
617 #define REF_MIN 48
618 #define REF_MAX 400
619 #define VCO_MIN 2400
620 #define VCO_MAX 4800
621
622 #define abs_diff(a, b) ({ \
623 typeof(a) __a = (a); \
624 typeof(b) __b = (b); \
625 (void) (&__a == &__b); \
626 __a > __b ? (__a - __b) : (__b - __a); })
627
628 struct wrpll_rnp {
629 unsigned p, n2, r2;
630 };
631
632 static unsigned wrpll_get_budget_for_freq(int clock)
633 {
634 unsigned budget;
635
636 switch (clock) {
637 case 25175000:
638 case 25200000:
639 case 27000000:
640 case 27027000:
641 case 37762500:
642 case 37800000:
643 case 40500000:
644 case 40541000:
645 case 54000000:
646 case 54054000:
647 case 59341000:
648 case 59400000:
649 case 72000000:
650 case 74176000:
651 case 74250000:
652 case 81000000:
653 case 81081000:
654 case 89012000:
655 case 89100000:
656 case 108000000:
657 case 108108000:
658 case 111264000:
659 case 111375000:
660 case 148352000:
661 case 148500000:
662 case 162000000:
663 case 162162000:
664 case 222525000:
665 case 222750000:
666 case 296703000:
667 case 297000000:
668 budget = 0;
669 break;
670 case 233500000:
671 case 245250000:
672 case 247750000:
673 case 253250000:
674 case 298000000:
675 budget = 1500;
676 break;
677 case 169128000:
678 case 169500000:
679 case 179500000:
680 case 202000000:
681 budget = 2000;
682 break;
683 case 256250000:
684 case 262500000:
685 case 270000000:
686 case 272500000:
687 case 273750000:
688 case 280750000:
689 case 281250000:
690 case 286000000:
691 case 291750000:
692 budget = 4000;
693 break;
694 case 267250000:
695 case 268500000:
696 budget = 5000;
697 break;
698 default:
699 budget = 1000;
700 break;
701 }
702
703 return budget;
704 }
705
706 static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
707 unsigned r2, unsigned n2, unsigned p,
708 struct wrpll_rnp *best)
709 {
710 uint64_t a, b, c, d, diff, diff_best;
711
712 /* No best (r,n,p) yet */
713 if (best->p == 0) {
714 best->p = p;
715 best->n2 = n2;
716 best->r2 = r2;
717 return;
718 }
719
720 /*
721 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
722 * freq2k.
723 *
724 * delta = 1e6 *
725 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
726 * freq2k;
727 *
728 * and we would like delta <= budget.
729 *
730 * If the discrepancy is above the PPM-based budget, always prefer to
731 * improve upon the previous solution. However, if you're within the
732 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
733 */
734 a = freq2k * budget * p * r2;
735 b = freq2k * budget * best->p * best->r2;
736 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
737 diff_best = abs_diff(freq2k * best->p * best->r2,
738 LC_FREQ_2K * best->n2);
739 c = 1000000 * diff;
740 d = 1000000 * diff_best;
741
742 if (a < c && b < d) {
743 /* If both are above the budget, pick the closer */
744 if (best->p * best->r2 * diff < p * r2 * diff_best) {
745 best->p = p;
746 best->n2 = n2;
747 best->r2 = r2;
748 }
749 } else if (a >= c && b < d) {
750 /* If A is below the threshold but B is above it? Update. */
751 best->p = p;
752 best->n2 = n2;
753 best->r2 = r2;
754 } else if (a >= c && b >= d) {
755 /* Both are below the limit, so pick the higher n2/(r2*r2) */
756 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
757 best->p = p;
758 best->n2 = n2;
759 best->r2 = r2;
760 }
761 }
762 /* Otherwise a < c && b >= d, do nothing */
763 }
764
765 static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
766 int reg)
767 {
768 int refclk = LC_FREQ;
769 int n, p, r;
770 u32 wrpll;
771
772 wrpll = I915_READ(reg);
773 switch (wrpll & WRPLL_PLL_REF_MASK) {
774 case WRPLL_PLL_SSC:
775 case WRPLL_PLL_NON_SSC:
776 /*
777 * We could calculate spread here, but our checking
778 * code only cares about 5% accuracy, and spread is a max of
779 * 0.5% downspread.
780 */
781 refclk = 135;
782 break;
783 case WRPLL_PLL_LCPLL:
784 refclk = LC_FREQ;
785 break;
786 default:
787 WARN(1, "bad wrpll refclk\n");
788 return 0;
789 }
790
791 r = wrpll & WRPLL_DIVIDER_REF_MASK;
792 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
793 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
794
795 /* Convert to KHz, p & r have a fixed point portion */
796 return (refclk * n * 100) / (p * r);
797 }
798
799 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
800 uint32_t dpll)
801 {
802 uint32_t cfgcr1_reg, cfgcr2_reg;
803 uint32_t cfgcr1_val, cfgcr2_val;
804 uint32_t p0, p1, p2, dco_freq;
805
806 cfgcr1_reg = GET_CFG_CR1_REG(dpll);
807 cfgcr2_reg = GET_CFG_CR2_REG(dpll);
808
809 cfgcr1_val = I915_READ(cfgcr1_reg);
810 cfgcr2_val = I915_READ(cfgcr2_reg);
811
812 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
813 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
814
815 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
816 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
817 else
818 p1 = 1;
819
820
821 switch (p0) {
822 case DPLL_CFGCR2_PDIV_1:
823 p0 = 1;
824 break;
825 case DPLL_CFGCR2_PDIV_2:
826 p0 = 2;
827 break;
828 case DPLL_CFGCR2_PDIV_3:
829 p0 = 3;
830 break;
831 case DPLL_CFGCR2_PDIV_7:
832 p0 = 7;
833 break;
834 }
835
836 switch (p2) {
837 case DPLL_CFGCR2_KDIV_5:
838 p2 = 5;
839 break;
840 case DPLL_CFGCR2_KDIV_2:
841 p2 = 2;
842 break;
843 case DPLL_CFGCR2_KDIV_3:
844 p2 = 3;
845 break;
846 case DPLL_CFGCR2_KDIV_1:
847 p2 = 1;
848 break;
849 }
850
851 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
852
853 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
854 1000) / 0x8000;
855
856 return dco_freq / (p0 * p1 * p2 * 5);
857 }
858
859
860 static void skl_ddi_clock_get(struct intel_encoder *encoder,
861 struct intel_crtc_state *pipe_config)
862 {
863 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
864 int link_clock = 0;
865 uint32_t dpll_ctl1, dpll;
866
867 dpll = pipe_config->ddi_pll_sel;
868
869 dpll_ctl1 = I915_READ(DPLL_CTRL1);
870
871 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
872 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
873 } else {
874 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
875 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
876
877 switch (link_clock) {
878 case DPLL_CTRL1_LINK_RATE_810:
879 link_clock = 81000;
880 break;
881 case DPLL_CTRL1_LINK_RATE_1080:
882 link_clock = 108000;
883 break;
884 case DPLL_CTRL1_LINK_RATE_1350:
885 link_clock = 135000;
886 break;
887 case DPLL_CTRL1_LINK_RATE_1620:
888 link_clock = 162000;
889 break;
890 case DPLL_CTRL1_LINK_RATE_2160:
891 link_clock = 216000;
892 break;
893 case DPLL_CTRL1_LINK_RATE_2700:
894 link_clock = 270000;
895 break;
896 default:
897 WARN(1, "Unsupported link rate\n");
898 break;
899 }
900 link_clock *= 2;
901 }
902
903 pipe_config->port_clock = link_clock;
904
905 if (pipe_config->has_dp_encoder)
906 pipe_config->base.adjusted_mode.crtc_clock =
907 intel_dotclock_calculate(pipe_config->port_clock,
908 &pipe_config->dp_m_n);
909 else
910 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
911 }
912
913 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
914 struct intel_crtc_state *pipe_config)
915 {
916 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
917 int link_clock = 0;
918 u32 val, pll;
919
920 val = pipe_config->ddi_pll_sel;
921 switch (val & PORT_CLK_SEL_MASK) {
922 case PORT_CLK_SEL_LCPLL_810:
923 link_clock = 81000;
924 break;
925 case PORT_CLK_SEL_LCPLL_1350:
926 link_clock = 135000;
927 break;
928 case PORT_CLK_SEL_LCPLL_2700:
929 link_clock = 270000;
930 break;
931 case PORT_CLK_SEL_WRPLL1:
932 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
933 break;
934 case PORT_CLK_SEL_WRPLL2:
935 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
936 break;
937 case PORT_CLK_SEL_SPLL:
938 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
939 if (pll == SPLL_PLL_FREQ_810MHz)
940 link_clock = 81000;
941 else if (pll == SPLL_PLL_FREQ_1350MHz)
942 link_clock = 135000;
943 else if (pll == SPLL_PLL_FREQ_2700MHz)
944 link_clock = 270000;
945 else {
946 WARN(1, "bad spll freq\n");
947 return;
948 }
949 break;
950 default:
951 WARN(1, "bad port clock sel\n");
952 return;
953 }
954
955 pipe_config->port_clock = link_clock * 2;
956
957 if (pipe_config->has_pch_encoder)
958 pipe_config->base.adjusted_mode.crtc_clock =
959 intel_dotclock_calculate(pipe_config->port_clock,
960 &pipe_config->fdi_m_n);
961 else if (pipe_config->has_dp_encoder)
962 pipe_config->base.adjusted_mode.crtc_clock =
963 intel_dotclock_calculate(pipe_config->port_clock,
964 &pipe_config->dp_m_n);
965 else
966 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
967 }
968
969 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
970 enum intel_dpll_id dpll)
971 {
972 /* FIXME formula not available in bspec */
973 return 0;
974 }
975
976 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
977 struct intel_crtc_state *pipe_config)
978 {
979 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
980 enum port port = intel_ddi_get_encoder_port(encoder);
981 uint32_t dpll = port;
982
983 pipe_config->port_clock =
984 bxt_calc_pll_link(dev_priv, dpll);
985
986 if (pipe_config->has_dp_encoder)
987 pipe_config->base.adjusted_mode.crtc_clock =
988 intel_dotclock_calculate(pipe_config->port_clock,
989 &pipe_config->dp_m_n);
990 else
991 pipe_config->base.adjusted_mode.crtc_clock =
992 pipe_config->port_clock;
993 }
994
995 void intel_ddi_clock_get(struct intel_encoder *encoder,
996 struct intel_crtc_state *pipe_config)
997 {
998 struct drm_device *dev = encoder->base.dev;
999
1000 if (INTEL_INFO(dev)->gen <= 8)
1001 hsw_ddi_clock_get(encoder, pipe_config);
1002 else if (IS_SKYLAKE(dev))
1003 skl_ddi_clock_get(encoder, pipe_config);
1004 else if (IS_BROXTON(dev))
1005 bxt_ddi_clock_get(encoder, pipe_config);
1006 }
1007
1008 static void
1009 hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1010 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1011 {
1012 uint64_t freq2k;
1013 unsigned p, n2, r2;
1014 struct wrpll_rnp best = { 0, 0, 0 };
1015 unsigned budget;
1016
1017 freq2k = clock / 100;
1018
1019 budget = wrpll_get_budget_for_freq(clock);
1020
1021 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1022 * and directly pass the LC PLL to it. */
1023 if (freq2k == 5400000) {
1024 *n2_out = 2;
1025 *p_out = 1;
1026 *r2_out = 2;
1027 return;
1028 }
1029
1030 /*
1031 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1032 * the WR PLL.
1033 *
1034 * We want R so that REF_MIN <= Ref <= REF_MAX.
1035 * Injecting R2 = 2 * R gives:
1036 * REF_MAX * r2 > LC_FREQ * 2 and
1037 * REF_MIN * r2 < LC_FREQ * 2
1038 *
1039 * Which means the desired boundaries for r2 are:
1040 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1041 *
1042 */
1043 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1044 r2 <= LC_FREQ * 2 / REF_MIN;
1045 r2++) {
1046
1047 /*
1048 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1049 *
1050 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1051 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1052 * VCO_MAX * r2 > n2 * LC_FREQ and
1053 * VCO_MIN * r2 < n2 * LC_FREQ)
1054 *
1055 * Which means the desired boundaries for n2 are:
1056 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1057 */
1058 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1059 n2 <= VCO_MAX * r2 / LC_FREQ;
1060 n2++) {
1061
1062 for (p = P_MIN; p <= P_MAX; p += P_INC)
1063 wrpll_update_rnp(freq2k, budget,
1064 r2, n2, p, &best);
1065 }
1066 }
1067
1068 *n2_out = best.n2;
1069 *p_out = best.p;
1070 *r2_out = best.r2;
1071 }
1072
1073 static bool
1074 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
1075 struct intel_crtc_state *crtc_state,
1076 struct intel_encoder *intel_encoder,
1077 int clock)
1078 {
1079 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1080 struct intel_shared_dpll *pll;
1081 uint32_t val;
1082 unsigned p, n2, r2;
1083
1084 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
1085
1086 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
1087 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1088 WRPLL_DIVIDER_POST(p);
1089
1090 memset(&crtc_state->dpll_hw_state, 0,
1091 sizeof(crtc_state->dpll_hw_state));
1092
1093 crtc_state->dpll_hw_state.wrpll = val;
1094
1095 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1096 if (pll == NULL) {
1097 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1098 pipe_name(intel_crtc->pipe));
1099 return false;
1100 }
1101
1102 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
1103 }
1104
1105 return true;
1106 }
1107
1108 struct skl_wrpll_params {
1109 uint32_t dco_fraction;
1110 uint32_t dco_integer;
1111 uint32_t qdiv_ratio;
1112 uint32_t qdiv_mode;
1113 uint32_t kdiv;
1114 uint32_t pdiv;
1115 uint32_t central_freq;
1116 };
1117
1118 static void
1119 skl_ddi_calculate_wrpll(int clock /* in Hz */,
1120 struct skl_wrpll_params *wrpll_params)
1121 {
1122 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
1123 uint64_t dco_central_freq[3] = {8400000000ULL,
1124 9000000000ULL,
1125 9600000000ULL};
1126 uint32_t min_dco_deviation = 400;
1127 uint32_t min_dco_index = 3;
1128 uint32_t P0[4] = {1, 2, 3, 7};
1129 uint32_t P2[4] = {1, 2, 3, 5};
1130 bool found = false;
1131 uint32_t candidate_p = 0;
1132 uint32_t candidate_p0[3] = {0}, candidate_p1[3] = {0};
1133 uint32_t candidate_p2[3] = {0};
1134 uint32_t dco_central_freq_deviation[3];
1135 uint32_t i, P1, k, dco_count;
1136 bool retry_with_odd = false;
1137 uint64_t dco_freq;
1138
1139 /* Determine P0, P1 or P2 */
1140 for (dco_count = 0; dco_count < 3; dco_count++) {
1141 found = false;
1142 candidate_p =
1143 div64_u64(dco_central_freq[dco_count], afe_clock);
1144 if (retry_with_odd == false)
1145 candidate_p = (candidate_p % 2 == 0 ?
1146 candidate_p : candidate_p + 1);
1147
1148 for (P1 = 1; P1 < candidate_p; P1++) {
1149 for (i = 0; i < 4; i++) {
1150 if (!(P0[i] != 1 || P1 == 1))
1151 continue;
1152
1153 for (k = 0; k < 4; k++) {
1154 if (P1 != 1 && P2[k] != 2)
1155 continue;
1156
1157 if (candidate_p == P0[i] * P1 * P2[k]) {
1158 /* Found possible P0, P1, P2 */
1159 found = true;
1160 candidate_p0[dco_count] = P0[i];
1161 candidate_p1[dco_count] = P1;
1162 candidate_p2[dco_count] = P2[k];
1163 goto found;
1164 }
1165
1166 }
1167 }
1168 }
1169
1170 found:
1171 if (found) {
1172 dco_central_freq_deviation[dco_count] =
1173 div64_u64(10000 *
1174 abs_diff((candidate_p * afe_clock),
1175 dco_central_freq[dco_count]),
1176 dco_central_freq[dco_count]);
1177
1178 if (dco_central_freq_deviation[dco_count] <
1179 min_dco_deviation) {
1180 min_dco_deviation =
1181 dco_central_freq_deviation[dco_count];
1182 min_dco_index = dco_count;
1183 }
1184 }
1185
1186 if (min_dco_index > 2 && dco_count == 2) {
1187 retry_with_odd = true;
1188 dco_count = 0;
1189 }
1190 }
1191
1192 if (min_dco_index > 2) {
1193 WARN(1, "No valid values found for the given pixel clock\n");
1194 } else {
1195 wrpll_params->central_freq = dco_central_freq[min_dco_index];
1196
1197 switch (dco_central_freq[min_dco_index]) {
1198 case 9600000000ULL:
1199 wrpll_params->central_freq = 0;
1200 break;
1201 case 9000000000ULL:
1202 wrpll_params->central_freq = 1;
1203 break;
1204 case 8400000000ULL:
1205 wrpll_params->central_freq = 3;
1206 }
1207
1208 switch (candidate_p0[min_dco_index]) {
1209 case 1:
1210 wrpll_params->pdiv = 0;
1211 break;
1212 case 2:
1213 wrpll_params->pdiv = 1;
1214 break;
1215 case 3:
1216 wrpll_params->pdiv = 2;
1217 break;
1218 case 7:
1219 wrpll_params->pdiv = 4;
1220 break;
1221 default:
1222 WARN(1, "Incorrect PDiv\n");
1223 }
1224
1225 switch (candidate_p2[min_dco_index]) {
1226 case 5:
1227 wrpll_params->kdiv = 0;
1228 break;
1229 case 2:
1230 wrpll_params->kdiv = 1;
1231 break;
1232 case 3:
1233 wrpll_params->kdiv = 2;
1234 break;
1235 case 1:
1236 wrpll_params->kdiv = 3;
1237 break;
1238 default:
1239 WARN(1, "Incorrect KDiv\n");
1240 }
1241
1242 wrpll_params->qdiv_ratio = candidate_p1[min_dco_index];
1243 wrpll_params->qdiv_mode =
1244 (wrpll_params->qdiv_ratio == 1) ? 0 : 1;
1245
1246 dco_freq = candidate_p0[min_dco_index] *
1247 candidate_p1[min_dco_index] *
1248 candidate_p2[min_dco_index] * afe_clock;
1249
1250 /*
1251 * Intermediate values are in Hz.
1252 * Divide by MHz to match bsepc
1253 */
1254 wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1)));
1255 wrpll_params->dco_fraction =
1256 div_u64(((div_u64(dco_freq, 24) -
1257 wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1));
1258
1259 }
1260 }
1261
1262
1263 static bool
1264 skl_ddi_pll_select(struct intel_crtc *intel_crtc,
1265 struct intel_crtc_state *crtc_state,
1266 struct intel_encoder *intel_encoder,
1267 int clock)
1268 {
1269 struct intel_shared_dpll *pll;
1270 uint32_t ctrl1, cfgcr1, cfgcr2;
1271
1272 /*
1273 * See comment in intel_dpll_hw_state to understand why we always use 0
1274 * as the DPLL id in this function.
1275 */
1276
1277 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1278
1279 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1280 struct skl_wrpll_params wrpll_params = { 0, };
1281
1282 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1283
1284 skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params);
1285
1286 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1287 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1288 wrpll_params.dco_integer;
1289
1290 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1291 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1292 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1293 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1294 wrpll_params.central_freq;
1295 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1296 struct drm_encoder *encoder = &intel_encoder->base;
1297 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1298
1299 switch (intel_dp->link_bw) {
1300 case DP_LINK_BW_1_62:
1301 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
1302 break;
1303 case DP_LINK_BW_2_7:
1304 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
1305 break;
1306 case DP_LINK_BW_5_4:
1307 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
1308 break;
1309 }
1310
1311 cfgcr1 = cfgcr2 = 0;
1312 } else /* eDP */
1313 return true;
1314
1315 memset(&crtc_state->dpll_hw_state, 0,
1316 sizeof(crtc_state->dpll_hw_state));
1317
1318 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1319 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1320 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
1321
1322 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1323 if (pll == NULL) {
1324 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1325 pipe_name(intel_crtc->pipe));
1326 return false;
1327 }
1328
1329 /* shared DPLL id 0 is DPLL 1 */
1330 crtc_state->ddi_pll_sel = pll->id + 1;
1331
1332 return true;
1333 }
1334
1335 /* bxt clock parameters */
1336 struct bxt_clk_div {
1337 uint32_t p1;
1338 uint32_t p2;
1339 uint32_t m2_int;
1340 uint32_t m2_frac;
1341 bool m2_frac_en;
1342 uint32_t n;
1343 };
1344
1345 /* pre-calculated values for DP linkrates */
1346 static struct bxt_clk_div bxt_dp_clk_val[7] = {
1347 /* 162 */ {4, 2, 32, 1677722, 1, 1},
1348 /* 270 */ {4, 1, 27, 0, 0, 1},
1349 /* 540 */ {2, 1, 27, 0, 0, 1},
1350 /* 216 */ {3, 2, 32, 1677722, 1, 1},
1351 /* 243 */ {4, 1, 24, 1258291, 1, 1},
1352 /* 324 */ {4, 1, 32, 1677722, 1, 1},
1353 /* 432 */ {3, 1, 32, 1677722, 1, 1}
1354 };
1355
1356 static bool
1357 bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1358 struct intel_crtc_state *crtc_state,
1359 struct intel_encoder *intel_encoder,
1360 int clock)
1361 {
1362 struct intel_shared_dpll *pll;
1363 struct bxt_clk_div clk_div = {0};
1364 int vco = 0;
1365 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
1366 uint32_t dcoampovr_en_h, dco_amp, lanestagger;
1367
1368 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1369 intel_clock_t best_clock;
1370
1371 /* Calculate HDMI div */
1372 /*
1373 * FIXME: tie the following calculation into
1374 * i9xx_crtc_compute_clock
1375 */
1376 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1377 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1378 clock, pipe_name(intel_crtc->pipe));
1379 return false;
1380 }
1381
1382 clk_div.p1 = best_clock.p1;
1383 clk_div.p2 = best_clock.p2;
1384 WARN_ON(best_clock.m1 != 2);
1385 clk_div.n = best_clock.n;
1386 clk_div.m2_int = best_clock.m2 >> 22;
1387 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1388 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1389
1390 vco = best_clock.vco;
1391 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1392 intel_encoder->type == INTEL_OUTPUT_EDP) {
1393 struct drm_encoder *encoder = &intel_encoder->base;
1394 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1395
1396 switch (intel_dp->link_bw) {
1397 case DP_LINK_BW_1_62:
1398 clk_div = bxt_dp_clk_val[0];
1399 break;
1400 case DP_LINK_BW_2_7:
1401 clk_div = bxt_dp_clk_val[1];
1402 break;
1403 case DP_LINK_BW_5_4:
1404 clk_div = bxt_dp_clk_val[2];
1405 break;
1406 default:
1407 clk_div = bxt_dp_clk_val[0];
1408 DRM_ERROR("Unknown link rate\n");
1409 }
1410 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1411 }
1412
1413 dco_amp = 15;
1414 dcoampovr_en_h = 0;
1415 if (vco >= 6200000 && vco <= 6480000) {
1416 prop_coef = 4;
1417 int_coef = 9;
1418 gain_ctl = 3;
1419 targ_cnt = 8;
1420 } else if ((vco > 5400000 && vco < 6200000) ||
1421 (vco >= 4800000 && vco < 5400000)) {
1422 prop_coef = 5;
1423 int_coef = 11;
1424 gain_ctl = 3;
1425 targ_cnt = 9;
1426 if (vco >= 4800000 && vco < 5400000)
1427 dcoampovr_en_h = 1;
1428 } else if (vco == 5400000) {
1429 prop_coef = 3;
1430 int_coef = 8;
1431 gain_ctl = 1;
1432 targ_cnt = 9;
1433 } else {
1434 DRM_ERROR("Invalid VCO\n");
1435 return false;
1436 }
1437
1438 memset(&crtc_state->dpll_hw_state, 0,
1439 sizeof(crtc_state->dpll_hw_state));
1440
1441 if (clock > 270000)
1442 lanestagger = 0x18;
1443 else if (clock > 135000)
1444 lanestagger = 0x0d;
1445 else if (clock > 67000)
1446 lanestagger = 0x07;
1447 else if (clock > 33000)
1448 lanestagger = 0x04;
1449 else
1450 lanestagger = 0x02;
1451
1452 crtc_state->dpll_hw_state.ebb0 =
1453 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1454 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1455 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1456 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1457
1458 if (clk_div.m2_frac_en)
1459 crtc_state->dpll_hw_state.pll3 =
1460 PORT_PLL_M2_FRAC_ENABLE;
1461
1462 crtc_state->dpll_hw_state.pll6 =
1463 prop_coef | PORT_PLL_INT_COEFF(int_coef);
1464 crtc_state->dpll_hw_state.pll6 |=
1465 PORT_PLL_GAIN_CTL(gain_ctl);
1466
1467 crtc_state->dpll_hw_state.pll8 = targ_cnt;
1468
1469 if (dcoampovr_en_h)
1470 crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H;
1471
1472 crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp);
1473
1474 crtc_state->dpll_hw_state.pcsdw12 =
1475 LANESTAGGER_STRAP_OVRD | lanestagger;
1476
1477 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1478 if (pll == NULL) {
1479 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1480 pipe_name(intel_crtc->pipe));
1481 return false;
1482 }
1483
1484 /* shared DPLL id 0 is DPLL A */
1485 crtc_state->ddi_pll_sel = pll->id;
1486
1487 return true;
1488 }
1489
1490 /*
1491 * Tries to find a *shared* PLL for the CRTC and store it in
1492 * intel_crtc->ddi_pll_sel.
1493 *
1494 * For private DPLLs, compute_config() should do the selection for us. This
1495 * function should be folded into compute_config() eventually.
1496 */
1497 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1498 struct intel_crtc_state *crtc_state)
1499 {
1500 struct drm_device *dev = intel_crtc->base.dev;
1501 struct intel_encoder *intel_encoder =
1502 intel_ddi_get_crtc_new_encoder(crtc_state);
1503 int clock = crtc_state->port_clock;
1504
1505 if (IS_SKYLAKE(dev))
1506 return skl_ddi_pll_select(intel_crtc, crtc_state,
1507 intel_encoder, clock);
1508 else if (IS_BROXTON(dev))
1509 return bxt_ddi_pll_select(intel_crtc, crtc_state,
1510 intel_encoder, clock);
1511 else
1512 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1513 intel_encoder, clock);
1514 }
1515
1516 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1517 {
1518 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1519 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1520 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1521 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1522 int type = intel_encoder->type;
1523 uint32_t temp;
1524
1525 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1526 temp = TRANS_MSA_SYNC_CLK;
1527 switch (intel_crtc->config->pipe_bpp) {
1528 case 18:
1529 temp |= TRANS_MSA_6_BPC;
1530 break;
1531 case 24:
1532 temp |= TRANS_MSA_8_BPC;
1533 break;
1534 case 30:
1535 temp |= TRANS_MSA_10_BPC;
1536 break;
1537 case 36:
1538 temp |= TRANS_MSA_12_BPC;
1539 break;
1540 default:
1541 BUG();
1542 }
1543 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1544 }
1545 }
1546
1547 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1548 {
1549 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1550 struct drm_device *dev = crtc->dev;
1551 struct drm_i915_private *dev_priv = dev->dev_private;
1552 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1553 uint32_t temp;
1554 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1555 if (state == true)
1556 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1557 else
1558 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1559 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1560 }
1561
1562 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1563 {
1564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1565 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1566 struct drm_encoder *encoder = &intel_encoder->base;
1567 struct drm_device *dev = crtc->dev;
1568 struct drm_i915_private *dev_priv = dev->dev_private;
1569 enum pipe pipe = intel_crtc->pipe;
1570 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1571 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1572 int type = intel_encoder->type;
1573 uint32_t temp;
1574
1575 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1576 temp = TRANS_DDI_FUNC_ENABLE;
1577 temp |= TRANS_DDI_SELECT_PORT(port);
1578
1579 switch (intel_crtc->config->pipe_bpp) {
1580 case 18:
1581 temp |= TRANS_DDI_BPC_6;
1582 break;
1583 case 24:
1584 temp |= TRANS_DDI_BPC_8;
1585 break;
1586 case 30:
1587 temp |= TRANS_DDI_BPC_10;
1588 break;
1589 case 36:
1590 temp |= TRANS_DDI_BPC_12;
1591 break;
1592 default:
1593 BUG();
1594 }
1595
1596 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1597 temp |= TRANS_DDI_PVSYNC;
1598 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1599 temp |= TRANS_DDI_PHSYNC;
1600
1601 if (cpu_transcoder == TRANSCODER_EDP) {
1602 switch (pipe) {
1603 case PIPE_A:
1604 /* On Haswell, can only use the always-on power well for
1605 * eDP when not using the panel fitter, and when not
1606 * using motion blur mitigation (which we don't
1607 * support). */
1608 if (IS_HASWELL(dev) &&
1609 (intel_crtc->config->pch_pfit.enabled ||
1610 intel_crtc->config->pch_pfit.force_thru))
1611 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1612 else
1613 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1614 break;
1615 case PIPE_B:
1616 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1617 break;
1618 case PIPE_C:
1619 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1620 break;
1621 default:
1622 BUG();
1623 break;
1624 }
1625 }
1626
1627 if (type == INTEL_OUTPUT_HDMI) {
1628 if (intel_crtc->config->has_hdmi_sink)
1629 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1630 else
1631 temp |= TRANS_DDI_MODE_SELECT_DVI;
1632
1633 } else if (type == INTEL_OUTPUT_ANALOG) {
1634 temp |= TRANS_DDI_MODE_SELECT_FDI;
1635 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
1636
1637 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1638 type == INTEL_OUTPUT_EDP) {
1639 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1640
1641 if (intel_dp->is_mst) {
1642 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1643 } else
1644 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1645
1646 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1647 } else if (type == INTEL_OUTPUT_DP_MST) {
1648 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1649
1650 if (intel_dp->is_mst) {
1651 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1652 } else
1653 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1654
1655 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1656 } else {
1657 WARN(1, "Invalid encoder type %d for pipe %c\n",
1658 intel_encoder->type, pipe_name(pipe));
1659 }
1660
1661 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1662 }
1663
1664 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1665 enum transcoder cpu_transcoder)
1666 {
1667 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1668 uint32_t val = I915_READ(reg);
1669
1670 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1671 val |= TRANS_DDI_PORT_NONE;
1672 I915_WRITE(reg, val);
1673 }
1674
1675 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1676 {
1677 struct drm_device *dev = intel_connector->base.dev;
1678 struct drm_i915_private *dev_priv = dev->dev_private;
1679 struct intel_encoder *intel_encoder = intel_connector->encoder;
1680 int type = intel_connector->base.connector_type;
1681 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1682 enum pipe pipe = 0;
1683 enum transcoder cpu_transcoder;
1684 enum intel_display_power_domain power_domain;
1685 uint32_t tmp;
1686
1687 power_domain = intel_display_port_power_domain(intel_encoder);
1688 if (!intel_display_power_is_enabled(dev_priv, power_domain))
1689 return false;
1690
1691 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1692 return false;
1693
1694 if (port == PORT_A)
1695 cpu_transcoder = TRANSCODER_EDP;
1696 else
1697 cpu_transcoder = (enum transcoder) pipe;
1698
1699 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1700
1701 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1702 case TRANS_DDI_MODE_SELECT_HDMI:
1703 case TRANS_DDI_MODE_SELECT_DVI:
1704 return (type == DRM_MODE_CONNECTOR_HDMIA);
1705
1706 case TRANS_DDI_MODE_SELECT_DP_SST:
1707 if (type == DRM_MODE_CONNECTOR_eDP)
1708 return true;
1709 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1710 case TRANS_DDI_MODE_SELECT_DP_MST:
1711 /* if the transcoder is in MST state then
1712 * connector isn't connected */
1713 return false;
1714
1715 case TRANS_DDI_MODE_SELECT_FDI:
1716 return (type == DRM_MODE_CONNECTOR_VGA);
1717
1718 default:
1719 return false;
1720 }
1721 }
1722
1723 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1724 enum pipe *pipe)
1725 {
1726 struct drm_device *dev = encoder->base.dev;
1727 struct drm_i915_private *dev_priv = dev->dev_private;
1728 enum port port = intel_ddi_get_encoder_port(encoder);
1729 enum intel_display_power_domain power_domain;
1730 u32 tmp;
1731 int i;
1732
1733 power_domain = intel_display_port_power_domain(encoder);
1734 if (!intel_display_power_is_enabled(dev_priv, power_domain))
1735 return false;
1736
1737 tmp = I915_READ(DDI_BUF_CTL(port));
1738
1739 if (!(tmp & DDI_BUF_CTL_ENABLE))
1740 return false;
1741
1742 if (port == PORT_A) {
1743 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1744
1745 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1746 case TRANS_DDI_EDP_INPUT_A_ON:
1747 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1748 *pipe = PIPE_A;
1749 break;
1750 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1751 *pipe = PIPE_B;
1752 break;
1753 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1754 *pipe = PIPE_C;
1755 break;
1756 }
1757
1758 return true;
1759 } else {
1760 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1761 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1762
1763 if ((tmp & TRANS_DDI_PORT_MASK)
1764 == TRANS_DDI_SELECT_PORT(port)) {
1765 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
1766 return false;
1767
1768 *pipe = i;
1769 return true;
1770 }
1771 }
1772 }
1773
1774 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1775
1776 return false;
1777 }
1778
1779 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1780 {
1781 struct drm_crtc *crtc = &intel_crtc->base;
1782 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1783 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1784 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1785 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1786
1787 if (cpu_transcoder != TRANSCODER_EDP)
1788 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1789 TRANS_CLK_SEL_PORT(port));
1790 }
1791
1792 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1793 {
1794 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1795 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1796
1797 if (cpu_transcoder != TRANSCODER_EDP)
1798 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1799 TRANS_CLK_SEL_DISABLED);
1800 }
1801
1802 void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
1803 enum port port, int type)
1804 {
1805 struct drm_i915_private *dev_priv = dev->dev_private;
1806 const struct bxt_ddi_buf_trans *ddi_translations;
1807 u32 n_entries, i;
1808 uint32_t val;
1809
1810 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1811 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1812 ddi_translations = bxt_ddi_translations_dp;
1813 } else if (type == INTEL_OUTPUT_HDMI) {
1814 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1815 ddi_translations = bxt_ddi_translations_hdmi;
1816 } else {
1817 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1818 type);
1819 return;
1820 }
1821
1822 /* Check if default value has to be used */
1823 if (level >= n_entries ||
1824 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1825 for (i = 0; i < n_entries; i++) {
1826 if (ddi_translations[i].default_index) {
1827 level = i;
1828 break;
1829 }
1830 }
1831 }
1832
1833 /*
1834 * While we write to the group register to program all lanes at once we
1835 * can read only lane registers and we pick lanes 0/1 for that.
1836 */
1837 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1838 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
1839 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1840
1841 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
1842 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
1843 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
1844 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
1845 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
1846
1847 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
1848 val &= ~UNIQE_TRANGE_EN_METHOD;
1849 if (ddi_translations[level].enable)
1850 val |= UNIQE_TRANGE_EN_METHOD;
1851 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
1852
1853 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
1854 val &= ~DE_EMPHASIS;
1855 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
1856 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
1857
1858 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1859 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
1860 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1861 }
1862
1863 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1864 {
1865 struct drm_encoder *encoder = &intel_encoder->base;
1866 struct drm_device *dev = encoder->dev;
1867 struct drm_i915_private *dev_priv = dev->dev_private;
1868 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1869 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1870 int type = intel_encoder->type;
1871 int hdmi_level;
1872
1873 if (type == INTEL_OUTPUT_EDP) {
1874 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1875 intel_edp_panel_on(intel_dp);
1876 }
1877
1878 if (IS_SKYLAKE(dev)) {
1879 uint32_t dpll = crtc->config->ddi_pll_sel;
1880 uint32_t val;
1881
1882 /*
1883 * DPLL0 is used for eDP and is the only "private" DPLL (as
1884 * opposed to shared) on SKL
1885 */
1886 if (type == INTEL_OUTPUT_EDP) {
1887 WARN_ON(dpll != SKL_DPLL0);
1888
1889 val = I915_READ(DPLL_CTRL1);
1890
1891 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
1892 DPLL_CTRL1_SSC(dpll) |
1893 DPLL_CTRL1_LINK_RATE_MASK(dpll));
1894 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
1895
1896 I915_WRITE(DPLL_CTRL1, val);
1897 POSTING_READ(DPLL_CTRL1);
1898 }
1899
1900 /* DDI -> PLL mapping */
1901 val = I915_READ(DPLL_CTRL2);
1902
1903 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1904 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1905 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
1906 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1907
1908 I915_WRITE(DPLL_CTRL2, val);
1909
1910 } else if (INTEL_INFO(dev)->gen < 9) {
1911 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
1912 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
1913 }
1914
1915 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1916 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1917
1918 intel_ddi_init_dp_buf_reg(intel_encoder);
1919
1920 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1921 intel_dp_start_link_train(intel_dp);
1922 intel_dp_complete_link_train(intel_dp);
1923 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
1924 intel_dp_stop_link_train(intel_dp);
1925 } else if (type == INTEL_OUTPUT_HDMI) {
1926 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1927
1928 if (IS_BROXTON(dev)) {
1929 hdmi_level = dev_priv->vbt.
1930 ddi_port_info[port].hdmi_level_shift;
1931 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
1932 INTEL_OUTPUT_HDMI);
1933 }
1934 intel_hdmi->set_infoframes(encoder,
1935 crtc->config->has_hdmi_sink,
1936 &crtc->config->base.adjusted_mode);
1937 }
1938 }
1939
1940 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1941 {
1942 struct drm_encoder *encoder = &intel_encoder->base;
1943 struct drm_device *dev = encoder->dev;
1944 struct drm_i915_private *dev_priv = dev->dev_private;
1945 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1946 int type = intel_encoder->type;
1947 uint32_t val;
1948 bool wait = false;
1949
1950 val = I915_READ(DDI_BUF_CTL(port));
1951 if (val & DDI_BUF_CTL_ENABLE) {
1952 val &= ~DDI_BUF_CTL_ENABLE;
1953 I915_WRITE(DDI_BUF_CTL(port), val);
1954 wait = true;
1955 }
1956
1957 val = I915_READ(DP_TP_CTL(port));
1958 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1959 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1960 I915_WRITE(DP_TP_CTL(port), val);
1961
1962 if (wait)
1963 intel_wait_ddi_buf_idle(dev_priv, port);
1964
1965 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1966 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1967 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1968 intel_edp_panel_vdd_on(intel_dp);
1969 intel_edp_panel_off(intel_dp);
1970 }
1971
1972 if (IS_SKYLAKE(dev))
1973 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1974 DPLL_CTRL2_DDI_CLK_OFF(port)));
1975 else if (INTEL_INFO(dev)->gen < 9)
1976 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1977 }
1978
1979 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1980 {
1981 struct drm_encoder *encoder = &intel_encoder->base;
1982 struct drm_crtc *crtc = encoder->crtc;
1983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1984 struct drm_device *dev = encoder->dev;
1985 struct drm_i915_private *dev_priv = dev->dev_private;
1986 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1987 int type = intel_encoder->type;
1988
1989 if (type == INTEL_OUTPUT_HDMI) {
1990 struct intel_digital_port *intel_dig_port =
1991 enc_to_dig_port(encoder);
1992
1993 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1994 * are ignored so nothing special needs to be done besides
1995 * enabling the port.
1996 */
1997 I915_WRITE(DDI_BUF_CTL(port),
1998 intel_dig_port->saved_port_bits |
1999 DDI_BUF_CTL_ENABLE);
2000 } else if (type == INTEL_OUTPUT_EDP) {
2001 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2002
2003 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
2004 intel_dp_stop_link_train(intel_dp);
2005
2006 intel_edp_backlight_on(intel_dp);
2007 intel_psr_enable(intel_dp);
2008 intel_edp_drrs_enable(intel_dp);
2009 }
2010
2011 if (intel_crtc->config->has_audio) {
2012 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
2013 intel_audio_codec_enable(intel_encoder);
2014 }
2015 }
2016
2017 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
2018 {
2019 struct drm_encoder *encoder = &intel_encoder->base;
2020 struct drm_crtc *crtc = encoder->crtc;
2021 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2022 int type = intel_encoder->type;
2023 struct drm_device *dev = encoder->dev;
2024 struct drm_i915_private *dev_priv = dev->dev_private;
2025
2026 if (intel_crtc->config->has_audio) {
2027 intel_audio_codec_disable(intel_encoder);
2028 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
2029 }
2030
2031 if (type == INTEL_OUTPUT_EDP) {
2032 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2033
2034 intel_edp_drrs_disable(intel_dp);
2035 intel_psr_disable(intel_dp);
2036 intel_edp_backlight_off(intel_dp);
2037 }
2038 }
2039
2040 static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
2041 struct intel_shared_dpll *pll)
2042 {
2043 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
2044 POSTING_READ(WRPLL_CTL(pll->id));
2045 udelay(20);
2046 }
2047
2048 static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
2049 struct intel_shared_dpll *pll)
2050 {
2051 uint32_t val;
2052
2053 val = I915_READ(WRPLL_CTL(pll->id));
2054 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2055 POSTING_READ(WRPLL_CTL(pll->id));
2056 }
2057
2058 static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2059 struct intel_shared_dpll *pll,
2060 struct intel_dpll_hw_state *hw_state)
2061 {
2062 uint32_t val;
2063
2064 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2065 return false;
2066
2067 val = I915_READ(WRPLL_CTL(pll->id));
2068 hw_state->wrpll = val;
2069
2070 return val & WRPLL_PLL_ENABLE;
2071 }
2072
2073 static const char * const hsw_ddi_pll_names[] = {
2074 "WRPLL 1",
2075 "WRPLL 2",
2076 };
2077
2078 static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
2079 {
2080 int i;
2081
2082 dev_priv->num_shared_dpll = 2;
2083
2084 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2085 dev_priv->shared_dplls[i].id = i;
2086 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
2087 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
2088 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
2089 dev_priv->shared_dplls[i].get_hw_state =
2090 hsw_ddi_pll_get_hw_state;
2091 }
2092 }
2093
2094 static const char * const skl_ddi_pll_names[] = {
2095 "DPLL 1",
2096 "DPLL 2",
2097 "DPLL 3",
2098 };
2099
2100 struct skl_dpll_regs {
2101 u32 ctl, cfgcr1, cfgcr2;
2102 };
2103
2104 /* this array is indexed by the *shared* pll id */
2105 static const struct skl_dpll_regs skl_dpll_regs[3] = {
2106 {
2107 /* DPLL 1 */
2108 .ctl = LCPLL2_CTL,
2109 .cfgcr1 = DPLL1_CFGCR1,
2110 .cfgcr2 = DPLL1_CFGCR2,
2111 },
2112 {
2113 /* DPLL 2 */
2114 .ctl = WRPLL_CTL1,
2115 .cfgcr1 = DPLL2_CFGCR1,
2116 .cfgcr2 = DPLL2_CFGCR2,
2117 },
2118 {
2119 /* DPLL 3 */
2120 .ctl = WRPLL_CTL2,
2121 .cfgcr1 = DPLL3_CFGCR1,
2122 .cfgcr2 = DPLL3_CFGCR2,
2123 },
2124 };
2125
2126 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2127 struct intel_shared_dpll *pll)
2128 {
2129 uint32_t val;
2130 unsigned int dpll;
2131 const struct skl_dpll_regs *regs = skl_dpll_regs;
2132
2133 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2134 dpll = pll->id + 1;
2135
2136 val = I915_READ(DPLL_CTRL1);
2137
2138 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
2139 DPLL_CTRL1_LINK_RATE_MASK(dpll));
2140 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2141
2142 I915_WRITE(DPLL_CTRL1, val);
2143 POSTING_READ(DPLL_CTRL1);
2144
2145 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2146 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2147 POSTING_READ(regs[pll->id].cfgcr1);
2148 POSTING_READ(regs[pll->id].cfgcr2);
2149
2150 /* the enable bit is always bit 31 */
2151 I915_WRITE(regs[pll->id].ctl,
2152 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2153
2154 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2155 DRM_ERROR("DPLL %d not locked\n", dpll);
2156 }
2157
2158 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2159 struct intel_shared_dpll *pll)
2160 {
2161 const struct skl_dpll_regs *regs = skl_dpll_regs;
2162
2163 /* the enable bit is always bit 31 */
2164 I915_WRITE(regs[pll->id].ctl,
2165 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2166 POSTING_READ(regs[pll->id].ctl);
2167 }
2168
2169 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2170 struct intel_shared_dpll *pll,
2171 struct intel_dpll_hw_state *hw_state)
2172 {
2173 uint32_t val;
2174 unsigned int dpll;
2175 const struct skl_dpll_regs *regs = skl_dpll_regs;
2176
2177 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2178 return false;
2179
2180 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2181 dpll = pll->id + 1;
2182
2183 val = I915_READ(regs[pll->id].ctl);
2184 if (!(val & LCPLL_PLL_ENABLE))
2185 return false;
2186
2187 val = I915_READ(DPLL_CTRL1);
2188 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2189
2190 /* avoid reading back stale values if HDMI mode is not enabled */
2191 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2192 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2193 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2194 }
2195
2196 return true;
2197 }
2198
2199 static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2200 {
2201 int i;
2202
2203 dev_priv->num_shared_dpll = 3;
2204
2205 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2206 dev_priv->shared_dplls[i].id = i;
2207 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2208 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2209 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2210 dev_priv->shared_dplls[i].get_hw_state =
2211 skl_ddi_pll_get_hw_state;
2212 }
2213 }
2214
2215 static void broxton_phy_init(struct drm_i915_private *dev_priv,
2216 enum dpio_phy phy)
2217 {
2218 enum port port;
2219 uint32_t val;
2220
2221 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2222 val |= GT_DISPLAY_POWER_ON(phy);
2223 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2224
2225 /* Considering 10ms timeout until BSpec is updated */
2226 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2227 DRM_ERROR("timeout during PHY%d power on\n", phy);
2228
2229 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2230 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2231 int lane;
2232
2233 for (lane = 0; lane < 4; lane++) {
2234 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2235 /*
2236 * Note that on CHV this flag is called UPAR, but has
2237 * the same function.
2238 */
2239 val &= ~LATENCY_OPTIM;
2240 if (lane != 1)
2241 val |= LATENCY_OPTIM;
2242
2243 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2244 }
2245 }
2246
2247 /* Program PLL Rcomp code offset */
2248 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2249 val &= ~IREF0RC_OFFSET_MASK;
2250 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2251 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2252
2253 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2254 val &= ~IREF1RC_OFFSET_MASK;
2255 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2256 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2257
2258 /* Program power gating */
2259 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2260 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2261 SUS_CLK_CONFIG;
2262 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2263
2264 if (phy == DPIO_PHY0) {
2265 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2266 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2267 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2268 }
2269
2270 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2271 val &= ~OCL2_LDOFUSE_PWR_DIS;
2272 /*
2273 * On PHY1 disable power on the second channel, since no port is
2274 * connected there. On PHY0 both channels have a port, so leave it
2275 * enabled.
2276 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2277 * power down the second channel on PHY0 as well.
2278 */
2279 if (phy == DPIO_PHY1)
2280 val |= OCL2_LDOFUSE_PWR_DIS;
2281 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2282
2283 if (phy == DPIO_PHY0) {
2284 uint32_t grc_code;
2285 /*
2286 * PHY0 isn't connected to an RCOMP resistor so copy over
2287 * the corresponding calibrated value from PHY1, and disable
2288 * the automatic calibration on PHY0.
2289 */
2290 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2291 10))
2292 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2293
2294 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2295 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2296 grc_code = val << GRC_CODE_FAST_SHIFT |
2297 val << GRC_CODE_SLOW_SHIFT |
2298 val;
2299 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2300
2301 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2302 val |= GRC_DIS | GRC_RDY_OVRD;
2303 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2304 }
2305
2306 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2307 val |= COMMON_RESET_DIS;
2308 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2309 }
2310
2311 void broxton_ddi_phy_init(struct drm_device *dev)
2312 {
2313 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2314 broxton_phy_init(dev->dev_private, DPIO_PHY1);
2315 broxton_phy_init(dev->dev_private, DPIO_PHY0);
2316 }
2317
2318 static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2319 enum dpio_phy phy)
2320 {
2321 uint32_t val;
2322
2323 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2324 val &= ~COMMON_RESET_DIS;
2325 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2326 }
2327
2328 void broxton_ddi_phy_uninit(struct drm_device *dev)
2329 {
2330 struct drm_i915_private *dev_priv = dev->dev_private;
2331
2332 broxton_phy_uninit(dev_priv, DPIO_PHY1);
2333 broxton_phy_uninit(dev_priv, DPIO_PHY0);
2334
2335 /* FIXME: do this in broxton_phy_uninit per phy */
2336 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2337 }
2338
2339 static const char * const bxt_ddi_pll_names[] = {
2340 "PORT PLL A",
2341 "PORT PLL B",
2342 "PORT PLL C",
2343 };
2344
2345 static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2346 struct intel_shared_dpll *pll)
2347 {
2348 uint32_t temp;
2349 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2350
2351 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2352 temp &= ~PORT_PLL_REF_SEL;
2353 /* Non-SSC reference */
2354 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2355
2356 /* Disable 10 bit clock */
2357 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2358 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2359 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2360
2361 /* Write P1 & P2 */
2362 temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2363 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2364 temp |= pll->config.hw_state.ebb0;
2365 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2366
2367 /* Write M2 integer */
2368 temp = I915_READ(BXT_PORT_PLL(port, 0));
2369 temp &= ~PORT_PLL_M2_MASK;
2370 temp |= pll->config.hw_state.pll0;
2371 I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2372
2373 /* Write N */
2374 temp = I915_READ(BXT_PORT_PLL(port, 1));
2375 temp &= ~PORT_PLL_N_MASK;
2376 temp |= pll->config.hw_state.pll1;
2377 I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2378
2379 /* Write M2 fraction */
2380 temp = I915_READ(BXT_PORT_PLL(port, 2));
2381 temp &= ~PORT_PLL_M2_FRAC_MASK;
2382 temp |= pll->config.hw_state.pll2;
2383 I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2384
2385 /* Write M2 fraction enable */
2386 temp = I915_READ(BXT_PORT_PLL(port, 3));
2387 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2388 temp |= pll->config.hw_state.pll3;
2389 I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2390
2391 /* Write coeff */
2392 temp = I915_READ(BXT_PORT_PLL(port, 6));
2393 temp &= ~PORT_PLL_PROP_COEFF_MASK;
2394 temp &= ~PORT_PLL_INT_COEFF_MASK;
2395 temp &= ~PORT_PLL_GAIN_CTL_MASK;
2396 temp |= pll->config.hw_state.pll6;
2397 I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2398
2399 /* Write calibration val */
2400 temp = I915_READ(BXT_PORT_PLL(port, 8));
2401 temp &= ~PORT_PLL_TARGET_CNT_MASK;
2402 temp |= pll->config.hw_state.pll8;
2403 I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2404
2405 temp = I915_READ(BXT_PORT_PLL(port, 9));
2406 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
2407 temp |= (5 << 1);
2408 I915_WRITE(BXT_PORT_PLL(port, 9), temp);
2409
2410 temp = I915_READ(BXT_PORT_PLL(port, 10));
2411 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
2412 temp &= ~PORT_PLL_DCO_AMP_MASK;
2413 temp |= pll->config.hw_state.pll10;
2414 I915_WRITE(BXT_PORT_PLL(port, 10), temp);
2415
2416 /* Recalibrate with new settings */
2417 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2418 temp |= PORT_PLL_RECALIBRATE;
2419 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2420 /* Enable 10 bit clock */
2421 temp |= PORT_PLL_10BIT_CLK_ENABLE;
2422 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2423
2424 /* Enable PLL */
2425 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2426 temp |= PORT_PLL_ENABLE;
2427 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2428 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2429
2430 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2431 PORT_PLL_LOCK), 200))
2432 DRM_ERROR("PLL %d not locked\n", port);
2433
2434 /*
2435 * While we write to the group register to program all lanes at once we
2436 * can read only lane registers and we pick lanes 0/1 for that.
2437 */
2438 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2439 temp &= ~LANE_STAGGER_MASK;
2440 temp &= ~LANESTAGGER_STRAP_OVRD;
2441 temp |= pll->config.hw_state.pcsdw12;
2442 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2443 }
2444
2445 static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2446 struct intel_shared_dpll *pll)
2447 {
2448 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2449 uint32_t temp;
2450
2451 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2452 temp &= ~PORT_PLL_ENABLE;
2453 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2454 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2455 }
2456
2457 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2458 struct intel_shared_dpll *pll,
2459 struct intel_dpll_hw_state *hw_state)
2460 {
2461 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2462 uint32_t val;
2463
2464 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2465 return false;
2466
2467 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2468 if (!(val & PORT_PLL_ENABLE))
2469 return false;
2470
2471 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
2472 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
2473 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
2474 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
2475 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
2476 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
2477 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
2478 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
2479 /*
2480 * While we write to the group register to program all lanes at once we
2481 * can read only lane registers. We configure all lanes the same way, so
2482 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2483 */
2484 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2485 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port) != hw_state->pcsdw12))
2486 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2487 hw_state->pcsdw12,
2488 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
2489
2490 return true;
2491 }
2492
2493 static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2494 {
2495 int i;
2496
2497 dev_priv->num_shared_dpll = 3;
2498
2499 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2500 dev_priv->shared_dplls[i].id = i;
2501 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
2502 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
2503 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
2504 dev_priv->shared_dplls[i].get_hw_state =
2505 bxt_ddi_pll_get_hw_state;
2506 }
2507 }
2508
2509 void intel_ddi_pll_init(struct drm_device *dev)
2510 {
2511 struct drm_i915_private *dev_priv = dev->dev_private;
2512 uint32_t val = I915_READ(LCPLL_CTL);
2513 int cdclk_freq;
2514
2515 if (IS_SKYLAKE(dev))
2516 skl_shared_dplls_init(dev_priv);
2517 else if (IS_BROXTON(dev))
2518 bxt_shared_dplls_init(dev_priv);
2519 else
2520 hsw_shared_dplls_init(dev_priv);
2521
2522 cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
2523 DRM_DEBUG_KMS("CDCLK running at %dKHz\n", cdclk_freq);
2524
2525 if (IS_SKYLAKE(dev)) {
2526 dev_priv->skl_boot_cdclk = cdclk_freq;
2527 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
2528 DRM_ERROR("LCPLL1 is disabled\n");
2529 else
2530 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
2531 } else if (IS_BROXTON(dev)) {
2532 broxton_init_cdclk(dev);
2533 broxton_ddi_phy_init(dev);
2534 } else {
2535 /*
2536 * The LCPLL register should be turned on by the BIOS. For now
2537 * let's just check its state and print errors in case
2538 * something is wrong. Don't even try to turn it on.
2539 */
2540
2541 if (val & LCPLL_CD_SOURCE_FCLK)
2542 DRM_ERROR("CDCLK source is not LCPLL\n");
2543
2544 if (val & LCPLL_PLL_DISABLE)
2545 DRM_ERROR("LCPLL is disabled\n");
2546 }
2547 }
2548
2549 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
2550 {
2551 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2552 struct intel_dp *intel_dp = &intel_dig_port->dp;
2553 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
2554 enum port port = intel_dig_port->port;
2555 uint32_t val;
2556 bool wait = false;
2557
2558 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2559 val = I915_READ(DDI_BUF_CTL(port));
2560 if (val & DDI_BUF_CTL_ENABLE) {
2561 val &= ~DDI_BUF_CTL_ENABLE;
2562 I915_WRITE(DDI_BUF_CTL(port), val);
2563 wait = true;
2564 }
2565
2566 val = I915_READ(DP_TP_CTL(port));
2567 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2568 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2569 I915_WRITE(DP_TP_CTL(port), val);
2570 POSTING_READ(DP_TP_CTL(port));
2571
2572 if (wait)
2573 intel_wait_ddi_buf_idle(dev_priv, port);
2574 }
2575
2576 val = DP_TP_CTL_ENABLE |
2577 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
2578 if (intel_dp->is_mst)
2579 val |= DP_TP_CTL_MODE_MST;
2580 else {
2581 val |= DP_TP_CTL_MODE_SST;
2582 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2583 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2584 }
2585 I915_WRITE(DP_TP_CTL(port), val);
2586 POSTING_READ(DP_TP_CTL(port));
2587
2588 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2589 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2590 POSTING_READ(DDI_BUF_CTL(port));
2591
2592 udelay(600);
2593 }
2594
2595 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
2596 {
2597 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2598 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2599 uint32_t val;
2600
2601 intel_ddi_post_disable(intel_encoder);
2602
2603 val = I915_READ(_FDI_RXA_CTL);
2604 val &= ~FDI_RX_ENABLE;
2605 I915_WRITE(_FDI_RXA_CTL, val);
2606
2607 val = I915_READ(_FDI_RXA_MISC);
2608 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2609 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2610 I915_WRITE(_FDI_RXA_MISC, val);
2611
2612 val = I915_READ(_FDI_RXA_CTL);
2613 val &= ~FDI_PCDCLK;
2614 I915_WRITE(_FDI_RXA_CTL, val);
2615
2616 val = I915_READ(_FDI_RXA_CTL);
2617 val &= ~FDI_RX_PLL_ENABLE;
2618 I915_WRITE(_FDI_RXA_CTL, val);
2619 }
2620
2621 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
2622 {
2623 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base);
2624 int type = intel_dig_port->base.type;
2625
2626 if (type != INTEL_OUTPUT_DISPLAYPORT &&
2627 type != INTEL_OUTPUT_EDP &&
2628 type != INTEL_OUTPUT_UNKNOWN) {
2629 return;
2630 }
2631
2632 intel_dp_hot_plug(intel_encoder);
2633 }
2634
2635 void intel_ddi_get_config(struct intel_encoder *encoder,
2636 struct intel_crtc_state *pipe_config)
2637 {
2638 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
2639 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2640 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2641 struct intel_hdmi *intel_hdmi;
2642 u32 temp, flags = 0;
2643
2644 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2645 if (temp & TRANS_DDI_PHSYNC)
2646 flags |= DRM_MODE_FLAG_PHSYNC;
2647 else
2648 flags |= DRM_MODE_FLAG_NHSYNC;
2649 if (temp & TRANS_DDI_PVSYNC)
2650 flags |= DRM_MODE_FLAG_PVSYNC;
2651 else
2652 flags |= DRM_MODE_FLAG_NVSYNC;
2653
2654 pipe_config->base.adjusted_mode.flags |= flags;
2655
2656 switch (temp & TRANS_DDI_BPC_MASK) {
2657 case TRANS_DDI_BPC_6:
2658 pipe_config->pipe_bpp = 18;
2659 break;
2660 case TRANS_DDI_BPC_8:
2661 pipe_config->pipe_bpp = 24;
2662 break;
2663 case TRANS_DDI_BPC_10:
2664 pipe_config->pipe_bpp = 30;
2665 break;
2666 case TRANS_DDI_BPC_12:
2667 pipe_config->pipe_bpp = 36;
2668 break;
2669 default:
2670 break;
2671 }
2672
2673 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2674 case TRANS_DDI_MODE_SELECT_HDMI:
2675 pipe_config->has_hdmi_sink = true;
2676 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2677
2678 if (intel_hdmi->infoframe_enabled(&encoder->base))
2679 pipe_config->has_infoframe = true;
2680 break;
2681 case TRANS_DDI_MODE_SELECT_DVI:
2682 case TRANS_DDI_MODE_SELECT_FDI:
2683 break;
2684 case TRANS_DDI_MODE_SELECT_DP_SST:
2685 case TRANS_DDI_MODE_SELECT_DP_MST:
2686 pipe_config->has_dp_encoder = true;
2687 intel_dp_get_m_n(intel_crtc, pipe_config);
2688 break;
2689 default:
2690 break;
2691 }
2692
2693 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2694 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2695 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2696 pipe_config->has_audio = true;
2697 }
2698
2699 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
2700 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2701 /*
2702 * This is a big fat ugly hack.
2703 *
2704 * Some machines in UEFI boot mode provide us a VBT that has 18
2705 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2706 * unknown we fail to light up. Yet the same BIOS boots up with
2707 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2708 * max, not what it tells us to use.
2709 *
2710 * Note: This will still be broken if the eDP panel is not lit
2711 * up by the BIOS, and thus we can't get the mode at module
2712 * load.
2713 */
2714 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2715 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2716 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2717 }
2718
2719 intel_ddi_clock_get(encoder, pipe_config);
2720 }
2721
2722 static void intel_ddi_destroy(struct drm_encoder *encoder)
2723 {
2724 /* HDMI has nothing special to destroy, so we can go with this. */
2725 intel_dp_encoder_destroy(encoder);
2726 }
2727
2728 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
2729 struct intel_crtc_state *pipe_config)
2730 {
2731 int type = encoder->type;
2732 int port = intel_ddi_get_encoder_port(encoder);
2733
2734 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
2735
2736 if (port == PORT_A)
2737 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2738
2739 if (type == INTEL_OUTPUT_HDMI)
2740 return intel_hdmi_compute_config(encoder, pipe_config);
2741 else
2742 return intel_dp_compute_config(encoder, pipe_config);
2743 }
2744
2745 static const struct drm_encoder_funcs intel_ddi_funcs = {
2746 .destroy = intel_ddi_destroy,
2747 };
2748
2749 static struct intel_connector *
2750 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2751 {
2752 struct intel_connector *connector;
2753 enum port port = intel_dig_port->port;
2754
2755 connector = intel_connector_alloc();
2756 if (!connector)
2757 return NULL;
2758
2759 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2760 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2761 kfree(connector);
2762 return NULL;
2763 }
2764
2765 return connector;
2766 }
2767
2768 static struct intel_connector *
2769 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2770 {
2771 struct intel_connector *connector;
2772 enum port port = intel_dig_port->port;
2773
2774 connector = intel_connector_alloc();
2775 if (!connector)
2776 return NULL;
2777
2778 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2779 intel_hdmi_init_connector(intel_dig_port, connector);
2780
2781 return connector;
2782 }
2783
2784 void intel_ddi_init(struct drm_device *dev, enum port port)
2785 {
2786 struct drm_i915_private *dev_priv = dev->dev_private;
2787 struct intel_digital_port *intel_dig_port;
2788 struct intel_encoder *intel_encoder;
2789 struct drm_encoder *encoder;
2790 bool init_hdmi, init_dp;
2791
2792 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2793 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2794 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2795 if (!init_dp && !init_hdmi) {
2796 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
2797 port_name(port));
2798 init_hdmi = true;
2799 init_dp = true;
2800 }
2801
2802 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2803 if (!intel_dig_port)
2804 return;
2805
2806 intel_encoder = &intel_dig_port->base;
2807 encoder = &intel_encoder->base;
2808
2809 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
2810 DRM_MODE_ENCODER_TMDS);
2811
2812 intel_encoder->compute_config = intel_ddi_compute_config;
2813 intel_encoder->enable = intel_enable_ddi;
2814 intel_encoder->pre_enable = intel_ddi_pre_enable;
2815 intel_encoder->disable = intel_disable_ddi;
2816 intel_encoder->post_disable = intel_ddi_post_disable;
2817 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2818 intel_encoder->get_config = intel_ddi_get_config;
2819
2820 intel_dig_port->port = port;
2821 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2822 (DDI_BUF_PORT_REVERSAL |
2823 DDI_A_4_LANES);
2824
2825 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
2826 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2827 intel_encoder->cloneable = 0;
2828 intel_encoder->hot_plug = intel_ddi_hot_plug;
2829
2830 if (init_dp) {
2831 if (!intel_ddi_init_dp_connector(intel_dig_port))
2832 goto err;
2833
2834 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2835 dev_priv->hpd_irq_port[port] = intel_dig_port;
2836 }
2837
2838 /* In theory we don't need the encoder->type check, but leave it just in
2839 * case we have some really bad VBTs... */
2840 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2841 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2842 goto err;
2843 }
2844
2845 return;
2846
2847 err:
2848 drm_encoder_cleanup(encoder);
2849 kfree(intel_dig_port);
2850 }
Linux kernel - Deliverables
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