2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 struct ddi_buf_trans
{
32 u32 trans1
; /* balance leg enable, de-emph level */
33 u32 trans2
; /* vref sel, vswing */
34 u8 i_boost
; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
37 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
41 static const struct ddi_buf_trans hsw_ddi_translations_dp
[] = {
42 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
53 static const struct ddi_buf_trans hsw_ddi_translations_fdi
[] = {
54 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
65 static const struct ddi_buf_trans hsw_ddi_translations_hdmi
[] = {
66 /* Idx NT mV d T mV d db */
67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
81 static const struct ddi_buf_trans bdw_ddi_translations_edp
[] = {
82 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
93 static const struct ddi_buf_trans bdw_ddi_translations_dp
[] = {
94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
105 static const struct ddi_buf_trans bdw_ddi_translations_fdi
[] = {
106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
117 static const struct ddi_buf_trans bdw_ddi_translations_hdmi
[] = {
118 /* Idx NT mV d T mV df db */
119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
131 /* Skylake H, S, and Skylake Y with 0.95V VccIO */
132 static const struct ddi_buf_trans skl_ddi_translations_dp
[] = {
133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
136 { 0x00009010, 0x000000C7, 0x0 },
137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
139 { 0x00007011, 0x000000C7, 0x0 },
140 { 0x00002016, 0x000000DF, 0x0 },
141 { 0x00005012, 0x000000C7, 0x0 },
145 static const struct ddi_buf_trans skl_u_ddi_translations_dp
[] = {
146 { 0x00002016, 0x000000A2, 0x0 },
147 { 0x00005012, 0x00000088, 0x0 },
148 { 0x00007011, 0x00000087, 0x0 },
149 { 0x80009010, 0x000000C7, 0x1 }, /* Uses I_boost */
150 { 0x00002016, 0x0000009D, 0x0 },
151 { 0x00005012, 0x000000C7, 0x0 },
152 { 0x00007011, 0x000000C7, 0x0 },
153 { 0x00002016, 0x00000088, 0x0 },
154 { 0x00005012, 0x000000C7, 0x0 },
157 /* Skylake Y with 0.85V VccIO */
158 static const struct ddi_buf_trans skl_y_085v_ddi_translations_dp
[] = {
159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
161 { 0x00007011, 0x00000087, 0x0 },
162 { 0x80009010, 0x000000C7, 0x1 }, /* Uses I_boost */
163 { 0x00000018, 0x0000009D, 0x0 },
164 { 0x00005012, 0x000000C7, 0x0 },
165 { 0x00007011, 0x000000C7, 0x0 },
166 { 0x00000018, 0x00000088, 0x0 },
167 { 0x00005012, 0x000000C7, 0x0 },
171 * Skylake H and S, and Skylake Y with 0.95V VccIO
172 * eDP 1.4 low vswing translation parameters
174 static const struct ddi_buf_trans skl_ddi_translations_edp
[] = {
175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
189 * eDP 1.4 low vswing translation parameters
191 static const struct ddi_buf_trans skl_u_ddi_translations_edp
[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
205 * Skylake Y with 0.95V VccIO
206 * eDP 1.4 low vswing translation parameters
208 static const struct ddi_buf_trans skl_y_085v_ddi_translations_edp
[] = {
209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
221 /* Skylake H, S and U, and Skylake Y with 0.95V VccIO */
222 static const struct ddi_buf_trans skl_ddi_translations_hdmi
[] = {
223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
229 { 0x00006012, 0x00000087, 0x0 },
230 { 0x00000018, 0x000000DF, 0x0 },
231 { 0x00003015, 0x00000087, 0x0 }, /* Default */
232 { 0x00003015, 0x000000C7, 0x0 },
233 { 0x00000018, 0x000000C7, 0x0 },
236 /* Skylake Y with 0.85V VccIO */
237 static const struct ddi_buf_trans skl_y_085v_ddi_translations_hdmi
[] = {
238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
240 { 0x00007011, 0x00000084, 0x0 },
241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
244 { 0x00006013, 0x000000C7, 0x0 },
245 { 0x00000018, 0x0000008A, 0x0 },
246 { 0x00003015, 0x000000C7, 0x0 }, /* Default */
247 { 0x80003015, 0x000000C7, 0x7 }, /* Uses I_boost */
248 { 0x00000018, 0x000000C7, 0x0 },
251 struct bxt_ddi_buf_trans
{
252 u32 margin
; /* swing value */
253 u32 scale
; /* scale value */
254 u32 enable
; /* scale enable */
256 bool default_index
; /* true if the entry represents default value */
259 /* BSpec does not define separate vswing/pre-emphasis values for eDP.
260 * Using DP values for eDP as well.
262 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp
[] = {
263 /* Idx NT mV diff db */
264 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
265 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
266 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
267 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
268 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
269 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
270 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
271 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
272 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
273 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
276 /* BSpec has 2 recommended values - entries 0 and 8.
277 * Using the entry with higher vswing.
279 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi
[] = {
280 /* Idx NT mV diff db */
281 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
282 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
283 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
284 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
285 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
286 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
287 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
288 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
289 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
290 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
293 static void bxt_ddi_vswing_sequence(struct drm_device
*dev
, u32 level
,
294 enum port port
, int type
);
296 static void ddi_get_encoder_port(struct intel_encoder
*intel_encoder
,
297 struct intel_digital_port
**dig_port
,
300 struct drm_encoder
*encoder
= &intel_encoder
->base
;
301 int type
= intel_encoder
->type
;
303 if (type
== INTEL_OUTPUT_DP_MST
) {
304 *dig_port
= enc_to_mst(encoder
)->primary
;
305 *port
= (*dig_port
)->port
;
306 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
||
307 type
== INTEL_OUTPUT_HDMI
|| type
== INTEL_OUTPUT_UNKNOWN
) {
308 *dig_port
= enc_to_dig_port(encoder
);
309 *port
= (*dig_port
)->port
;
310 } else if (type
== INTEL_OUTPUT_ANALOG
) {
314 DRM_ERROR("Invalid DDI encoder type %d\n", type
);
319 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
)
321 struct intel_digital_port
*dig_port
;
324 ddi_get_encoder_port(intel_encoder
, &dig_port
, &port
);
330 intel_dig_port_supports_hdmi(const struct intel_digital_port
*intel_dig_port
)
332 return intel_dig_port
->hdmi
.hdmi_reg
;
335 static const struct ddi_buf_trans
*skl_get_buf_trans_dp(struct drm_device
*dev
,
338 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
339 const struct ddi_buf_trans
*ddi_translations
;
340 static int is_095v
= -1;
343 u32 spr1
= I915_READ(UAIMI_SPR1
);
345 is_095v
= spr1
& SKL_VCCIO_MASK
;
348 if (IS_SKL_ULX(dev
) && !is_095v
) {
349 ddi_translations
= skl_y_085v_ddi_translations_dp
;
350 *n_entries
= ARRAY_SIZE(skl_y_085v_ddi_translations_dp
);
351 } else if (IS_SKL_ULT(dev
)) {
352 ddi_translations
= skl_u_ddi_translations_dp
;
353 *n_entries
= ARRAY_SIZE(skl_u_ddi_translations_dp
);
355 ddi_translations
= skl_ddi_translations_dp
;
356 *n_entries
= ARRAY_SIZE(skl_ddi_translations_dp
);
359 return ddi_translations
;
362 static const struct ddi_buf_trans
*skl_get_buf_trans_edp(struct drm_device
*dev
,
365 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
366 const struct ddi_buf_trans
*ddi_translations
;
367 static int is_095v
= -1;
370 u32 spr1
= I915_READ(UAIMI_SPR1
);
372 is_095v
= spr1
& SKL_VCCIO_MASK
;
375 if (IS_SKL_ULX(dev
) && !is_095v
) {
376 if (dev_priv
->edp_low_vswing
) {
377 ddi_translations
= skl_y_085v_ddi_translations_edp
;
379 ARRAY_SIZE(skl_y_085v_ddi_translations_edp
);
381 ddi_translations
= skl_y_085v_ddi_translations_dp
;
383 ARRAY_SIZE(skl_y_085v_ddi_translations_dp
);
385 } else if (IS_SKL_ULT(dev
)) {
386 if (dev_priv
->edp_low_vswing
) {
387 ddi_translations
= skl_u_ddi_translations_edp
;
388 *n_entries
= ARRAY_SIZE(skl_u_ddi_translations_edp
);
390 ddi_translations
= skl_u_ddi_translations_dp
;
391 *n_entries
= ARRAY_SIZE(skl_u_ddi_translations_dp
);
394 if (dev_priv
->edp_low_vswing
) {
395 ddi_translations
= skl_ddi_translations_edp
;
396 *n_entries
= ARRAY_SIZE(skl_ddi_translations_edp
);
398 ddi_translations
= skl_ddi_translations_dp
;
399 *n_entries
= ARRAY_SIZE(skl_ddi_translations_dp
);
403 return ddi_translations
;
406 static const struct ddi_buf_trans
*
407 skl_get_buf_trans_hdmi(struct drm_device
*dev
,
410 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
411 const struct ddi_buf_trans
*ddi_translations
;
412 static int is_095v
= -1;
415 u32 spr1
= I915_READ(UAIMI_SPR1
);
417 is_095v
= spr1
& SKL_VCCIO_MASK
;
420 if (IS_SKL_ULX(dev
) && !is_095v
) {
421 ddi_translations
= skl_y_085v_ddi_translations_hdmi
;
422 *n_entries
= ARRAY_SIZE(skl_y_085v_ddi_translations_hdmi
);
424 ddi_translations
= skl_ddi_translations_hdmi
;
425 *n_entries
= ARRAY_SIZE(skl_ddi_translations_hdmi
);
428 return ddi_translations
;
432 * Starting with Haswell, DDI port buffers must be programmed with correct
433 * values in advance. The buffer values are different for FDI and DP modes,
434 * but the HDMI/DVI fields are shared among those. So we program the DDI
435 * in either FDI or DP modes only, as HDMI connections will work with both
438 static void intel_prepare_ddi_buffers(struct drm_device
*dev
, enum port port
,
441 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
443 int i
, n_hdmi_entries
, n_dp_entries
, n_edp_entries
, hdmi_default_entry
,
445 int hdmi_level
= dev_priv
->vbt
.ddi_port_info
[port
].hdmi_level_shift
;
446 const struct ddi_buf_trans
*ddi_translations_fdi
;
447 const struct ddi_buf_trans
*ddi_translations_dp
;
448 const struct ddi_buf_trans
*ddi_translations_edp
;
449 const struct ddi_buf_trans
*ddi_translations_hdmi
;
450 const struct ddi_buf_trans
*ddi_translations
;
452 if (IS_BROXTON(dev
)) {
456 /* Vswing programming for HDMI */
457 bxt_ddi_vswing_sequence(dev
, hdmi_level
, port
,
460 } else if (IS_SKYLAKE(dev
)) {
461 ddi_translations_dp
=
462 skl_get_buf_trans_dp(dev
, &n_dp_entries
);
463 ddi_translations_edp
=
464 skl_get_buf_trans_edp(dev
, &n_edp_entries
);
465 ddi_translations_hdmi
=
466 skl_get_buf_trans_hdmi(dev
, &n_hdmi_entries
);
467 hdmi_default_entry
= 8;
468 } else if (IS_BROADWELL(dev
)) {
469 ddi_translations_fdi
= bdw_ddi_translations_fdi
;
470 ddi_translations_dp
= bdw_ddi_translations_dp
;
471 ddi_translations_edp
= bdw_ddi_translations_edp
;
472 ddi_translations_hdmi
= bdw_ddi_translations_hdmi
;
473 n_edp_entries
= ARRAY_SIZE(bdw_ddi_translations_edp
);
474 n_dp_entries
= ARRAY_SIZE(bdw_ddi_translations_dp
);
475 n_hdmi_entries
= ARRAY_SIZE(bdw_ddi_translations_hdmi
);
476 hdmi_default_entry
= 7;
477 } else if (IS_HASWELL(dev
)) {
478 ddi_translations_fdi
= hsw_ddi_translations_fdi
;
479 ddi_translations_dp
= hsw_ddi_translations_dp
;
480 ddi_translations_edp
= hsw_ddi_translations_dp
;
481 ddi_translations_hdmi
= hsw_ddi_translations_hdmi
;
482 n_dp_entries
= n_edp_entries
= ARRAY_SIZE(hsw_ddi_translations_dp
);
483 n_hdmi_entries
= ARRAY_SIZE(hsw_ddi_translations_hdmi
);
484 hdmi_default_entry
= 6;
486 WARN(1, "ddi translation table missing\n");
487 ddi_translations_edp
= bdw_ddi_translations_dp
;
488 ddi_translations_fdi
= bdw_ddi_translations_fdi
;
489 ddi_translations_dp
= bdw_ddi_translations_dp
;
490 ddi_translations_hdmi
= bdw_ddi_translations_hdmi
;
491 n_edp_entries
= ARRAY_SIZE(bdw_ddi_translations_edp
);
492 n_dp_entries
= ARRAY_SIZE(bdw_ddi_translations_dp
);
493 n_hdmi_entries
= ARRAY_SIZE(bdw_ddi_translations_hdmi
);
494 hdmi_default_entry
= 7;
499 ddi_translations
= ddi_translations_edp
;
500 size
= n_edp_entries
;
504 ddi_translations
= ddi_translations_dp
;
508 if (intel_dp_is_edp(dev
, PORT_D
)) {
509 ddi_translations
= ddi_translations_edp
;
510 size
= n_edp_entries
;
512 ddi_translations
= ddi_translations_dp
;
517 if (ddi_translations_fdi
)
518 ddi_translations
= ddi_translations_fdi
;
520 ddi_translations
= ddi_translations_dp
;
527 for (i
= 0, reg
= DDI_BUF_TRANS(port
); i
< size
; i
++) {
528 I915_WRITE(reg
, ddi_translations
[i
].trans1
);
530 I915_WRITE(reg
, ddi_translations
[i
].trans2
);
537 /* Choose a good default if VBT is badly populated */
538 if (hdmi_level
== HDMI_LEVEL_SHIFT_UNKNOWN
||
539 hdmi_level
>= n_hdmi_entries
)
540 hdmi_level
= hdmi_default_entry
;
542 /* Entry 9 is for HDMI: */
543 I915_WRITE(reg
, ddi_translations_hdmi
[hdmi_level
].trans1
);
545 I915_WRITE(reg
, ddi_translations_hdmi
[hdmi_level
].trans2
);
549 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
550 * mode and port E for FDI.
552 void intel_prepare_ddi(struct drm_device
*dev
)
554 struct intel_encoder
*intel_encoder
;
555 bool visited
[I915_MAX_PORTS
] = { 0, };
560 for_each_intel_encoder(dev
, intel_encoder
) {
561 struct intel_digital_port
*intel_dig_port
;
565 ddi_get_encoder_port(intel_encoder
, &intel_dig_port
, &port
);
570 supports_hdmi
= intel_dig_port
&&
571 intel_dig_port_supports_hdmi(intel_dig_port
);
573 intel_prepare_ddi_buffers(dev
, port
, supports_hdmi
);
574 visited
[port
] = true;
578 static void intel_wait_ddi_buf_idle(struct drm_i915_private
*dev_priv
,
581 uint32_t reg
= DDI_BUF_CTL(port
);
584 for (i
= 0; i
< 16; i
++) {
586 if (I915_READ(reg
) & DDI_BUF_IS_IDLE
)
589 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port
));
592 /* Starting with Haswell, different DDI ports can work in FDI mode for
593 * connection to the PCH-located connectors. For this, it is necessary to train
594 * both the DDI port and PCH receiver for the desired DDI buffer settings.
596 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
597 * please note that when FDI mode is active on DDI E, it shares 2 lines with
598 * DDI A (which is used for eDP)
601 void hsw_fdi_link_train(struct drm_crtc
*crtc
)
603 struct drm_device
*dev
= crtc
->dev
;
604 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
605 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
606 u32 temp
, i
, rx_ctl_val
;
608 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
609 * mode set "sequence for CRT port" document:
610 * - TP1 to TP2 time with the default value
613 * WaFDIAutoLinkSetTimingOverrride:hsw
615 I915_WRITE(_FDI_RXA_MISC
, FDI_RX_PWRDN_LANE1_VAL(2) |
616 FDI_RX_PWRDN_LANE0_VAL(2) |
617 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
619 /* Enable the PCH Receiver FDI PLL */
620 rx_ctl_val
= dev_priv
->fdi_rx_config
| FDI_RX_ENHANCE_FRAME_ENABLE
|
622 FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
623 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
624 POSTING_READ(_FDI_RXA_CTL
);
627 /* Switch from Rawclk to PCDclk */
628 rx_ctl_val
|= FDI_PCDCLK
;
629 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
631 /* Configure Port Clock Select */
632 I915_WRITE(PORT_CLK_SEL(PORT_E
), intel_crtc
->config
->ddi_pll_sel
);
633 WARN_ON(intel_crtc
->config
->ddi_pll_sel
!= PORT_CLK_SEL_SPLL
);
635 /* Start the training iterating through available voltages and emphasis,
636 * testing each value twice. */
637 for (i
= 0; i
< ARRAY_SIZE(hsw_ddi_translations_fdi
) * 2; i
++) {
638 /* Configure DP_TP_CTL with auto-training */
639 I915_WRITE(DP_TP_CTL(PORT_E
),
640 DP_TP_CTL_FDI_AUTOTRAIN
|
641 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
642 DP_TP_CTL_LINK_TRAIN_PAT1
|
645 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
646 * DDI E does not support port reversal, the functionality is
647 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
648 * port reversal bit */
649 I915_WRITE(DDI_BUF_CTL(PORT_E
),
651 ((intel_crtc
->config
->fdi_lanes
- 1) << 1) |
652 DDI_BUF_TRANS_SELECT(i
/ 2));
653 POSTING_READ(DDI_BUF_CTL(PORT_E
));
657 /* Program PCH FDI Receiver TU */
658 I915_WRITE(_FDI_RXA_TUSIZE1
, TU_SIZE(64));
660 /* Enable PCH FDI Receiver with auto-training */
661 rx_ctl_val
|= FDI_RX_ENABLE
| FDI_LINK_TRAIN_AUTO
;
662 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
663 POSTING_READ(_FDI_RXA_CTL
);
665 /* Wait for FDI receiver lane calibration */
668 /* Unset FDI_RX_MISC pwrdn lanes */
669 temp
= I915_READ(_FDI_RXA_MISC
);
670 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
671 I915_WRITE(_FDI_RXA_MISC
, temp
);
672 POSTING_READ(_FDI_RXA_MISC
);
674 /* Wait for FDI auto training time */
677 temp
= I915_READ(DP_TP_STATUS(PORT_E
));
678 if (temp
& DP_TP_STATUS_AUTOTRAIN_DONE
) {
679 DRM_DEBUG_KMS("FDI link training done on step %d\n", i
);
681 /* Enable normal pixel sending for FDI */
682 I915_WRITE(DP_TP_CTL(PORT_E
),
683 DP_TP_CTL_FDI_AUTOTRAIN
|
684 DP_TP_CTL_LINK_TRAIN_NORMAL
|
685 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
691 temp
= I915_READ(DDI_BUF_CTL(PORT_E
));
692 temp
&= ~DDI_BUF_CTL_ENABLE
;
693 I915_WRITE(DDI_BUF_CTL(PORT_E
), temp
);
694 POSTING_READ(DDI_BUF_CTL(PORT_E
));
696 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
697 temp
= I915_READ(DP_TP_CTL(PORT_E
));
698 temp
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
699 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
700 I915_WRITE(DP_TP_CTL(PORT_E
), temp
);
701 POSTING_READ(DP_TP_CTL(PORT_E
));
703 intel_wait_ddi_buf_idle(dev_priv
, PORT_E
);
705 rx_ctl_val
&= ~FDI_RX_ENABLE
;
706 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
707 POSTING_READ(_FDI_RXA_CTL
);
709 /* Reset FDI_RX_MISC pwrdn lanes */
710 temp
= I915_READ(_FDI_RXA_MISC
);
711 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
712 temp
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
713 I915_WRITE(_FDI_RXA_MISC
, temp
);
714 POSTING_READ(_FDI_RXA_MISC
);
717 DRM_ERROR("FDI link training failed!\n");
720 void intel_ddi_init_dp_buf_reg(struct intel_encoder
*encoder
)
722 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
723 struct intel_digital_port
*intel_dig_port
=
724 enc_to_dig_port(&encoder
->base
);
726 intel_dp
->DP
= intel_dig_port
->saved_port_bits
|
727 DDI_BUF_CTL_ENABLE
| DDI_BUF_TRANS_SELECT(0);
728 intel_dp
->DP
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
732 static struct intel_encoder
*
733 intel_ddi_get_crtc_encoder(struct drm_crtc
*crtc
)
735 struct drm_device
*dev
= crtc
->dev
;
736 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
737 struct intel_encoder
*intel_encoder
, *ret
= NULL
;
738 int num_encoders
= 0;
740 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
745 if (num_encoders
!= 1)
746 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders
,
747 pipe_name(intel_crtc
->pipe
));
753 struct intel_encoder
*
754 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state
*crtc_state
)
756 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
757 struct intel_encoder
*ret
= NULL
;
758 struct drm_atomic_state
*state
;
759 struct drm_connector
*connector
;
760 struct drm_connector_state
*connector_state
;
761 int num_encoders
= 0;
764 state
= crtc_state
->base
.state
;
766 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
767 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
770 ret
= to_intel_encoder(connector_state
->best_encoder
);
774 WARN(num_encoders
!= 1, "%d encoders on crtc for pipe %c\n", num_encoders
,
775 pipe_name(crtc
->pipe
));
782 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
788 /* Constraints for PLL good behavior */
794 #define abs_diff(a, b) ({ \
795 typeof(a) __a = (a); \
796 typeof(b) __b = (b); \
797 (void) (&__a == &__b); \
798 __a > __b ? (__a - __b) : (__b - __a); })
800 struct hsw_wrpll_rnp
{
804 static unsigned hsw_wrpll_get_budget_for_freq(int clock
)
878 static void hsw_wrpll_update_rnp(uint64_t freq2k
, unsigned budget
,
879 unsigned r2
, unsigned n2
, unsigned p
,
880 struct hsw_wrpll_rnp
*best
)
882 uint64_t a
, b
, c
, d
, diff
, diff_best
;
884 /* No best (r,n,p) yet */
893 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
897 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
900 * and we would like delta <= budget.
902 * If the discrepancy is above the PPM-based budget, always prefer to
903 * improve upon the previous solution. However, if you're within the
904 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
906 a
= freq2k
* budget
* p
* r2
;
907 b
= freq2k
* budget
* best
->p
* best
->r2
;
908 diff
= abs_diff(freq2k
* p
* r2
, LC_FREQ_2K
* n2
);
909 diff_best
= abs_diff(freq2k
* best
->p
* best
->r2
,
910 LC_FREQ_2K
* best
->n2
);
912 d
= 1000000 * diff_best
;
914 if (a
< c
&& b
< d
) {
915 /* If both are above the budget, pick the closer */
916 if (best
->p
* best
->r2
* diff
< p
* r2
* diff_best
) {
921 } else if (a
>= c
&& b
< d
) {
922 /* If A is below the threshold but B is above it? Update. */
926 } else if (a
>= c
&& b
>= d
) {
927 /* Both are below the limit, so pick the higher n2/(r2*r2) */
928 if (n2
* best
->r2
* best
->r2
> best
->n2
* r2
* r2
) {
934 /* Otherwise a < c && b >= d, do nothing */
937 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private
*dev_priv
, int reg
)
939 int refclk
= LC_FREQ
;
943 wrpll
= I915_READ(reg
);
944 switch (wrpll
& WRPLL_PLL_REF_MASK
) {
946 case WRPLL_PLL_NON_SSC
:
948 * We could calculate spread here, but our checking
949 * code only cares about 5% accuracy, and spread is a max of
954 case WRPLL_PLL_LCPLL
:
958 WARN(1, "bad wrpll refclk\n");
962 r
= wrpll
& WRPLL_DIVIDER_REF_MASK
;
963 p
= (wrpll
& WRPLL_DIVIDER_POST_MASK
) >> WRPLL_DIVIDER_POST_SHIFT
;
964 n
= (wrpll
& WRPLL_DIVIDER_FB_MASK
) >> WRPLL_DIVIDER_FB_SHIFT
;
966 /* Convert to KHz, p & r have a fixed point portion */
967 return (refclk
* n
* 100) / (p
* r
);
970 static int skl_calc_wrpll_link(struct drm_i915_private
*dev_priv
,
973 uint32_t cfgcr1_reg
, cfgcr2_reg
;
974 uint32_t cfgcr1_val
, cfgcr2_val
;
975 uint32_t p0
, p1
, p2
, dco_freq
;
977 cfgcr1_reg
= GET_CFG_CR1_REG(dpll
);
978 cfgcr2_reg
= GET_CFG_CR2_REG(dpll
);
980 cfgcr1_val
= I915_READ(cfgcr1_reg
);
981 cfgcr2_val
= I915_READ(cfgcr2_reg
);
983 p0
= cfgcr2_val
& DPLL_CFGCR2_PDIV_MASK
;
984 p2
= cfgcr2_val
& DPLL_CFGCR2_KDIV_MASK
;
986 if (cfgcr2_val
& DPLL_CFGCR2_QDIV_MODE(1))
987 p1
= (cfgcr2_val
& DPLL_CFGCR2_QDIV_RATIO_MASK
) >> 8;
993 case DPLL_CFGCR2_PDIV_1
:
996 case DPLL_CFGCR2_PDIV_2
:
999 case DPLL_CFGCR2_PDIV_3
:
1002 case DPLL_CFGCR2_PDIV_7
:
1008 case DPLL_CFGCR2_KDIV_5
:
1011 case DPLL_CFGCR2_KDIV_2
:
1014 case DPLL_CFGCR2_KDIV_3
:
1017 case DPLL_CFGCR2_KDIV_1
:
1022 dco_freq
= (cfgcr1_val
& DPLL_CFGCR1_DCO_INTEGER_MASK
) * 24 * 1000;
1024 dco_freq
+= (((cfgcr1_val
& DPLL_CFGCR1_DCO_FRACTION_MASK
) >> 9) * 24 *
1027 return dco_freq
/ (p0
* p1
* p2
* 5);
1030 static void ddi_dotclock_get(struct intel_crtc_state
*pipe_config
)
1034 if (pipe_config
->has_pch_encoder
)
1035 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
1036 &pipe_config
->fdi_m_n
);
1037 else if (pipe_config
->has_dp_encoder
)
1038 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
1039 &pipe_config
->dp_m_n
);
1040 else if (pipe_config
->has_hdmi_sink
&& pipe_config
->pipe_bpp
== 36)
1041 dotclock
= pipe_config
->port_clock
* 2 / 3;
1043 dotclock
= pipe_config
->port_clock
;
1045 if (pipe_config
->pixel_multiplier
)
1046 dotclock
/= pipe_config
->pixel_multiplier
;
1048 pipe_config
->base
.adjusted_mode
.crtc_clock
= dotclock
;
1051 static void skl_ddi_clock_get(struct intel_encoder
*encoder
,
1052 struct intel_crtc_state
*pipe_config
)
1054 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
1056 uint32_t dpll_ctl1
, dpll
;
1058 dpll
= pipe_config
->ddi_pll_sel
;
1060 dpll_ctl1
= I915_READ(DPLL_CTRL1
);
1062 if (dpll_ctl1
& DPLL_CTRL1_HDMI_MODE(dpll
)) {
1063 link_clock
= skl_calc_wrpll_link(dev_priv
, dpll
);
1065 link_clock
= dpll_ctl1
& DPLL_CTRL1_LINK_RATE_MASK(dpll
);
1066 link_clock
>>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll
);
1068 switch (link_clock
) {
1069 case DPLL_CTRL1_LINK_RATE_810
:
1072 case DPLL_CTRL1_LINK_RATE_1080
:
1073 link_clock
= 108000;
1075 case DPLL_CTRL1_LINK_RATE_1350
:
1076 link_clock
= 135000;
1078 case DPLL_CTRL1_LINK_RATE_1620
:
1079 link_clock
= 162000;
1081 case DPLL_CTRL1_LINK_RATE_2160
:
1082 link_clock
= 216000;
1084 case DPLL_CTRL1_LINK_RATE_2700
:
1085 link_clock
= 270000;
1088 WARN(1, "Unsupported link rate\n");
1094 pipe_config
->port_clock
= link_clock
;
1096 ddi_dotclock_get(pipe_config
);
1099 static void hsw_ddi_clock_get(struct intel_encoder
*encoder
,
1100 struct intel_crtc_state
*pipe_config
)
1102 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
1106 val
= pipe_config
->ddi_pll_sel
;
1107 switch (val
& PORT_CLK_SEL_MASK
) {
1108 case PORT_CLK_SEL_LCPLL_810
:
1111 case PORT_CLK_SEL_LCPLL_1350
:
1112 link_clock
= 135000;
1114 case PORT_CLK_SEL_LCPLL_2700
:
1115 link_clock
= 270000;
1117 case PORT_CLK_SEL_WRPLL1
:
1118 link_clock
= hsw_ddi_calc_wrpll_link(dev_priv
, WRPLL_CTL1
);
1120 case PORT_CLK_SEL_WRPLL2
:
1121 link_clock
= hsw_ddi_calc_wrpll_link(dev_priv
, WRPLL_CTL2
);
1123 case PORT_CLK_SEL_SPLL
:
1124 pll
= I915_READ(SPLL_CTL
) & SPLL_PLL_FREQ_MASK
;
1125 if (pll
== SPLL_PLL_FREQ_810MHz
)
1127 else if (pll
== SPLL_PLL_FREQ_1350MHz
)
1128 link_clock
= 135000;
1129 else if (pll
== SPLL_PLL_FREQ_2700MHz
)
1130 link_clock
= 270000;
1132 WARN(1, "bad spll freq\n");
1137 WARN(1, "bad port clock sel\n");
1141 pipe_config
->port_clock
= link_clock
* 2;
1143 ddi_dotclock_get(pipe_config
);
1146 static int bxt_calc_pll_link(struct drm_i915_private
*dev_priv
,
1147 enum intel_dpll_id dpll
)
1149 struct intel_shared_dpll
*pll
;
1150 struct intel_dpll_hw_state
*state
;
1151 intel_clock_t clock
;
1153 /* For DDI ports we always use a shared PLL. */
1154 if (WARN_ON(dpll
== DPLL_ID_PRIVATE
))
1157 pll
= &dev_priv
->shared_dplls
[dpll
];
1158 state
= &pll
->config
.hw_state
;
1161 clock
.m2
= (state
->pll0
& PORT_PLL_M2_MASK
) << 22;
1162 if (state
->pll3
& PORT_PLL_M2_FRAC_ENABLE
)
1163 clock
.m2
|= state
->pll2
& PORT_PLL_M2_FRAC_MASK
;
1164 clock
.n
= (state
->pll1
& PORT_PLL_N_MASK
) >> PORT_PLL_N_SHIFT
;
1165 clock
.p1
= (state
->ebb0
& PORT_PLL_P1_MASK
) >> PORT_PLL_P1_SHIFT
;
1166 clock
.p2
= (state
->ebb0
& PORT_PLL_P2_MASK
) >> PORT_PLL_P2_SHIFT
;
1168 return chv_calc_dpll_params(100000, &clock
);
1171 static void bxt_ddi_clock_get(struct intel_encoder
*encoder
,
1172 struct intel_crtc_state
*pipe_config
)
1174 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
1175 enum port port
= intel_ddi_get_encoder_port(encoder
);
1176 uint32_t dpll
= port
;
1178 pipe_config
->port_clock
= bxt_calc_pll_link(dev_priv
, dpll
);
1180 ddi_dotclock_get(pipe_config
);
1183 void intel_ddi_clock_get(struct intel_encoder
*encoder
,
1184 struct intel_crtc_state
*pipe_config
)
1186 struct drm_device
*dev
= encoder
->base
.dev
;
1188 if (INTEL_INFO(dev
)->gen
<= 8)
1189 hsw_ddi_clock_get(encoder
, pipe_config
);
1190 else if (IS_SKYLAKE(dev
))
1191 skl_ddi_clock_get(encoder
, pipe_config
);
1192 else if (IS_BROXTON(dev
))
1193 bxt_ddi_clock_get(encoder
, pipe_config
);
1197 hsw_ddi_calculate_wrpll(int clock
/* in Hz */,
1198 unsigned *r2_out
, unsigned *n2_out
, unsigned *p_out
)
1202 struct hsw_wrpll_rnp best
= { 0, 0, 0 };
1205 freq2k
= clock
/ 100;
1207 budget
= hsw_wrpll_get_budget_for_freq(clock
);
1209 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1210 * and directly pass the LC PLL to it. */
1211 if (freq2k
== 5400000) {
1219 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1222 * We want R so that REF_MIN <= Ref <= REF_MAX.
1223 * Injecting R2 = 2 * R gives:
1224 * REF_MAX * r2 > LC_FREQ * 2 and
1225 * REF_MIN * r2 < LC_FREQ * 2
1227 * Which means the desired boundaries for r2 are:
1228 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1231 for (r2
= LC_FREQ
* 2 / REF_MAX
+ 1;
1232 r2
<= LC_FREQ
* 2 / REF_MIN
;
1236 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1238 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1239 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1240 * VCO_MAX * r2 > n2 * LC_FREQ and
1241 * VCO_MIN * r2 < n2 * LC_FREQ)
1243 * Which means the desired boundaries for n2 are:
1244 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1246 for (n2
= VCO_MIN
* r2
/ LC_FREQ
+ 1;
1247 n2
<= VCO_MAX
* r2
/ LC_FREQ
;
1250 for (p
= P_MIN
; p
<= P_MAX
; p
+= P_INC
)
1251 hsw_wrpll_update_rnp(freq2k
, budget
,
1262 hsw_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1263 struct intel_crtc_state
*crtc_state
,
1264 struct intel_encoder
*intel_encoder
,
1267 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
1268 struct intel_shared_dpll
*pll
;
1272 hsw_ddi_calculate_wrpll(clock
* 1000, &r2
, &n2
, &p
);
1274 val
= WRPLL_PLL_ENABLE
| WRPLL_PLL_LCPLL
|
1275 WRPLL_DIVIDER_REFERENCE(r2
) | WRPLL_DIVIDER_FEEDBACK(n2
) |
1276 WRPLL_DIVIDER_POST(p
);
1278 memset(&crtc_state
->dpll_hw_state
, 0,
1279 sizeof(crtc_state
->dpll_hw_state
));
1281 crtc_state
->dpll_hw_state
.wrpll
= val
;
1283 pll
= intel_get_shared_dpll(intel_crtc
, crtc_state
);
1285 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1286 pipe_name(intel_crtc
->pipe
));
1290 crtc_state
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL(pll
->id
);
1296 struct skl_wrpll_context
{
1297 uint64_t min_deviation
; /* current minimal deviation */
1298 uint64_t central_freq
; /* chosen central freq */
1299 uint64_t dco_freq
; /* chosen dco freq */
1300 unsigned int p
; /* chosen divider */
1303 static void skl_wrpll_context_init(struct skl_wrpll_context
*ctx
)
1305 memset(ctx
, 0, sizeof(*ctx
));
1307 ctx
->min_deviation
= U64_MAX
;
1310 /* DCO freq must be within +1%/-6% of the DCO central freq */
1311 #define SKL_DCO_MAX_PDEVIATION 100
1312 #define SKL_DCO_MAX_NDEVIATION 600
1314 static void skl_wrpll_try_divider(struct skl_wrpll_context
*ctx
,
1315 uint64_t central_freq
,
1317 unsigned int divider
)
1321 deviation
= div64_u64(10000 * abs_diff(dco_freq
, central_freq
),
1324 /* positive deviation */
1325 if (dco_freq
>= central_freq
) {
1326 if (deviation
< SKL_DCO_MAX_PDEVIATION
&&
1327 deviation
< ctx
->min_deviation
) {
1328 ctx
->min_deviation
= deviation
;
1329 ctx
->central_freq
= central_freq
;
1330 ctx
->dco_freq
= dco_freq
;
1333 /* negative deviation */
1334 } else if (deviation
< SKL_DCO_MAX_NDEVIATION
&&
1335 deviation
< ctx
->min_deviation
) {
1336 ctx
->min_deviation
= deviation
;
1337 ctx
->central_freq
= central_freq
;
1338 ctx
->dco_freq
= dco_freq
;
1343 static void skl_wrpll_get_multipliers(unsigned int p
,
1344 unsigned int *p0
/* out */,
1345 unsigned int *p1
/* out */,
1346 unsigned int *p2
/* out */)
1350 unsigned int half
= p
/ 2;
1352 if (half
== 1 || half
== 2 || half
== 3 || half
== 5) {
1356 } else if (half
% 2 == 0) {
1360 } else if (half
% 3 == 0) {
1364 } else if (half
% 7 == 0) {
1369 } else if (p
== 3 || p
== 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1373 } else if (p
== 5 || p
== 7) {
1377 } else if (p
== 15) {
1381 } else if (p
== 21) {
1385 } else if (p
== 35) {
1392 struct skl_wrpll_params
{
1393 uint32_t dco_fraction
;
1394 uint32_t dco_integer
;
1395 uint32_t qdiv_ratio
;
1399 uint32_t central_freq
;
1402 static void skl_wrpll_params_populate(struct skl_wrpll_params
*params
,
1404 uint64_t central_freq
,
1405 uint32_t p0
, uint32_t p1
, uint32_t p2
)
1409 switch (central_freq
) {
1411 params
->central_freq
= 0;
1414 params
->central_freq
= 1;
1417 params
->central_freq
= 3;
1434 WARN(1, "Incorrect PDiv\n");
1451 WARN(1, "Incorrect KDiv\n");
1454 params
->qdiv_ratio
= p1
;
1455 params
->qdiv_mode
= (params
->qdiv_ratio
== 1) ? 0 : 1;
1457 dco_freq
= p0
* p1
* p2
* afe_clock
;
1460 * Intermediate values are in Hz.
1461 * Divide by MHz to match bsepc
1463 params
->dco_integer
= div_u64(dco_freq
, 24 * MHz(1));
1464 params
->dco_fraction
=
1465 div_u64((div_u64(dco_freq
, 24) -
1466 params
->dco_integer
* MHz(1)) * 0x8000, MHz(1));
1470 skl_ddi_calculate_wrpll(int clock
/* in Hz */,
1471 struct skl_wrpll_params
*wrpll_params
)
1473 uint64_t afe_clock
= clock
* 5; /* AFE Clock is 5x Pixel clock */
1474 uint64_t dco_central_freq
[3] = {8400000000ULL,
1477 static const int even_dividers
[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1478 24, 28, 30, 32, 36, 40, 42, 44,
1479 48, 52, 54, 56, 60, 64, 66, 68,
1480 70, 72, 76, 78, 80, 84, 88, 90,
1482 static const int odd_dividers
[] = { 3, 5, 7, 9, 15, 21, 35 };
1483 static const struct {
1487 { even_dividers
, ARRAY_SIZE(even_dividers
) },
1488 { odd_dividers
, ARRAY_SIZE(odd_dividers
) },
1490 struct skl_wrpll_context ctx
;
1491 unsigned int dco
, d
, i
;
1492 unsigned int p0
, p1
, p2
;
1494 skl_wrpll_context_init(&ctx
);
1496 for (d
= 0; d
< ARRAY_SIZE(dividers
); d
++) {
1497 for (dco
= 0; dco
< ARRAY_SIZE(dco_central_freq
); dco
++) {
1498 for (i
= 0; i
< dividers
[d
].n_dividers
; i
++) {
1499 unsigned int p
= dividers
[d
].list
[i
];
1500 uint64_t dco_freq
= p
* afe_clock
;
1502 skl_wrpll_try_divider(&ctx
,
1503 dco_central_freq
[dco
],
1507 * Skip the remaining dividers if we're sure to
1508 * have found the definitive divider, we can't
1509 * improve a 0 deviation.
1511 if (ctx
.min_deviation
== 0)
1512 goto skip_remaining_dividers
;
1516 skip_remaining_dividers
:
1518 * If a solution is found with an even divider, prefer
1521 if (d
== 0 && ctx
.p
)
1526 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock
);
1531 * gcc incorrectly analyses that these can be used without being
1532 * initialized. To be fair, it's hard to guess.
1535 skl_wrpll_get_multipliers(ctx
.p
, &p0
, &p1
, &p2
);
1536 skl_wrpll_params_populate(wrpll_params
, afe_clock
, ctx
.central_freq
,
1543 skl_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1544 struct intel_crtc_state
*crtc_state
,
1545 struct intel_encoder
*intel_encoder
,
1548 struct intel_shared_dpll
*pll
;
1549 uint32_t ctrl1
, cfgcr1
, cfgcr2
;
1552 * See comment in intel_dpll_hw_state to understand why we always use 0
1553 * as the DPLL id in this function.
1556 ctrl1
= DPLL_CTRL1_OVERRIDE(0);
1558 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
1559 struct skl_wrpll_params wrpll_params
= { 0, };
1561 ctrl1
|= DPLL_CTRL1_HDMI_MODE(0);
1563 if (!skl_ddi_calculate_wrpll(clock
* 1000, &wrpll_params
))
1566 cfgcr1
= DPLL_CFGCR1_FREQ_ENABLE
|
1567 DPLL_CFGCR1_DCO_FRACTION(wrpll_params
.dco_fraction
) |
1568 wrpll_params
.dco_integer
;
1570 cfgcr2
= DPLL_CFGCR2_QDIV_RATIO(wrpll_params
.qdiv_ratio
) |
1571 DPLL_CFGCR2_QDIV_MODE(wrpll_params
.qdiv_mode
) |
1572 DPLL_CFGCR2_KDIV(wrpll_params
.kdiv
) |
1573 DPLL_CFGCR2_PDIV(wrpll_params
.pdiv
) |
1574 wrpll_params
.central_freq
;
1575 } else if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
) {
1576 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1577 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1579 switch (intel_dp
->link_bw
) {
1580 case DP_LINK_BW_1_62
:
1581 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
, 0);
1583 case DP_LINK_BW_2_7
:
1584 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350
, 0);
1586 case DP_LINK_BW_5_4
:
1587 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700
, 0);
1591 cfgcr1
= cfgcr2
= 0;
1595 memset(&crtc_state
->dpll_hw_state
, 0,
1596 sizeof(crtc_state
->dpll_hw_state
));
1598 crtc_state
->dpll_hw_state
.ctrl1
= ctrl1
;
1599 crtc_state
->dpll_hw_state
.cfgcr1
= cfgcr1
;
1600 crtc_state
->dpll_hw_state
.cfgcr2
= cfgcr2
;
1602 pll
= intel_get_shared_dpll(intel_crtc
, crtc_state
);
1604 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1605 pipe_name(intel_crtc
->pipe
));
1609 /* shared DPLL id 0 is DPLL 1 */
1610 crtc_state
->ddi_pll_sel
= pll
->id
+ 1;
1615 /* bxt clock parameters */
1616 struct bxt_clk_div
{
1626 /* pre-calculated values for DP linkrates */
1627 static const struct bxt_clk_div bxt_dp_clk_val
[] = {
1628 {162000, 4, 2, 32, 1677722, 1, 1},
1629 {270000, 4, 1, 27, 0, 0, 1},
1630 {540000, 2, 1, 27, 0, 0, 1},
1631 {216000, 3, 2, 32, 1677722, 1, 1},
1632 {243000, 4, 1, 24, 1258291, 1, 1},
1633 {324000, 4, 1, 32, 1677722, 1, 1},
1634 {432000, 3, 1, 32, 1677722, 1, 1}
1638 bxt_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1639 struct intel_crtc_state
*crtc_state
,
1640 struct intel_encoder
*intel_encoder
,
1643 struct intel_shared_dpll
*pll
;
1644 struct bxt_clk_div clk_div
= {0};
1646 uint32_t prop_coef
, int_coef
, gain_ctl
, targ_cnt
;
1647 uint32_t lanestagger
;
1649 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
1650 intel_clock_t best_clock
;
1652 /* Calculate HDMI div */
1654 * FIXME: tie the following calculation into
1655 * i9xx_crtc_compute_clock
1657 if (!bxt_find_best_dpll(crtc_state
, clock
, &best_clock
)) {
1658 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1659 clock
, pipe_name(intel_crtc
->pipe
));
1663 clk_div
.p1
= best_clock
.p1
;
1664 clk_div
.p2
= best_clock
.p2
;
1665 WARN_ON(best_clock
.m1
!= 2);
1666 clk_div
.n
= best_clock
.n
;
1667 clk_div
.m2_int
= best_clock
.m2
>> 22;
1668 clk_div
.m2_frac
= best_clock
.m2
& ((1 << 22) - 1);
1669 clk_div
.m2_frac_en
= clk_div
.m2_frac
!= 0;
1671 vco
= best_clock
.vco
;
1672 } else if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
1673 intel_encoder
->type
== INTEL_OUTPUT_EDP
) {
1676 clk_div
= bxt_dp_clk_val
[0];
1677 for (i
= 0; i
< ARRAY_SIZE(bxt_dp_clk_val
); ++i
) {
1678 if (bxt_dp_clk_val
[i
].clock
== clock
) {
1679 clk_div
= bxt_dp_clk_val
[i
];
1683 vco
= clock
* 10 / 2 * clk_div
.p1
* clk_div
.p2
;
1686 if (vco
>= 6200000 && vco
<= 6700000) {
1691 } else if ((vco
> 5400000 && vco
< 6200000) ||
1692 (vco
>= 4800000 && vco
< 5400000)) {
1697 } else if (vco
== 5400000) {
1703 DRM_ERROR("Invalid VCO\n");
1707 memset(&crtc_state
->dpll_hw_state
, 0,
1708 sizeof(crtc_state
->dpll_hw_state
));
1712 else if (clock
> 135000)
1714 else if (clock
> 67000)
1716 else if (clock
> 33000)
1721 crtc_state
->dpll_hw_state
.ebb0
=
1722 PORT_PLL_P1(clk_div
.p1
) | PORT_PLL_P2(clk_div
.p2
);
1723 crtc_state
->dpll_hw_state
.pll0
= clk_div
.m2_int
;
1724 crtc_state
->dpll_hw_state
.pll1
= PORT_PLL_N(clk_div
.n
);
1725 crtc_state
->dpll_hw_state
.pll2
= clk_div
.m2_frac
;
1727 if (clk_div
.m2_frac_en
)
1728 crtc_state
->dpll_hw_state
.pll3
=
1729 PORT_PLL_M2_FRAC_ENABLE
;
1731 crtc_state
->dpll_hw_state
.pll6
=
1732 prop_coef
| PORT_PLL_INT_COEFF(int_coef
);
1733 crtc_state
->dpll_hw_state
.pll6
|=
1734 PORT_PLL_GAIN_CTL(gain_ctl
);
1736 crtc_state
->dpll_hw_state
.pll8
= targ_cnt
;
1738 crtc_state
->dpll_hw_state
.pll9
= 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT
;
1740 crtc_state
->dpll_hw_state
.pll10
=
1741 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT
)
1742 | PORT_PLL_DCO_AMP_OVR_EN_H
;
1744 crtc_state
->dpll_hw_state
.ebb4
= PORT_PLL_10BIT_CLK_ENABLE
;
1746 crtc_state
->dpll_hw_state
.pcsdw12
=
1747 LANESTAGGER_STRAP_OVRD
| lanestagger
;
1749 pll
= intel_get_shared_dpll(intel_crtc
, crtc_state
);
1751 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1752 pipe_name(intel_crtc
->pipe
));
1756 /* shared DPLL id 0 is DPLL A */
1757 crtc_state
->ddi_pll_sel
= pll
->id
;
1763 * Tries to find a *shared* PLL for the CRTC and store it in
1764 * intel_crtc->ddi_pll_sel.
1766 * For private DPLLs, compute_config() should do the selection for us. This
1767 * function should be folded into compute_config() eventually.
1769 bool intel_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1770 struct intel_crtc_state
*crtc_state
)
1772 struct drm_device
*dev
= intel_crtc
->base
.dev
;
1773 struct intel_encoder
*intel_encoder
=
1774 intel_ddi_get_crtc_new_encoder(crtc_state
);
1775 int clock
= crtc_state
->port_clock
;
1777 if (IS_SKYLAKE(dev
))
1778 return skl_ddi_pll_select(intel_crtc
, crtc_state
,
1779 intel_encoder
, clock
);
1780 else if (IS_BROXTON(dev
))
1781 return bxt_ddi_pll_select(intel_crtc
, crtc_state
,
1782 intel_encoder
, clock
);
1784 return hsw_ddi_pll_select(intel_crtc
, crtc_state
,
1785 intel_encoder
, clock
);
1788 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
)
1790 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1791 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1792 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1793 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1794 int type
= intel_encoder
->type
;
1797 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
|| type
== INTEL_OUTPUT_DP_MST
) {
1798 temp
= TRANS_MSA_SYNC_CLK
;
1799 switch (intel_crtc
->config
->pipe_bpp
) {
1801 temp
|= TRANS_MSA_6_BPC
;
1804 temp
|= TRANS_MSA_8_BPC
;
1807 temp
|= TRANS_MSA_10_BPC
;
1810 temp
|= TRANS_MSA_12_BPC
;
1815 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder
), temp
);
1819 void intel_ddi_set_vc_payload_alloc(struct drm_crtc
*crtc
, bool state
)
1821 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1822 struct drm_device
*dev
= crtc
->dev
;
1823 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1824 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1826 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1828 temp
|= TRANS_DDI_DP_VC_PAYLOAD_ALLOC
;
1830 temp
&= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC
;
1831 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1834 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
)
1836 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1837 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1838 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1839 struct drm_device
*dev
= crtc
->dev
;
1840 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1841 enum pipe pipe
= intel_crtc
->pipe
;
1842 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1843 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1844 int type
= intel_encoder
->type
;
1847 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1848 temp
= TRANS_DDI_FUNC_ENABLE
;
1849 temp
|= TRANS_DDI_SELECT_PORT(port
);
1851 switch (intel_crtc
->config
->pipe_bpp
) {
1853 temp
|= TRANS_DDI_BPC_6
;
1856 temp
|= TRANS_DDI_BPC_8
;
1859 temp
|= TRANS_DDI_BPC_10
;
1862 temp
|= TRANS_DDI_BPC_12
;
1868 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
1869 temp
|= TRANS_DDI_PVSYNC
;
1870 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
1871 temp
|= TRANS_DDI_PHSYNC
;
1873 if (cpu_transcoder
== TRANSCODER_EDP
) {
1876 /* On Haswell, can only use the always-on power well for
1877 * eDP when not using the panel fitter, and when not
1878 * using motion blur mitigation (which we don't
1880 if (IS_HASWELL(dev
) &&
1881 (intel_crtc
->config
->pch_pfit
.enabled
||
1882 intel_crtc
->config
->pch_pfit
.force_thru
))
1883 temp
|= TRANS_DDI_EDP_INPUT_A_ONOFF
;
1885 temp
|= TRANS_DDI_EDP_INPUT_A_ON
;
1888 temp
|= TRANS_DDI_EDP_INPUT_B_ONOFF
;
1891 temp
|= TRANS_DDI_EDP_INPUT_C_ONOFF
;
1899 if (type
== INTEL_OUTPUT_HDMI
) {
1900 if (intel_crtc
->config
->has_hdmi_sink
)
1901 temp
|= TRANS_DDI_MODE_SELECT_HDMI
;
1903 temp
|= TRANS_DDI_MODE_SELECT_DVI
;
1905 } else if (type
== INTEL_OUTPUT_ANALOG
) {
1906 temp
|= TRANS_DDI_MODE_SELECT_FDI
;
1907 temp
|= (intel_crtc
->config
->fdi_lanes
- 1) << 1;
1909 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
||
1910 type
== INTEL_OUTPUT_EDP
) {
1911 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1913 if (intel_dp
->is_mst
) {
1914 temp
|= TRANS_DDI_MODE_SELECT_DP_MST
;
1916 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
1918 temp
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
1919 } else if (type
== INTEL_OUTPUT_DP_MST
) {
1920 struct intel_dp
*intel_dp
= &enc_to_mst(encoder
)->primary
->dp
;
1922 if (intel_dp
->is_mst
) {
1923 temp
|= TRANS_DDI_MODE_SELECT_DP_MST
;
1925 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
1927 temp
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
1929 WARN(1, "Invalid encoder type %d for pipe %c\n",
1930 intel_encoder
->type
, pipe_name(pipe
));
1933 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1936 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1937 enum transcoder cpu_transcoder
)
1939 uint32_t reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1940 uint32_t val
= I915_READ(reg
);
1942 val
&= ~(TRANS_DDI_FUNC_ENABLE
| TRANS_DDI_PORT_MASK
| TRANS_DDI_DP_VC_PAYLOAD_ALLOC
);
1943 val
|= TRANS_DDI_PORT_NONE
;
1944 I915_WRITE(reg
, val
);
1947 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
)
1949 struct drm_device
*dev
= intel_connector
->base
.dev
;
1950 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1951 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
1952 int type
= intel_connector
->base
.connector_type
;
1953 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1955 enum transcoder cpu_transcoder
;
1956 enum intel_display_power_domain power_domain
;
1959 power_domain
= intel_display_port_power_domain(intel_encoder
);
1960 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
1963 if (!intel_encoder
->get_hw_state(intel_encoder
, &pipe
))
1967 cpu_transcoder
= TRANSCODER_EDP
;
1969 cpu_transcoder
= (enum transcoder
) pipe
;
1971 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1973 switch (tmp
& TRANS_DDI_MODE_SELECT_MASK
) {
1974 case TRANS_DDI_MODE_SELECT_HDMI
:
1975 case TRANS_DDI_MODE_SELECT_DVI
:
1976 return (type
== DRM_MODE_CONNECTOR_HDMIA
);
1978 case TRANS_DDI_MODE_SELECT_DP_SST
:
1979 if (type
== DRM_MODE_CONNECTOR_eDP
)
1981 return (type
== DRM_MODE_CONNECTOR_DisplayPort
);
1982 case TRANS_DDI_MODE_SELECT_DP_MST
:
1983 /* if the transcoder is in MST state then
1984 * connector isn't connected */
1987 case TRANS_DDI_MODE_SELECT_FDI
:
1988 return (type
== DRM_MODE_CONNECTOR_VGA
);
1995 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
,
1998 struct drm_device
*dev
= encoder
->base
.dev
;
1999 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2000 enum port port
= intel_ddi_get_encoder_port(encoder
);
2001 enum intel_display_power_domain power_domain
;
2005 power_domain
= intel_display_port_power_domain(encoder
);
2006 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
2009 tmp
= I915_READ(DDI_BUF_CTL(port
));
2011 if (!(tmp
& DDI_BUF_CTL_ENABLE
))
2014 if (port
== PORT_A
) {
2015 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
2017 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
2018 case TRANS_DDI_EDP_INPUT_A_ON
:
2019 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
2022 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
2025 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
2032 for (i
= TRANSCODER_A
; i
<= TRANSCODER_C
; i
++) {
2033 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(i
));
2035 if ((tmp
& TRANS_DDI_PORT_MASK
)
2036 == TRANS_DDI_SELECT_PORT(port
)) {
2037 if ((tmp
& TRANS_DDI_MODE_SELECT_MASK
) == TRANS_DDI_MODE_SELECT_DP_MST
)
2046 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port
));
2051 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
)
2053 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2054 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
2055 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
2056 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
2057 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
2059 if (cpu_transcoder
!= TRANSCODER_EDP
)
2060 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
2061 TRANS_CLK_SEL_PORT(port
));
2064 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
)
2066 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
2067 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
2069 if (cpu_transcoder
!= TRANSCODER_EDP
)
2070 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
2071 TRANS_CLK_SEL_DISABLED
);
2074 static void skl_ddi_set_iboost(struct drm_device
*dev
, u32 level
,
2075 enum port port
, int type
)
2077 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2078 const struct ddi_buf_trans
*ddi_translations
;
2083 if (type
== INTEL_OUTPUT_DISPLAYPORT
) {
2084 ddi_translations
= skl_get_buf_trans_dp(dev
, &n_entries
);
2085 iboost
= ddi_translations
[port
].i_boost
;
2086 } else if (type
== INTEL_OUTPUT_EDP
) {
2087 ddi_translations
= skl_get_buf_trans_edp(dev
, &n_entries
);
2088 iboost
= ddi_translations
[port
].i_boost
;
2089 } else if (type
== INTEL_OUTPUT_HDMI
) {
2090 ddi_translations
= skl_get_buf_trans_hdmi(dev
, &n_entries
);
2091 iboost
= ddi_translations
[port
].i_boost
;
2096 /* Make sure that the requested I_boost is valid */
2097 if (iboost
&& iboost
!= 0x1 && iboost
!= 0x3 && iboost
!= 0x7) {
2098 DRM_ERROR("Invalid I_boost value %u\n", iboost
);
2102 reg
= I915_READ(DISPIO_CR_TX_BMU_CR0
);
2103 reg
&= ~BALANCE_LEG_MASK(port
);
2104 reg
&= ~(1 << (BALANCE_LEG_DISABLE_SHIFT
+ port
));
2107 reg
|= iboost
<< BALANCE_LEG_SHIFT(port
);
2109 reg
|= 1 << (BALANCE_LEG_DISABLE_SHIFT
+ port
);
2111 I915_WRITE(DISPIO_CR_TX_BMU_CR0
, reg
);
2114 static void bxt_ddi_vswing_sequence(struct drm_device
*dev
, u32 level
,
2115 enum port port
, int type
)
2117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2118 const struct bxt_ddi_buf_trans
*ddi_translations
;
2122 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
2123 n_entries
= ARRAY_SIZE(bxt_ddi_translations_dp
);
2124 ddi_translations
= bxt_ddi_translations_dp
;
2125 } else if (type
== INTEL_OUTPUT_HDMI
) {
2126 n_entries
= ARRAY_SIZE(bxt_ddi_translations_hdmi
);
2127 ddi_translations
= bxt_ddi_translations_hdmi
;
2129 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
2134 /* Check if default value has to be used */
2135 if (level
>= n_entries
||
2136 (type
== INTEL_OUTPUT_HDMI
&& level
== HDMI_LEVEL_SHIFT_UNKNOWN
)) {
2137 for (i
= 0; i
< n_entries
; i
++) {
2138 if (ddi_translations
[i
].default_index
) {
2146 * While we write to the group register to program all lanes at once we
2147 * can read only lane registers and we pick lanes 0/1 for that.
2149 val
= I915_READ(BXT_PORT_PCS_DW10_LN01(port
));
2150 val
&= ~(TX2_SWING_CALC_INIT
| TX1_SWING_CALC_INIT
);
2151 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port
), val
);
2153 val
= I915_READ(BXT_PORT_TX_DW2_LN0(port
));
2154 val
&= ~(MARGIN_000
| UNIQ_TRANS_SCALE
);
2155 val
|= ddi_translations
[level
].margin
<< MARGIN_000_SHIFT
|
2156 ddi_translations
[level
].scale
<< UNIQ_TRANS_SCALE_SHIFT
;
2157 I915_WRITE(BXT_PORT_TX_DW2_GRP(port
), val
);
2159 val
= I915_READ(BXT_PORT_TX_DW3_LN0(port
));
2160 val
&= ~UNIQE_TRANGE_EN_METHOD
;
2161 if (ddi_translations
[level
].enable
)
2162 val
|= UNIQE_TRANGE_EN_METHOD
;
2163 I915_WRITE(BXT_PORT_TX_DW3_GRP(port
), val
);
2165 val
= I915_READ(BXT_PORT_TX_DW4_LN0(port
));
2166 val
&= ~DE_EMPHASIS
;
2167 val
|= ddi_translations
[level
].deemphasis
<< DEEMPH_SHIFT
;
2168 I915_WRITE(BXT_PORT_TX_DW4_GRP(port
), val
);
2170 val
= I915_READ(BXT_PORT_PCS_DW10_LN01(port
));
2171 val
|= TX2_SWING_CALC_INIT
| TX1_SWING_CALC_INIT
;
2172 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port
), val
);
2175 static uint32_t translate_signal_level(int signal_levels
)
2179 switch (signal_levels
) {
2181 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2183 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
2186 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
2189 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
2192 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_3
:
2196 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
2199 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
2202 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
2206 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
2209 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
2213 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
2221 uint32_t ddi_signal_levels(struct intel_dp
*intel_dp
)
2223 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2224 struct drm_device
*dev
= dport
->base
.base
.dev
;
2225 struct intel_encoder
*encoder
= &dport
->base
;
2226 uint8_t train_set
= intel_dp
->train_set
[0];
2227 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2228 DP_TRAIN_PRE_EMPHASIS_MASK
);
2229 enum port port
= dport
->port
;
2232 level
= translate_signal_level(signal_levels
);
2234 if (IS_SKYLAKE(dev
))
2235 skl_ddi_set_iboost(dev
, level
, port
, encoder
->type
);
2236 else if (IS_BROXTON(dev
))
2237 bxt_ddi_vswing_sequence(dev
, level
, port
, encoder
->type
);
2239 return DDI_BUF_TRANS_SELECT(level
);
2242 static void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder
)
2244 struct drm_encoder
*encoder
= &intel_encoder
->base
;
2245 struct drm_device
*dev
= encoder
->dev
;
2246 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2247 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->crtc
);
2248 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
2249 int type
= intel_encoder
->type
;
2252 if (type
== INTEL_OUTPUT_EDP
) {
2253 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2254 intel_edp_panel_on(intel_dp
);
2257 if (IS_SKYLAKE(dev
)) {
2258 uint32_t dpll
= crtc
->config
->ddi_pll_sel
;
2262 * DPLL0 is used for eDP and is the only "private" DPLL (as
2263 * opposed to shared) on SKL
2265 if (type
== INTEL_OUTPUT_EDP
) {
2266 WARN_ON(dpll
!= SKL_DPLL0
);
2268 val
= I915_READ(DPLL_CTRL1
);
2270 val
&= ~(DPLL_CTRL1_HDMI_MODE(dpll
) |
2271 DPLL_CTRL1_SSC(dpll
) |
2272 DPLL_CTRL1_LINK_RATE_MASK(dpll
));
2273 val
|= crtc
->config
->dpll_hw_state
.ctrl1
<< (dpll
* 6);
2275 I915_WRITE(DPLL_CTRL1
, val
);
2276 POSTING_READ(DPLL_CTRL1
);
2279 /* DDI -> PLL mapping */
2280 val
= I915_READ(DPLL_CTRL2
);
2282 val
&= ~(DPLL_CTRL2_DDI_CLK_OFF(port
) |
2283 DPLL_CTRL2_DDI_CLK_SEL_MASK(port
));
2284 val
|= (DPLL_CTRL2_DDI_CLK_SEL(dpll
, port
) |
2285 DPLL_CTRL2_DDI_SEL_OVERRIDE(port
));
2287 I915_WRITE(DPLL_CTRL2
, val
);
2289 } else if (INTEL_INFO(dev
)->gen
< 9) {
2290 WARN_ON(crtc
->config
->ddi_pll_sel
== PORT_CLK_SEL_NONE
);
2291 I915_WRITE(PORT_CLK_SEL(port
), crtc
->config
->ddi_pll_sel
);
2294 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
2295 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2297 intel_ddi_init_dp_buf_reg(intel_encoder
);
2299 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2300 intel_dp_start_link_train(intel_dp
);
2301 intel_dp_complete_link_train(intel_dp
);
2302 if (port
!= PORT_A
|| INTEL_INFO(dev
)->gen
>= 9)
2303 intel_dp_stop_link_train(intel_dp
);
2304 } else if (type
== INTEL_OUTPUT_HDMI
) {
2305 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
2307 if (IS_BROXTON(dev
)) {
2308 hdmi_level
= dev_priv
->vbt
.
2309 ddi_port_info
[port
].hdmi_level_shift
;
2310 bxt_ddi_vswing_sequence(dev
, hdmi_level
, port
,
2313 intel_hdmi
->set_infoframes(encoder
,
2314 crtc
->config
->has_hdmi_sink
,
2315 &crtc
->config
->base
.adjusted_mode
);
2319 static void intel_ddi_post_disable(struct intel_encoder
*intel_encoder
)
2321 struct drm_encoder
*encoder
= &intel_encoder
->base
;
2322 struct drm_device
*dev
= encoder
->dev
;
2323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2324 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
2325 int type
= intel_encoder
->type
;
2329 val
= I915_READ(DDI_BUF_CTL(port
));
2330 if (val
& DDI_BUF_CTL_ENABLE
) {
2331 val
&= ~DDI_BUF_CTL_ENABLE
;
2332 I915_WRITE(DDI_BUF_CTL(port
), val
);
2336 val
= I915_READ(DP_TP_CTL(port
));
2337 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
2338 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2339 I915_WRITE(DP_TP_CTL(port
), val
);
2342 intel_wait_ddi_buf_idle(dev_priv
, port
);
2344 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
2345 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2346 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2347 intel_edp_panel_vdd_on(intel_dp
);
2348 intel_edp_panel_off(intel_dp
);
2351 if (IS_SKYLAKE(dev
))
2352 I915_WRITE(DPLL_CTRL2
, (I915_READ(DPLL_CTRL2
) |
2353 DPLL_CTRL2_DDI_CLK_OFF(port
)));
2354 else if (INTEL_INFO(dev
)->gen
< 9)
2355 I915_WRITE(PORT_CLK_SEL(port
), PORT_CLK_SEL_NONE
);
2358 static void intel_enable_ddi(struct intel_encoder
*intel_encoder
)
2360 struct drm_encoder
*encoder
= &intel_encoder
->base
;
2361 struct drm_crtc
*crtc
= encoder
->crtc
;
2362 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2363 struct drm_device
*dev
= encoder
->dev
;
2364 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2365 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
2366 int type
= intel_encoder
->type
;
2368 if (type
== INTEL_OUTPUT_HDMI
) {
2369 struct intel_digital_port
*intel_dig_port
=
2370 enc_to_dig_port(encoder
);
2372 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2373 * are ignored so nothing special needs to be done besides
2374 * enabling the port.
2376 I915_WRITE(DDI_BUF_CTL(port
),
2377 intel_dig_port
->saved_port_bits
|
2378 DDI_BUF_CTL_ENABLE
);
2379 } else if (type
== INTEL_OUTPUT_EDP
) {
2380 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2382 if (port
== PORT_A
&& INTEL_INFO(dev
)->gen
< 9)
2383 intel_dp_stop_link_train(intel_dp
);
2385 intel_edp_backlight_on(intel_dp
);
2386 intel_psr_enable(intel_dp
);
2387 intel_edp_drrs_enable(intel_dp
);
2390 if (intel_crtc
->config
->has_audio
) {
2391 intel_display_power_get(dev_priv
, POWER_DOMAIN_AUDIO
);
2392 intel_audio_codec_enable(intel_encoder
);
2396 static void intel_disable_ddi(struct intel_encoder
*intel_encoder
)
2398 struct drm_encoder
*encoder
= &intel_encoder
->base
;
2399 struct drm_crtc
*crtc
= encoder
->crtc
;
2400 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2401 int type
= intel_encoder
->type
;
2402 struct drm_device
*dev
= encoder
->dev
;
2403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2405 if (intel_crtc
->config
->has_audio
) {
2406 intel_audio_codec_disable(intel_encoder
);
2407 intel_display_power_put(dev_priv
, POWER_DOMAIN_AUDIO
);
2410 if (type
== INTEL_OUTPUT_EDP
) {
2411 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2413 intel_edp_drrs_disable(intel_dp
);
2414 intel_psr_disable(intel_dp
);
2415 intel_edp_backlight_off(intel_dp
);
2419 static void hsw_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
2420 struct intel_shared_dpll
*pll
)
2422 I915_WRITE(WRPLL_CTL(pll
->id
), pll
->config
.hw_state
.wrpll
);
2423 POSTING_READ(WRPLL_CTL(pll
->id
));
2427 static void hsw_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
2428 struct intel_shared_dpll
*pll
)
2432 val
= I915_READ(WRPLL_CTL(pll
->id
));
2433 I915_WRITE(WRPLL_CTL(pll
->id
), val
& ~WRPLL_PLL_ENABLE
);
2434 POSTING_READ(WRPLL_CTL(pll
->id
));
2437 static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
2438 struct intel_shared_dpll
*pll
,
2439 struct intel_dpll_hw_state
*hw_state
)
2443 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
2446 val
= I915_READ(WRPLL_CTL(pll
->id
));
2447 hw_state
->wrpll
= val
;
2449 return val
& WRPLL_PLL_ENABLE
;
2452 static const char * const hsw_ddi_pll_names
[] = {
2457 static void hsw_shared_dplls_init(struct drm_i915_private
*dev_priv
)
2461 dev_priv
->num_shared_dpll
= 2;
2463 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
2464 dev_priv
->shared_dplls
[i
].id
= i
;
2465 dev_priv
->shared_dplls
[i
].name
= hsw_ddi_pll_names
[i
];
2466 dev_priv
->shared_dplls
[i
].disable
= hsw_ddi_pll_disable
;
2467 dev_priv
->shared_dplls
[i
].enable
= hsw_ddi_pll_enable
;
2468 dev_priv
->shared_dplls
[i
].get_hw_state
=
2469 hsw_ddi_pll_get_hw_state
;
2473 static const char * const skl_ddi_pll_names
[] = {
2479 struct skl_dpll_regs
{
2480 u32 ctl
, cfgcr1
, cfgcr2
;
2483 /* this array is indexed by the *shared* pll id */
2484 static const struct skl_dpll_regs skl_dpll_regs
[3] = {
2488 .cfgcr1
= DPLL1_CFGCR1
,
2489 .cfgcr2
= DPLL1_CFGCR2
,
2494 .cfgcr1
= DPLL2_CFGCR1
,
2495 .cfgcr2
= DPLL2_CFGCR2
,
2500 .cfgcr1
= DPLL3_CFGCR1
,
2501 .cfgcr2
= DPLL3_CFGCR2
,
2505 static void skl_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
2506 struct intel_shared_dpll
*pll
)
2510 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
2512 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2515 val
= I915_READ(DPLL_CTRL1
);
2517 val
&= ~(DPLL_CTRL1_HDMI_MODE(dpll
) | DPLL_CTRL1_SSC(dpll
) |
2518 DPLL_CTRL1_LINK_RATE_MASK(dpll
));
2519 val
|= pll
->config
.hw_state
.ctrl1
<< (dpll
* 6);
2521 I915_WRITE(DPLL_CTRL1
, val
);
2522 POSTING_READ(DPLL_CTRL1
);
2524 I915_WRITE(regs
[pll
->id
].cfgcr1
, pll
->config
.hw_state
.cfgcr1
);
2525 I915_WRITE(regs
[pll
->id
].cfgcr2
, pll
->config
.hw_state
.cfgcr2
);
2526 POSTING_READ(regs
[pll
->id
].cfgcr1
);
2527 POSTING_READ(regs
[pll
->id
].cfgcr2
);
2529 /* the enable bit is always bit 31 */
2530 I915_WRITE(regs
[pll
->id
].ctl
,
2531 I915_READ(regs
[pll
->id
].ctl
) | LCPLL_PLL_ENABLE
);
2533 if (wait_for(I915_READ(DPLL_STATUS
) & DPLL_LOCK(dpll
), 5))
2534 DRM_ERROR("DPLL %d not locked\n", dpll
);
2537 static void skl_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
2538 struct intel_shared_dpll
*pll
)
2540 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
2542 /* the enable bit is always bit 31 */
2543 I915_WRITE(regs
[pll
->id
].ctl
,
2544 I915_READ(regs
[pll
->id
].ctl
) & ~LCPLL_PLL_ENABLE
);
2545 POSTING_READ(regs
[pll
->id
].ctl
);
2548 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
2549 struct intel_shared_dpll
*pll
,
2550 struct intel_dpll_hw_state
*hw_state
)
2554 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
2556 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
2559 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2562 val
= I915_READ(regs
[pll
->id
].ctl
);
2563 if (!(val
& LCPLL_PLL_ENABLE
))
2566 val
= I915_READ(DPLL_CTRL1
);
2567 hw_state
->ctrl1
= (val
>> (dpll
* 6)) & 0x3f;
2569 /* avoid reading back stale values if HDMI mode is not enabled */
2570 if (val
& DPLL_CTRL1_HDMI_MODE(dpll
)) {
2571 hw_state
->cfgcr1
= I915_READ(regs
[pll
->id
].cfgcr1
);
2572 hw_state
->cfgcr2
= I915_READ(regs
[pll
->id
].cfgcr2
);
2578 static void skl_shared_dplls_init(struct drm_i915_private
*dev_priv
)
2582 dev_priv
->num_shared_dpll
= 3;
2584 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
2585 dev_priv
->shared_dplls
[i
].id
= i
;
2586 dev_priv
->shared_dplls
[i
].name
= skl_ddi_pll_names
[i
];
2587 dev_priv
->shared_dplls
[i
].disable
= skl_ddi_pll_disable
;
2588 dev_priv
->shared_dplls
[i
].enable
= skl_ddi_pll_enable
;
2589 dev_priv
->shared_dplls
[i
].get_hw_state
=
2590 skl_ddi_pll_get_hw_state
;
2594 static void broxton_phy_init(struct drm_i915_private
*dev_priv
,
2600 val
= I915_READ(BXT_P_CR_GT_DISP_PWRON
);
2601 val
|= GT_DISPLAY_POWER_ON(phy
);
2602 I915_WRITE(BXT_P_CR_GT_DISP_PWRON
, val
);
2604 /* Considering 10ms timeout until BSpec is updated */
2605 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy
)) & PHY_POWER_GOOD
, 10))
2606 DRM_ERROR("timeout during PHY%d power on\n", phy
);
2608 for (port
= (phy
== DPIO_PHY0
? PORT_B
: PORT_A
);
2609 port
<= (phy
== DPIO_PHY0
? PORT_C
: PORT_A
); port
++) {
2612 for (lane
= 0; lane
< 4; lane
++) {
2613 val
= I915_READ(BXT_PORT_TX_DW14_LN(port
, lane
));
2615 * Note that on CHV this flag is called UPAR, but has
2616 * the same function.
2618 val
&= ~LATENCY_OPTIM
;
2620 val
|= LATENCY_OPTIM
;
2622 I915_WRITE(BXT_PORT_TX_DW14_LN(port
, lane
), val
);
2626 /* Program PLL Rcomp code offset */
2627 val
= I915_READ(BXT_PORT_CL1CM_DW9(phy
));
2628 val
&= ~IREF0RC_OFFSET_MASK
;
2629 val
|= 0xE4 << IREF0RC_OFFSET_SHIFT
;
2630 I915_WRITE(BXT_PORT_CL1CM_DW9(phy
), val
);
2632 val
= I915_READ(BXT_PORT_CL1CM_DW10(phy
));
2633 val
&= ~IREF1RC_OFFSET_MASK
;
2634 val
|= 0xE4 << IREF1RC_OFFSET_SHIFT
;
2635 I915_WRITE(BXT_PORT_CL1CM_DW10(phy
), val
);
2637 /* Program power gating */
2638 val
= I915_READ(BXT_PORT_CL1CM_DW28(phy
));
2639 val
|= OCL1_POWER_DOWN_EN
| DW28_OLDO_DYN_PWR_DOWN_EN
|
2641 I915_WRITE(BXT_PORT_CL1CM_DW28(phy
), val
);
2643 if (phy
== DPIO_PHY0
) {
2644 val
= I915_READ(BXT_PORT_CL2CM_DW6_BC
);
2645 val
|= DW6_OLDO_DYN_PWR_DOWN_EN
;
2646 I915_WRITE(BXT_PORT_CL2CM_DW6_BC
, val
);
2649 val
= I915_READ(BXT_PORT_CL1CM_DW30(phy
));
2650 val
&= ~OCL2_LDOFUSE_PWR_DIS
;
2652 * On PHY1 disable power on the second channel, since no port is
2653 * connected there. On PHY0 both channels have a port, so leave it
2655 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2656 * power down the second channel on PHY0 as well.
2658 if (phy
== DPIO_PHY1
)
2659 val
|= OCL2_LDOFUSE_PWR_DIS
;
2660 I915_WRITE(BXT_PORT_CL1CM_DW30(phy
), val
);
2662 if (phy
== DPIO_PHY0
) {
2665 * PHY0 isn't connected to an RCOMP resistor so copy over
2666 * the corresponding calibrated value from PHY1, and disable
2667 * the automatic calibration on PHY0.
2669 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1
)) & GRC_DONE
,
2671 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2673 val
= I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1
));
2674 val
= (val
& GRC_CODE_MASK
) >> GRC_CODE_SHIFT
;
2675 grc_code
= val
<< GRC_CODE_FAST_SHIFT
|
2676 val
<< GRC_CODE_SLOW_SHIFT
|
2678 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0
), grc_code
);
2680 val
= I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0
));
2681 val
|= GRC_DIS
| GRC_RDY_OVRD
;
2682 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0
), val
);
2685 val
= I915_READ(BXT_PHY_CTL_FAMILY(phy
));
2686 val
|= COMMON_RESET_DIS
;
2687 I915_WRITE(BXT_PHY_CTL_FAMILY(phy
), val
);
2690 void broxton_ddi_phy_init(struct drm_device
*dev
)
2692 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2693 broxton_phy_init(dev
->dev_private
, DPIO_PHY1
);
2694 broxton_phy_init(dev
->dev_private
, DPIO_PHY0
);
2697 static void broxton_phy_uninit(struct drm_i915_private
*dev_priv
,
2702 val
= I915_READ(BXT_PHY_CTL_FAMILY(phy
));
2703 val
&= ~COMMON_RESET_DIS
;
2704 I915_WRITE(BXT_PHY_CTL_FAMILY(phy
), val
);
2707 void broxton_ddi_phy_uninit(struct drm_device
*dev
)
2709 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2711 broxton_phy_uninit(dev_priv
, DPIO_PHY1
);
2712 broxton_phy_uninit(dev_priv
, DPIO_PHY0
);
2714 /* FIXME: do this in broxton_phy_uninit per phy */
2715 I915_WRITE(BXT_P_CR_GT_DISP_PWRON
, 0);
2718 static const char * const bxt_ddi_pll_names
[] = {
2724 static void bxt_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
2725 struct intel_shared_dpll
*pll
)
2728 enum port port
= (enum port
)pll
->id
; /* 1:1 port->PLL mapping */
2730 temp
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
2731 temp
&= ~PORT_PLL_REF_SEL
;
2732 /* Non-SSC reference */
2733 I915_WRITE(BXT_PORT_PLL_ENABLE(port
), temp
);
2735 /* Disable 10 bit clock */
2736 temp
= I915_READ(BXT_PORT_PLL_EBB_4(port
));
2737 temp
&= ~PORT_PLL_10BIT_CLK_ENABLE
;
2738 I915_WRITE(BXT_PORT_PLL_EBB_4(port
), temp
);
2741 temp
= I915_READ(BXT_PORT_PLL_EBB_0(port
));
2742 temp
&= ~(PORT_PLL_P1_MASK
| PORT_PLL_P2_MASK
);
2743 temp
|= pll
->config
.hw_state
.ebb0
;
2744 I915_WRITE(BXT_PORT_PLL_EBB_0(port
), temp
);
2746 /* Write M2 integer */
2747 temp
= I915_READ(BXT_PORT_PLL(port
, 0));
2748 temp
&= ~PORT_PLL_M2_MASK
;
2749 temp
|= pll
->config
.hw_state
.pll0
;
2750 I915_WRITE(BXT_PORT_PLL(port
, 0), temp
);
2753 temp
= I915_READ(BXT_PORT_PLL(port
, 1));
2754 temp
&= ~PORT_PLL_N_MASK
;
2755 temp
|= pll
->config
.hw_state
.pll1
;
2756 I915_WRITE(BXT_PORT_PLL(port
, 1), temp
);
2758 /* Write M2 fraction */
2759 temp
= I915_READ(BXT_PORT_PLL(port
, 2));
2760 temp
&= ~PORT_PLL_M2_FRAC_MASK
;
2761 temp
|= pll
->config
.hw_state
.pll2
;
2762 I915_WRITE(BXT_PORT_PLL(port
, 2), temp
);
2764 /* Write M2 fraction enable */
2765 temp
= I915_READ(BXT_PORT_PLL(port
, 3));
2766 temp
&= ~PORT_PLL_M2_FRAC_ENABLE
;
2767 temp
|= pll
->config
.hw_state
.pll3
;
2768 I915_WRITE(BXT_PORT_PLL(port
, 3), temp
);
2771 temp
= I915_READ(BXT_PORT_PLL(port
, 6));
2772 temp
&= ~PORT_PLL_PROP_COEFF_MASK
;
2773 temp
&= ~PORT_PLL_INT_COEFF_MASK
;
2774 temp
&= ~PORT_PLL_GAIN_CTL_MASK
;
2775 temp
|= pll
->config
.hw_state
.pll6
;
2776 I915_WRITE(BXT_PORT_PLL(port
, 6), temp
);
2778 /* Write calibration val */
2779 temp
= I915_READ(BXT_PORT_PLL(port
, 8));
2780 temp
&= ~PORT_PLL_TARGET_CNT_MASK
;
2781 temp
|= pll
->config
.hw_state
.pll8
;
2782 I915_WRITE(BXT_PORT_PLL(port
, 8), temp
);
2784 temp
= I915_READ(BXT_PORT_PLL(port
, 9));
2785 temp
&= ~PORT_PLL_LOCK_THRESHOLD_MASK
;
2786 temp
|= pll
->config
.hw_state
.pll9
;
2787 I915_WRITE(BXT_PORT_PLL(port
, 9), temp
);
2789 temp
= I915_READ(BXT_PORT_PLL(port
, 10));
2790 temp
&= ~PORT_PLL_DCO_AMP_OVR_EN_H
;
2791 temp
&= ~PORT_PLL_DCO_AMP_MASK
;
2792 temp
|= pll
->config
.hw_state
.pll10
;
2793 I915_WRITE(BXT_PORT_PLL(port
, 10), temp
);
2795 /* Recalibrate with new settings */
2796 temp
= I915_READ(BXT_PORT_PLL_EBB_4(port
));
2797 temp
|= PORT_PLL_RECALIBRATE
;
2798 I915_WRITE(BXT_PORT_PLL_EBB_4(port
), temp
);
2799 temp
&= ~PORT_PLL_10BIT_CLK_ENABLE
;
2800 temp
|= pll
->config
.hw_state
.ebb4
;
2801 I915_WRITE(BXT_PORT_PLL_EBB_4(port
), temp
);
2804 temp
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
2805 temp
|= PORT_PLL_ENABLE
;
2806 I915_WRITE(BXT_PORT_PLL_ENABLE(port
), temp
);
2807 POSTING_READ(BXT_PORT_PLL_ENABLE(port
));
2809 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port
)) &
2810 PORT_PLL_LOCK
), 200))
2811 DRM_ERROR("PLL %d not locked\n", port
);
2814 * While we write to the group register to program all lanes at once we
2815 * can read only lane registers and we pick lanes 0/1 for that.
2817 temp
= I915_READ(BXT_PORT_PCS_DW12_LN01(port
));
2818 temp
&= ~LANE_STAGGER_MASK
;
2819 temp
&= ~LANESTAGGER_STRAP_OVRD
;
2820 temp
|= pll
->config
.hw_state
.pcsdw12
;
2821 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port
), temp
);
2824 static void bxt_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
2825 struct intel_shared_dpll
*pll
)
2827 enum port port
= (enum port
)pll
->id
; /* 1:1 port->PLL mapping */
2830 temp
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
2831 temp
&= ~PORT_PLL_ENABLE
;
2832 I915_WRITE(BXT_PORT_PLL_ENABLE(port
), temp
);
2833 POSTING_READ(BXT_PORT_PLL_ENABLE(port
));
2836 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
2837 struct intel_shared_dpll
*pll
,
2838 struct intel_dpll_hw_state
*hw_state
)
2840 enum port port
= (enum port
)pll
->id
; /* 1:1 port->PLL mapping */
2843 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
2846 val
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
2847 if (!(val
& PORT_PLL_ENABLE
))
2850 hw_state
->ebb0
= I915_READ(BXT_PORT_PLL_EBB_0(port
));
2851 hw_state
->ebb0
&= PORT_PLL_P1_MASK
| PORT_PLL_P2_MASK
;
2853 hw_state
->ebb4
= I915_READ(BXT_PORT_PLL_EBB_4(port
));
2854 hw_state
->ebb4
&= PORT_PLL_10BIT_CLK_ENABLE
;
2856 hw_state
->pll0
= I915_READ(BXT_PORT_PLL(port
, 0));
2857 hw_state
->pll0
&= PORT_PLL_M2_MASK
;
2859 hw_state
->pll1
= I915_READ(BXT_PORT_PLL(port
, 1));
2860 hw_state
->pll1
&= PORT_PLL_N_MASK
;
2862 hw_state
->pll2
= I915_READ(BXT_PORT_PLL(port
, 2));
2863 hw_state
->pll2
&= PORT_PLL_M2_FRAC_MASK
;
2865 hw_state
->pll3
= I915_READ(BXT_PORT_PLL(port
, 3));
2866 hw_state
->pll3
&= PORT_PLL_M2_FRAC_ENABLE
;
2868 hw_state
->pll6
= I915_READ(BXT_PORT_PLL(port
, 6));
2869 hw_state
->pll6
&= PORT_PLL_PROP_COEFF_MASK
|
2870 PORT_PLL_INT_COEFF_MASK
|
2871 PORT_PLL_GAIN_CTL_MASK
;
2873 hw_state
->pll8
= I915_READ(BXT_PORT_PLL(port
, 8));
2874 hw_state
->pll8
&= PORT_PLL_TARGET_CNT_MASK
;
2876 hw_state
->pll9
= I915_READ(BXT_PORT_PLL(port
, 9));
2877 hw_state
->pll9
&= PORT_PLL_LOCK_THRESHOLD_MASK
;
2879 hw_state
->pll10
= I915_READ(BXT_PORT_PLL(port
, 10));
2880 hw_state
->pll10
&= PORT_PLL_DCO_AMP_OVR_EN_H
|
2881 PORT_PLL_DCO_AMP_MASK
;
2884 * While we write to the group register to program all lanes at once we
2885 * can read only lane registers. We configure all lanes the same way, so
2886 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2888 hw_state
->pcsdw12
= I915_READ(BXT_PORT_PCS_DW12_LN01(port
));
2889 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port
) != hw_state
->pcsdw12
))
2890 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2892 I915_READ(BXT_PORT_PCS_DW12_LN23(port
)));
2893 hw_state
->pcsdw12
&= LANE_STAGGER_MASK
| LANESTAGGER_STRAP_OVRD
;
2898 static void bxt_shared_dplls_init(struct drm_i915_private
*dev_priv
)
2902 dev_priv
->num_shared_dpll
= 3;
2904 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
2905 dev_priv
->shared_dplls
[i
].id
= i
;
2906 dev_priv
->shared_dplls
[i
].name
= bxt_ddi_pll_names
[i
];
2907 dev_priv
->shared_dplls
[i
].disable
= bxt_ddi_pll_disable
;
2908 dev_priv
->shared_dplls
[i
].enable
= bxt_ddi_pll_enable
;
2909 dev_priv
->shared_dplls
[i
].get_hw_state
=
2910 bxt_ddi_pll_get_hw_state
;
2914 void intel_ddi_pll_init(struct drm_device
*dev
)
2916 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2917 uint32_t val
= I915_READ(LCPLL_CTL
);
2919 if (IS_SKYLAKE(dev
))
2920 skl_shared_dplls_init(dev_priv
);
2921 else if (IS_BROXTON(dev
))
2922 bxt_shared_dplls_init(dev_priv
);
2924 hsw_shared_dplls_init(dev_priv
);
2926 if (IS_SKYLAKE(dev
)) {
2929 cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
2930 dev_priv
->skl_boot_cdclk
= cdclk_freq
;
2931 if (!(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_ENABLE
))
2932 DRM_ERROR("LCPLL1 is disabled\n");
2934 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
2935 } else if (IS_BROXTON(dev
)) {
2936 broxton_init_cdclk(dev
);
2937 broxton_ddi_phy_init(dev
);
2940 * The LCPLL register should be turned on by the BIOS. For now
2941 * let's just check its state and print errors in case
2942 * something is wrong. Don't even try to turn it on.
2945 if (val
& LCPLL_CD_SOURCE_FCLK
)
2946 DRM_ERROR("CDCLK source is not LCPLL\n");
2948 if (val
& LCPLL_PLL_DISABLE
)
2949 DRM_ERROR("LCPLL is disabled\n");
2953 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
)
2955 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
2956 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
2957 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
2958 enum port port
= intel_dig_port
->port
;
2962 if (I915_READ(DP_TP_CTL(port
)) & DP_TP_CTL_ENABLE
) {
2963 val
= I915_READ(DDI_BUF_CTL(port
));
2964 if (val
& DDI_BUF_CTL_ENABLE
) {
2965 val
&= ~DDI_BUF_CTL_ENABLE
;
2966 I915_WRITE(DDI_BUF_CTL(port
), val
);
2970 val
= I915_READ(DP_TP_CTL(port
));
2971 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
2972 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2973 I915_WRITE(DP_TP_CTL(port
), val
);
2974 POSTING_READ(DP_TP_CTL(port
));
2977 intel_wait_ddi_buf_idle(dev_priv
, port
);
2980 val
= DP_TP_CTL_ENABLE
|
2981 DP_TP_CTL_LINK_TRAIN_PAT1
| DP_TP_CTL_SCRAMBLE_DISABLE
;
2982 if (intel_dp
->is_mst
)
2983 val
|= DP_TP_CTL_MODE_MST
;
2985 val
|= DP_TP_CTL_MODE_SST
;
2986 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
2987 val
|= DP_TP_CTL_ENHANCED_FRAME_ENABLE
;
2989 I915_WRITE(DP_TP_CTL(port
), val
);
2990 POSTING_READ(DP_TP_CTL(port
));
2992 intel_dp
->DP
|= DDI_BUF_CTL_ENABLE
;
2993 I915_WRITE(DDI_BUF_CTL(port
), intel_dp
->DP
);
2994 POSTING_READ(DDI_BUF_CTL(port
));
2999 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
)
3001 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
3002 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
3005 intel_ddi_post_disable(intel_encoder
);
3007 val
= I915_READ(_FDI_RXA_CTL
);
3008 val
&= ~FDI_RX_ENABLE
;
3009 I915_WRITE(_FDI_RXA_CTL
, val
);
3011 val
= I915_READ(_FDI_RXA_MISC
);
3012 val
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
3013 val
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3014 I915_WRITE(_FDI_RXA_MISC
, val
);
3016 val
= I915_READ(_FDI_RXA_CTL
);
3018 I915_WRITE(_FDI_RXA_CTL
, val
);
3020 val
= I915_READ(_FDI_RXA_CTL
);
3021 val
&= ~FDI_RX_PLL_ENABLE
;
3022 I915_WRITE(_FDI_RXA_CTL
, val
);
3025 void intel_ddi_get_config(struct intel_encoder
*encoder
,
3026 struct intel_crtc_state
*pipe_config
)
3028 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
3029 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
3030 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
3031 struct intel_hdmi
*intel_hdmi
;
3032 u32 temp
, flags
= 0;
3034 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
3035 if (temp
& TRANS_DDI_PHSYNC
)
3036 flags
|= DRM_MODE_FLAG_PHSYNC
;
3038 flags
|= DRM_MODE_FLAG_NHSYNC
;
3039 if (temp
& TRANS_DDI_PVSYNC
)
3040 flags
|= DRM_MODE_FLAG_PVSYNC
;
3042 flags
|= DRM_MODE_FLAG_NVSYNC
;
3044 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
3046 switch (temp
& TRANS_DDI_BPC_MASK
) {
3047 case TRANS_DDI_BPC_6
:
3048 pipe_config
->pipe_bpp
= 18;
3050 case TRANS_DDI_BPC_8
:
3051 pipe_config
->pipe_bpp
= 24;
3053 case TRANS_DDI_BPC_10
:
3054 pipe_config
->pipe_bpp
= 30;
3056 case TRANS_DDI_BPC_12
:
3057 pipe_config
->pipe_bpp
= 36;
3063 switch (temp
& TRANS_DDI_MODE_SELECT_MASK
) {
3064 case TRANS_DDI_MODE_SELECT_HDMI
:
3065 pipe_config
->has_hdmi_sink
= true;
3066 intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
3068 if (intel_hdmi
->infoframe_enabled(&encoder
->base
))
3069 pipe_config
->has_infoframe
= true;
3071 case TRANS_DDI_MODE_SELECT_DVI
:
3072 case TRANS_DDI_MODE_SELECT_FDI
:
3074 case TRANS_DDI_MODE_SELECT_DP_SST
:
3075 case TRANS_DDI_MODE_SELECT_DP_MST
:
3076 pipe_config
->has_dp_encoder
= true;
3077 intel_dp_get_m_n(intel_crtc
, pipe_config
);
3083 if (intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_AUDIO
)) {
3084 temp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
3085 if (temp
& AUDIO_OUTPUT_ENABLE(intel_crtc
->pipe
))
3086 pipe_config
->has_audio
= true;
3089 if (encoder
->type
== INTEL_OUTPUT_EDP
&& dev_priv
->vbt
.edp_bpp
&&
3090 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
3092 * This is a big fat ugly hack.
3094 * Some machines in UEFI boot mode provide us a VBT that has 18
3095 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3096 * unknown we fail to light up. Yet the same BIOS boots up with
3097 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3098 * max, not what it tells us to use.
3100 * Note: This will still be broken if the eDP panel is not lit
3101 * up by the BIOS, and thus we can't get the mode at module
3104 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3105 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
3106 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
3109 intel_ddi_clock_get(encoder
, pipe_config
);
3112 static void intel_ddi_destroy(struct drm_encoder
*encoder
)
3114 /* HDMI has nothing special to destroy, so we can go with this. */
3115 intel_dp_encoder_destroy(encoder
);
3118 static bool intel_ddi_compute_config(struct intel_encoder
*encoder
,
3119 struct intel_crtc_state
*pipe_config
)
3121 int type
= encoder
->type
;
3122 int port
= intel_ddi_get_encoder_port(encoder
);
3124 WARN(type
== INTEL_OUTPUT_UNKNOWN
, "compute_config() on unknown output!\n");
3127 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
3129 if (type
== INTEL_OUTPUT_HDMI
)
3130 return intel_hdmi_compute_config(encoder
, pipe_config
);
3132 return intel_dp_compute_config(encoder
, pipe_config
);
3135 static const struct drm_encoder_funcs intel_ddi_funcs
= {
3136 .destroy
= intel_ddi_destroy
,
3139 static struct intel_connector
*
3140 intel_ddi_init_dp_connector(struct intel_digital_port
*intel_dig_port
)
3142 struct intel_connector
*connector
;
3143 enum port port
= intel_dig_port
->port
;
3145 connector
= intel_connector_alloc();
3149 intel_dig_port
->dp
.output_reg
= DDI_BUF_CTL(port
);
3150 if (!intel_dp_init_connector(intel_dig_port
, connector
)) {
3158 static struct intel_connector
*
3159 intel_ddi_init_hdmi_connector(struct intel_digital_port
*intel_dig_port
)
3161 struct intel_connector
*connector
;
3162 enum port port
= intel_dig_port
->port
;
3164 connector
= intel_connector_alloc();
3168 intel_dig_port
->hdmi
.hdmi_reg
= DDI_BUF_CTL(port
);
3169 intel_hdmi_init_connector(intel_dig_port
, connector
);
3174 void intel_ddi_init(struct drm_device
*dev
, enum port port
)
3176 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3177 struct intel_digital_port
*intel_dig_port
;
3178 struct intel_encoder
*intel_encoder
;
3179 struct drm_encoder
*encoder
;
3180 bool init_hdmi
, init_dp
;
3182 init_hdmi
= (dev_priv
->vbt
.ddi_port_info
[port
].supports_dvi
||
3183 dev_priv
->vbt
.ddi_port_info
[port
].supports_hdmi
);
3184 init_dp
= dev_priv
->vbt
.ddi_port_info
[port
].supports_dp
;
3185 if (!init_dp
&& !init_hdmi
) {
3186 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
3192 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
3193 if (!intel_dig_port
)
3196 intel_encoder
= &intel_dig_port
->base
;
3197 encoder
= &intel_encoder
->base
;
3199 drm_encoder_init(dev
, encoder
, &intel_ddi_funcs
,
3200 DRM_MODE_ENCODER_TMDS
);
3202 intel_encoder
->compute_config
= intel_ddi_compute_config
;
3203 intel_encoder
->enable
= intel_enable_ddi
;
3204 intel_encoder
->pre_enable
= intel_ddi_pre_enable
;
3205 intel_encoder
->disable
= intel_disable_ddi
;
3206 intel_encoder
->post_disable
= intel_ddi_post_disable
;
3207 intel_encoder
->get_hw_state
= intel_ddi_get_hw_state
;
3208 intel_encoder
->get_config
= intel_ddi_get_config
;
3210 intel_dig_port
->port
= port
;
3211 intel_dig_port
->saved_port_bits
= I915_READ(DDI_BUF_CTL(port
)) &
3212 (DDI_BUF_PORT_REVERSAL
|
3215 intel_encoder
->type
= INTEL_OUTPUT_UNKNOWN
;
3216 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
3217 intel_encoder
->cloneable
= 0;
3220 if (!intel_ddi_init_dp_connector(intel_dig_port
))
3223 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
3224 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
3227 /* In theory we don't need the encoder->type check, but leave it just in
3228 * case we have some really bad VBTs... */
3229 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
&& init_hdmi
) {
3230 if (!intel_ddi_init_hdmi_connector(intel_dig_port
))
3237 drm_encoder_cleanup(encoder
);
3238 kfree(intel_dig_port
);