2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 struct ddi_buf_trans
{
32 u32 trans1
; /* balance leg enable, de-emph level */
33 u32 trans2
; /* vref sel, vswing */
36 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
37 * them for both DP and FDI transports, allowing those ports to
38 * automatically adapt to HDMI connections as well
40 static const struct ddi_buf_trans hsw_ddi_translations_dp
[] = {
41 { 0x00FFFFFF, 0x0006000E },
42 { 0x00D75FFF, 0x0005000A },
43 { 0x00C30FFF, 0x00040006 },
44 { 0x80AAAFFF, 0x000B0000 },
45 { 0x00FFFFFF, 0x0005000A },
46 { 0x00D75FFF, 0x000C0004 },
47 { 0x80C30FFF, 0x000B0000 },
48 { 0x00FFFFFF, 0x00040006 },
49 { 0x80D75FFF, 0x000B0000 },
52 static const struct ddi_buf_trans hsw_ddi_translations_fdi
[] = {
53 { 0x00FFFFFF, 0x0007000E },
54 { 0x00D75FFF, 0x000F000A },
55 { 0x00C30FFF, 0x00060006 },
56 { 0x00AAAFFF, 0x001E0000 },
57 { 0x00FFFFFF, 0x000F000A },
58 { 0x00D75FFF, 0x00160004 },
59 { 0x00C30FFF, 0x001E0000 },
60 { 0x00FFFFFF, 0x00060006 },
61 { 0x00D75FFF, 0x001E0000 },
64 static const struct ddi_buf_trans hsw_ddi_translations_hdmi
[] = {
65 /* Idx NT mV d T mV d db */
66 { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */
67 { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */
68 { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */
69 { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */
70 { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */
71 { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */
72 { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */
73 { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */
74 { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */
75 { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */
76 { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */
77 { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */
80 static const struct ddi_buf_trans bdw_ddi_translations_edp
[] = {
81 { 0x00FFFFFF, 0x00000012 },
82 { 0x00EBAFFF, 0x00020011 },
83 { 0x00C71FFF, 0x0006000F },
84 { 0x00AAAFFF, 0x000E000A },
85 { 0x00FFFFFF, 0x00020011 },
86 { 0x00DB6FFF, 0x0005000F },
87 { 0x00BEEFFF, 0x000A000C },
88 { 0x00FFFFFF, 0x0005000F },
89 { 0x00DB6FFF, 0x000A000C },
92 static const struct ddi_buf_trans bdw_ddi_translations_dp
[] = {
93 { 0x00FFFFFF, 0x0007000E },
94 { 0x00D75FFF, 0x000E000A },
95 { 0x00BEFFFF, 0x00140006 },
96 { 0x80B2CFFF, 0x001B0002 },
97 { 0x00FFFFFF, 0x000E000A },
98 { 0x00DB6FFF, 0x00160005 },
99 { 0x80C71FFF, 0x001A0002 },
100 { 0x00F7DFFF, 0x00180004 },
101 { 0x80D75FFF, 0x001B0002 },
104 static const struct ddi_buf_trans bdw_ddi_translations_fdi
[] = {
105 { 0x00FFFFFF, 0x0001000E },
106 { 0x00D75FFF, 0x0004000A },
107 { 0x00C30FFF, 0x00070006 },
108 { 0x00AAAFFF, 0x000C0000 },
109 { 0x00FFFFFF, 0x0004000A },
110 { 0x00D75FFF, 0x00090004 },
111 { 0x00C30FFF, 0x000C0000 },
112 { 0x00FFFFFF, 0x00070006 },
113 { 0x00D75FFF, 0x000C0000 },
116 static const struct ddi_buf_trans bdw_ddi_translations_hdmi
[] = {
117 /* Idx NT mV d T mV df db */
118 { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */
119 { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */
120 { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */
121 { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */
122 { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */
123 { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */
124 { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */
125 { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */
126 { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */
127 { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */
130 static const struct ddi_buf_trans skl_ddi_translations_dp
[] = {
131 { 0x00000018, 0x000000a2 },
132 { 0x00004014, 0x0000009B },
133 { 0x00006012, 0x00000088 },
134 { 0x00008010, 0x00000087 },
135 { 0x00000018, 0x0000009B },
136 { 0x00004014, 0x00000088 },
137 { 0x00006012, 0x00000087 },
138 { 0x00000018, 0x00000088 },
139 { 0x00004014, 0x00000087 },
142 /* eDP 1.4 low vswing translation parameters */
143 static const struct ddi_buf_trans skl_ddi_translations_edp
[] = {
144 { 0x00000018, 0x000000a8 },
145 { 0x00002016, 0x000000ab },
146 { 0x00006012, 0x000000a2 },
147 { 0x00008010, 0x00000088 },
148 { 0x00000018, 0x000000ab },
149 { 0x00004014, 0x000000a2 },
150 { 0x00006012, 0x000000a6 },
151 { 0x00000018, 0x000000a2 },
152 { 0x00005013, 0x0000009c },
153 { 0x00000018, 0x00000088 },
157 static const struct ddi_buf_trans skl_ddi_translations_hdmi
[] = {
158 { 0x00000018, 0x000000ac },
159 { 0x00005012, 0x0000009d },
160 { 0x00007011, 0x00000088 },
161 { 0x00000018, 0x000000a1 },
162 { 0x00000018, 0x00000098 },
163 { 0x00004013, 0x00000088 },
164 { 0x00006012, 0x00000087 },
165 { 0x00000018, 0x000000df },
166 { 0x00003015, 0x00000087 },
167 { 0x00003015, 0x000000c7 },
168 { 0x00000018, 0x000000c7 },
171 struct bxt_ddi_buf_trans
{
172 u32 margin
; /* swing value */
173 u32 scale
; /* scale value */
174 u32 enable
; /* scale enable */
176 bool default_index
; /* true if the entry represents default value */
179 /* BSpec does not define separate vswing/pre-emphasis values for eDP.
180 * Using DP values for eDP as well.
182 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp
[] = {
183 /* Idx NT mV diff db */
184 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
185 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
186 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
187 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
188 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
189 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
190 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
191 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
192 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
193 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
196 /* BSpec has 2 recommended values - entries 0 and 8.
197 * Using the entry with higher vswing.
199 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi
[] = {
200 /* Idx NT mV diff db */
201 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
202 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
203 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
204 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
205 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
206 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
207 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
208 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
209 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
210 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
213 static void ddi_get_encoder_port(struct intel_encoder
*intel_encoder
,
214 struct intel_digital_port
**dig_port
,
217 struct drm_encoder
*encoder
= &intel_encoder
->base
;
218 int type
= intel_encoder
->type
;
220 if (type
== INTEL_OUTPUT_DP_MST
) {
221 *dig_port
= enc_to_mst(encoder
)->primary
;
222 *port
= (*dig_port
)->port
;
223 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
||
224 type
== INTEL_OUTPUT_HDMI
|| type
== INTEL_OUTPUT_UNKNOWN
) {
225 *dig_port
= enc_to_dig_port(encoder
);
226 *port
= (*dig_port
)->port
;
227 } else if (type
== INTEL_OUTPUT_ANALOG
) {
231 DRM_ERROR("Invalid DDI encoder type %d\n", type
);
236 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
)
238 struct intel_digital_port
*dig_port
;
241 ddi_get_encoder_port(intel_encoder
, &dig_port
, &port
);
247 intel_dig_port_supports_hdmi(const struct intel_digital_port
*intel_dig_port
)
249 return intel_dig_port
->hdmi
.hdmi_reg
;
253 * Starting with Haswell, DDI port buffers must be programmed with correct
254 * values in advance. The buffer values are different for FDI and DP modes,
255 * but the HDMI/DVI fields are shared among those. So we program the DDI
256 * in either FDI or DP modes only, as HDMI connections will work with both
259 static void intel_prepare_ddi_buffers(struct drm_device
*dev
, enum port port
,
262 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
264 int i
, n_hdmi_entries
, n_dp_entries
, n_edp_entries
, hdmi_default_entry
,
266 int hdmi_level
= dev_priv
->vbt
.ddi_port_info
[port
].hdmi_level_shift
;
267 const struct ddi_buf_trans
*ddi_translations_fdi
;
268 const struct ddi_buf_trans
*ddi_translations_dp
;
269 const struct ddi_buf_trans
*ddi_translations_edp
;
270 const struct ddi_buf_trans
*ddi_translations_hdmi
;
271 const struct ddi_buf_trans
*ddi_translations
;
273 if (IS_BROXTON(dev
)) {
277 /* Vswing programming for HDMI */
278 bxt_ddi_vswing_sequence(dev
, hdmi_level
, port
,
281 } else if (IS_SKYLAKE(dev
)) {
282 ddi_translations_fdi
= NULL
;
283 ddi_translations_dp
= skl_ddi_translations_dp
;
284 n_dp_entries
= ARRAY_SIZE(skl_ddi_translations_dp
);
285 if (dev_priv
->edp_low_vswing
) {
286 ddi_translations_edp
= skl_ddi_translations_edp
;
287 n_edp_entries
= ARRAY_SIZE(skl_ddi_translations_edp
);
289 ddi_translations_edp
= skl_ddi_translations_dp
;
290 n_edp_entries
= ARRAY_SIZE(skl_ddi_translations_dp
);
293 ddi_translations_hdmi
= skl_ddi_translations_hdmi
;
294 n_hdmi_entries
= ARRAY_SIZE(skl_ddi_translations_hdmi
);
295 hdmi_default_entry
= 7;
296 } else if (IS_BROADWELL(dev
)) {
297 ddi_translations_fdi
= bdw_ddi_translations_fdi
;
298 ddi_translations_dp
= bdw_ddi_translations_dp
;
299 ddi_translations_edp
= bdw_ddi_translations_edp
;
300 ddi_translations_hdmi
= bdw_ddi_translations_hdmi
;
301 n_edp_entries
= ARRAY_SIZE(bdw_ddi_translations_edp
);
302 n_dp_entries
= ARRAY_SIZE(bdw_ddi_translations_dp
);
303 n_hdmi_entries
= ARRAY_SIZE(bdw_ddi_translations_hdmi
);
304 hdmi_default_entry
= 7;
305 } else if (IS_HASWELL(dev
)) {
306 ddi_translations_fdi
= hsw_ddi_translations_fdi
;
307 ddi_translations_dp
= hsw_ddi_translations_dp
;
308 ddi_translations_edp
= hsw_ddi_translations_dp
;
309 ddi_translations_hdmi
= hsw_ddi_translations_hdmi
;
310 n_dp_entries
= n_edp_entries
= ARRAY_SIZE(hsw_ddi_translations_dp
);
311 n_hdmi_entries
= ARRAY_SIZE(hsw_ddi_translations_hdmi
);
312 hdmi_default_entry
= 6;
314 WARN(1, "ddi translation table missing\n");
315 ddi_translations_edp
= bdw_ddi_translations_dp
;
316 ddi_translations_fdi
= bdw_ddi_translations_fdi
;
317 ddi_translations_dp
= bdw_ddi_translations_dp
;
318 ddi_translations_hdmi
= bdw_ddi_translations_hdmi
;
319 n_edp_entries
= ARRAY_SIZE(bdw_ddi_translations_edp
);
320 n_dp_entries
= ARRAY_SIZE(bdw_ddi_translations_dp
);
321 n_hdmi_entries
= ARRAY_SIZE(bdw_ddi_translations_hdmi
);
322 hdmi_default_entry
= 7;
327 ddi_translations
= ddi_translations_edp
;
328 size
= n_edp_entries
;
332 ddi_translations
= ddi_translations_dp
;
336 if (intel_dp_is_edp(dev
, PORT_D
)) {
337 ddi_translations
= ddi_translations_edp
;
338 size
= n_edp_entries
;
340 ddi_translations
= ddi_translations_dp
;
345 if (ddi_translations_fdi
)
346 ddi_translations
= ddi_translations_fdi
;
348 ddi_translations
= ddi_translations_dp
;
355 for (i
= 0, reg
= DDI_BUF_TRANS(port
); i
< size
; i
++) {
356 I915_WRITE(reg
, ddi_translations
[i
].trans1
);
358 I915_WRITE(reg
, ddi_translations
[i
].trans2
);
365 /* Choose a good default if VBT is badly populated */
366 if (hdmi_level
== HDMI_LEVEL_SHIFT_UNKNOWN
||
367 hdmi_level
>= n_hdmi_entries
)
368 hdmi_level
= hdmi_default_entry
;
370 /* Entry 9 is for HDMI: */
371 I915_WRITE(reg
, ddi_translations_hdmi
[hdmi_level
].trans1
);
373 I915_WRITE(reg
, ddi_translations_hdmi
[hdmi_level
].trans2
);
377 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
378 * mode and port E for FDI.
380 void intel_prepare_ddi(struct drm_device
*dev
)
382 struct intel_encoder
*intel_encoder
;
383 bool visited
[I915_MAX_PORTS
] = { 0, };
388 for_each_intel_encoder(dev
, intel_encoder
) {
389 struct intel_digital_port
*intel_dig_port
;
393 ddi_get_encoder_port(intel_encoder
, &intel_dig_port
, &port
);
398 supports_hdmi
= intel_dig_port
&&
399 intel_dig_port_supports_hdmi(intel_dig_port
);
401 intel_prepare_ddi_buffers(dev
, port
, supports_hdmi
);
402 visited
[port
] = true;
406 static void intel_wait_ddi_buf_idle(struct drm_i915_private
*dev_priv
,
409 uint32_t reg
= DDI_BUF_CTL(port
);
412 for (i
= 0; i
< 16; i
++) {
414 if (I915_READ(reg
) & DDI_BUF_IS_IDLE
)
417 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port
));
420 /* Starting with Haswell, different DDI ports can work in FDI mode for
421 * connection to the PCH-located connectors. For this, it is necessary to train
422 * both the DDI port and PCH receiver for the desired DDI buffer settings.
424 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
425 * please note that when FDI mode is active on DDI E, it shares 2 lines with
426 * DDI A (which is used for eDP)
429 void hsw_fdi_link_train(struct drm_crtc
*crtc
)
431 struct drm_device
*dev
= crtc
->dev
;
432 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
433 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
434 u32 temp
, i
, rx_ctl_val
;
436 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
437 * mode set "sequence for CRT port" document:
438 * - TP1 to TP2 time with the default value
441 * WaFDIAutoLinkSetTimingOverrride:hsw
443 I915_WRITE(_FDI_RXA_MISC
, FDI_RX_PWRDN_LANE1_VAL(2) |
444 FDI_RX_PWRDN_LANE0_VAL(2) |
445 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
447 /* Enable the PCH Receiver FDI PLL */
448 rx_ctl_val
= dev_priv
->fdi_rx_config
| FDI_RX_ENHANCE_FRAME_ENABLE
|
450 FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
451 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
452 POSTING_READ(_FDI_RXA_CTL
);
455 /* Switch from Rawclk to PCDclk */
456 rx_ctl_val
|= FDI_PCDCLK
;
457 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
459 /* Configure Port Clock Select */
460 I915_WRITE(PORT_CLK_SEL(PORT_E
), intel_crtc
->config
->ddi_pll_sel
);
461 WARN_ON(intel_crtc
->config
->ddi_pll_sel
!= PORT_CLK_SEL_SPLL
);
463 /* Start the training iterating through available voltages and emphasis,
464 * testing each value twice. */
465 for (i
= 0; i
< ARRAY_SIZE(hsw_ddi_translations_fdi
) * 2; i
++) {
466 /* Configure DP_TP_CTL with auto-training */
467 I915_WRITE(DP_TP_CTL(PORT_E
),
468 DP_TP_CTL_FDI_AUTOTRAIN
|
469 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
470 DP_TP_CTL_LINK_TRAIN_PAT1
|
473 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
474 * DDI E does not support port reversal, the functionality is
475 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
476 * port reversal bit */
477 I915_WRITE(DDI_BUF_CTL(PORT_E
),
479 ((intel_crtc
->config
->fdi_lanes
- 1) << 1) |
480 DDI_BUF_TRANS_SELECT(i
/ 2));
481 POSTING_READ(DDI_BUF_CTL(PORT_E
));
485 /* Program PCH FDI Receiver TU */
486 I915_WRITE(_FDI_RXA_TUSIZE1
, TU_SIZE(64));
488 /* Enable PCH FDI Receiver with auto-training */
489 rx_ctl_val
|= FDI_RX_ENABLE
| FDI_LINK_TRAIN_AUTO
;
490 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
491 POSTING_READ(_FDI_RXA_CTL
);
493 /* Wait for FDI receiver lane calibration */
496 /* Unset FDI_RX_MISC pwrdn lanes */
497 temp
= I915_READ(_FDI_RXA_MISC
);
498 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
499 I915_WRITE(_FDI_RXA_MISC
, temp
);
500 POSTING_READ(_FDI_RXA_MISC
);
502 /* Wait for FDI auto training time */
505 temp
= I915_READ(DP_TP_STATUS(PORT_E
));
506 if (temp
& DP_TP_STATUS_AUTOTRAIN_DONE
) {
507 DRM_DEBUG_KMS("FDI link training done on step %d\n", i
);
509 /* Enable normal pixel sending for FDI */
510 I915_WRITE(DP_TP_CTL(PORT_E
),
511 DP_TP_CTL_FDI_AUTOTRAIN
|
512 DP_TP_CTL_LINK_TRAIN_NORMAL
|
513 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
519 temp
= I915_READ(DDI_BUF_CTL(PORT_E
));
520 temp
&= ~DDI_BUF_CTL_ENABLE
;
521 I915_WRITE(DDI_BUF_CTL(PORT_E
), temp
);
522 POSTING_READ(DDI_BUF_CTL(PORT_E
));
524 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
525 temp
= I915_READ(DP_TP_CTL(PORT_E
));
526 temp
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
527 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
528 I915_WRITE(DP_TP_CTL(PORT_E
), temp
);
529 POSTING_READ(DP_TP_CTL(PORT_E
));
531 intel_wait_ddi_buf_idle(dev_priv
, PORT_E
);
533 rx_ctl_val
&= ~FDI_RX_ENABLE
;
534 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
535 POSTING_READ(_FDI_RXA_CTL
);
537 /* Reset FDI_RX_MISC pwrdn lanes */
538 temp
= I915_READ(_FDI_RXA_MISC
);
539 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
540 temp
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
541 I915_WRITE(_FDI_RXA_MISC
, temp
);
542 POSTING_READ(_FDI_RXA_MISC
);
545 DRM_ERROR("FDI link training failed!\n");
548 void intel_ddi_init_dp_buf_reg(struct intel_encoder
*encoder
)
550 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
551 struct intel_digital_port
*intel_dig_port
=
552 enc_to_dig_port(&encoder
->base
);
554 intel_dp
->DP
= intel_dig_port
->saved_port_bits
|
555 DDI_BUF_CTL_ENABLE
| DDI_BUF_TRANS_SELECT(0);
556 intel_dp
->DP
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
560 static struct intel_encoder
*
561 intel_ddi_get_crtc_encoder(struct drm_crtc
*crtc
)
563 struct drm_device
*dev
= crtc
->dev
;
564 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
565 struct intel_encoder
*intel_encoder
, *ret
= NULL
;
566 int num_encoders
= 0;
568 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
573 if (num_encoders
!= 1)
574 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders
,
575 pipe_name(intel_crtc
->pipe
));
581 struct intel_encoder
*
582 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state
*crtc_state
)
584 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
585 struct intel_encoder
*ret
= NULL
;
586 struct drm_atomic_state
*state
;
587 struct drm_connector
*connector
;
588 struct drm_connector_state
*connector_state
;
589 int num_encoders
= 0;
592 state
= crtc_state
->base
.state
;
594 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
595 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
598 ret
= to_intel_encoder(connector_state
->best_encoder
);
602 WARN(num_encoders
!= 1, "%d encoders on crtc for pipe %c\n", num_encoders
,
603 pipe_name(crtc
->pipe
));
610 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
616 /* Constraints for PLL good behavior */
622 #define abs_diff(a, b) ({ \
623 typeof(a) __a = (a); \
624 typeof(b) __b = (b); \
625 (void) (&__a == &__b); \
626 __a > __b ? (__a - __b) : (__b - __a); })
628 struct hsw_wrpll_rnp
{
632 static unsigned hsw_wrpll_get_budget_for_freq(int clock
)
706 static void hsw_wrpll_update_rnp(uint64_t freq2k
, unsigned budget
,
707 unsigned r2
, unsigned n2
, unsigned p
,
708 struct hsw_wrpll_rnp
*best
)
710 uint64_t a
, b
, c
, d
, diff
, diff_best
;
712 /* No best (r,n,p) yet */
721 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
725 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
728 * and we would like delta <= budget.
730 * If the discrepancy is above the PPM-based budget, always prefer to
731 * improve upon the previous solution. However, if you're within the
732 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
734 a
= freq2k
* budget
* p
* r2
;
735 b
= freq2k
* budget
* best
->p
* best
->r2
;
736 diff
= abs_diff(freq2k
* p
* r2
, LC_FREQ_2K
* n2
);
737 diff_best
= abs_diff(freq2k
* best
->p
* best
->r2
,
738 LC_FREQ_2K
* best
->n2
);
740 d
= 1000000 * diff_best
;
742 if (a
< c
&& b
< d
) {
743 /* If both are above the budget, pick the closer */
744 if (best
->p
* best
->r2
* diff
< p
* r2
* diff_best
) {
749 } else if (a
>= c
&& b
< d
) {
750 /* If A is below the threshold but B is above it? Update. */
754 } else if (a
>= c
&& b
>= d
) {
755 /* Both are below the limit, so pick the higher n2/(r2*r2) */
756 if (n2
* best
->r2
* best
->r2
> best
->n2
* r2
* r2
) {
762 /* Otherwise a < c && b >= d, do nothing */
765 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private
*dev_priv
, int reg
)
767 int refclk
= LC_FREQ
;
771 wrpll
= I915_READ(reg
);
772 switch (wrpll
& WRPLL_PLL_REF_MASK
) {
774 case WRPLL_PLL_NON_SSC
:
776 * We could calculate spread here, but our checking
777 * code only cares about 5% accuracy, and spread is a max of
782 case WRPLL_PLL_LCPLL
:
786 WARN(1, "bad wrpll refclk\n");
790 r
= wrpll
& WRPLL_DIVIDER_REF_MASK
;
791 p
= (wrpll
& WRPLL_DIVIDER_POST_MASK
) >> WRPLL_DIVIDER_POST_SHIFT
;
792 n
= (wrpll
& WRPLL_DIVIDER_FB_MASK
) >> WRPLL_DIVIDER_FB_SHIFT
;
794 /* Convert to KHz, p & r have a fixed point portion */
795 return (refclk
* n
* 100) / (p
* r
);
798 static int skl_calc_wrpll_link(struct drm_i915_private
*dev_priv
,
801 uint32_t cfgcr1_reg
, cfgcr2_reg
;
802 uint32_t cfgcr1_val
, cfgcr2_val
;
803 uint32_t p0
, p1
, p2
, dco_freq
;
805 cfgcr1_reg
= GET_CFG_CR1_REG(dpll
);
806 cfgcr2_reg
= GET_CFG_CR2_REG(dpll
);
808 cfgcr1_val
= I915_READ(cfgcr1_reg
);
809 cfgcr2_val
= I915_READ(cfgcr2_reg
);
811 p0
= cfgcr2_val
& DPLL_CFGCR2_PDIV_MASK
;
812 p2
= cfgcr2_val
& DPLL_CFGCR2_KDIV_MASK
;
814 if (cfgcr2_val
& DPLL_CFGCR2_QDIV_MODE(1))
815 p1
= (cfgcr2_val
& DPLL_CFGCR2_QDIV_RATIO_MASK
) >> 8;
821 case DPLL_CFGCR2_PDIV_1
:
824 case DPLL_CFGCR2_PDIV_2
:
827 case DPLL_CFGCR2_PDIV_3
:
830 case DPLL_CFGCR2_PDIV_7
:
836 case DPLL_CFGCR2_KDIV_5
:
839 case DPLL_CFGCR2_KDIV_2
:
842 case DPLL_CFGCR2_KDIV_3
:
845 case DPLL_CFGCR2_KDIV_1
:
850 dco_freq
= (cfgcr1_val
& DPLL_CFGCR1_DCO_INTEGER_MASK
) * 24 * 1000;
852 dco_freq
+= (((cfgcr1_val
& DPLL_CFGCR1_DCO_FRACTION_MASK
) >> 9) * 24 *
855 return dco_freq
/ (p0
* p1
* p2
* 5);
859 static void skl_ddi_clock_get(struct intel_encoder
*encoder
,
860 struct intel_crtc_state
*pipe_config
)
862 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
864 uint32_t dpll_ctl1
, dpll
;
866 dpll
= pipe_config
->ddi_pll_sel
;
868 dpll_ctl1
= I915_READ(DPLL_CTRL1
);
870 if (dpll_ctl1
& DPLL_CTRL1_HDMI_MODE(dpll
)) {
871 link_clock
= skl_calc_wrpll_link(dev_priv
, dpll
);
873 link_clock
= dpll_ctl1
& DPLL_CTRL1_LINK_RATE_MASK(dpll
);
874 link_clock
>>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll
);
876 switch (link_clock
) {
877 case DPLL_CTRL1_LINK_RATE_810
:
880 case DPLL_CTRL1_LINK_RATE_1080
:
883 case DPLL_CTRL1_LINK_RATE_1350
:
886 case DPLL_CTRL1_LINK_RATE_1620
:
889 case DPLL_CTRL1_LINK_RATE_2160
:
892 case DPLL_CTRL1_LINK_RATE_2700
:
896 WARN(1, "Unsupported link rate\n");
902 pipe_config
->port_clock
= link_clock
;
904 if (pipe_config
->has_dp_encoder
)
905 pipe_config
->base
.adjusted_mode
.crtc_clock
=
906 intel_dotclock_calculate(pipe_config
->port_clock
,
907 &pipe_config
->dp_m_n
);
909 pipe_config
->base
.adjusted_mode
.crtc_clock
= pipe_config
->port_clock
;
912 static void hsw_ddi_clock_get(struct intel_encoder
*encoder
,
913 struct intel_crtc_state
*pipe_config
)
915 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
919 val
= pipe_config
->ddi_pll_sel
;
920 switch (val
& PORT_CLK_SEL_MASK
) {
921 case PORT_CLK_SEL_LCPLL_810
:
924 case PORT_CLK_SEL_LCPLL_1350
:
927 case PORT_CLK_SEL_LCPLL_2700
:
930 case PORT_CLK_SEL_WRPLL1
:
931 link_clock
= hsw_ddi_calc_wrpll_link(dev_priv
, WRPLL_CTL1
);
933 case PORT_CLK_SEL_WRPLL2
:
934 link_clock
= hsw_ddi_calc_wrpll_link(dev_priv
, WRPLL_CTL2
);
936 case PORT_CLK_SEL_SPLL
:
937 pll
= I915_READ(SPLL_CTL
) & SPLL_PLL_FREQ_MASK
;
938 if (pll
== SPLL_PLL_FREQ_810MHz
)
940 else if (pll
== SPLL_PLL_FREQ_1350MHz
)
942 else if (pll
== SPLL_PLL_FREQ_2700MHz
)
945 WARN(1, "bad spll freq\n");
950 WARN(1, "bad port clock sel\n");
954 pipe_config
->port_clock
= link_clock
* 2;
956 if (pipe_config
->has_pch_encoder
)
957 pipe_config
->base
.adjusted_mode
.crtc_clock
=
958 intel_dotclock_calculate(pipe_config
->port_clock
,
959 &pipe_config
->fdi_m_n
);
960 else if (pipe_config
->has_dp_encoder
)
961 pipe_config
->base
.adjusted_mode
.crtc_clock
=
962 intel_dotclock_calculate(pipe_config
->port_clock
,
963 &pipe_config
->dp_m_n
);
965 pipe_config
->base
.adjusted_mode
.crtc_clock
= pipe_config
->port_clock
;
968 static int bxt_calc_pll_link(struct drm_i915_private
*dev_priv
,
969 enum intel_dpll_id dpll
)
971 /* FIXME formula not available in bspec */
975 static void bxt_ddi_clock_get(struct intel_encoder
*encoder
,
976 struct intel_crtc_state
*pipe_config
)
978 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
979 enum port port
= intel_ddi_get_encoder_port(encoder
);
980 uint32_t dpll
= port
;
982 pipe_config
->port_clock
=
983 bxt_calc_pll_link(dev_priv
, dpll
);
985 if (pipe_config
->has_dp_encoder
)
986 pipe_config
->base
.adjusted_mode
.crtc_clock
=
987 intel_dotclock_calculate(pipe_config
->port_clock
,
988 &pipe_config
->dp_m_n
);
990 pipe_config
->base
.adjusted_mode
.crtc_clock
=
991 pipe_config
->port_clock
;
994 void intel_ddi_clock_get(struct intel_encoder
*encoder
,
995 struct intel_crtc_state
*pipe_config
)
997 struct drm_device
*dev
= encoder
->base
.dev
;
999 if (INTEL_INFO(dev
)->gen
<= 8)
1000 hsw_ddi_clock_get(encoder
, pipe_config
);
1001 else if (IS_SKYLAKE(dev
))
1002 skl_ddi_clock_get(encoder
, pipe_config
);
1003 else if (IS_BROXTON(dev
))
1004 bxt_ddi_clock_get(encoder
, pipe_config
);
1008 hsw_ddi_calculate_wrpll(int clock
/* in Hz */,
1009 unsigned *r2_out
, unsigned *n2_out
, unsigned *p_out
)
1013 struct hsw_wrpll_rnp best
= { 0, 0, 0 };
1016 freq2k
= clock
/ 100;
1018 budget
= hsw_wrpll_get_budget_for_freq(clock
);
1020 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1021 * and directly pass the LC PLL to it. */
1022 if (freq2k
== 5400000) {
1030 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1033 * We want R so that REF_MIN <= Ref <= REF_MAX.
1034 * Injecting R2 = 2 * R gives:
1035 * REF_MAX * r2 > LC_FREQ * 2 and
1036 * REF_MIN * r2 < LC_FREQ * 2
1038 * Which means the desired boundaries for r2 are:
1039 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1042 for (r2
= LC_FREQ
* 2 / REF_MAX
+ 1;
1043 r2
<= LC_FREQ
* 2 / REF_MIN
;
1047 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1049 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1050 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1051 * VCO_MAX * r2 > n2 * LC_FREQ and
1052 * VCO_MIN * r2 < n2 * LC_FREQ)
1054 * Which means the desired boundaries for n2 are:
1055 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1057 for (n2
= VCO_MIN
* r2
/ LC_FREQ
+ 1;
1058 n2
<= VCO_MAX
* r2
/ LC_FREQ
;
1061 for (p
= P_MIN
; p
<= P_MAX
; p
+= P_INC
)
1062 hsw_wrpll_update_rnp(freq2k
, budget
,
1073 hsw_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1074 struct intel_crtc_state
*crtc_state
,
1075 struct intel_encoder
*intel_encoder
,
1078 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
1079 struct intel_shared_dpll
*pll
;
1083 hsw_ddi_calculate_wrpll(clock
* 1000, &r2
, &n2
, &p
);
1085 val
= WRPLL_PLL_ENABLE
| WRPLL_PLL_LCPLL
|
1086 WRPLL_DIVIDER_REFERENCE(r2
) | WRPLL_DIVIDER_FEEDBACK(n2
) |
1087 WRPLL_DIVIDER_POST(p
);
1089 memset(&crtc_state
->dpll_hw_state
, 0,
1090 sizeof(crtc_state
->dpll_hw_state
));
1092 crtc_state
->dpll_hw_state
.wrpll
= val
;
1094 pll
= intel_get_shared_dpll(intel_crtc
, crtc_state
);
1096 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1097 pipe_name(intel_crtc
->pipe
));
1101 crtc_state
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL(pll
->id
);
1107 struct skl_wrpll_params
{
1108 uint32_t dco_fraction
;
1109 uint32_t dco_integer
;
1110 uint32_t qdiv_ratio
;
1114 uint32_t central_freq
;
1117 static void skl_wrpll_params_populate(struct skl_wrpll_params
*params
,
1119 uint64_t central_freq
,
1120 uint32_t p0
, uint32_t p1
, uint32_t p2
)
1124 switch (central_freq
) {
1126 params
->central_freq
= 0;
1129 params
->central_freq
= 1;
1132 params
->central_freq
= 3;
1149 WARN(1, "Incorrect PDiv\n");
1166 WARN(1, "Incorrect KDiv\n");
1169 params
->qdiv_ratio
= p1
;
1170 params
->qdiv_mode
= (params
->qdiv_ratio
== 1) ? 0 : 1;
1172 dco_freq
= p0
* p1
* p2
* afe_clock
;
1175 * Intermediate values are in Hz.
1176 * Divide by MHz to match bsepc
1178 params
->dco_integer
= div_u64(dco_freq
, 24 * MHz(1));
1179 params
->dco_fraction
=
1180 div_u64((div_u64(dco_freq
, 24) -
1181 params
->dco_integer
* MHz(1)) * 0x8000, MHz(1));
1185 skl_ddi_calculate_wrpll(int clock
/* in Hz */,
1186 struct skl_wrpll_params
*wrpll_params
)
1188 uint64_t afe_clock
= clock
* 5; /* AFE Clock is 5x Pixel clock */
1189 uint64_t dco_central_freq
[3] = {8400000000ULL,
1192 uint32_t min_dco_deviation
= 400;
1193 uint32_t min_dco_index
= 3;
1194 uint32_t P0
[4] = {1, 2, 3, 7};
1195 uint32_t P2
[4] = {1, 2, 3, 5};
1197 uint32_t candidate_p
= 0;
1198 uint32_t candidate_p0
[3] = {0}, candidate_p1
[3] = {0};
1199 uint32_t candidate_p2
[3] = {0};
1200 uint32_t dco_central_freq_deviation
[3];
1201 uint32_t i
, P1
, k
, dco_count
;
1202 bool retry_with_odd
= false;
1204 /* Determine P0, P1 or P2 */
1205 for (dco_count
= 0; dco_count
< 3; dco_count
++) {
1208 div64_u64(dco_central_freq
[dco_count
], afe_clock
);
1209 if (retry_with_odd
== false)
1210 candidate_p
= (candidate_p
% 2 == 0 ?
1211 candidate_p
: candidate_p
+ 1);
1213 for (P1
= 1; P1
< candidate_p
; P1
++) {
1214 for (i
= 0; i
< 4; i
++) {
1215 if (!(P0
[i
] != 1 || P1
== 1))
1218 for (k
= 0; k
< 4; k
++) {
1219 if (P1
!= 1 && P2
[k
] != 2)
1222 if (candidate_p
== P0
[i
] * P1
* P2
[k
]) {
1223 /* Found possible P0, P1, P2 */
1225 candidate_p0
[dco_count
] = P0
[i
];
1226 candidate_p1
[dco_count
] = P1
;
1227 candidate_p2
[dco_count
] = P2
[k
];
1237 dco_central_freq_deviation
[dco_count
] =
1239 abs_diff(candidate_p
* afe_clock
,
1240 dco_central_freq
[dco_count
]),
1241 dco_central_freq
[dco_count
]);
1243 if (dco_central_freq_deviation
[dco_count
] <
1244 min_dco_deviation
) {
1246 dco_central_freq_deviation
[dco_count
];
1247 min_dco_index
= dco_count
;
1251 if (min_dco_index
> 2 && dco_count
== 2) {
1252 /* oh well, we tried... */
1256 retry_with_odd
= true;
1261 if (WARN(min_dco_index
> 2,
1262 "No valid parameters found for pixel clock: %dHz\n", clock
))
1265 skl_wrpll_params_populate(wrpll_params
,
1267 dco_central_freq
[min_dco_index
],
1268 candidate_p0
[min_dco_index
],
1269 candidate_p1
[min_dco_index
],
1270 candidate_p2
[min_dco_index
]);
1277 skl_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1278 struct intel_crtc_state
*crtc_state
,
1279 struct intel_encoder
*intel_encoder
,
1282 struct intel_shared_dpll
*pll
;
1283 uint32_t ctrl1
, cfgcr1
, cfgcr2
;
1286 * See comment in intel_dpll_hw_state to understand why we always use 0
1287 * as the DPLL id in this function.
1290 ctrl1
= DPLL_CTRL1_OVERRIDE(0);
1292 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
1293 struct skl_wrpll_params wrpll_params
= { 0, };
1295 ctrl1
|= DPLL_CTRL1_HDMI_MODE(0);
1297 if (!skl_ddi_calculate_wrpll(clock
* 1000, &wrpll_params
))
1300 cfgcr1
= DPLL_CFGCR1_FREQ_ENABLE
|
1301 DPLL_CFGCR1_DCO_FRACTION(wrpll_params
.dco_fraction
) |
1302 wrpll_params
.dco_integer
;
1304 cfgcr2
= DPLL_CFGCR2_QDIV_RATIO(wrpll_params
.qdiv_ratio
) |
1305 DPLL_CFGCR2_QDIV_MODE(wrpll_params
.qdiv_mode
) |
1306 DPLL_CFGCR2_KDIV(wrpll_params
.kdiv
) |
1307 DPLL_CFGCR2_PDIV(wrpll_params
.pdiv
) |
1308 wrpll_params
.central_freq
;
1309 } else if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
) {
1310 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1311 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1313 switch (intel_dp
->link_bw
) {
1314 case DP_LINK_BW_1_62
:
1315 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
, 0);
1317 case DP_LINK_BW_2_7
:
1318 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350
, 0);
1320 case DP_LINK_BW_5_4
:
1321 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700
, 0);
1325 cfgcr1
= cfgcr2
= 0;
1329 memset(&crtc_state
->dpll_hw_state
, 0,
1330 sizeof(crtc_state
->dpll_hw_state
));
1332 crtc_state
->dpll_hw_state
.ctrl1
= ctrl1
;
1333 crtc_state
->dpll_hw_state
.cfgcr1
= cfgcr1
;
1334 crtc_state
->dpll_hw_state
.cfgcr2
= cfgcr2
;
1336 pll
= intel_get_shared_dpll(intel_crtc
, crtc_state
);
1338 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1339 pipe_name(intel_crtc
->pipe
));
1343 /* shared DPLL id 0 is DPLL 1 */
1344 crtc_state
->ddi_pll_sel
= pll
->id
+ 1;
1349 /* bxt clock parameters */
1350 struct bxt_clk_div
{
1360 /* pre-calculated values for DP linkrates */
1361 static const struct bxt_clk_div bxt_dp_clk_val
[] = {
1362 {162000, 4, 2, 32, 1677722, 1, 1},
1363 {270000, 4, 1, 27, 0, 0, 1},
1364 {540000, 2, 1, 27, 0, 0, 1},
1365 {216000, 3, 2, 32, 1677722, 1, 1},
1366 {243000, 4, 1, 24, 1258291, 1, 1},
1367 {324000, 4, 1, 32, 1677722, 1, 1},
1368 {432000, 3, 1, 32, 1677722, 1, 1}
1372 bxt_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1373 struct intel_crtc_state
*crtc_state
,
1374 struct intel_encoder
*intel_encoder
,
1377 struct intel_shared_dpll
*pll
;
1378 struct bxt_clk_div clk_div
= {0};
1380 uint32_t prop_coef
, int_coef
, gain_ctl
, targ_cnt
;
1381 uint32_t dcoampovr_en_h
, dco_amp
, lanestagger
;
1383 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
1384 intel_clock_t best_clock
;
1386 /* Calculate HDMI div */
1388 * FIXME: tie the following calculation into
1389 * i9xx_crtc_compute_clock
1391 if (!bxt_find_best_dpll(crtc_state
, clock
, &best_clock
)) {
1392 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1393 clock
, pipe_name(intel_crtc
->pipe
));
1397 clk_div
.p1
= best_clock
.p1
;
1398 clk_div
.p2
= best_clock
.p2
;
1399 WARN_ON(best_clock
.m1
!= 2);
1400 clk_div
.n
= best_clock
.n
;
1401 clk_div
.m2_int
= best_clock
.m2
>> 22;
1402 clk_div
.m2_frac
= best_clock
.m2
& ((1 << 22) - 1);
1403 clk_div
.m2_frac_en
= clk_div
.m2_frac
!= 0;
1405 vco
= best_clock
.vco
;
1406 } else if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
1407 intel_encoder
->type
== INTEL_OUTPUT_EDP
) {
1410 clk_div
= bxt_dp_clk_val
[0];
1411 for (i
= 0; i
< ARRAY_SIZE(bxt_dp_clk_val
); ++i
) {
1412 if (bxt_dp_clk_val
[i
].clock
== clock
) {
1413 clk_div
= bxt_dp_clk_val
[i
];
1417 vco
= clock
* 10 / 2 * clk_div
.p1
* clk_div
.p2
;
1422 if (vco
>= 6200000 && vco
<= 6480000) {
1427 } else if ((vco
> 5400000 && vco
< 6200000) ||
1428 (vco
>= 4800000 && vco
< 5400000)) {
1433 if (vco
>= 4800000 && vco
< 5400000)
1435 } else if (vco
== 5400000) {
1441 DRM_ERROR("Invalid VCO\n");
1445 memset(&crtc_state
->dpll_hw_state
, 0,
1446 sizeof(crtc_state
->dpll_hw_state
));
1450 else if (clock
> 135000)
1452 else if (clock
> 67000)
1454 else if (clock
> 33000)
1459 crtc_state
->dpll_hw_state
.ebb0
=
1460 PORT_PLL_P1(clk_div
.p1
) | PORT_PLL_P2(clk_div
.p2
);
1461 crtc_state
->dpll_hw_state
.pll0
= clk_div
.m2_int
;
1462 crtc_state
->dpll_hw_state
.pll1
= PORT_PLL_N(clk_div
.n
);
1463 crtc_state
->dpll_hw_state
.pll2
= clk_div
.m2_frac
;
1465 if (clk_div
.m2_frac_en
)
1466 crtc_state
->dpll_hw_state
.pll3
=
1467 PORT_PLL_M2_FRAC_ENABLE
;
1469 crtc_state
->dpll_hw_state
.pll6
=
1470 prop_coef
| PORT_PLL_INT_COEFF(int_coef
);
1471 crtc_state
->dpll_hw_state
.pll6
|=
1472 PORT_PLL_GAIN_CTL(gain_ctl
);
1474 crtc_state
->dpll_hw_state
.pll8
= targ_cnt
;
1477 crtc_state
->dpll_hw_state
.pll10
= PORT_PLL_DCO_AMP_OVR_EN_H
;
1479 crtc_state
->dpll_hw_state
.pll10
|= PORT_PLL_DCO_AMP(dco_amp
);
1481 crtc_state
->dpll_hw_state
.pcsdw12
=
1482 LANESTAGGER_STRAP_OVRD
| lanestagger
;
1484 pll
= intel_get_shared_dpll(intel_crtc
, crtc_state
);
1486 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1487 pipe_name(intel_crtc
->pipe
));
1491 /* shared DPLL id 0 is DPLL A */
1492 crtc_state
->ddi_pll_sel
= pll
->id
;
1498 * Tries to find a *shared* PLL for the CRTC and store it in
1499 * intel_crtc->ddi_pll_sel.
1501 * For private DPLLs, compute_config() should do the selection for us. This
1502 * function should be folded into compute_config() eventually.
1504 bool intel_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1505 struct intel_crtc_state
*crtc_state
)
1507 struct drm_device
*dev
= intel_crtc
->base
.dev
;
1508 struct intel_encoder
*intel_encoder
=
1509 intel_ddi_get_crtc_new_encoder(crtc_state
);
1510 int clock
= crtc_state
->port_clock
;
1512 if (IS_SKYLAKE(dev
))
1513 return skl_ddi_pll_select(intel_crtc
, crtc_state
,
1514 intel_encoder
, clock
);
1515 else if (IS_BROXTON(dev
))
1516 return bxt_ddi_pll_select(intel_crtc
, crtc_state
,
1517 intel_encoder
, clock
);
1519 return hsw_ddi_pll_select(intel_crtc
, crtc_state
,
1520 intel_encoder
, clock
);
1523 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
)
1525 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1526 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1527 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1528 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1529 int type
= intel_encoder
->type
;
1532 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
|| type
== INTEL_OUTPUT_DP_MST
) {
1533 temp
= TRANS_MSA_SYNC_CLK
;
1534 switch (intel_crtc
->config
->pipe_bpp
) {
1536 temp
|= TRANS_MSA_6_BPC
;
1539 temp
|= TRANS_MSA_8_BPC
;
1542 temp
|= TRANS_MSA_10_BPC
;
1545 temp
|= TRANS_MSA_12_BPC
;
1550 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder
), temp
);
1554 void intel_ddi_set_vc_payload_alloc(struct drm_crtc
*crtc
, bool state
)
1556 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1557 struct drm_device
*dev
= crtc
->dev
;
1558 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1559 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1561 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1563 temp
|= TRANS_DDI_DP_VC_PAYLOAD_ALLOC
;
1565 temp
&= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC
;
1566 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1569 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
)
1571 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1572 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1573 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1574 struct drm_device
*dev
= crtc
->dev
;
1575 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1576 enum pipe pipe
= intel_crtc
->pipe
;
1577 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1578 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1579 int type
= intel_encoder
->type
;
1582 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1583 temp
= TRANS_DDI_FUNC_ENABLE
;
1584 temp
|= TRANS_DDI_SELECT_PORT(port
);
1586 switch (intel_crtc
->config
->pipe_bpp
) {
1588 temp
|= TRANS_DDI_BPC_6
;
1591 temp
|= TRANS_DDI_BPC_8
;
1594 temp
|= TRANS_DDI_BPC_10
;
1597 temp
|= TRANS_DDI_BPC_12
;
1603 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
1604 temp
|= TRANS_DDI_PVSYNC
;
1605 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
1606 temp
|= TRANS_DDI_PHSYNC
;
1608 if (cpu_transcoder
== TRANSCODER_EDP
) {
1611 /* On Haswell, can only use the always-on power well for
1612 * eDP when not using the panel fitter, and when not
1613 * using motion blur mitigation (which we don't
1615 if (IS_HASWELL(dev
) &&
1616 (intel_crtc
->config
->pch_pfit
.enabled
||
1617 intel_crtc
->config
->pch_pfit
.force_thru
))
1618 temp
|= TRANS_DDI_EDP_INPUT_A_ONOFF
;
1620 temp
|= TRANS_DDI_EDP_INPUT_A_ON
;
1623 temp
|= TRANS_DDI_EDP_INPUT_B_ONOFF
;
1626 temp
|= TRANS_DDI_EDP_INPUT_C_ONOFF
;
1634 if (type
== INTEL_OUTPUT_HDMI
) {
1635 if (intel_crtc
->config
->has_hdmi_sink
)
1636 temp
|= TRANS_DDI_MODE_SELECT_HDMI
;
1638 temp
|= TRANS_DDI_MODE_SELECT_DVI
;
1640 } else if (type
== INTEL_OUTPUT_ANALOG
) {
1641 temp
|= TRANS_DDI_MODE_SELECT_FDI
;
1642 temp
|= (intel_crtc
->config
->fdi_lanes
- 1) << 1;
1644 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
||
1645 type
== INTEL_OUTPUT_EDP
) {
1646 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1648 if (intel_dp
->is_mst
) {
1649 temp
|= TRANS_DDI_MODE_SELECT_DP_MST
;
1651 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
1653 temp
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
1654 } else if (type
== INTEL_OUTPUT_DP_MST
) {
1655 struct intel_dp
*intel_dp
= &enc_to_mst(encoder
)->primary
->dp
;
1657 if (intel_dp
->is_mst
) {
1658 temp
|= TRANS_DDI_MODE_SELECT_DP_MST
;
1660 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
1662 temp
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
1664 WARN(1, "Invalid encoder type %d for pipe %c\n",
1665 intel_encoder
->type
, pipe_name(pipe
));
1668 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1671 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1672 enum transcoder cpu_transcoder
)
1674 uint32_t reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1675 uint32_t val
= I915_READ(reg
);
1677 val
&= ~(TRANS_DDI_FUNC_ENABLE
| TRANS_DDI_PORT_MASK
| TRANS_DDI_DP_VC_PAYLOAD_ALLOC
);
1678 val
|= TRANS_DDI_PORT_NONE
;
1679 I915_WRITE(reg
, val
);
1682 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
)
1684 struct drm_device
*dev
= intel_connector
->base
.dev
;
1685 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1686 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
1687 int type
= intel_connector
->base
.connector_type
;
1688 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1690 enum transcoder cpu_transcoder
;
1691 enum intel_display_power_domain power_domain
;
1694 power_domain
= intel_display_port_power_domain(intel_encoder
);
1695 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
1698 if (!intel_encoder
->get_hw_state(intel_encoder
, &pipe
))
1702 cpu_transcoder
= TRANSCODER_EDP
;
1704 cpu_transcoder
= (enum transcoder
) pipe
;
1706 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1708 switch (tmp
& TRANS_DDI_MODE_SELECT_MASK
) {
1709 case TRANS_DDI_MODE_SELECT_HDMI
:
1710 case TRANS_DDI_MODE_SELECT_DVI
:
1711 return (type
== DRM_MODE_CONNECTOR_HDMIA
);
1713 case TRANS_DDI_MODE_SELECT_DP_SST
:
1714 if (type
== DRM_MODE_CONNECTOR_eDP
)
1716 return (type
== DRM_MODE_CONNECTOR_DisplayPort
);
1717 case TRANS_DDI_MODE_SELECT_DP_MST
:
1718 /* if the transcoder is in MST state then
1719 * connector isn't connected */
1722 case TRANS_DDI_MODE_SELECT_FDI
:
1723 return (type
== DRM_MODE_CONNECTOR_VGA
);
1730 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
,
1733 struct drm_device
*dev
= encoder
->base
.dev
;
1734 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1735 enum port port
= intel_ddi_get_encoder_port(encoder
);
1736 enum intel_display_power_domain power_domain
;
1740 power_domain
= intel_display_port_power_domain(encoder
);
1741 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
1744 tmp
= I915_READ(DDI_BUF_CTL(port
));
1746 if (!(tmp
& DDI_BUF_CTL_ENABLE
))
1749 if (port
== PORT_A
) {
1750 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
1752 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
1753 case TRANS_DDI_EDP_INPUT_A_ON
:
1754 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
1757 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
1760 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
1767 for (i
= TRANSCODER_A
; i
<= TRANSCODER_C
; i
++) {
1768 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(i
));
1770 if ((tmp
& TRANS_DDI_PORT_MASK
)
1771 == TRANS_DDI_SELECT_PORT(port
)) {
1772 if ((tmp
& TRANS_DDI_MODE_SELECT_MASK
) == TRANS_DDI_MODE_SELECT_DP_MST
)
1781 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port
));
1786 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
)
1788 struct drm_crtc
*crtc
= &intel_crtc
->base
;
1789 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1790 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1791 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1792 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1794 if (cpu_transcoder
!= TRANSCODER_EDP
)
1795 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1796 TRANS_CLK_SEL_PORT(port
));
1799 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
)
1801 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1802 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1804 if (cpu_transcoder
!= TRANSCODER_EDP
)
1805 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1806 TRANS_CLK_SEL_DISABLED
);
1809 void bxt_ddi_vswing_sequence(struct drm_device
*dev
, u32 level
,
1810 enum port port
, int type
)
1812 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1813 const struct bxt_ddi_buf_trans
*ddi_translations
;
1817 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
1818 n_entries
= ARRAY_SIZE(bxt_ddi_translations_dp
);
1819 ddi_translations
= bxt_ddi_translations_dp
;
1820 } else if (type
== INTEL_OUTPUT_HDMI
) {
1821 n_entries
= ARRAY_SIZE(bxt_ddi_translations_hdmi
);
1822 ddi_translations
= bxt_ddi_translations_hdmi
;
1824 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1829 /* Check if default value has to be used */
1830 if (level
>= n_entries
||
1831 (type
== INTEL_OUTPUT_HDMI
&& level
== HDMI_LEVEL_SHIFT_UNKNOWN
)) {
1832 for (i
= 0; i
< n_entries
; i
++) {
1833 if (ddi_translations
[i
].default_index
) {
1841 * While we write to the group register to program all lanes at once we
1842 * can read only lane registers and we pick lanes 0/1 for that.
1844 val
= I915_READ(BXT_PORT_PCS_DW10_LN01(port
));
1845 val
&= ~(TX2_SWING_CALC_INIT
| TX1_SWING_CALC_INIT
);
1846 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port
), val
);
1848 val
= I915_READ(BXT_PORT_TX_DW2_LN0(port
));
1849 val
&= ~(MARGIN_000
| UNIQ_TRANS_SCALE
);
1850 val
|= ddi_translations
[level
].margin
<< MARGIN_000_SHIFT
|
1851 ddi_translations
[level
].scale
<< UNIQ_TRANS_SCALE_SHIFT
;
1852 I915_WRITE(BXT_PORT_TX_DW2_GRP(port
), val
);
1854 val
= I915_READ(BXT_PORT_TX_DW3_LN0(port
));
1855 val
&= ~UNIQE_TRANGE_EN_METHOD
;
1856 if (ddi_translations
[level
].enable
)
1857 val
|= UNIQE_TRANGE_EN_METHOD
;
1858 I915_WRITE(BXT_PORT_TX_DW3_GRP(port
), val
);
1860 val
= I915_READ(BXT_PORT_TX_DW4_LN0(port
));
1861 val
&= ~DE_EMPHASIS
;
1862 val
|= ddi_translations
[level
].deemphasis
<< DEEMPH_SHIFT
;
1863 I915_WRITE(BXT_PORT_TX_DW4_GRP(port
), val
);
1865 val
= I915_READ(BXT_PORT_PCS_DW10_LN01(port
));
1866 val
|= TX2_SWING_CALC_INIT
| TX1_SWING_CALC_INIT
;
1867 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port
), val
);
1870 static void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder
)
1872 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1873 struct drm_device
*dev
= encoder
->dev
;
1874 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1875 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->crtc
);
1876 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1877 int type
= intel_encoder
->type
;
1880 if (type
== INTEL_OUTPUT_EDP
) {
1881 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1882 intel_edp_panel_on(intel_dp
);
1885 if (IS_SKYLAKE(dev
)) {
1886 uint32_t dpll
= crtc
->config
->ddi_pll_sel
;
1890 * DPLL0 is used for eDP and is the only "private" DPLL (as
1891 * opposed to shared) on SKL
1893 if (type
== INTEL_OUTPUT_EDP
) {
1894 WARN_ON(dpll
!= SKL_DPLL0
);
1896 val
= I915_READ(DPLL_CTRL1
);
1898 val
&= ~(DPLL_CTRL1_HDMI_MODE(dpll
) |
1899 DPLL_CTRL1_SSC(dpll
) |
1900 DPLL_CTRL1_LINK_RATE_MASK(dpll
));
1901 val
|= crtc
->config
->dpll_hw_state
.ctrl1
<< (dpll
* 6);
1903 I915_WRITE(DPLL_CTRL1
, val
);
1904 POSTING_READ(DPLL_CTRL1
);
1907 /* DDI -> PLL mapping */
1908 val
= I915_READ(DPLL_CTRL2
);
1910 val
&= ~(DPLL_CTRL2_DDI_CLK_OFF(port
) |
1911 DPLL_CTRL2_DDI_CLK_SEL_MASK(port
));
1912 val
|= (DPLL_CTRL2_DDI_CLK_SEL(dpll
, port
) |
1913 DPLL_CTRL2_DDI_SEL_OVERRIDE(port
));
1915 I915_WRITE(DPLL_CTRL2
, val
);
1917 } else if (INTEL_INFO(dev
)->gen
< 9) {
1918 WARN_ON(crtc
->config
->ddi_pll_sel
== PORT_CLK_SEL_NONE
);
1919 I915_WRITE(PORT_CLK_SEL(port
), crtc
->config
->ddi_pll_sel
);
1922 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
1923 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1925 intel_ddi_init_dp_buf_reg(intel_encoder
);
1927 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1928 intel_dp_start_link_train(intel_dp
);
1929 intel_dp_complete_link_train(intel_dp
);
1930 if (port
!= PORT_A
|| INTEL_INFO(dev
)->gen
>= 9)
1931 intel_dp_stop_link_train(intel_dp
);
1932 } else if (type
== INTEL_OUTPUT_HDMI
) {
1933 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1935 if (IS_BROXTON(dev
)) {
1936 hdmi_level
= dev_priv
->vbt
.
1937 ddi_port_info
[port
].hdmi_level_shift
;
1938 bxt_ddi_vswing_sequence(dev
, hdmi_level
, port
,
1941 intel_hdmi
->set_infoframes(encoder
,
1942 crtc
->config
->has_hdmi_sink
,
1943 &crtc
->config
->base
.adjusted_mode
);
1947 static void intel_ddi_post_disable(struct intel_encoder
*intel_encoder
)
1949 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1950 struct drm_device
*dev
= encoder
->dev
;
1951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1952 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1953 int type
= intel_encoder
->type
;
1957 val
= I915_READ(DDI_BUF_CTL(port
));
1958 if (val
& DDI_BUF_CTL_ENABLE
) {
1959 val
&= ~DDI_BUF_CTL_ENABLE
;
1960 I915_WRITE(DDI_BUF_CTL(port
), val
);
1964 val
= I915_READ(DP_TP_CTL(port
));
1965 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1966 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1967 I915_WRITE(DP_TP_CTL(port
), val
);
1970 intel_wait_ddi_buf_idle(dev_priv
, port
);
1972 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
1973 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1974 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
1975 intel_edp_panel_vdd_on(intel_dp
);
1976 intel_edp_panel_off(intel_dp
);
1979 if (IS_SKYLAKE(dev
))
1980 I915_WRITE(DPLL_CTRL2
, (I915_READ(DPLL_CTRL2
) |
1981 DPLL_CTRL2_DDI_CLK_OFF(port
)));
1982 else if (INTEL_INFO(dev
)->gen
< 9)
1983 I915_WRITE(PORT_CLK_SEL(port
), PORT_CLK_SEL_NONE
);
1986 static void intel_enable_ddi(struct intel_encoder
*intel_encoder
)
1988 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1989 struct drm_crtc
*crtc
= encoder
->crtc
;
1990 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1991 struct drm_device
*dev
= encoder
->dev
;
1992 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1993 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1994 int type
= intel_encoder
->type
;
1996 if (type
== INTEL_OUTPUT_HDMI
) {
1997 struct intel_digital_port
*intel_dig_port
=
1998 enc_to_dig_port(encoder
);
2000 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2001 * are ignored so nothing special needs to be done besides
2002 * enabling the port.
2004 I915_WRITE(DDI_BUF_CTL(port
),
2005 intel_dig_port
->saved_port_bits
|
2006 DDI_BUF_CTL_ENABLE
);
2007 } else if (type
== INTEL_OUTPUT_EDP
) {
2008 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2010 if (port
== PORT_A
&& INTEL_INFO(dev
)->gen
< 9)
2011 intel_dp_stop_link_train(intel_dp
);
2013 intel_edp_backlight_on(intel_dp
);
2014 intel_psr_enable(intel_dp
);
2015 intel_edp_drrs_enable(intel_dp
);
2018 if (intel_crtc
->config
->has_audio
) {
2019 intel_display_power_get(dev_priv
, POWER_DOMAIN_AUDIO
);
2020 intel_audio_codec_enable(intel_encoder
);
2024 static void intel_disable_ddi(struct intel_encoder
*intel_encoder
)
2026 struct drm_encoder
*encoder
= &intel_encoder
->base
;
2027 struct drm_crtc
*crtc
= encoder
->crtc
;
2028 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2029 int type
= intel_encoder
->type
;
2030 struct drm_device
*dev
= encoder
->dev
;
2031 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2033 if (intel_crtc
->config
->has_audio
) {
2034 intel_audio_codec_disable(intel_encoder
);
2035 intel_display_power_put(dev_priv
, POWER_DOMAIN_AUDIO
);
2038 if (type
== INTEL_OUTPUT_EDP
) {
2039 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2041 intel_edp_drrs_disable(intel_dp
);
2042 intel_psr_disable(intel_dp
);
2043 intel_edp_backlight_off(intel_dp
);
2047 static void hsw_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
2048 struct intel_shared_dpll
*pll
)
2050 I915_WRITE(WRPLL_CTL(pll
->id
), pll
->config
.hw_state
.wrpll
);
2051 POSTING_READ(WRPLL_CTL(pll
->id
));
2055 static void hsw_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
2056 struct intel_shared_dpll
*pll
)
2060 val
= I915_READ(WRPLL_CTL(pll
->id
));
2061 I915_WRITE(WRPLL_CTL(pll
->id
), val
& ~WRPLL_PLL_ENABLE
);
2062 POSTING_READ(WRPLL_CTL(pll
->id
));
2065 static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
2066 struct intel_shared_dpll
*pll
,
2067 struct intel_dpll_hw_state
*hw_state
)
2071 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
2074 val
= I915_READ(WRPLL_CTL(pll
->id
));
2075 hw_state
->wrpll
= val
;
2077 return val
& WRPLL_PLL_ENABLE
;
2080 static const char * const hsw_ddi_pll_names
[] = {
2085 static void hsw_shared_dplls_init(struct drm_i915_private
*dev_priv
)
2089 dev_priv
->num_shared_dpll
= 2;
2091 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
2092 dev_priv
->shared_dplls
[i
].id
= i
;
2093 dev_priv
->shared_dplls
[i
].name
= hsw_ddi_pll_names
[i
];
2094 dev_priv
->shared_dplls
[i
].disable
= hsw_ddi_pll_disable
;
2095 dev_priv
->shared_dplls
[i
].enable
= hsw_ddi_pll_enable
;
2096 dev_priv
->shared_dplls
[i
].get_hw_state
=
2097 hsw_ddi_pll_get_hw_state
;
2101 static const char * const skl_ddi_pll_names
[] = {
2107 struct skl_dpll_regs
{
2108 u32 ctl
, cfgcr1
, cfgcr2
;
2111 /* this array is indexed by the *shared* pll id */
2112 static const struct skl_dpll_regs skl_dpll_regs
[3] = {
2116 .cfgcr1
= DPLL1_CFGCR1
,
2117 .cfgcr2
= DPLL1_CFGCR2
,
2122 .cfgcr1
= DPLL2_CFGCR1
,
2123 .cfgcr2
= DPLL2_CFGCR2
,
2128 .cfgcr1
= DPLL3_CFGCR1
,
2129 .cfgcr2
= DPLL3_CFGCR2
,
2133 static void skl_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
2134 struct intel_shared_dpll
*pll
)
2138 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
2140 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2143 val
= I915_READ(DPLL_CTRL1
);
2145 val
&= ~(DPLL_CTRL1_HDMI_MODE(dpll
) | DPLL_CTRL1_SSC(dpll
) |
2146 DPLL_CTRL1_LINK_RATE_MASK(dpll
));
2147 val
|= pll
->config
.hw_state
.ctrl1
<< (dpll
* 6);
2149 I915_WRITE(DPLL_CTRL1
, val
);
2150 POSTING_READ(DPLL_CTRL1
);
2152 I915_WRITE(regs
[pll
->id
].cfgcr1
, pll
->config
.hw_state
.cfgcr1
);
2153 I915_WRITE(regs
[pll
->id
].cfgcr2
, pll
->config
.hw_state
.cfgcr2
);
2154 POSTING_READ(regs
[pll
->id
].cfgcr1
);
2155 POSTING_READ(regs
[pll
->id
].cfgcr2
);
2157 /* the enable bit is always bit 31 */
2158 I915_WRITE(regs
[pll
->id
].ctl
,
2159 I915_READ(regs
[pll
->id
].ctl
) | LCPLL_PLL_ENABLE
);
2161 if (wait_for(I915_READ(DPLL_STATUS
) & DPLL_LOCK(dpll
), 5))
2162 DRM_ERROR("DPLL %d not locked\n", dpll
);
2165 static void skl_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
2166 struct intel_shared_dpll
*pll
)
2168 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
2170 /* the enable bit is always bit 31 */
2171 I915_WRITE(regs
[pll
->id
].ctl
,
2172 I915_READ(regs
[pll
->id
].ctl
) & ~LCPLL_PLL_ENABLE
);
2173 POSTING_READ(regs
[pll
->id
].ctl
);
2176 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
2177 struct intel_shared_dpll
*pll
,
2178 struct intel_dpll_hw_state
*hw_state
)
2182 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
2184 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
2187 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2190 val
= I915_READ(regs
[pll
->id
].ctl
);
2191 if (!(val
& LCPLL_PLL_ENABLE
))
2194 val
= I915_READ(DPLL_CTRL1
);
2195 hw_state
->ctrl1
= (val
>> (dpll
* 6)) & 0x3f;
2197 /* avoid reading back stale values if HDMI mode is not enabled */
2198 if (val
& DPLL_CTRL1_HDMI_MODE(dpll
)) {
2199 hw_state
->cfgcr1
= I915_READ(regs
[pll
->id
].cfgcr1
);
2200 hw_state
->cfgcr2
= I915_READ(regs
[pll
->id
].cfgcr2
);
2206 static void skl_shared_dplls_init(struct drm_i915_private
*dev_priv
)
2210 dev_priv
->num_shared_dpll
= 3;
2212 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
2213 dev_priv
->shared_dplls
[i
].id
= i
;
2214 dev_priv
->shared_dplls
[i
].name
= skl_ddi_pll_names
[i
];
2215 dev_priv
->shared_dplls
[i
].disable
= skl_ddi_pll_disable
;
2216 dev_priv
->shared_dplls
[i
].enable
= skl_ddi_pll_enable
;
2217 dev_priv
->shared_dplls
[i
].get_hw_state
=
2218 skl_ddi_pll_get_hw_state
;
2222 static void broxton_phy_init(struct drm_i915_private
*dev_priv
,
2228 val
= I915_READ(BXT_P_CR_GT_DISP_PWRON
);
2229 val
|= GT_DISPLAY_POWER_ON(phy
);
2230 I915_WRITE(BXT_P_CR_GT_DISP_PWRON
, val
);
2232 /* Considering 10ms timeout until BSpec is updated */
2233 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy
)) & PHY_POWER_GOOD
, 10))
2234 DRM_ERROR("timeout during PHY%d power on\n", phy
);
2236 for (port
= (phy
== DPIO_PHY0
? PORT_B
: PORT_A
);
2237 port
<= (phy
== DPIO_PHY0
? PORT_C
: PORT_A
); port
++) {
2240 for (lane
= 0; lane
< 4; lane
++) {
2241 val
= I915_READ(BXT_PORT_TX_DW14_LN(port
, lane
));
2243 * Note that on CHV this flag is called UPAR, but has
2244 * the same function.
2246 val
&= ~LATENCY_OPTIM
;
2248 val
|= LATENCY_OPTIM
;
2250 I915_WRITE(BXT_PORT_TX_DW14_LN(port
, lane
), val
);
2254 /* Program PLL Rcomp code offset */
2255 val
= I915_READ(BXT_PORT_CL1CM_DW9(phy
));
2256 val
&= ~IREF0RC_OFFSET_MASK
;
2257 val
|= 0xE4 << IREF0RC_OFFSET_SHIFT
;
2258 I915_WRITE(BXT_PORT_CL1CM_DW9(phy
), val
);
2260 val
= I915_READ(BXT_PORT_CL1CM_DW10(phy
));
2261 val
&= ~IREF1RC_OFFSET_MASK
;
2262 val
|= 0xE4 << IREF1RC_OFFSET_SHIFT
;
2263 I915_WRITE(BXT_PORT_CL1CM_DW10(phy
), val
);
2265 /* Program power gating */
2266 val
= I915_READ(BXT_PORT_CL1CM_DW28(phy
));
2267 val
|= OCL1_POWER_DOWN_EN
| DW28_OLDO_DYN_PWR_DOWN_EN
|
2269 I915_WRITE(BXT_PORT_CL1CM_DW28(phy
), val
);
2271 if (phy
== DPIO_PHY0
) {
2272 val
= I915_READ(BXT_PORT_CL2CM_DW6_BC
);
2273 val
|= DW6_OLDO_DYN_PWR_DOWN_EN
;
2274 I915_WRITE(BXT_PORT_CL2CM_DW6_BC
, val
);
2277 val
= I915_READ(BXT_PORT_CL1CM_DW30(phy
));
2278 val
&= ~OCL2_LDOFUSE_PWR_DIS
;
2280 * On PHY1 disable power on the second channel, since no port is
2281 * connected there. On PHY0 both channels have a port, so leave it
2283 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2284 * power down the second channel on PHY0 as well.
2286 if (phy
== DPIO_PHY1
)
2287 val
|= OCL2_LDOFUSE_PWR_DIS
;
2288 I915_WRITE(BXT_PORT_CL1CM_DW30(phy
), val
);
2290 if (phy
== DPIO_PHY0
) {
2293 * PHY0 isn't connected to an RCOMP resistor so copy over
2294 * the corresponding calibrated value from PHY1, and disable
2295 * the automatic calibration on PHY0.
2297 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1
)) & GRC_DONE
,
2299 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2301 val
= I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1
));
2302 val
= (val
& GRC_CODE_MASK
) >> GRC_CODE_SHIFT
;
2303 grc_code
= val
<< GRC_CODE_FAST_SHIFT
|
2304 val
<< GRC_CODE_SLOW_SHIFT
|
2306 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0
), grc_code
);
2308 val
= I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0
));
2309 val
|= GRC_DIS
| GRC_RDY_OVRD
;
2310 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0
), val
);
2313 val
= I915_READ(BXT_PHY_CTL_FAMILY(phy
));
2314 val
|= COMMON_RESET_DIS
;
2315 I915_WRITE(BXT_PHY_CTL_FAMILY(phy
), val
);
2318 void broxton_ddi_phy_init(struct drm_device
*dev
)
2320 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2321 broxton_phy_init(dev
->dev_private
, DPIO_PHY1
);
2322 broxton_phy_init(dev
->dev_private
, DPIO_PHY0
);
2325 static void broxton_phy_uninit(struct drm_i915_private
*dev_priv
,
2330 val
= I915_READ(BXT_PHY_CTL_FAMILY(phy
));
2331 val
&= ~COMMON_RESET_DIS
;
2332 I915_WRITE(BXT_PHY_CTL_FAMILY(phy
), val
);
2335 void broxton_ddi_phy_uninit(struct drm_device
*dev
)
2337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2339 broxton_phy_uninit(dev_priv
, DPIO_PHY1
);
2340 broxton_phy_uninit(dev_priv
, DPIO_PHY0
);
2342 /* FIXME: do this in broxton_phy_uninit per phy */
2343 I915_WRITE(BXT_P_CR_GT_DISP_PWRON
, 0);
2346 static const char * const bxt_ddi_pll_names
[] = {
2352 static void bxt_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
2353 struct intel_shared_dpll
*pll
)
2356 enum port port
= (enum port
)pll
->id
; /* 1:1 port->PLL mapping */
2358 temp
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
2359 temp
&= ~PORT_PLL_REF_SEL
;
2360 /* Non-SSC reference */
2361 I915_WRITE(BXT_PORT_PLL_ENABLE(port
), temp
);
2363 /* Disable 10 bit clock */
2364 temp
= I915_READ(BXT_PORT_PLL_EBB_4(port
));
2365 temp
&= ~PORT_PLL_10BIT_CLK_ENABLE
;
2366 I915_WRITE(BXT_PORT_PLL_EBB_4(port
), temp
);
2369 temp
= I915_READ(BXT_PORT_PLL_EBB_0(port
));
2370 temp
&= ~(PORT_PLL_P1_MASK
| PORT_PLL_P2_MASK
);
2371 temp
|= pll
->config
.hw_state
.ebb0
;
2372 I915_WRITE(BXT_PORT_PLL_EBB_0(port
), temp
);
2374 /* Write M2 integer */
2375 temp
= I915_READ(BXT_PORT_PLL(port
, 0));
2376 temp
&= ~PORT_PLL_M2_MASK
;
2377 temp
|= pll
->config
.hw_state
.pll0
;
2378 I915_WRITE(BXT_PORT_PLL(port
, 0), temp
);
2381 temp
= I915_READ(BXT_PORT_PLL(port
, 1));
2382 temp
&= ~PORT_PLL_N_MASK
;
2383 temp
|= pll
->config
.hw_state
.pll1
;
2384 I915_WRITE(BXT_PORT_PLL(port
, 1), temp
);
2386 /* Write M2 fraction */
2387 temp
= I915_READ(BXT_PORT_PLL(port
, 2));
2388 temp
&= ~PORT_PLL_M2_FRAC_MASK
;
2389 temp
|= pll
->config
.hw_state
.pll2
;
2390 I915_WRITE(BXT_PORT_PLL(port
, 2), temp
);
2392 /* Write M2 fraction enable */
2393 temp
= I915_READ(BXT_PORT_PLL(port
, 3));
2394 temp
&= ~PORT_PLL_M2_FRAC_ENABLE
;
2395 temp
|= pll
->config
.hw_state
.pll3
;
2396 I915_WRITE(BXT_PORT_PLL(port
, 3), temp
);
2399 temp
= I915_READ(BXT_PORT_PLL(port
, 6));
2400 temp
&= ~PORT_PLL_PROP_COEFF_MASK
;
2401 temp
&= ~PORT_PLL_INT_COEFF_MASK
;
2402 temp
&= ~PORT_PLL_GAIN_CTL_MASK
;
2403 temp
|= pll
->config
.hw_state
.pll6
;
2404 I915_WRITE(BXT_PORT_PLL(port
, 6), temp
);
2406 /* Write calibration val */
2407 temp
= I915_READ(BXT_PORT_PLL(port
, 8));
2408 temp
&= ~PORT_PLL_TARGET_CNT_MASK
;
2409 temp
|= pll
->config
.hw_state
.pll8
;
2410 I915_WRITE(BXT_PORT_PLL(port
, 8), temp
);
2412 temp
= I915_READ(BXT_PORT_PLL(port
, 9));
2413 temp
&= ~PORT_PLL_LOCK_THRESHOLD_MASK
;
2415 I915_WRITE(BXT_PORT_PLL(port
, 9), temp
);
2417 temp
= I915_READ(BXT_PORT_PLL(port
, 10));
2418 temp
&= ~PORT_PLL_DCO_AMP_OVR_EN_H
;
2419 temp
&= ~PORT_PLL_DCO_AMP_MASK
;
2420 temp
|= pll
->config
.hw_state
.pll10
;
2421 I915_WRITE(BXT_PORT_PLL(port
, 10), temp
);
2423 /* Recalibrate with new settings */
2424 temp
= I915_READ(BXT_PORT_PLL_EBB_4(port
));
2425 temp
|= PORT_PLL_RECALIBRATE
;
2426 I915_WRITE(BXT_PORT_PLL_EBB_4(port
), temp
);
2427 /* Enable 10 bit clock */
2428 temp
|= PORT_PLL_10BIT_CLK_ENABLE
;
2429 I915_WRITE(BXT_PORT_PLL_EBB_4(port
), temp
);
2432 temp
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
2433 temp
|= PORT_PLL_ENABLE
;
2434 I915_WRITE(BXT_PORT_PLL_ENABLE(port
), temp
);
2435 POSTING_READ(BXT_PORT_PLL_ENABLE(port
));
2437 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port
)) &
2438 PORT_PLL_LOCK
), 200))
2439 DRM_ERROR("PLL %d not locked\n", port
);
2442 * While we write to the group register to program all lanes at once we
2443 * can read only lane registers and we pick lanes 0/1 for that.
2445 temp
= I915_READ(BXT_PORT_PCS_DW12_LN01(port
));
2446 temp
&= ~LANE_STAGGER_MASK
;
2447 temp
&= ~LANESTAGGER_STRAP_OVRD
;
2448 temp
|= pll
->config
.hw_state
.pcsdw12
;
2449 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port
), temp
);
2452 static void bxt_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
2453 struct intel_shared_dpll
*pll
)
2455 enum port port
= (enum port
)pll
->id
; /* 1:1 port->PLL mapping */
2458 temp
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
2459 temp
&= ~PORT_PLL_ENABLE
;
2460 I915_WRITE(BXT_PORT_PLL_ENABLE(port
), temp
);
2461 POSTING_READ(BXT_PORT_PLL_ENABLE(port
));
2464 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
2465 struct intel_shared_dpll
*pll
,
2466 struct intel_dpll_hw_state
*hw_state
)
2468 enum port port
= (enum port
)pll
->id
; /* 1:1 port->PLL mapping */
2471 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
2474 val
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
2475 if (!(val
& PORT_PLL_ENABLE
))
2478 hw_state
->ebb0
= I915_READ(BXT_PORT_PLL_EBB_0(port
));
2479 hw_state
->pll0
= I915_READ(BXT_PORT_PLL(port
, 0));
2480 hw_state
->pll1
= I915_READ(BXT_PORT_PLL(port
, 1));
2481 hw_state
->pll2
= I915_READ(BXT_PORT_PLL(port
, 2));
2482 hw_state
->pll3
= I915_READ(BXT_PORT_PLL(port
, 3));
2483 hw_state
->pll6
= I915_READ(BXT_PORT_PLL(port
, 6));
2484 hw_state
->pll8
= I915_READ(BXT_PORT_PLL(port
, 8));
2485 hw_state
->pll10
= I915_READ(BXT_PORT_PLL(port
, 10));
2487 * While we write to the group register to program all lanes at once we
2488 * can read only lane registers. We configure all lanes the same way, so
2489 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2491 hw_state
->pcsdw12
= I915_READ(BXT_PORT_PCS_DW12_LN01(port
));
2492 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port
) != hw_state
->pcsdw12
))
2493 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2495 I915_READ(BXT_PORT_PCS_DW12_LN23(port
)));
2500 static void bxt_shared_dplls_init(struct drm_i915_private
*dev_priv
)
2504 dev_priv
->num_shared_dpll
= 3;
2506 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
2507 dev_priv
->shared_dplls
[i
].id
= i
;
2508 dev_priv
->shared_dplls
[i
].name
= bxt_ddi_pll_names
[i
];
2509 dev_priv
->shared_dplls
[i
].disable
= bxt_ddi_pll_disable
;
2510 dev_priv
->shared_dplls
[i
].enable
= bxt_ddi_pll_enable
;
2511 dev_priv
->shared_dplls
[i
].get_hw_state
=
2512 bxt_ddi_pll_get_hw_state
;
2516 void intel_ddi_pll_init(struct drm_device
*dev
)
2518 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2519 uint32_t val
= I915_READ(LCPLL_CTL
);
2521 if (IS_SKYLAKE(dev
))
2522 skl_shared_dplls_init(dev_priv
);
2523 else if (IS_BROXTON(dev
))
2524 bxt_shared_dplls_init(dev_priv
);
2526 hsw_shared_dplls_init(dev_priv
);
2528 if (IS_SKYLAKE(dev
)) {
2531 cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
2532 dev_priv
->skl_boot_cdclk
= cdclk_freq
;
2533 if (!(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_ENABLE
))
2534 DRM_ERROR("LCPLL1 is disabled\n");
2536 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
2537 } else if (IS_BROXTON(dev
)) {
2538 broxton_init_cdclk(dev
);
2539 broxton_ddi_phy_init(dev
);
2542 * The LCPLL register should be turned on by the BIOS. For now
2543 * let's just check its state and print errors in case
2544 * something is wrong. Don't even try to turn it on.
2547 if (val
& LCPLL_CD_SOURCE_FCLK
)
2548 DRM_ERROR("CDCLK source is not LCPLL\n");
2550 if (val
& LCPLL_PLL_DISABLE
)
2551 DRM_ERROR("LCPLL is disabled\n");
2555 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
)
2557 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
2558 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
2559 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
2560 enum port port
= intel_dig_port
->port
;
2564 if (I915_READ(DP_TP_CTL(port
)) & DP_TP_CTL_ENABLE
) {
2565 val
= I915_READ(DDI_BUF_CTL(port
));
2566 if (val
& DDI_BUF_CTL_ENABLE
) {
2567 val
&= ~DDI_BUF_CTL_ENABLE
;
2568 I915_WRITE(DDI_BUF_CTL(port
), val
);
2572 val
= I915_READ(DP_TP_CTL(port
));
2573 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
2574 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2575 I915_WRITE(DP_TP_CTL(port
), val
);
2576 POSTING_READ(DP_TP_CTL(port
));
2579 intel_wait_ddi_buf_idle(dev_priv
, port
);
2582 val
= DP_TP_CTL_ENABLE
|
2583 DP_TP_CTL_LINK_TRAIN_PAT1
| DP_TP_CTL_SCRAMBLE_DISABLE
;
2584 if (intel_dp
->is_mst
)
2585 val
|= DP_TP_CTL_MODE_MST
;
2587 val
|= DP_TP_CTL_MODE_SST
;
2588 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
2589 val
|= DP_TP_CTL_ENHANCED_FRAME_ENABLE
;
2591 I915_WRITE(DP_TP_CTL(port
), val
);
2592 POSTING_READ(DP_TP_CTL(port
));
2594 intel_dp
->DP
|= DDI_BUF_CTL_ENABLE
;
2595 I915_WRITE(DDI_BUF_CTL(port
), intel_dp
->DP
);
2596 POSTING_READ(DDI_BUF_CTL(port
));
2601 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
)
2603 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
2604 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
2607 intel_ddi_post_disable(intel_encoder
);
2609 val
= I915_READ(_FDI_RXA_CTL
);
2610 val
&= ~FDI_RX_ENABLE
;
2611 I915_WRITE(_FDI_RXA_CTL
, val
);
2613 val
= I915_READ(_FDI_RXA_MISC
);
2614 val
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
2615 val
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2616 I915_WRITE(_FDI_RXA_MISC
, val
);
2618 val
= I915_READ(_FDI_RXA_CTL
);
2620 I915_WRITE(_FDI_RXA_CTL
, val
);
2622 val
= I915_READ(_FDI_RXA_CTL
);
2623 val
&= ~FDI_RX_PLL_ENABLE
;
2624 I915_WRITE(_FDI_RXA_CTL
, val
);
2627 void intel_ddi_get_config(struct intel_encoder
*encoder
,
2628 struct intel_crtc_state
*pipe_config
)
2630 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
2631 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2632 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
2633 struct intel_hdmi
*intel_hdmi
;
2634 u32 temp
, flags
= 0;
2636 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
2637 if (temp
& TRANS_DDI_PHSYNC
)
2638 flags
|= DRM_MODE_FLAG_PHSYNC
;
2640 flags
|= DRM_MODE_FLAG_NHSYNC
;
2641 if (temp
& TRANS_DDI_PVSYNC
)
2642 flags
|= DRM_MODE_FLAG_PVSYNC
;
2644 flags
|= DRM_MODE_FLAG_NVSYNC
;
2646 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2648 switch (temp
& TRANS_DDI_BPC_MASK
) {
2649 case TRANS_DDI_BPC_6
:
2650 pipe_config
->pipe_bpp
= 18;
2652 case TRANS_DDI_BPC_8
:
2653 pipe_config
->pipe_bpp
= 24;
2655 case TRANS_DDI_BPC_10
:
2656 pipe_config
->pipe_bpp
= 30;
2658 case TRANS_DDI_BPC_12
:
2659 pipe_config
->pipe_bpp
= 36;
2665 switch (temp
& TRANS_DDI_MODE_SELECT_MASK
) {
2666 case TRANS_DDI_MODE_SELECT_HDMI
:
2667 pipe_config
->has_hdmi_sink
= true;
2668 intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
2670 if (intel_hdmi
->infoframe_enabled(&encoder
->base
))
2671 pipe_config
->has_infoframe
= true;
2673 case TRANS_DDI_MODE_SELECT_DVI
:
2674 case TRANS_DDI_MODE_SELECT_FDI
:
2676 case TRANS_DDI_MODE_SELECT_DP_SST
:
2677 case TRANS_DDI_MODE_SELECT_DP_MST
:
2678 pipe_config
->has_dp_encoder
= true;
2679 intel_dp_get_m_n(intel_crtc
, pipe_config
);
2685 if (intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_AUDIO
)) {
2686 temp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
2687 if (temp
& AUDIO_OUTPUT_ENABLE(intel_crtc
->pipe
))
2688 pipe_config
->has_audio
= true;
2691 if (encoder
->type
== INTEL_OUTPUT_EDP
&& dev_priv
->vbt
.edp_bpp
&&
2692 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
2694 * This is a big fat ugly hack.
2696 * Some machines in UEFI boot mode provide us a VBT that has 18
2697 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2698 * unknown we fail to light up. Yet the same BIOS boots up with
2699 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2700 * max, not what it tells us to use.
2702 * Note: This will still be broken if the eDP panel is not lit
2703 * up by the BIOS, and thus we can't get the mode at module
2706 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2707 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
2708 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
2711 intel_ddi_clock_get(encoder
, pipe_config
);
2714 static void intel_ddi_destroy(struct drm_encoder
*encoder
)
2716 /* HDMI has nothing special to destroy, so we can go with this. */
2717 intel_dp_encoder_destroy(encoder
);
2720 static bool intel_ddi_compute_config(struct intel_encoder
*encoder
,
2721 struct intel_crtc_state
*pipe_config
)
2723 int type
= encoder
->type
;
2724 int port
= intel_ddi_get_encoder_port(encoder
);
2726 WARN(type
== INTEL_OUTPUT_UNKNOWN
, "compute_config() on unknown output!\n");
2729 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
2731 if (type
== INTEL_OUTPUT_HDMI
)
2732 return intel_hdmi_compute_config(encoder
, pipe_config
);
2734 return intel_dp_compute_config(encoder
, pipe_config
);
2737 static const struct drm_encoder_funcs intel_ddi_funcs
= {
2738 .destroy
= intel_ddi_destroy
,
2741 static struct intel_connector
*
2742 intel_ddi_init_dp_connector(struct intel_digital_port
*intel_dig_port
)
2744 struct intel_connector
*connector
;
2745 enum port port
= intel_dig_port
->port
;
2747 connector
= intel_connector_alloc();
2751 intel_dig_port
->dp
.output_reg
= DDI_BUF_CTL(port
);
2752 if (!intel_dp_init_connector(intel_dig_port
, connector
)) {
2760 static struct intel_connector
*
2761 intel_ddi_init_hdmi_connector(struct intel_digital_port
*intel_dig_port
)
2763 struct intel_connector
*connector
;
2764 enum port port
= intel_dig_port
->port
;
2766 connector
= intel_connector_alloc();
2770 intel_dig_port
->hdmi
.hdmi_reg
= DDI_BUF_CTL(port
);
2771 intel_hdmi_init_connector(intel_dig_port
, connector
);
2776 void intel_ddi_init(struct drm_device
*dev
, enum port port
)
2778 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2779 struct intel_digital_port
*intel_dig_port
;
2780 struct intel_encoder
*intel_encoder
;
2781 struct drm_encoder
*encoder
;
2782 bool init_hdmi
, init_dp
;
2784 init_hdmi
= (dev_priv
->vbt
.ddi_port_info
[port
].supports_dvi
||
2785 dev_priv
->vbt
.ddi_port_info
[port
].supports_hdmi
);
2786 init_dp
= dev_priv
->vbt
.ddi_port_info
[port
].supports_dp
;
2787 if (!init_dp
&& !init_hdmi
) {
2788 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
2794 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
2795 if (!intel_dig_port
)
2798 intel_encoder
= &intel_dig_port
->base
;
2799 encoder
= &intel_encoder
->base
;
2801 drm_encoder_init(dev
, encoder
, &intel_ddi_funcs
,
2802 DRM_MODE_ENCODER_TMDS
);
2804 intel_encoder
->compute_config
= intel_ddi_compute_config
;
2805 intel_encoder
->enable
= intel_enable_ddi
;
2806 intel_encoder
->pre_enable
= intel_ddi_pre_enable
;
2807 intel_encoder
->disable
= intel_disable_ddi
;
2808 intel_encoder
->post_disable
= intel_ddi_post_disable
;
2809 intel_encoder
->get_hw_state
= intel_ddi_get_hw_state
;
2810 intel_encoder
->get_config
= intel_ddi_get_config
;
2812 intel_dig_port
->port
= port
;
2813 intel_dig_port
->saved_port_bits
= I915_READ(DDI_BUF_CTL(port
)) &
2814 (DDI_BUF_PORT_REVERSAL
|
2817 intel_encoder
->type
= INTEL_OUTPUT_UNKNOWN
;
2818 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
2819 intel_encoder
->cloneable
= 0;
2822 if (!intel_ddi_init_dp_connector(intel_dig_port
))
2825 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
2826 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
2829 /* In theory we don't need the encoder->type check, but leave it just in
2830 * case we have some really bad VBTs... */
2831 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
&& init_hdmi
) {
2832 if (!intel_ddi_init_hdmi_connector(intel_dig_port
))
2839 drm_encoder_cleanup(encoder
);
2840 kfree(intel_dig_port
);