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drm/i915: Handle return value in intel_pin_and_fence_fb_obj, v2.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
52 DRM_FORMAT_XRGB1555,
53 DRM_FORMAT_XRGB8888,
54 };
55
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64 };
65
66 static const uint32_t skl_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_ARGB8888,
72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
75 };
76
77 /* Cursor formats */
78 static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80 };
81
82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
83
84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
85 struct intel_crtc_state *pipe_config);
86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
87 struct intel_crtc_state *pipe_config);
88
89 static int intel_framebuffer_init(struct drm_device *dev,
90 struct intel_framebuffer *ifb,
91 struct drm_mode_fb_cmd2 *mode_cmd,
92 struct drm_i915_gem_object *obj);
93 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
94 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
95 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
96 struct intel_link_m_n *m_n,
97 struct intel_link_m_n *m2_n2);
98 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
99 static void haswell_set_pipeconf(struct drm_crtc *crtc);
100 static void intel_set_pipe_csc(struct drm_crtc *crtc);
101 static void vlv_prepare_pll(struct intel_crtc *crtc,
102 const struct intel_crtc_state *pipe_config);
103 static void chv_prepare_pll(struct intel_crtc *crtc,
104 const struct intel_crtc_state *pipe_config);
105 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
106 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
107 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
108 struct intel_crtc_state *crtc_state);
109 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
110 int num_connectors);
111 static void intel_modeset_setup_hw_state(struct drm_device *dev);
112
113 typedef struct {
114 int min, max;
115 } intel_range_t;
116
117 typedef struct {
118 int dot_limit;
119 int p2_slow, p2_fast;
120 } intel_p2_t;
121
122 typedef struct intel_limit intel_limit_t;
123 struct intel_limit {
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
126 };
127
128 int
129 intel_pch_rawclk(struct drm_device *dev)
130 {
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136 }
137
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
140 {
141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
146 }
147
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
159 };
160
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172 };
173
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
185 };
186
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
211 };
212
213
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
226 },
227 };
228
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
253 },
254 };
255
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
267 },
268 };
269
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
283 };
284
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
296 };
297
298 /* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
314 };
315
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 };
328
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340 };
341
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
354 };
355
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
367 };
368
369 static const intel_limit_t intel_limits_vlv = {
370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
383 };
384
385 static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4800000, .max = 6480000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399 };
400
401 static const intel_limit_t intel_limits_bxt = {
402 /* FIXME: find real dot limits */
403 .dot = { .min = 0, .max = INT_MAX },
404 .vco = { .min = 4800000, .max = 6700000 },
405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 /* FIXME: find real m2 limits */
408 .m2 = { .min = 2 << 22, .max = 255 << 22 },
409 .p1 = { .min = 2, .max = 4 },
410 .p2 = { .p2_slow = 1, .p2_fast = 20 },
411 };
412
413 static bool
414 needs_modeset(struct drm_crtc_state *state)
415 {
416 return drm_atomic_crtc_needs_modeset(state);
417 }
418
419 /**
420 * Returns whether any output on the specified pipe is of the specified type
421 */
422 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
423 {
424 struct drm_device *dev = crtc->base.dev;
425 struct intel_encoder *encoder;
426
427 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
428 if (encoder->type == type)
429 return true;
430
431 return false;
432 }
433
434 /**
435 * Returns whether any output on the specified pipe will have the specified
436 * type after a staged modeset is complete, i.e., the same as
437 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
438 * encoder->crtc.
439 */
440 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
441 int type)
442 {
443 struct drm_atomic_state *state = crtc_state->base.state;
444 struct drm_connector *connector;
445 struct drm_connector_state *connector_state;
446 struct intel_encoder *encoder;
447 int i, num_connectors = 0;
448
449 for_each_connector_in_state(state, connector, connector_state, i) {
450 if (connector_state->crtc != crtc_state->base.crtc)
451 continue;
452
453 num_connectors++;
454
455 encoder = to_intel_encoder(connector_state->best_encoder);
456 if (encoder->type == type)
457 return true;
458 }
459
460 WARN_ON(num_connectors == 0);
461
462 return false;
463 }
464
465 static const intel_limit_t *
466 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
467 {
468 struct drm_device *dev = crtc_state->base.crtc->dev;
469 const intel_limit_t *limit;
470
471 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
472 if (intel_is_dual_link_lvds(dev)) {
473 if (refclk == 100000)
474 limit = &intel_limits_ironlake_dual_lvds_100m;
475 else
476 limit = &intel_limits_ironlake_dual_lvds;
477 } else {
478 if (refclk == 100000)
479 limit = &intel_limits_ironlake_single_lvds_100m;
480 else
481 limit = &intel_limits_ironlake_single_lvds;
482 }
483 } else
484 limit = &intel_limits_ironlake_dac;
485
486 return limit;
487 }
488
489 static const intel_limit_t *
490 intel_g4x_limit(struct intel_crtc_state *crtc_state)
491 {
492 struct drm_device *dev = crtc_state->base.crtc->dev;
493 const intel_limit_t *limit;
494
495 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
496 if (intel_is_dual_link_lvds(dev))
497 limit = &intel_limits_g4x_dual_channel_lvds;
498 else
499 limit = &intel_limits_g4x_single_channel_lvds;
500 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
501 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
502 limit = &intel_limits_g4x_hdmi;
503 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
504 limit = &intel_limits_g4x_sdvo;
505 } else /* The option is for other outputs */
506 limit = &intel_limits_i9xx_sdvo;
507
508 return limit;
509 }
510
511 static const intel_limit_t *
512 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
513 {
514 struct drm_device *dev = crtc_state->base.crtc->dev;
515 const intel_limit_t *limit;
516
517 if (IS_BROXTON(dev))
518 limit = &intel_limits_bxt;
519 else if (HAS_PCH_SPLIT(dev))
520 limit = intel_ironlake_limit(crtc_state, refclk);
521 else if (IS_G4X(dev)) {
522 limit = intel_g4x_limit(crtc_state);
523 } else if (IS_PINEVIEW(dev)) {
524 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
525 limit = &intel_limits_pineview_lvds;
526 else
527 limit = &intel_limits_pineview_sdvo;
528 } else if (IS_CHERRYVIEW(dev)) {
529 limit = &intel_limits_chv;
530 } else if (IS_VALLEYVIEW(dev)) {
531 limit = &intel_limits_vlv;
532 } else if (!IS_GEN2(dev)) {
533 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
534 limit = &intel_limits_i9xx_lvds;
535 else
536 limit = &intel_limits_i9xx_sdvo;
537 } else {
538 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
539 limit = &intel_limits_i8xx_lvds;
540 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
541 limit = &intel_limits_i8xx_dvo;
542 else
543 limit = &intel_limits_i8xx_dac;
544 }
545 return limit;
546 }
547
548 /*
549 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
550 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
551 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
552 * The helpers' return value is the rate of the clock that is fed to the
553 * display engine's pipe which can be the above fast dot clock rate or a
554 * divided-down version of it.
555 */
556 /* m1 is reserved as 0 in Pineview, n is a ring counter */
557 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
558 {
559 clock->m = clock->m2 + 2;
560 clock->p = clock->p1 * clock->p2;
561 if (WARN_ON(clock->n == 0 || clock->p == 0))
562 return 0;
563 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
564 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
565
566 return clock->dot;
567 }
568
569 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
570 {
571 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
572 }
573
574 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
575 {
576 clock->m = i9xx_dpll_compute_m(clock);
577 clock->p = clock->p1 * clock->p2;
578 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
579 return 0;
580 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
581 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
582
583 return clock->dot;
584 }
585
586 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
587 {
588 clock->m = clock->m1 * clock->m2;
589 clock->p = clock->p1 * clock->p2;
590 if (WARN_ON(clock->n == 0 || clock->p == 0))
591 return 0;
592 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
593 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
594
595 return clock->dot / 5;
596 }
597
598 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
599 {
600 clock->m = clock->m1 * clock->m2;
601 clock->p = clock->p1 * clock->p2;
602 if (WARN_ON(clock->n == 0 || clock->p == 0))
603 return 0;
604 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
605 clock->n << 22);
606 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
607
608 return clock->dot / 5;
609 }
610
611 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
612 /**
613 * Returns whether the given set of divisors are valid for a given refclk with
614 * the given connectors.
615 */
616
617 static bool intel_PLL_is_valid(struct drm_device *dev,
618 const intel_limit_t *limit,
619 const intel_clock_t *clock)
620 {
621 if (clock->n < limit->n.min || limit->n.max < clock->n)
622 INTELPllInvalid("n out of range\n");
623 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
624 INTELPllInvalid("p1 out of range\n");
625 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
626 INTELPllInvalid("m2 out of range\n");
627 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
628 INTELPllInvalid("m1 out of range\n");
629
630 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
631 if (clock->m1 <= clock->m2)
632 INTELPllInvalid("m1 <= m2\n");
633
634 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
635 if (clock->p < limit->p.min || limit->p.max < clock->p)
636 INTELPllInvalid("p out of range\n");
637 if (clock->m < limit->m.min || limit->m.max < clock->m)
638 INTELPllInvalid("m out of range\n");
639 }
640
641 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
642 INTELPllInvalid("vco out of range\n");
643 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
644 * connector, etc., rather than just a single range.
645 */
646 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
647 INTELPllInvalid("dot out of range\n");
648
649 return true;
650 }
651
652 static int
653 i9xx_select_p2_div(const intel_limit_t *limit,
654 const struct intel_crtc_state *crtc_state,
655 int target)
656 {
657 struct drm_device *dev = crtc_state->base.crtc->dev;
658
659 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
660 /*
661 * For LVDS just rely on its current settings for dual-channel.
662 * We haven't figured out how to reliably set up different
663 * single/dual channel state, if we even can.
664 */
665 if (intel_is_dual_link_lvds(dev))
666 return limit->p2.p2_fast;
667 else
668 return limit->p2.p2_slow;
669 } else {
670 if (target < limit->p2.dot_limit)
671 return limit->p2.p2_slow;
672 else
673 return limit->p2.p2_fast;
674 }
675 }
676
677 static bool
678 i9xx_find_best_dpll(const intel_limit_t *limit,
679 struct intel_crtc_state *crtc_state,
680 int target, int refclk, intel_clock_t *match_clock,
681 intel_clock_t *best_clock)
682 {
683 struct drm_device *dev = crtc_state->base.crtc->dev;
684 intel_clock_t clock;
685 int err = target;
686
687 memset(best_clock, 0, sizeof(*best_clock));
688
689 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
690
691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
692 clock.m1++) {
693 for (clock.m2 = limit->m2.min;
694 clock.m2 <= limit->m2.max; clock.m2++) {
695 if (clock.m2 >= clock.m1)
696 break;
697 for (clock.n = limit->n.min;
698 clock.n <= limit->n.max; clock.n++) {
699 for (clock.p1 = limit->p1.min;
700 clock.p1 <= limit->p1.max; clock.p1++) {
701 int this_err;
702
703 i9xx_calc_dpll_params(refclk, &clock);
704 if (!intel_PLL_is_valid(dev, limit,
705 &clock))
706 continue;
707 if (match_clock &&
708 clock.p != match_clock->p)
709 continue;
710
711 this_err = abs(clock.dot - target);
712 if (this_err < err) {
713 *best_clock = clock;
714 err = this_err;
715 }
716 }
717 }
718 }
719 }
720
721 return (err != target);
722 }
723
724 static bool
725 pnv_find_best_dpll(const intel_limit_t *limit,
726 struct intel_crtc_state *crtc_state,
727 int target, int refclk, intel_clock_t *match_clock,
728 intel_clock_t *best_clock)
729 {
730 struct drm_device *dev = crtc_state->base.crtc->dev;
731 intel_clock_t clock;
732 int err = target;
733
734 memset(best_clock, 0, sizeof(*best_clock));
735
736 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
737
738 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
739 clock.m1++) {
740 for (clock.m2 = limit->m2.min;
741 clock.m2 <= limit->m2.max; clock.m2++) {
742 for (clock.n = limit->n.min;
743 clock.n <= limit->n.max; clock.n++) {
744 for (clock.p1 = limit->p1.min;
745 clock.p1 <= limit->p1.max; clock.p1++) {
746 int this_err;
747
748 pnv_calc_dpll_params(refclk, &clock);
749 if (!intel_PLL_is_valid(dev, limit,
750 &clock))
751 continue;
752 if (match_clock &&
753 clock.p != match_clock->p)
754 continue;
755
756 this_err = abs(clock.dot - target);
757 if (this_err < err) {
758 *best_clock = clock;
759 err = this_err;
760 }
761 }
762 }
763 }
764 }
765
766 return (err != target);
767 }
768
769 static bool
770 g4x_find_best_dpll(const intel_limit_t *limit,
771 struct intel_crtc_state *crtc_state,
772 int target, int refclk, intel_clock_t *match_clock,
773 intel_clock_t *best_clock)
774 {
775 struct drm_device *dev = crtc_state->base.crtc->dev;
776 intel_clock_t clock;
777 int max_n;
778 bool found = false;
779 /* approximately equals target * 0.00585 */
780 int err_most = (target >> 8) + (target >> 9);
781
782 memset(best_clock, 0, sizeof(*best_clock));
783
784 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
785
786 max_n = limit->n.max;
787 /* based on hardware requirement, prefer smaller n to precision */
788 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
789 /* based on hardware requirement, prefere larger m1,m2 */
790 for (clock.m1 = limit->m1.max;
791 clock.m1 >= limit->m1.min; clock.m1--) {
792 for (clock.m2 = limit->m2.max;
793 clock.m2 >= limit->m2.min; clock.m2--) {
794 for (clock.p1 = limit->p1.max;
795 clock.p1 >= limit->p1.min; clock.p1--) {
796 int this_err;
797
798 i9xx_calc_dpll_params(refclk, &clock);
799 if (!intel_PLL_is_valid(dev, limit,
800 &clock))
801 continue;
802
803 this_err = abs(clock.dot - target);
804 if (this_err < err_most) {
805 *best_clock = clock;
806 err_most = this_err;
807 max_n = clock.n;
808 found = true;
809 }
810 }
811 }
812 }
813 }
814 return found;
815 }
816
817 /*
818 * Check if the calculated PLL configuration is more optimal compared to the
819 * best configuration and error found so far. Return the calculated error.
820 */
821 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
822 const intel_clock_t *calculated_clock,
823 const intel_clock_t *best_clock,
824 unsigned int best_error_ppm,
825 unsigned int *error_ppm)
826 {
827 /*
828 * For CHV ignore the error and consider only the P value.
829 * Prefer a bigger P value based on HW requirements.
830 */
831 if (IS_CHERRYVIEW(dev)) {
832 *error_ppm = 0;
833
834 return calculated_clock->p > best_clock->p;
835 }
836
837 if (WARN_ON_ONCE(!target_freq))
838 return false;
839
840 *error_ppm = div_u64(1000000ULL *
841 abs(target_freq - calculated_clock->dot),
842 target_freq);
843 /*
844 * Prefer a better P value over a better (smaller) error if the error
845 * is small. Ensure this preference for future configurations too by
846 * setting the error to 0.
847 */
848 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
849 *error_ppm = 0;
850
851 return true;
852 }
853
854 return *error_ppm + 10 < best_error_ppm;
855 }
856
857 static bool
858 vlv_find_best_dpll(const intel_limit_t *limit,
859 struct intel_crtc_state *crtc_state,
860 int target, int refclk, intel_clock_t *match_clock,
861 intel_clock_t *best_clock)
862 {
863 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
864 struct drm_device *dev = crtc->base.dev;
865 intel_clock_t clock;
866 unsigned int bestppm = 1000000;
867 /* min update 19.2 MHz */
868 int max_n = min(limit->n.max, refclk / 19200);
869 bool found = false;
870
871 target *= 5; /* fast clock */
872
873 memset(best_clock, 0, sizeof(*best_clock));
874
875 /* based on hardware requirement, prefer smaller n to precision */
876 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
877 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
878 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
879 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
880 clock.p = clock.p1 * clock.p2;
881 /* based on hardware requirement, prefer bigger m1,m2 values */
882 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
883 unsigned int ppm;
884
885 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
886 refclk * clock.m1);
887
888 vlv_calc_dpll_params(refclk, &clock);
889
890 if (!intel_PLL_is_valid(dev, limit,
891 &clock))
892 continue;
893
894 if (!vlv_PLL_is_optimal(dev, target,
895 &clock,
896 best_clock,
897 bestppm, &ppm))
898 continue;
899
900 *best_clock = clock;
901 bestppm = ppm;
902 found = true;
903 }
904 }
905 }
906 }
907
908 return found;
909 }
910
911 static bool
912 chv_find_best_dpll(const intel_limit_t *limit,
913 struct intel_crtc_state *crtc_state,
914 int target, int refclk, intel_clock_t *match_clock,
915 intel_clock_t *best_clock)
916 {
917 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
918 struct drm_device *dev = crtc->base.dev;
919 unsigned int best_error_ppm;
920 intel_clock_t clock;
921 uint64_t m2;
922 int found = false;
923
924 memset(best_clock, 0, sizeof(*best_clock));
925 best_error_ppm = 1000000;
926
927 /*
928 * Based on hardware doc, the n always set to 1, and m1 always
929 * set to 2. If requires to support 200Mhz refclk, we need to
930 * revisit this because n may not 1 anymore.
931 */
932 clock.n = 1, clock.m1 = 2;
933 target *= 5; /* fast clock */
934
935 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
936 for (clock.p2 = limit->p2.p2_fast;
937 clock.p2 >= limit->p2.p2_slow;
938 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
939 unsigned int error_ppm;
940
941 clock.p = clock.p1 * clock.p2;
942
943 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
944 clock.n) << 22, refclk * clock.m1);
945
946 if (m2 > INT_MAX/clock.m1)
947 continue;
948
949 clock.m2 = m2;
950
951 chv_calc_dpll_params(refclk, &clock);
952
953 if (!intel_PLL_is_valid(dev, limit, &clock))
954 continue;
955
956 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
957 best_error_ppm, &error_ppm))
958 continue;
959
960 *best_clock = clock;
961 best_error_ppm = error_ppm;
962 found = true;
963 }
964 }
965
966 return found;
967 }
968
969 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
970 intel_clock_t *best_clock)
971 {
972 int refclk = i9xx_get_refclk(crtc_state, 0);
973
974 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
975 target_clock, refclk, NULL, best_clock);
976 }
977
978 bool intel_crtc_active(struct drm_crtc *crtc)
979 {
980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
981
982 /* Be paranoid as we can arrive here with only partial
983 * state retrieved from the hardware during setup.
984 *
985 * We can ditch the adjusted_mode.crtc_clock check as soon
986 * as Haswell has gained clock readout/fastboot support.
987 *
988 * We can ditch the crtc->primary->fb check as soon as we can
989 * properly reconstruct framebuffers.
990 *
991 * FIXME: The intel_crtc->active here should be switched to
992 * crtc->state->active once we have proper CRTC states wired up
993 * for atomic.
994 */
995 return intel_crtc->active && crtc->primary->state->fb &&
996 intel_crtc->config->base.adjusted_mode.crtc_clock;
997 }
998
999 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1000 enum pipe pipe)
1001 {
1002 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1004
1005 return intel_crtc->config->cpu_transcoder;
1006 }
1007
1008 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1009 {
1010 struct drm_i915_private *dev_priv = dev->dev_private;
1011 u32 reg = PIPEDSL(pipe);
1012 u32 line1, line2;
1013 u32 line_mask;
1014
1015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
1020 line1 = I915_READ(reg) & line_mask;
1021 msleep(5);
1022 line2 = I915_READ(reg) & line_mask;
1023
1024 return line1 == line2;
1025 }
1026
1027 /*
1028 * intel_wait_for_pipe_off - wait for pipe to turn off
1029 * @crtc: crtc whose pipe to wait for
1030 *
1031 * After disabling a pipe, we can't wait for vblank in the usual way,
1032 * spinning on the vblank interrupt status bit, since we won't actually
1033 * see an interrupt when the pipe is disabled.
1034 *
1035 * On Gen4 and above:
1036 * wait for the pipe register state bit to turn off
1037 *
1038 * Otherwise:
1039 * wait for the display line value to settle (it usually
1040 * ends up stopping at the start of the next frame).
1041 *
1042 */
1043 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1044 {
1045 struct drm_device *dev = crtc->base.dev;
1046 struct drm_i915_private *dev_priv = dev->dev_private;
1047 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1048 enum pipe pipe = crtc->pipe;
1049
1050 if (INTEL_INFO(dev)->gen >= 4) {
1051 int reg = PIPECONF(cpu_transcoder);
1052
1053 /* Wait for the Pipe State to go off */
1054 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1055 100))
1056 WARN(1, "pipe_off wait timed out\n");
1057 } else {
1058 /* Wait for the display line to settle */
1059 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1060 WARN(1, "pipe_off wait timed out\n");
1061 }
1062 }
1063
1064 /*
1065 * ibx_digital_port_connected - is the specified port connected?
1066 * @dev_priv: i915 private structure
1067 * @port: the port to test
1068 *
1069 * Returns true if @port is connected, false otherwise.
1070 */
1071 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1072 struct intel_digital_port *port)
1073 {
1074 u32 bit;
1075
1076 if (HAS_PCH_IBX(dev_priv->dev)) {
1077 switch (port->port) {
1078 case PORT_B:
1079 bit = SDE_PORTB_HOTPLUG;
1080 break;
1081 case PORT_C:
1082 bit = SDE_PORTC_HOTPLUG;
1083 break;
1084 case PORT_D:
1085 bit = SDE_PORTD_HOTPLUG;
1086 break;
1087 default:
1088 return true;
1089 }
1090 } else {
1091 switch (port->port) {
1092 case PORT_B:
1093 bit = SDE_PORTB_HOTPLUG_CPT;
1094 break;
1095 case PORT_C:
1096 bit = SDE_PORTC_HOTPLUG_CPT;
1097 break;
1098 case PORT_D:
1099 bit = SDE_PORTD_HOTPLUG_CPT;
1100 break;
1101 default:
1102 return true;
1103 }
1104 }
1105
1106 return I915_READ(SDEISR) & bit;
1107 }
1108
1109 static const char *state_string(bool enabled)
1110 {
1111 return enabled ? "on" : "off";
1112 }
1113
1114 /* Only for pre-ILK configs */
1115 void assert_pll(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1117 {
1118 int reg;
1119 u32 val;
1120 bool cur_state;
1121
1122 reg = DPLL(pipe);
1123 val = I915_READ(reg);
1124 cur_state = !!(val & DPLL_VCO_ENABLE);
1125 I915_STATE_WARN(cur_state != state,
1126 "PLL state assertion failure (expected %s, current %s)\n",
1127 state_string(state), state_string(cur_state));
1128 }
1129
1130 /* XXX: the dsi pll is shared between MIPI DSI ports */
1131 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1132 {
1133 u32 val;
1134 bool cur_state;
1135
1136 mutex_lock(&dev_priv->sb_lock);
1137 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1138 mutex_unlock(&dev_priv->sb_lock);
1139
1140 cur_state = val & DSI_PLL_VCO_EN;
1141 I915_STATE_WARN(cur_state != state,
1142 "DSI PLL state assertion failure (expected %s, current %s)\n",
1143 state_string(state), state_string(cur_state));
1144 }
1145 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1146 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1147
1148 struct intel_shared_dpll *
1149 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1150 {
1151 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1152
1153 if (crtc->config->shared_dpll < 0)
1154 return NULL;
1155
1156 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1157 }
1158
1159 /* For ILK+ */
1160 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1161 struct intel_shared_dpll *pll,
1162 bool state)
1163 {
1164 bool cur_state;
1165 struct intel_dpll_hw_state hw_state;
1166
1167 if (WARN (!pll,
1168 "asserting DPLL %s with no DPLL\n", state_string(state)))
1169 return;
1170
1171 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1172 I915_STATE_WARN(cur_state != state,
1173 "%s assertion failure (expected %s, current %s)\n",
1174 pll->name, state_string(state), state_string(cur_state));
1175 }
1176
1177 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1178 enum pipe pipe, bool state)
1179 {
1180 int reg;
1181 u32 val;
1182 bool cur_state;
1183 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1184 pipe);
1185
1186 if (HAS_DDI(dev_priv->dev)) {
1187 /* DDI does not have a specific FDI_TX register */
1188 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1189 val = I915_READ(reg);
1190 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1191 } else {
1192 reg = FDI_TX_CTL(pipe);
1193 val = I915_READ(reg);
1194 cur_state = !!(val & FDI_TX_ENABLE);
1195 }
1196 I915_STATE_WARN(cur_state != state,
1197 "FDI TX state assertion failure (expected %s, current %s)\n",
1198 state_string(state), state_string(cur_state));
1199 }
1200 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1201 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1202
1203 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1204 enum pipe pipe, bool state)
1205 {
1206 int reg;
1207 u32 val;
1208 bool cur_state;
1209
1210 reg = FDI_RX_CTL(pipe);
1211 val = I915_READ(reg);
1212 cur_state = !!(val & FDI_RX_ENABLE);
1213 I915_STATE_WARN(cur_state != state,
1214 "FDI RX state assertion failure (expected %s, current %s)\n",
1215 state_string(state), state_string(cur_state));
1216 }
1217 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1218 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1219
1220 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1221 enum pipe pipe)
1222 {
1223 int reg;
1224 u32 val;
1225
1226 /* ILK FDI PLL is always enabled */
1227 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1228 return;
1229
1230 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1231 if (HAS_DDI(dev_priv->dev))
1232 return;
1233
1234 reg = FDI_TX_CTL(pipe);
1235 val = I915_READ(reg);
1236 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1237 }
1238
1239 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, bool state)
1241 {
1242 int reg;
1243 u32 val;
1244 bool cur_state;
1245
1246 reg = FDI_RX_CTL(pipe);
1247 val = I915_READ(reg);
1248 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1249 I915_STATE_WARN(cur_state != state,
1250 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1251 state_string(state), state_string(cur_state));
1252 }
1253
1254 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1255 enum pipe pipe)
1256 {
1257 struct drm_device *dev = dev_priv->dev;
1258 int pp_reg;
1259 u32 val;
1260 enum pipe panel_pipe = PIPE_A;
1261 bool locked = true;
1262
1263 if (WARN_ON(HAS_DDI(dev)))
1264 return;
1265
1266 if (HAS_PCH_SPLIT(dev)) {
1267 u32 port_sel;
1268
1269 pp_reg = PCH_PP_CONTROL;
1270 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1271
1272 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1273 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1274 panel_pipe = PIPE_B;
1275 /* XXX: else fix for eDP */
1276 } else if (IS_VALLEYVIEW(dev)) {
1277 /* presumably write lock depends on pipe, not port select */
1278 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1279 panel_pipe = pipe;
1280 } else {
1281 pp_reg = PP_CONTROL;
1282 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1283 panel_pipe = PIPE_B;
1284 }
1285
1286 val = I915_READ(pp_reg);
1287 if (!(val & PANEL_POWER_ON) ||
1288 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1289 locked = false;
1290
1291 I915_STATE_WARN(panel_pipe == pipe && locked,
1292 "panel assertion failure, pipe %c regs locked\n",
1293 pipe_name(pipe));
1294 }
1295
1296 static void assert_cursor(struct drm_i915_private *dev_priv,
1297 enum pipe pipe, bool state)
1298 {
1299 struct drm_device *dev = dev_priv->dev;
1300 bool cur_state;
1301
1302 if (IS_845G(dev) || IS_I865G(dev))
1303 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1304 else
1305 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1306
1307 I915_STATE_WARN(cur_state != state,
1308 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1309 pipe_name(pipe), state_string(state), state_string(cur_state));
1310 }
1311 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1312 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1313
1314 void assert_pipe(struct drm_i915_private *dev_priv,
1315 enum pipe pipe, bool state)
1316 {
1317 int reg;
1318 u32 val;
1319 bool cur_state;
1320 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1321 pipe);
1322
1323 /* if we need the pipe quirk it must be always on */
1324 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1325 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1326 state = true;
1327
1328 if (!intel_display_power_is_enabled(dev_priv,
1329 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1330 cur_state = false;
1331 } else {
1332 reg = PIPECONF(cpu_transcoder);
1333 val = I915_READ(reg);
1334 cur_state = !!(val & PIPECONF_ENABLE);
1335 }
1336
1337 I915_STATE_WARN(cur_state != state,
1338 "pipe %c assertion failure (expected %s, current %s)\n",
1339 pipe_name(pipe), state_string(state), state_string(cur_state));
1340 }
1341
1342 static void assert_plane(struct drm_i915_private *dev_priv,
1343 enum plane plane, bool state)
1344 {
1345 int reg;
1346 u32 val;
1347 bool cur_state;
1348
1349 reg = DSPCNTR(plane);
1350 val = I915_READ(reg);
1351 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1352 I915_STATE_WARN(cur_state != state,
1353 "plane %c assertion failure (expected %s, current %s)\n",
1354 plane_name(plane), state_string(state), state_string(cur_state));
1355 }
1356
1357 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1358 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1359
1360 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1361 enum pipe pipe)
1362 {
1363 struct drm_device *dev = dev_priv->dev;
1364 int reg, i;
1365 u32 val;
1366 int cur_pipe;
1367
1368 /* Primary planes are fixed to pipes on gen4+ */
1369 if (INTEL_INFO(dev)->gen >= 4) {
1370 reg = DSPCNTR(pipe);
1371 val = I915_READ(reg);
1372 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1373 "plane %c assertion failure, should be disabled but not\n",
1374 plane_name(pipe));
1375 return;
1376 }
1377
1378 /* Need to check both planes against the pipe */
1379 for_each_pipe(dev_priv, i) {
1380 reg = DSPCNTR(i);
1381 val = I915_READ(reg);
1382 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1383 DISPPLANE_SEL_PIPE_SHIFT;
1384 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1385 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1386 plane_name(i), pipe_name(pipe));
1387 }
1388 }
1389
1390 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1391 enum pipe pipe)
1392 {
1393 struct drm_device *dev = dev_priv->dev;
1394 int reg, sprite;
1395 u32 val;
1396
1397 if (INTEL_INFO(dev)->gen >= 9) {
1398 for_each_sprite(dev_priv, pipe, sprite) {
1399 val = I915_READ(PLANE_CTL(pipe, sprite));
1400 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1401 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1402 sprite, pipe_name(pipe));
1403 }
1404 } else if (IS_VALLEYVIEW(dev)) {
1405 for_each_sprite(dev_priv, pipe, sprite) {
1406 reg = SPCNTR(pipe, sprite);
1407 val = I915_READ(reg);
1408 I915_STATE_WARN(val & SP_ENABLE,
1409 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1410 sprite_name(pipe, sprite), pipe_name(pipe));
1411 }
1412 } else if (INTEL_INFO(dev)->gen >= 7) {
1413 reg = SPRCTL(pipe);
1414 val = I915_READ(reg);
1415 I915_STATE_WARN(val & SPRITE_ENABLE,
1416 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1417 plane_name(pipe), pipe_name(pipe));
1418 } else if (INTEL_INFO(dev)->gen >= 5) {
1419 reg = DVSCNTR(pipe);
1420 val = I915_READ(reg);
1421 I915_STATE_WARN(val & DVS_ENABLE,
1422 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1423 plane_name(pipe), pipe_name(pipe));
1424 }
1425 }
1426
1427 static void assert_vblank_disabled(struct drm_crtc *crtc)
1428 {
1429 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1430 drm_crtc_vblank_put(crtc);
1431 }
1432
1433 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1434 {
1435 u32 val;
1436 bool enabled;
1437
1438 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1439
1440 val = I915_READ(PCH_DREF_CONTROL);
1441 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1442 DREF_SUPERSPREAD_SOURCE_MASK));
1443 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1444 }
1445
1446 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1447 enum pipe pipe)
1448 {
1449 int reg;
1450 u32 val;
1451 bool enabled;
1452
1453 reg = PCH_TRANSCONF(pipe);
1454 val = I915_READ(reg);
1455 enabled = !!(val & TRANS_ENABLE);
1456 I915_STATE_WARN(enabled,
1457 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1458 pipe_name(pipe));
1459 }
1460
1461 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1462 enum pipe pipe, u32 port_sel, u32 val)
1463 {
1464 if ((val & DP_PORT_EN) == 0)
1465 return false;
1466
1467 if (HAS_PCH_CPT(dev_priv->dev)) {
1468 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1469 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1470 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1471 return false;
1472 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1473 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1474 return false;
1475 } else {
1476 if ((val & DP_PIPE_MASK) != (pipe << 30))
1477 return false;
1478 }
1479 return true;
1480 }
1481
1482 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1483 enum pipe pipe, u32 val)
1484 {
1485 if ((val & SDVO_ENABLE) == 0)
1486 return false;
1487
1488 if (HAS_PCH_CPT(dev_priv->dev)) {
1489 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1490 return false;
1491 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1492 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1493 return false;
1494 } else {
1495 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1496 return false;
1497 }
1498 return true;
1499 }
1500
1501 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1502 enum pipe pipe, u32 val)
1503 {
1504 if ((val & LVDS_PORT_EN) == 0)
1505 return false;
1506
1507 if (HAS_PCH_CPT(dev_priv->dev)) {
1508 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1509 return false;
1510 } else {
1511 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1512 return false;
1513 }
1514 return true;
1515 }
1516
1517 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1518 enum pipe pipe, u32 val)
1519 {
1520 if ((val & ADPA_DAC_ENABLE) == 0)
1521 return false;
1522 if (HAS_PCH_CPT(dev_priv->dev)) {
1523 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1524 return false;
1525 } else {
1526 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1527 return false;
1528 }
1529 return true;
1530 }
1531
1532 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1533 enum pipe pipe, int reg, u32 port_sel)
1534 {
1535 u32 val = I915_READ(reg);
1536 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1537 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1538 reg, pipe_name(pipe));
1539
1540 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1541 && (val & DP_PIPEB_SELECT),
1542 "IBX PCH dp port still using transcoder B\n");
1543 }
1544
1545 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1546 enum pipe pipe, int reg)
1547 {
1548 u32 val = I915_READ(reg);
1549 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1550 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1551 reg, pipe_name(pipe));
1552
1553 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1554 && (val & SDVO_PIPE_B_SELECT),
1555 "IBX PCH hdmi port still using transcoder B\n");
1556 }
1557
1558 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1559 enum pipe pipe)
1560 {
1561 int reg;
1562 u32 val;
1563
1564 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1565 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1566 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1567
1568 reg = PCH_ADPA;
1569 val = I915_READ(reg);
1570 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1571 "PCH VGA enabled on transcoder %c, should be disabled\n",
1572 pipe_name(pipe));
1573
1574 reg = PCH_LVDS;
1575 val = I915_READ(reg);
1576 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1577 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1578 pipe_name(pipe));
1579
1580 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1581 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1582 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1583 }
1584
1585 static void intel_init_dpio(struct drm_device *dev)
1586 {
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1588
1589 if (!IS_VALLEYVIEW(dev))
1590 return;
1591
1592 /*
1593 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1594 * CHV x1 PHY (DP/HDMI D)
1595 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1596 */
1597 if (IS_CHERRYVIEW(dev)) {
1598 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1599 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1600 } else {
1601 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1602 }
1603 }
1604
1605 static void vlv_enable_pll(struct intel_crtc *crtc,
1606 const struct intel_crtc_state *pipe_config)
1607 {
1608 struct drm_device *dev = crtc->base.dev;
1609 struct drm_i915_private *dev_priv = dev->dev_private;
1610 int reg = DPLL(crtc->pipe);
1611 u32 dpll = pipe_config->dpll_hw_state.dpll;
1612
1613 assert_pipe_disabled(dev_priv, crtc->pipe);
1614
1615 /* No really, not for ILK+ */
1616 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1617
1618 /* PLL is protected by panel, make sure we can write it */
1619 if (IS_MOBILE(dev_priv->dev))
1620 assert_panel_unlocked(dev_priv, crtc->pipe);
1621
1622 I915_WRITE(reg, dpll);
1623 POSTING_READ(reg);
1624 udelay(150);
1625
1626 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1627 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1628
1629 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1630 POSTING_READ(DPLL_MD(crtc->pipe));
1631
1632 /* We do this three times for luck */
1633 I915_WRITE(reg, dpll);
1634 POSTING_READ(reg);
1635 udelay(150); /* wait for warmup */
1636 I915_WRITE(reg, dpll);
1637 POSTING_READ(reg);
1638 udelay(150); /* wait for warmup */
1639 I915_WRITE(reg, dpll);
1640 POSTING_READ(reg);
1641 udelay(150); /* wait for warmup */
1642 }
1643
1644 static void chv_enable_pll(struct intel_crtc *crtc,
1645 const struct intel_crtc_state *pipe_config)
1646 {
1647 struct drm_device *dev = crtc->base.dev;
1648 struct drm_i915_private *dev_priv = dev->dev_private;
1649 int pipe = crtc->pipe;
1650 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1651 u32 tmp;
1652
1653 assert_pipe_disabled(dev_priv, crtc->pipe);
1654
1655 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1656
1657 mutex_lock(&dev_priv->sb_lock);
1658
1659 /* Enable back the 10bit clock to display controller */
1660 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1661 tmp |= DPIO_DCLKP_EN;
1662 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1663
1664 mutex_unlock(&dev_priv->sb_lock);
1665
1666 /*
1667 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1668 */
1669 udelay(1);
1670
1671 /* Enable PLL */
1672 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1673
1674 /* Check PLL is locked */
1675 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1676 DRM_ERROR("PLL %d failed to lock\n", pipe);
1677
1678 /* not sure when this should be written */
1679 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1680 POSTING_READ(DPLL_MD(pipe));
1681 }
1682
1683 static int intel_num_dvo_pipes(struct drm_device *dev)
1684 {
1685 struct intel_crtc *crtc;
1686 int count = 0;
1687
1688 for_each_intel_crtc(dev, crtc)
1689 count += crtc->base.state->active &&
1690 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1691
1692 return count;
1693 }
1694
1695 static void i9xx_enable_pll(struct intel_crtc *crtc)
1696 {
1697 struct drm_device *dev = crtc->base.dev;
1698 struct drm_i915_private *dev_priv = dev->dev_private;
1699 int reg = DPLL(crtc->pipe);
1700 u32 dpll = crtc->config->dpll_hw_state.dpll;
1701
1702 assert_pipe_disabled(dev_priv, crtc->pipe);
1703
1704 /* No really, not for ILK+ */
1705 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1706
1707 /* PLL is protected by panel, make sure we can write it */
1708 if (IS_MOBILE(dev) && !IS_I830(dev))
1709 assert_panel_unlocked(dev_priv, crtc->pipe);
1710
1711 /* Enable DVO 2x clock on both PLLs if necessary */
1712 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1713 /*
1714 * It appears to be important that we don't enable this
1715 * for the current pipe before otherwise configuring the
1716 * PLL. No idea how this should be handled if multiple
1717 * DVO outputs are enabled simultaneosly.
1718 */
1719 dpll |= DPLL_DVO_2X_MODE;
1720 I915_WRITE(DPLL(!crtc->pipe),
1721 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1722 }
1723
1724 /* Wait for the clocks to stabilize. */
1725 POSTING_READ(reg);
1726 udelay(150);
1727
1728 if (INTEL_INFO(dev)->gen >= 4) {
1729 I915_WRITE(DPLL_MD(crtc->pipe),
1730 crtc->config->dpll_hw_state.dpll_md);
1731 } else {
1732 /* The pixel multiplier can only be updated once the
1733 * DPLL is enabled and the clocks are stable.
1734 *
1735 * So write it again.
1736 */
1737 I915_WRITE(reg, dpll);
1738 }
1739
1740 /* We do this three times for luck */
1741 I915_WRITE(reg, dpll);
1742 POSTING_READ(reg);
1743 udelay(150); /* wait for warmup */
1744 I915_WRITE(reg, dpll);
1745 POSTING_READ(reg);
1746 udelay(150); /* wait for warmup */
1747 I915_WRITE(reg, dpll);
1748 POSTING_READ(reg);
1749 udelay(150); /* wait for warmup */
1750 }
1751
1752 /**
1753 * i9xx_disable_pll - disable a PLL
1754 * @dev_priv: i915 private structure
1755 * @pipe: pipe PLL to disable
1756 *
1757 * Disable the PLL for @pipe, making sure the pipe is off first.
1758 *
1759 * Note! This is for pre-ILK only.
1760 */
1761 static void i9xx_disable_pll(struct intel_crtc *crtc)
1762 {
1763 struct drm_device *dev = crtc->base.dev;
1764 struct drm_i915_private *dev_priv = dev->dev_private;
1765 enum pipe pipe = crtc->pipe;
1766
1767 /* Disable DVO 2x clock on both PLLs if necessary */
1768 if (IS_I830(dev) &&
1769 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1770 !intel_num_dvo_pipes(dev)) {
1771 I915_WRITE(DPLL(PIPE_B),
1772 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1773 I915_WRITE(DPLL(PIPE_A),
1774 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1775 }
1776
1777 /* Don't disable pipe or pipe PLLs if needed */
1778 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1779 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1780 return;
1781
1782 /* Make sure the pipe isn't still relying on us */
1783 assert_pipe_disabled(dev_priv, pipe);
1784
1785 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1786 POSTING_READ(DPLL(pipe));
1787 }
1788
1789 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1790 {
1791 u32 val;
1792
1793 /* Make sure the pipe isn't still relying on us */
1794 assert_pipe_disabled(dev_priv, pipe);
1795
1796 /*
1797 * Leave integrated clock source and reference clock enabled for pipe B.
1798 * The latter is needed for VGA hotplug / manual detection.
1799 */
1800 val = DPLL_VGA_MODE_DIS;
1801 if (pipe == PIPE_B)
1802 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1803 I915_WRITE(DPLL(pipe), val);
1804 POSTING_READ(DPLL(pipe));
1805
1806 }
1807
1808 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1809 {
1810 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1811 u32 val;
1812
1813 /* Make sure the pipe isn't still relying on us */
1814 assert_pipe_disabled(dev_priv, pipe);
1815
1816 /* Set PLL en = 0 */
1817 val = DPLL_SSC_REF_CLK_CHV |
1818 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1819 if (pipe != PIPE_A)
1820 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1821 I915_WRITE(DPLL(pipe), val);
1822 POSTING_READ(DPLL(pipe));
1823
1824 mutex_lock(&dev_priv->sb_lock);
1825
1826 /* Disable 10bit clock to display controller */
1827 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1828 val &= ~DPIO_DCLKP_EN;
1829 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1830
1831 /* disable left/right clock distribution */
1832 if (pipe != PIPE_B) {
1833 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1834 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1835 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1836 } else {
1837 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1838 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1839 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1840 }
1841
1842 mutex_unlock(&dev_priv->sb_lock);
1843 }
1844
1845 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1846 struct intel_digital_port *dport,
1847 unsigned int expected_mask)
1848 {
1849 u32 port_mask;
1850 int dpll_reg;
1851
1852 switch (dport->port) {
1853 case PORT_B:
1854 port_mask = DPLL_PORTB_READY_MASK;
1855 dpll_reg = DPLL(0);
1856 break;
1857 case PORT_C:
1858 port_mask = DPLL_PORTC_READY_MASK;
1859 dpll_reg = DPLL(0);
1860 expected_mask <<= 4;
1861 break;
1862 case PORT_D:
1863 port_mask = DPLL_PORTD_READY_MASK;
1864 dpll_reg = DPIO_PHY_STATUS;
1865 break;
1866 default:
1867 BUG();
1868 }
1869
1870 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1871 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1872 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1873 }
1874
1875 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1876 {
1877 struct drm_device *dev = crtc->base.dev;
1878 struct drm_i915_private *dev_priv = dev->dev_private;
1879 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1880
1881 if (WARN_ON(pll == NULL))
1882 return;
1883
1884 WARN_ON(!pll->config.crtc_mask);
1885 if (pll->active == 0) {
1886 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1887 WARN_ON(pll->on);
1888 assert_shared_dpll_disabled(dev_priv, pll);
1889
1890 pll->mode_set(dev_priv, pll);
1891 }
1892 }
1893
1894 /**
1895 * intel_enable_shared_dpll - enable PCH PLL
1896 * @dev_priv: i915 private structure
1897 * @pipe: pipe PLL to enable
1898 *
1899 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1900 * drives the transcoder clock.
1901 */
1902 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1903 {
1904 struct drm_device *dev = crtc->base.dev;
1905 struct drm_i915_private *dev_priv = dev->dev_private;
1906 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1907
1908 if (WARN_ON(pll == NULL))
1909 return;
1910
1911 if (WARN_ON(pll->config.crtc_mask == 0))
1912 return;
1913
1914 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1915 pll->name, pll->active, pll->on,
1916 crtc->base.base.id);
1917
1918 if (pll->active++) {
1919 WARN_ON(!pll->on);
1920 assert_shared_dpll_enabled(dev_priv, pll);
1921 return;
1922 }
1923 WARN_ON(pll->on);
1924
1925 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1926
1927 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1928 pll->enable(dev_priv, pll);
1929 pll->on = true;
1930 }
1931
1932 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1933 {
1934 struct drm_device *dev = crtc->base.dev;
1935 struct drm_i915_private *dev_priv = dev->dev_private;
1936 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1937
1938 /* PCH only available on ILK+ */
1939 if (INTEL_INFO(dev)->gen < 5)
1940 return;
1941
1942 if (pll == NULL)
1943 return;
1944
1945 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1946 return;
1947
1948 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1949 pll->name, pll->active, pll->on,
1950 crtc->base.base.id);
1951
1952 if (WARN_ON(pll->active == 0)) {
1953 assert_shared_dpll_disabled(dev_priv, pll);
1954 return;
1955 }
1956
1957 assert_shared_dpll_enabled(dev_priv, pll);
1958 WARN_ON(!pll->on);
1959 if (--pll->active)
1960 return;
1961
1962 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1963 pll->disable(dev_priv, pll);
1964 pll->on = false;
1965
1966 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1967 }
1968
1969 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1970 enum pipe pipe)
1971 {
1972 struct drm_device *dev = dev_priv->dev;
1973 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1975 uint32_t reg, val, pipeconf_val;
1976
1977 /* PCH only available on ILK+ */
1978 BUG_ON(!HAS_PCH_SPLIT(dev));
1979
1980 /* Make sure PCH DPLL is enabled */
1981 assert_shared_dpll_enabled(dev_priv,
1982 intel_crtc_to_shared_dpll(intel_crtc));
1983
1984 /* FDI must be feeding us bits for PCH ports */
1985 assert_fdi_tx_enabled(dev_priv, pipe);
1986 assert_fdi_rx_enabled(dev_priv, pipe);
1987
1988 if (HAS_PCH_CPT(dev)) {
1989 /* Workaround: Set the timing override bit before enabling the
1990 * pch transcoder. */
1991 reg = TRANS_CHICKEN2(pipe);
1992 val = I915_READ(reg);
1993 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1994 I915_WRITE(reg, val);
1995 }
1996
1997 reg = PCH_TRANSCONF(pipe);
1998 val = I915_READ(reg);
1999 pipeconf_val = I915_READ(PIPECONF(pipe));
2000
2001 if (HAS_PCH_IBX(dev_priv->dev)) {
2002 /*
2003 * Make the BPC in transcoder be consistent with
2004 * that in pipeconf reg. For HDMI we must use 8bpc
2005 * here for both 8bpc and 12bpc.
2006 */
2007 val &= ~PIPECONF_BPC_MASK;
2008 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2009 val |= PIPECONF_8BPC;
2010 else
2011 val |= pipeconf_val & PIPECONF_BPC_MASK;
2012 }
2013
2014 val &= ~TRANS_INTERLACE_MASK;
2015 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2016 if (HAS_PCH_IBX(dev_priv->dev) &&
2017 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2018 val |= TRANS_LEGACY_INTERLACED_ILK;
2019 else
2020 val |= TRANS_INTERLACED;
2021 else
2022 val |= TRANS_PROGRESSIVE;
2023
2024 I915_WRITE(reg, val | TRANS_ENABLE);
2025 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2026 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2027 }
2028
2029 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2030 enum transcoder cpu_transcoder)
2031 {
2032 u32 val, pipeconf_val;
2033
2034 /* PCH only available on ILK+ */
2035 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2036
2037 /* FDI must be feeding us bits for PCH ports */
2038 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2039 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2040
2041 /* Workaround: set timing override bit. */
2042 val = I915_READ(_TRANSA_CHICKEN2);
2043 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2044 I915_WRITE(_TRANSA_CHICKEN2, val);
2045
2046 val = TRANS_ENABLE;
2047 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2048
2049 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2050 PIPECONF_INTERLACED_ILK)
2051 val |= TRANS_INTERLACED;
2052 else
2053 val |= TRANS_PROGRESSIVE;
2054
2055 I915_WRITE(LPT_TRANSCONF, val);
2056 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2057 DRM_ERROR("Failed to enable PCH transcoder\n");
2058 }
2059
2060 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2061 enum pipe pipe)
2062 {
2063 struct drm_device *dev = dev_priv->dev;
2064 uint32_t reg, val;
2065
2066 /* FDI relies on the transcoder */
2067 assert_fdi_tx_disabled(dev_priv, pipe);
2068 assert_fdi_rx_disabled(dev_priv, pipe);
2069
2070 /* Ports must be off as well */
2071 assert_pch_ports_disabled(dev_priv, pipe);
2072
2073 reg = PCH_TRANSCONF(pipe);
2074 val = I915_READ(reg);
2075 val &= ~TRANS_ENABLE;
2076 I915_WRITE(reg, val);
2077 /* wait for PCH transcoder off, transcoder state */
2078 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2079 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2080
2081 if (!HAS_PCH_IBX(dev)) {
2082 /* Workaround: Clear the timing override chicken bit again. */
2083 reg = TRANS_CHICKEN2(pipe);
2084 val = I915_READ(reg);
2085 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2086 I915_WRITE(reg, val);
2087 }
2088 }
2089
2090 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2091 {
2092 u32 val;
2093
2094 val = I915_READ(LPT_TRANSCONF);
2095 val &= ~TRANS_ENABLE;
2096 I915_WRITE(LPT_TRANSCONF, val);
2097 /* wait for PCH transcoder off, transcoder state */
2098 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2099 DRM_ERROR("Failed to disable PCH transcoder\n");
2100
2101 /* Workaround: clear timing override bit. */
2102 val = I915_READ(_TRANSA_CHICKEN2);
2103 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2104 I915_WRITE(_TRANSA_CHICKEN2, val);
2105 }
2106
2107 /**
2108 * intel_enable_pipe - enable a pipe, asserting requirements
2109 * @crtc: crtc responsible for the pipe
2110 *
2111 * Enable @crtc's pipe, making sure that various hardware specific requirements
2112 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2113 */
2114 static void intel_enable_pipe(struct intel_crtc *crtc)
2115 {
2116 struct drm_device *dev = crtc->base.dev;
2117 struct drm_i915_private *dev_priv = dev->dev_private;
2118 enum pipe pipe = crtc->pipe;
2119 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2120 pipe);
2121 enum pipe pch_transcoder;
2122 int reg;
2123 u32 val;
2124
2125 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2126
2127 assert_planes_disabled(dev_priv, pipe);
2128 assert_cursor_disabled(dev_priv, pipe);
2129 assert_sprites_disabled(dev_priv, pipe);
2130
2131 if (HAS_PCH_LPT(dev_priv->dev))
2132 pch_transcoder = TRANSCODER_A;
2133 else
2134 pch_transcoder = pipe;
2135
2136 /*
2137 * A pipe without a PLL won't actually be able to drive bits from
2138 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2139 * need the check.
2140 */
2141 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2142 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2143 assert_dsi_pll_enabled(dev_priv);
2144 else
2145 assert_pll_enabled(dev_priv, pipe);
2146 else {
2147 if (crtc->config->has_pch_encoder) {
2148 /* if driving the PCH, we need FDI enabled */
2149 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2150 assert_fdi_tx_pll_enabled(dev_priv,
2151 (enum pipe) cpu_transcoder);
2152 }
2153 /* FIXME: assert CPU port conditions for SNB+ */
2154 }
2155
2156 reg = PIPECONF(cpu_transcoder);
2157 val = I915_READ(reg);
2158 if (val & PIPECONF_ENABLE) {
2159 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2160 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2161 return;
2162 }
2163
2164 I915_WRITE(reg, val | PIPECONF_ENABLE);
2165 POSTING_READ(reg);
2166 }
2167
2168 /**
2169 * intel_disable_pipe - disable a pipe, asserting requirements
2170 * @crtc: crtc whose pipes is to be disabled
2171 *
2172 * Disable the pipe of @crtc, making sure that various hardware
2173 * specific requirements are met, if applicable, e.g. plane
2174 * disabled, panel fitter off, etc.
2175 *
2176 * Will wait until the pipe has shut down before returning.
2177 */
2178 static void intel_disable_pipe(struct intel_crtc *crtc)
2179 {
2180 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2181 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2182 enum pipe pipe = crtc->pipe;
2183 int reg;
2184 u32 val;
2185
2186 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2187
2188 /*
2189 * Make sure planes won't keep trying to pump pixels to us,
2190 * or we might hang the display.
2191 */
2192 assert_planes_disabled(dev_priv, pipe);
2193 assert_cursor_disabled(dev_priv, pipe);
2194 assert_sprites_disabled(dev_priv, pipe);
2195
2196 reg = PIPECONF(cpu_transcoder);
2197 val = I915_READ(reg);
2198 if ((val & PIPECONF_ENABLE) == 0)
2199 return;
2200
2201 /*
2202 * Double wide has implications for planes
2203 * so best keep it disabled when not needed.
2204 */
2205 if (crtc->config->double_wide)
2206 val &= ~PIPECONF_DOUBLE_WIDE;
2207
2208 /* Don't disable pipe or pipe PLLs if needed */
2209 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2210 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2211 val &= ~PIPECONF_ENABLE;
2212
2213 I915_WRITE(reg, val);
2214 if ((val & PIPECONF_ENABLE) == 0)
2215 intel_wait_for_pipe_off(crtc);
2216 }
2217
2218 static bool need_vtd_wa(struct drm_device *dev)
2219 {
2220 #ifdef CONFIG_INTEL_IOMMU
2221 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2222 return true;
2223 #endif
2224 return false;
2225 }
2226
2227 unsigned int
2228 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2229 uint64_t fb_format_modifier)
2230 {
2231 unsigned int tile_height;
2232 uint32_t pixel_bytes;
2233
2234 switch (fb_format_modifier) {
2235 case DRM_FORMAT_MOD_NONE:
2236 tile_height = 1;
2237 break;
2238 case I915_FORMAT_MOD_X_TILED:
2239 tile_height = IS_GEN2(dev) ? 16 : 8;
2240 break;
2241 case I915_FORMAT_MOD_Y_TILED:
2242 tile_height = 32;
2243 break;
2244 case I915_FORMAT_MOD_Yf_TILED:
2245 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2246 switch (pixel_bytes) {
2247 default:
2248 case 1:
2249 tile_height = 64;
2250 break;
2251 case 2:
2252 case 4:
2253 tile_height = 32;
2254 break;
2255 case 8:
2256 tile_height = 16;
2257 break;
2258 case 16:
2259 WARN_ONCE(1,
2260 "128-bit pixels are not supported for display!");
2261 tile_height = 16;
2262 break;
2263 }
2264 break;
2265 default:
2266 MISSING_CASE(fb_format_modifier);
2267 tile_height = 1;
2268 break;
2269 }
2270
2271 return tile_height;
2272 }
2273
2274 unsigned int
2275 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2276 uint32_t pixel_format, uint64_t fb_format_modifier)
2277 {
2278 return ALIGN(height, intel_tile_height(dev, pixel_format,
2279 fb_format_modifier));
2280 }
2281
2282 static int
2283 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2284 const struct drm_plane_state *plane_state)
2285 {
2286 struct intel_rotation_info *info = &view->rotation_info;
2287 unsigned int tile_height, tile_pitch;
2288
2289 *view = i915_ggtt_view_normal;
2290
2291 if (!plane_state)
2292 return 0;
2293
2294 if (!intel_rotation_90_or_270(plane_state->rotation))
2295 return 0;
2296
2297 *view = i915_ggtt_view_rotated;
2298
2299 info->height = fb->height;
2300 info->pixel_format = fb->pixel_format;
2301 info->pitch = fb->pitches[0];
2302 info->fb_modifier = fb->modifier[0];
2303
2304 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2305 fb->modifier[0]);
2306 tile_pitch = PAGE_SIZE / tile_height;
2307 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2308 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2309 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2310
2311 return 0;
2312 }
2313
2314 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2315 {
2316 if (INTEL_INFO(dev_priv)->gen >= 9)
2317 return 256 * 1024;
2318 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2319 IS_VALLEYVIEW(dev_priv))
2320 return 128 * 1024;
2321 else if (INTEL_INFO(dev_priv)->gen >= 4)
2322 return 4 * 1024;
2323 else
2324 return 0;
2325 }
2326
2327 int
2328 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2329 struct drm_framebuffer *fb,
2330 const struct drm_plane_state *plane_state,
2331 struct intel_engine_cs *pipelined,
2332 struct drm_i915_gem_request **pipelined_request)
2333 {
2334 struct drm_device *dev = fb->dev;
2335 struct drm_i915_private *dev_priv = dev->dev_private;
2336 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2337 struct i915_ggtt_view view;
2338 u32 alignment;
2339 int ret;
2340
2341 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2342
2343 switch (fb->modifier[0]) {
2344 case DRM_FORMAT_MOD_NONE:
2345 alignment = intel_linear_alignment(dev_priv);
2346 break;
2347 case I915_FORMAT_MOD_X_TILED:
2348 if (INTEL_INFO(dev)->gen >= 9)
2349 alignment = 256 * 1024;
2350 else {
2351 /* pin() will align the object as required by fence */
2352 alignment = 0;
2353 }
2354 break;
2355 case I915_FORMAT_MOD_Y_TILED:
2356 case I915_FORMAT_MOD_Yf_TILED:
2357 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2358 "Y tiling bo slipped through, driver bug!\n"))
2359 return -EINVAL;
2360 alignment = 1 * 1024 * 1024;
2361 break;
2362 default:
2363 MISSING_CASE(fb->modifier[0]);
2364 return -EINVAL;
2365 }
2366
2367 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2368 if (ret)
2369 return ret;
2370
2371 /* Note that the w/a also requires 64 PTE of padding following the
2372 * bo. We currently fill all unused PTE with the shadow page and so
2373 * we should always have valid PTE following the scanout preventing
2374 * the VT-d warning.
2375 */
2376 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2377 alignment = 256 * 1024;
2378
2379 /*
2380 * Global gtt pte registers are special registers which actually forward
2381 * writes to a chunk of system memory. Which means that there is no risk
2382 * that the register values disappear as soon as we call
2383 * intel_runtime_pm_put(), so it is correct to wrap only the
2384 * pin/unpin/fence and not more.
2385 */
2386 intel_runtime_pm_get(dev_priv);
2387
2388 dev_priv->mm.interruptible = false;
2389 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2390 pipelined_request, &view);
2391 if (ret)
2392 goto err_interruptible;
2393
2394 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2395 * fence, whereas 965+ only requires a fence if using
2396 * framebuffer compression. For simplicity, we always install
2397 * a fence as the cost is not that onerous.
2398 */
2399 ret = i915_gem_object_get_fence(obj);
2400 if (ret == -EDEADLK) {
2401 /*
2402 * -EDEADLK means there are no free fences
2403 * no pending flips.
2404 *
2405 * This is propagated to atomic, but it uses
2406 * -EDEADLK to force a locking recovery, so
2407 * change the returned error to -EBUSY.
2408 */
2409 ret = -EBUSY;
2410 goto err_unpin;
2411 } else if (ret)
2412 goto err_unpin;
2413
2414 i915_gem_object_pin_fence(obj);
2415
2416 dev_priv->mm.interruptible = true;
2417 intel_runtime_pm_put(dev_priv);
2418 return 0;
2419
2420 err_unpin:
2421 i915_gem_object_unpin_from_display_plane(obj, &view);
2422 err_interruptible:
2423 dev_priv->mm.interruptible = true;
2424 intel_runtime_pm_put(dev_priv);
2425 return ret;
2426 }
2427
2428 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2429 const struct drm_plane_state *plane_state)
2430 {
2431 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2432 struct i915_ggtt_view view;
2433 int ret;
2434
2435 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2436
2437 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2438 WARN_ONCE(ret, "Couldn't get view from plane state!");
2439
2440 i915_gem_object_unpin_fence(obj);
2441 i915_gem_object_unpin_from_display_plane(obj, &view);
2442 }
2443
2444 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2445 * is assumed to be a power-of-two. */
2446 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2447 int *x, int *y,
2448 unsigned int tiling_mode,
2449 unsigned int cpp,
2450 unsigned int pitch)
2451 {
2452 if (tiling_mode != I915_TILING_NONE) {
2453 unsigned int tile_rows, tiles;
2454
2455 tile_rows = *y / 8;
2456 *y %= 8;
2457
2458 tiles = *x / (512/cpp);
2459 *x %= 512/cpp;
2460
2461 return tile_rows * pitch * 8 + tiles * 4096;
2462 } else {
2463 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2464 unsigned int offset;
2465
2466 offset = *y * pitch + *x * cpp;
2467 *y = (offset & alignment) / pitch;
2468 *x = ((offset & alignment) - *y * pitch) / cpp;
2469 return offset & ~alignment;
2470 }
2471 }
2472
2473 static int i9xx_format_to_fourcc(int format)
2474 {
2475 switch (format) {
2476 case DISPPLANE_8BPP:
2477 return DRM_FORMAT_C8;
2478 case DISPPLANE_BGRX555:
2479 return DRM_FORMAT_XRGB1555;
2480 case DISPPLANE_BGRX565:
2481 return DRM_FORMAT_RGB565;
2482 default:
2483 case DISPPLANE_BGRX888:
2484 return DRM_FORMAT_XRGB8888;
2485 case DISPPLANE_RGBX888:
2486 return DRM_FORMAT_XBGR8888;
2487 case DISPPLANE_BGRX101010:
2488 return DRM_FORMAT_XRGB2101010;
2489 case DISPPLANE_RGBX101010:
2490 return DRM_FORMAT_XBGR2101010;
2491 }
2492 }
2493
2494 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2495 {
2496 switch (format) {
2497 case PLANE_CTL_FORMAT_RGB_565:
2498 return DRM_FORMAT_RGB565;
2499 default:
2500 case PLANE_CTL_FORMAT_XRGB_8888:
2501 if (rgb_order) {
2502 if (alpha)
2503 return DRM_FORMAT_ABGR8888;
2504 else
2505 return DRM_FORMAT_XBGR8888;
2506 } else {
2507 if (alpha)
2508 return DRM_FORMAT_ARGB8888;
2509 else
2510 return DRM_FORMAT_XRGB8888;
2511 }
2512 case PLANE_CTL_FORMAT_XRGB_2101010:
2513 if (rgb_order)
2514 return DRM_FORMAT_XBGR2101010;
2515 else
2516 return DRM_FORMAT_XRGB2101010;
2517 }
2518 }
2519
2520 static bool
2521 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2522 struct intel_initial_plane_config *plane_config)
2523 {
2524 struct drm_device *dev = crtc->base.dev;
2525 struct drm_i915_gem_object *obj = NULL;
2526 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2527 struct drm_framebuffer *fb = &plane_config->fb->base;
2528 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2529 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2530 PAGE_SIZE);
2531
2532 size_aligned -= base_aligned;
2533
2534 if (plane_config->size == 0)
2535 return false;
2536
2537 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2538 base_aligned,
2539 base_aligned,
2540 size_aligned);
2541 if (!obj)
2542 return false;
2543
2544 obj->tiling_mode = plane_config->tiling;
2545 if (obj->tiling_mode == I915_TILING_X)
2546 obj->stride = fb->pitches[0];
2547
2548 mode_cmd.pixel_format = fb->pixel_format;
2549 mode_cmd.width = fb->width;
2550 mode_cmd.height = fb->height;
2551 mode_cmd.pitches[0] = fb->pitches[0];
2552 mode_cmd.modifier[0] = fb->modifier[0];
2553 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2554
2555 mutex_lock(&dev->struct_mutex);
2556 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2557 &mode_cmd, obj)) {
2558 DRM_DEBUG_KMS("intel fb init failed\n");
2559 goto out_unref_obj;
2560 }
2561 mutex_unlock(&dev->struct_mutex);
2562
2563 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2564 return true;
2565
2566 out_unref_obj:
2567 drm_gem_object_unreference(&obj->base);
2568 mutex_unlock(&dev->struct_mutex);
2569 return false;
2570 }
2571
2572 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2573 static void
2574 update_state_fb(struct drm_plane *plane)
2575 {
2576 if (plane->fb == plane->state->fb)
2577 return;
2578
2579 if (plane->state->fb)
2580 drm_framebuffer_unreference(plane->state->fb);
2581 plane->state->fb = plane->fb;
2582 if (plane->state->fb)
2583 drm_framebuffer_reference(plane->state->fb);
2584 }
2585
2586 static void
2587 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2588 struct intel_initial_plane_config *plane_config)
2589 {
2590 struct drm_device *dev = intel_crtc->base.dev;
2591 struct drm_i915_private *dev_priv = dev->dev_private;
2592 struct drm_crtc *c;
2593 struct intel_crtc *i;
2594 struct drm_i915_gem_object *obj;
2595 struct drm_plane *primary = intel_crtc->base.primary;
2596 struct drm_plane_state *plane_state = primary->state;
2597 struct drm_framebuffer *fb;
2598
2599 if (!plane_config->fb)
2600 return;
2601
2602 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2603 fb = &plane_config->fb->base;
2604 goto valid_fb;
2605 }
2606
2607 kfree(plane_config->fb);
2608
2609 /*
2610 * Failed to alloc the obj, check to see if we should share
2611 * an fb with another CRTC instead
2612 */
2613 for_each_crtc(dev, c) {
2614 i = to_intel_crtc(c);
2615
2616 if (c == &intel_crtc->base)
2617 continue;
2618
2619 if (!i->active)
2620 continue;
2621
2622 fb = c->primary->fb;
2623 if (!fb)
2624 continue;
2625
2626 obj = intel_fb_obj(fb);
2627 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2628 drm_framebuffer_reference(fb);
2629 goto valid_fb;
2630 }
2631 }
2632
2633 return;
2634
2635 valid_fb:
2636 plane_state->src_x = plane_state->src_y = 0;
2637 plane_state->src_w = fb->width << 16;
2638 plane_state->src_h = fb->height << 16;
2639
2640 plane_state->crtc_x = plane_state->src_y = 0;
2641 plane_state->crtc_w = fb->width;
2642 plane_state->crtc_h = fb->height;
2643
2644 obj = intel_fb_obj(fb);
2645 if (obj->tiling_mode != I915_TILING_NONE)
2646 dev_priv->preserve_bios_swizzle = true;
2647
2648 drm_framebuffer_reference(fb);
2649 primary->fb = primary->state->fb = fb;
2650 primary->crtc = primary->state->crtc = &intel_crtc->base;
2651 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2652 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2653 }
2654
2655 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2656 struct drm_framebuffer *fb,
2657 int x, int y)
2658 {
2659 struct drm_device *dev = crtc->dev;
2660 struct drm_i915_private *dev_priv = dev->dev_private;
2661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2662 struct drm_plane *primary = crtc->primary;
2663 bool visible = to_intel_plane_state(primary->state)->visible;
2664 struct drm_i915_gem_object *obj;
2665 int plane = intel_crtc->plane;
2666 unsigned long linear_offset;
2667 u32 dspcntr;
2668 u32 reg = DSPCNTR(plane);
2669 int pixel_size;
2670
2671 if (!visible || !fb) {
2672 I915_WRITE(reg, 0);
2673 if (INTEL_INFO(dev)->gen >= 4)
2674 I915_WRITE(DSPSURF(plane), 0);
2675 else
2676 I915_WRITE(DSPADDR(plane), 0);
2677 POSTING_READ(reg);
2678 return;
2679 }
2680
2681 obj = intel_fb_obj(fb);
2682 if (WARN_ON(obj == NULL))
2683 return;
2684
2685 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2686
2687 dspcntr = DISPPLANE_GAMMA_ENABLE;
2688
2689 dspcntr |= DISPLAY_PLANE_ENABLE;
2690
2691 if (INTEL_INFO(dev)->gen < 4) {
2692 if (intel_crtc->pipe == PIPE_B)
2693 dspcntr |= DISPPLANE_SEL_PIPE_B;
2694
2695 /* pipesrc and dspsize control the size that is scaled from,
2696 * which should always be the user's requested size.
2697 */
2698 I915_WRITE(DSPSIZE(plane),
2699 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2700 (intel_crtc->config->pipe_src_w - 1));
2701 I915_WRITE(DSPPOS(plane), 0);
2702 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2703 I915_WRITE(PRIMSIZE(plane),
2704 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2705 (intel_crtc->config->pipe_src_w - 1));
2706 I915_WRITE(PRIMPOS(plane), 0);
2707 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2708 }
2709
2710 switch (fb->pixel_format) {
2711 case DRM_FORMAT_C8:
2712 dspcntr |= DISPPLANE_8BPP;
2713 break;
2714 case DRM_FORMAT_XRGB1555:
2715 dspcntr |= DISPPLANE_BGRX555;
2716 break;
2717 case DRM_FORMAT_RGB565:
2718 dspcntr |= DISPPLANE_BGRX565;
2719 break;
2720 case DRM_FORMAT_XRGB8888:
2721 dspcntr |= DISPPLANE_BGRX888;
2722 break;
2723 case DRM_FORMAT_XBGR8888:
2724 dspcntr |= DISPPLANE_RGBX888;
2725 break;
2726 case DRM_FORMAT_XRGB2101010:
2727 dspcntr |= DISPPLANE_BGRX101010;
2728 break;
2729 case DRM_FORMAT_XBGR2101010:
2730 dspcntr |= DISPPLANE_RGBX101010;
2731 break;
2732 default:
2733 BUG();
2734 }
2735
2736 if (INTEL_INFO(dev)->gen >= 4 &&
2737 obj->tiling_mode != I915_TILING_NONE)
2738 dspcntr |= DISPPLANE_TILED;
2739
2740 if (IS_G4X(dev))
2741 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2742
2743 linear_offset = y * fb->pitches[0] + x * pixel_size;
2744
2745 if (INTEL_INFO(dev)->gen >= 4) {
2746 intel_crtc->dspaddr_offset =
2747 intel_gen4_compute_page_offset(dev_priv,
2748 &x, &y, obj->tiling_mode,
2749 pixel_size,
2750 fb->pitches[0]);
2751 linear_offset -= intel_crtc->dspaddr_offset;
2752 } else {
2753 intel_crtc->dspaddr_offset = linear_offset;
2754 }
2755
2756 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2757 dspcntr |= DISPPLANE_ROTATE_180;
2758
2759 x += (intel_crtc->config->pipe_src_w - 1);
2760 y += (intel_crtc->config->pipe_src_h - 1);
2761
2762 /* Finding the last pixel of the last line of the display
2763 data and adding to linear_offset*/
2764 linear_offset +=
2765 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2766 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2767 }
2768
2769 I915_WRITE(reg, dspcntr);
2770
2771 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2772 if (INTEL_INFO(dev)->gen >= 4) {
2773 I915_WRITE(DSPSURF(plane),
2774 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2775 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2776 I915_WRITE(DSPLINOFF(plane), linear_offset);
2777 } else
2778 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2779 POSTING_READ(reg);
2780 }
2781
2782 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2783 struct drm_framebuffer *fb,
2784 int x, int y)
2785 {
2786 struct drm_device *dev = crtc->dev;
2787 struct drm_i915_private *dev_priv = dev->dev_private;
2788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2789 struct drm_plane *primary = crtc->primary;
2790 bool visible = to_intel_plane_state(primary->state)->visible;
2791 struct drm_i915_gem_object *obj;
2792 int plane = intel_crtc->plane;
2793 unsigned long linear_offset;
2794 u32 dspcntr;
2795 u32 reg = DSPCNTR(plane);
2796 int pixel_size;
2797
2798 if (!visible || !fb) {
2799 I915_WRITE(reg, 0);
2800 I915_WRITE(DSPSURF(plane), 0);
2801 POSTING_READ(reg);
2802 return;
2803 }
2804
2805 obj = intel_fb_obj(fb);
2806 if (WARN_ON(obj == NULL))
2807 return;
2808
2809 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2810
2811 dspcntr = DISPPLANE_GAMMA_ENABLE;
2812
2813 dspcntr |= DISPLAY_PLANE_ENABLE;
2814
2815 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2816 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2817
2818 switch (fb->pixel_format) {
2819 case DRM_FORMAT_C8:
2820 dspcntr |= DISPPLANE_8BPP;
2821 break;
2822 case DRM_FORMAT_RGB565:
2823 dspcntr |= DISPPLANE_BGRX565;
2824 break;
2825 case DRM_FORMAT_XRGB8888:
2826 dspcntr |= DISPPLANE_BGRX888;
2827 break;
2828 case DRM_FORMAT_XBGR8888:
2829 dspcntr |= DISPPLANE_RGBX888;
2830 break;
2831 case DRM_FORMAT_XRGB2101010:
2832 dspcntr |= DISPPLANE_BGRX101010;
2833 break;
2834 case DRM_FORMAT_XBGR2101010:
2835 dspcntr |= DISPPLANE_RGBX101010;
2836 break;
2837 default:
2838 BUG();
2839 }
2840
2841 if (obj->tiling_mode != I915_TILING_NONE)
2842 dspcntr |= DISPPLANE_TILED;
2843
2844 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2845 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2846
2847 linear_offset = y * fb->pitches[0] + x * pixel_size;
2848 intel_crtc->dspaddr_offset =
2849 intel_gen4_compute_page_offset(dev_priv,
2850 &x, &y, obj->tiling_mode,
2851 pixel_size,
2852 fb->pitches[0]);
2853 linear_offset -= intel_crtc->dspaddr_offset;
2854 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2855 dspcntr |= DISPPLANE_ROTATE_180;
2856
2857 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2858 x += (intel_crtc->config->pipe_src_w - 1);
2859 y += (intel_crtc->config->pipe_src_h - 1);
2860
2861 /* Finding the last pixel of the last line of the display
2862 data and adding to linear_offset*/
2863 linear_offset +=
2864 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2865 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2866 }
2867 }
2868
2869 I915_WRITE(reg, dspcntr);
2870
2871 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2872 I915_WRITE(DSPSURF(plane),
2873 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2874 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2875 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2876 } else {
2877 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2878 I915_WRITE(DSPLINOFF(plane), linear_offset);
2879 }
2880 POSTING_READ(reg);
2881 }
2882
2883 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2884 uint32_t pixel_format)
2885 {
2886 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2887
2888 /*
2889 * The stride is either expressed as a multiple of 64 bytes
2890 * chunks for linear buffers or in number of tiles for tiled
2891 * buffers.
2892 */
2893 switch (fb_modifier) {
2894 case DRM_FORMAT_MOD_NONE:
2895 return 64;
2896 case I915_FORMAT_MOD_X_TILED:
2897 if (INTEL_INFO(dev)->gen == 2)
2898 return 128;
2899 return 512;
2900 case I915_FORMAT_MOD_Y_TILED:
2901 /* No need to check for old gens and Y tiling since this is
2902 * about the display engine and those will be blocked before
2903 * we get here.
2904 */
2905 return 128;
2906 case I915_FORMAT_MOD_Yf_TILED:
2907 if (bits_per_pixel == 8)
2908 return 64;
2909 else
2910 return 128;
2911 default:
2912 MISSING_CASE(fb_modifier);
2913 return 64;
2914 }
2915 }
2916
2917 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2918 struct drm_i915_gem_object *obj)
2919 {
2920 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2921
2922 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2923 view = &i915_ggtt_view_rotated;
2924
2925 return i915_gem_obj_ggtt_offset_view(obj, view);
2926 }
2927
2928 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2929 {
2930 struct drm_device *dev = intel_crtc->base.dev;
2931 struct drm_i915_private *dev_priv = dev->dev_private;
2932
2933 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2934 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2935 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2936 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2937 intel_crtc->base.base.id, intel_crtc->pipe, id);
2938 }
2939
2940 /*
2941 * This function detaches (aka. unbinds) unused scalers in hardware
2942 */
2943 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2944 {
2945 struct intel_crtc_scaler_state *scaler_state;
2946 int i;
2947
2948 scaler_state = &intel_crtc->config->scaler_state;
2949
2950 /* loop through and disable scalers that aren't in use */
2951 for (i = 0; i < intel_crtc->num_scalers; i++) {
2952 if (!scaler_state->scalers[i].in_use)
2953 skl_detach_scaler(intel_crtc, i);
2954 }
2955 }
2956
2957 u32 skl_plane_ctl_format(uint32_t pixel_format)
2958 {
2959 switch (pixel_format) {
2960 case DRM_FORMAT_C8:
2961 return PLANE_CTL_FORMAT_INDEXED;
2962 case DRM_FORMAT_RGB565:
2963 return PLANE_CTL_FORMAT_RGB_565;
2964 case DRM_FORMAT_XBGR8888:
2965 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2966 case DRM_FORMAT_XRGB8888:
2967 return PLANE_CTL_FORMAT_XRGB_8888;
2968 /*
2969 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2970 * to be already pre-multiplied. We need to add a knob (or a different
2971 * DRM_FORMAT) for user-space to configure that.
2972 */
2973 case DRM_FORMAT_ABGR8888:
2974 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2975 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2976 case DRM_FORMAT_ARGB8888:
2977 return PLANE_CTL_FORMAT_XRGB_8888 |
2978 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2979 case DRM_FORMAT_XRGB2101010:
2980 return PLANE_CTL_FORMAT_XRGB_2101010;
2981 case DRM_FORMAT_XBGR2101010:
2982 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2983 case DRM_FORMAT_YUYV:
2984 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2985 case DRM_FORMAT_YVYU:
2986 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2987 case DRM_FORMAT_UYVY:
2988 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2989 case DRM_FORMAT_VYUY:
2990 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2991 default:
2992 MISSING_CASE(pixel_format);
2993 }
2994
2995 return 0;
2996 }
2997
2998 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2999 {
3000 switch (fb_modifier) {
3001 case DRM_FORMAT_MOD_NONE:
3002 break;
3003 case I915_FORMAT_MOD_X_TILED:
3004 return PLANE_CTL_TILED_X;
3005 case I915_FORMAT_MOD_Y_TILED:
3006 return PLANE_CTL_TILED_Y;
3007 case I915_FORMAT_MOD_Yf_TILED:
3008 return PLANE_CTL_TILED_YF;
3009 default:
3010 MISSING_CASE(fb_modifier);
3011 }
3012
3013 return 0;
3014 }
3015
3016 u32 skl_plane_ctl_rotation(unsigned int rotation)
3017 {
3018 switch (rotation) {
3019 case BIT(DRM_ROTATE_0):
3020 break;
3021 /*
3022 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3023 * while i915 HW rotation is clockwise, thats why this swapping.
3024 */
3025 case BIT(DRM_ROTATE_90):
3026 return PLANE_CTL_ROTATE_270;
3027 case BIT(DRM_ROTATE_180):
3028 return PLANE_CTL_ROTATE_180;
3029 case BIT(DRM_ROTATE_270):
3030 return PLANE_CTL_ROTATE_90;
3031 default:
3032 MISSING_CASE(rotation);
3033 }
3034
3035 return 0;
3036 }
3037
3038 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3039 struct drm_framebuffer *fb,
3040 int x, int y)
3041 {
3042 struct drm_device *dev = crtc->dev;
3043 struct drm_i915_private *dev_priv = dev->dev_private;
3044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3045 struct drm_plane *plane = crtc->primary;
3046 bool visible = to_intel_plane_state(plane->state)->visible;
3047 struct drm_i915_gem_object *obj;
3048 int pipe = intel_crtc->pipe;
3049 u32 plane_ctl, stride_div, stride;
3050 u32 tile_height, plane_offset, plane_size;
3051 unsigned int rotation;
3052 int x_offset, y_offset;
3053 unsigned long surf_addr;
3054 struct intel_crtc_state *crtc_state = intel_crtc->config;
3055 struct intel_plane_state *plane_state;
3056 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3057 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3058 int scaler_id = -1;
3059
3060 plane_state = to_intel_plane_state(plane->state);
3061
3062 if (!visible || !fb) {
3063 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3064 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3065 POSTING_READ(PLANE_CTL(pipe, 0));
3066 return;
3067 }
3068
3069 plane_ctl = PLANE_CTL_ENABLE |
3070 PLANE_CTL_PIPE_GAMMA_ENABLE |
3071 PLANE_CTL_PIPE_CSC_ENABLE;
3072
3073 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3074 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3075 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3076
3077 rotation = plane->state->rotation;
3078 plane_ctl |= skl_plane_ctl_rotation(rotation);
3079
3080 obj = intel_fb_obj(fb);
3081 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3082 fb->pixel_format);
3083 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3084
3085 /*
3086 * FIXME: intel_plane_state->src, dst aren't set when transitional
3087 * update_plane helpers are called from legacy paths.
3088 * Once full atomic crtc is available, below check can be avoided.
3089 */
3090 if (drm_rect_width(&plane_state->src)) {
3091 scaler_id = plane_state->scaler_id;
3092 src_x = plane_state->src.x1 >> 16;
3093 src_y = plane_state->src.y1 >> 16;
3094 src_w = drm_rect_width(&plane_state->src) >> 16;
3095 src_h = drm_rect_height(&plane_state->src) >> 16;
3096 dst_x = plane_state->dst.x1;
3097 dst_y = plane_state->dst.y1;
3098 dst_w = drm_rect_width(&plane_state->dst);
3099 dst_h = drm_rect_height(&plane_state->dst);
3100
3101 WARN_ON(x != src_x || y != src_y);
3102 } else {
3103 src_w = intel_crtc->config->pipe_src_w;
3104 src_h = intel_crtc->config->pipe_src_h;
3105 }
3106
3107 if (intel_rotation_90_or_270(rotation)) {
3108 /* stride = Surface height in tiles */
3109 tile_height = intel_tile_height(dev, fb->pixel_format,
3110 fb->modifier[0]);
3111 stride = DIV_ROUND_UP(fb->height, tile_height);
3112 x_offset = stride * tile_height - y - src_h;
3113 y_offset = x;
3114 plane_size = (src_w - 1) << 16 | (src_h - 1);
3115 } else {
3116 stride = fb->pitches[0] / stride_div;
3117 x_offset = x;
3118 y_offset = y;
3119 plane_size = (src_h - 1) << 16 | (src_w - 1);
3120 }
3121 plane_offset = y_offset << 16 | x_offset;
3122
3123 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3124 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3125 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3126 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3127
3128 if (scaler_id >= 0) {
3129 uint32_t ps_ctrl = 0;
3130
3131 WARN_ON(!dst_w || !dst_h);
3132 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3133 crtc_state->scaler_state.scalers[scaler_id].mode;
3134 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3135 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3136 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3137 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3138 I915_WRITE(PLANE_POS(pipe, 0), 0);
3139 } else {
3140 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3141 }
3142
3143 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3144
3145 POSTING_READ(PLANE_SURF(pipe, 0));
3146 }
3147
3148 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3149 static int
3150 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3151 int x, int y, enum mode_set_atomic state)
3152 {
3153 struct drm_device *dev = crtc->dev;
3154 struct drm_i915_private *dev_priv = dev->dev_private;
3155
3156 if (dev_priv->fbc.disable_fbc)
3157 dev_priv->fbc.disable_fbc(dev_priv);
3158
3159 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3160
3161 return 0;
3162 }
3163
3164 static void intel_complete_page_flips(struct drm_device *dev)
3165 {
3166 struct drm_crtc *crtc;
3167
3168 for_each_crtc(dev, crtc) {
3169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3170 enum plane plane = intel_crtc->plane;
3171
3172 intel_prepare_page_flip(dev, plane);
3173 intel_finish_page_flip_plane(dev, plane);
3174 }
3175 }
3176
3177 static void intel_update_primary_planes(struct drm_device *dev)
3178 {
3179 struct drm_i915_private *dev_priv = dev->dev_private;
3180 struct drm_crtc *crtc;
3181
3182 for_each_crtc(dev, crtc) {
3183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3184
3185 drm_modeset_lock(&crtc->mutex, NULL);
3186 /*
3187 * FIXME: Once we have proper support for primary planes (and
3188 * disabling them without disabling the entire crtc) allow again
3189 * a NULL crtc->primary->fb.
3190 */
3191 if (intel_crtc->active && crtc->primary->fb)
3192 dev_priv->display.update_primary_plane(crtc,
3193 crtc->primary->fb,
3194 crtc->x,
3195 crtc->y);
3196 drm_modeset_unlock(&crtc->mutex);
3197 }
3198 }
3199
3200 void intel_prepare_reset(struct drm_device *dev)
3201 {
3202 /* no reset support for gen2 */
3203 if (IS_GEN2(dev))
3204 return;
3205
3206 /* reset doesn't touch the display */
3207 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3208 return;
3209
3210 drm_modeset_lock_all(dev);
3211 /*
3212 * Disabling the crtcs gracefully seems nicer. Also the
3213 * g33 docs say we should at least disable all the planes.
3214 */
3215 intel_display_suspend(dev);
3216 }
3217
3218 void intel_finish_reset(struct drm_device *dev)
3219 {
3220 struct drm_i915_private *dev_priv = to_i915(dev);
3221
3222 /*
3223 * Flips in the rings will be nuked by the reset,
3224 * so complete all pending flips so that user space
3225 * will get its events and not get stuck.
3226 */
3227 intel_complete_page_flips(dev);
3228
3229 /* no reset support for gen2 */
3230 if (IS_GEN2(dev))
3231 return;
3232
3233 /* reset doesn't touch the display */
3234 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3235 /*
3236 * Flips in the rings have been nuked by the reset,
3237 * so update the base address of all primary
3238 * planes to the the last fb to make sure we're
3239 * showing the correct fb after a reset.
3240 */
3241 intel_update_primary_planes(dev);
3242 return;
3243 }
3244
3245 /*
3246 * The display has been reset as well,
3247 * so need a full re-initialization.
3248 */
3249 intel_runtime_pm_disable_interrupts(dev_priv);
3250 intel_runtime_pm_enable_interrupts(dev_priv);
3251
3252 intel_modeset_init_hw(dev);
3253
3254 spin_lock_irq(&dev_priv->irq_lock);
3255 if (dev_priv->display.hpd_irq_setup)
3256 dev_priv->display.hpd_irq_setup(dev);
3257 spin_unlock_irq(&dev_priv->irq_lock);
3258
3259 intel_display_resume(dev);
3260
3261 intel_hpd_init(dev_priv);
3262
3263 drm_modeset_unlock_all(dev);
3264 }
3265
3266 static void
3267 intel_finish_fb(struct drm_framebuffer *old_fb)
3268 {
3269 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3270 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3271 bool was_interruptible = dev_priv->mm.interruptible;
3272 int ret;
3273
3274 /* Big Hammer, we also need to ensure that any pending
3275 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3276 * current scanout is retired before unpinning the old
3277 * framebuffer. Note that we rely on userspace rendering
3278 * into the buffer attached to the pipe they are waiting
3279 * on. If not, userspace generates a GPU hang with IPEHR
3280 * point to the MI_WAIT_FOR_EVENT.
3281 *
3282 * This should only fail upon a hung GPU, in which case we
3283 * can safely continue.
3284 */
3285 dev_priv->mm.interruptible = false;
3286 ret = i915_gem_object_wait_rendering(obj, true);
3287 dev_priv->mm.interruptible = was_interruptible;
3288
3289 WARN_ON(ret);
3290 }
3291
3292 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3293 {
3294 struct drm_device *dev = crtc->dev;
3295 struct drm_i915_private *dev_priv = dev->dev_private;
3296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3297 bool pending;
3298
3299 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3300 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3301 return false;
3302
3303 spin_lock_irq(&dev->event_lock);
3304 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3305 spin_unlock_irq(&dev->event_lock);
3306
3307 return pending;
3308 }
3309
3310 static void intel_update_pipe_size(struct intel_crtc *crtc)
3311 {
3312 struct drm_device *dev = crtc->base.dev;
3313 struct drm_i915_private *dev_priv = dev->dev_private;
3314 const struct drm_display_mode *adjusted_mode;
3315
3316 if (!i915.fastboot)
3317 return;
3318
3319 /*
3320 * Update pipe size and adjust fitter if needed: the reason for this is
3321 * that in compute_mode_changes we check the native mode (not the pfit
3322 * mode) to see if we can flip rather than do a full mode set. In the
3323 * fastboot case, we'll flip, but if we don't update the pipesrc and
3324 * pfit state, we'll end up with a big fb scanned out into the wrong
3325 * sized surface.
3326 *
3327 * To fix this properly, we need to hoist the checks up into
3328 * compute_mode_changes (or above), check the actual pfit state and
3329 * whether the platform allows pfit disable with pipe active, and only
3330 * then update the pipesrc and pfit state, even on the flip path.
3331 */
3332
3333 adjusted_mode = &crtc->config->base.adjusted_mode;
3334
3335 I915_WRITE(PIPESRC(crtc->pipe),
3336 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3337 (adjusted_mode->crtc_vdisplay - 1));
3338 if (!crtc->config->pch_pfit.enabled &&
3339 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3340 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3341 I915_WRITE(PF_CTL(crtc->pipe), 0);
3342 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3343 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3344 }
3345 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3346 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3347 }
3348
3349 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3350 {
3351 struct drm_device *dev = crtc->dev;
3352 struct drm_i915_private *dev_priv = dev->dev_private;
3353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3354 int pipe = intel_crtc->pipe;
3355 u32 reg, temp;
3356
3357 /* enable normal train */
3358 reg = FDI_TX_CTL(pipe);
3359 temp = I915_READ(reg);
3360 if (IS_IVYBRIDGE(dev)) {
3361 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3362 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3363 } else {
3364 temp &= ~FDI_LINK_TRAIN_NONE;
3365 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3366 }
3367 I915_WRITE(reg, temp);
3368
3369 reg = FDI_RX_CTL(pipe);
3370 temp = I915_READ(reg);
3371 if (HAS_PCH_CPT(dev)) {
3372 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3373 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3374 } else {
3375 temp &= ~FDI_LINK_TRAIN_NONE;
3376 temp |= FDI_LINK_TRAIN_NONE;
3377 }
3378 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3379
3380 /* wait one idle pattern time */
3381 POSTING_READ(reg);
3382 udelay(1000);
3383
3384 /* IVB wants error correction enabled */
3385 if (IS_IVYBRIDGE(dev))
3386 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3387 FDI_FE_ERRC_ENABLE);
3388 }
3389
3390 /* The FDI link training functions for ILK/Ibexpeak. */
3391 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3392 {
3393 struct drm_device *dev = crtc->dev;
3394 struct drm_i915_private *dev_priv = dev->dev_private;
3395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3396 int pipe = intel_crtc->pipe;
3397 u32 reg, temp, tries;
3398
3399 /* FDI needs bits from pipe first */
3400 assert_pipe_enabled(dev_priv, pipe);
3401
3402 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3403 for train result */
3404 reg = FDI_RX_IMR(pipe);
3405 temp = I915_READ(reg);
3406 temp &= ~FDI_RX_SYMBOL_LOCK;
3407 temp &= ~FDI_RX_BIT_LOCK;
3408 I915_WRITE(reg, temp);
3409 I915_READ(reg);
3410 udelay(150);
3411
3412 /* enable CPU FDI TX and PCH FDI RX */
3413 reg = FDI_TX_CTL(pipe);
3414 temp = I915_READ(reg);
3415 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3416 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3417 temp &= ~FDI_LINK_TRAIN_NONE;
3418 temp |= FDI_LINK_TRAIN_PATTERN_1;
3419 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3420
3421 reg = FDI_RX_CTL(pipe);
3422 temp = I915_READ(reg);
3423 temp &= ~FDI_LINK_TRAIN_NONE;
3424 temp |= FDI_LINK_TRAIN_PATTERN_1;
3425 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3426
3427 POSTING_READ(reg);
3428 udelay(150);
3429
3430 /* Ironlake workaround, enable clock pointer after FDI enable*/
3431 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3432 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3433 FDI_RX_PHASE_SYNC_POINTER_EN);
3434
3435 reg = FDI_RX_IIR(pipe);
3436 for (tries = 0; tries < 5; tries++) {
3437 temp = I915_READ(reg);
3438 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3439
3440 if ((temp & FDI_RX_BIT_LOCK)) {
3441 DRM_DEBUG_KMS("FDI train 1 done.\n");
3442 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3443 break;
3444 }
3445 }
3446 if (tries == 5)
3447 DRM_ERROR("FDI train 1 fail!\n");
3448
3449 /* Train 2 */
3450 reg = FDI_TX_CTL(pipe);
3451 temp = I915_READ(reg);
3452 temp &= ~FDI_LINK_TRAIN_NONE;
3453 temp |= FDI_LINK_TRAIN_PATTERN_2;
3454 I915_WRITE(reg, temp);
3455
3456 reg = FDI_RX_CTL(pipe);
3457 temp = I915_READ(reg);
3458 temp &= ~FDI_LINK_TRAIN_NONE;
3459 temp |= FDI_LINK_TRAIN_PATTERN_2;
3460 I915_WRITE(reg, temp);
3461
3462 POSTING_READ(reg);
3463 udelay(150);
3464
3465 reg = FDI_RX_IIR(pipe);
3466 for (tries = 0; tries < 5; tries++) {
3467 temp = I915_READ(reg);
3468 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3469
3470 if (temp & FDI_RX_SYMBOL_LOCK) {
3471 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3472 DRM_DEBUG_KMS("FDI train 2 done.\n");
3473 break;
3474 }
3475 }
3476 if (tries == 5)
3477 DRM_ERROR("FDI train 2 fail!\n");
3478
3479 DRM_DEBUG_KMS("FDI train done\n");
3480
3481 }
3482
3483 static const int snb_b_fdi_train_param[] = {
3484 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3485 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3486 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3487 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3488 };
3489
3490 /* The FDI link training functions for SNB/Cougarpoint. */
3491 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3492 {
3493 struct drm_device *dev = crtc->dev;
3494 struct drm_i915_private *dev_priv = dev->dev_private;
3495 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3496 int pipe = intel_crtc->pipe;
3497 u32 reg, temp, i, retry;
3498
3499 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3500 for train result */
3501 reg = FDI_RX_IMR(pipe);
3502 temp = I915_READ(reg);
3503 temp &= ~FDI_RX_SYMBOL_LOCK;
3504 temp &= ~FDI_RX_BIT_LOCK;
3505 I915_WRITE(reg, temp);
3506
3507 POSTING_READ(reg);
3508 udelay(150);
3509
3510 /* enable CPU FDI TX and PCH FDI RX */
3511 reg = FDI_TX_CTL(pipe);
3512 temp = I915_READ(reg);
3513 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3514 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3515 temp &= ~FDI_LINK_TRAIN_NONE;
3516 temp |= FDI_LINK_TRAIN_PATTERN_1;
3517 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3518 /* SNB-B */
3519 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3520 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3521
3522 I915_WRITE(FDI_RX_MISC(pipe),
3523 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3524
3525 reg = FDI_RX_CTL(pipe);
3526 temp = I915_READ(reg);
3527 if (HAS_PCH_CPT(dev)) {
3528 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3529 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3530 } else {
3531 temp &= ~FDI_LINK_TRAIN_NONE;
3532 temp |= FDI_LINK_TRAIN_PATTERN_1;
3533 }
3534 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3535
3536 POSTING_READ(reg);
3537 udelay(150);
3538
3539 for (i = 0; i < 4; i++) {
3540 reg = FDI_TX_CTL(pipe);
3541 temp = I915_READ(reg);
3542 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3543 temp |= snb_b_fdi_train_param[i];
3544 I915_WRITE(reg, temp);
3545
3546 POSTING_READ(reg);
3547 udelay(500);
3548
3549 for (retry = 0; retry < 5; retry++) {
3550 reg = FDI_RX_IIR(pipe);
3551 temp = I915_READ(reg);
3552 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3553 if (temp & FDI_RX_BIT_LOCK) {
3554 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3555 DRM_DEBUG_KMS("FDI train 1 done.\n");
3556 break;
3557 }
3558 udelay(50);
3559 }
3560 if (retry < 5)
3561 break;
3562 }
3563 if (i == 4)
3564 DRM_ERROR("FDI train 1 fail!\n");
3565
3566 /* Train 2 */
3567 reg = FDI_TX_CTL(pipe);
3568 temp = I915_READ(reg);
3569 temp &= ~FDI_LINK_TRAIN_NONE;
3570 temp |= FDI_LINK_TRAIN_PATTERN_2;
3571 if (IS_GEN6(dev)) {
3572 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3573 /* SNB-B */
3574 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3575 }
3576 I915_WRITE(reg, temp);
3577
3578 reg = FDI_RX_CTL(pipe);
3579 temp = I915_READ(reg);
3580 if (HAS_PCH_CPT(dev)) {
3581 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3582 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3583 } else {
3584 temp &= ~FDI_LINK_TRAIN_NONE;
3585 temp |= FDI_LINK_TRAIN_PATTERN_2;
3586 }
3587 I915_WRITE(reg, temp);
3588
3589 POSTING_READ(reg);
3590 udelay(150);
3591
3592 for (i = 0; i < 4; i++) {
3593 reg = FDI_TX_CTL(pipe);
3594 temp = I915_READ(reg);
3595 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3596 temp |= snb_b_fdi_train_param[i];
3597 I915_WRITE(reg, temp);
3598
3599 POSTING_READ(reg);
3600 udelay(500);
3601
3602 for (retry = 0; retry < 5; retry++) {
3603 reg = FDI_RX_IIR(pipe);
3604 temp = I915_READ(reg);
3605 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3606 if (temp & FDI_RX_SYMBOL_LOCK) {
3607 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3608 DRM_DEBUG_KMS("FDI train 2 done.\n");
3609 break;
3610 }
3611 udelay(50);
3612 }
3613 if (retry < 5)
3614 break;
3615 }
3616 if (i == 4)
3617 DRM_ERROR("FDI train 2 fail!\n");
3618
3619 DRM_DEBUG_KMS("FDI train done.\n");
3620 }
3621
3622 /* Manual link training for Ivy Bridge A0 parts */
3623 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3624 {
3625 struct drm_device *dev = crtc->dev;
3626 struct drm_i915_private *dev_priv = dev->dev_private;
3627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3628 int pipe = intel_crtc->pipe;
3629 u32 reg, temp, i, j;
3630
3631 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3632 for train result */
3633 reg = FDI_RX_IMR(pipe);
3634 temp = I915_READ(reg);
3635 temp &= ~FDI_RX_SYMBOL_LOCK;
3636 temp &= ~FDI_RX_BIT_LOCK;
3637 I915_WRITE(reg, temp);
3638
3639 POSTING_READ(reg);
3640 udelay(150);
3641
3642 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3643 I915_READ(FDI_RX_IIR(pipe)));
3644
3645 /* Try each vswing and preemphasis setting twice before moving on */
3646 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3647 /* disable first in case we need to retry */
3648 reg = FDI_TX_CTL(pipe);
3649 temp = I915_READ(reg);
3650 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3651 temp &= ~FDI_TX_ENABLE;
3652 I915_WRITE(reg, temp);
3653
3654 reg = FDI_RX_CTL(pipe);
3655 temp = I915_READ(reg);
3656 temp &= ~FDI_LINK_TRAIN_AUTO;
3657 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3658 temp &= ~FDI_RX_ENABLE;
3659 I915_WRITE(reg, temp);
3660
3661 /* enable CPU FDI TX and PCH FDI RX */
3662 reg = FDI_TX_CTL(pipe);
3663 temp = I915_READ(reg);
3664 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3665 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3666 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3667 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3668 temp |= snb_b_fdi_train_param[j/2];
3669 temp |= FDI_COMPOSITE_SYNC;
3670 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3671
3672 I915_WRITE(FDI_RX_MISC(pipe),
3673 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3674
3675 reg = FDI_RX_CTL(pipe);
3676 temp = I915_READ(reg);
3677 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3678 temp |= FDI_COMPOSITE_SYNC;
3679 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3680
3681 POSTING_READ(reg);
3682 udelay(1); /* should be 0.5us */
3683
3684 for (i = 0; i < 4; i++) {
3685 reg = FDI_RX_IIR(pipe);
3686 temp = I915_READ(reg);
3687 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3688
3689 if (temp & FDI_RX_BIT_LOCK ||
3690 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3691 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3692 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3693 i);
3694 break;
3695 }
3696 udelay(1); /* should be 0.5us */
3697 }
3698 if (i == 4) {
3699 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3700 continue;
3701 }
3702
3703 /* Train 2 */
3704 reg = FDI_TX_CTL(pipe);
3705 temp = I915_READ(reg);
3706 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3707 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3708 I915_WRITE(reg, temp);
3709
3710 reg = FDI_RX_CTL(pipe);
3711 temp = I915_READ(reg);
3712 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3713 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3714 I915_WRITE(reg, temp);
3715
3716 POSTING_READ(reg);
3717 udelay(2); /* should be 1.5us */
3718
3719 for (i = 0; i < 4; i++) {
3720 reg = FDI_RX_IIR(pipe);
3721 temp = I915_READ(reg);
3722 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3723
3724 if (temp & FDI_RX_SYMBOL_LOCK ||
3725 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3726 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3727 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3728 i);
3729 goto train_done;
3730 }
3731 udelay(2); /* should be 1.5us */
3732 }
3733 if (i == 4)
3734 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3735 }
3736
3737 train_done:
3738 DRM_DEBUG_KMS("FDI train done.\n");
3739 }
3740
3741 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3742 {
3743 struct drm_device *dev = intel_crtc->base.dev;
3744 struct drm_i915_private *dev_priv = dev->dev_private;
3745 int pipe = intel_crtc->pipe;
3746 u32 reg, temp;
3747
3748
3749 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3750 reg = FDI_RX_CTL(pipe);
3751 temp = I915_READ(reg);
3752 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3753 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3754 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3755 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3756
3757 POSTING_READ(reg);
3758 udelay(200);
3759
3760 /* Switch from Rawclk to PCDclk */
3761 temp = I915_READ(reg);
3762 I915_WRITE(reg, temp | FDI_PCDCLK);
3763
3764 POSTING_READ(reg);
3765 udelay(200);
3766
3767 /* Enable CPU FDI TX PLL, always on for Ironlake */
3768 reg = FDI_TX_CTL(pipe);
3769 temp = I915_READ(reg);
3770 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3771 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3772
3773 POSTING_READ(reg);
3774 udelay(100);
3775 }
3776 }
3777
3778 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3779 {
3780 struct drm_device *dev = intel_crtc->base.dev;
3781 struct drm_i915_private *dev_priv = dev->dev_private;
3782 int pipe = intel_crtc->pipe;
3783 u32 reg, temp;
3784
3785 /* Switch from PCDclk to Rawclk */
3786 reg = FDI_RX_CTL(pipe);
3787 temp = I915_READ(reg);
3788 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3789
3790 /* Disable CPU FDI TX PLL */
3791 reg = FDI_TX_CTL(pipe);
3792 temp = I915_READ(reg);
3793 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3794
3795 POSTING_READ(reg);
3796 udelay(100);
3797
3798 reg = FDI_RX_CTL(pipe);
3799 temp = I915_READ(reg);
3800 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3801
3802 /* Wait for the clocks to turn off. */
3803 POSTING_READ(reg);
3804 udelay(100);
3805 }
3806
3807 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3808 {
3809 struct drm_device *dev = crtc->dev;
3810 struct drm_i915_private *dev_priv = dev->dev_private;
3811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3812 int pipe = intel_crtc->pipe;
3813 u32 reg, temp;
3814
3815 /* disable CPU FDI tx and PCH FDI rx */
3816 reg = FDI_TX_CTL(pipe);
3817 temp = I915_READ(reg);
3818 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3819 POSTING_READ(reg);
3820
3821 reg = FDI_RX_CTL(pipe);
3822 temp = I915_READ(reg);
3823 temp &= ~(0x7 << 16);
3824 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3825 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3826
3827 POSTING_READ(reg);
3828 udelay(100);
3829
3830 /* Ironlake workaround, disable clock pointer after downing FDI */
3831 if (HAS_PCH_IBX(dev))
3832 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3833
3834 /* still set train pattern 1 */
3835 reg = FDI_TX_CTL(pipe);
3836 temp = I915_READ(reg);
3837 temp &= ~FDI_LINK_TRAIN_NONE;
3838 temp |= FDI_LINK_TRAIN_PATTERN_1;
3839 I915_WRITE(reg, temp);
3840
3841 reg = FDI_RX_CTL(pipe);
3842 temp = I915_READ(reg);
3843 if (HAS_PCH_CPT(dev)) {
3844 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3845 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3846 } else {
3847 temp &= ~FDI_LINK_TRAIN_NONE;
3848 temp |= FDI_LINK_TRAIN_PATTERN_1;
3849 }
3850 /* BPC in FDI rx is consistent with that in PIPECONF */
3851 temp &= ~(0x07 << 16);
3852 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3853 I915_WRITE(reg, temp);
3854
3855 POSTING_READ(reg);
3856 udelay(100);
3857 }
3858
3859 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3860 {
3861 struct intel_crtc *crtc;
3862
3863 /* Note that we don't need to be called with mode_config.lock here
3864 * as our list of CRTC objects is static for the lifetime of the
3865 * device and so cannot disappear as we iterate. Similarly, we can
3866 * happily treat the predicates as racy, atomic checks as userspace
3867 * cannot claim and pin a new fb without at least acquring the
3868 * struct_mutex and so serialising with us.
3869 */
3870 for_each_intel_crtc(dev, crtc) {
3871 if (atomic_read(&crtc->unpin_work_count) == 0)
3872 continue;
3873
3874 if (crtc->unpin_work)
3875 intel_wait_for_vblank(dev, crtc->pipe);
3876
3877 return true;
3878 }
3879
3880 return false;
3881 }
3882
3883 static void page_flip_completed(struct intel_crtc *intel_crtc)
3884 {
3885 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3886 struct intel_unpin_work *work = intel_crtc->unpin_work;
3887
3888 /* ensure that the unpin work is consistent wrt ->pending. */
3889 smp_rmb();
3890 intel_crtc->unpin_work = NULL;
3891
3892 if (work->event)
3893 drm_send_vblank_event(intel_crtc->base.dev,
3894 intel_crtc->pipe,
3895 work->event);
3896
3897 drm_crtc_vblank_put(&intel_crtc->base);
3898
3899 wake_up_all(&dev_priv->pending_flip_queue);
3900 queue_work(dev_priv->wq, &work->work);
3901
3902 trace_i915_flip_complete(intel_crtc->plane,
3903 work->pending_flip_obj);
3904 }
3905
3906 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3907 {
3908 struct drm_device *dev = crtc->dev;
3909 struct drm_i915_private *dev_priv = dev->dev_private;
3910
3911 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3912 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3913 !intel_crtc_has_pending_flip(crtc),
3914 60*HZ) == 0)) {
3915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3916
3917 spin_lock_irq(&dev->event_lock);
3918 if (intel_crtc->unpin_work) {
3919 WARN_ONCE(1, "Removing stuck page flip\n");
3920 page_flip_completed(intel_crtc);
3921 }
3922 spin_unlock_irq(&dev->event_lock);
3923 }
3924
3925 if (crtc->primary->fb) {
3926 mutex_lock(&dev->struct_mutex);
3927 intel_finish_fb(crtc->primary->fb);
3928 mutex_unlock(&dev->struct_mutex);
3929 }
3930 }
3931
3932 /* Program iCLKIP clock to the desired frequency */
3933 static void lpt_program_iclkip(struct drm_crtc *crtc)
3934 {
3935 struct drm_device *dev = crtc->dev;
3936 struct drm_i915_private *dev_priv = dev->dev_private;
3937 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3938 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3939 u32 temp;
3940
3941 mutex_lock(&dev_priv->sb_lock);
3942
3943 /* It is necessary to ungate the pixclk gate prior to programming
3944 * the divisors, and gate it back when it is done.
3945 */
3946 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3947
3948 /* Disable SSCCTL */
3949 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3950 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3951 SBI_SSCCTL_DISABLE,
3952 SBI_ICLK);
3953
3954 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3955 if (clock == 20000) {
3956 auxdiv = 1;
3957 divsel = 0x41;
3958 phaseinc = 0x20;
3959 } else {
3960 /* The iCLK virtual clock root frequency is in MHz,
3961 * but the adjusted_mode->crtc_clock in in KHz. To get the
3962 * divisors, it is necessary to divide one by another, so we
3963 * convert the virtual clock precision to KHz here for higher
3964 * precision.
3965 */
3966 u32 iclk_virtual_root_freq = 172800 * 1000;
3967 u32 iclk_pi_range = 64;
3968 u32 desired_divisor, msb_divisor_value, pi_value;
3969
3970 desired_divisor = (iclk_virtual_root_freq / clock);
3971 msb_divisor_value = desired_divisor / iclk_pi_range;
3972 pi_value = desired_divisor % iclk_pi_range;
3973
3974 auxdiv = 0;
3975 divsel = msb_divisor_value - 2;
3976 phaseinc = pi_value;
3977 }
3978
3979 /* This should not happen with any sane values */
3980 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3981 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3982 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3983 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3984
3985 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3986 clock,
3987 auxdiv,
3988 divsel,
3989 phasedir,
3990 phaseinc);
3991
3992 /* Program SSCDIVINTPHASE6 */
3993 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3994 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3995 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3996 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3997 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3998 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3999 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4000 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4001
4002 /* Program SSCAUXDIV */
4003 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4004 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4005 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4006 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4007
4008 /* Enable modulator and associated divider */
4009 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4010 temp &= ~SBI_SSCCTL_DISABLE;
4011 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4012
4013 /* Wait for initialization time */
4014 udelay(24);
4015
4016 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4017
4018 mutex_unlock(&dev_priv->sb_lock);
4019 }
4020
4021 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4022 enum pipe pch_transcoder)
4023 {
4024 struct drm_device *dev = crtc->base.dev;
4025 struct drm_i915_private *dev_priv = dev->dev_private;
4026 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4027
4028 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4029 I915_READ(HTOTAL(cpu_transcoder)));
4030 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4031 I915_READ(HBLANK(cpu_transcoder)));
4032 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4033 I915_READ(HSYNC(cpu_transcoder)));
4034
4035 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4036 I915_READ(VTOTAL(cpu_transcoder)));
4037 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4038 I915_READ(VBLANK(cpu_transcoder)));
4039 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4040 I915_READ(VSYNC(cpu_transcoder)));
4041 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4042 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4043 }
4044
4045 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4046 {
4047 struct drm_i915_private *dev_priv = dev->dev_private;
4048 uint32_t temp;
4049
4050 temp = I915_READ(SOUTH_CHICKEN1);
4051 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4052 return;
4053
4054 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4055 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4056
4057 temp &= ~FDI_BC_BIFURCATION_SELECT;
4058 if (enable)
4059 temp |= FDI_BC_BIFURCATION_SELECT;
4060
4061 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4062 I915_WRITE(SOUTH_CHICKEN1, temp);
4063 POSTING_READ(SOUTH_CHICKEN1);
4064 }
4065
4066 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4067 {
4068 struct drm_device *dev = intel_crtc->base.dev;
4069
4070 switch (intel_crtc->pipe) {
4071 case PIPE_A:
4072 break;
4073 case PIPE_B:
4074 if (intel_crtc->config->fdi_lanes > 2)
4075 cpt_set_fdi_bc_bifurcation(dev, false);
4076 else
4077 cpt_set_fdi_bc_bifurcation(dev, true);
4078
4079 break;
4080 case PIPE_C:
4081 cpt_set_fdi_bc_bifurcation(dev, true);
4082
4083 break;
4084 default:
4085 BUG();
4086 }
4087 }
4088
4089 /*
4090 * Enable PCH resources required for PCH ports:
4091 * - PCH PLLs
4092 * - FDI training & RX/TX
4093 * - update transcoder timings
4094 * - DP transcoding bits
4095 * - transcoder
4096 */
4097 static void ironlake_pch_enable(struct drm_crtc *crtc)
4098 {
4099 struct drm_device *dev = crtc->dev;
4100 struct drm_i915_private *dev_priv = dev->dev_private;
4101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4102 int pipe = intel_crtc->pipe;
4103 u32 reg, temp;
4104
4105 assert_pch_transcoder_disabled(dev_priv, pipe);
4106
4107 if (IS_IVYBRIDGE(dev))
4108 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4109
4110 /* Write the TU size bits before fdi link training, so that error
4111 * detection works. */
4112 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4113 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4114
4115 /* For PCH output, training FDI link */
4116 dev_priv->display.fdi_link_train(crtc);
4117
4118 /* We need to program the right clock selection before writing the pixel
4119 * mutliplier into the DPLL. */
4120 if (HAS_PCH_CPT(dev)) {
4121 u32 sel;
4122
4123 temp = I915_READ(PCH_DPLL_SEL);
4124 temp |= TRANS_DPLL_ENABLE(pipe);
4125 sel = TRANS_DPLLB_SEL(pipe);
4126 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4127 temp |= sel;
4128 else
4129 temp &= ~sel;
4130 I915_WRITE(PCH_DPLL_SEL, temp);
4131 }
4132
4133 /* XXX: pch pll's can be enabled any time before we enable the PCH
4134 * transcoder, and we actually should do this to not upset any PCH
4135 * transcoder that already use the clock when we share it.
4136 *
4137 * Note that enable_shared_dpll tries to do the right thing, but
4138 * get_shared_dpll unconditionally resets the pll - we need that to have
4139 * the right LVDS enable sequence. */
4140 intel_enable_shared_dpll(intel_crtc);
4141
4142 /* set transcoder timing, panel must allow it */
4143 assert_panel_unlocked(dev_priv, pipe);
4144 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4145
4146 intel_fdi_normal_train(crtc);
4147
4148 /* For PCH DP, enable TRANS_DP_CTL */
4149 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4150 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4151 reg = TRANS_DP_CTL(pipe);
4152 temp = I915_READ(reg);
4153 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4154 TRANS_DP_SYNC_MASK |
4155 TRANS_DP_BPC_MASK);
4156 temp |= TRANS_DP_OUTPUT_ENABLE;
4157 temp |= bpc << 9; /* same format but at 11:9 */
4158
4159 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4160 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4161 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4162 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4163
4164 switch (intel_trans_dp_port_sel(crtc)) {
4165 case PCH_DP_B:
4166 temp |= TRANS_DP_PORT_SEL_B;
4167 break;
4168 case PCH_DP_C:
4169 temp |= TRANS_DP_PORT_SEL_C;
4170 break;
4171 case PCH_DP_D:
4172 temp |= TRANS_DP_PORT_SEL_D;
4173 break;
4174 default:
4175 BUG();
4176 }
4177
4178 I915_WRITE(reg, temp);
4179 }
4180
4181 ironlake_enable_pch_transcoder(dev_priv, pipe);
4182 }
4183
4184 static void lpt_pch_enable(struct drm_crtc *crtc)
4185 {
4186 struct drm_device *dev = crtc->dev;
4187 struct drm_i915_private *dev_priv = dev->dev_private;
4188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4189 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4190
4191 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4192
4193 lpt_program_iclkip(crtc);
4194
4195 /* Set transcoder timing. */
4196 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4197
4198 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4199 }
4200
4201 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4202 struct intel_crtc_state *crtc_state)
4203 {
4204 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4205 struct intel_shared_dpll *pll;
4206 struct intel_shared_dpll_config *shared_dpll;
4207 enum intel_dpll_id i;
4208
4209 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4210
4211 if (HAS_PCH_IBX(dev_priv->dev)) {
4212 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4213 i = (enum intel_dpll_id) crtc->pipe;
4214 pll = &dev_priv->shared_dplls[i];
4215
4216 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4217 crtc->base.base.id, pll->name);
4218
4219 WARN_ON(shared_dpll[i].crtc_mask);
4220
4221 goto found;
4222 }
4223
4224 if (IS_BROXTON(dev_priv->dev)) {
4225 /* PLL is attached to port in bxt */
4226 struct intel_encoder *encoder;
4227 struct intel_digital_port *intel_dig_port;
4228
4229 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4230 if (WARN_ON(!encoder))
4231 return NULL;
4232
4233 intel_dig_port = enc_to_dig_port(&encoder->base);
4234 /* 1:1 mapping between ports and PLLs */
4235 i = (enum intel_dpll_id)intel_dig_port->port;
4236 pll = &dev_priv->shared_dplls[i];
4237 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4238 crtc->base.base.id, pll->name);
4239 WARN_ON(shared_dpll[i].crtc_mask);
4240
4241 goto found;
4242 }
4243
4244 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4245 pll = &dev_priv->shared_dplls[i];
4246
4247 /* Only want to check enabled timings first */
4248 if (shared_dpll[i].crtc_mask == 0)
4249 continue;
4250
4251 if (memcmp(&crtc_state->dpll_hw_state,
4252 &shared_dpll[i].hw_state,
4253 sizeof(crtc_state->dpll_hw_state)) == 0) {
4254 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4255 crtc->base.base.id, pll->name,
4256 shared_dpll[i].crtc_mask,
4257 pll->active);
4258 goto found;
4259 }
4260 }
4261
4262 /* Ok no matching timings, maybe there's a free one? */
4263 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4264 pll = &dev_priv->shared_dplls[i];
4265 if (shared_dpll[i].crtc_mask == 0) {
4266 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4267 crtc->base.base.id, pll->name);
4268 goto found;
4269 }
4270 }
4271
4272 return NULL;
4273
4274 found:
4275 if (shared_dpll[i].crtc_mask == 0)
4276 shared_dpll[i].hw_state =
4277 crtc_state->dpll_hw_state;
4278
4279 crtc_state->shared_dpll = i;
4280 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4281 pipe_name(crtc->pipe));
4282
4283 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4284
4285 return pll;
4286 }
4287
4288 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4289 {
4290 struct drm_i915_private *dev_priv = to_i915(state->dev);
4291 struct intel_shared_dpll_config *shared_dpll;
4292 struct intel_shared_dpll *pll;
4293 enum intel_dpll_id i;
4294
4295 if (!to_intel_atomic_state(state)->dpll_set)
4296 return;
4297
4298 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4299 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4300 pll = &dev_priv->shared_dplls[i];
4301 pll->config = shared_dpll[i];
4302 }
4303 }
4304
4305 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4306 {
4307 struct drm_i915_private *dev_priv = dev->dev_private;
4308 int dslreg = PIPEDSL(pipe);
4309 u32 temp;
4310
4311 temp = I915_READ(dslreg);
4312 udelay(500);
4313 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4314 if (wait_for(I915_READ(dslreg) != temp, 5))
4315 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4316 }
4317 }
4318
4319 static int
4320 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4321 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4322 int src_w, int src_h, int dst_w, int dst_h)
4323 {
4324 struct intel_crtc_scaler_state *scaler_state =
4325 &crtc_state->scaler_state;
4326 struct intel_crtc *intel_crtc =
4327 to_intel_crtc(crtc_state->base.crtc);
4328 int need_scaling;
4329
4330 need_scaling = intel_rotation_90_or_270(rotation) ?
4331 (src_h != dst_w || src_w != dst_h):
4332 (src_w != dst_w || src_h != dst_h);
4333
4334 /*
4335 * if plane is being disabled or scaler is no more required or force detach
4336 * - free scaler binded to this plane/crtc
4337 * - in order to do this, update crtc->scaler_usage
4338 *
4339 * Here scaler state in crtc_state is set free so that
4340 * scaler can be assigned to other user. Actual register
4341 * update to free the scaler is done in plane/panel-fit programming.
4342 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4343 */
4344 if (force_detach || !need_scaling) {
4345 if (*scaler_id >= 0) {
4346 scaler_state->scaler_users &= ~(1 << scaler_user);
4347 scaler_state->scalers[*scaler_id].in_use = 0;
4348
4349 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4350 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4351 intel_crtc->pipe, scaler_user, *scaler_id,
4352 scaler_state->scaler_users);
4353 *scaler_id = -1;
4354 }
4355 return 0;
4356 }
4357
4358 /* range checks */
4359 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4360 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4361
4362 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4363 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4364 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4365 "size is out of scaler range\n",
4366 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4367 return -EINVAL;
4368 }
4369
4370 /* mark this plane as a scaler user in crtc_state */
4371 scaler_state->scaler_users |= (1 << scaler_user);
4372 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4373 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4374 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4375 scaler_state->scaler_users);
4376
4377 return 0;
4378 }
4379
4380 /**
4381 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4382 *
4383 * @state: crtc's scaler state
4384 *
4385 * Return
4386 * 0 - scaler_usage updated successfully
4387 * error - requested scaling cannot be supported or other error condition
4388 */
4389 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4390 {
4391 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4392 struct drm_display_mode *adjusted_mode =
4393 &state->base.adjusted_mode;
4394
4395 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4396 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4397
4398 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4399 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4400 state->pipe_src_w, state->pipe_src_h,
4401 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
4402 }
4403
4404 /**
4405 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4406 *
4407 * @state: crtc's scaler state
4408 * @plane_state: atomic plane state to update
4409 *
4410 * Return
4411 * 0 - scaler_usage updated successfully
4412 * error - requested scaling cannot be supported or other error condition
4413 */
4414 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4415 struct intel_plane_state *plane_state)
4416 {
4417
4418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4419 struct intel_plane *intel_plane =
4420 to_intel_plane(plane_state->base.plane);
4421 struct drm_framebuffer *fb = plane_state->base.fb;
4422 int ret;
4423
4424 bool force_detach = !fb || !plane_state->visible;
4425
4426 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4427 intel_plane->base.base.id, intel_crtc->pipe,
4428 drm_plane_index(&intel_plane->base));
4429
4430 ret = skl_update_scaler(crtc_state, force_detach,
4431 drm_plane_index(&intel_plane->base),
4432 &plane_state->scaler_id,
4433 plane_state->base.rotation,
4434 drm_rect_width(&plane_state->src) >> 16,
4435 drm_rect_height(&plane_state->src) >> 16,
4436 drm_rect_width(&plane_state->dst),
4437 drm_rect_height(&plane_state->dst));
4438
4439 if (ret || plane_state->scaler_id < 0)
4440 return ret;
4441
4442 /* check colorkey */
4443 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4444 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4445 intel_plane->base.base.id);
4446 return -EINVAL;
4447 }
4448
4449 /* Check src format */
4450 switch (fb->pixel_format) {
4451 case DRM_FORMAT_RGB565:
4452 case DRM_FORMAT_XBGR8888:
4453 case DRM_FORMAT_XRGB8888:
4454 case DRM_FORMAT_ABGR8888:
4455 case DRM_FORMAT_ARGB8888:
4456 case DRM_FORMAT_XRGB2101010:
4457 case DRM_FORMAT_XBGR2101010:
4458 case DRM_FORMAT_YUYV:
4459 case DRM_FORMAT_YVYU:
4460 case DRM_FORMAT_UYVY:
4461 case DRM_FORMAT_VYUY:
4462 break;
4463 default:
4464 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4465 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4466 return -EINVAL;
4467 }
4468
4469 return 0;
4470 }
4471
4472 static void skylake_scaler_disable(struct intel_crtc *crtc)
4473 {
4474 int i;
4475
4476 for (i = 0; i < crtc->num_scalers; i++)
4477 skl_detach_scaler(crtc, i);
4478 }
4479
4480 static void skylake_pfit_enable(struct intel_crtc *crtc)
4481 {
4482 struct drm_device *dev = crtc->base.dev;
4483 struct drm_i915_private *dev_priv = dev->dev_private;
4484 int pipe = crtc->pipe;
4485 struct intel_crtc_scaler_state *scaler_state =
4486 &crtc->config->scaler_state;
4487
4488 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4489
4490 if (crtc->config->pch_pfit.enabled) {
4491 int id;
4492
4493 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4494 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4495 return;
4496 }
4497
4498 id = scaler_state->scaler_id;
4499 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4500 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4501 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4502 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4503
4504 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4505 }
4506 }
4507
4508 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4509 {
4510 struct drm_device *dev = crtc->base.dev;
4511 struct drm_i915_private *dev_priv = dev->dev_private;
4512 int pipe = crtc->pipe;
4513
4514 if (crtc->config->pch_pfit.enabled) {
4515 /* Force use of hard-coded filter coefficients
4516 * as some pre-programmed values are broken,
4517 * e.g. x201.
4518 */
4519 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4520 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4521 PF_PIPE_SEL_IVB(pipe));
4522 else
4523 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4524 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4525 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4526 }
4527 }
4528
4529 void hsw_enable_ips(struct intel_crtc *crtc)
4530 {
4531 struct drm_device *dev = crtc->base.dev;
4532 struct drm_i915_private *dev_priv = dev->dev_private;
4533
4534 if (!crtc->config->ips_enabled)
4535 return;
4536
4537 /* We can only enable IPS after we enable a plane and wait for a vblank */
4538 intel_wait_for_vblank(dev, crtc->pipe);
4539
4540 assert_plane_enabled(dev_priv, crtc->plane);
4541 if (IS_BROADWELL(dev)) {
4542 mutex_lock(&dev_priv->rps.hw_lock);
4543 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4544 mutex_unlock(&dev_priv->rps.hw_lock);
4545 /* Quoting Art Runyan: "its not safe to expect any particular
4546 * value in IPS_CTL bit 31 after enabling IPS through the
4547 * mailbox." Moreover, the mailbox may return a bogus state,
4548 * so we need to just enable it and continue on.
4549 */
4550 } else {
4551 I915_WRITE(IPS_CTL, IPS_ENABLE);
4552 /* The bit only becomes 1 in the next vblank, so this wait here
4553 * is essentially intel_wait_for_vblank. If we don't have this
4554 * and don't wait for vblanks until the end of crtc_enable, then
4555 * the HW state readout code will complain that the expected
4556 * IPS_CTL value is not the one we read. */
4557 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4558 DRM_ERROR("Timed out waiting for IPS enable\n");
4559 }
4560 }
4561
4562 void hsw_disable_ips(struct intel_crtc *crtc)
4563 {
4564 struct drm_device *dev = crtc->base.dev;
4565 struct drm_i915_private *dev_priv = dev->dev_private;
4566
4567 if (!crtc->config->ips_enabled)
4568 return;
4569
4570 assert_plane_enabled(dev_priv, crtc->plane);
4571 if (IS_BROADWELL(dev)) {
4572 mutex_lock(&dev_priv->rps.hw_lock);
4573 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4574 mutex_unlock(&dev_priv->rps.hw_lock);
4575 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4576 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4577 DRM_ERROR("Timed out waiting for IPS disable\n");
4578 } else {
4579 I915_WRITE(IPS_CTL, 0);
4580 POSTING_READ(IPS_CTL);
4581 }
4582
4583 /* We need to wait for a vblank before we can disable the plane. */
4584 intel_wait_for_vblank(dev, crtc->pipe);
4585 }
4586
4587 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4588 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4589 {
4590 struct drm_device *dev = crtc->dev;
4591 struct drm_i915_private *dev_priv = dev->dev_private;
4592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4593 enum pipe pipe = intel_crtc->pipe;
4594 int palreg = PALETTE(pipe);
4595 int i;
4596 bool reenable_ips = false;
4597
4598 /* The clocks have to be on to load the palette. */
4599 if (!crtc->state->active)
4600 return;
4601
4602 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4603 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4604 assert_dsi_pll_enabled(dev_priv);
4605 else
4606 assert_pll_enabled(dev_priv, pipe);
4607 }
4608
4609 /* use legacy palette for Ironlake */
4610 if (!HAS_GMCH_DISPLAY(dev))
4611 palreg = LGC_PALETTE(pipe);
4612
4613 /* Workaround : Do not read or write the pipe palette/gamma data while
4614 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4615 */
4616 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4617 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4618 GAMMA_MODE_MODE_SPLIT)) {
4619 hsw_disable_ips(intel_crtc);
4620 reenable_ips = true;
4621 }
4622
4623 for (i = 0; i < 256; i++) {
4624 I915_WRITE(palreg + 4 * i,
4625 (intel_crtc->lut_r[i] << 16) |
4626 (intel_crtc->lut_g[i] << 8) |
4627 intel_crtc->lut_b[i]);
4628 }
4629
4630 if (reenable_ips)
4631 hsw_enable_ips(intel_crtc);
4632 }
4633
4634 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4635 {
4636 if (intel_crtc->overlay) {
4637 struct drm_device *dev = intel_crtc->base.dev;
4638 struct drm_i915_private *dev_priv = dev->dev_private;
4639
4640 mutex_lock(&dev->struct_mutex);
4641 dev_priv->mm.interruptible = false;
4642 (void) intel_overlay_switch_off(intel_crtc->overlay);
4643 dev_priv->mm.interruptible = true;
4644 mutex_unlock(&dev->struct_mutex);
4645 }
4646
4647 /* Let userspace switch the overlay on again. In most cases userspace
4648 * has to recompute where to put it anyway.
4649 */
4650 }
4651
4652 /**
4653 * intel_post_enable_primary - Perform operations after enabling primary plane
4654 * @crtc: the CRTC whose primary plane was just enabled
4655 *
4656 * Performs potentially sleeping operations that must be done after the primary
4657 * plane is enabled, such as updating FBC and IPS. Note that this may be
4658 * called due to an explicit primary plane update, or due to an implicit
4659 * re-enable that is caused when a sprite plane is updated to no longer
4660 * completely hide the primary plane.
4661 */
4662 static void
4663 intel_post_enable_primary(struct drm_crtc *crtc)
4664 {
4665 struct drm_device *dev = crtc->dev;
4666 struct drm_i915_private *dev_priv = dev->dev_private;
4667 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4668 int pipe = intel_crtc->pipe;
4669
4670 /*
4671 * BDW signals flip done immediately if the plane
4672 * is disabled, even if the plane enable is already
4673 * armed to occur at the next vblank :(
4674 */
4675 if (IS_BROADWELL(dev))
4676 intel_wait_for_vblank(dev, pipe);
4677
4678 /*
4679 * FIXME IPS should be fine as long as one plane is
4680 * enabled, but in practice it seems to have problems
4681 * when going from primary only to sprite only and vice
4682 * versa.
4683 */
4684 hsw_enable_ips(intel_crtc);
4685
4686 /*
4687 * Gen2 reports pipe underruns whenever all planes are disabled.
4688 * So don't enable underrun reporting before at least some planes
4689 * are enabled.
4690 * FIXME: Need to fix the logic to work when we turn off all planes
4691 * but leave the pipe running.
4692 */
4693 if (IS_GEN2(dev))
4694 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4695
4696 /* Underruns don't raise interrupts, so check manually. */
4697 if (HAS_GMCH_DISPLAY(dev))
4698 i9xx_check_fifo_underruns(dev_priv);
4699 }
4700
4701 /**
4702 * intel_pre_disable_primary - Perform operations before disabling primary plane
4703 * @crtc: the CRTC whose primary plane is to be disabled
4704 *
4705 * Performs potentially sleeping operations that must be done before the
4706 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4707 * be called due to an explicit primary plane update, or due to an implicit
4708 * disable that is caused when a sprite plane completely hides the primary
4709 * plane.
4710 */
4711 static void
4712 intel_pre_disable_primary(struct drm_crtc *crtc)
4713 {
4714 struct drm_device *dev = crtc->dev;
4715 struct drm_i915_private *dev_priv = dev->dev_private;
4716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4717 int pipe = intel_crtc->pipe;
4718
4719 /*
4720 * Gen2 reports pipe underruns whenever all planes are disabled.
4721 * So diasble underrun reporting before all the planes get disabled.
4722 * FIXME: Need to fix the logic to work when we turn off all planes
4723 * but leave the pipe running.
4724 */
4725 if (IS_GEN2(dev))
4726 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4727
4728 /*
4729 * Vblank time updates from the shadow to live plane control register
4730 * are blocked if the memory self-refresh mode is active at that
4731 * moment. So to make sure the plane gets truly disabled, disable
4732 * first the self-refresh mode. The self-refresh enable bit in turn
4733 * will be checked/applied by the HW only at the next frame start
4734 * event which is after the vblank start event, so we need to have a
4735 * wait-for-vblank between disabling the plane and the pipe.
4736 */
4737 if (HAS_GMCH_DISPLAY(dev)) {
4738 intel_set_memory_cxsr(dev_priv, false);
4739 dev_priv->wm.vlv.cxsr = false;
4740 intel_wait_for_vblank(dev, pipe);
4741 }
4742
4743 /*
4744 * FIXME IPS should be fine as long as one plane is
4745 * enabled, but in practice it seems to have problems
4746 * when going from primary only to sprite only and vice
4747 * versa.
4748 */
4749 hsw_disable_ips(intel_crtc);
4750 }
4751
4752 static void intel_post_plane_update(struct intel_crtc *crtc)
4753 {
4754 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4755 struct drm_device *dev = crtc->base.dev;
4756 struct drm_i915_private *dev_priv = dev->dev_private;
4757 struct drm_plane *plane;
4758
4759 if (atomic->wait_vblank)
4760 intel_wait_for_vblank(dev, crtc->pipe);
4761
4762 intel_frontbuffer_flip(dev, atomic->fb_bits);
4763
4764 if (atomic->disable_cxsr)
4765 crtc->wm.cxsr_allowed = true;
4766
4767 if (crtc->atomic.update_wm_post)
4768 intel_update_watermarks(&crtc->base);
4769
4770 if (atomic->update_fbc)
4771 intel_fbc_update(dev_priv);
4772
4773 if (atomic->post_enable_primary)
4774 intel_post_enable_primary(&crtc->base);
4775
4776 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4777 intel_update_sprite_watermarks(plane, &crtc->base,
4778 0, 0, 0, false, false);
4779
4780 memset(atomic, 0, sizeof(*atomic));
4781 }
4782
4783 static void intel_pre_plane_update(struct intel_crtc *crtc)
4784 {
4785 struct drm_device *dev = crtc->base.dev;
4786 struct drm_i915_private *dev_priv = dev->dev_private;
4787 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4788 struct drm_plane *p;
4789
4790 /* Track fb's for any planes being disabled */
4791 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4792 struct intel_plane *plane = to_intel_plane(p);
4793
4794 mutex_lock(&dev->struct_mutex);
4795 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4796 plane->frontbuffer_bit);
4797 mutex_unlock(&dev->struct_mutex);
4798 }
4799
4800 if (atomic->wait_for_flips)
4801 intel_crtc_wait_for_pending_flips(&crtc->base);
4802
4803 if (atomic->disable_fbc)
4804 intel_fbc_disable_crtc(crtc);
4805
4806 if (crtc->atomic.disable_ips)
4807 hsw_disable_ips(crtc);
4808
4809 if (atomic->pre_disable_primary)
4810 intel_pre_disable_primary(&crtc->base);
4811
4812 if (atomic->disable_cxsr) {
4813 crtc->wm.cxsr_allowed = false;
4814 intel_set_memory_cxsr(dev_priv, false);
4815 }
4816 }
4817
4818 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4819 {
4820 struct drm_device *dev = crtc->dev;
4821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4822 struct drm_plane *p;
4823 int pipe = intel_crtc->pipe;
4824
4825 intel_crtc_dpms_overlay_disable(intel_crtc);
4826
4827 drm_for_each_plane_mask(p, dev, plane_mask)
4828 to_intel_plane(p)->disable_plane(p, crtc);
4829
4830 /*
4831 * FIXME: Once we grow proper nuclear flip support out of this we need
4832 * to compute the mask of flip planes precisely. For the time being
4833 * consider this a flip to a NULL plane.
4834 */
4835 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4836 }
4837
4838 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4839 {
4840 struct drm_device *dev = crtc->dev;
4841 struct drm_i915_private *dev_priv = dev->dev_private;
4842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4843 struct intel_encoder *encoder;
4844 int pipe = intel_crtc->pipe;
4845
4846 if (WARN_ON(intel_crtc->active))
4847 return;
4848
4849 if (intel_crtc->config->has_pch_encoder)
4850 intel_prepare_shared_dpll(intel_crtc);
4851
4852 if (intel_crtc->config->has_dp_encoder)
4853 intel_dp_set_m_n(intel_crtc, M1_N1);
4854
4855 intel_set_pipe_timings(intel_crtc);
4856
4857 if (intel_crtc->config->has_pch_encoder) {
4858 intel_cpu_transcoder_set_m_n(intel_crtc,
4859 &intel_crtc->config->fdi_m_n, NULL);
4860 }
4861
4862 ironlake_set_pipeconf(crtc);
4863
4864 intel_crtc->active = true;
4865
4866 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4867 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4868
4869 for_each_encoder_on_crtc(dev, crtc, encoder)
4870 if (encoder->pre_enable)
4871 encoder->pre_enable(encoder);
4872
4873 if (intel_crtc->config->has_pch_encoder) {
4874 /* Note: FDI PLL enabling _must_ be done before we enable the
4875 * cpu pipes, hence this is separate from all the other fdi/pch
4876 * enabling. */
4877 ironlake_fdi_pll_enable(intel_crtc);
4878 } else {
4879 assert_fdi_tx_disabled(dev_priv, pipe);
4880 assert_fdi_rx_disabled(dev_priv, pipe);
4881 }
4882
4883 ironlake_pfit_enable(intel_crtc);
4884
4885 /*
4886 * On ILK+ LUT must be loaded before the pipe is running but with
4887 * clocks enabled
4888 */
4889 intel_crtc_load_lut(crtc);
4890
4891 intel_update_watermarks(crtc);
4892 intel_enable_pipe(intel_crtc);
4893
4894 if (intel_crtc->config->has_pch_encoder)
4895 ironlake_pch_enable(crtc);
4896
4897 assert_vblank_disabled(crtc);
4898 drm_crtc_vblank_on(crtc);
4899
4900 for_each_encoder_on_crtc(dev, crtc, encoder)
4901 encoder->enable(encoder);
4902
4903 if (HAS_PCH_CPT(dev))
4904 cpt_verify_modeset(dev, intel_crtc->pipe);
4905 }
4906
4907 /* IPS only exists on ULT machines and is tied to pipe A. */
4908 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4909 {
4910 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4911 }
4912
4913 static void haswell_crtc_enable(struct drm_crtc *crtc)
4914 {
4915 struct drm_device *dev = crtc->dev;
4916 struct drm_i915_private *dev_priv = dev->dev_private;
4917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4918 struct intel_encoder *encoder;
4919 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4920 struct intel_crtc_state *pipe_config =
4921 to_intel_crtc_state(crtc->state);
4922
4923 if (WARN_ON(intel_crtc->active))
4924 return;
4925
4926 if (intel_crtc_to_shared_dpll(intel_crtc))
4927 intel_enable_shared_dpll(intel_crtc);
4928
4929 if (intel_crtc->config->has_dp_encoder)
4930 intel_dp_set_m_n(intel_crtc, M1_N1);
4931
4932 intel_set_pipe_timings(intel_crtc);
4933
4934 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4935 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4936 intel_crtc->config->pixel_multiplier - 1);
4937 }
4938
4939 if (intel_crtc->config->has_pch_encoder) {
4940 intel_cpu_transcoder_set_m_n(intel_crtc,
4941 &intel_crtc->config->fdi_m_n, NULL);
4942 }
4943
4944 haswell_set_pipeconf(crtc);
4945
4946 intel_set_pipe_csc(crtc);
4947
4948 intel_crtc->active = true;
4949
4950 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4951 for_each_encoder_on_crtc(dev, crtc, encoder)
4952 if (encoder->pre_enable)
4953 encoder->pre_enable(encoder);
4954
4955 if (intel_crtc->config->has_pch_encoder) {
4956 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4957 true);
4958 dev_priv->display.fdi_link_train(crtc);
4959 }
4960
4961 intel_ddi_enable_pipe_clock(intel_crtc);
4962
4963 if (INTEL_INFO(dev)->gen == 9)
4964 skylake_pfit_enable(intel_crtc);
4965 else if (INTEL_INFO(dev)->gen < 9)
4966 ironlake_pfit_enable(intel_crtc);
4967 else
4968 MISSING_CASE(INTEL_INFO(dev)->gen);
4969
4970 /*
4971 * On ILK+ LUT must be loaded before the pipe is running but with
4972 * clocks enabled
4973 */
4974 intel_crtc_load_lut(crtc);
4975
4976 intel_ddi_set_pipe_settings(crtc);
4977 intel_ddi_enable_transcoder_func(crtc);
4978
4979 intel_update_watermarks(crtc);
4980 intel_enable_pipe(intel_crtc);
4981
4982 if (intel_crtc->config->has_pch_encoder)
4983 lpt_pch_enable(crtc);
4984
4985 if (intel_crtc->config->dp_encoder_is_mst)
4986 intel_ddi_set_vc_payload_alloc(crtc, true);
4987
4988 assert_vblank_disabled(crtc);
4989 drm_crtc_vblank_on(crtc);
4990
4991 for_each_encoder_on_crtc(dev, crtc, encoder) {
4992 encoder->enable(encoder);
4993 intel_opregion_notify_encoder(encoder, true);
4994 }
4995
4996 /* If we change the relative order between pipe/planes enabling, we need
4997 * to change the workaround. */
4998 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4999 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5000 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5001 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5002 }
5003 }
5004
5005 static void ironlake_pfit_disable(struct intel_crtc *crtc)
5006 {
5007 struct drm_device *dev = crtc->base.dev;
5008 struct drm_i915_private *dev_priv = dev->dev_private;
5009 int pipe = crtc->pipe;
5010
5011 /* To avoid upsetting the power well on haswell only disable the pfit if
5012 * it's in use. The hw state code will make sure we get this right. */
5013 if (crtc->config->pch_pfit.enabled) {
5014 I915_WRITE(PF_CTL(pipe), 0);
5015 I915_WRITE(PF_WIN_POS(pipe), 0);
5016 I915_WRITE(PF_WIN_SZ(pipe), 0);
5017 }
5018 }
5019
5020 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5021 {
5022 struct drm_device *dev = crtc->dev;
5023 struct drm_i915_private *dev_priv = dev->dev_private;
5024 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5025 struct intel_encoder *encoder;
5026 int pipe = intel_crtc->pipe;
5027 u32 reg, temp;
5028
5029 for_each_encoder_on_crtc(dev, crtc, encoder)
5030 encoder->disable(encoder);
5031
5032 drm_crtc_vblank_off(crtc);
5033 assert_vblank_disabled(crtc);
5034
5035 if (intel_crtc->config->has_pch_encoder)
5036 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5037
5038 intel_disable_pipe(intel_crtc);
5039
5040 ironlake_pfit_disable(intel_crtc);
5041
5042 if (intel_crtc->config->has_pch_encoder)
5043 ironlake_fdi_disable(crtc);
5044
5045 for_each_encoder_on_crtc(dev, crtc, encoder)
5046 if (encoder->post_disable)
5047 encoder->post_disable(encoder);
5048
5049 if (intel_crtc->config->has_pch_encoder) {
5050 ironlake_disable_pch_transcoder(dev_priv, pipe);
5051
5052 if (HAS_PCH_CPT(dev)) {
5053 /* disable TRANS_DP_CTL */
5054 reg = TRANS_DP_CTL(pipe);
5055 temp = I915_READ(reg);
5056 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5057 TRANS_DP_PORT_SEL_MASK);
5058 temp |= TRANS_DP_PORT_SEL_NONE;
5059 I915_WRITE(reg, temp);
5060
5061 /* disable DPLL_SEL */
5062 temp = I915_READ(PCH_DPLL_SEL);
5063 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5064 I915_WRITE(PCH_DPLL_SEL, temp);
5065 }
5066
5067 ironlake_fdi_pll_disable(intel_crtc);
5068 }
5069
5070 intel_crtc->active = false;
5071 intel_update_watermarks(crtc);
5072 }
5073
5074 static void haswell_crtc_disable(struct drm_crtc *crtc)
5075 {
5076 struct drm_device *dev = crtc->dev;
5077 struct drm_i915_private *dev_priv = dev->dev_private;
5078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5079 struct intel_encoder *encoder;
5080 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5081
5082 for_each_encoder_on_crtc(dev, crtc, encoder) {
5083 intel_opregion_notify_encoder(encoder, false);
5084 encoder->disable(encoder);
5085 }
5086
5087 drm_crtc_vblank_off(crtc);
5088 assert_vblank_disabled(crtc);
5089
5090 if (intel_crtc->config->has_pch_encoder)
5091 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5092 false);
5093 intel_disable_pipe(intel_crtc);
5094
5095 if (intel_crtc->config->dp_encoder_is_mst)
5096 intel_ddi_set_vc_payload_alloc(crtc, false);
5097
5098 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5099
5100 if (INTEL_INFO(dev)->gen == 9)
5101 skylake_scaler_disable(intel_crtc);
5102 else if (INTEL_INFO(dev)->gen < 9)
5103 ironlake_pfit_disable(intel_crtc);
5104 else
5105 MISSING_CASE(INTEL_INFO(dev)->gen);
5106
5107 intel_ddi_disable_pipe_clock(intel_crtc);
5108
5109 if (intel_crtc->config->has_pch_encoder) {
5110 lpt_disable_pch_transcoder(dev_priv);
5111 intel_ddi_fdi_disable(crtc);
5112 }
5113
5114 for_each_encoder_on_crtc(dev, crtc, encoder)
5115 if (encoder->post_disable)
5116 encoder->post_disable(encoder);
5117
5118 intel_crtc->active = false;
5119 intel_update_watermarks(crtc);
5120 }
5121
5122 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5123 {
5124 struct drm_device *dev = crtc->base.dev;
5125 struct drm_i915_private *dev_priv = dev->dev_private;
5126 struct intel_crtc_state *pipe_config = crtc->config;
5127
5128 if (!pipe_config->gmch_pfit.control)
5129 return;
5130
5131 /*
5132 * The panel fitter should only be adjusted whilst the pipe is disabled,
5133 * according to register description and PRM.
5134 */
5135 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5136 assert_pipe_disabled(dev_priv, crtc->pipe);
5137
5138 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5139 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5140
5141 /* Border color in case we don't scale up to the full screen. Black by
5142 * default, change to something else for debugging. */
5143 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5144 }
5145
5146 static enum intel_display_power_domain port_to_power_domain(enum port port)
5147 {
5148 switch (port) {
5149 case PORT_A:
5150 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5151 case PORT_B:
5152 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5153 case PORT_C:
5154 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5155 case PORT_D:
5156 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5157 default:
5158 WARN_ON_ONCE(1);
5159 return POWER_DOMAIN_PORT_OTHER;
5160 }
5161 }
5162
5163 #define for_each_power_domain(domain, mask) \
5164 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5165 if ((1 << (domain)) & (mask))
5166
5167 enum intel_display_power_domain
5168 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5169 {
5170 struct drm_device *dev = intel_encoder->base.dev;
5171 struct intel_digital_port *intel_dig_port;
5172
5173 switch (intel_encoder->type) {
5174 case INTEL_OUTPUT_UNKNOWN:
5175 /* Only DDI platforms should ever use this output type */
5176 WARN_ON_ONCE(!HAS_DDI(dev));
5177 case INTEL_OUTPUT_DISPLAYPORT:
5178 case INTEL_OUTPUT_HDMI:
5179 case INTEL_OUTPUT_EDP:
5180 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5181 return port_to_power_domain(intel_dig_port->port);
5182 case INTEL_OUTPUT_DP_MST:
5183 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5184 return port_to_power_domain(intel_dig_port->port);
5185 case INTEL_OUTPUT_ANALOG:
5186 return POWER_DOMAIN_PORT_CRT;
5187 case INTEL_OUTPUT_DSI:
5188 return POWER_DOMAIN_PORT_DSI;
5189 default:
5190 return POWER_DOMAIN_PORT_OTHER;
5191 }
5192 }
5193
5194 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5195 {
5196 struct drm_device *dev = crtc->dev;
5197 struct intel_encoder *intel_encoder;
5198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5199 enum pipe pipe = intel_crtc->pipe;
5200 unsigned long mask;
5201 enum transcoder transcoder;
5202
5203 if (!crtc->state->active)
5204 return 0;
5205
5206 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5207
5208 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5209 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5210 if (intel_crtc->config->pch_pfit.enabled ||
5211 intel_crtc->config->pch_pfit.force_thru)
5212 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5213
5214 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5215 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5216
5217 return mask;
5218 }
5219
5220 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5221 {
5222 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5224 enum intel_display_power_domain domain;
5225 unsigned long domains, new_domains, old_domains;
5226
5227 old_domains = intel_crtc->enabled_power_domains;
5228 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5229
5230 domains = new_domains & ~old_domains;
5231
5232 for_each_power_domain(domain, domains)
5233 intel_display_power_get(dev_priv, domain);
5234
5235 return old_domains & ~new_domains;
5236 }
5237
5238 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5239 unsigned long domains)
5240 {
5241 enum intel_display_power_domain domain;
5242
5243 for_each_power_domain(domain, domains)
5244 intel_display_power_put(dev_priv, domain);
5245 }
5246
5247 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5248 {
5249 struct drm_device *dev = state->dev;
5250 struct drm_i915_private *dev_priv = dev->dev_private;
5251 unsigned long put_domains[I915_MAX_PIPES] = {};
5252 struct drm_crtc_state *crtc_state;
5253 struct drm_crtc *crtc;
5254 int i;
5255
5256 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5257 if (needs_modeset(crtc->state))
5258 put_domains[to_intel_crtc(crtc)->pipe] =
5259 modeset_get_crtc_power_domains(crtc);
5260 }
5261
5262 if (dev_priv->display.modeset_commit_cdclk) {
5263 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5264
5265 if (cdclk != dev_priv->cdclk_freq &&
5266 !WARN_ON(!state->allow_modeset))
5267 dev_priv->display.modeset_commit_cdclk(state);
5268 }
5269
5270 for (i = 0; i < I915_MAX_PIPES; i++)
5271 if (put_domains[i])
5272 modeset_put_power_domains(dev_priv, put_domains[i]);
5273 }
5274
5275 static void intel_update_max_cdclk(struct drm_device *dev)
5276 {
5277 struct drm_i915_private *dev_priv = dev->dev_private;
5278
5279 if (IS_SKYLAKE(dev)) {
5280 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5281
5282 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5283 dev_priv->max_cdclk_freq = 675000;
5284 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5285 dev_priv->max_cdclk_freq = 540000;
5286 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5287 dev_priv->max_cdclk_freq = 450000;
5288 else
5289 dev_priv->max_cdclk_freq = 337500;
5290 } else if (IS_BROADWELL(dev)) {
5291 /*
5292 * FIXME with extra cooling we can allow
5293 * 540 MHz for ULX and 675 Mhz for ULT.
5294 * How can we know if extra cooling is
5295 * available? PCI ID, VTB, something else?
5296 */
5297 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5298 dev_priv->max_cdclk_freq = 450000;
5299 else if (IS_BDW_ULX(dev))
5300 dev_priv->max_cdclk_freq = 450000;
5301 else if (IS_BDW_ULT(dev))
5302 dev_priv->max_cdclk_freq = 540000;
5303 else
5304 dev_priv->max_cdclk_freq = 675000;
5305 } else if (IS_CHERRYVIEW(dev)) {
5306 dev_priv->max_cdclk_freq = 320000;
5307 } else if (IS_VALLEYVIEW(dev)) {
5308 dev_priv->max_cdclk_freq = 400000;
5309 } else {
5310 /* otherwise assume cdclk is fixed */
5311 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5312 }
5313
5314 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5315 dev_priv->max_cdclk_freq);
5316 }
5317
5318 static void intel_update_cdclk(struct drm_device *dev)
5319 {
5320 struct drm_i915_private *dev_priv = dev->dev_private;
5321
5322 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5323 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5324 dev_priv->cdclk_freq);
5325
5326 /*
5327 * Program the gmbus_freq based on the cdclk frequency.
5328 * BSpec erroneously claims we should aim for 4MHz, but
5329 * in fact 1MHz is the correct frequency.
5330 */
5331 if (IS_VALLEYVIEW(dev)) {
5332 /*
5333 * Program the gmbus_freq based on the cdclk frequency.
5334 * BSpec erroneously claims we should aim for 4MHz, but
5335 * in fact 1MHz is the correct frequency.
5336 */
5337 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5338 }
5339
5340 if (dev_priv->max_cdclk_freq == 0)
5341 intel_update_max_cdclk(dev);
5342 }
5343
5344 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5345 {
5346 struct drm_i915_private *dev_priv = dev->dev_private;
5347 uint32_t divider;
5348 uint32_t ratio;
5349 uint32_t current_freq;
5350 int ret;
5351
5352 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5353 switch (frequency) {
5354 case 144000:
5355 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5356 ratio = BXT_DE_PLL_RATIO(60);
5357 break;
5358 case 288000:
5359 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5360 ratio = BXT_DE_PLL_RATIO(60);
5361 break;
5362 case 384000:
5363 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5364 ratio = BXT_DE_PLL_RATIO(60);
5365 break;
5366 case 576000:
5367 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5368 ratio = BXT_DE_PLL_RATIO(60);
5369 break;
5370 case 624000:
5371 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5372 ratio = BXT_DE_PLL_RATIO(65);
5373 break;
5374 case 19200:
5375 /*
5376 * Bypass frequency with DE PLL disabled. Init ratio, divider
5377 * to suppress GCC warning.
5378 */
5379 ratio = 0;
5380 divider = 0;
5381 break;
5382 default:
5383 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5384
5385 return;
5386 }
5387
5388 mutex_lock(&dev_priv->rps.hw_lock);
5389 /* Inform power controller of upcoming frequency change */
5390 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5391 0x80000000);
5392 mutex_unlock(&dev_priv->rps.hw_lock);
5393
5394 if (ret) {
5395 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5396 ret, frequency);
5397 return;
5398 }
5399
5400 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5401 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5402 current_freq = current_freq * 500 + 1000;
5403
5404 /*
5405 * DE PLL has to be disabled when
5406 * - setting to 19.2MHz (bypass, PLL isn't used)
5407 * - before setting to 624MHz (PLL needs toggling)
5408 * - before setting to any frequency from 624MHz (PLL needs toggling)
5409 */
5410 if (frequency == 19200 || frequency == 624000 ||
5411 current_freq == 624000) {
5412 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5413 /* Timeout 200us */
5414 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5415 1))
5416 DRM_ERROR("timout waiting for DE PLL unlock\n");
5417 }
5418
5419 if (frequency != 19200) {
5420 uint32_t val;
5421
5422 val = I915_READ(BXT_DE_PLL_CTL);
5423 val &= ~BXT_DE_PLL_RATIO_MASK;
5424 val |= ratio;
5425 I915_WRITE(BXT_DE_PLL_CTL, val);
5426
5427 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5428 /* Timeout 200us */
5429 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5430 DRM_ERROR("timeout waiting for DE PLL lock\n");
5431
5432 val = I915_READ(CDCLK_CTL);
5433 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5434 val |= divider;
5435 /*
5436 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5437 * enable otherwise.
5438 */
5439 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5440 if (frequency >= 500000)
5441 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5442
5443 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5444 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5445 val |= (frequency - 1000) / 500;
5446 I915_WRITE(CDCLK_CTL, val);
5447 }
5448
5449 mutex_lock(&dev_priv->rps.hw_lock);
5450 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5451 DIV_ROUND_UP(frequency, 25000));
5452 mutex_unlock(&dev_priv->rps.hw_lock);
5453
5454 if (ret) {
5455 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5456 ret, frequency);
5457 return;
5458 }
5459
5460 intel_update_cdclk(dev);
5461 }
5462
5463 void broxton_init_cdclk(struct drm_device *dev)
5464 {
5465 struct drm_i915_private *dev_priv = dev->dev_private;
5466 uint32_t val;
5467
5468 /*
5469 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5470 * or else the reset will hang because there is no PCH to respond.
5471 * Move the handshake programming to initialization sequence.
5472 * Previously was left up to BIOS.
5473 */
5474 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5475 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5476 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5477
5478 /* Enable PG1 for cdclk */
5479 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5480
5481 /* check if cd clock is enabled */
5482 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5483 DRM_DEBUG_KMS("Display already initialized\n");
5484 return;
5485 }
5486
5487 /*
5488 * FIXME:
5489 * - The initial CDCLK needs to be read from VBT.
5490 * Need to make this change after VBT has changes for BXT.
5491 * - check if setting the max (or any) cdclk freq is really necessary
5492 * here, it belongs to modeset time
5493 */
5494 broxton_set_cdclk(dev, 624000);
5495
5496 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5497 POSTING_READ(DBUF_CTL);
5498
5499 udelay(10);
5500
5501 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5502 DRM_ERROR("DBuf power enable timeout!\n");
5503 }
5504
5505 void broxton_uninit_cdclk(struct drm_device *dev)
5506 {
5507 struct drm_i915_private *dev_priv = dev->dev_private;
5508
5509 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5510 POSTING_READ(DBUF_CTL);
5511
5512 udelay(10);
5513
5514 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5515 DRM_ERROR("DBuf power disable timeout!\n");
5516
5517 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5518 broxton_set_cdclk(dev, 19200);
5519
5520 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5521 }
5522
5523 static const struct skl_cdclk_entry {
5524 unsigned int freq;
5525 unsigned int vco;
5526 } skl_cdclk_frequencies[] = {
5527 { .freq = 308570, .vco = 8640 },
5528 { .freq = 337500, .vco = 8100 },
5529 { .freq = 432000, .vco = 8640 },
5530 { .freq = 450000, .vco = 8100 },
5531 { .freq = 540000, .vco = 8100 },
5532 { .freq = 617140, .vco = 8640 },
5533 { .freq = 675000, .vco = 8100 },
5534 };
5535
5536 static unsigned int skl_cdclk_decimal(unsigned int freq)
5537 {
5538 return (freq - 1000) / 500;
5539 }
5540
5541 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5542 {
5543 unsigned int i;
5544
5545 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5546 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5547
5548 if (e->freq == freq)
5549 return e->vco;
5550 }
5551
5552 return 8100;
5553 }
5554
5555 static void
5556 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5557 {
5558 unsigned int min_freq;
5559 u32 val;
5560
5561 /* select the minimum CDCLK before enabling DPLL 0 */
5562 val = I915_READ(CDCLK_CTL);
5563 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5564 val |= CDCLK_FREQ_337_308;
5565
5566 if (required_vco == 8640)
5567 min_freq = 308570;
5568 else
5569 min_freq = 337500;
5570
5571 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5572
5573 I915_WRITE(CDCLK_CTL, val);
5574 POSTING_READ(CDCLK_CTL);
5575
5576 /*
5577 * We always enable DPLL0 with the lowest link rate possible, but still
5578 * taking into account the VCO required to operate the eDP panel at the
5579 * desired frequency. The usual DP link rates operate with a VCO of
5580 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5581 * The modeset code is responsible for the selection of the exact link
5582 * rate later on, with the constraint of choosing a frequency that
5583 * works with required_vco.
5584 */
5585 val = I915_READ(DPLL_CTRL1);
5586
5587 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5588 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5589 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5590 if (required_vco == 8640)
5591 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5592 SKL_DPLL0);
5593 else
5594 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5595 SKL_DPLL0);
5596
5597 I915_WRITE(DPLL_CTRL1, val);
5598 POSTING_READ(DPLL_CTRL1);
5599
5600 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5601
5602 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5603 DRM_ERROR("DPLL0 not locked\n");
5604 }
5605
5606 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5607 {
5608 int ret;
5609 u32 val;
5610
5611 /* inform PCU we want to change CDCLK */
5612 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5613 mutex_lock(&dev_priv->rps.hw_lock);
5614 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5615 mutex_unlock(&dev_priv->rps.hw_lock);
5616
5617 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5618 }
5619
5620 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5621 {
5622 unsigned int i;
5623
5624 for (i = 0; i < 15; i++) {
5625 if (skl_cdclk_pcu_ready(dev_priv))
5626 return true;
5627 udelay(10);
5628 }
5629
5630 return false;
5631 }
5632
5633 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5634 {
5635 struct drm_device *dev = dev_priv->dev;
5636 u32 freq_select, pcu_ack;
5637
5638 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5639
5640 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5641 DRM_ERROR("failed to inform PCU about cdclk change\n");
5642 return;
5643 }
5644
5645 /* set CDCLK_CTL */
5646 switch(freq) {
5647 case 450000:
5648 case 432000:
5649 freq_select = CDCLK_FREQ_450_432;
5650 pcu_ack = 1;
5651 break;
5652 case 540000:
5653 freq_select = CDCLK_FREQ_540;
5654 pcu_ack = 2;
5655 break;
5656 case 308570:
5657 case 337500:
5658 default:
5659 freq_select = CDCLK_FREQ_337_308;
5660 pcu_ack = 0;
5661 break;
5662 case 617140:
5663 case 675000:
5664 freq_select = CDCLK_FREQ_675_617;
5665 pcu_ack = 3;
5666 break;
5667 }
5668
5669 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5670 POSTING_READ(CDCLK_CTL);
5671
5672 /* inform PCU of the change */
5673 mutex_lock(&dev_priv->rps.hw_lock);
5674 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5675 mutex_unlock(&dev_priv->rps.hw_lock);
5676
5677 intel_update_cdclk(dev);
5678 }
5679
5680 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5681 {
5682 /* disable DBUF power */
5683 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5684 POSTING_READ(DBUF_CTL);
5685
5686 udelay(10);
5687
5688 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5689 DRM_ERROR("DBuf power disable timeout\n");
5690
5691 /* disable DPLL0 */
5692 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5693 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5694 DRM_ERROR("Couldn't disable DPLL0\n");
5695
5696 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5697 }
5698
5699 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5700 {
5701 u32 val;
5702 unsigned int required_vco;
5703
5704 /* enable PCH reset handshake */
5705 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5706 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5707
5708 /* enable PG1 and Misc I/O */
5709 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5710
5711 /* DPLL0 already enabed !? */
5712 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5713 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5714 return;
5715 }
5716
5717 /* enable DPLL0 */
5718 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5719 skl_dpll0_enable(dev_priv, required_vco);
5720
5721 /* set CDCLK to the frequency the BIOS chose */
5722 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5723
5724 /* enable DBUF power */
5725 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5726 POSTING_READ(DBUF_CTL);
5727
5728 udelay(10);
5729
5730 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5731 DRM_ERROR("DBuf power enable timeout\n");
5732 }
5733
5734 /* returns HPLL frequency in kHz */
5735 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5736 {
5737 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5738
5739 /* Obtain SKU information */
5740 mutex_lock(&dev_priv->sb_lock);
5741 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5742 CCK_FUSE_HPLL_FREQ_MASK;
5743 mutex_unlock(&dev_priv->sb_lock);
5744
5745 return vco_freq[hpll_freq] * 1000;
5746 }
5747
5748 /* Adjust CDclk dividers to allow high res or save power if possible */
5749 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5750 {
5751 struct drm_i915_private *dev_priv = dev->dev_private;
5752 u32 val, cmd;
5753
5754 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5755 != dev_priv->cdclk_freq);
5756
5757 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5758 cmd = 2;
5759 else if (cdclk == 266667)
5760 cmd = 1;
5761 else
5762 cmd = 0;
5763
5764 mutex_lock(&dev_priv->rps.hw_lock);
5765 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5766 val &= ~DSPFREQGUAR_MASK;
5767 val |= (cmd << DSPFREQGUAR_SHIFT);
5768 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5769 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5770 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5771 50)) {
5772 DRM_ERROR("timed out waiting for CDclk change\n");
5773 }
5774 mutex_unlock(&dev_priv->rps.hw_lock);
5775
5776 mutex_lock(&dev_priv->sb_lock);
5777
5778 if (cdclk == 400000) {
5779 u32 divider;
5780
5781 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5782
5783 /* adjust cdclk divider */
5784 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5785 val &= ~DISPLAY_FREQUENCY_VALUES;
5786 val |= divider;
5787 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5788
5789 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5790 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5791 50))
5792 DRM_ERROR("timed out waiting for CDclk change\n");
5793 }
5794
5795 /* adjust self-refresh exit latency value */
5796 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5797 val &= ~0x7f;
5798
5799 /*
5800 * For high bandwidth configs, we set a higher latency in the bunit
5801 * so that the core display fetch happens in time to avoid underruns.
5802 */
5803 if (cdclk == 400000)
5804 val |= 4500 / 250; /* 4.5 usec */
5805 else
5806 val |= 3000 / 250; /* 3.0 usec */
5807 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5808
5809 mutex_unlock(&dev_priv->sb_lock);
5810
5811 intel_update_cdclk(dev);
5812 }
5813
5814 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5815 {
5816 struct drm_i915_private *dev_priv = dev->dev_private;
5817 u32 val, cmd;
5818
5819 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5820 != dev_priv->cdclk_freq);
5821
5822 switch (cdclk) {
5823 case 333333:
5824 case 320000:
5825 case 266667:
5826 case 200000:
5827 break;
5828 default:
5829 MISSING_CASE(cdclk);
5830 return;
5831 }
5832
5833 /*
5834 * Specs are full of misinformation, but testing on actual
5835 * hardware has shown that we just need to write the desired
5836 * CCK divider into the Punit register.
5837 */
5838 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5839
5840 mutex_lock(&dev_priv->rps.hw_lock);
5841 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5842 val &= ~DSPFREQGUAR_MASK_CHV;
5843 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5844 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5845 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5846 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5847 50)) {
5848 DRM_ERROR("timed out waiting for CDclk change\n");
5849 }
5850 mutex_unlock(&dev_priv->rps.hw_lock);
5851
5852 intel_update_cdclk(dev);
5853 }
5854
5855 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5856 int max_pixclk)
5857 {
5858 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5859 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5860
5861 /*
5862 * Really only a few cases to deal with, as only 4 CDclks are supported:
5863 * 200MHz
5864 * 267MHz
5865 * 320/333MHz (depends on HPLL freq)
5866 * 400MHz (VLV only)
5867 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5868 * of the lower bin and adjust if needed.
5869 *
5870 * We seem to get an unstable or solid color picture at 200MHz.
5871 * Not sure what's wrong. For now use 200MHz only when all pipes
5872 * are off.
5873 */
5874 if (!IS_CHERRYVIEW(dev_priv) &&
5875 max_pixclk > freq_320*limit/100)
5876 return 400000;
5877 else if (max_pixclk > 266667*limit/100)
5878 return freq_320;
5879 else if (max_pixclk > 0)
5880 return 266667;
5881 else
5882 return 200000;
5883 }
5884
5885 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5886 int max_pixclk)
5887 {
5888 /*
5889 * FIXME:
5890 * - remove the guardband, it's not needed on BXT
5891 * - set 19.2MHz bypass frequency if there are no active pipes
5892 */
5893 if (max_pixclk > 576000*9/10)
5894 return 624000;
5895 else if (max_pixclk > 384000*9/10)
5896 return 576000;
5897 else if (max_pixclk > 288000*9/10)
5898 return 384000;
5899 else if (max_pixclk > 144000*9/10)
5900 return 288000;
5901 else
5902 return 144000;
5903 }
5904
5905 /* Compute the max pixel clock for new configuration. Uses atomic state if
5906 * that's non-NULL, look at current state otherwise. */
5907 static int intel_mode_max_pixclk(struct drm_device *dev,
5908 struct drm_atomic_state *state)
5909 {
5910 struct intel_crtc *intel_crtc;
5911 struct intel_crtc_state *crtc_state;
5912 int max_pixclk = 0;
5913
5914 for_each_intel_crtc(dev, intel_crtc) {
5915 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5916 if (IS_ERR(crtc_state))
5917 return PTR_ERR(crtc_state);
5918
5919 if (!crtc_state->base.enable)
5920 continue;
5921
5922 max_pixclk = max(max_pixclk,
5923 crtc_state->base.adjusted_mode.crtc_clock);
5924 }
5925
5926 return max_pixclk;
5927 }
5928
5929 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5930 {
5931 struct drm_device *dev = state->dev;
5932 struct drm_i915_private *dev_priv = dev->dev_private;
5933 int max_pixclk = intel_mode_max_pixclk(dev, state);
5934
5935 if (max_pixclk < 0)
5936 return max_pixclk;
5937
5938 to_intel_atomic_state(state)->cdclk =
5939 valleyview_calc_cdclk(dev_priv, max_pixclk);
5940
5941 return 0;
5942 }
5943
5944 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5945 {
5946 struct drm_device *dev = state->dev;
5947 struct drm_i915_private *dev_priv = dev->dev_private;
5948 int max_pixclk = intel_mode_max_pixclk(dev, state);
5949
5950 if (max_pixclk < 0)
5951 return max_pixclk;
5952
5953 to_intel_atomic_state(state)->cdclk =
5954 broxton_calc_cdclk(dev_priv, max_pixclk);
5955
5956 return 0;
5957 }
5958
5959 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5960 {
5961 unsigned int credits, default_credits;
5962
5963 if (IS_CHERRYVIEW(dev_priv))
5964 default_credits = PFI_CREDIT(12);
5965 else
5966 default_credits = PFI_CREDIT(8);
5967
5968 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5969 /* CHV suggested value is 31 or 63 */
5970 if (IS_CHERRYVIEW(dev_priv))
5971 credits = PFI_CREDIT_63;
5972 else
5973 credits = PFI_CREDIT(15);
5974 } else {
5975 credits = default_credits;
5976 }
5977
5978 /*
5979 * WA - write default credits before re-programming
5980 * FIXME: should we also set the resend bit here?
5981 */
5982 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5983 default_credits);
5984
5985 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5986 credits | PFI_CREDIT_RESEND);
5987
5988 /*
5989 * FIXME is this guaranteed to clear
5990 * immediately or should we poll for it?
5991 */
5992 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5993 }
5994
5995 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
5996 {
5997 struct drm_device *dev = old_state->dev;
5998 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
5999 struct drm_i915_private *dev_priv = dev->dev_private;
6000
6001 /*
6002 * FIXME: We can end up here with all power domains off, yet
6003 * with a CDCLK frequency other than the minimum. To account
6004 * for this take the PIPE-A power domain, which covers the HW
6005 * blocks needed for the following programming. This can be
6006 * removed once it's guaranteed that we get here either with
6007 * the minimum CDCLK set, or the required power domains
6008 * enabled.
6009 */
6010 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6011
6012 if (IS_CHERRYVIEW(dev))
6013 cherryview_set_cdclk(dev, req_cdclk);
6014 else
6015 valleyview_set_cdclk(dev, req_cdclk);
6016
6017 vlv_program_pfi_credits(dev_priv);
6018
6019 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6020 }
6021
6022 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6023 {
6024 struct drm_device *dev = crtc->dev;
6025 struct drm_i915_private *dev_priv = to_i915(dev);
6026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6027 struct intel_encoder *encoder;
6028 int pipe = intel_crtc->pipe;
6029 bool is_dsi;
6030
6031 if (WARN_ON(intel_crtc->active))
6032 return;
6033
6034 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6035
6036 if (!is_dsi) {
6037 if (IS_CHERRYVIEW(dev))
6038 chv_prepare_pll(intel_crtc, intel_crtc->config);
6039 else
6040 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6041 }
6042
6043 if (intel_crtc->config->has_dp_encoder)
6044 intel_dp_set_m_n(intel_crtc, M1_N1);
6045
6046 intel_set_pipe_timings(intel_crtc);
6047
6048 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6049 struct drm_i915_private *dev_priv = dev->dev_private;
6050
6051 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6052 I915_WRITE(CHV_CANVAS(pipe), 0);
6053 }
6054
6055 i9xx_set_pipeconf(intel_crtc);
6056
6057 intel_crtc->active = true;
6058
6059 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6060
6061 for_each_encoder_on_crtc(dev, crtc, encoder)
6062 if (encoder->pre_pll_enable)
6063 encoder->pre_pll_enable(encoder);
6064
6065 if (!is_dsi) {
6066 if (IS_CHERRYVIEW(dev))
6067 chv_enable_pll(intel_crtc, intel_crtc->config);
6068 else
6069 vlv_enable_pll(intel_crtc, intel_crtc->config);
6070 }
6071
6072 for_each_encoder_on_crtc(dev, crtc, encoder)
6073 if (encoder->pre_enable)
6074 encoder->pre_enable(encoder);
6075
6076 i9xx_pfit_enable(intel_crtc);
6077
6078 intel_crtc_load_lut(crtc);
6079
6080 intel_enable_pipe(intel_crtc);
6081
6082 assert_vblank_disabled(crtc);
6083 drm_crtc_vblank_on(crtc);
6084
6085 for_each_encoder_on_crtc(dev, crtc, encoder)
6086 encoder->enable(encoder);
6087 }
6088
6089 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6090 {
6091 struct drm_device *dev = crtc->base.dev;
6092 struct drm_i915_private *dev_priv = dev->dev_private;
6093
6094 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6095 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6096 }
6097
6098 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6099 {
6100 struct drm_device *dev = crtc->dev;
6101 struct drm_i915_private *dev_priv = to_i915(dev);
6102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6103 struct intel_encoder *encoder;
6104 int pipe = intel_crtc->pipe;
6105
6106 if (WARN_ON(intel_crtc->active))
6107 return;
6108
6109 i9xx_set_pll_dividers(intel_crtc);
6110
6111 if (intel_crtc->config->has_dp_encoder)
6112 intel_dp_set_m_n(intel_crtc, M1_N1);
6113
6114 intel_set_pipe_timings(intel_crtc);
6115
6116 i9xx_set_pipeconf(intel_crtc);
6117
6118 intel_crtc->active = true;
6119
6120 if (!IS_GEN2(dev))
6121 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6122
6123 for_each_encoder_on_crtc(dev, crtc, encoder)
6124 if (encoder->pre_enable)
6125 encoder->pre_enable(encoder);
6126
6127 i9xx_enable_pll(intel_crtc);
6128
6129 i9xx_pfit_enable(intel_crtc);
6130
6131 intel_crtc_load_lut(crtc);
6132
6133 intel_update_watermarks(crtc);
6134 intel_enable_pipe(intel_crtc);
6135
6136 assert_vblank_disabled(crtc);
6137 drm_crtc_vblank_on(crtc);
6138
6139 for_each_encoder_on_crtc(dev, crtc, encoder)
6140 encoder->enable(encoder);
6141 }
6142
6143 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6144 {
6145 struct drm_device *dev = crtc->base.dev;
6146 struct drm_i915_private *dev_priv = dev->dev_private;
6147
6148 if (!crtc->config->gmch_pfit.control)
6149 return;
6150
6151 assert_pipe_disabled(dev_priv, crtc->pipe);
6152
6153 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6154 I915_READ(PFIT_CONTROL));
6155 I915_WRITE(PFIT_CONTROL, 0);
6156 }
6157
6158 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6159 {
6160 struct drm_device *dev = crtc->dev;
6161 struct drm_i915_private *dev_priv = dev->dev_private;
6162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6163 struct intel_encoder *encoder;
6164 int pipe = intel_crtc->pipe;
6165
6166 /*
6167 * On gen2 planes are double buffered but the pipe isn't, so we must
6168 * wait for planes to fully turn off before disabling the pipe.
6169 * We also need to wait on all gmch platforms because of the
6170 * self-refresh mode constraint explained above.
6171 */
6172 intel_wait_for_vblank(dev, pipe);
6173
6174 for_each_encoder_on_crtc(dev, crtc, encoder)
6175 encoder->disable(encoder);
6176
6177 drm_crtc_vblank_off(crtc);
6178 assert_vblank_disabled(crtc);
6179
6180 intel_disable_pipe(intel_crtc);
6181
6182 i9xx_pfit_disable(intel_crtc);
6183
6184 for_each_encoder_on_crtc(dev, crtc, encoder)
6185 if (encoder->post_disable)
6186 encoder->post_disable(encoder);
6187
6188 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6189 if (IS_CHERRYVIEW(dev))
6190 chv_disable_pll(dev_priv, pipe);
6191 else if (IS_VALLEYVIEW(dev))
6192 vlv_disable_pll(dev_priv, pipe);
6193 else
6194 i9xx_disable_pll(intel_crtc);
6195 }
6196
6197 if (!IS_GEN2(dev))
6198 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6199
6200 intel_crtc->active = false;
6201 intel_update_watermarks(crtc);
6202 }
6203
6204 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6205 {
6206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6207 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6208 enum intel_display_power_domain domain;
6209 unsigned long domains;
6210
6211 if (!intel_crtc->active)
6212 return;
6213
6214 if (to_intel_plane_state(crtc->primary->state)->visible) {
6215 intel_crtc_wait_for_pending_flips(crtc);
6216 intel_pre_disable_primary(crtc);
6217 }
6218
6219 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6220 dev_priv->display.crtc_disable(crtc);
6221 intel_disable_shared_dpll(intel_crtc);
6222
6223 domains = intel_crtc->enabled_power_domains;
6224 for_each_power_domain(domain, domains)
6225 intel_display_power_put(dev_priv, domain);
6226 intel_crtc->enabled_power_domains = 0;
6227 }
6228
6229 /*
6230 * turn all crtc's off, but do not adjust state
6231 * This has to be paired with a call to intel_modeset_setup_hw_state.
6232 */
6233 int intel_display_suspend(struct drm_device *dev)
6234 {
6235 struct drm_mode_config *config = &dev->mode_config;
6236 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6237 struct drm_atomic_state *state;
6238 struct drm_crtc *crtc;
6239 unsigned crtc_mask = 0;
6240 int ret = 0;
6241
6242 if (WARN_ON(!ctx))
6243 return 0;
6244
6245 lockdep_assert_held(&ctx->ww_ctx);
6246 state = drm_atomic_state_alloc(dev);
6247 if (WARN_ON(!state))
6248 return -ENOMEM;
6249
6250 state->acquire_ctx = ctx;
6251 state->allow_modeset = true;
6252
6253 for_each_crtc(dev, crtc) {
6254 struct drm_crtc_state *crtc_state =
6255 drm_atomic_get_crtc_state(state, crtc);
6256
6257 ret = PTR_ERR_OR_ZERO(crtc_state);
6258 if (ret)
6259 goto free;
6260
6261 if (!crtc_state->active)
6262 continue;
6263
6264 crtc_state->active = false;
6265 crtc_mask |= 1 << drm_crtc_index(crtc);
6266 }
6267
6268 if (crtc_mask) {
6269 ret = drm_atomic_commit(state);
6270
6271 if (!ret) {
6272 for_each_crtc(dev, crtc)
6273 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6274 crtc->state->active = true;
6275
6276 return ret;
6277 }
6278 }
6279
6280 free:
6281 if (ret)
6282 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6283 drm_atomic_state_free(state);
6284 return ret;
6285 }
6286
6287 void intel_encoder_destroy(struct drm_encoder *encoder)
6288 {
6289 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6290
6291 drm_encoder_cleanup(encoder);
6292 kfree(intel_encoder);
6293 }
6294
6295 /* Cross check the actual hw state with our own modeset state tracking (and it's
6296 * internal consistency). */
6297 static void intel_connector_check_state(struct intel_connector *connector)
6298 {
6299 struct drm_crtc *crtc = connector->base.state->crtc;
6300
6301 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6302 connector->base.base.id,
6303 connector->base.name);
6304
6305 if (connector->get_hw_state(connector)) {
6306 struct drm_encoder *encoder = &connector->encoder->base;
6307 struct drm_connector_state *conn_state = connector->base.state;
6308
6309 I915_STATE_WARN(!crtc,
6310 "connector enabled without attached crtc\n");
6311
6312 if (!crtc)
6313 return;
6314
6315 I915_STATE_WARN(!crtc->state->active,
6316 "connector is active, but attached crtc isn't\n");
6317
6318 if (!encoder)
6319 return;
6320
6321 I915_STATE_WARN(conn_state->best_encoder != encoder,
6322 "atomic encoder doesn't match attached encoder\n");
6323
6324 I915_STATE_WARN(conn_state->crtc != encoder->crtc,
6325 "attached encoder crtc differs from connector crtc\n");
6326 } else {
6327 I915_STATE_WARN(crtc && crtc->state->active,
6328 "attached crtc is active, but connector isn't\n");
6329 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6330 "best encoder set without crtc!\n");
6331 }
6332 }
6333
6334 int intel_connector_init(struct intel_connector *connector)
6335 {
6336 struct drm_connector_state *connector_state;
6337
6338 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6339 if (!connector_state)
6340 return -ENOMEM;
6341
6342 connector->base.state = connector_state;
6343 return 0;
6344 }
6345
6346 struct intel_connector *intel_connector_alloc(void)
6347 {
6348 struct intel_connector *connector;
6349
6350 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6351 if (!connector)
6352 return NULL;
6353
6354 if (intel_connector_init(connector) < 0) {
6355 kfree(connector);
6356 return NULL;
6357 }
6358
6359 return connector;
6360 }
6361
6362 /* Simple connector->get_hw_state implementation for encoders that support only
6363 * one connector and no cloning and hence the encoder state determines the state
6364 * of the connector. */
6365 bool intel_connector_get_hw_state(struct intel_connector *connector)
6366 {
6367 enum pipe pipe = 0;
6368 struct intel_encoder *encoder = connector->encoder;
6369
6370 return encoder->get_hw_state(encoder, &pipe);
6371 }
6372
6373 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6374 {
6375 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6376 return crtc_state->fdi_lanes;
6377
6378 return 0;
6379 }
6380
6381 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6382 struct intel_crtc_state *pipe_config)
6383 {
6384 struct drm_atomic_state *state = pipe_config->base.state;
6385 struct intel_crtc *other_crtc;
6386 struct intel_crtc_state *other_crtc_state;
6387
6388 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6389 pipe_name(pipe), pipe_config->fdi_lanes);
6390 if (pipe_config->fdi_lanes > 4) {
6391 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6392 pipe_name(pipe), pipe_config->fdi_lanes);
6393 return -EINVAL;
6394 }
6395
6396 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6397 if (pipe_config->fdi_lanes > 2) {
6398 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6399 pipe_config->fdi_lanes);
6400 return -EINVAL;
6401 } else {
6402 return 0;
6403 }
6404 }
6405
6406 if (INTEL_INFO(dev)->num_pipes == 2)
6407 return 0;
6408
6409 /* Ivybridge 3 pipe is really complicated */
6410 switch (pipe) {
6411 case PIPE_A:
6412 return 0;
6413 case PIPE_B:
6414 if (pipe_config->fdi_lanes <= 2)
6415 return 0;
6416
6417 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6418 other_crtc_state =
6419 intel_atomic_get_crtc_state(state, other_crtc);
6420 if (IS_ERR(other_crtc_state))
6421 return PTR_ERR(other_crtc_state);
6422
6423 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6424 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6425 pipe_name(pipe), pipe_config->fdi_lanes);
6426 return -EINVAL;
6427 }
6428 return 0;
6429 case PIPE_C:
6430 if (pipe_config->fdi_lanes > 2) {
6431 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6432 pipe_name(pipe), pipe_config->fdi_lanes);
6433 return -EINVAL;
6434 }
6435
6436 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6437 other_crtc_state =
6438 intel_atomic_get_crtc_state(state, other_crtc);
6439 if (IS_ERR(other_crtc_state))
6440 return PTR_ERR(other_crtc_state);
6441
6442 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6443 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6444 return -EINVAL;
6445 }
6446 return 0;
6447 default:
6448 BUG();
6449 }
6450 }
6451
6452 #define RETRY 1
6453 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6454 struct intel_crtc_state *pipe_config)
6455 {
6456 struct drm_device *dev = intel_crtc->base.dev;
6457 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6458 int lane, link_bw, fdi_dotclock, ret;
6459 bool needs_recompute = false;
6460
6461 retry:
6462 /* FDI is a binary signal running at ~2.7GHz, encoding
6463 * each output octet as 10 bits. The actual frequency
6464 * is stored as a divider into a 100MHz clock, and the
6465 * mode pixel clock is stored in units of 1KHz.
6466 * Hence the bw of each lane in terms of the mode signal
6467 * is:
6468 */
6469 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6470
6471 fdi_dotclock = adjusted_mode->crtc_clock;
6472
6473 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6474 pipe_config->pipe_bpp);
6475
6476 pipe_config->fdi_lanes = lane;
6477
6478 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6479 link_bw, &pipe_config->fdi_m_n);
6480
6481 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6482 intel_crtc->pipe, pipe_config);
6483 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6484 pipe_config->pipe_bpp -= 2*3;
6485 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6486 pipe_config->pipe_bpp);
6487 needs_recompute = true;
6488 pipe_config->bw_constrained = true;
6489
6490 goto retry;
6491 }
6492
6493 if (needs_recompute)
6494 return RETRY;
6495
6496 return ret;
6497 }
6498
6499 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6500 struct intel_crtc_state *pipe_config)
6501 {
6502 if (pipe_config->pipe_bpp > 24)
6503 return false;
6504
6505 /* HSW can handle pixel rate up to cdclk? */
6506 if (IS_HASWELL(dev_priv->dev))
6507 return true;
6508
6509 /*
6510 * We compare against max which means we must take
6511 * the increased cdclk requirement into account when
6512 * calculating the new cdclk.
6513 *
6514 * Should measure whether using a lower cdclk w/o IPS
6515 */
6516 return ilk_pipe_pixel_rate(pipe_config) <=
6517 dev_priv->max_cdclk_freq * 95 / 100;
6518 }
6519
6520 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6521 struct intel_crtc_state *pipe_config)
6522 {
6523 struct drm_device *dev = crtc->base.dev;
6524 struct drm_i915_private *dev_priv = dev->dev_private;
6525
6526 pipe_config->ips_enabled = i915.enable_ips &&
6527 hsw_crtc_supports_ips(crtc) &&
6528 pipe_config_supports_ips(dev_priv, pipe_config);
6529 }
6530
6531 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6532 struct intel_crtc_state *pipe_config)
6533 {
6534 struct drm_device *dev = crtc->base.dev;
6535 struct drm_i915_private *dev_priv = dev->dev_private;
6536 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6537
6538 /* FIXME should check pixel clock limits on all platforms */
6539 if (INTEL_INFO(dev)->gen < 4) {
6540 int clock_limit = dev_priv->max_cdclk_freq;
6541
6542 /*
6543 * Enable pixel doubling when the dot clock
6544 * is > 90% of the (display) core speed.
6545 *
6546 * GDG double wide on either pipe,
6547 * otherwise pipe A only.
6548 */
6549 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6550 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6551 clock_limit *= 2;
6552 pipe_config->double_wide = true;
6553 }
6554
6555 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6556 return -EINVAL;
6557 }
6558
6559 /*
6560 * Pipe horizontal size must be even in:
6561 * - DVO ganged mode
6562 * - LVDS dual channel mode
6563 * - Double wide pipe
6564 */
6565 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6566 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6567 pipe_config->pipe_src_w &= ~1;
6568
6569 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6570 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6571 */
6572 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6573 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6574 return -EINVAL;
6575
6576 if (HAS_IPS(dev))
6577 hsw_compute_ips_config(crtc, pipe_config);
6578
6579 if (pipe_config->has_pch_encoder)
6580 return ironlake_fdi_compute_config(crtc, pipe_config);
6581
6582 return 0;
6583 }
6584
6585 static int skylake_get_display_clock_speed(struct drm_device *dev)
6586 {
6587 struct drm_i915_private *dev_priv = to_i915(dev);
6588 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6589 uint32_t cdctl = I915_READ(CDCLK_CTL);
6590 uint32_t linkrate;
6591
6592 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6593 return 24000; /* 24MHz is the cd freq with NSSC ref */
6594
6595 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6596 return 540000;
6597
6598 linkrate = (I915_READ(DPLL_CTRL1) &
6599 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6600
6601 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6602 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6603 /* vco 8640 */
6604 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6605 case CDCLK_FREQ_450_432:
6606 return 432000;
6607 case CDCLK_FREQ_337_308:
6608 return 308570;
6609 case CDCLK_FREQ_675_617:
6610 return 617140;
6611 default:
6612 WARN(1, "Unknown cd freq selection\n");
6613 }
6614 } else {
6615 /* vco 8100 */
6616 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6617 case CDCLK_FREQ_450_432:
6618 return 450000;
6619 case CDCLK_FREQ_337_308:
6620 return 337500;
6621 case CDCLK_FREQ_675_617:
6622 return 675000;
6623 default:
6624 WARN(1, "Unknown cd freq selection\n");
6625 }
6626 }
6627
6628 /* error case, do as if DPLL0 isn't enabled */
6629 return 24000;
6630 }
6631
6632 static int broxton_get_display_clock_speed(struct drm_device *dev)
6633 {
6634 struct drm_i915_private *dev_priv = to_i915(dev);
6635 uint32_t cdctl = I915_READ(CDCLK_CTL);
6636 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6637 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6638 int cdclk;
6639
6640 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6641 return 19200;
6642
6643 cdclk = 19200 * pll_ratio / 2;
6644
6645 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6646 case BXT_CDCLK_CD2X_DIV_SEL_1:
6647 return cdclk; /* 576MHz or 624MHz */
6648 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6649 return cdclk * 2 / 3; /* 384MHz */
6650 case BXT_CDCLK_CD2X_DIV_SEL_2:
6651 return cdclk / 2; /* 288MHz */
6652 case BXT_CDCLK_CD2X_DIV_SEL_4:
6653 return cdclk / 4; /* 144MHz */
6654 }
6655
6656 /* error case, do as if DE PLL isn't enabled */
6657 return 19200;
6658 }
6659
6660 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6661 {
6662 struct drm_i915_private *dev_priv = dev->dev_private;
6663 uint32_t lcpll = I915_READ(LCPLL_CTL);
6664 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6665
6666 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6667 return 800000;
6668 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6669 return 450000;
6670 else if (freq == LCPLL_CLK_FREQ_450)
6671 return 450000;
6672 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6673 return 540000;
6674 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6675 return 337500;
6676 else
6677 return 675000;
6678 }
6679
6680 static int haswell_get_display_clock_speed(struct drm_device *dev)
6681 {
6682 struct drm_i915_private *dev_priv = dev->dev_private;
6683 uint32_t lcpll = I915_READ(LCPLL_CTL);
6684 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6685
6686 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6687 return 800000;
6688 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6689 return 450000;
6690 else if (freq == LCPLL_CLK_FREQ_450)
6691 return 450000;
6692 else if (IS_HSW_ULT(dev))
6693 return 337500;
6694 else
6695 return 540000;
6696 }
6697
6698 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6699 {
6700 struct drm_i915_private *dev_priv = dev->dev_private;
6701 u32 val;
6702 int divider;
6703
6704 if (dev_priv->hpll_freq == 0)
6705 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6706
6707 mutex_lock(&dev_priv->sb_lock);
6708 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6709 mutex_unlock(&dev_priv->sb_lock);
6710
6711 divider = val & DISPLAY_FREQUENCY_VALUES;
6712
6713 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6714 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6715 "cdclk change in progress\n");
6716
6717 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6718 }
6719
6720 static int ilk_get_display_clock_speed(struct drm_device *dev)
6721 {
6722 return 450000;
6723 }
6724
6725 static int i945_get_display_clock_speed(struct drm_device *dev)
6726 {
6727 return 400000;
6728 }
6729
6730 static int i915_get_display_clock_speed(struct drm_device *dev)
6731 {
6732 return 333333;
6733 }
6734
6735 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6736 {
6737 return 200000;
6738 }
6739
6740 static int pnv_get_display_clock_speed(struct drm_device *dev)
6741 {
6742 u16 gcfgc = 0;
6743
6744 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6745
6746 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6747 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6748 return 266667;
6749 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6750 return 333333;
6751 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6752 return 444444;
6753 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6754 return 200000;
6755 default:
6756 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6757 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6758 return 133333;
6759 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6760 return 166667;
6761 }
6762 }
6763
6764 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6765 {
6766 u16 gcfgc = 0;
6767
6768 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6769
6770 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6771 return 133333;
6772 else {
6773 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6774 case GC_DISPLAY_CLOCK_333_MHZ:
6775 return 333333;
6776 default:
6777 case GC_DISPLAY_CLOCK_190_200_MHZ:
6778 return 190000;
6779 }
6780 }
6781 }
6782
6783 static int i865_get_display_clock_speed(struct drm_device *dev)
6784 {
6785 return 266667;
6786 }
6787
6788 static int i85x_get_display_clock_speed(struct drm_device *dev)
6789 {
6790 u16 hpllcc = 0;
6791
6792 /*
6793 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6794 * encoding is different :(
6795 * FIXME is this the right way to detect 852GM/852GMV?
6796 */
6797 if (dev->pdev->revision == 0x1)
6798 return 133333;
6799
6800 pci_bus_read_config_word(dev->pdev->bus,
6801 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6802
6803 /* Assume that the hardware is in the high speed state. This
6804 * should be the default.
6805 */
6806 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6807 case GC_CLOCK_133_200:
6808 case GC_CLOCK_133_200_2:
6809 case GC_CLOCK_100_200:
6810 return 200000;
6811 case GC_CLOCK_166_250:
6812 return 250000;
6813 case GC_CLOCK_100_133:
6814 return 133333;
6815 case GC_CLOCK_133_266:
6816 case GC_CLOCK_133_266_2:
6817 case GC_CLOCK_166_266:
6818 return 266667;
6819 }
6820
6821 /* Shouldn't happen */
6822 return 0;
6823 }
6824
6825 static int i830_get_display_clock_speed(struct drm_device *dev)
6826 {
6827 return 133333;
6828 }
6829
6830 static unsigned int intel_hpll_vco(struct drm_device *dev)
6831 {
6832 struct drm_i915_private *dev_priv = dev->dev_private;
6833 static const unsigned int blb_vco[8] = {
6834 [0] = 3200000,
6835 [1] = 4000000,
6836 [2] = 5333333,
6837 [3] = 4800000,
6838 [4] = 6400000,
6839 };
6840 static const unsigned int pnv_vco[8] = {
6841 [0] = 3200000,
6842 [1] = 4000000,
6843 [2] = 5333333,
6844 [3] = 4800000,
6845 [4] = 2666667,
6846 };
6847 static const unsigned int cl_vco[8] = {
6848 [0] = 3200000,
6849 [1] = 4000000,
6850 [2] = 5333333,
6851 [3] = 6400000,
6852 [4] = 3333333,
6853 [5] = 3566667,
6854 [6] = 4266667,
6855 };
6856 static const unsigned int elk_vco[8] = {
6857 [0] = 3200000,
6858 [1] = 4000000,
6859 [2] = 5333333,
6860 [3] = 4800000,
6861 };
6862 static const unsigned int ctg_vco[8] = {
6863 [0] = 3200000,
6864 [1] = 4000000,
6865 [2] = 5333333,
6866 [3] = 6400000,
6867 [4] = 2666667,
6868 [5] = 4266667,
6869 };
6870 const unsigned int *vco_table;
6871 unsigned int vco;
6872 uint8_t tmp = 0;
6873
6874 /* FIXME other chipsets? */
6875 if (IS_GM45(dev))
6876 vco_table = ctg_vco;
6877 else if (IS_G4X(dev))
6878 vco_table = elk_vco;
6879 else if (IS_CRESTLINE(dev))
6880 vco_table = cl_vco;
6881 else if (IS_PINEVIEW(dev))
6882 vco_table = pnv_vco;
6883 else if (IS_G33(dev))
6884 vco_table = blb_vco;
6885 else
6886 return 0;
6887
6888 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6889
6890 vco = vco_table[tmp & 0x7];
6891 if (vco == 0)
6892 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6893 else
6894 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6895
6896 return vco;
6897 }
6898
6899 static int gm45_get_display_clock_speed(struct drm_device *dev)
6900 {
6901 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6902 uint16_t tmp = 0;
6903
6904 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6905
6906 cdclk_sel = (tmp >> 12) & 0x1;
6907
6908 switch (vco) {
6909 case 2666667:
6910 case 4000000:
6911 case 5333333:
6912 return cdclk_sel ? 333333 : 222222;
6913 case 3200000:
6914 return cdclk_sel ? 320000 : 228571;
6915 default:
6916 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6917 return 222222;
6918 }
6919 }
6920
6921 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6922 {
6923 static const uint8_t div_3200[] = { 16, 10, 8 };
6924 static const uint8_t div_4000[] = { 20, 12, 10 };
6925 static const uint8_t div_5333[] = { 24, 16, 14 };
6926 const uint8_t *div_table;
6927 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6928 uint16_t tmp = 0;
6929
6930 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6931
6932 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6933
6934 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6935 goto fail;
6936
6937 switch (vco) {
6938 case 3200000:
6939 div_table = div_3200;
6940 break;
6941 case 4000000:
6942 div_table = div_4000;
6943 break;
6944 case 5333333:
6945 div_table = div_5333;
6946 break;
6947 default:
6948 goto fail;
6949 }
6950
6951 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6952
6953 fail:
6954 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6955 return 200000;
6956 }
6957
6958 static int g33_get_display_clock_speed(struct drm_device *dev)
6959 {
6960 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6961 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6962 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6963 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6964 const uint8_t *div_table;
6965 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6966 uint16_t tmp = 0;
6967
6968 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6969
6970 cdclk_sel = (tmp >> 4) & 0x7;
6971
6972 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6973 goto fail;
6974
6975 switch (vco) {
6976 case 3200000:
6977 div_table = div_3200;
6978 break;
6979 case 4000000:
6980 div_table = div_4000;
6981 break;
6982 case 4800000:
6983 div_table = div_4800;
6984 break;
6985 case 5333333:
6986 div_table = div_5333;
6987 break;
6988 default:
6989 goto fail;
6990 }
6991
6992 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6993
6994 fail:
6995 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6996 return 190476;
6997 }
6998
6999 static void
7000 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7001 {
7002 while (*num > DATA_LINK_M_N_MASK ||
7003 *den > DATA_LINK_M_N_MASK) {
7004 *num >>= 1;
7005 *den >>= 1;
7006 }
7007 }
7008
7009 static void compute_m_n(unsigned int m, unsigned int n,
7010 uint32_t *ret_m, uint32_t *ret_n)
7011 {
7012 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7013 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7014 intel_reduce_m_n_ratio(ret_m, ret_n);
7015 }
7016
7017 void
7018 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7019 int pixel_clock, int link_clock,
7020 struct intel_link_m_n *m_n)
7021 {
7022 m_n->tu = 64;
7023
7024 compute_m_n(bits_per_pixel * pixel_clock,
7025 link_clock * nlanes * 8,
7026 &m_n->gmch_m, &m_n->gmch_n);
7027
7028 compute_m_n(pixel_clock, link_clock,
7029 &m_n->link_m, &m_n->link_n);
7030 }
7031
7032 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7033 {
7034 if (i915.panel_use_ssc >= 0)
7035 return i915.panel_use_ssc != 0;
7036 return dev_priv->vbt.lvds_use_ssc
7037 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7038 }
7039
7040 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7041 int num_connectors)
7042 {
7043 struct drm_device *dev = crtc_state->base.crtc->dev;
7044 struct drm_i915_private *dev_priv = dev->dev_private;
7045 int refclk;
7046
7047 WARN_ON(!crtc_state->base.state);
7048
7049 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7050 refclk = 100000;
7051 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7052 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7053 refclk = dev_priv->vbt.lvds_ssc_freq;
7054 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7055 } else if (!IS_GEN2(dev)) {
7056 refclk = 96000;
7057 } else {
7058 refclk = 48000;
7059 }
7060
7061 return refclk;
7062 }
7063
7064 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7065 {
7066 return (1 << dpll->n) << 16 | dpll->m2;
7067 }
7068
7069 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7070 {
7071 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7072 }
7073
7074 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7075 struct intel_crtc_state *crtc_state,
7076 intel_clock_t *reduced_clock)
7077 {
7078 struct drm_device *dev = crtc->base.dev;
7079 u32 fp, fp2 = 0;
7080
7081 if (IS_PINEVIEW(dev)) {
7082 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7083 if (reduced_clock)
7084 fp2 = pnv_dpll_compute_fp(reduced_clock);
7085 } else {
7086 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7087 if (reduced_clock)
7088 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7089 }
7090
7091 crtc_state->dpll_hw_state.fp0 = fp;
7092
7093 crtc->lowfreq_avail = false;
7094 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7095 reduced_clock) {
7096 crtc_state->dpll_hw_state.fp1 = fp2;
7097 crtc->lowfreq_avail = true;
7098 } else {
7099 crtc_state->dpll_hw_state.fp1 = fp;
7100 }
7101 }
7102
7103 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7104 pipe)
7105 {
7106 u32 reg_val;
7107
7108 /*
7109 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7110 * and set it to a reasonable value instead.
7111 */
7112 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7113 reg_val &= 0xffffff00;
7114 reg_val |= 0x00000030;
7115 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7116
7117 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7118 reg_val &= 0x8cffffff;
7119 reg_val = 0x8c000000;
7120 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7121
7122 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7123 reg_val &= 0xffffff00;
7124 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7125
7126 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7127 reg_val &= 0x00ffffff;
7128 reg_val |= 0xb0000000;
7129 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7130 }
7131
7132 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7133 struct intel_link_m_n *m_n)
7134 {
7135 struct drm_device *dev = crtc->base.dev;
7136 struct drm_i915_private *dev_priv = dev->dev_private;
7137 int pipe = crtc->pipe;
7138
7139 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7140 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7141 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7142 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7143 }
7144
7145 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7146 struct intel_link_m_n *m_n,
7147 struct intel_link_m_n *m2_n2)
7148 {
7149 struct drm_device *dev = crtc->base.dev;
7150 struct drm_i915_private *dev_priv = dev->dev_private;
7151 int pipe = crtc->pipe;
7152 enum transcoder transcoder = crtc->config->cpu_transcoder;
7153
7154 if (INTEL_INFO(dev)->gen >= 5) {
7155 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7156 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7157 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7158 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7159 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7160 * for gen < 8) and if DRRS is supported (to make sure the
7161 * registers are not unnecessarily accessed).
7162 */
7163 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7164 crtc->config->has_drrs) {
7165 I915_WRITE(PIPE_DATA_M2(transcoder),
7166 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7167 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7168 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7169 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7170 }
7171 } else {
7172 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7173 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7174 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7175 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7176 }
7177 }
7178
7179 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7180 {
7181 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7182
7183 if (m_n == M1_N1) {
7184 dp_m_n = &crtc->config->dp_m_n;
7185 dp_m2_n2 = &crtc->config->dp_m2_n2;
7186 } else if (m_n == M2_N2) {
7187
7188 /*
7189 * M2_N2 registers are not supported. Hence m2_n2 divider value
7190 * needs to be programmed into M1_N1.
7191 */
7192 dp_m_n = &crtc->config->dp_m2_n2;
7193 } else {
7194 DRM_ERROR("Unsupported divider value\n");
7195 return;
7196 }
7197
7198 if (crtc->config->has_pch_encoder)
7199 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7200 else
7201 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7202 }
7203
7204 static void vlv_compute_dpll(struct intel_crtc *crtc,
7205 struct intel_crtc_state *pipe_config)
7206 {
7207 u32 dpll, dpll_md;
7208
7209 /*
7210 * Enable DPIO clock input. We should never disable the reference
7211 * clock for pipe B, since VGA hotplug / manual detection depends
7212 * on it.
7213 */
7214 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7215 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7216 /* We should never disable this, set it here for state tracking */
7217 if (crtc->pipe == PIPE_B)
7218 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7219 dpll |= DPLL_VCO_ENABLE;
7220 pipe_config->dpll_hw_state.dpll = dpll;
7221
7222 dpll_md = (pipe_config->pixel_multiplier - 1)
7223 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7224 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7225 }
7226
7227 static void vlv_prepare_pll(struct intel_crtc *crtc,
7228 const struct intel_crtc_state *pipe_config)
7229 {
7230 struct drm_device *dev = crtc->base.dev;
7231 struct drm_i915_private *dev_priv = dev->dev_private;
7232 int pipe = crtc->pipe;
7233 u32 mdiv;
7234 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7235 u32 coreclk, reg_val;
7236
7237 mutex_lock(&dev_priv->sb_lock);
7238
7239 bestn = pipe_config->dpll.n;
7240 bestm1 = pipe_config->dpll.m1;
7241 bestm2 = pipe_config->dpll.m2;
7242 bestp1 = pipe_config->dpll.p1;
7243 bestp2 = pipe_config->dpll.p2;
7244
7245 /* See eDP HDMI DPIO driver vbios notes doc */
7246
7247 /* PLL B needs special handling */
7248 if (pipe == PIPE_B)
7249 vlv_pllb_recal_opamp(dev_priv, pipe);
7250
7251 /* Set up Tx target for periodic Rcomp update */
7252 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7253
7254 /* Disable target IRef on PLL */
7255 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7256 reg_val &= 0x00ffffff;
7257 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7258
7259 /* Disable fast lock */
7260 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7261
7262 /* Set idtafcrecal before PLL is enabled */
7263 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7264 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7265 mdiv |= ((bestn << DPIO_N_SHIFT));
7266 mdiv |= (1 << DPIO_K_SHIFT);
7267
7268 /*
7269 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7270 * but we don't support that).
7271 * Note: don't use the DAC post divider as it seems unstable.
7272 */
7273 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7274 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7275
7276 mdiv |= DPIO_ENABLE_CALIBRATION;
7277 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7278
7279 /* Set HBR and RBR LPF coefficients */
7280 if (pipe_config->port_clock == 162000 ||
7281 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7282 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7283 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7284 0x009f0003);
7285 else
7286 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7287 0x00d0000f);
7288
7289 if (pipe_config->has_dp_encoder) {
7290 /* Use SSC source */
7291 if (pipe == PIPE_A)
7292 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7293 0x0df40000);
7294 else
7295 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7296 0x0df70000);
7297 } else { /* HDMI or VGA */
7298 /* Use bend source */
7299 if (pipe == PIPE_A)
7300 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7301 0x0df70000);
7302 else
7303 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7304 0x0df40000);
7305 }
7306
7307 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7308 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7309 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7310 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7311 coreclk |= 0x01000000;
7312 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7313
7314 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7315 mutex_unlock(&dev_priv->sb_lock);
7316 }
7317
7318 static void chv_compute_dpll(struct intel_crtc *crtc,
7319 struct intel_crtc_state *pipe_config)
7320 {
7321 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7322 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7323 DPLL_VCO_ENABLE;
7324 if (crtc->pipe != PIPE_A)
7325 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7326
7327 pipe_config->dpll_hw_state.dpll_md =
7328 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7329 }
7330
7331 static void chv_prepare_pll(struct intel_crtc *crtc,
7332 const struct intel_crtc_state *pipe_config)
7333 {
7334 struct drm_device *dev = crtc->base.dev;
7335 struct drm_i915_private *dev_priv = dev->dev_private;
7336 int pipe = crtc->pipe;
7337 int dpll_reg = DPLL(crtc->pipe);
7338 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7339 u32 loopfilter, tribuf_calcntr;
7340 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7341 u32 dpio_val;
7342 int vco;
7343
7344 bestn = pipe_config->dpll.n;
7345 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7346 bestm1 = pipe_config->dpll.m1;
7347 bestm2 = pipe_config->dpll.m2 >> 22;
7348 bestp1 = pipe_config->dpll.p1;
7349 bestp2 = pipe_config->dpll.p2;
7350 vco = pipe_config->dpll.vco;
7351 dpio_val = 0;
7352 loopfilter = 0;
7353
7354 /*
7355 * Enable Refclk and SSC
7356 */
7357 I915_WRITE(dpll_reg,
7358 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7359
7360 mutex_lock(&dev_priv->sb_lock);
7361
7362 /* p1 and p2 divider */
7363 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7364 5 << DPIO_CHV_S1_DIV_SHIFT |
7365 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7366 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7367 1 << DPIO_CHV_K_DIV_SHIFT);
7368
7369 /* Feedback post-divider - m2 */
7370 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7371
7372 /* Feedback refclk divider - n and m1 */
7373 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7374 DPIO_CHV_M1_DIV_BY_2 |
7375 1 << DPIO_CHV_N_DIV_SHIFT);
7376
7377 /* M2 fraction division */
7378 if (bestm2_frac)
7379 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7380
7381 /* M2 fraction division enable */
7382 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7383 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7384 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7385 if (bestm2_frac)
7386 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7387 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7388
7389 /* Program digital lock detect threshold */
7390 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7391 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7392 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7393 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7394 if (!bestm2_frac)
7395 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7396 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7397
7398 /* Loop filter */
7399 if (vco == 5400000) {
7400 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7401 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7402 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7403 tribuf_calcntr = 0x9;
7404 } else if (vco <= 6200000) {
7405 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7406 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7407 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7408 tribuf_calcntr = 0x9;
7409 } else if (vco <= 6480000) {
7410 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7411 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7412 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7413 tribuf_calcntr = 0x8;
7414 } else {
7415 /* Not supported. Apply the same limits as in the max case */
7416 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7417 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7418 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7419 tribuf_calcntr = 0;
7420 }
7421 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7422
7423 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7424 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7425 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7426 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7427
7428 /* AFC Recal */
7429 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7430 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7431 DPIO_AFC_RECAL);
7432
7433 mutex_unlock(&dev_priv->sb_lock);
7434 }
7435
7436 /**
7437 * vlv_force_pll_on - forcibly enable just the PLL
7438 * @dev_priv: i915 private structure
7439 * @pipe: pipe PLL to enable
7440 * @dpll: PLL configuration
7441 *
7442 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7443 * in cases where we need the PLL enabled even when @pipe is not going to
7444 * be enabled.
7445 */
7446 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7447 const struct dpll *dpll)
7448 {
7449 struct intel_crtc *crtc =
7450 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7451 struct intel_crtc_state pipe_config = {
7452 .base.crtc = &crtc->base,
7453 .pixel_multiplier = 1,
7454 .dpll = *dpll,
7455 };
7456
7457 if (IS_CHERRYVIEW(dev)) {
7458 chv_compute_dpll(crtc, &pipe_config);
7459 chv_prepare_pll(crtc, &pipe_config);
7460 chv_enable_pll(crtc, &pipe_config);
7461 } else {
7462 vlv_compute_dpll(crtc, &pipe_config);
7463 vlv_prepare_pll(crtc, &pipe_config);
7464 vlv_enable_pll(crtc, &pipe_config);
7465 }
7466 }
7467
7468 /**
7469 * vlv_force_pll_off - forcibly disable just the PLL
7470 * @dev_priv: i915 private structure
7471 * @pipe: pipe PLL to disable
7472 *
7473 * Disable the PLL for @pipe. To be used in cases where we need
7474 * the PLL enabled even when @pipe is not going to be enabled.
7475 */
7476 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7477 {
7478 if (IS_CHERRYVIEW(dev))
7479 chv_disable_pll(to_i915(dev), pipe);
7480 else
7481 vlv_disable_pll(to_i915(dev), pipe);
7482 }
7483
7484 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7485 struct intel_crtc_state *crtc_state,
7486 intel_clock_t *reduced_clock,
7487 int num_connectors)
7488 {
7489 struct drm_device *dev = crtc->base.dev;
7490 struct drm_i915_private *dev_priv = dev->dev_private;
7491 u32 dpll;
7492 bool is_sdvo;
7493 struct dpll *clock = &crtc_state->dpll;
7494
7495 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7496
7497 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7498 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7499
7500 dpll = DPLL_VGA_MODE_DIS;
7501
7502 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7503 dpll |= DPLLB_MODE_LVDS;
7504 else
7505 dpll |= DPLLB_MODE_DAC_SERIAL;
7506
7507 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7508 dpll |= (crtc_state->pixel_multiplier - 1)
7509 << SDVO_MULTIPLIER_SHIFT_HIRES;
7510 }
7511
7512 if (is_sdvo)
7513 dpll |= DPLL_SDVO_HIGH_SPEED;
7514
7515 if (crtc_state->has_dp_encoder)
7516 dpll |= DPLL_SDVO_HIGH_SPEED;
7517
7518 /* compute bitmask from p1 value */
7519 if (IS_PINEVIEW(dev))
7520 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7521 else {
7522 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7523 if (IS_G4X(dev) && reduced_clock)
7524 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7525 }
7526 switch (clock->p2) {
7527 case 5:
7528 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7529 break;
7530 case 7:
7531 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7532 break;
7533 case 10:
7534 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7535 break;
7536 case 14:
7537 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7538 break;
7539 }
7540 if (INTEL_INFO(dev)->gen >= 4)
7541 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7542
7543 if (crtc_state->sdvo_tv_clock)
7544 dpll |= PLL_REF_INPUT_TVCLKINBC;
7545 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7546 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7547 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7548 else
7549 dpll |= PLL_REF_INPUT_DREFCLK;
7550
7551 dpll |= DPLL_VCO_ENABLE;
7552 crtc_state->dpll_hw_state.dpll = dpll;
7553
7554 if (INTEL_INFO(dev)->gen >= 4) {
7555 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7556 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7557 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7558 }
7559 }
7560
7561 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7562 struct intel_crtc_state *crtc_state,
7563 intel_clock_t *reduced_clock,
7564 int num_connectors)
7565 {
7566 struct drm_device *dev = crtc->base.dev;
7567 struct drm_i915_private *dev_priv = dev->dev_private;
7568 u32 dpll;
7569 struct dpll *clock = &crtc_state->dpll;
7570
7571 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7572
7573 dpll = DPLL_VGA_MODE_DIS;
7574
7575 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7576 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7577 } else {
7578 if (clock->p1 == 2)
7579 dpll |= PLL_P1_DIVIDE_BY_TWO;
7580 else
7581 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7582 if (clock->p2 == 4)
7583 dpll |= PLL_P2_DIVIDE_BY_4;
7584 }
7585
7586 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7587 dpll |= DPLL_DVO_2X_MODE;
7588
7589 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7590 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7591 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7592 else
7593 dpll |= PLL_REF_INPUT_DREFCLK;
7594
7595 dpll |= DPLL_VCO_ENABLE;
7596 crtc_state->dpll_hw_state.dpll = dpll;
7597 }
7598
7599 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7600 {
7601 struct drm_device *dev = intel_crtc->base.dev;
7602 struct drm_i915_private *dev_priv = dev->dev_private;
7603 enum pipe pipe = intel_crtc->pipe;
7604 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7605 struct drm_display_mode *adjusted_mode =
7606 &intel_crtc->config->base.adjusted_mode;
7607 uint32_t crtc_vtotal, crtc_vblank_end;
7608 int vsyncshift = 0;
7609
7610 /* We need to be careful not to changed the adjusted mode, for otherwise
7611 * the hw state checker will get angry at the mismatch. */
7612 crtc_vtotal = adjusted_mode->crtc_vtotal;
7613 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7614
7615 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7616 /* the chip adds 2 halflines automatically */
7617 crtc_vtotal -= 1;
7618 crtc_vblank_end -= 1;
7619
7620 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7621 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7622 else
7623 vsyncshift = adjusted_mode->crtc_hsync_start -
7624 adjusted_mode->crtc_htotal / 2;
7625 if (vsyncshift < 0)
7626 vsyncshift += adjusted_mode->crtc_htotal;
7627 }
7628
7629 if (INTEL_INFO(dev)->gen > 3)
7630 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7631
7632 I915_WRITE(HTOTAL(cpu_transcoder),
7633 (adjusted_mode->crtc_hdisplay - 1) |
7634 ((adjusted_mode->crtc_htotal - 1) << 16));
7635 I915_WRITE(HBLANK(cpu_transcoder),
7636 (adjusted_mode->crtc_hblank_start - 1) |
7637 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7638 I915_WRITE(HSYNC(cpu_transcoder),
7639 (adjusted_mode->crtc_hsync_start - 1) |
7640 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7641
7642 I915_WRITE(VTOTAL(cpu_transcoder),
7643 (adjusted_mode->crtc_vdisplay - 1) |
7644 ((crtc_vtotal - 1) << 16));
7645 I915_WRITE(VBLANK(cpu_transcoder),
7646 (adjusted_mode->crtc_vblank_start - 1) |
7647 ((crtc_vblank_end - 1) << 16));
7648 I915_WRITE(VSYNC(cpu_transcoder),
7649 (adjusted_mode->crtc_vsync_start - 1) |
7650 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7651
7652 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7653 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7654 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7655 * bits. */
7656 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7657 (pipe == PIPE_B || pipe == PIPE_C))
7658 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7659
7660 /* pipesrc controls the size that is scaled from, which should
7661 * always be the user's requested size.
7662 */
7663 I915_WRITE(PIPESRC(pipe),
7664 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7665 (intel_crtc->config->pipe_src_h - 1));
7666 }
7667
7668 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7669 struct intel_crtc_state *pipe_config)
7670 {
7671 struct drm_device *dev = crtc->base.dev;
7672 struct drm_i915_private *dev_priv = dev->dev_private;
7673 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7674 uint32_t tmp;
7675
7676 tmp = I915_READ(HTOTAL(cpu_transcoder));
7677 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7678 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7679 tmp = I915_READ(HBLANK(cpu_transcoder));
7680 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7681 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7682 tmp = I915_READ(HSYNC(cpu_transcoder));
7683 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7684 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7685
7686 tmp = I915_READ(VTOTAL(cpu_transcoder));
7687 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7688 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7689 tmp = I915_READ(VBLANK(cpu_transcoder));
7690 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7691 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7692 tmp = I915_READ(VSYNC(cpu_transcoder));
7693 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7694 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7695
7696 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7697 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7698 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7699 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7700 }
7701
7702 tmp = I915_READ(PIPESRC(crtc->pipe));
7703 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7704 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7705
7706 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7707 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7708 }
7709
7710 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7711 struct intel_crtc_state *pipe_config)
7712 {
7713 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7714 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7715 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7716 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7717
7718 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7719 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7720 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7721 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7722
7723 mode->flags = pipe_config->base.adjusted_mode.flags;
7724 mode->type = DRM_MODE_TYPE_DRIVER;
7725
7726 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7727 mode->flags |= pipe_config->base.adjusted_mode.flags;
7728
7729 mode->hsync = drm_mode_hsync(mode);
7730 mode->vrefresh = drm_mode_vrefresh(mode);
7731 drm_mode_set_name(mode);
7732 }
7733
7734 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7735 {
7736 struct drm_device *dev = intel_crtc->base.dev;
7737 struct drm_i915_private *dev_priv = dev->dev_private;
7738 uint32_t pipeconf;
7739
7740 pipeconf = 0;
7741
7742 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7743 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7744 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7745
7746 if (intel_crtc->config->double_wide)
7747 pipeconf |= PIPECONF_DOUBLE_WIDE;
7748
7749 /* only g4x and later have fancy bpc/dither controls */
7750 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7751 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7752 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7753 pipeconf |= PIPECONF_DITHER_EN |
7754 PIPECONF_DITHER_TYPE_SP;
7755
7756 switch (intel_crtc->config->pipe_bpp) {
7757 case 18:
7758 pipeconf |= PIPECONF_6BPC;
7759 break;
7760 case 24:
7761 pipeconf |= PIPECONF_8BPC;
7762 break;
7763 case 30:
7764 pipeconf |= PIPECONF_10BPC;
7765 break;
7766 default:
7767 /* Case prevented by intel_choose_pipe_bpp_dither. */
7768 BUG();
7769 }
7770 }
7771
7772 if (HAS_PIPE_CXSR(dev)) {
7773 if (intel_crtc->lowfreq_avail) {
7774 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7775 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7776 } else {
7777 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7778 }
7779 }
7780
7781 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7782 if (INTEL_INFO(dev)->gen < 4 ||
7783 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7784 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7785 else
7786 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7787 } else
7788 pipeconf |= PIPECONF_PROGRESSIVE;
7789
7790 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7791 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7792
7793 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7794 POSTING_READ(PIPECONF(intel_crtc->pipe));
7795 }
7796
7797 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7798 struct intel_crtc_state *crtc_state)
7799 {
7800 struct drm_device *dev = crtc->base.dev;
7801 struct drm_i915_private *dev_priv = dev->dev_private;
7802 int refclk, num_connectors = 0;
7803 intel_clock_t clock;
7804 bool ok;
7805 bool is_dsi = false;
7806 struct intel_encoder *encoder;
7807 const intel_limit_t *limit;
7808 struct drm_atomic_state *state = crtc_state->base.state;
7809 struct drm_connector *connector;
7810 struct drm_connector_state *connector_state;
7811 int i;
7812
7813 memset(&crtc_state->dpll_hw_state, 0,
7814 sizeof(crtc_state->dpll_hw_state));
7815
7816 for_each_connector_in_state(state, connector, connector_state, i) {
7817 if (connector_state->crtc != &crtc->base)
7818 continue;
7819
7820 encoder = to_intel_encoder(connector_state->best_encoder);
7821
7822 switch (encoder->type) {
7823 case INTEL_OUTPUT_DSI:
7824 is_dsi = true;
7825 break;
7826 default:
7827 break;
7828 }
7829
7830 num_connectors++;
7831 }
7832
7833 if (is_dsi)
7834 return 0;
7835
7836 if (!crtc_state->clock_set) {
7837 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7838
7839 /*
7840 * Returns a set of divisors for the desired target clock with
7841 * the given refclk, or FALSE. The returned values represent
7842 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7843 * 2) / p1 / p2.
7844 */
7845 limit = intel_limit(crtc_state, refclk);
7846 ok = dev_priv->display.find_dpll(limit, crtc_state,
7847 crtc_state->port_clock,
7848 refclk, NULL, &clock);
7849 if (!ok) {
7850 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7851 return -EINVAL;
7852 }
7853
7854 /* Compat-code for transition, will disappear. */
7855 crtc_state->dpll.n = clock.n;
7856 crtc_state->dpll.m1 = clock.m1;
7857 crtc_state->dpll.m2 = clock.m2;
7858 crtc_state->dpll.p1 = clock.p1;
7859 crtc_state->dpll.p2 = clock.p2;
7860 }
7861
7862 if (IS_GEN2(dev)) {
7863 i8xx_compute_dpll(crtc, crtc_state, NULL,
7864 num_connectors);
7865 } else if (IS_CHERRYVIEW(dev)) {
7866 chv_compute_dpll(crtc, crtc_state);
7867 } else if (IS_VALLEYVIEW(dev)) {
7868 vlv_compute_dpll(crtc, crtc_state);
7869 } else {
7870 i9xx_compute_dpll(crtc, crtc_state, NULL,
7871 num_connectors);
7872 }
7873
7874 return 0;
7875 }
7876
7877 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7878 struct intel_crtc_state *pipe_config)
7879 {
7880 struct drm_device *dev = crtc->base.dev;
7881 struct drm_i915_private *dev_priv = dev->dev_private;
7882 uint32_t tmp;
7883
7884 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7885 return;
7886
7887 tmp = I915_READ(PFIT_CONTROL);
7888 if (!(tmp & PFIT_ENABLE))
7889 return;
7890
7891 /* Check whether the pfit is attached to our pipe. */
7892 if (INTEL_INFO(dev)->gen < 4) {
7893 if (crtc->pipe != PIPE_B)
7894 return;
7895 } else {
7896 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7897 return;
7898 }
7899
7900 pipe_config->gmch_pfit.control = tmp;
7901 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7902 if (INTEL_INFO(dev)->gen < 5)
7903 pipe_config->gmch_pfit.lvds_border_bits =
7904 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7905 }
7906
7907 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7908 struct intel_crtc_state *pipe_config)
7909 {
7910 struct drm_device *dev = crtc->base.dev;
7911 struct drm_i915_private *dev_priv = dev->dev_private;
7912 int pipe = pipe_config->cpu_transcoder;
7913 intel_clock_t clock;
7914 u32 mdiv;
7915 int refclk = 100000;
7916
7917 /* In case of MIPI DPLL will not even be used */
7918 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7919 return;
7920
7921 mutex_lock(&dev_priv->sb_lock);
7922 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7923 mutex_unlock(&dev_priv->sb_lock);
7924
7925 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7926 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7927 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7928 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7929 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7930
7931 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7932 }
7933
7934 static void
7935 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7936 struct intel_initial_plane_config *plane_config)
7937 {
7938 struct drm_device *dev = crtc->base.dev;
7939 struct drm_i915_private *dev_priv = dev->dev_private;
7940 u32 val, base, offset;
7941 int pipe = crtc->pipe, plane = crtc->plane;
7942 int fourcc, pixel_format;
7943 unsigned int aligned_height;
7944 struct drm_framebuffer *fb;
7945 struct intel_framebuffer *intel_fb;
7946
7947 val = I915_READ(DSPCNTR(plane));
7948 if (!(val & DISPLAY_PLANE_ENABLE))
7949 return;
7950
7951 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7952 if (!intel_fb) {
7953 DRM_DEBUG_KMS("failed to alloc fb\n");
7954 return;
7955 }
7956
7957 fb = &intel_fb->base;
7958
7959 if (INTEL_INFO(dev)->gen >= 4) {
7960 if (val & DISPPLANE_TILED) {
7961 plane_config->tiling = I915_TILING_X;
7962 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7963 }
7964 }
7965
7966 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7967 fourcc = i9xx_format_to_fourcc(pixel_format);
7968 fb->pixel_format = fourcc;
7969 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7970
7971 if (INTEL_INFO(dev)->gen >= 4) {
7972 if (plane_config->tiling)
7973 offset = I915_READ(DSPTILEOFF(plane));
7974 else
7975 offset = I915_READ(DSPLINOFF(plane));
7976 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7977 } else {
7978 base = I915_READ(DSPADDR(plane));
7979 }
7980 plane_config->base = base;
7981
7982 val = I915_READ(PIPESRC(pipe));
7983 fb->width = ((val >> 16) & 0xfff) + 1;
7984 fb->height = ((val >> 0) & 0xfff) + 1;
7985
7986 val = I915_READ(DSPSTRIDE(pipe));
7987 fb->pitches[0] = val & 0xffffffc0;
7988
7989 aligned_height = intel_fb_align_height(dev, fb->height,
7990 fb->pixel_format,
7991 fb->modifier[0]);
7992
7993 plane_config->size = fb->pitches[0] * aligned_height;
7994
7995 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7996 pipe_name(pipe), plane, fb->width, fb->height,
7997 fb->bits_per_pixel, base, fb->pitches[0],
7998 plane_config->size);
7999
8000 plane_config->fb = intel_fb;
8001 }
8002
8003 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8004 struct intel_crtc_state *pipe_config)
8005 {
8006 struct drm_device *dev = crtc->base.dev;
8007 struct drm_i915_private *dev_priv = dev->dev_private;
8008 int pipe = pipe_config->cpu_transcoder;
8009 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8010 intel_clock_t clock;
8011 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8012 int refclk = 100000;
8013
8014 mutex_lock(&dev_priv->sb_lock);
8015 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8016 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8017 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8018 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8019 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8020 mutex_unlock(&dev_priv->sb_lock);
8021
8022 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8023 clock.m2 = (pll_dw0 & 0xff) << 22;
8024 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8025 clock.m2 |= pll_dw2 & 0x3fffff;
8026 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8027 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8028 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8029
8030 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8031 }
8032
8033 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8034 struct intel_crtc_state *pipe_config)
8035 {
8036 struct drm_device *dev = crtc->base.dev;
8037 struct drm_i915_private *dev_priv = dev->dev_private;
8038 uint32_t tmp;
8039
8040 if (!intel_display_power_is_enabled(dev_priv,
8041 POWER_DOMAIN_PIPE(crtc->pipe)))
8042 return false;
8043
8044 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8045 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8046
8047 tmp = I915_READ(PIPECONF(crtc->pipe));
8048 if (!(tmp & PIPECONF_ENABLE))
8049 return false;
8050
8051 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8052 switch (tmp & PIPECONF_BPC_MASK) {
8053 case PIPECONF_6BPC:
8054 pipe_config->pipe_bpp = 18;
8055 break;
8056 case PIPECONF_8BPC:
8057 pipe_config->pipe_bpp = 24;
8058 break;
8059 case PIPECONF_10BPC:
8060 pipe_config->pipe_bpp = 30;
8061 break;
8062 default:
8063 break;
8064 }
8065 }
8066
8067 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8068 pipe_config->limited_color_range = true;
8069
8070 if (INTEL_INFO(dev)->gen < 4)
8071 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8072
8073 intel_get_pipe_timings(crtc, pipe_config);
8074
8075 i9xx_get_pfit_config(crtc, pipe_config);
8076
8077 if (INTEL_INFO(dev)->gen >= 4) {
8078 tmp = I915_READ(DPLL_MD(crtc->pipe));
8079 pipe_config->pixel_multiplier =
8080 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8081 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8082 pipe_config->dpll_hw_state.dpll_md = tmp;
8083 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8084 tmp = I915_READ(DPLL(crtc->pipe));
8085 pipe_config->pixel_multiplier =
8086 ((tmp & SDVO_MULTIPLIER_MASK)
8087 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8088 } else {
8089 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8090 * port and will be fixed up in the encoder->get_config
8091 * function. */
8092 pipe_config->pixel_multiplier = 1;
8093 }
8094 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8095 if (!IS_VALLEYVIEW(dev)) {
8096 /*
8097 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8098 * on 830. Filter it out here so that we don't
8099 * report errors due to that.
8100 */
8101 if (IS_I830(dev))
8102 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8103
8104 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8105 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8106 } else {
8107 /* Mask out read-only status bits. */
8108 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8109 DPLL_PORTC_READY_MASK |
8110 DPLL_PORTB_READY_MASK);
8111 }
8112
8113 if (IS_CHERRYVIEW(dev))
8114 chv_crtc_clock_get(crtc, pipe_config);
8115 else if (IS_VALLEYVIEW(dev))
8116 vlv_crtc_clock_get(crtc, pipe_config);
8117 else
8118 i9xx_crtc_clock_get(crtc, pipe_config);
8119
8120 return true;
8121 }
8122
8123 static void ironlake_init_pch_refclk(struct drm_device *dev)
8124 {
8125 struct drm_i915_private *dev_priv = dev->dev_private;
8126 struct intel_encoder *encoder;
8127 u32 val, final;
8128 bool has_lvds = false;
8129 bool has_cpu_edp = false;
8130 bool has_panel = false;
8131 bool has_ck505 = false;
8132 bool can_ssc = false;
8133
8134 /* We need to take the global config into account */
8135 for_each_intel_encoder(dev, encoder) {
8136 switch (encoder->type) {
8137 case INTEL_OUTPUT_LVDS:
8138 has_panel = true;
8139 has_lvds = true;
8140 break;
8141 case INTEL_OUTPUT_EDP:
8142 has_panel = true;
8143 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8144 has_cpu_edp = true;
8145 break;
8146 default:
8147 break;
8148 }
8149 }
8150
8151 if (HAS_PCH_IBX(dev)) {
8152 has_ck505 = dev_priv->vbt.display_clock_mode;
8153 can_ssc = has_ck505;
8154 } else {
8155 has_ck505 = false;
8156 can_ssc = true;
8157 }
8158
8159 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8160 has_panel, has_lvds, has_ck505);
8161
8162 /* Ironlake: try to setup display ref clock before DPLL
8163 * enabling. This is only under driver's control after
8164 * PCH B stepping, previous chipset stepping should be
8165 * ignoring this setting.
8166 */
8167 val = I915_READ(PCH_DREF_CONTROL);
8168
8169 /* As we must carefully and slowly disable/enable each source in turn,
8170 * compute the final state we want first and check if we need to
8171 * make any changes at all.
8172 */
8173 final = val;
8174 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8175 if (has_ck505)
8176 final |= DREF_NONSPREAD_CK505_ENABLE;
8177 else
8178 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8179
8180 final &= ~DREF_SSC_SOURCE_MASK;
8181 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8182 final &= ~DREF_SSC1_ENABLE;
8183
8184 if (has_panel) {
8185 final |= DREF_SSC_SOURCE_ENABLE;
8186
8187 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8188 final |= DREF_SSC1_ENABLE;
8189
8190 if (has_cpu_edp) {
8191 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8192 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8193 else
8194 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8195 } else
8196 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8197 } else {
8198 final |= DREF_SSC_SOURCE_DISABLE;
8199 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8200 }
8201
8202 if (final == val)
8203 return;
8204
8205 /* Always enable nonspread source */
8206 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8207
8208 if (has_ck505)
8209 val |= DREF_NONSPREAD_CK505_ENABLE;
8210 else
8211 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8212
8213 if (has_panel) {
8214 val &= ~DREF_SSC_SOURCE_MASK;
8215 val |= DREF_SSC_SOURCE_ENABLE;
8216
8217 /* SSC must be turned on before enabling the CPU output */
8218 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8219 DRM_DEBUG_KMS("Using SSC on panel\n");
8220 val |= DREF_SSC1_ENABLE;
8221 } else
8222 val &= ~DREF_SSC1_ENABLE;
8223
8224 /* Get SSC going before enabling the outputs */
8225 I915_WRITE(PCH_DREF_CONTROL, val);
8226 POSTING_READ(PCH_DREF_CONTROL);
8227 udelay(200);
8228
8229 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8230
8231 /* Enable CPU source on CPU attached eDP */
8232 if (has_cpu_edp) {
8233 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8234 DRM_DEBUG_KMS("Using SSC on eDP\n");
8235 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8236 } else
8237 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8238 } else
8239 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8240
8241 I915_WRITE(PCH_DREF_CONTROL, val);
8242 POSTING_READ(PCH_DREF_CONTROL);
8243 udelay(200);
8244 } else {
8245 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8246
8247 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8248
8249 /* Turn off CPU output */
8250 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8251
8252 I915_WRITE(PCH_DREF_CONTROL, val);
8253 POSTING_READ(PCH_DREF_CONTROL);
8254 udelay(200);
8255
8256 /* Turn off the SSC source */
8257 val &= ~DREF_SSC_SOURCE_MASK;
8258 val |= DREF_SSC_SOURCE_DISABLE;
8259
8260 /* Turn off SSC1 */
8261 val &= ~DREF_SSC1_ENABLE;
8262
8263 I915_WRITE(PCH_DREF_CONTROL, val);
8264 POSTING_READ(PCH_DREF_CONTROL);
8265 udelay(200);
8266 }
8267
8268 BUG_ON(val != final);
8269 }
8270
8271 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8272 {
8273 uint32_t tmp;
8274
8275 tmp = I915_READ(SOUTH_CHICKEN2);
8276 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8277 I915_WRITE(SOUTH_CHICKEN2, tmp);
8278
8279 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8280 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8281 DRM_ERROR("FDI mPHY reset assert timeout\n");
8282
8283 tmp = I915_READ(SOUTH_CHICKEN2);
8284 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8285 I915_WRITE(SOUTH_CHICKEN2, tmp);
8286
8287 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8288 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8289 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8290 }
8291
8292 /* WaMPhyProgramming:hsw */
8293 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8294 {
8295 uint32_t tmp;
8296
8297 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8298 tmp &= ~(0xFF << 24);
8299 tmp |= (0x12 << 24);
8300 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8301
8302 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8303 tmp |= (1 << 11);
8304 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8305
8306 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8307 tmp |= (1 << 11);
8308 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8309
8310 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8311 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8312 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8313
8314 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8315 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8316 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8317
8318 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8319 tmp &= ~(7 << 13);
8320 tmp |= (5 << 13);
8321 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8322
8323 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8324 tmp &= ~(7 << 13);
8325 tmp |= (5 << 13);
8326 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8327
8328 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8329 tmp &= ~0xFF;
8330 tmp |= 0x1C;
8331 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8332
8333 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8334 tmp &= ~0xFF;
8335 tmp |= 0x1C;
8336 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8337
8338 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8339 tmp &= ~(0xFF << 16);
8340 tmp |= (0x1C << 16);
8341 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8342
8343 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8344 tmp &= ~(0xFF << 16);
8345 tmp |= (0x1C << 16);
8346 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8347
8348 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8349 tmp |= (1 << 27);
8350 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8351
8352 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8353 tmp |= (1 << 27);
8354 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8355
8356 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8357 tmp &= ~(0xF << 28);
8358 tmp |= (4 << 28);
8359 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8360
8361 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8362 tmp &= ~(0xF << 28);
8363 tmp |= (4 << 28);
8364 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8365 }
8366
8367 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8368 * Programming" based on the parameters passed:
8369 * - Sequence to enable CLKOUT_DP
8370 * - Sequence to enable CLKOUT_DP without spread
8371 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8372 */
8373 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8374 bool with_fdi)
8375 {
8376 struct drm_i915_private *dev_priv = dev->dev_private;
8377 uint32_t reg, tmp;
8378
8379 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8380 with_spread = true;
8381 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8382 with_fdi, "LP PCH doesn't have FDI\n"))
8383 with_fdi = false;
8384
8385 mutex_lock(&dev_priv->sb_lock);
8386
8387 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8388 tmp &= ~SBI_SSCCTL_DISABLE;
8389 tmp |= SBI_SSCCTL_PATHALT;
8390 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8391
8392 udelay(24);
8393
8394 if (with_spread) {
8395 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8396 tmp &= ~SBI_SSCCTL_PATHALT;
8397 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8398
8399 if (with_fdi) {
8400 lpt_reset_fdi_mphy(dev_priv);
8401 lpt_program_fdi_mphy(dev_priv);
8402 }
8403 }
8404
8405 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8406 SBI_GEN0 : SBI_DBUFF0;
8407 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8408 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8409 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8410
8411 mutex_unlock(&dev_priv->sb_lock);
8412 }
8413
8414 /* Sequence to disable CLKOUT_DP */
8415 static void lpt_disable_clkout_dp(struct drm_device *dev)
8416 {
8417 struct drm_i915_private *dev_priv = dev->dev_private;
8418 uint32_t reg, tmp;
8419
8420 mutex_lock(&dev_priv->sb_lock);
8421
8422 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8423 SBI_GEN0 : SBI_DBUFF0;
8424 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8425 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8426 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8427
8428 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8429 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8430 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8431 tmp |= SBI_SSCCTL_PATHALT;
8432 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8433 udelay(32);
8434 }
8435 tmp |= SBI_SSCCTL_DISABLE;
8436 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8437 }
8438
8439 mutex_unlock(&dev_priv->sb_lock);
8440 }
8441
8442 static void lpt_init_pch_refclk(struct drm_device *dev)
8443 {
8444 struct intel_encoder *encoder;
8445 bool has_vga = false;
8446
8447 for_each_intel_encoder(dev, encoder) {
8448 switch (encoder->type) {
8449 case INTEL_OUTPUT_ANALOG:
8450 has_vga = true;
8451 break;
8452 default:
8453 break;
8454 }
8455 }
8456
8457 if (has_vga)
8458 lpt_enable_clkout_dp(dev, true, true);
8459 else
8460 lpt_disable_clkout_dp(dev);
8461 }
8462
8463 /*
8464 * Initialize reference clocks when the driver loads
8465 */
8466 void intel_init_pch_refclk(struct drm_device *dev)
8467 {
8468 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8469 ironlake_init_pch_refclk(dev);
8470 else if (HAS_PCH_LPT(dev))
8471 lpt_init_pch_refclk(dev);
8472 }
8473
8474 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8475 {
8476 struct drm_device *dev = crtc_state->base.crtc->dev;
8477 struct drm_i915_private *dev_priv = dev->dev_private;
8478 struct drm_atomic_state *state = crtc_state->base.state;
8479 struct drm_connector *connector;
8480 struct drm_connector_state *connector_state;
8481 struct intel_encoder *encoder;
8482 int num_connectors = 0, i;
8483 bool is_lvds = false;
8484
8485 for_each_connector_in_state(state, connector, connector_state, i) {
8486 if (connector_state->crtc != crtc_state->base.crtc)
8487 continue;
8488
8489 encoder = to_intel_encoder(connector_state->best_encoder);
8490
8491 switch (encoder->type) {
8492 case INTEL_OUTPUT_LVDS:
8493 is_lvds = true;
8494 break;
8495 default:
8496 break;
8497 }
8498 num_connectors++;
8499 }
8500
8501 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8502 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8503 dev_priv->vbt.lvds_ssc_freq);
8504 return dev_priv->vbt.lvds_ssc_freq;
8505 }
8506
8507 return 120000;
8508 }
8509
8510 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8511 {
8512 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8514 int pipe = intel_crtc->pipe;
8515 uint32_t val;
8516
8517 val = 0;
8518
8519 switch (intel_crtc->config->pipe_bpp) {
8520 case 18:
8521 val |= PIPECONF_6BPC;
8522 break;
8523 case 24:
8524 val |= PIPECONF_8BPC;
8525 break;
8526 case 30:
8527 val |= PIPECONF_10BPC;
8528 break;
8529 case 36:
8530 val |= PIPECONF_12BPC;
8531 break;
8532 default:
8533 /* Case prevented by intel_choose_pipe_bpp_dither. */
8534 BUG();
8535 }
8536
8537 if (intel_crtc->config->dither)
8538 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8539
8540 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8541 val |= PIPECONF_INTERLACED_ILK;
8542 else
8543 val |= PIPECONF_PROGRESSIVE;
8544
8545 if (intel_crtc->config->limited_color_range)
8546 val |= PIPECONF_COLOR_RANGE_SELECT;
8547
8548 I915_WRITE(PIPECONF(pipe), val);
8549 POSTING_READ(PIPECONF(pipe));
8550 }
8551
8552 /*
8553 * Set up the pipe CSC unit.
8554 *
8555 * Currently only full range RGB to limited range RGB conversion
8556 * is supported, but eventually this should handle various
8557 * RGB<->YCbCr scenarios as well.
8558 */
8559 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8560 {
8561 struct drm_device *dev = crtc->dev;
8562 struct drm_i915_private *dev_priv = dev->dev_private;
8563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8564 int pipe = intel_crtc->pipe;
8565 uint16_t coeff = 0x7800; /* 1.0 */
8566
8567 /*
8568 * TODO: Check what kind of values actually come out of the pipe
8569 * with these coeff/postoff values and adjust to get the best
8570 * accuracy. Perhaps we even need to take the bpc value into
8571 * consideration.
8572 */
8573
8574 if (intel_crtc->config->limited_color_range)
8575 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8576
8577 /*
8578 * GY/GU and RY/RU should be the other way around according
8579 * to BSpec, but reality doesn't agree. Just set them up in
8580 * a way that results in the correct picture.
8581 */
8582 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8583 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8584
8585 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8586 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8587
8588 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8589 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8590
8591 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8592 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8593 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8594
8595 if (INTEL_INFO(dev)->gen > 6) {
8596 uint16_t postoff = 0;
8597
8598 if (intel_crtc->config->limited_color_range)
8599 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8600
8601 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8602 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8603 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8604
8605 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8606 } else {
8607 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8608
8609 if (intel_crtc->config->limited_color_range)
8610 mode |= CSC_BLACK_SCREEN_OFFSET;
8611
8612 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8613 }
8614 }
8615
8616 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8617 {
8618 struct drm_device *dev = crtc->dev;
8619 struct drm_i915_private *dev_priv = dev->dev_private;
8620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8621 enum pipe pipe = intel_crtc->pipe;
8622 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8623 uint32_t val;
8624
8625 val = 0;
8626
8627 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8628 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8629
8630 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8631 val |= PIPECONF_INTERLACED_ILK;
8632 else
8633 val |= PIPECONF_PROGRESSIVE;
8634
8635 I915_WRITE(PIPECONF(cpu_transcoder), val);
8636 POSTING_READ(PIPECONF(cpu_transcoder));
8637
8638 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8639 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8640
8641 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8642 val = 0;
8643
8644 switch (intel_crtc->config->pipe_bpp) {
8645 case 18:
8646 val |= PIPEMISC_DITHER_6_BPC;
8647 break;
8648 case 24:
8649 val |= PIPEMISC_DITHER_8_BPC;
8650 break;
8651 case 30:
8652 val |= PIPEMISC_DITHER_10_BPC;
8653 break;
8654 case 36:
8655 val |= PIPEMISC_DITHER_12_BPC;
8656 break;
8657 default:
8658 /* Case prevented by pipe_config_set_bpp. */
8659 BUG();
8660 }
8661
8662 if (intel_crtc->config->dither)
8663 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8664
8665 I915_WRITE(PIPEMISC(pipe), val);
8666 }
8667 }
8668
8669 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8670 struct intel_crtc_state *crtc_state,
8671 intel_clock_t *clock,
8672 bool *has_reduced_clock,
8673 intel_clock_t *reduced_clock)
8674 {
8675 struct drm_device *dev = crtc->dev;
8676 struct drm_i915_private *dev_priv = dev->dev_private;
8677 int refclk;
8678 const intel_limit_t *limit;
8679 bool ret;
8680
8681 refclk = ironlake_get_refclk(crtc_state);
8682
8683 /*
8684 * Returns a set of divisors for the desired target clock with the given
8685 * refclk, or FALSE. The returned values represent the clock equation:
8686 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8687 */
8688 limit = intel_limit(crtc_state, refclk);
8689 ret = dev_priv->display.find_dpll(limit, crtc_state,
8690 crtc_state->port_clock,
8691 refclk, NULL, clock);
8692 if (!ret)
8693 return false;
8694
8695 return true;
8696 }
8697
8698 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8699 {
8700 /*
8701 * Account for spread spectrum to avoid
8702 * oversubscribing the link. Max center spread
8703 * is 2.5%; use 5% for safety's sake.
8704 */
8705 u32 bps = target_clock * bpp * 21 / 20;
8706 return DIV_ROUND_UP(bps, link_bw * 8);
8707 }
8708
8709 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8710 {
8711 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8712 }
8713
8714 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8715 struct intel_crtc_state *crtc_state,
8716 u32 *fp,
8717 intel_clock_t *reduced_clock, u32 *fp2)
8718 {
8719 struct drm_crtc *crtc = &intel_crtc->base;
8720 struct drm_device *dev = crtc->dev;
8721 struct drm_i915_private *dev_priv = dev->dev_private;
8722 struct drm_atomic_state *state = crtc_state->base.state;
8723 struct drm_connector *connector;
8724 struct drm_connector_state *connector_state;
8725 struct intel_encoder *encoder;
8726 uint32_t dpll;
8727 int factor, num_connectors = 0, i;
8728 bool is_lvds = false, is_sdvo = false;
8729
8730 for_each_connector_in_state(state, connector, connector_state, i) {
8731 if (connector_state->crtc != crtc_state->base.crtc)
8732 continue;
8733
8734 encoder = to_intel_encoder(connector_state->best_encoder);
8735
8736 switch (encoder->type) {
8737 case INTEL_OUTPUT_LVDS:
8738 is_lvds = true;
8739 break;
8740 case INTEL_OUTPUT_SDVO:
8741 case INTEL_OUTPUT_HDMI:
8742 is_sdvo = true;
8743 break;
8744 default:
8745 break;
8746 }
8747
8748 num_connectors++;
8749 }
8750
8751 /* Enable autotuning of the PLL clock (if permissible) */
8752 factor = 21;
8753 if (is_lvds) {
8754 if ((intel_panel_use_ssc(dev_priv) &&
8755 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8756 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8757 factor = 25;
8758 } else if (crtc_state->sdvo_tv_clock)
8759 factor = 20;
8760
8761 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8762 *fp |= FP_CB_TUNE;
8763
8764 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8765 *fp2 |= FP_CB_TUNE;
8766
8767 dpll = 0;
8768
8769 if (is_lvds)
8770 dpll |= DPLLB_MODE_LVDS;
8771 else
8772 dpll |= DPLLB_MODE_DAC_SERIAL;
8773
8774 dpll |= (crtc_state->pixel_multiplier - 1)
8775 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8776
8777 if (is_sdvo)
8778 dpll |= DPLL_SDVO_HIGH_SPEED;
8779 if (crtc_state->has_dp_encoder)
8780 dpll |= DPLL_SDVO_HIGH_SPEED;
8781
8782 /* compute bitmask from p1 value */
8783 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8784 /* also FPA1 */
8785 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8786
8787 switch (crtc_state->dpll.p2) {
8788 case 5:
8789 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8790 break;
8791 case 7:
8792 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8793 break;
8794 case 10:
8795 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8796 break;
8797 case 14:
8798 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8799 break;
8800 }
8801
8802 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8803 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8804 else
8805 dpll |= PLL_REF_INPUT_DREFCLK;
8806
8807 return dpll | DPLL_VCO_ENABLE;
8808 }
8809
8810 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8811 struct intel_crtc_state *crtc_state)
8812 {
8813 struct drm_device *dev = crtc->base.dev;
8814 intel_clock_t clock, reduced_clock;
8815 u32 dpll = 0, fp = 0, fp2 = 0;
8816 bool ok, has_reduced_clock = false;
8817 bool is_lvds = false;
8818 struct intel_shared_dpll *pll;
8819
8820 memset(&crtc_state->dpll_hw_state, 0,
8821 sizeof(crtc_state->dpll_hw_state));
8822
8823 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8824
8825 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8826 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8827
8828 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8829 &has_reduced_clock, &reduced_clock);
8830 if (!ok && !crtc_state->clock_set) {
8831 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8832 return -EINVAL;
8833 }
8834 /* Compat-code for transition, will disappear. */
8835 if (!crtc_state->clock_set) {
8836 crtc_state->dpll.n = clock.n;
8837 crtc_state->dpll.m1 = clock.m1;
8838 crtc_state->dpll.m2 = clock.m2;
8839 crtc_state->dpll.p1 = clock.p1;
8840 crtc_state->dpll.p2 = clock.p2;
8841 }
8842
8843 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8844 if (crtc_state->has_pch_encoder) {
8845 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8846 if (has_reduced_clock)
8847 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8848
8849 dpll = ironlake_compute_dpll(crtc, crtc_state,
8850 &fp, &reduced_clock,
8851 has_reduced_clock ? &fp2 : NULL);
8852
8853 crtc_state->dpll_hw_state.dpll = dpll;
8854 crtc_state->dpll_hw_state.fp0 = fp;
8855 if (has_reduced_clock)
8856 crtc_state->dpll_hw_state.fp1 = fp2;
8857 else
8858 crtc_state->dpll_hw_state.fp1 = fp;
8859
8860 pll = intel_get_shared_dpll(crtc, crtc_state);
8861 if (pll == NULL) {
8862 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8863 pipe_name(crtc->pipe));
8864 return -EINVAL;
8865 }
8866 }
8867
8868 if (is_lvds && has_reduced_clock)
8869 crtc->lowfreq_avail = true;
8870 else
8871 crtc->lowfreq_avail = false;
8872
8873 return 0;
8874 }
8875
8876 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8877 struct intel_link_m_n *m_n)
8878 {
8879 struct drm_device *dev = crtc->base.dev;
8880 struct drm_i915_private *dev_priv = dev->dev_private;
8881 enum pipe pipe = crtc->pipe;
8882
8883 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8884 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8885 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8886 & ~TU_SIZE_MASK;
8887 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8888 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8889 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8890 }
8891
8892 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8893 enum transcoder transcoder,
8894 struct intel_link_m_n *m_n,
8895 struct intel_link_m_n *m2_n2)
8896 {
8897 struct drm_device *dev = crtc->base.dev;
8898 struct drm_i915_private *dev_priv = dev->dev_private;
8899 enum pipe pipe = crtc->pipe;
8900
8901 if (INTEL_INFO(dev)->gen >= 5) {
8902 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8903 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8904 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8905 & ~TU_SIZE_MASK;
8906 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8907 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8908 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8909 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8910 * gen < 8) and if DRRS is supported (to make sure the
8911 * registers are not unnecessarily read).
8912 */
8913 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8914 crtc->config->has_drrs) {
8915 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8916 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8917 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8918 & ~TU_SIZE_MASK;
8919 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8920 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8921 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8922 }
8923 } else {
8924 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8925 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8926 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8927 & ~TU_SIZE_MASK;
8928 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8929 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8930 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8931 }
8932 }
8933
8934 void intel_dp_get_m_n(struct intel_crtc *crtc,
8935 struct intel_crtc_state *pipe_config)
8936 {
8937 if (pipe_config->has_pch_encoder)
8938 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8939 else
8940 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8941 &pipe_config->dp_m_n,
8942 &pipe_config->dp_m2_n2);
8943 }
8944
8945 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8946 struct intel_crtc_state *pipe_config)
8947 {
8948 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8949 &pipe_config->fdi_m_n, NULL);
8950 }
8951
8952 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8953 struct intel_crtc_state *pipe_config)
8954 {
8955 struct drm_device *dev = crtc->base.dev;
8956 struct drm_i915_private *dev_priv = dev->dev_private;
8957 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8958 uint32_t ps_ctrl = 0;
8959 int id = -1;
8960 int i;
8961
8962 /* find scaler attached to this pipe */
8963 for (i = 0; i < crtc->num_scalers; i++) {
8964 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8965 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8966 id = i;
8967 pipe_config->pch_pfit.enabled = true;
8968 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8969 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8970 break;
8971 }
8972 }
8973
8974 scaler_state->scaler_id = id;
8975 if (id >= 0) {
8976 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8977 } else {
8978 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8979 }
8980 }
8981
8982 static void
8983 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8984 struct intel_initial_plane_config *plane_config)
8985 {
8986 struct drm_device *dev = crtc->base.dev;
8987 struct drm_i915_private *dev_priv = dev->dev_private;
8988 u32 val, base, offset, stride_mult, tiling;
8989 int pipe = crtc->pipe;
8990 int fourcc, pixel_format;
8991 unsigned int aligned_height;
8992 struct drm_framebuffer *fb;
8993 struct intel_framebuffer *intel_fb;
8994
8995 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8996 if (!intel_fb) {
8997 DRM_DEBUG_KMS("failed to alloc fb\n");
8998 return;
8999 }
9000
9001 fb = &intel_fb->base;
9002
9003 val = I915_READ(PLANE_CTL(pipe, 0));
9004 if (!(val & PLANE_CTL_ENABLE))
9005 goto error;
9006
9007 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9008 fourcc = skl_format_to_fourcc(pixel_format,
9009 val & PLANE_CTL_ORDER_RGBX,
9010 val & PLANE_CTL_ALPHA_MASK);
9011 fb->pixel_format = fourcc;
9012 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9013
9014 tiling = val & PLANE_CTL_TILED_MASK;
9015 switch (tiling) {
9016 case PLANE_CTL_TILED_LINEAR:
9017 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9018 break;
9019 case PLANE_CTL_TILED_X:
9020 plane_config->tiling = I915_TILING_X;
9021 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9022 break;
9023 case PLANE_CTL_TILED_Y:
9024 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9025 break;
9026 case PLANE_CTL_TILED_YF:
9027 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9028 break;
9029 default:
9030 MISSING_CASE(tiling);
9031 goto error;
9032 }
9033
9034 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9035 plane_config->base = base;
9036
9037 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9038
9039 val = I915_READ(PLANE_SIZE(pipe, 0));
9040 fb->height = ((val >> 16) & 0xfff) + 1;
9041 fb->width = ((val >> 0) & 0x1fff) + 1;
9042
9043 val = I915_READ(PLANE_STRIDE(pipe, 0));
9044 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9045 fb->pixel_format);
9046 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9047
9048 aligned_height = intel_fb_align_height(dev, fb->height,
9049 fb->pixel_format,
9050 fb->modifier[0]);
9051
9052 plane_config->size = fb->pitches[0] * aligned_height;
9053
9054 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9055 pipe_name(pipe), fb->width, fb->height,
9056 fb->bits_per_pixel, base, fb->pitches[0],
9057 plane_config->size);
9058
9059 plane_config->fb = intel_fb;
9060 return;
9061
9062 error:
9063 kfree(fb);
9064 }
9065
9066 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9067 struct intel_crtc_state *pipe_config)
9068 {
9069 struct drm_device *dev = crtc->base.dev;
9070 struct drm_i915_private *dev_priv = dev->dev_private;
9071 uint32_t tmp;
9072
9073 tmp = I915_READ(PF_CTL(crtc->pipe));
9074
9075 if (tmp & PF_ENABLE) {
9076 pipe_config->pch_pfit.enabled = true;
9077 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9078 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9079
9080 /* We currently do not free assignements of panel fitters on
9081 * ivb/hsw (since we don't use the higher upscaling modes which
9082 * differentiates them) so just WARN about this case for now. */
9083 if (IS_GEN7(dev)) {
9084 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9085 PF_PIPE_SEL_IVB(crtc->pipe));
9086 }
9087 }
9088 }
9089
9090 static void
9091 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9092 struct intel_initial_plane_config *plane_config)
9093 {
9094 struct drm_device *dev = crtc->base.dev;
9095 struct drm_i915_private *dev_priv = dev->dev_private;
9096 u32 val, base, offset;
9097 int pipe = crtc->pipe;
9098 int fourcc, pixel_format;
9099 unsigned int aligned_height;
9100 struct drm_framebuffer *fb;
9101 struct intel_framebuffer *intel_fb;
9102
9103 val = I915_READ(DSPCNTR(pipe));
9104 if (!(val & DISPLAY_PLANE_ENABLE))
9105 return;
9106
9107 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9108 if (!intel_fb) {
9109 DRM_DEBUG_KMS("failed to alloc fb\n");
9110 return;
9111 }
9112
9113 fb = &intel_fb->base;
9114
9115 if (INTEL_INFO(dev)->gen >= 4) {
9116 if (val & DISPPLANE_TILED) {
9117 plane_config->tiling = I915_TILING_X;
9118 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9119 }
9120 }
9121
9122 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9123 fourcc = i9xx_format_to_fourcc(pixel_format);
9124 fb->pixel_format = fourcc;
9125 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9126
9127 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9128 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9129 offset = I915_READ(DSPOFFSET(pipe));
9130 } else {
9131 if (plane_config->tiling)
9132 offset = I915_READ(DSPTILEOFF(pipe));
9133 else
9134 offset = I915_READ(DSPLINOFF(pipe));
9135 }
9136 plane_config->base = base;
9137
9138 val = I915_READ(PIPESRC(pipe));
9139 fb->width = ((val >> 16) & 0xfff) + 1;
9140 fb->height = ((val >> 0) & 0xfff) + 1;
9141
9142 val = I915_READ(DSPSTRIDE(pipe));
9143 fb->pitches[0] = val & 0xffffffc0;
9144
9145 aligned_height = intel_fb_align_height(dev, fb->height,
9146 fb->pixel_format,
9147 fb->modifier[0]);
9148
9149 plane_config->size = fb->pitches[0] * aligned_height;
9150
9151 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9152 pipe_name(pipe), fb->width, fb->height,
9153 fb->bits_per_pixel, base, fb->pitches[0],
9154 plane_config->size);
9155
9156 plane_config->fb = intel_fb;
9157 }
9158
9159 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9160 struct intel_crtc_state *pipe_config)
9161 {
9162 struct drm_device *dev = crtc->base.dev;
9163 struct drm_i915_private *dev_priv = dev->dev_private;
9164 uint32_t tmp;
9165
9166 if (!intel_display_power_is_enabled(dev_priv,
9167 POWER_DOMAIN_PIPE(crtc->pipe)))
9168 return false;
9169
9170 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9171 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9172
9173 tmp = I915_READ(PIPECONF(crtc->pipe));
9174 if (!(tmp & PIPECONF_ENABLE))
9175 return false;
9176
9177 switch (tmp & PIPECONF_BPC_MASK) {
9178 case PIPECONF_6BPC:
9179 pipe_config->pipe_bpp = 18;
9180 break;
9181 case PIPECONF_8BPC:
9182 pipe_config->pipe_bpp = 24;
9183 break;
9184 case PIPECONF_10BPC:
9185 pipe_config->pipe_bpp = 30;
9186 break;
9187 case PIPECONF_12BPC:
9188 pipe_config->pipe_bpp = 36;
9189 break;
9190 default:
9191 break;
9192 }
9193
9194 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9195 pipe_config->limited_color_range = true;
9196
9197 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9198 struct intel_shared_dpll *pll;
9199
9200 pipe_config->has_pch_encoder = true;
9201
9202 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9203 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9204 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9205
9206 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9207
9208 if (HAS_PCH_IBX(dev_priv->dev)) {
9209 pipe_config->shared_dpll =
9210 (enum intel_dpll_id) crtc->pipe;
9211 } else {
9212 tmp = I915_READ(PCH_DPLL_SEL);
9213 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9214 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9215 else
9216 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9217 }
9218
9219 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9220
9221 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9222 &pipe_config->dpll_hw_state));
9223
9224 tmp = pipe_config->dpll_hw_state.dpll;
9225 pipe_config->pixel_multiplier =
9226 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9227 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9228
9229 ironlake_pch_clock_get(crtc, pipe_config);
9230 } else {
9231 pipe_config->pixel_multiplier = 1;
9232 }
9233
9234 intel_get_pipe_timings(crtc, pipe_config);
9235
9236 ironlake_get_pfit_config(crtc, pipe_config);
9237
9238 return true;
9239 }
9240
9241 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9242 {
9243 struct drm_device *dev = dev_priv->dev;
9244 struct intel_crtc *crtc;
9245
9246 for_each_intel_crtc(dev, crtc)
9247 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9248 pipe_name(crtc->pipe));
9249
9250 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9251 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9252 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9253 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9254 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9255 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9256 "CPU PWM1 enabled\n");
9257 if (IS_HASWELL(dev))
9258 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9259 "CPU PWM2 enabled\n");
9260 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9261 "PCH PWM1 enabled\n");
9262 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9263 "Utility pin enabled\n");
9264 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9265
9266 /*
9267 * In theory we can still leave IRQs enabled, as long as only the HPD
9268 * interrupts remain enabled. We used to check for that, but since it's
9269 * gen-specific and since we only disable LCPLL after we fully disable
9270 * the interrupts, the check below should be enough.
9271 */
9272 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9273 }
9274
9275 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9276 {
9277 struct drm_device *dev = dev_priv->dev;
9278
9279 if (IS_HASWELL(dev))
9280 return I915_READ(D_COMP_HSW);
9281 else
9282 return I915_READ(D_COMP_BDW);
9283 }
9284
9285 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9286 {
9287 struct drm_device *dev = dev_priv->dev;
9288
9289 if (IS_HASWELL(dev)) {
9290 mutex_lock(&dev_priv->rps.hw_lock);
9291 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9292 val))
9293 DRM_ERROR("Failed to write to D_COMP\n");
9294 mutex_unlock(&dev_priv->rps.hw_lock);
9295 } else {
9296 I915_WRITE(D_COMP_BDW, val);
9297 POSTING_READ(D_COMP_BDW);
9298 }
9299 }
9300
9301 /*
9302 * This function implements pieces of two sequences from BSpec:
9303 * - Sequence for display software to disable LCPLL
9304 * - Sequence for display software to allow package C8+
9305 * The steps implemented here are just the steps that actually touch the LCPLL
9306 * register. Callers should take care of disabling all the display engine
9307 * functions, doing the mode unset, fixing interrupts, etc.
9308 */
9309 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9310 bool switch_to_fclk, bool allow_power_down)
9311 {
9312 uint32_t val;
9313
9314 assert_can_disable_lcpll(dev_priv);
9315
9316 val = I915_READ(LCPLL_CTL);
9317
9318 if (switch_to_fclk) {
9319 val |= LCPLL_CD_SOURCE_FCLK;
9320 I915_WRITE(LCPLL_CTL, val);
9321
9322 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9323 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9324 DRM_ERROR("Switching to FCLK failed\n");
9325
9326 val = I915_READ(LCPLL_CTL);
9327 }
9328
9329 val |= LCPLL_PLL_DISABLE;
9330 I915_WRITE(LCPLL_CTL, val);
9331 POSTING_READ(LCPLL_CTL);
9332
9333 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9334 DRM_ERROR("LCPLL still locked\n");
9335
9336 val = hsw_read_dcomp(dev_priv);
9337 val |= D_COMP_COMP_DISABLE;
9338 hsw_write_dcomp(dev_priv, val);
9339 ndelay(100);
9340
9341 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9342 1))
9343 DRM_ERROR("D_COMP RCOMP still in progress\n");
9344
9345 if (allow_power_down) {
9346 val = I915_READ(LCPLL_CTL);
9347 val |= LCPLL_POWER_DOWN_ALLOW;
9348 I915_WRITE(LCPLL_CTL, val);
9349 POSTING_READ(LCPLL_CTL);
9350 }
9351 }
9352
9353 /*
9354 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9355 * source.
9356 */
9357 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9358 {
9359 uint32_t val;
9360
9361 val = I915_READ(LCPLL_CTL);
9362
9363 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9364 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9365 return;
9366
9367 /*
9368 * Make sure we're not on PC8 state before disabling PC8, otherwise
9369 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9370 */
9371 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9372
9373 if (val & LCPLL_POWER_DOWN_ALLOW) {
9374 val &= ~LCPLL_POWER_DOWN_ALLOW;
9375 I915_WRITE(LCPLL_CTL, val);
9376 POSTING_READ(LCPLL_CTL);
9377 }
9378
9379 val = hsw_read_dcomp(dev_priv);
9380 val |= D_COMP_COMP_FORCE;
9381 val &= ~D_COMP_COMP_DISABLE;
9382 hsw_write_dcomp(dev_priv, val);
9383
9384 val = I915_READ(LCPLL_CTL);
9385 val &= ~LCPLL_PLL_DISABLE;
9386 I915_WRITE(LCPLL_CTL, val);
9387
9388 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9389 DRM_ERROR("LCPLL not locked yet\n");
9390
9391 if (val & LCPLL_CD_SOURCE_FCLK) {
9392 val = I915_READ(LCPLL_CTL);
9393 val &= ~LCPLL_CD_SOURCE_FCLK;
9394 I915_WRITE(LCPLL_CTL, val);
9395
9396 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9397 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9398 DRM_ERROR("Switching back to LCPLL failed\n");
9399 }
9400
9401 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9402 intel_update_cdclk(dev_priv->dev);
9403 }
9404
9405 /*
9406 * Package states C8 and deeper are really deep PC states that can only be
9407 * reached when all the devices on the system allow it, so even if the graphics
9408 * device allows PC8+, it doesn't mean the system will actually get to these
9409 * states. Our driver only allows PC8+ when going into runtime PM.
9410 *
9411 * The requirements for PC8+ are that all the outputs are disabled, the power
9412 * well is disabled and most interrupts are disabled, and these are also
9413 * requirements for runtime PM. When these conditions are met, we manually do
9414 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9415 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9416 * hang the machine.
9417 *
9418 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9419 * the state of some registers, so when we come back from PC8+ we need to
9420 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9421 * need to take care of the registers kept by RC6. Notice that this happens even
9422 * if we don't put the device in PCI D3 state (which is what currently happens
9423 * because of the runtime PM support).
9424 *
9425 * For more, read "Display Sequences for Package C8" on the hardware
9426 * documentation.
9427 */
9428 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9429 {
9430 struct drm_device *dev = dev_priv->dev;
9431 uint32_t val;
9432
9433 DRM_DEBUG_KMS("Enabling package C8+\n");
9434
9435 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9436 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9437 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9438 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9439 }
9440
9441 lpt_disable_clkout_dp(dev);
9442 hsw_disable_lcpll(dev_priv, true, true);
9443 }
9444
9445 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9446 {
9447 struct drm_device *dev = dev_priv->dev;
9448 uint32_t val;
9449
9450 DRM_DEBUG_KMS("Disabling package C8+\n");
9451
9452 hsw_restore_lcpll(dev_priv);
9453 lpt_init_pch_refclk(dev);
9454
9455 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9456 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9457 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9458 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9459 }
9460
9461 intel_prepare_ddi(dev);
9462 }
9463
9464 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9465 {
9466 struct drm_device *dev = old_state->dev;
9467 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9468
9469 broxton_set_cdclk(dev, req_cdclk);
9470 }
9471
9472 /* compute the max rate for new configuration */
9473 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9474 {
9475 struct intel_crtc *intel_crtc;
9476 struct intel_crtc_state *crtc_state;
9477 int max_pixel_rate = 0;
9478
9479 for_each_intel_crtc(state->dev, intel_crtc) {
9480 int pixel_rate;
9481
9482 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9483 if (IS_ERR(crtc_state))
9484 return PTR_ERR(crtc_state);
9485
9486 if (!crtc_state->base.enable)
9487 continue;
9488
9489 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9490
9491 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9492 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9493 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9494
9495 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9496 }
9497
9498 return max_pixel_rate;
9499 }
9500
9501 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9502 {
9503 struct drm_i915_private *dev_priv = dev->dev_private;
9504 uint32_t val, data;
9505 int ret;
9506
9507 if (WARN((I915_READ(LCPLL_CTL) &
9508 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9509 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9510 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9511 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9512 "trying to change cdclk frequency with cdclk not enabled\n"))
9513 return;
9514
9515 mutex_lock(&dev_priv->rps.hw_lock);
9516 ret = sandybridge_pcode_write(dev_priv,
9517 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9518 mutex_unlock(&dev_priv->rps.hw_lock);
9519 if (ret) {
9520 DRM_ERROR("failed to inform pcode about cdclk change\n");
9521 return;
9522 }
9523
9524 val = I915_READ(LCPLL_CTL);
9525 val |= LCPLL_CD_SOURCE_FCLK;
9526 I915_WRITE(LCPLL_CTL, val);
9527
9528 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9529 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9530 DRM_ERROR("Switching to FCLK failed\n");
9531
9532 val = I915_READ(LCPLL_CTL);
9533 val &= ~LCPLL_CLK_FREQ_MASK;
9534
9535 switch (cdclk) {
9536 case 450000:
9537 val |= LCPLL_CLK_FREQ_450;
9538 data = 0;
9539 break;
9540 case 540000:
9541 val |= LCPLL_CLK_FREQ_54O_BDW;
9542 data = 1;
9543 break;
9544 case 337500:
9545 val |= LCPLL_CLK_FREQ_337_5_BDW;
9546 data = 2;
9547 break;
9548 case 675000:
9549 val |= LCPLL_CLK_FREQ_675_BDW;
9550 data = 3;
9551 break;
9552 default:
9553 WARN(1, "invalid cdclk frequency\n");
9554 return;
9555 }
9556
9557 I915_WRITE(LCPLL_CTL, val);
9558
9559 val = I915_READ(LCPLL_CTL);
9560 val &= ~LCPLL_CD_SOURCE_FCLK;
9561 I915_WRITE(LCPLL_CTL, val);
9562
9563 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9564 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9565 DRM_ERROR("Switching back to LCPLL failed\n");
9566
9567 mutex_lock(&dev_priv->rps.hw_lock);
9568 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9569 mutex_unlock(&dev_priv->rps.hw_lock);
9570
9571 intel_update_cdclk(dev);
9572
9573 WARN(cdclk != dev_priv->cdclk_freq,
9574 "cdclk requested %d kHz but got %d kHz\n",
9575 cdclk, dev_priv->cdclk_freq);
9576 }
9577
9578 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9579 {
9580 struct drm_i915_private *dev_priv = to_i915(state->dev);
9581 int max_pixclk = ilk_max_pixel_rate(state);
9582 int cdclk;
9583
9584 /*
9585 * FIXME should also account for plane ratio
9586 * once 64bpp pixel formats are supported.
9587 */
9588 if (max_pixclk > 540000)
9589 cdclk = 675000;
9590 else if (max_pixclk > 450000)
9591 cdclk = 540000;
9592 else if (max_pixclk > 337500)
9593 cdclk = 450000;
9594 else
9595 cdclk = 337500;
9596
9597 /*
9598 * FIXME move the cdclk caclulation to
9599 * compute_config() so we can fail gracegully.
9600 */
9601 if (cdclk > dev_priv->max_cdclk_freq) {
9602 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9603 cdclk, dev_priv->max_cdclk_freq);
9604 cdclk = dev_priv->max_cdclk_freq;
9605 }
9606
9607 to_intel_atomic_state(state)->cdclk = cdclk;
9608
9609 return 0;
9610 }
9611
9612 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9613 {
9614 struct drm_device *dev = old_state->dev;
9615 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9616
9617 broadwell_set_cdclk(dev, req_cdclk);
9618 }
9619
9620 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9621 struct intel_crtc_state *crtc_state)
9622 {
9623 if (!intel_ddi_pll_select(crtc, crtc_state))
9624 return -EINVAL;
9625
9626 crtc->lowfreq_avail = false;
9627
9628 return 0;
9629 }
9630
9631 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9632 enum port port,
9633 struct intel_crtc_state *pipe_config)
9634 {
9635 switch (port) {
9636 case PORT_A:
9637 pipe_config->ddi_pll_sel = SKL_DPLL0;
9638 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9639 break;
9640 case PORT_B:
9641 pipe_config->ddi_pll_sel = SKL_DPLL1;
9642 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9643 break;
9644 case PORT_C:
9645 pipe_config->ddi_pll_sel = SKL_DPLL2;
9646 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9647 break;
9648 default:
9649 DRM_ERROR("Incorrect port type\n");
9650 }
9651 }
9652
9653 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9654 enum port port,
9655 struct intel_crtc_state *pipe_config)
9656 {
9657 u32 temp, dpll_ctl1;
9658
9659 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9660 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9661
9662 switch (pipe_config->ddi_pll_sel) {
9663 case SKL_DPLL0:
9664 /*
9665 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9666 * of the shared DPLL framework and thus needs to be read out
9667 * separately
9668 */
9669 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9670 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9671 break;
9672 case SKL_DPLL1:
9673 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9674 break;
9675 case SKL_DPLL2:
9676 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9677 break;
9678 case SKL_DPLL3:
9679 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9680 break;
9681 }
9682 }
9683
9684 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9685 enum port port,
9686 struct intel_crtc_state *pipe_config)
9687 {
9688 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9689
9690 switch (pipe_config->ddi_pll_sel) {
9691 case PORT_CLK_SEL_WRPLL1:
9692 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9693 break;
9694 case PORT_CLK_SEL_WRPLL2:
9695 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9696 break;
9697 }
9698 }
9699
9700 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9701 struct intel_crtc_state *pipe_config)
9702 {
9703 struct drm_device *dev = crtc->base.dev;
9704 struct drm_i915_private *dev_priv = dev->dev_private;
9705 struct intel_shared_dpll *pll;
9706 enum port port;
9707 uint32_t tmp;
9708
9709 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9710
9711 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9712
9713 if (IS_SKYLAKE(dev))
9714 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9715 else if (IS_BROXTON(dev))
9716 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9717 else
9718 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9719
9720 if (pipe_config->shared_dpll >= 0) {
9721 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9722
9723 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9724 &pipe_config->dpll_hw_state));
9725 }
9726
9727 /*
9728 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9729 * DDI E. So just check whether this pipe is wired to DDI E and whether
9730 * the PCH transcoder is on.
9731 */
9732 if (INTEL_INFO(dev)->gen < 9 &&
9733 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9734 pipe_config->has_pch_encoder = true;
9735
9736 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9737 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9738 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9739
9740 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9741 }
9742 }
9743
9744 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9745 struct intel_crtc_state *pipe_config)
9746 {
9747 struct drm_device *dev = crtc->base.dev;
9748 struct drm_i915_private *dev_priv = dev->dev_private;
9749 enum intel_display_power_domain pfit_domain;
9750 uint32_t tmp;
9751
9752 if (!intel_display_power_is_enabled(dev_priv,
9753 POWER_DOMAIN_PIPE(crtc->pipe)))
9754 return false;
9755
9756 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9757 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9758
9759 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9760 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9761 enum pipe trans_edp_pipe;
9762 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9763 default:
9764 WARN(1, "unknown pipe linked to edp transcoder\n");
9765 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9766 case TRANS_DDI_EDP_INPUT_A_ON:
9767 trans_edp_pipe = PIPE_A;
9768 break;
9769 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9770 trans_edp_pipe = PIPE_B;
9771 break;
9772 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9773 trans_edp_pipe = PIPE_C;
9774 break;
9775 }
9776
9777 if (trans_edp_pipe == crtc->pipe)
9778 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9779 }
9780
9781 if (!intel_display_power_is_enabled(dev_priv,
9782 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9783 return false;
9784
9785 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9786 if (!(tmp & PIPECONF_ENABLE))
9787 return false;
9788
9789 haswell_get_ddi_port_state(crtc, pipe_config);
9790
9791 intel_get_pipe_timings(crtc, pipe_config);
9792
9793 if (INTEL_INFO(dev)->gen >= 9) {
9794 skl_init_scalers(dev, crtc, pipe_config);
9795 }
9796
9797 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9798
9799 if (INTEL_INFO(dev)->gen >= 9) {
9800 pipe_config->scaler_state.scaler_id = -1;
9801 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9802 }
9803
9804 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9805 if (INTEL_INFO(dev)->gen == 9)
9806 skylake_get_pfit_config(crtc, pipe_config);
9807 else if (INTEL_INFO(dev)->gen < 9)
9808 ironlake_get_pfit_config(crtc, pipe_config);
9809 else
9810 MISSING_CASE(INTEL_INFO(dev)->gen);
9811 }
9812
9813 if (IS_HASWELL(dev))
9814 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9815 (I915_READ(IPS_CTL) & IPS_ENABLE);
9816
9817 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9818 pipe_config->pixel_multiplier =
9819 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9820 } else {
9821 pipe_config->pixel_multiplier = 1;
9822 }
9823
9824 return true;
9825 }
9826
9827 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9828 {
9829 struct drm_device *dev = crtc->dev;
9830 struct drm_i915_private *dev_priv = dev->dev_private;
9831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9832 uint32_t cntl = 0, size = 0;
9833
9834 if (base) {
9835 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9836 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9837 unsigned int stride = roundup_pow_of_two(width) * 4;
9838
9839 switch (stride) {
9840 default:
9841 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9842 width, stride);
9843 stride = 256;
9844 /* fallthrough */
9845 case 256:
9846 case 512:
9847 case 1024:
9848 case 2048:
9849 break;
9850 }
9851
9852 cntl |= CURSOR_ENABLE |
9853 CURSOR_GAMMA_ENABLE |
9854 CURSOR_FORMAT_ARGB |
9855 CURSOR_STRIDE(stride);
9856
9857 size = (height << 12) | width;
9858 }
9859
9860 if (intel_crtc->cursor_cntl != 0 &&
9861 (intel_crtc->cursor_base != base ||
9862 intel_crtc->cursor_size != size ||
9863 intel_crtc->cursor_cntl != cntl)) {
9864 /* On these chipsets we can only modify the base/size/stride
9865 * whilst the cursor is disabled.
9866 */
9867 I915_WRITE(_CURACNTR, 0);
9868 POSTING_READ(_CURACNTR);
9869 intel_crtc->cursor_cntl = 0;
9870 }
9871
9872 if (intel_crtc->cursor_base != base) {
9873 I915_WRITE(_CURABASE, base);
9874 intel_crtc->cursor_base = base;
9875 }
9876
9877 if (intel_crtc->cursor_size != size) {
9878 I915_WRITE(CURSIZE, size);
9879 intel_crtc->cursor_size = size;
9880 }
9881
9882 if (intel_crtc->cursor_cntl != cntl) {
9883 I915_WRITE(_CURACNTR, cntl);
9884 POSTING_READ(_CURACNTR);
9885 intel_crtc->cursor_cntl = cntl;
9886 }
9887 }
9888
9889 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9890 {
9891 struct drm_device *dev = crtc->dev;
9892 struct drm_i915_private *dev_priv = dev->dev_private;
9893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9894 int pipe = intel_crtc->pipe;
9895 uint32_t cntl;
9896
9897 cntl = 0;
9898 if (base) {
9899 cntl = MCURSOR_GAMMA_ENABLE;
9900 switch (intel_crtc->base.cursor->state->crtc_w) {
9901 case 64:
9902 cntl |= CURSOR_MODE_64_ARGB_AX;
9903 break;
9904 case 128:
9905 cntl |= CURSOR_MODE_128_ARGB_AX;
9906 break;
9907 case 256:
9908 cntl |= CURSOR_MODE_256_ARGB_AX;
9909 break;
9910 default:
9911 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9912 return;
9913 }
9914 cntl |= pipe << 28; /* Connect to correct pipe */
9915
9916 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9917 cntl |= CURSOR_PIPE_CSC_ENABLE;
9918 }
9919
9920 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9921 cntl |= CURSOR_ROTATE_180;
9922
9923 if (intel_crtc->cursor_cntl != cntl) {
9924 I915_WRITE(CURCNTR(pipe), cntl);
9925 POSTING_READ(CURCNTR(pipe));
9926 intel_crtc->cursor_cntl = cntl;
9927 }
9928
9929 /* and commit changes on next vblank */
9930 I915_WRITE(CURBASE(pipe), base);
9931 POSTING_READ(CURBASE(pipe));
9932
9933 intel_crtc->cursor_base = base;
9934 }
9935
9936 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9937 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9938 bool on)
9939 {
9940 struct drm_device *dev = crtc->dev;
9941 struct drm_i915_private *dev_priv = dev->dev_private;
9942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9943 int pipe = intel_crtc->pipe;
9944 int x = crtc->cursor_x;
9945 int y = crtc->cursor_y;
9946 u32 base = 0, pos = 0;
9947
9948 if (on)
9949 base = intel_crtc->cursor_addr;
9950
9951 if (x >= intel_crtc->config->pipe_src_w)
9952 base = 0;
9953
9954 if (y >= intel_crtc->config->pipe_src_h)
9955 base = 0;
9956
9957 if (x < 0) {
9958 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9959 base = 0;
9960
9961 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9962 x = -x;
9963 }
9964 pos |= x << CURSOR_X_SHIFT;
9965
9966 if (y < 0) {
9967 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9968 base = 0;
9969
9970 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9971 y = -y;
9972 }
9973 pos |= y << CURSOR_Y_SHIFT;
9974
9975 if (base == 0 && intel_crtc->cursor_base == 0)
9976 return;
9977
9978 I915_WRITE(CURPOS(pipe), pos);
9979
9980 /* ILK+ do this automagically */
9981 if (HAS_GMCH_DISPLAY(dev) &&
9982 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9983 base += (intel_crtc->base.cursor->state->crtc_h *
9984 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9985 }
9986
9987 if (IS_845G(dev) || IS_I865G(dev))
9988 i845_update_cursor(crtc, base);
9989 else
9990 i9xx_update_cursor(crtc, base);
9991 }
9992
9993 static bool cursor_size_ok(struct drm_device *dev,
9994 uint32_t width, uint32_t height)
9995 {
9996 if (width == 0 || height == 0)
9997 return false;
9998
9999 /*
10000 * 845g/865g are special in that they are only limited by
10001 * the width of their cursors, the height is arbitrary up to
10002 * the precision of the register. Everything else requires
10003 * square cursors, limited to a few power-of-two sizes.
10004 */
10005 if (IS_845G(dev) || IS_I865G(dev)) {
10006 if ((width & 63) != 0)
10007 return false;
10008
10009 if (width > (IS_845G(dev) ? 64 : 512))
10010 return false;
10011
10012 if (height > 1023)
10013 return false;
10014 } else {
10015 switch (width | height) {
10016 case 256:
10017 case 128:
10018 if (IS_GEN2(dev))
10019 return false;
10020 case 64:
10021 break;
10022 default:
10023 return false;
10024 }
10025 }
10026
10027 return true;
10028 }
10029
10030 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10031 u16 *blue, uint32_t start, uint32_t size)
10032 {
10033 int end = (start + size > 256) ? 256 : start + size, i;
10034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10035
10036 for (i = start; i < end; i++) {
10037 intel_crtc->lut_r[i] = red[i] >> 8;
10038 intel_crtc->lut_g[i] = green[i] >> 8;
10039 intel_crtc->lut_b[i] = blue[i] >> 8;
10040 }
10041
10042 intel_crtc_load_lut(crtc);
10043 }
10044
10045 /* VESA 640x480x72Hz mode to set on the pipe */
10046 static struct drm_display_mode load_detect_mode = {
10047 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10048 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10049 };
10050
10051 struct drm_framebuffer *
10052 __intel_framebuffer_create(struct drm_device *dev,
10053 struct drm_mode_fb_cmd2 *mode_cmd,
10054 struct drm_i915_gem_object *obj)
10055 {
10056 struct intel_framebuffer *intel_fb;
10057 int ret;
10058
10059 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10060 if (!intel_fb) {
10061 drm_gem_object_unreference(&obj->base);
10062 return ERR_PTR(-ENOMEM);
10063 }
10064
10065 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10066 if (ret)
10067 goto err;
10068
10069 return &intel_fb->base;
10070 err:
10071 drm_gem_object_unreference(&obj->base);
10072 kfree(intel_fb);
10073
10074 return ERR_PTR(ret);
10075 }
10076
10077 static struct drm_framebuffer *
10078 intel_framebuffer_create(struct drm_device *dev,
10079 struct drm_mode_fb_cmd2 *mode_cmd,
10080 struct drm_i915_gem_object *obj)
10081 {
10082 struct drm_framebuffer *fb;
10083 int ret;
10084
10085 ret = i915_mutex_lock_interruptible(dev);
10086 if (ret)
10087 return ERR_PTR(ret);
10088 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10089 mutex_unlock(&dev->struct_mutex);
10090
10091 return fb;
10092 }
10093
10094 static u32
10095 intel_framebuffer_pitch_for_width(int width, int bpp)
10096 {
10097 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10098 return ALIGN(pitch, 64);
10099 }
10100
10101 static u32
10102 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10103 {
10104 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10105 return PAGE_ALIGN(pitch * mode->vdisplay);
10106 }
10107
10108 static struct drm_framebuffer *
10109 intel_framebuffer_create_for_mode(struct drm_device *dev,
10110 struct drm_display_mode *mode,
10111 int depth, int bpp)
10112 {
10113 struct drm_i915_gem_object *obj;
10114 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10115
10116 obj = i915_gem_alloc_object(dev,
10117 intel_framebuffer_size_for_mode(mode, bpp));
10118 if (obj == NULL)
10119 return ERR_PTR(-ENOMEM);
10120
10121 mode_cmd.width = mode->hdisplay;
10122 mode_cmd.height = mode->vdisplay;
10123 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10124 bpp);
10125 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10126
10127 return intel_framebuffer_create(dev, &mode_cmd, obj);
10128 }
10129
10130 static struct drm_framebuffer *
10131 mode_fits_in_fbdev(struct drm_device *dev,
10132 struct drm_display_mode *mode)
10133 {
10134 #ifdef CONFIG_DRM_I915_FBDEV
10135 struct drm_i915_private *dev_priv = dev->dev_private;
10136 struct drm_i915_gem_object *obj;
10137 struct drm_framebuffer *fb;
10138
10139 if (!dev_priv->fbdev)
10140 return NULL;
10141
10142 if (!dev_priv->fbdev->fb)
10143 return NULL;
10144
10145 obj = dev_priv->fbdev->fb->obj;
10146 BUG_ON(!obj);
10147
10148 fb = &dev_priv->fbdev->fb->base;
10149 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10150 fb->bits_per_pixel))
10151 return NULL;
10152
10153 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10154 return NULL;
10155
10156 return fb;
10157 #else
10158 return NULL;
10159 #endif
10160 }
10161
10162 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10163 struct drm_crtc *crtc,
10164 struct drm_display_mode *mode,
10165 struct drm_framebuffer *fb,
10166 int x, int y)
10167 {
10168 struct drm_plane_state *plane_state;
10169 int hdisplay, vdisplay;
10170 int ret;
10171
10172 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10173 if (IS_ERR(plane_state))
10174 return PTR_ERR(plane_state);
10175
10176 if (mode)
10177 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10178 else
10179 hdisplay = vdisplay = 0;
10180
10181 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10182 if (ret)
10183 return ret;
10184 drm_atomic_set_fb_for_plane(plane_state, fb);
10185 plane_state->crtc_x = 0;
10186 plane_state->crtc_y = 0;
10187 plane_state->crtc_w = hdisplay;
10188 plane_state->crtc_h = vdisplay;
10189 plane_state->src_x = x << 16;
10190 plane_state->src_y = y << 16;
10191 plane_state->src_w = hdisplay << 16;
10192 plane_state->src_h = vdisplay << 16;
10193
10194 return 0;
10195 }
10196
10197 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10198 struct drm_display_mode *mode,
10199 struct intel_load_detect_pipe *old,
10200 struct drm_modeset_acquire_ctx *ctx)
10201 {
10202 struct intel_crtc *intel_crtc;
10203 struct intel_encoder *intel_encoder =
10204 intel_attached_encoder(connector);
10205 struct drm_crtc *possible_crtc;
10206 struct drm_encoder *encoder = &intel_encoder->base;
10207 struct drm_crtc *crtc = NULL;
10208 struct drm_device *dev = encoder->dev;
10209 struct drm_framebuffer *fb;
10210 struct drm_mode_config *config = &dev->mode_config;
10211 struct drm_atomic_state *state = NULL;
10212 struct drm_connector_state *connector_state;
10213 struct intel_crtc_state *crtc_state;
10214 int ret, i = -1;
10215
10216 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10217 connector->base.id, connector->name,
10218 encoder->base.id, encoder->name);
10219
10220 retry:
10221 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10222 if (ret)
10223 goto fail;
10224
10225 /*
10226 * Algorithm gets a little messy:
10227 *
10228 * - if the connector already has an assigned crtc, use it (but make
10229 * sure it's on first)
10230 *
10231 * - try to find the first unused crtc that can drive this connector,
10232 * and use that if we find one
10233 */
10234
10235 /* See if we already have a CRTC for this connector */
10236 if (encoder->crtc) {
10237 crtc = encoder->crtc;
10238
10239 ret = drm_modeset_lock(&crtc->mutex, ctx);
10240 if (ret)
10241 goto fail;
10242 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10243 if (ret)
10244 goto fail;
10245
10246 old->dpms_mode = connector->dpms;
10247 old->load_detect_temp = false;
10248
10249 /* Make sure the crtc and connector are running */
10250 if (connector->dpms != DRM_MODE_DPMS_ON)
10251 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10252
10253 return true;
10254 }
10255
10256 /* Find an unused one (if possible) */
10257 for_each_crtc(dev, possible_crtc) {
10258 i++;
10259 if (!(encoder->possible_crtcs & (1 << i)))
10260 continue;
10261 if (possible_crtc->state->enable)
10262 continue;
10263
10264 crtc = possible_crtc;
10265 break;
10266 }
10267
10268 /*
10269 * If we didn't find an unused CRTC, don't use any.
10270 */
10271 if (!crtc) {
10272 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10273 goto fail;
10274 }
10275
10276 ret = drm_modeset_lock(&crtc->mutex, ctx);
10277 if (ret)
10278 goto fail;
10279 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10280 if (ret)
10281 goto fail;
10282
10283 intel_crtc = to_intel_crtc(crtc);
10284 old->dpms_mode = connector->dpms;
10285 old->load_detect_temp = true;
10286 old->release_fb = NULL;
10287
10288 state = drm_atomic_state_alloc(dev);
10289 if (!state)
10290 return false;
10291
10292 state->acquire_ctx = ctx;
10293
10294 connector_state = drm_atomic_get_connector_state(state, connector);
10295 if (IS_ERR(connector_state)) {
10296 ret = PTR_ERR(connector_state);
10297 goto fail;
10298 }
10299
10300 connector_state->crtc = crtc;
10301 connector_state->best_encoder = &intel_encoder->base;
10302
10303 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10304 if (IS_ERR(crtc_state)) {
10305 ret = PTR_ERR(crtc_state);
10306 goto fail;
10307 }
10308
10309 crtc_state->base.active = crtc_state->base.enable = true;
10310
10311 if (!mode)
10312 mode = &load_detect_mode;
10313
10314 /* We need a framebuffer large enough to accommodate all accesses
10315 * that the plane may generate whilst we perform load detection.
10316 * We can not rely on the fbcon either being present (we get called
10317 * during its initialisation to detect all boot displays, or it may
10318 * not even exist) or that it is large enough to satisfy the
10319 * requested mode.
10320 */
10321 fb = mode_fits_in_fbdev(dev, mode);
10322 if (fb == NULL) {
10323 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10324 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10325 old->release_fb = fb;
10326 } else
10327 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10328 if (IS_ERR(fb)) {
10329 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10330 goto fail;
10331 }
10332
10333 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10334 if (ret)
10335 goto fail;
10336
10337 drm_mode_copy(&crtc_state->base.mode, mode);
10338
10339 if (drm_atomic_commit(state)) {
10340 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10341 if (old->release_fb)
10342 old->release_fb->funcs->destroy(old->release_fb);
10343 goto fail;
10344 }
10345 crtc->primary->crtc = crtc;
10346
10347 /* let the connector get through one full cycle before testing */
10348 intel_wait_for_vblank(dev, intel_crtc->pipe);
10349 return true;
10350
10351 fail:
10352 drm_atomic_state_free(state);
10353 state = NULL;
10354
10355 if (ret == -EDEADLK) {
10356 drm_modeset_backoff(ctx);
10357 goto retry;
10358 }
10359
10360 return false;
10361 }
10362
10363 void intel_release_load_detect_pipe(struct drm_connector *connector,
10364 struct intel_load_detect_pipe *old,
10365 struct drm_modeset_acquire_ctx *ctx)
10366 {
10367 struct drm_device *dev = connector->dev;
10368 struct intel_encoder *intel_encoder =
10369 intel_attached_encoder(connector);
10370 struct drm_encoder *encoder = &intel_encoder->base;
10371 struct drm_crtc *crtc = encoder->crtc;
10372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10373 struct drm_atomic_state *state;
10374 struct drm_connector_state *connector_state;
10375 struct intel_crtc_state *crtc_state;
10376 int ret;
10377
10378 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10379 connector->base.id, connector->name,
10380 encoder->base.id, encoder->name);
10381
10382 if (old->load_detect_temp) {
10383 state = drm_atomic_state_alloc(dev);
10384 if (!state)
10385 goto fail;
10386
10387 state->acquire_ctx = ctx;
10388
10389 connector_state = drm_atomic_get_connector_state(state, connector);
10390 if (IS_ERR(connector_state))
10391 goto fail;
10392
10393 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10394 if (IS_ERR(crtc_state))
10395 goto fail;
10396
10397 connector_state->best_encoder = NULL;
10398 connector_state->crtc = NULL;
10399
10400 crtc_state->base.enable = crtc_state->base.active = false;
10401
10402 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10403 0, 0);
10404 if (ret)
10405 goto fail;
10406
10407 ret = drm_atomic_commit(state);
10408 if (ret)
10409 goto fail;
10410
10411 if (old->release_fb) {
10412 drm_framebuffer_unregister_private(old->release_fb);
10413 drm_framebuffer_unreference(old->release_fb);
10414 }
10415
10416 return;
10417 }
10418
10419 /* Switch crtc and encoder back off if necessary */
10420 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10421 connector->funcs->dpms(connector, old->dpms_mode);
10422
10423 return;
10424 fail:
10425 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10426 drm_atomic_state_free(state);
10427 }
10428
10429 static int i9xx_pll_refclk(struct drm_device *dev,
10430 const struct intel_crtc_state *pipe_config)
10431 {
10432 struct drm_i915_private *dev_priv = dev->dev_private;
10433 u32 dpll = pipe_config->dpll_hw_state.dpll;
10434
10435 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10436 return dev_priv->vbt.lvds_ssc_freq;
10437 else if (HAS_PCH_SPLIT(dev))
10438 return 120000;
10439 else if (!IS_GEN2(dev))
10440 return 96000;
10441 else
10442 return 48000;
10443 }
10444
10445 /* Returns the clock of the currently programmed mode of the given pipe. */
10446 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10447 struct intel_crtc_state *pipe_config)
10448 {
10449 struct drm_device *dev = crtc->base.dev;
10450 struct drm_i915_private *dev_priv = dev->dev_private;
10451 int pipe = pipe_config->cpu_transcoder;
10452 u32 dpll = pipe_config->dpll_hw_state.dpll;
10453 u32 fp;
10454 intel_clock_t clock;
10455 int port_clock;
10456 int refclk = i9xx_pll_refclk(dev, pipe_config);
10457
10458 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10459 fp = pipe_config->dpll_hw_state.fp0;
10460 else
10461 fp = pipe_config->dpll_hw_state.fp1;
10462
10463 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10464 if (IS_PINEVIEW(dev)) {
10465 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10466 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10467 } else {
10468 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10469 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10470 }
10471
10472 if (!IS_GEN2(dev)) {
10473 if (IS_PINEVIEW(dev))
10474 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10475 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10476 else
10477 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10478 DPLL_FPA01_P1_POST_DIV_SHIFT);
10479
10480 switch (dpll & DPLL_MODE_MASK) {
10481 case DPLLB_MODE_DAC_SERIAL:
10482 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10483 5 : 10;
10484 break;
10485 case DPLLB_MODE_LVDS:
10486 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10487 7 : 14;
10488 break;
10489 default:
10490 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10491 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10492 return;
10493 }
10494
10495 if (IS_PINEVIEW(dev))
10496 port_clock = pnv_calc_dpll_params(refclk, &clock);
10497 else
10498 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10499 } else {
10500 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10501 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10502
10503 if (is_lvds) {
10504 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10505 DPLL_FPA01_P1_POST_DIV_SHIFT);
10506
10507 if (lvds & LVDS_CLKB_POWER_UP)
10508 clock.p2 = 7;
10509 else
10510 clock.p2 = 14;
10511 } else {
10512 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10513 clock.p1 = 2;
10514 else {
10515 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10516 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10517 }
10518 if (dpll & PLL_P2_DIVIDE_BY_4)
10519 clock.p2 = 4;
10520 else
10521 clock.p2 = 2;
10522 }
10523
10524 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10525 }
10526
10527 /*
10528 * This value includes pixel_multiplier. We will use
10529 * port_clock to compute adjusted_mode.crtc_clock in the
10530 * encoder's get_config() function.
10531 */
10532 pipe_config->port_clock = port_clock;
10533 }
10534
10535 int intel_dotclock_calculate(int link_freq,
10536 const struct intel_link_m_n *m_n)
10537 {
10538 /*
10539 * The calculation for the data clock is:
10540 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10541 * But we want to avoid losing precison if possible, so:
10542 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10543 *
10544 * and the link clock is simpler:
10545 * link_clock = (m * link_clock) / n
10546 */
10547
10548 if (!m_n->link_n)
10549 return 0;
10550
10551 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10552 }
10553
10554 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10555 struct intel_crtc_state *pipe_config)
10556 {
10557 struct drm_device *dev = crtc->base.dev;
10558
10559 /* read out port_clock from the DPLL */
10560 i9xx_crtc_clock_get(crtc, pipe_config);
10561
10562 /*
10563 * This value does not include pixel_multiplier.
10564 * We will check that port_clock and adjusted_mode.crtc_clock
10565 * agree once we know their relationship in the encoder's
10566 * get_config() function.
10567 */
10568 pipe_config->base.adjusted_mode.crtc_clock =
10569 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10570 &pipe_config->fdi_m_n);
10571 }
10572
10573 /** Returns the currently programmed mode of the given pipe. */
10574 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10575 struct drm_crtc *crtc)
10576 {
10577 struct drm_i915_private *dev_priv = dev->dev_private;
10578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10579 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10580 struct drm_display_mode *mode;
10581 struct intel_crtc_state pipe_config;
10582 int htot = I915_READ(HTOTAL(cpu_transcoder));
10583 int hsync = I915_READ(HSYNC(cpu_transcoder));
10584 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10585 int vsync = I915_READ(VSYNC(cpu_transcoder));
10586 enum pipe pipe = intel_crtc->pipe;
10587
10588 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10589 if (!mode)
10590 return NULL;
10591
10592 /*
10593 * Construct a pipe_config sufficient for getting the clock info
10594 * back out of crtc_clock_get.
10595 *
10596 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10597 * to use a real value here instead.
10598 */
10599 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10600 pipe_config.pixel_multiplier = 1;
10601 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10602 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10603 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10604 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10605
10606 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10607 mode->hdisplay = (htot & 0xffff) + 1;
10608 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10609 mode->hsync_start = (hsync & 0xffff) + 1;
10610 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10611 mode->vdisplay = (vtot & 0xffff) + 1;
10612 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10613 mode->vsync_start = (vsync & 0xffff) + 1;
10614 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10615
10616 drm_mode_set_name(mode);
10617
10618 return mode;
10619 }
10620
10621 void intel_mark_busy(struct drm_device *dev)
10622 {
10623 struct drm_i915_private *dev_priv = dev->dev_private;
10624
10625 if (dev_priv->mm.busy)
10626 return;
10627
10628 intel_runtime_pm_get(dev_priv);
10629 i915_update_gfx_val(dev_priv);
10630 if (INTEL_INFO(dev)->gen >= 6)
10631 gen6_rps_busy(dev_priv);
10632 dev_priv->mm.busy = true;
10633 }
10634
10635 void intel_mark_idle(struct drm_device *dev)
10636 {
10637 struct drm_i915_private *dev_priv = dev->dev_private;
10638
10639 if (!dev_priv->mm.busy)
10640 return;
10641
10642 dev_priv->mm.busy = false;
10643
10644 if (INTEL_INFO(dev)->gen >= 6)
10645 gen6_rps_idle(dev->dev_private);
10646
10647 intel_runtime_pm_put(dev_priv);
10648 }
10649
10650 static void intel_crtc_destroy(struct drm_crtc *crtc)
10651 {
10652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10653 struct drm_device *dev = crtc->dev;
10654 struct intel_unpin_work *work;
10655
10656 spin_lock_irq(&dev->event_lock);
10657 work = intel_crtc->unpin_work;
10658 intel_crtc->unpin_work = NULL;
10659 spin_unlock_irq(&dev->event_lock);
10660
10661 if (work) {
10662 cancel_work_sync(&work->work);
10663 kfree(work);
10664 }
10665
10666 drm_crtc_cleanup(crtc);
10667
10668 kfree(intel_crtc);
10669 }
10670
10671 static void intel_unpin_work_fn(struct work_struct *__work)
10672 {
10673 struct intel_unpin_work *work =
10674 container_of(__work, struct intel_unpin_work, work);
10675 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10676 struct drm_device *dev = crtc->base.dev;
10677 struct drm_plane *primary = crtc->base.primary;
10678
10679 mutex_lock(&dev->struct_mutex);
10680 intel_unpin_fb_obj(work->old_fb, primary->state);
10681 drm_gem_object_unreference(&work->pending_flip_obj->base);
10682
10683 if (work->flip_queued_req)
10684 i915_gem_request_assign(&work->flip_queued_req, NULL);
10685 mutex_unlock(&dev->struct_mutex);
10686
10687 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10688 drm_framebuffer_unreference(work->old_fb);
10689
10690 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10691 atomic_dec(&crtc->unpin_work_count);
10692
10693 kfree(work);
10694 }
10695
10696 static void do_intel_finish_page_flip(struct drm_device *dev,
10697 struct drm_crtc *crtc)
10698 {
10699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10700 struct intel_unpin_work *work;
10701 unsigned long flags;
10702
10703 /* Ignore early vblank irqs */
10704 if (intel_crtc == NULL)
10705 return;
10706
10707 /*
10708 * This is called both by irq handlers and the reset code (to complete
10709 * lost pageflips) so needs the full irqsave spinlocks.
10710 */
10711 spin_lock_irqsave(&dev->event_lock, flags);
10712 work = intel_crtc->unpin_work;
10713
10714 /* Ensure we don't miss a work->pending update ... */
10715 smp_rmb();
10716
10717 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10718 spin_unlock_irqrestore(&dev->event_lock, flags);
10719 return;
10720 }
10721
10722 page_flip_completed(intel_crtc);
10723
10724 spin_unlock_irqrestore(&dev->event_lock, flags);
10725 }
10726
10727 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10728 {
10729 struct drm_i915_private *dev_priv = dev->dev_private;
10730 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10731
10732 do_intel_finish_page_flip(dev, crtc);
10733 }
10734
10735 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10736 {
10737 struct drm_i915_private *dev_priv = dev->dev_private;
10738 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10739
10740 do_intel_finish_page_flip(dev, crtc);
10741 }
10742
10743 /* Is 'a' after or equal to 'b'? */
10744 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10745 {
10746 return !((a - b) & 0x80000000);
10747 }
10748
10749 static bool page_flip_finished(struct intel_crtc *crtc)
10750 {
10751 struct drm_device *dev = crtc->base.dev;
10752 struct drm_i915_private *dev_priv = dev->dev_private;
10753
10754 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10755 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10756 return true;
10757
10758 /*
10759 * The relevant registers doen't exist on pre-ctg.
10760 * As the flip done interrupt doesn't trigger for mmio
10761 * flips on gmch platforms, a flip count check isn't
10762 * really needed there. But since ctg has the registers,
10763 * include it in the check anyway.
10764 */
10765 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10766 return true;
10767
10768 /*
10769 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10770 * used the same base address. In that case the mmio flip might
10771 * have completed, but the CS hasn't even executed the flip yet.
10772 *
10773 * A flip count check isn't enough as the CS might have updated
10774 * the base address just after start of vblank, but before we
10775 * managed to process the interrupt. This means we'd complete the
10776 * CS flip too soon.
10777 *
10778 * Combining both checks should get us a good enough result. It may
10779 * still happen that the CS flip has been executed, but has not
10780 * yet actually completed. But in case the base address is the same
10781 * anyway, we don't really care.
10782 */
10783 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10784 crtc->unpin_work->gtt_offset &&
10785 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10786 crtc->unpin_work->flip_count);
10787 }
10788
10789 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10790 {
10791 struct drm_i915_private *dev_priv = dev->dev_private;
10792 struct intel_crtc *intel_crtc =
10793 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10794 unsigned long flags;
10795
10796
10797 /*
10798 * This is called both by irq handlers and the reset code (to complete
10799 * lost pageflips) so needs the full irqsave spinlocks.
10800 *
10801 * NB: An MMIO update of the plane base pointer will also
10802 * generate a page-flip completion irq, i.e. every modeset
10803 * is also accompanied by a spurious intel_prepare_page_flip().
10804 */
10805 spin_lock_irqsave(&dev->event_lock, flags);
10806 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10807 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10808 spin_unlock_irqrestore(&dev->event_lock, flags);
10809 }
10810
10811 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10812 {
10813 /* Ensure that the work item is consistent when activating it ... */
10814 smp_wmb();
10815 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10816 /* and that it is marked active as soon as the irq could fire. */
10817 smp_wmb();
10818 }
10819
10820 static int intel_gen2_queue_flip(struct drm_device *dev,
10821 struct drm_crtc *crtc,
10822 struct drm_framebuffer *fb,
10823 struct drm_i915_gem_object *obj,
10824 struct drm_i915_gem_request *req,
10825 uint32_t flags)
10826 {
10827 struct intel_engine_cs *ring = req->ring;
10828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10829 u32 flip_mask;
10830 int ret;
10831
10832 ret = intel_ring_begin(req, 6);
10833 if (ret)
10834 return ret;
10835
10836 /* Can't queue multiple flips, so wait for the previous
10837 * one to finish before executing the next.
10838 */
10839 if (intel_crtc->plane)
10840 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10841 else
10842 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10843 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10844 intel_ring_emit(ring, MI_NOOP);
10845 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10846 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10847 intel_ring_emit(ring, fb->pitches[0]);
10848 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10849 intel_ring_emit(ring, 0); /* aux display base address, unused */
10850
10851 intel_mark_page_flip_active(intel_crtc);
10852 return 0;
10853 }
10854
10855 static int intel_gen3_queue_flip(struct drm_device *dev,
10856 struct drm_crtc *crtc,
10857 struct drm_framebuffer *fb,
10858 struct drm_i915_gem_object *obj,
10859 struct drm_i915_gem_request *req,
10860 uint32_t flags)
10861 {
10862 struct intel_engine_cs *ring = req->ring;
10863 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10864 u32 flip_mask;
10865 int ret;
10866
10867 ret = intel_ring_begin(req, 6);
10868 if (ret)
10869 return ret;
10870
10871 if (intel_crtc->plane)
10872 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10873 else
10874 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10875 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10876 intel_ring_emit(ring, MI_NOOP);
10877 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10878 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10879 intel_ring_emit(ring, fb->pitches[0]);
10880 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10881 intel_ring_emit(ring, MI_NOOP);
10882
10883 intel_mark_page_flip_active(intel_crtc);
10884 return 0;
10885 }
10886
10887 static int intel_gen4_queue_flip(struct drm_device *dev,
10888 struct drm_crtc *crtc,
10889 struct drm_framebuffer *fb,
10890 struct drm_i915_gem_object *obj,
10891 struct drm_i915_gem_request *req,
10892 uint32_t flags)
10893 {
10894 struct intel_engine_cs *ring = req->ring;
10895 struct drm_i915_private *dev_priv = dev->dev_private;
10896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10897 uint32_t pf, pipesrc;
10898 int ret;
10899
10900 ret = intel_ring_begin(req, 4);
10901 if (ret)
10902 return ret;
10903
10904 /* i965+ uses the linear or tiled offsets from the
10905 * Display Registers (which do not change across a page-flip)
10906 * so we need only reprogram the base address.
10907 */
10908 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10909 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10910 intel_ring_emit(ring, fb->pitches[0]);
10911 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10912 obj->tiling_mode);
10913
10914 /* XXX Enabling the panel-fitter across page-flip is so far
10915 * untested on non-native modes, so ignore it for now.
10916 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10917 */
10918 pf = 0;
10919 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10920 intel_ring_emit(ring, pf | pipesrc);
10921
10922 intel_mark_page_flip_active(intel_crtc);
10923 return 0;
10924 }
10925
10926 static int intel_gen6_queue_flip(struct drm_device *dev,
10927 struct drm_crtc *crtc,
10928 struct drm_framebuffer *fb,
10929 struct drm_i915_gem_object *obj,
10930 struct drm_i915_gem_request *req,
10931 uint32_t flags)
10932 {
10933 struct intel_engine_cs *ring = req->ring;
10934 struct drm_i915_private *dev_priv = dev->dev_private;
10935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10936 uint32_t pf, pipesrc;
10937 int ret;
10938
10939 ret = intel_ring_begin(req, 4);
10940 if (ret)
10941 return ret;
10942
10943 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10944 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10945 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10946 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10947
10948 /* Contrary to the suggestions in the documentation,
10949 * "Enable Panel Fitter" does not seem to be required when page
10950 * flipping with a non-native mode, and worse causes a normal
10951 * modeset to fail.
10952 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10953 */
10954 pf = 0;
10955 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10956 intel_ring_emit(ring, pf | pipesrc);
10957
10958 intel_mark_page_flip_active(intel_crtc);
10959 return 0;
10960 }
10961
10962 static int intel_gen7_queue_flip(struct drm_device *dev,
10963 struct drm_crtc *crtc,
10964 struct drm_framebuffer *fb,
10965 struct drm_i915_gem_object *obj,
10966 struct drm_i915_gem_request *req,
10967 uint32_t flags)
10968 {
10969 struct intel_engine_cs *ring = req->ring;
10970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10971 uint32_t plane_bit = 0;
10972 int len, ret;
10973
10974 switch (intel_crtc->plane) {
10975 case PLANE_A:
10976 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10977 break;
10978 case PLANE_B:
10979 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10980 break;
10981 case PLANE_C:
10982 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10983 break;
10984 default:
10985 WARN_ONCE(1, "unknown plane in flip command\n");
10986 return -ENODEV;
10987 }
10988
10989 len = 4;
10990 if (ring->id == RCS) {
10991 len += 6;
10992 /*
10993 * On Gen 8, SRM is now taking an extra dword to accommodate
10994 * 48bits addresses, and we need a NOOP for the batch size to
10995 * stay even.
10996 */
10997 if (IS_GEN8(dev))
10998 len += 2;
10999 }
11000
11001 /*
11002 * BSpec MI_DISPLAY_FLIP for IVB:
11003 * "The full packet must be contained within the same cache line."
11004 *
11005 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11006 * cacheline, if we ever start emitting more commands before
11007 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11008 * then do the cacheline alignment, and finally emit the
11009 * MI_DISPLAY_FLIP.
11010 */
11011 ret = intel_ring_cacheline_align(req);
11012 if (ret)
11013 return ret;
11014
11015 ret = intel_ring_begin(req, len);
11016 if (ret)
11017 return ret;
11018
11019 /* Unmask the flip-done completion message. Note that the bspec says that
11020 * we should do this for both the BCS and RCS, and that we must not unmask
11021 * more than one flip event at any time (or ensure that one flip message
11022 * can be sent by waiting for flip-done prior to queueing new flips).
11023 * Experimentation says that BCS works despite DERRMR masking all
11024 * flip-done completion events and that unmasking all planes at once
11025 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11026 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11027 */
11028 if (ring->id == RCS) {
11029 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11030 intel_ring_emit(ring, DERRMR);
11031 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11032 DERRMR_PIPEB_PRI_FLIP_DONE |
11033 DERRMR_PIPEC_PRI_FLIP_DONE));
11034 if (IS_GEN8(dev))
11035 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11036 MI_SRM_LRM_GLOBAL_GTT);
11037 else
11038 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11039 MI_SRM_LRM_GLOBAL_GTT);
11040 intel_ring_emit(ring, DERRMR);
11041 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11042 if (IS_GEN8(dev)) {
11043 intel_ring_emit(ring, 0);
11044 intel_ring_emit(ring, MI_NOOP);
11045 }
11046 }
11047
11048 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11049 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11050 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11051 intel_ring_emit(ring, (MI_NOOP));
11052
11053 intel_mark_page_flip_active(intel_crtc);
11054 return 0;
11055 }
11056
11057 static bool use_mmio_flip(struct intel_engine_cs *ring,
11058 struct drm_i915_gem_object *obj)
11059 {
11060 /*
11061 * This is not being used for older platforms, because
11062 * non-availability of flip done interrupt forces us to use
11063 * CS flips. Older platforms derive flip done using some clever
11064 * tricks involving the flip_pending status bits and vblank irqs.
11065 * So using MMIO flips there would disrupt this mechanism.
11066 */
11067
11068 if (ring == NULL)
11069 return true;
11070
11071 if (INTEL_INFO(ring->dev)->gen < 5)
11072 return false;
11073
11074 if (i915.use_mmio_flip < 0)
11075 return false;
11076 else if (i915.use_mmio_flip > 0)
11077 return true;
11078 else if (i915.enable_execlists)
11079 return true;
11080 else
11081 return ring != i915_gem_request_get_ring(obj->last_write_req);
11082 }
11083
11084 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11085 {
11086 struct drm_device *dev = intel_crtc->base.dev;
11087 struct drm_i915_private *dev_priv = dev->dev_private;
11088 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11089 const enum pipe pipe = intel_crtc->pipe;
11090 u32 ctl, stride;
11091
11092 ctl = I915_READ(PLANE_CTL(pipe, 0));
11093 ctl &= ~PLANE_CTL_TILED_MASK;
11094 switch (fb->modifier[0]) {
11095 case DRM_FORMAT_MOD_NONE:
11096 break;
11097 case I915_FORMAT_MOD_X_TILED:
11098 ctl |= PLANE_CTL_TILED_X;
11099 break;
11100 case I915_FORMAT_MOD_Y_TILED:
11101 ctl |= PLANE_CTL_TILED_Y;
11102 break;
11103 case I915_FORMAT_MOD_Yf_TILED:
11104 ctl |= PLANE_CTL_TILED_YF;
11105 break;
11106 default:
11107 MISSING_CASE(fb->modifier[0]);
11108 }
11109
11110 /*
11111 * The stride is either expressed as a multiple of 64 bytes chunks for
11112 * linear buffers or in number of tiles for tiled buffers.
11113 */
11114 stride = fb->pitches[0] /
11115 intel_fb_stride_alignment(dev, fb->modifier[0],
11116 fb->pixel_format);
11117
11118 /*
11119 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11120 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11121 */
11122 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11123 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11124
11125 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11126 POSTING_READ(PLANE_SURF(pipe, 0));
11127 }
11128
11129 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11130 {
11131 struct drm_device *dev = intel_crtc->base.dev;
11132 struct drm_i915_private *dev_priv = dev->dev_private;
11133 struct intel_framebuffer *intel_fb =
11134 to_intel_framebuffer(intel_crtc->base.primary->fb);
11135 struct drm_i915_gem_object *obj = intel_fb->obj;
11136 u32 dspcntr;
11137 u32 reg;
11138
11139 reg = DSPCNTR(intel_crtc->plane);
11140 dspcntr = I915_READ(reg);
11141
11142 if (obj->tiling_mode != I915_TILING_NONE)
11143 dspcntr |= DISPPLANE_TILED;
11144 else
11145 dspcntr &= ~DISPPLANE_TILED;
11146
11147 I915_WRITE(reg, dspcntr);
11148
11149 I915_WRITE(DSPSURF(intel_crtc->plane),
11150 intel_crtc->unpin_work->gtt_offset);
11151 POSTING_READ(DSPSURF(intel_crtc->plane));
11152
11153 }
11154
11155 /*
11156 * XXX: This is the temporary way to update the plane registers until we get
11157 * around to using the usual plane update functions for MMIO flips
11158 */
11159 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11160 {
11161 struct drm_device *dev = intel_crtc->base.dev;
11162 u32 start_vbl_count;
11163
11164 intel_mark_page_flip_active(intel_crtc);
11165
11166 intel_pipe_update_start(intel_crtc, &start_vbl_count);
11167
11168 if (INTEL_INFO(dev)->gen >= 9)
11169 skl_do_mmio_flip(intel_crtc);
11170 else
11171 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11172 ilk_do_mmio_flip(intel_crtc);
11173
11174 intel_pipe_update_end(intel_crtc, start_vbl_count);
11175 }
11176
11177 static void intel_mmio_flip_work_func(struct work_struct *work)
11178 {
11179 struct intel_mmio_flip *mmio_flip =
11180 container_of(work, struct intel_mmio_flip, work);
11181
11182 if (mmio_flip->req)
11183 WARN_ON(__i915_wait_request(mmio_flip->req,
11184 mmio_flip->crtc->reset_counter,
11185 false, NULL,
11186 &mmio_flip->i915->rps.mmioflips));
11187
11188 intel_do_mmio_flip(mmio_flip->crtc);
11189
11190 i915_gem_request_unreference__unlocked(mmio_flip->req);
11191 kfree(mmio_flip);
11192 }
11193
11194 static int intel_queue_mmio_flip(struct drm_device *dev,
11195 struct drm_crtc *crtc,
11196 struct drm_framebuffer *fb,
11197 struct drm_i915_gem_object *obj,
11198 struct intel_engine_cs *ring,
11199 uint32_t flags)
11200 {
11201 struct intel_mmio_flip *mmio_flip;
11202
11203 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11204 if (mmio_flip == NULL)
11205 return -ENOMEM;
11206
11207 mmio_flip->i915 = to_i915(dev);
11208 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11209 mmio_flip->crtc = to_intel_crtc(crtc);
11210
11211 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11212 schedule_work(&mmio_flip->work);
11213
11214 return 0;
11215 }
11216
11217 static int intel_default_queue_flip(struct drm_device *dev,
11218 struct drm_crtc *crtc,
11219 struct drm_framebuffer *fb,
11220 struct drm_i915_gem_object *obj,
11221 struct drm_i915_gem_request *req,
11222 uint32_t flags)
11223 {
11224 return -ENODEV;
11225 }
11226
11227 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11228 struct drm_crtc *crtc)
11229 {
11230 struct drm_i915_private *dev_priv = dev->dev_private;
11231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11232 struct intel_unpin_work *work = intel_crtc->unpin_work;
11233 u32 addr;
11234
11235 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11236 return true;
11237
11238 if (!work->enable_stall_check)
11239 return false;
11240
11241 if (work->flip_ready_vblank == 0) {
11242 if (work->flip_queued_req &&
11243 !i915_gem_request_completed(work->flip_queued_req, true))
11244 return false;
11245
11246 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11247 }
11248
11249 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11250 return false;
11251
11252 /* Potential stall - if we see that the flip has happened,
11253 * assume a missed interrupt. */
11254 if (INTEL_INFO(dev)->gen >= 4)
11255 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11256 else
11257 addr = I915_READ(DSPADDR(intel_crtc->plane));
11258
11259 /* There is a potential issue here with a false positive after a flip
11260 * to the same address. We could address this by checking for a
11261 * non-incrementing frame counter.
11262 */
11263 return addr == work->gtt_offset;
11264 }
11265
11266 void intel_check_page_flip(struct drm_device *dev, int pipe)
11267 {
11268 struct drm_i915_private *dev_priv = dev->dev_private;
11269 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11271 struct intel_unpin_work *work;
11272
11273 WARN_ON(!in_interrupt());
11274
11275 if (crtc == NULL)
11276 return;
11277
11278 spin_lock(&dev->event_lock);
11279 work = intel_crtc->unpin_work;
11280 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11281 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11282 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11283 page_flip_completed(intel_crtc);
11284 work = NULL;
11285 }
11286 if (work != NULL &&
11287 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11288 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11289 spin_unlock(&dev->event_lock);
11290 }
11291
11292 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11293 struct drm_framebuffer *fb,
11294 struct drm_pending_vblank_event *event,
11295 uint32_t page_flip_flags)
11296 {
11297 struct drm_device *dev = crtc->dev;
11298 struct drm_i915_private *dev_priv = dev->dev_private;
11299 struct drm_framebuffer *old_fb = crtc->primary->fb;
11300 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11301 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11302 struct drm_plane *primary = crtc->primary;
11303 enum pipe pipe = intel_crtc->pipe;
11304 struct intel_unpin_work *work;
11305 struct intel_engine_cs *ring;
11306 bool mmio_flip;
11307 struct drm_i915_gem_request *request = NULL;
11308 int ret;
11309
11310 /*
11311 * drm_mode_page_flip_ioctl() should already catch this, but double
11312 * check to be safe. In the future we may enable pageflipping from
11313 * a disabled primary plane.
11314 */
11315 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11316 return -EBUSY;
11317
11318 /* Can't change pixel format via MI display flips. */
11319 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11320 return -EINVAL;
11321
11322 /*
11323 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11324 * Note that pitch changes could also affect these register.
11325 */
11326 if (INTEL_INFO(dev)->gen > 3 &&
11327 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11328 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11329 return -EINVAL;
11330
11331 if (i915_terminally_wedged(&dev_priv->gpu_error))
11332 goto out_hang;
11333
11334 work = kzalloc(sizeof(*work), GFP_KERNEL);
11335 if (work == NULL)
11336 return -ENOMEM;
11337
11338 work->event = event;
11339 work->crtc = crtc;
11340 work->old_fb = old_fb;
11341 INIT_WORK(&work->work, intel_unpin_work_fn);
11342
11343 ret = drm_crtc_vblank_get(crtc);
11344 if (ret)
11345 goto free_work;
11346
11347 /* We borrow the event spin lock for protecting unpin_work */
11348 spin_lock_irq(&dev->event_lock);
11349 if (intel_crtc->unpin_work) {
11350 /* Before declaring the flip queue wedged, check if
11351 * the hardware completed the operation behind our backs.
11352 */
11353 if (__intel_pageflip_stall_check(dev, crtc)) {
11354 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11355 page_flip_completed(intel_crtc);
11356 } else {
11357 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11358 spin_unlock_irq(&dev->event_lock);
11359
11360 drm_crtc_vblank_put(crtc);
11361 kfree(work);
11362 return -EBUSY;
11363 }
11364 }
11365 intel_crtc->unpin_work = work;
11366 spin_unlock_irq(&dev->event_lock);
11367
11368 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11369 flush_workqueue(dev_priv->wq);
11370
11371 /* Reference the objects for the scheduled work. */
11372 drm_framebuffer_reference(work->old_fb);
11373 drm_gem_object_reference(&obj->base);
11374
11375 crtc->primary->fb = fb;
11376 update_state_fb(crtc->primary);
11377
11378 work->pending_flip_obj = obj;
11379
11380 ret = i915_mutex_lock_interruptible(dev);
11381 if (ret)
11382 goto cleanup;
11383
11384 atomic_inc(&intel_crtc->unpin_work_count);
11385 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11386
11387 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11388 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11389
11390 if (IS_VALLEYVIEW(dev)) {
11391 ring = &dev_priv->ring[BCS];
11392 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11393 /* vlv: DISPLAY_FLIP fails to change tiling */
11394 ring = NULL;
11395 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11396 ring = &dev_priv->ring[BCS];
11397 } else if (INTEL_INFO(dev)->gen >= 7) {
11398 ring = i915_gem_request_get_ring(obj->last_write_req);
11399 if (ring == NULL || ring->id != RCS)
11400 ring = &dev_priv->ring[BCS];
11401 } else {
11402 ring = &dev_priv->ring[RCS];
11403 }
11404
11405 mmio_flip = use_mmio_flip(ring, obj);
11406
11407 /* When using CS flips, we want to emit semaphores between rings.
11408 * However, when using mmio flips we will create a task to do the
11409 * synchronisation, so all we want here is to pin the framebuffer
11410 * into the display plane and skip any waits.
11411 */
11412 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11413 crtc->primary->state,
11414 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11415 if (ret)
11416 goto cleanup_pending;
11417
11418 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11419 + intel_crtc->dspaddr_offset;
11420
11421 if (mmio_flip) {
11422 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11423 page_flip_flags);
11424 if (ret)
11425 goto cleanup_unpin;
11426
11427 i915_gem_request_assign(&work->flip_queued_req,
11428 obj->last_write_req);
11429 } else {
11430 if (!request) {
11431 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11432 if (ret)
11433 goto cleanup_unpin;
11434 }
11435
11436 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11437 page_flip_flags);
11438 if (ret)
11439 goto cleanup_unpin;
11440
11441 i915_gem_request_assign(&work->flip_queued_req, request);
11442 }
11443
11444 if (request)
11445 i915_add_request_no_flush(request);
11446
11447 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11448 work->enable_stall_check = true;
11449
11450 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11451 to_intel_plane(primary)->frontbuffer_bit);
11452 mutex_unlock(&dev->struct_mutex);
11453
11454 intel_fbc_disable_crtc(intel_crtc);
11455 intel_frontbuffer_flip_prepare(dev,
11456 to_intel_plane(primary)->frontbuffer_bit);
11457
11458 trace_i915_flip_request(intel_crtc->plane, obj);
11459
11460 return 0;
11461
11462 cleanup_unpin:
11463 intel_unpin_fb_obj(fb, crtc->primary->state);
11464 cleanup_pending:
11465 if (request)
11466 i915_gem_request_cancel(request);
11467 atomic_dec(&intel_crtc->unpin_work_count);
11468 mutex_unlock(&dev->struct_mutex);
11469 cleanup:
11470 crtc->primary->fb = old_fb;
11471 update_state_fb(crtc->primary);
11472
11473 drm_gem_object_unreference_unlocked(&obj->base);
11474 drm_framebuffer_unreference(work->old_fb);
11475
11476 spin_lock_irq(&dev->event_lock);
11477 intel_crtc->unpin_work = NULL;
11478 spin_unlock_irq(&dev->event_lock);
11479
11480 drm_crtc_vblank_put(crtc);
11481 free_work:
11482 kfree(work);
11483
11484 if (ret == -EIO) {
11485 struct drm_atomic_state *state;
11486 struct drm_plane_state *plane_state;
11487
11488 out_hang:
11489 state = drm_atomic_state_alloc(dev);
11490 if (!state)
11491 return -ENOMEM;
11492 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11493
11494 retry:
11495 plane_state = drm_atomic_get_plane_state(state, primary);
11496 ret = PTR_ERR_OR_ZERO(plane_state);
11497 if (!ret) {
11498 drm_atomic_set_fb_for_plane(plane_state, fb);
11499
11500 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11501 if (!ret)
11502 ret = drm_atomic_commit(state);
11503 }
11504
11505 if (ret == -EDEADLK) {
11506 drm_modeset_backoff(state->acquire_ctx);
11507 drm_atomic_state_clear(state);
11508 goto retry;
11509 }
11510
11511 if (ret)
11512 drm_atomic_state_free(state);
11513
11514 if (ret == 0 && event) {
11515 spin_lock_irq(&dev->event_lock);
11516 drm_send_vblank_event(dev, pipe, event);
11517 spin_unlock_irq(&dev->event_lock);
11518 }
11519 }
11520 return ret;
11521 }
11522
11523
11524 /**
11525 * intel_wm_need_update - Check whether watermarks need updating
11526 * @plane: drm plane
11527 * @state: new plane state
11528 *
11529 * Check current plane state versus the new one to determine whether
11530 * watermarks need to be recalculated.
11531 *
11532 * Returns true or false.
11533 */
11534 static bool intel_wm_need_update(struct drm_plane *plane,
11535 struct drm_plane_state *state)
11536 {
11537 /* Update watermarks on tiling changes. */
11538 if (!plane->state->fb || !state->fb ||
11539 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11540 plane->state->rotation != state->rotation)
11541 return true;
11542
11543 if (plane->state->crtc_w != state->crtc_w)
11544 return true;
11545
11546 return false;
11547 }
11548
11549 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11550 struct drm_plane_state *plane_state)
11551 {
11552 struct drm_crtc *crtc = crtc_state->crtc;
11553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11554 struct drm_plane *plane = plane_state->plane;
11555 struct drm_device *dev = crtc->dev;
11556 struct drm_i915_private *dev_priv = dev->dev_private;
11557 struct intel_plane_state *old_plane_state =
11558 to_intel_plane_state(plane->state);
11559 int idx = intel_crtc->base.base.id, ret;
11560 int i = drm_plane_index(plane);
11561 bool mode_changed = needs_modeset(crtc_state);
11562 bool was_crtc_enabled = crtc->state->active;
11563 bool is_crtc_enabled = crtc_state->active;
11564
11565 bool turn_off, turn_on, visible, was_visible;
11566 struct drm_framebuffer *fb = plane_state->fb;
11567
11568 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11569 plane->type != DRM_PLANE_TYPE_CURSOR) {
11570 ret = skl_update_scaler_plane(
11571 to_intel_crtc_state(crtc_state),
11572 to_intel_plane_state(plane_state));
11573 if (ret)
11574 return ret;
11575 }
11576
11577 /*
11578 * Disabling a plane is always okay; we just need to update
11579 * fb tracking in a special way since cleanup_fb() won't
11580 * get called by the plane helpers.
11581 */
11582 if (old_plane_state->base.fb && !fb)
11583 intel_crtc->atomic.disabled_planes |= 1 << i;
11584
11585 was_visible = old_plane_state->visible;
11586 visible = to_intel_plane_state(plane_state)->visible;
11587
11588 if (!was_crtc_enabled && WARN_ON(was_visible))
11589 was_visible = false;
11590
11591 if (!is_crtc_enabled && WARN_ON(visible))
11592 visible = false;
11593
11594 if (!was_visible && !visible)
11595 return 0;
11596
11597 turn_off = was_visible && (!visible || mode_changed);
11598 turn_on = visible && (!was_visible || mode_changed);
11599
11600 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11601 plane->base.id, fb ? fb->base.id : -1);
11602
11603 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11604 plane->base.id, was_visible, visible,
11605 turn_off, turn_on, mode_changed);
11606
11607 if (turn_on) {
11608 intel_crtc->atomic.update_wm_pre = true;
11609 /* must disable cxsr around plane enable/disable */
11610 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11611 intel_crtc->atomic.disable_cxsr = true;
11612 /* to potentially re-enable cxsr */
11613 intel_crtc->atomic.wait_vblank = true;
11614 intel_crtc->atomic.update_wm_post = true;
11615 }
11616 } else if (turn_off) {
11617 intel_crtc->atomic.update_wm_post = true;
11618 /* must disable cxsr around plane enable/disable */
11619 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11620 if (is_crtc_enabled)
11621 intel_crtc->atomic.wait_vblank = true;
11622 intel_crtc->atomic.disable_cxsr = true;
11623 }
11624 } else if (intel_wm_need_update(plane, plane_state)) {
11625 intel_crtc->atomic.update_wm_pre = true;
11626 }
11627
11628 if (visible)
11629 intel_crtc->atomic.fb_bits |=
11630 to_intel_plane(plane)->frontbuffer_bit;
11631
11632 switch (plane->type) {
11633 case DRM_PLANE_TYPE_PRIMARY:
11634 intel_crtc->atomic.wait_for_flips = true;
11635 intel_crtc->atomic.pre_disable_primary = turn_off;
11636 intel_crtc->atomic.post_enable_primary = turn_on;
11637
11638 if (turn_off) {
11639 /*
11640 * FIXME: Actually if we will still have any other
11641 * plane enabled on the pipe we could let IPS enabled
11642 * still, but for now lets consider that when we make
11643 * primary invisible by setting DSPCNTR to 0 on
11644 * update_primary_plane function IPS needs to be
11645 * disable.
11646 */
11647 intel_crtc->atomic.disable_ips = true;
11648
11649 intel_crtc->atomic.disable_fbc = true;
11650 }
11651
11652 /*
11653 * FBC does not work on some platforms for rotated
11654 * planes, so disable it when rotation is not 0 and
11655 * update it when rotation is set back to 0.
11656 *
11657 * FIXME: This is redundant with the fbc update done in
11658 * the primary plane enable function except that that
11659 * one is done too late. We eventually need to unify
11660 * this.
11661 */
11662
11663 if (visible &&
11664 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11665 dev_priv->fbc.crtc == intel_crtc &&
11666 plane_state->rotation != BIT(DRM_ROTATE_0))
11667 intel_crtc->atomic.disable_fbc = true;
11668
11669 /*
11670 * BDW signals flip done immediately if the plane
11671 * is disabled, even if the plane enable is already
11672 * armed to occur at the next vblank :(
11673 */
11674 if (turn_on && IS_BROADWELL(dev))
11675 intel_crtc->atomic.wait_vblank = true;
11676
11677 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11678 break;
11679 case DRM_PLANE_TYPE_CURSOR:
11680 break;
11681 case DRM_PLANE_TYPE_OVERLAY:
11682 if (turn_off && !mode_changed) {
11683 intel_crtc->atomic.wait_vblank = true;
11684 intel_crtc->atomic.update_sprite_watermarks |=
11685 1 << i;
11686 }
11687 }
11688 return 0;
11689 }
11690
11691 static bool encoders_cloneable(const struct intel_encoder *a,
11692 const struct intel_encoder *b)
11693 {
11694 /* masks could be asymmetric, so check both ways */
11695 return a == b || (a->cloneable & (1 << b->type) &&
11696 b->cloneable & (1 << a->type));
11697 }
11698
11699 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11700 struct intel_crtc *crtc,
11701 struct intel_encoder *encoder)
11702 {
11703 struct intel_encoder *source_encoder;
11704 struct drm_connector *connector;
11705 struct drm_connector_state *connector_state;
11706 int i;
11707
11708 for_each_connector_in_state(state, connector, connector_state, i) {
11709 if (connector_state->crtc != &crtc->base)
11710 continue;
11711
11712 source_encoder =
11713 to_intel_encoder(connector_state->best_encoder);
11714 if (!encoders_cloneable(encoder, source_encoder))
11715 return false;
11716 }
11717
11718 return true;
11719 }
11720
11721 static bool check_encoder_cloning(struct drm_atomic_state *state,
11722 struct intel_crtc *crtc)
11723 {
11724 struct intel_encoder *encoder;
11725 struct drm_connector *connector;
11726 struct drm_connector_state *connector_state;
11727 int i;
11728
11729 for_each_connector_in_state(state, connector, connector_state, i) {
11730 if (connector_state->crtc != &crtc->base)
11731 continue;
11732
11733 encoder = to_intel_encoder(connector_state->best_encoder);
11734 if (!check_single_encoder_cloning(state, crtc, encoder))
11735 return false;
11736 }
11737
11738 return true;
11739 }
11740
11741 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11742 struct drm_crtc_state *crtc_state)
11743 {
11744 struct drm_device *dev = crtc->dev;
11745 struct drm_i915_private *dev_priv = dev->dev_private;
11746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11747 struct intel_crtc_state *pipe_config =
11748 to_intel_crtc_state(crtc_state);
11749 struct drm_atomic_state *state = crtc_state->state;
11750 int ret;
11751 bool mode_changed = needs_modeset(crtc_state);
11752
11753 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11754 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11755 return -EINVAL;
11756 }
11757
11758 if (mode_changed && !crtc_state->active)
11759 intel_crtc->atomic.update_wm_post = true;
11760
11761 if (mode_changed && crtc_state->enable &&
11762 dev_priv->display.crtc_compute_clock &&
11763 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11764 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11765 pipe_config);
11766 if (ret)
11767 return ret;
11768 }
11769
11770 ret = 0;
11771 if (INTEL_INFO(dev)->gen >= 9) {
11772 if (mode_changed)
11773 ret = skl_update_scaler_crtc(pipe_config);
11774
11775 if (!ret)
11776 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11777 pipe_config);
11778 }
11779
11780 return ret;
11781 }
11782
11783 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11784 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11785 .load_lut = intel_crtc_load_lut,
11786 .atomic_begin = intel_begin_crtc_commit,
11787 .atomic_flush = intel_finish_crtc_commit,
11788 .atomic_check = intel_crtc_atomic_check,
11789 };
11790
11791 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11792 {
11793 struct intel_connector *connector;
11794
11795 for_each_intel_connector(dev, connector) {
11796 if (connector->base.encoder) {
11797 connector->base.state->best_encoder =
11798 connector->base.encoder;
11799 connector->base.state->crtc =
11800 connector->base.encoder->crtc;
11801 } else {
11802 connector->base.state->best_encoder = NULL;
11803 connector->base.state->crtc = NULL;
11804 }
11805 }
11806 }
11807
11808 static void
11809 connected_sink_compute_bpp(struct intel_connector *connector,
11810 struct intel_crtc_state *pipe_config)
11811 {
11812 int bpp = pipe_config->pipe_bpp;
11813
11814 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11815 connector->base.base.id,
11816 connector->base.name);
11817
11818 /* Don't use an invalid EDID bpc value */
11819 if (connector->base.display_info.bpc &&
11820 connector->base.display_info.bpc * 3 < bpp) {
11821 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11822 bpp, connector->base.display_info.bpc*3);
11823 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11824 }
11825
11826 /* Clamp bpp to 8 on screens without EDID 1.4 */
11827 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11828 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11829 bpp);
11830 pipe_config->pipe_bpp = 24;
11831 }
11832 }
11833
11834 static int
11835 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11836 struct intel_crtc_state *pipe_config)
11837 {
11838 struct drm_device *dev = crtc->base.dev;
11839 struct drm_atomic_state *state;
11840 struct drm_connector *connector;
11841 struct drm_connector_state *connector_state;
11842 int bpp, i;
11843
11844 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11845 bpp = 10*3;
11846 else if (INTEL_INFO(dev)->gen >= 5)
11847 bpp = 12*3;
11848 else
11849 bpp = 8*3;
11850
11851
11852 pipe_config->pipe_bpp = bpp;
11853
11854 state = pipe_config->base.state;
11855
11856 /* Clamp display bpp to EDID value */
11857 for_each_connector_in_state(state, connector, connector_state, i) {
11858 if (connector_state->crtc != &crtc->base)
11859 continue;
11860
11861 connected_sink_compute_bpp(to_intel_connector(connector),
11862 pipe_config);
11863 }
11864
11865 return bpp;
11866 }
11867
11868 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11869 {
11870 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11871 "type: 0x%x flags: 0x%x\n",
11872 mode->crtc_clock,
11873 mode->crtc_hdisplay, mode->crtc_hsync_start,
11874 mode->crtc_hsync_end, mode->crtc_htotal,
11875 mode->crtc_vdisplay, mode->crtc_vsync_start,
11876 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11877 }
11878
11879 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11880 struct intel_crtc_state *pipe_config,
11881 const char *context)
11882 {
11883 struct drm_device *dev = crtc->base.dev;
11884 struct drm_plane *plane;
11885 struct intel_plane *intel_plane;
11886 struct intel_plane_state *state;
11887 struct drm_framebuffer *fb;
11888
11889 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11890 context, pipe_config, pipe_name(crtc->pipe));
11891
11892 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11893 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11894 pipe_config->pipe_bpp, pipe_config->dither);
11895 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11896 pipe_config->has_pch_encoder,
11897 pipe_config->fdi_lanes,
11898 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11899 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11900 pipe_config->fdi_m_n.tu);
11901 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11902 pipe_config->has_dp_encoder,
11903 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11904 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11905 pipe_config->dp_m_n.tu);
11906
11907 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11908 pipe_config->has_dp_encoder,
11909 pipe_config->dp_m2_n2.gmch_m,
11910 pipe_config->dp_m2_n2.gmch_n,
11911 pipe_config->dp_m2_n2.link_m,
11912 pipe_config->dp_m2_n2.link_n,
11913 pipe_config->dp_m2_n2.tu);
11914
11915 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11916 pipe_config->has_audio,
11917 pipe_config->has_infoframe);
11918
11919 DRM_DEBUG_KMS("requested mode:\n");
11920 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11921 DRM_DEBUG_KMS("adjusted mode:\n");
11922 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11923 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11924 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11925 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11926 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11927 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11928 crtc->num_scalers,
11929 pipe_config->scaler_state.scaler_users,
11930 pipe_config->scaler_state.scaler_id);
11931 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11932 pipe_config->gmch_pfit.control,
11933 pipe_config->gmch_pfit.pgm_ratios,
11934 pipe_config->gmch_pfit.lvds_border_bits);
11935 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11936 pipe_config->pch_pfit.pos,
11937 pipe_config->pch_pfit.size,
11938 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11939 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11940 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11941
11942 if (IS_BROXTON(dev)) {
11943 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11944 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11945 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11946 pipe_config->ddi_pll_sel,
11947 pipe_config->dpll_hw_state.ebb0,
11948 pipe_config->dpll_hw_state.ebb4,
11949 pipe_config->dpll_hw_state.pll0,
11950 pipe_config->dpll_hw_state.pll1,
11951 pipe_config->dpll_hw_state.pll2,
11952 pipe_config->dpll_hw_state.pll3,
11953 pipe_config->dpll_hw_state.pll6,
11954 pipe_config->dpll_hw_state.pll8,
11955 pipe_config->dpll_hw_state.pll9,
11956 pipe_config->dpll_hw_state.pll10,
11957 pipe_config->dpll_hw_state.pcsdw12);
11958 } else if (IS_SKYLAKE(dev)) {
11959 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11960 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11961 pipe_config->ddi_pll_sel,
11962 pipe_config->dpll_hw_state.ctrl1,
11963 pipe_config->dpll_hw_state.cfgcr1,
11964 pipe_config->dpll_hw_state.cfgcr2);
11965 } else if (HAS_DDI(dev)) {
11966 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11967 pipe_config->ddi_pll_sel,
11968 pipe_config->dpll_hw_state.wrpll);
11969 } else {
11970 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11971 "fp0: 0x%x, fp1: 0x%x\n",
11972 pipe_config->dpll_hw_state.dpll,
11973 pipe_config->dpll_hw_state.dpll_md,
11974 pipe_config->dpll_hw_state.fp0,
11975 pipe_config->dpll_hw_state.fp1);
11976 }
11977
11978 DRM_DEBUG_KMS("planes on this crtc\n");
11979 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11980 intel_plane = to_intel_plane(plane);
11981 if (intel_plane->pipe != crtc->pipe)
11982 continue;
11983
11984 state = to_intel_plane_state(plane->state);
11985 fb = state->base.fb;
11986 if (!fb) {
11987 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11988 "disabled, scaler_id = %d\n",
11989 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11990 plane->base.id, intel_plane->pipe,
11991 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11992 drm_plane_index(plane), state->scaler_id);
11993 continue;
11994 }
11995
11996 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11997 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11998 plane->base.id, intel_plane->pipe,
11999 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12000 drm_plane_index(plane));
12001 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12002 fb->base.id, fb->width, fb->height, fb->pixel_format);
12003 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12004 state->scaler_id,
12005 state->src.x1 >> 16, state->src.y1 >> 16,
12006 drm_rect_width(&state->src) >> 16,
12007 drm_rect_height(&state->src) >> 16,
12008 state->dst.x1, state->dst.y1,
12009 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12010 }
12011 }
12012
12013 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12014 {
12015 struct drm_device *dev = state->dev;
12016 struct intel_encoder *encoder;
12017 struct drm_connector *connector;
12018 struct drm_connector_state *connector_state;
12019 unsigned int used_ports = 0;
12020 int i;
12021
12022 /*
12023 * Walk the connector list instead of the encoder
12024 * list to detect the problem on ddi platforms
12025 * where there's just one encoder per digital port.
12026 */
12027 for_each_connector_in_state(state, connector, connector_state, i) {
12028 if (!connector_state->best_encoder)
12029 continue;
12030
12031 encoder = to_intel_encoder(connector_state->best_encoder);
12032
12033 WARN_ON(!connector_state->crtc);
12034
12035 switch (encoder->type) {
12036 unsigned int port_mask;
12037 case INTEL_OUTPUT_UNKNOWN:
12038 if (WARN_ON(!HAS_DDI(dev)))
12039 break;
12040 case INTEL_OUTPUT_DISPLAYPORT:
12041 case INTEL_OUTPUT_HDMI:
12042 case INTEL_OUTPUT_EDP:
12043 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12044
12045 /* the same port mustn't appear more than once */
12046 if (used_ports & port_mask)
12047 return false;
12048
12049 used_ports |= port_mask;
12050 default:
12051 break;
12052 }
12053 }
12054
12055 return true;
12056 }
12057
12058 static void
12059 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12060 {
12061 struct drm_crtc_state tmp_state;
12062 struct intel_crtc_scaler_state scaler_state;
12063 struct intel_dpll_hw_state dpll_hw_state;
12064 enum intel_dpll_id shared_dpll;
12065 uint32_t ddi_pll_sel;
12066 bool force_thru;
12067
12068 /* FIXME: before the switch to atomic started, a new pipe_config was
12069 * kzalloc'd. Code that depends on any field being zero should be
12070 * fixed, so that the crtc_state can be safely duplicated. For now,
12071 * only fields that are know to not cause problems are preserved. */
12072
12073 tmp_state = crtc_state->base;
12074 scaler_state = crtc_state->scaler_state;
12075 shared_dpll = crtc_state->shared_dpll;
12076 dpll_hw_state = crtc_state->dpll_hw_state;
12077 ddi_pll_sel = crtc_state->ddi_pll_sel;
12078 force_thru = crtc_state->pch_pfit.force_thru;
12079
12080 memset(crtc_state, 0, sizeof *crtc_state);
12081
12082 crtc_state->base = tmp_state;
12083 crtc_state->scaler_state = scaler_state;
12084 crtc_state->shared_dpll = shared_dpll;
12085 crtc_state->dpll_hw_state = dpll_hw_state;
12086 crtc_state->ddi_pll_sel = ddi_pll_sel;
12087 crtc_state->pch_pfit.force_thru = force_thru;
12088 }
12089
12090 static int
12091 intel_modeset_pipe_config(struct drm_crtc *crtc,
12092 struct intel_crtc_state *pipe_config)
12093 {
12094 struct drm_atomic_state *state = pipe_config->base.state;
12095 struct intel_encoder *encoder;
12096 struct drm_connector *connector;
12097 struct drm_connector_state *connector_state;
12098 int base_bpp, ret = -EINVAL;
12099 int i;
12100 bool retry = true;
12101
12102 clear_intel_crtc_state(pipe_config);
12103
12104 pipe_config->cpu_transcoder =
12105 (enum transcoder) to_intel_crtc(crtc)->pipe;
12106
12107 /*
12108 * Sanitize sync polarity flags based on requested ones. If neither
12109 * positive or negative polarity is requested, treat this as meaning
12110 * negative polarity.
12111 */
12112 if (!(pipe_config->base.adjusted_mode.flags &
12113 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12114 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12115
12116 if (!(pipe_config->base.adjusted_mode.flags &
12117 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12118 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12119
12120 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12121 * plane pixel format and any sink constraints into account. Returns the
12122 * source plane bpp so that dithering can be selected on mismatches
12123 * after encoders and crtc also have had their say. */
12124 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12125 pipe_config);
12126 if (base_bpp < 0)
12127 goto fail;
12128
12129 /*
12130 * Determine the real pipe dimensions. Note that stereo modes can
12131 * increase the actual pipe size due to the frame doubling and
12132 * insertion of additional space for blanks between the frame. This
12133 * is stored in the crtc timings. We use the requested mode to do this
12134 * computation to clearly distinguish it from the adjusted mode, which
12135 * can be changed by the connectors in the below retry loop.
12136 */
12137 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12138 &pipe_config->pipe_src_w,
12139 &pipe_config->pipe_src_h);
12140
12141 encoder_retry:
12142 /* Ensure the port clock defaults are reset when retrying. */
12143 pipe_config->port_clock = 0;
12144 pipe_config->pixel_multiplier = 1;
12145
12146 /* Fill in default crtc timings, allow encoders to overwrite them. */
12147 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12148 CRTC_STEREO_DOUBLE);
12149
12150 /* Pass our mode to the connectors and the CRTC to give them a chance to
12151 * adjust it according to limitations or connector properties, and also
12152 * a chance to reject the mode entirely.
12153 */
12154 for_each_connector_in_state(state, connector, connector_state, i) {
12155 if (connector_state->crtc != crtc)
12156 continue;
12157
12158 encoder = to_intel_encoder(connector_state->best_encoder);
12159
12160 if (!(encoder->compute_config(encoder, pipe_config))) {
12161 DRM_DEBUG_KMS("Encoder config failure\n");
12162 goto fail;
12163 }
12164 }
12165
12166 /* Set default port clock if not overwritten by the encoder. Needs to be
12167 * done afterwards in case the encoder adjusts the mode. */
12168 if (!pipe_config->port_clock)
12169 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12170 * pipe_config->pixel_multiplier;
12171
12172 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12173 if (ret < 0) {
12174 DRM_DEBUG_KMS("CRTC fixup failed\n");
12175 goto fail;
12176 }
12177
12178 if (ret == RETRY) {
12179 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12180 ret = -EINVAL;
12181 goto fail;
12182 }
12183
12184 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12185 retry = false;
12186 goto encoder_retry;
12187 }
12188
12189 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
12190 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12191 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12192
12193 fail:
12194 return ret;
12195 }
12196
12197 static void
12198 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12199 {
12200 struct drm_crtc *crtc;
12201 struct drm_crtc_state *crtc_state;
12202 int i;
12203
12204 /* Double check state. */
12205 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12206 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12207
12208 /* Update hwmode for vblank functions */
12209 if (crtc->state->active)
12210 crtc->hwmode = crtc->state->adjusted_mode;
12211 else
12212 crtc->hwmode.crtc_clock = 0;
12213 }
12214 }
12215
12216 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12217 {
12218 int diff;
12219
12220 if (clock1 == clock2)
12221 return true;
12222
12223 if (!clock1 || !clock2)
12224 return false;
12225
12226 diff = abs(clock1 - clock2);
12227
12228 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12229 return true;
12230
12231 return false;
12232 }
12233
12234 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12235 list_for_each_entry((intel_crtc), \
12236 &(dev)->mode_config.crtc_list, \
12237 base.head) \
12238 if (mask & (1 <<(intel_crtc)->pipe))
12239
12240
12241 static bool
12242 intel_compare_m_n(unsigned int m, unsigned int n,
12243 unsigned int m2, unsigned int n2,
12244 bool exact)
12245 {
12246 if (m == m2 && n == n2)
12247 return true;
12248
12249 if (exact || !m || !n || !m2 || !n2)
12250 return false;
12251
12252 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12253
12254 if (m > m2) {
12255 while (m > m2) {
12256 m2 <<= 1;
12257 n2 <<= 1;
12258 }
12259 } else if (m < m2) {
12260 while (m < m2) {
12261 m <<= 1;
12262 n <<= 1;
12263 }
12264 }
12265
12266 return m == m2 && n == n2;
12267 }
12268
12269 static bool
12270 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12271 struct intel_link_m_n *m2_n2,
12272 bool adjust)
12273 {
12274 if (m_n->tu == m2_n2->tu &&
12275 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12276 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12277 intel_compare_m_n(m_n->link_m, m_n->link_n,
12278 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12279 if (adjust)
12280 *m2_n2 = *m_n;
12281
12282 return true;
12283 }
12284
12285 return false;
12286 }
12287
12288 static bool
12289 intel_pipe_config_compare(struct drm_device *dev,
12290 struct intel_crtc_state *current_config,
12291 struct intel_crtc_state *pipe_config,
12292 bool adjust)
12293 {
12294 bool ret = true;
12295
12296 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12297 do { \
12298 if (!adjust) \
12299 DRM_ERROR(fmt, ##__VA_ARGS__); \
12300 else \
12301 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12302 } while (0)
12303
12304 #define PIPE_CONF_CHECK_X(name) \
12305 if (current_config->name != pipe_config->name) { \
12306 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12307 "(expected 0x%08x, found 0x%08x)\n", \
12308 current_config->name, \
12309 pipe_config->name); \
12310 ret = false; \
12311 }
12312
12313 #define PIPE_CONF_CHECK_I(name) \
12314 if (current_config->name != pipe_config->name) { \
12315 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12316 "(expected %i, found %i)\n", \
12317 current_config->name, \
12318 pipe_config->name); \
12319 ret = false; \
12320 }
12321
12322 #define PIPE_CONF_CHECK_M_N(name) \
12323 if (!intel_compare_link_m_n(&current_config->name, \
12324 &pipe_config->name,\
12325 adjust)) { \
12326 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12327 "(expected tu %i gmch %i/%i link %i/%i, " \
12328 "found tu %i, gmch %i/%i link %i/%i)\n", \
12329 current_config->name.tu, \
12330 current_config->name.gmch_m, \
12331 current_config->name.gmch_n, \
12332 current_config->name.link_m, \
12333 current_config->name.link_n, \
12334 pipe_config->name.tu, \
12335 pipe_config->name.gmch_m, \
12336 pipe_config->name.gmch_n, \
12337 pipe_config->name.link_m, \
12338 pipe_config->name.link_n); \
12339 ret = false; \
12340 }
12341
12342 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12343 if (!intel_compare_link_m_n(&current_config->name, \
12344 &pipe_config->name, adjust) && \
12345 !intel_compare_link_m_n(&current_config->alt_name, \
12346 &pipe_config->name, adjust)) { \
12347 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12348 "(expected tu %i gmch %i/%i link %i/%i, " \
12349 "or tu %i gmch %i/%i link %i/%i, " \
12350 "found tu %i, gmch %i/%i link %i/%i)\n", \
12351 current_config->name.tu, \
12352 current_config->name.gmch_m, \
12353 current_config->name.gmch_n, \
12354 current_config->name.link_m, \
12355 current_config->name.link_n, \
12356 current_config->alt_name.tu, \
12357 current_config->alt_name.gmch_m, \
12358 current_config->alt_name.gmch_n, \
12359 current_config->alt_name.link_m, \
12360 current_config->alt_name.link_n, \
12361 pipe_config->name.tu, \
12362 pipe_config->name.gmch_m, \
12363 pipe_config->name.gmch_n, \
12364 pipe_config->name.link_m, \
12365 pipe_config->name.link_n); \
12366 ret = false; \
12367 }
12368
12369 /* This is required for BDW+ where there is only one set of registers for
12370 * switching between high and low RR.
12371 * This macro can be used whenever a comparison has to be made between one
12372 * hw state and multiple sw state variables.
12373 */
12374 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12375 if ((current_config->name != pipe_config->name) && \
12376 (current_config->alt_name != pipe_config->name)) { \
12377 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12378 "(expected %i or %i, found %i)\n", \
12379 current_config->name, \
12380 current_config->alt_name, \
12381 pipe_config->name); \
12382 ret = false; \
12383 }
12384
12385 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12386 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12387 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12388 "(expected %i, found %i)\n", \
12389 current_config->name & (mask), \
12390 pipe_config->name & (mask)); \
12391 ret = false; \
12392 }
12393
12394 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12395 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12396 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12397 "(expected %i, found %i)\n", \
12398 current_config->name, \
12399 pipe_config->name); \
12400 ret = false; \
12401 }
12402
12403 #define PIPE_CONF_QUIRK(quirk) \
12404 ((current_config->quirks | pipe_config->quirks) & (quirk))
12405
12406 PIPE_CONF_CHECK_I(cpu_transcoder);
12407
12408 PIPE_CONF_CHECK_I(has_pch_encoder);
12409 PIPE_CONF_CHECK_I(fdi_lanes);
12410 PIPE_CONF_CHECK_M_N(fdi_m_n);
12411
12412 PIPE_CONF_CHECK_I(has_dp_encoder);
12413
12414 if (INTEL_INFO(dev)->gen < 8) {
12415 PIPE_CONF_CHECK_M_N(dp_m_n);
12416
12417 PIPE_CONF_CHECK_I(has_drrs);
12418 if (current_config->has_drrs)
12419 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12420 } else
12421 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12422
12423 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12424 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12425 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12426 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12427 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12428 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12429
12430 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12431 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12432 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12433 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12434 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12435 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12436
12437 PIPE_CONF_CHECK_I(pixel_multiplier);
12438 PIPE_CONF_CHECK_I(has_hdmi_sink);
12439 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12440 IS_VALLEYVIEW(dev))
12441 PIPE_CONF_CHECK_I(limited_color_range);
12442 PIPE_CONF_CHECK_I(has_infoframe);
12443
12444 PIPE_CONF_CHECK_I(has_audio);
12445
12446 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12447 DRM_MODE_FLAG_INTERLACE);
12448
12449 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12450 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12451 DRM_MODE_FLAG_PHSYNC);
12452 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12453 DRM_MODE_FLAG_NHSYNC);
12454 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12455 DRM_MODE_FLAG_PVSYNC);
12456 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12457 DRM_MODE_FLAG_NVSYNC);
12458 }
12459
12460 PIPE_CONF_CHECK_I(pipe_src_w);
12461 PIPE_CONF_CHECK_I(pipe_src_h);
12462
12463 PIPE_CONF_CHECK_I(gmch_pfit.control);
12464 /* pfit ratios are autocomputed by the hw on gen4+ */
12465 if (INTEL_INFO(dev)->gen < 4)
12466 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12467 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12468
12469 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12470 if (current_config->pch_pfit.enabled) {
12471 PIPE_CONF_CHECK_I(pch_pfit.pos);
12472 PIPE_CONF_CHECK_I(pch_pfit.size);
12473 }
12474
12475 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12476
12477 /* BDW+ don't expose a synchronous way to read the state */
12478 if (IS_HASWELL(dev))
12479 PIPE_CONF_CHECK_I(ips_enabled);
12480
12481 PIPE_CONF_CHECK_I(double_wide);
12482
12483 PIPE_CONF_CHECK_X(ddi_pll_sel);
12484
12485 PIPE_CONF_CHECK_I(shared_dpll);
12486 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12487 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12488 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12489 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12490 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12491 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12492 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12493 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12494
12495 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12496 PIPE_CONF_CHECK_I(pipe_bpp);
12497
12498 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12499 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12500
12501 #undef PIPE_CONF_CHECK_X
12502 #undef PIPE_CONF_CHECK_I
12503 #undef PIPE_CONF_CHECK_I_ALT
12504 #undef PIPE_CONF_CHECK_FLAGS
12505 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12506 #undef PIPE_CONF_QUIRK
12507 #undef INTEL_ERR_OR_DBG_KMS
12508
12509 return ret;
12510 }
12511
12512 static void check_wm_state(struct drm_device *dev)
12513 {
12514 struct drm_i915_private *dev_priv = dev->dev_private;
12515 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12516 struct intel_crtc *intel_crtc;
12517 int plane;
12518
12519 if (INTEL_INFO(dev)->gen < 9)
12520 return;
12521
12522 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12523 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12524
12525 for_each_intel_crtc(dev, intel_crtc) {
12526 struct skl_ddb_entry *hw_entry, *sw_entry;
12527 const enum pipe pipe = intel_crtc->pipe;
12528
12529 if (!intel_crtc->active)
12530 continue;
12531
12532 /* planes */
12533 for_each_plane(dev_priv, pipe, plane) {
12534 hw_entry = &hw_ddb.plane[pipe][plane];
12535 sw_entry = &sw_ddb->plane[pipe][plane];
12536
12537 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12538 continue;
12539
12540 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12541 "(expected (%u,%u), found (%u,%u))\n",
12542 pipe_name(pipe), plane + 1,
12543 sw_entry->start, sw_entry->end,
12544 hw_entry->start, hw_entry->end);
12545 }
12546
12547 /* cursor */
12548 hw_entry = &hw_ddb.cursor[pipe];
12549 sw_entry = &sw_ddb->cursor[pipe];
12550
12551 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12552 continue;
12553
12554 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12555 "(expected (%u,%u), found (%u,%u))\n",
12556 pipe_name(pipe),
12557 sw_entry->start, sw_entry->end,
12558 hw_entry->start, hw_entry->end);
12559 }
12560 }
12561
12562 static void
12563 check_connector_state(struct drm_device *dev,
12564 struct drm_atomic_state *old_state)
12565 {
12566 struct drm_connector_state *old_conn_state;
12567 struct drm_connector *connector;
12568 int i;
12569
12570 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12571 struct drm_encoder *encoder = connector->encoder;
12572 struct drm_connector_state *state = connector->state;
12573
12574 /* This also checks the encoder/connector hw state with the
12575 * ->get_hw_state callbacks. */
12576 intel_connector_check_state(to_intel_connector(connector));
12577
12578 I915_STATE_WARN(state->best_encoder != encoder,
12579 "connector's atomic encoder doesn't match legacy encoder\n");
12580 }
12581 }
12582
12583 static void
12584 check_encoder_state(struct drm_device *dev)
12585 {
12586 struct intel_encoder *encoder;
12587 struct intel_connector *connector;
12588
12589 for_each_intel_encoder(dev, encoder) {
12590 bool enabled = false;
12591 enum pipe pipe;
12592
12593 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12594 encoder->base.base.id,
12595 encoder->base.name);
12596
12597 for_each_intel_connector(dev, connector) {
12598 if (connector->base.state->best_encoder != &encoder->base)
12599 continue;
12600 enabled = true;
12601
12602 I915_STATE_WARN(connector->base.state->crtc !=
12603 encoder->base.crtc,
12604 "connector's crtc doesn't match encoder crtc\n");
12605 }
12606
12607 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12608 "encoder's enabled state mismatch "
12609 "(expected %i, found %i)\n",
12610 !!encoder->base.crtc, enabled);
12611
12612 if (!encoder->base.crtc) {
12613 bool active;
12614
12615 active = encoder->get_hw_state(encoder, &pipe);
12616 I915_STATE_WARN(active,
12617 "encoder detached but still enabled on pipe %c.\n",
12618 pipe_name(pipe));
12619 }
12620 }
12621 }
12622
12623 static void
12624 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12625 {
12626 struct drm_i915_private *dev_priv = dev->dev_private;
12627 struct intel_encoder *encoder;
12628 struct drm_crtc_state *old_crtc_state;
12629 struct drm_crtc *crtc;
12630 int i;
12631
12632 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12634 struct intel_crtc_state *pipe_config, *sw_config;
12635 bool active;
12636
12637 if (!needs_modeset(crtc->state))
12638 continue;
12639
12640 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12641 pipe_config = to_intel_crtc_state(old_crtc_state);
12642 memset(pipe_config, 0, sizeof(*pipe_config));
12643 pipe_config->base.crtc = crtc;
12644 pipe_config->base.state = old_state;
12645
12646 DRM_DEBUG_KMS("[CRTC:%d]\n",
12647 crtc->base.id);
12648
12649 active = dev_priv->display.get_pipe_config(intel_crtc,
12650 pipe_config);
12651
12652 /* hw state is inconsistent with the pipe quirk */
12653 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12654 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12655 active = crtc->state->active;
12656
12657 I915_STATE_WARN(crtc->state->active != active,
12658 "crtc active state doesn't match with hw state "
12659 "(expected %i, found %i)\n", crtc->state->active, active);
12660
12661 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12662 "transitional active state does not match atomic hw state "
12663 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12664
12665 for_each_encoder_on_crtc(dev, crtc, encoder) {
12666 enum pipe pipe;
12667
12668 active = encoder->get_hw_state(encoder, &pipe);
12669 I915_STATE_WARN(active != crtc->state->active,
12670 "[ENCODER:%i] active %i with crtc active %i\n",
12671 encoder->base.base.id, active, crtc->state->active);
12672
12673 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12674 "Encoder connected to wrong pipe %c\n",
12675 pipe_name(pipe));
12676
12677 if (active)
12678 encoder->get_config(encoder, pipe_config);
12679 }
12680
12681 if (!crtc->state->active)
12682 continue;
12683
12684 sw_config = to_intel_crtc_state(crtc->state);
12685 if (!intel_pipe_config_compare(dev, sw_config,
12686 pipe_config, false)) {
12687 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12688 intel_dump_pipe_config(intel_crtc, pipe_config,
12689 "[hw state]");
12690 intel_dump_pipe_config(intel_crtc, sw_config,
12691 "[sw state]");
12692 }
12693 }
12694 }
12695
12696 static void
12697 check_shared_dpll_state(struct drm_device *dev)
12698 {
12699 struct drm_i915_private *dev_priv = dev->dev_private;
12700 struct intel_crtc *crtc;
12701 struct intel_dpll_hw_state dpll_hw_state;
12702 int i;
12703
12704 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12705 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12706 int enabled_crtcs = 0, active_crtcs = 0;
12707 bool active;
12708
12709 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12710
12711 DRM_DEBUG_KMS("%s\n", pll->name);
12712
12713 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12714
12715 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12716 "more active pll users than references: %i vs %i\n",
12717 pll->active, hweight32(pll->config.crtc_mask));
12718 I915_STATE_WARN(pll->active && !pll->on,
12719 "pll in active use but not on in sw tracking\n");
12720 I915_STATE_WARN(pll->on && !pll->active,
12721 "pll in on but not on in use in sw tracking\n");
12722 I915_STATE_WARN(pll->on != active,
12723 "pll on state mismatch (expected %i, found %i)\n",
12724 pll->on, active);
12725
12726 for_each_intel_crtc(dev, crtc) {
12727 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12728 enabled_crtcs++;
12729 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12730 active_crtcs++;
12731 }
12732 I915_STATE_WARN(pll->active != active_crtcs,
12733 "pll active crtcs mismatch (expected %i, found %i)\n",
12734 pll->active, active_crtcs);
12735 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12736 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12737 hweight32(pll->config.crtc_mask), enabled_crtcs);
12738
12739 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12740 sizeof(dpll_hw_state)),
12741 "pll hw state mismatch\n");
12742 }
12743 }
12744
12745 static void
12746 intel_modeset_check_state(struct drm_device *dev,
12747 struct drm_atomic_state *old_state)
12748 {
12749 check_wm_state(dev);
12750 check_connector_state(dev, old_state);
12751 check_encoder_state(dev);
12752 check_crtc_state(dev, old_state);
12753 check_shared_dpll_state(dev);
12754 }
12755
12756 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12757 int dotclock)
12758 {
12759 /*
12760 * FDI already provided one idea for the dotclock.
12761 * Yell if the encoder disagrees.
12762 */
12763 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12764 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12765 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12766 }
12767
12768 static void update_scanline_offset(struct intel_crtc *crtc)
12769 {
12770 struct drm_device *dev = crtc->base.dev;
12771
12772 /*
12773 * The scanline counter increments at the leading edge of hsync.
12774 *
12775 * On most platforms it starts counting from vtotal-1 on the
12776 * first active line. That means the scanline counter value is
12777 * always one less than what we would expect. Ie. just after
12778 * start of vblank, which also occurs at start of hsync (on the
12779 * last active line), the scanline counter will read vblank_start-1.
12780 *
12781 * On gen2 the scanline counter starts counting from 1 instead
12782 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12783 * to keep the value positive), instead of adding one.
12784 *
12785 * On HSW+ the behaviour of the scanline counter depends on the output
12786 * type. For DP ports it behaves like most other platforms, but on HDMI
12787 * there's an extra 1 line difference. So we need to add two instead of
12788 * one to the value.
12789 */
12790 if (IS_GEN2(dev)) {
12791 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12792 int vtotal;
12793
12794 vtotal = mode->crtc_vtotal;
12795 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12796 vtotal /= 2;
12797
12798 crtc->scanline_offset = vtotal - 1;
12799 } else if (HAS_DDI(dev) &&
12800 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12801 crtc->scanline_offset = 2;
12802 } else
12803 crtc->scanline_offset = 1;
12804 }
12805
12806 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12807 {
12808 struct drm_device *dev = state->dev;
12809 struct drm_i915_private *dev_priv = to_i915(dev);
12810 struct intel_shared_dpll_config *shared_dpll = NULL;
12811 struct intel_crtc *intel_crtc;
12812 struct intel_crtc_state *intel_crtc_state;
12813 struct drm_crtc *crtc;
12814 struct drm_crtc_state *crtc_state;
12815 int i;
12816
12817 if (!dev_priv->display.crtc_compute_clock)
12818 return;
12819
12820 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12821 int dpll;
12822
12823 intel_crtc = to_intel_crtc(crtc);
12824 intel_crtc_state = to_intel_crtc_state(crtc_state);
12825 dpll = intel_crtc_state->shared_dpll;
12826
12827 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12828 continue;
12829
12830 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12831
12832 if (!shared_dpll)
12833 shared_dpll = intel_atomic_get_shared_dpll_state(state);
12834
12835 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12836 }
12837 }
12838
12839 /*
12840 * This implements the workaround described in the "notes" section of the mode
12841 * set sequence documentation. When going from no pipes or single pipe to
12842 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12843 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12844 */
12845 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12846 {
12847 struct drm_crtc_state *crtc_state;
12848 struct intel_crtc *intel_crtc;
12849 struct drm_crtc *crtc;
12850 struct intel_crtc_state *first_crtc_state = NULL;
12851 struct intel_crtc_state *other_crtc_state = NULL;
12852 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12853 int i;
12854
12855 /* look at all crtc's that are going to be enabled in during modeset */
12856 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12857 intel_crtc = to_intel_crtc(crtc);
12858
12859 if (!crtc_state->active || !needs_modeset(crtc_state))
12860 continue;
12861
12862 if (first_crtc_state) {
12863 other_crtc_state = to_intel_crtc_state(crtc_state);
12864 break;
12865 } else {
12866 first_crtc_state = to_intel_crtc_state(crtc_state);
12867 first_pipe = intel_crtc->pipe;
12868 }
12869 }
12870
12871 /* No workaround needed? */
12872 if (!first_crtc_state)
12873 return 0;
12874
12875 /* w/a possibly needed, check how many crtc's are already enabled. */
12876 for_each_intel_crtc(state->dev, intel_crtc) {
12877 struct intel_crtc_state *pipe_config;
12878
12879 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12880 if (IS_ERR(pipe_config))
12881 return PTR_ERR(pipe_config);
12882
12883 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12884
12885 if (!pipe_config->base.active ||
12886 needs_modeset(&pipe_config->base))
12887 continue;
12888
12889 /* 2 or more enabled crtcs means no need for w/a */
12890 if (enabled_pipe != INVALID_PIPE)
12891 return 0;
12892
12893 enabled_pipe = intel_crtc->pipe;
12894 }
12895
12896 if (enabled_pipe != INVALID_PIPE)
12897 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12898 else if (other_crtc_state)
12899 other_crtc_state->hsw_workaround_pipe = first_pipe;
12900
12901 return 0;
12902 }
12903
12904 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12905 {
12906 struct drm_crtc *crtc;
12907 struct drm_crtc_state *crtc_state;
12908 int ret = 0;
12909
12910 /* add all active pipes to the state */
12911 for_each_crtc(state->dev, crtc) {
12912 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12913 if (IS_ERR(crtc_state))
12914 return PTR_ERR(crtc_state);
12915
12916 if (!crtc_state->active || needs_modeset(crtc_state))
12917 continue;
12918
12919 crtc_state->mode_changed = true;
12920
12921 ret = drm_atomic_add_affected_connectors(state, crtc);
12922 if (ret)
12923 break;
12924
12925 ret = drm_atomic_add_affected_planes(state, crtc);
12926 if (ret)
12927 break;
12928 }
12929
12930 return ret;
12931 }
12932
12933
12934 static int intel_modeset_checks(struct drm_atomic_state *state)
12935 {
12936 struct drm_device *dev = state->dev;
12937 struct drm_i915_private *dev_priv = dev->dev_private;
12938 int ret;
12939
12940 if (!check_digital_port_conflicts(state)) {
12941 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12942 return -EINVAL;
12943 }
12944
12945 /*
12946 * See if the config requires any additional preparation, e.g.
12947 * to adjust global state with pipes off. We need to do this
12948 * here so we can get the modeset_pipe updated config for the new
12949 * mode set on this crtc. For other crtcs we need to use the
12950 * adjusted_mode bits in the crtc directly.
12951 */
12952 if (dev_priv->display.modeset_calc_cdclk) {
12953 unsigned int cdclk;
12954
12955 ret = dev_priv->display.modeset_calc_cdclk(state);
12956
12957 cdclk = to_intel_atomic_state(state)->cdclk;
12958 if (!ret && cdclk != dev_priv->cdclk_freq)
12959 ret = intel_modeset_all_pipes(state);
12960
12961 if (ret < 0)
12962 return ret;
12963 } else
12964 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
12965
12966 intel_modeset_clear_plls(state);
12967
12968 if (IS_HASWELL(dev))
12969 return haswell_mode_set_planes_workaround(state);
12970
12971 return 0;
12972 }
12973
12974 /**
12975 * intel_atomic_check - validate state object
12976 * @dev: drm device
12977 * @state: state to validate
12978 */
12979 static int intel_atomic_check(struct drm_device *dev,
12980 struct drm_atomic_state *state)
12981 {
12982 struct drm_crtc *crtc;
12983 struct drm_crtc_state *crtc_state;
12984 int ret, i;
12985 bool any_ms = false;
12986
12987 ret = drm_atomic_helper_check_modeset(dev, state);
12988 if (ret)
12989 return ret;
12990
12991 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12992 struct intel_crtc_state *pipe_config =
12993 to_intel_crtc_state(crtc_state);
12994
12995 /* Catch I915_MODE_FLAG_INHERITED */
12996 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
12997 crtc_state->mode_changed = true;
12998
12999 if (!crtc_state->enable) {
13000 if (needs_modeset(crtc_state))
13001 any_ms = true;
13002 continue;
13003 }
13004
13005 if (!needs_modeset(crtc_state))
13006 continue;
13007
13008 /* FIXME: For only active_changed we shouldn't need to do any
13009 * state recomputation at all. */
13010
13011 ret = drm_atomic_add_affected_connectors(state, crtc);
13012 if (ret)
13013 return ret;
13014
13015 ret = intel_modeset_pipe_config(crtc, pipe_config);
13016 if (ret)
13017 return ret;
13018
13019 if (i915.fastboot &&
13020 intel_pipe_config_compare(state->dev,
13021 to_intel_crtc_state(crtc->state),
13022 pipe_config, true)) {
13023 crtc_state->mode_changed = false;
13024 }
13025
13026 if (needs_modeset(crtc_state)) {
13027 any_ms = true;
13028
13029 ret = drm_atomic_add_affected_planes(state, crtc);
13030 if (ret)
13031 return ret;
13032 }
13033
13034 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13035 needs_modeset(crtc_state) ?
13036 "[modeset]" : "[fastset]");
13037 }
13038
13039 if (any_ms) {
13040 ret = intel_modeset_checks(state);
13041
13042 if (ret)
13043 return ret;
13044 } else
13045 to_intel_atomic_state(state)->cdclk =
13046 to_i915(state->dev)->cdclk_freq;
13047
13048 return drm_atomic_helper_check_planes(state->dev, state);
13049 }
13050
13051 /**
13052 * intel_atomic_commit - commit validated state object
13053 * @dev: DRM device
13054 * @state: the top-level driver state object
13055 * @async: asynchronous commit
13056 *
13057 * This function commits a top-level state object that has been validated
13058 * with drm_atomic_helper_check().
13059 *
13060 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13061 * we can only handle plane-related operations and do not yet support
13062 * asynchronous commit.
13063 *
13064 * RETURNS
13065 * Zero for success or -errno.
13066 */
13067 static int intel_atomic_commit(struct drm_device *dev,
13068 struct drm_atomic_state *state,
13069 bool async)
13070 {
13071 struct drm_i915_private *dev_priv = dev->dev_private;
13072 struct drm_crtc *crtc;
13073 struct drm_crtc_state *crtc_state;
13074 int ret = 0;
13075 int i;
13076 bool any_ms = false;
13077
13078 if (async) {
13079 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13080 return -EINVAL;
13081 }
13082
13083 ret = drm_atomic_helper_prepare_planes(dev, state);
13084 if (ret)
13085 return ret;
13086
13087 drm_atomic_helper_swap_state(dev, state);
13088
13089 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13091
13092 if (!needs_modeset(crtc->state))
13093 continue;
13094
13095 any_ms = true;
13096 intel_pre_plane_update(intel_crtc);
13097
13098 if (crtc_state->active) {
13099 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13100 dev_priv->display.crtc_disable(crtc);
13101 intel_crtc->active = false;
13102 intel_disable_shared_dpll(intel_crtc);
13103 }
13104 }
13105
13106 /* Only after disabling all output pipelines that will be changed can we
13107 * update the the output configuration. */
13108 intel_modeset_update_crtc_state(state);
13109
13110 if (any_ms) {
13111 intel_shared_dpll_commit(state);
13112
13113 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13114 modeset_update_crtc_power_domains(state);
13115 }
13116
13117 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13118 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13120 bool modeset = needs_modeset(crtc->state);
13121
13122 if (modeset && crtc->state->active) {
13123 update_scanline_offset(to_intel_crtc(crtc));
13124 dev_priv->display.crtc_enable(crtc);
13125 }
13126
13127 if (!modeset)
13128 intel_pre_plane_update(intel_crtc);
13129
13130 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13131 intel_post_plane_update(intel_crtc);
13132 }
13133
13134 /* FIXME: add subpixel order */
13135
13136 drm_atomic_helper_wait_for_vblanks(dev, state);
13137 drm_atomic_helper_cleanup_planes(dev, state);
13138
13139 if (any_ms)
13140 intel_modeset_check_state(dev, state);
13141
13142 drm_atomic_state_free(state);
13143
13144 return 0;
13145 }
13146
13147 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13148 {
13149 struct drm_device *dev = crtc->dev;
13150 struct drm_atomic_state *state;
13151 struct drm_crtc_state *crtc_state;
13152 int ret;
13153
13154 state = drm_atomic_state_alloc(dev);
13155 if (!state) {
13156 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13157 crtc->base.id);
13158 return;
13159 }
13160
13161 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13162
13163 retry:
13164 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13165 ret = PTR_ERR_OR_ZERO(crtc_state);
13166 if (!ret) {
13167 if (!crtc_state->active)
13168 goto out;
13169
13170 crtc_state->mode_changed = true;
13171 ret = drm_atomic_commit(state);
13172 }
13173
13174 if (ret == -EDEADLK) {
13175 drm_atomic_state_clear(state);
13176 drm_modeset_backoff(state->acquire_ctx);
13177 goto retry;
13178 }
13179
13180 if (ret)
13181 out:
13182 drm_atomic_state_free(state);
13183 }
13184
13185 #undef for_each_intel_crtc_masked
13186
13187 static const struct drm_crtc_funcs intel_crtc_funcs = {
13188 .gamma_set = intel_crtc_gamma_set,
13189 .set_config = drm_atomic_helper_set_config,
13190 .destroy = intel_crtc_destroy,
13191 .page_flip = intel_crtc_page_flip,
13192 .atomic_duplicate_state = intel_crtc_duplicate_state,
13193 .atomic_destroy_state = intel_crtc_destroy_state,
13194 };
13195
13196 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13197 struct intel_shared_dpll *pll,
13198 struct intel_dpll_hw_state *hw_state)
13199 {
13200 uint32_t val;
13201
13202 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13203 return false;
13204
13205 val = I915_READ(PCH_DPLL(pll->id));
13206 hw_state->dpll = val;
13207 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13208 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13209
13210 return val & DPLL_VCO_ENABLE;
13211 }
13212
13213 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13214 struct intel_shared_dpll *pll)
13215 {
13216 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13217 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13218 }
13219
13220 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13221 struct intel_shared_dpll *pll)
13222 {
13223 /* PCH refclock must be enabled first */
13224 ibx_assert_pch_refclk_enabled(dev_priv);
13225
13226 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13227
13228 /* Wait for the clocks to stabilize. */
13229 POSTING_READ(PCH_DPLL(pll->id));
13230 udelay(150);
13231
13232 /* The pixel multiplier can only be updated once the
13233 * DPLL is enabled and the clocks are stable.
13234 *
13235 * So write it again.
13236 */
13237 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13238 POSTING_READ(PCH_DPLL(pll->id));
13239 udelay(200);
13240 }
13241
13242 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13243 struct intel_shared_dpll *pll)
13244 {
13245 struct drm_device *dev = dev_priv->dev;
13246 struct intel_crtc *crtc;
13247
13248 /* Make sure no transcoder isn't still depending on us. */
13249 for_each_intel_crtc(dev, crtc) {
13250 if (intel_crtc_to_shared_dpll(crtc) == pll)
13251 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13252 }
13253
13254 I915_WRITE(PCH_DPLL(pll->id), 0);
13255 POSTING_READ(PCH_DPLL(pll->id));
13256 udelay(200);
13257 }
13258
13259 static char *ibx_pch_dpll_names[] = {
13260 "PCH DPLL A",
13261 "PCH DPLL B",
13262 };
13263
13264 static void ibx_pch_dpll_init(struct drm_device *dev)
13265 {
13266 struct drm_i915_private *dev_priv = dev->dev_private;
13267 int i;
13268
13269 dev_priv->num_shared_dpll = 2;
13270
13271 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13272 dev_priv->shared_dplls[i].id = i;
13273 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13274 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13275 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13276 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13277 dev_priv->shared_dplls[i].get_hw_state =
13278 ibx_pch_dpll_get_hw_state;
13279 }
13280 }
13281
13282 static void intel_shared_dpll_init(struct drm_device *dev)
13283 {
13284 struct drm_i915_private *dev_priv = dev->dev_private;
13285
13286 intel_update_cdclk(dev);
13287
13288 if (HAS_DDI(dev))
13289 intel_ddi_pll_init(dev);
13290 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13291 ibx_pch_dpll_init(dev);
13292 else
13293 dev_priv->num_shared_dpll = 0;
13294
13295 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13296 }
13297
13298 /**
13299 * intel_prepare_plane_fb - Prepare fb for usage on plane
13300 * @plane: drm plane to prepare for
13301 * @fb: framebuffer to prepare for presentation
13302 *
13303 * Prepares a framebuffer for usage on a display plane. Generally this
13304 * involves pinning the underlying object and updating the frontbuffer tracking
13305 * bits. Some older platforms need special physical address handling for
13306 * cursor planes.
13307 *
13308 * Returns 0 on success, negative error code on failure.
13309 */
13310 int
13311 intel_prepare_plane_fb(struct drm_plane *plane,
13312 struct drm_framebuffer *fb,
13313 const struct drm_plane_state *new_state)
13314 {
13315 struct drm_device *dev = plane->dev;
13316 struct intel_plane *intel_plane = to_intel_plane(plane);
13317 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13318 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13319 int ret = 0;
13320
13321 if (!obj)
13322 return 0;
13323
13324 mutex_lock(&dev->struct_mutex);
13325
13326 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13327 INTEL_INFO(dev)->cursor_needs_physical) {
13328 int align = IS_I830(dev) ? 16 * 1024 : 256;
13329 ret = i915_gem_object_attach_phys(obj, align);
13330 if (ret)
13331 DRM_DEBUG_KMS("failed to attach phys object\n");
13332 } else {
13333 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13334 }
13335
13336 if (ret == 0)
13337 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13338
13339 mutex_unlock(&dev->struct_mutex);
13340
13341 return ret;
13342 }
13343
13344 /**
13345 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13346 * @plane: drm plane to clean up for
13347 * @fb: old framebuffer that was on plane
13348 *
13349 * Cleans up a framebuffer that has just been removed from a plane.
13350 */
13351 void
13352 intel_cleanup_plane_fb(struct drm_plane *plane,
13353 struct drm_framebuffer *fb,
13354 const struct drm_plane_state *old_state)
13355 {
13356 struct drm_device *dev = plane->dev;
13357 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13358
13359 if (WARN_ON(!obj))
13360 return;
13361
13362 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13363 !INTEL_INFO(dev)->cursor_needs_physical) {
13364 mutex_lock(&dev->struct_mutex);
13365 intel_unpin_fb_obj(fb, old_state);
13366 mutex_unlock(&dev->struct_mutex);
13367 }
13368 }
13369
13370 int
13371 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13372 {
13373 int max_scale;
13374 struct drm_device *dev;
13375 struct drm_i915_private *dev_priv;
13376 int crtc_clock, cdclk;
13377
13378 if (!intel_crtc || !crtc_state)
13379 return DRM_PLANE_HELPER_NO_SCALING;
13380
13381 dev = intel_crtc->base.dev;
13382 dev_priv = dev->dev_private;
13383 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13384 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13385
13386 if (!crtc_clock || !cdclk)
13387 return DRM_PLANE_HELPER_NO_SCALING;
13388
13389 /*
13390 * skl max scale is lower of:
13391 * close to 3 but not 3, -1 is for that purpose
13392 * or
13393 * cdclk/crtc_clock
13394 */
13395 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13396
13397 return max_scale;
13398 }
13399
13400 static int
13401 intel_check_primary_plane(struct drm_plane *plane,
13402 struct intel_crtc_state *crtc_state,
13403 struct intel_plane_state *state)
13404 {
13405 struct drm_crtc *crtc = state->base.crtc;
13406 struct drm_framebuffer *fb = state->base.fb;
13407 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13408 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13409 bool can_position = false;
13410
13411 /* use scaler when colorkey is not required */
13412 if (INTEL_INFO(plane->dev)->gen >= 9 &&
13413 state->ckey.flags == I915_SET_COLORKEY_NONE) {
13414 min_scale = 1;
13415 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13416 can_position = true;
13417 }
13418
13419 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13420 &state->dst, &state->clip,
13421 min_scale, max_scale,
13422 can_position, true,
13423 &state->visible);
13424 }
13425
13426 static void
13427 intel_commit_primary_plane(struct drm_plane *plane,
13428 struct intel_plane_state *state)
13429 {
13430 struct drm_crtc *crtc = state->base.crtc;
13431 struct drm_framebuffer *fb = state->base.fb;
13432 struct drm_device *dev = plane->dev;
13433 struct drm_i915_private *dev_priv = dev->dev_private;
13434 struct intel_crtc *intel_crtc;
13435 struct drm_rect *src = &state->src;
13436
13437 crtc = crtc ? crtc : plane->crtc;
13438 intel_crtc = to_intel_crtc(crtc);
13439
13440 plane->fb = fb;
13441 crtc->x = src->x1 >> 16;
13442 crtc->y = src->y1 >> 16;
13443
13444 if (!crtc->state->active)
13445 return;
13446
13447 if (state->visible)
13448 /* FIXME: kill this fastboot hack */
13449 intel_update_pipe_size(intel_crtc);
13450
13451 dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
13452 }
13453
13454 static void
13455 intel_disable_primary_plane(struct drm_plane *plane,
13456 struct drm_crtc *crtc)
13457 {
13458 struct drm_device *dev = plane->dev;
13459 struct drm_i915_private *dev_priv = dev->dev_private;
13460
13461 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13462 }
13463
13464 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13465 struct drm_crtc_state *old_crtc_state)
13466 {
13467 struct drm_device *dev = crtc->dev;
13468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13469
13470 if (intel_crtc->atomic.update_wm_pre)
13471 intel_update_watermarks(crtc);
13472
13473 /* Perform vblank evasion around commit operation */
13474 if (crtc->state->active)
13475 intel_pipe_update_start(intel_crtc, &intel_crtc->start_vbl_count);
13476
13477 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13478 skl_detach_scalers(intel_crtc);
13479 }
13480
13481 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13482 struct drm_crtc_state *old_crtc_state)
13483 {
13484 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13485
13486 if (crtc->state->active)
13487 intel_pipe_update_end(intel_crtc, intel_crtc->start_vbl_count);
13488 }
13489
13490 /**
13491 * intel_plane_destroy - destroy a plane
13492 * @plane: plane to destroy
13493 *
13494 * Common destruction function for all types of planes (primary, cursor,
13495 * sprite).
13496 */
13497 void intel_plane_destroy(struct drm_plane *plane)
13498 {
13499 struct intel_plane *intel_plane = to_intel_plane(plane);
13500 drm_plane_cleanup(plane);
13501 kfree(intel_plane);
13502 }
13503
13504 const struct drm_plane_funcs intel_plane_funcs = {
13505 .update_plane = drm_atomic_helper_update_plane,
13506 .disable_plane = drm_atomic_helper_disable_plane,
13507 .destroy = intel_plane_destroy,
13508 .set_property = drm_atomic_helper_plane_set_property,
13509 .atomic_get_property = intel_plane_atomic_get_property,
13510 .atomic_set_property = intel_plane_atomic_set_property,
13511 .atomic_duplicate_state = intel_plane_duplicate_state,
13512 .atomic_destroy_state = intel_plane_destroy_state,
13513
13514 };
13515
13516 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13517 int pipe)
13518 {
13519 struct intel_plane *primary;
13520 struct intel_plane_state *state;
13521 const uint32_t *intel_primary_formats;
13522 int num_formats;
13523
13524 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13525 if (primary == NULL)
13526 return NULL;
13527
13528 state = intel_create_plane_state(&primary->base);
13529 if (!state) {
13530 kfree(primary);
13531 return NULL;
13532 }
13533 primary->base.state = &state->base;
13534
13535 primary->can_scale = false;
13536 primary->max_downscale = 1;
13537 if (INTEL_INFO(dev)->gen >= 9) {
13538 primary->can_scale = true;
13539 state->scaler_id = -1;
13540 }
13541 primary->pipe = pipe;
13542 primary->plane = pipe;
13543 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13544 primary->check_plane = intel_check_primary_plane;
13545 primary->commit_plane = intel_commit_primary_plane;
13546 primary->disable_plane = intel_disable_primary_plane;
13547 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13548 primary->plane = !pipe;
13549
13550 if (INTEL_INFO(dev)->gen >= 9) {
13551 intel_primary_formats = skl_primary_formats;
13552 num_formats = ARRAY_SIZE(skl_primary_formats);
13553 } else if (INTEL_INFO(dev)->gen >= 4) {
13554 intel_primary_formats = i965_primary_formats;
13555 num_formats = ARRAY_SIZE(i965_primary_formats);
13556 } else {
13557 intel_primary_formats = i8xx_primary_formats;
13558 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13559 }
13560
13561 drm_universal_plane_init(dev, &primary->base, 0,
13562 &intel_plane_funcs,
13563 intel_primary_formats, num_formats,
13564 DRM_PLANE_TYPE_PRIMARY);
13565
13566 if (INTEL_INFO(dev)->gen >= 4)
13567 intel_create_rotation_property(dev, primary);
13568
13569 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13570
13571 return &primary->base;
13572 }
13573
13574 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13575 {
13576 if (!dev->mode_config.rotation_property) {
13577 unsigned long flags = BIT(DRM_ROTATE_0) |
13578 BIT(DRM_ROTATE_180);
13579
13580 if (INTEL_INFO(dev)->gen >= 9)
13581 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13582
13583 dev->mode_config.rotation_property =
13584 drm_mode_create_rotation_property(dev, flags);
13585 }
13586 if (dev->mode_config.rotation_property)
13587 drm_object_attach_property(&plane->base.base,
13588 dev->mode_config.rotation_property,
13589 plane->base.state->rotation);
13590 }
13591
13592 static int
13593 intel_check_cursor_plane(struct drm_plane *plane,
13594 struct intel_crtc_state *crtc_state,
13595 struct intel_plane_state *state)
13596 {
13597 struct drm_crtc *crtc = crtc_state->base.crtc;
13598 struct drm_framebuffer *fb = state->base.fb;
13599 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13600 unsigned stride;
13601 int ret;
13602
13603 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13604 &state->dst, &state->clip,
13605 DRM_PLANE_HELPER_NO_SCALING,
13606 DRM_PLANE_HELPER_NO_SCALING,
13607 true, true, &state->visible);
13608 if (ret)
13609 return ret;
13610
13611 /* if we want to turn off the cursor ignore width and height */
13612 if (!obj)
13613 return 0;
13614
13615 /* Check for which cursor types we support */
13616 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13617 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13618 state->base.crtc_w, state->base.crtc_h);
13619 return -EINVAL;
13620 }
13621
13622 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13623 if (obj->base.size < stride * state->base.crtc_h) {
13624 DRM_DEBUG_KMS("buffer is too small\n");
13625 return -ENOMEM;
13626 }
13627
13628 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13629 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13630 return -EINVAL;
13631 }
13632
13633 return 0;
13634 }
13635
13636 static void
13637 intel_disable_cursor_plane(struct drm_plane *plane,
13638 struct drm_crtc *crtc)
13639 {
13640 intel_crtc_update_cursor(crtc, false);
13641 }
13642
13643 static void
13644 intel_commit_cursor_plane(struct drm_plane *plane,
13645 struct intel_plane_state *state)
13646 {
13647 struct drm_crtc *crtc = state->base.crtc;
13648 struct drm_device *dev = plane->dev;
13649 struct intel_crtc *intel_crtc;
13650 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13651 uint32_t addr;
13652
13653 crtc = crtc ? crtc : plane->crtc;
13654 intel_crtc = to_intel_crtc(crtc);
13655
13656 plane->fb = state->base.fb;
13657 crtc->cursor_x = state->base.crtc_x;
13658 crtc->cursor_y = state->base.crtc_y;
13659
13660 if (intel_crtc->cursor_bo == obj)
13661 goto update;
13662
13663 if (!obj)
13664 addr = 0;
13665 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13666 addr = i915_gem_obj_ggtt_offset(obj);
13667 else
13668 addr = obj->phys_handle->busaddr;
13669
13670 intel_crtc->cursor_addr = addr;
13671 intel_crtc->cursor_bo = obj;
13672
13673 update:
13674 if (crtc->state->active)
13675 intel_crtc_update_cursor(crtc, state->visible);
13676 }
13677
13678 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13679 int pipe)
13680 {
13681 struct intel_plane *cursor;
13682 struct intel_plane_state *state;
13683
13684 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13685 if (cursor == NULL)
13686 return NULL;
13687
13688 state = intel_create_plane_state(&cursor->base);
13689 if (!state) {
13690 kfree(cursor);
13691 return NULL;
13692 }
13693 cursor->base.state = &state->base;
13694
13695 cursor->can_scale = false;
13696 cursor->max_downscale = 1;
13697 cursor->pipe = pipe;
13698 cursor->plane = pipe;
13699 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13700 cursor->check_plane = intel_check_cursor_plane;
13701 cursor->commit_plane = intel_commit_cursor_plane;
13702 cursor->disable_plane = intel_disable_cursor_plane;
13703
13704 drm_universal_plane_init(dev, &cursor->base, 0,
13705 &intel_plane_funcs,
13706 intel_cursor_formats,
13707 ARRAY_SIZE(intel_cursor_formats),
13708 DRM_PLANE_TYPE_CURSOR);
13709
13710 if (INTEL_INFO(dev)->gen >= 4) {
13711 if (!dev->mode_config.rotation_property)
13712 dev->mode_config.rotation_property =
13713 drm_mode_create_rotation_property(dev,
13714 BIT(DRM_ROTATE_0) |
13715 BIT(DRM_ROTATE_180));
13716 if (dev->mode_config.rotation_property)
13717 drm_object_attach_property(&cursor->base.base,
13718 dev->mode_config.rotation_property,
13719 state->base.rotation);
13720 }
13721
13722 if (INTEL_INFO(dev)->gen >=9)
13723 state->scaler_id = -1;
13724
13725 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13726
13727 return &cursor->base;
13728 }
13729
13730 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13731 struct intel_crtc_state *crtc_state)
13732 {
13733 int i;
13734 struct intel_scaler *intel_scaler;
13735 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13736
13737 for (i = 0; i < intel_crtc->num_scalers; i++) {
13738 intel_scaler = &scaler_state->scalers[i];
13739 intel_scaler->in_use = 0;
13740 intel_scaler->mode = PS_SCALER_MODE_DYN;
13741 }
13742
13743 scaler_state->scaler_id = -1;
13744 }
13745
13746 static void intel_crtc_init(struct drm_device *dev, int pipe)
13747 {
13748 struct drm_i915_private *dev_priv = dev->dev_private;
13749 struct intel_crtc *intel_crtc;
13750 struct intel_crtc_state *crtc_state = NULL;
13751 struct drm_plane *primary = NULL;
13752 struct drm_plane *cursor = NULL;
13753 int i, ret;
13754
13755 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13756 if (intel_crtc == NULL)
13757 return;
13758
13759 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13760 if (!crtc_state)
13761 goto fail;
13762 intel_crtc->config = crtc_state;
13763 intel_crtc->base.state = &crtc_state->base;
13764 crtc_state->base.crtc = &intel_crtc->base;
13765
13766 /* initialize shared scalers */
13767 if (INTEL_INFO(dev)->gen >= 9) {
13768 if (pipe == PIPE_C)
13769 intel_crtc->num_scalers = 1;
13770 else
13771 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13772
13773 skl_init_scalers(dev, intel_crtc, crtc_state);
13774 }
13775
13776 primary = intel_primary_plane_create(dev, pipe);
13777 if (!primary)
13778 goto fail;
13779
13780 cursor = intel_cursor_plane_create(dev, pipe);
13781 if (!cursor)
13782 goto fail;
13783
13784 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13785 cursor, &intel_crtc_funcs);
13786 if (ret)
13787 goto fail;
13788
13789 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13790 for (i = 0; i < 256; i++) {
13791 intel_crtc->lut_r[i] = i;
13792 intel_crtc->lut_g[i] = i;
13793 intel_crtc->lut_b[i] = i;
13794 }
13795
13796 /*
13797 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13798 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13799 */
13800 intel_crtc->pipe = pipe;
13801 intel_crtc->plane = pipe;
13802 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13803 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13804 intel_crtc->plane = !pipe;
13805 }
13806
13807 intel_crtc->cursor_base = ~0;
13808 intel_crtc->cursor_cntl = ~0;
13809 intel_crtc->cursor_size = ~0;
13810
13811 intel_crtc->wm.cxsr_allowed = true;
13812
13813 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13814 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13815 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13816 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13817
13818 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13819
13820 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13821 return;
13822
13823 fail:
13824 if (primary)
13825 drm_plane_cleanup(primary);
13826 if (cursor)
13827 drm_plane_cleanup(cursor);
13828 kfree(crtc_state);
13829 kfree(intel_crtc);
13830 }
13831
13832 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13833 {
13834 struct drm_encoder *encoder = connector->base.encoder;
13835 struct drm_device *dev = connector->base.dev;
13836
13837 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13838
13839 if (!encoder || WARN_ON(!encoder->crtc))
13840 return INVALID_PIPE;
13841
13842 return to_intel_crtc(encoder->crtc)->pipe;
13843 }
13844
13845 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13846 struct drm_file *file)
13847 {
13848 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13849 struct drm_crtc *drmmode_crtc;
13850 struct intel_crtc *crtc;
13851
13852 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13853
13854 if (!drmmode_crtc) {
13855 DRM_ERROR("no such CRTC id\n");
13856 return -ENOENT;
13857 }
13858
13859 crtc = to_intel_crtc(drmmode_crtc);
13860 pipe_from_crtc_id->pipe = crtc->pipe;
13861
13862 return 0;
13863 }
13864
13865 static int intel_encoder_clones(struct intel_encoder *encoder)
13866 {
13867 struct drm_device *dev = encoder->base.dev;
13868 struct intel_encoder *source_encoder;
13869 int index_mask = 0;
13870 int entry = 0;
13871
13872 for_each_intel_encoder(dev, source_encoder) {
13873 if (encoders_cloneable(encoder, source_encoder))
13874 index_mask |= (1 << entry);
13875
13876 entry++;
13877 }
13878
13879 return index_mask;
13880 }
13881
13882 static bool has_edp_a(struct drm_device *dev)
13883 {
13884 struct drm_i915_private *dev_priv = dev->dev_private;
13885
13886 if (!IS_MOBILE(dev))
13887 return false;
13888
13889 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13890 return false;
13891
13892 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13893 return false;
13894
13895 return true;
13896 }
13897
13898 static bool intel_crt_present(struct drm_device *dev)
13899 {
13900 struct drm_i915_private *dev_priv = dev->dev_private;
13901
13902 if (INTEL_INFO(dev)->gen >= 9)
13903 return false;
13904
13905 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13906 return false;
13907
13908 if (IS_CHERRYVIEW(dev))
13909 return false;
13910
13911 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13912 return false;
13913
13914 return true;
13915 }
13916
13917 static void intel_setup_outputs(struct drm_device *dev)
13918 {
13919 struct drm_i915_private *dev_priv = dev->dev_private;
13920 struct intel_encoder *encoder;
13921 bool dpd_is_edp = false;
13922
13923 intel_lvds_init(dev);
13924
13925 if (intel_crt_present(dev))
13926 intel_crt_init(dev);
13927
13928 if (IS_BROXTON(dev)) {
13929 /*
13930 * FIXME: Broxton doesn't support port detection via the
13931 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13932 * detect the ports.
13933 */
13934 intel_ddi_init(dev, PORT_A);
13935 intel_ddi_init(dev, PORT_B);
13936 intel_ddi_init(dev, PORT_C);
13937 } else if (HAS_DDI(dev)) {
13938 int found;
13939
13940 /*
13941 * Haswell uses DDI functions to detect digital outputs.
13942 * On SKL pre-D0 the strap isn't connected, so we assume
13943 * it's there.
13944 */
13945 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13946 /* WaIgnoreDDIAStrap: skl */
13947 if (found ||
13948 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
13949 intel_ddi_init(dev, PORT_A);
13950
13951 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13952 * register */
13953 found = I915_READ(SFUSE_STRAP);
13954
13955 if (found & SFUSE_STRAP_DDIB_DETECTED)
13956 intel_ddi_init(dev, PORT_B);
13957 if (found & SFUSE_STRAP_DDIC_DETECTED)
13958 intel_ddi_init(dev, PORT_C);
13959 if (found & SFUSE_STRAP_DDID_DETECTED)
13960 intel_ddi_init(dev, PORT_D);
13961 } else if (HAS_PCH_SPLIT(dev)) {
13962 int found;
13963 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
13964
13965 if (has_edp_a(dev))
13966 intel_dp_init(dev, DP_A, PORT_A);
13967
13968 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13969 /* PCH SDVOB multiplex with HDMIB */
13970 found = intel_sdvo_init(dev, PCH_SDVOB, true);
13971 if (!found)
13972 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
13973 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13974 intel_dp_init(dev, PCH_DP_B, PORT_B);
13975 }
13976
13977 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13978 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
13979
13980 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13981 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
13982
13983 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13984 intel_dp_init(dev, PCH_DP_C, PORT_C);
13985
13986 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13987 intel_dp_init(dev, PCH_DP_D, PORT_D);
13988 } else if (IS_VALLEYVIEW(dev)) {
13989 /*
13990 * The DP_DETECTED bit is the latched state of the DDC
13991 * SDA pin at boot. However since eDP doesn't require DDC
13992 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13993 * eDP ports may have been muxed to an alternate function.
13994 * Thus we can't rely on the DP_DETECTED bit alone to detect
13995 * eDP ports. Consult the VBT as well as DP_DETECTED to
13996 * detect eDP ports.
13997 */
13998 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13999 !intel_dp_is_edp(dev, PORT_B))
14000 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14001 PORT_B);
14002 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14003 intel_dp_is_edp(dev, PORT_B))
14004 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14005
14006 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14007 !intel_dp_is_edp(dev, PORT_C))
14008 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14009 PORT_C);
14010 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14011 intel_dp_is_edp(dev, PORT_C))
14012 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14013
14014 if (IS_CHERRYVIEW(dev)) {
14015 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14016 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14017 PORT_D);
14018 /* eDP not supported on port D, so don't check VBT */
14019 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14020 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14021 }
14022
14023 intel_dsi_init(dev);
14024 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14025 bool found = false;
14026
14027 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14028 DRM_DEBUG_KMS("probing SDVOB\n");
14029 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14030 if (!found && IS_G4X(dev)) {
14031 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14032 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14033 }
14034
14035 if (!found && IS_G4X(dev))
14036 intel_dp_init(dev, DP_B, PORT_B);
14037 }
14038
14039 /* Before G4X SDVOC doesn't have its own detect register */
14040
14041 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14042 DRM_DEBUG_KMS("probing SDVOC\n");
14043 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14044 }
14045
14046 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14047
14048 if (IS_G4X(dev)) {
14049 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14050 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14051 }
14052 if (IS_G4X(dev))
14053 intel_dp_init(dev, DP_C, PORT_C);
14054 }
14055
14056 if (IS_G4X(dev) &&
14057 (I915_READ(DP_D) & DP_DETECTED))
14058 intel_dp_init(dev, DP_D, PORT_D);
14059 } else if (IS_GEN2(dev))
14060 intel_dvo_init(dev);
14061
14062 if (SUPPORTS_TV(dev))
14063 intel_tv_init(dev);
14064
14065 intel_psr_init(dev);
14066
14067 for_each_intel_encoder(dev, encoder) {
14068 encoder->base.possible_crtcs = encoder->crtc_mask;
14069 encoder->base.possible_clones =
14070 intel_encoder_clones(encoder);
14071 }
14072
14073 intel_init_pch_refclk(dev);
14074
14075 drm_helper_move_panel_connectors_to_head(dev);
14076 }
14077
14078 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14079 {
14080 struct drm_device *dev = fb->dev;
14081 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14082
14083 drm_framebuffer_cleanup(fb);
14084 mutex_lock(&dev->struct_mutex);
14085 WARN_ON(!intel_fb->obj->framebuffer_references--);
14086 drm_gem_object_unreference(&intel_fb->obj->base);
14087 mutex_unlock(&dev->struct_mutex);
14088 kfree(intel_fb);
14089 }
14090
14091 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14092 struct drm_file *file,
14093 unsigned int *handle)
14094 {
14095 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14096 struct drm_i915_gem_object *obj = intel_fb->obj;
14097
14098 return drm_gem_handle_create(file, &obj->base, handle);
14099 }
14100
14101 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14102 struct drm_file *file,
14103 unsigned flags, unsigned color,
14104 struct drm_clip_rect *clips,
14105 unsigned num_clips)
14106 {
14107 struct drm_device *dev = fb->dev;
14108 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14109 struct drm_i915_gem_object *obj = intel_fb->obj;
14110
14111 mutex_lock(&dev->struct_mutex);
14112 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14113 mutex_unlock(&dev->struct_mutex);
14114
14115 return 0;
14116 }
14117
14118 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14119 .destroy = intel_user_framebuffer_destroy,
14120 .create_handle = intel_user_framebuffer_create_handle,
14121 .dirty = intel_user_framebuffer_dirty,
14122 };
14123
14124 static
14125 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14126 uint32_t pixel_format)
14127 {
14128 u32 gen = INTEL_INFO(dev)->gen;
14129
14130 if (gen >= 9) {
14131 /* "The stride in bytes must not exceed the of the size of 8K
14132 * pixels and 32K bytes."
14133 */
14134 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14135 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14136 return 32*1024;
14137 } else if (gen >= 4) {
14138 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14139 return 16*1024;
14140 else
14141 return 32*1024;
14142 } else if (gen >= 3) {
14143 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14144 return 8*1024;
14145 else
14146 return 16*1024;
14147 } else {
14148 /* XXX DSPC is limited to 4k tiled */
14149 return 8*1024;
14150 }
14151 }
14152
14153 static int intel_framebuffer_init(struct drm_device *dev,
14154 struct intel_framebuffer *intel_fb,
14155 struct drm_mode_fb_cmd2 *mode_cmd,
14156 struct drm_i915_gem_object *obj)
14157 {
14158 unsigned int aligned_height;
14159 int ret;
14160 u32 pitch_limit, stride_alignment;
14161
14162 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14163
14164 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14165 /* Enforce that fb modifier and tiling mode match, but only for
14166 * X-tiled. This is needed for FBC. */
14167 if (!!(obj->tiling_mode == I915_TILING_X) !=
14168 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14169 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14170 return -EINVAL;
14171 }
14172 } else {
14173 if (obj->tiling_mode == I915_TILING_X)
14174 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14175 else if (obj->tiling_mode == I915_TILING_Y) {
14176 DRM_DEBUG("No Y tiling for legacy addfb\n");
14177 return -EINVAL;
14178 }
14179 }
14180
14181 /* Passed in modifier sanity checking. */
14182 switch (mode_cmd->modifier[0]) {
14183 case I915_FORMAT_MOD_Y_TILED:
14184 case I915_FORMAT_MOD_Yf_TILED:
14185 if (INTEL_INFO(dev)->gen < 9) {
14186 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14187 mode_cmd->modifier[0]);
14188 return -EINVAL;
14189 }
14190 case DRM_FORMAT_MOD_NONE:
14191 case I915_FORMAT_MOD_X_TILED:
14192 break;
14193 default:
14194 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14195 mode_cmd->modifier[0]);
14196 return -EINVAL;
14197 }
14198
14199 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14200 mode_cmd->pixel_format);
14201 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14202 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14203 mode_cmd->pitches[0], stride_alignment);
14204 return -EINVAL;
14205 }
14206
14207 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14208 mode_cmd->pixel_format);
14209 if (mode_cmd->pitches[0] > pitch_limit) {
14210 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14211 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14212 "tiled" : "linear",
14213 mode_cmd->pitches[0], pitch_limit);
14214 return -EINVAL;
14215 }
14216
14217 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14218 mode_cmd->pitches[0] != obj->stride) {
14219 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14220 mode_cmd->pitches[0], obj->stride);
14221 return -EINVAL;
14222 }
14223
14224 /* Reject formats not supported by any plane early. */
14225 switch (mode_cmd->pixel_format) {
14226 case DRM_FORMAT_C8:
14227 case DRM_FORMAT_RGB565:
14228 case DRM_FORMAT_XRGB8888:
14229 case DRM_FORMAT_ARGB8888:
14230 break;
14231 case DRM_FORMAT_XRGB1555:
14232 if (INTEL_INFO(dev)->gen > 3) {
14233 DRM_DEBUG("unsupported pixel format: %s\n",
14234 drm_get_format_name(mode_cmd->pixel_format));
14235 return -EINVAL;
14236 }
14237 break;
14238 case DRM_FORMAT_ABGR8888:
14239 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14240 DRM_DEBUG("unsupported pixel format: %s\n",
14241 drm_get_format_name(mode_cmd->pixel_format));
14242 return -EINVAL;
14243 }
14244 break;
14245 case DRM_FORMAT_XBGR8888:
14246 case DRM_FORMAT_XRGB2101010:
14247 case DRM_FORMAT_XBGR2101010:
14248 if (INTEL_INFO(dev)->gen < 4) {
14249 DRM_DEBUG("unsupported pixel format: %s\n",
14250 drm_get_format_name(mode_cmd->pixel_format));
14251 return -EINVAL;
14252 }
14253 break;
14254 case DRM_FORMAT_ABGR2101010:
14255 if (!IS_VALLEYVIEW(dev)) {
14256 DRM_DEBUG("unsupported pixel format: %s\n",
14257 drm_get_format_name(mode_cmd->pixel_format));
14258 return -EINVAL;
14259 }
14260 break;
14261 case DRM_FORMAT_YUYV:
14262 case DRM_FORMAT_UYVY:
14263 case DRM_FORMAT_YVYU:
14264 case DRM_FORMAT_VYUY:
14265 if (INTEL_INFO(dev)->gen < 5) {
14266 DRM_DEBUG("unsupported pixel format: %s\n",
14267 drm_get_format_name(mode_cmd->pixel_format));
14268 return -EINVAL;
14269 }
14270 break;
14271 default:
14272 DRM_DEBUG("unsupported pixel format: %s\n",
14273 drm_get_format_name(mode_cmd->pixel_format));
14274 return -EINVAL;
14275 }
14276
14277 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14278 if (mode_cmd->offsets[0] != 0)
14279 return -EINVAL;
14280
14281 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14282 mode_cmd->pixel_format,
14283 mode_cmd->modifier[0]);
14284 /* FIXME drm helper for size checks (especially planar formats)? */
14285 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14286 return -EINVAL;
14287
14288 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14289 intel_fb->obj = obj;
14290 intel_fb->obj->framebuffer_references++;
14291
14292 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14293 if (ret) {
14294 DRM_ERROR("framebuffer init failed %d\n", ret);
14295 return ret;
14296 }
14297
14298 return 0;
14299 }
14300
14301 static struct drm_framebuffer *
14302 intel_user_framebuffer_create(struct drm_device *dev,
14303 struct drm_file *filp,
14304 struct drm_mode_fb_cmd2 *mode_cmd)
14305 {
14306 struct drm_i915_gem_object *obj;
14307
14308 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14309 mode_cmd->handles[0]));
14310 if (&obj->base == NULL)
14311 return ERR_PTR(-ENOENT);
14312
14313 return intel_framebuffer_create(dev, mode_cmd, obj);
14314 }
14315
14316 #ifndef CONFIG_DRM_I915_FBDEV
14317 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14318 {
14319 }
14320 #endif
14321
14322 static const struct drm_mode_config_funcs intel_mode_funcs = {
14323 .fb_create = intel_user_framebuffer_create,
14324 .output_poll_changed = intel_fbdev_output_poll_changed,
14325 .atomic_check = intel_atomic_check,
14326 .atomic_commit = intel_atomic_commit,
14327 .atomic_state_alloc = intel_atomic_state_alloc,
14328 .atomic_state_clear = intel_atomic_state_clear,
14329 };
14330
14331 /* Set up chip specific display functions */
14332 static void intel_init_display(struct drm_device *dev)
14333 {
14334 struct drm_i915_private *dev_priv = dev->dev_private;
14335
14336 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14337 dev_priv->display.find_dpll = g4x_find_best_dpll;
14338 else if (IS_CHERRYVIEW(dev))
14339 dev_priv->display.find_dpll = chv_find_best_dpll;
14340 else if (IS_VALLEYVIEW(dev))
14341 dev_priv->display.find_dpll = vlv_find_best_dpll;
14342 else if (IS_PINEVIEW(dev))
14343 dev_priv->display.find_dpll = pnv_find_best_dpll;
14344 else
14345 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14346
14347 if (INTEL_INFO(dev)->gen >= 9) {
14348 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14349 dev_priv->display.get_initial_plane_config =
14350 skylake_get_initial_plane_config;
14351 dev_priv->display.crtc_compute_clock =
14352 haswell_crtc_compute_clock;
14353 dev_priv->display.crtc_enable = haswell_crtc_enable;
14354 dev_priv->display.crtc_disable = haswell_crtc_disable;
14355 dev_priv->display.update_primary_plane =
14356 skylake_update_primary_plane;
14357 } else if (HAS_DDI(dev)) {
14358 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14359 dev_priv->display.get_initial_plane_config =
14360 ironlake_get_initial_plane_config;
14361 dev_priv->display.crtc_compute_clock =
14362 haswell_crtc_compute_clock;
14363 dev_priv->display.crtc_enable = haswell_crtc_enable;
14364 dev_priv->display.crtc_disable = haswell_crtc_disable;
14365 dev_priv->display.update_primary_plane =
14366 ironlake_update_primary_plane;
14367 } else if (HAS_PCH_SPLIT(dev)) {
14368 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14369 dev_priv->display.get_initial_plane_config =
14370 ironlake_get_initial_plane_config;
14371 dev_priv->display.crtc_compute_clock =
14372 ironlake_crtc_compute_clock;
14373 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14374 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14375 dev_priv->display.update_primary_plane =
14376 ironlake_update_primary_plane;
14377 } else if (IS_VALLEYVIEW(dev)) {
14378 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14379 dev_priv->display.get_initial_plane_config =
14380 i9xx_get_initial_plane_config;
14381 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14382 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14383 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14384 dev_priv->display.update_primary_plane =
14385 i9xx_update_primary_plane;
14386 } else {
14387 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14388 dev_priv->display.get_initial_plane_config =
14389 i9xx_get_initial_plane_config;
14390 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14391 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14392 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14393 dev_priv->display.update_primary_plane =
14394 i9xx_update_primary_plane;
14395 }
14396
14397 /* Returns the core display clock speed */
14398 if (IS_SKYLAKE(dev))
14399 dev_priv->display.get_display_clock_speed =
14400 skylake_get_display_clock_speed;
14401 else if (IS_BROXTON(dev))
14402 dev_priv->display.get_display_clock_speed =
14403 broxton_get_display_clock_speed;
14404 else if (IS_BROADWELL(dev))
14405 dev_priv->display.get_display_clock_speed =
14406 broadwell_get_display_clock_speed;
14407 else if (IS_HASWELL(dev))
14408 dev_priv->display.get_display_clock_speed =
14409 haswell_get_display_clock_speed;
14410 else if (IS_VALLEYVIEW(dev))
14411 dev_priv->display.get_display_clock_speed =
14412 valleyview_get_display_clock_speed;
14413 else if (IS_GEN5(dev))
14414 dev_priv->display.get_display_clock_speed =
14415 ilk_get_display_clock_speed;
14416 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14417 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14418 dev_priv->display.get_display_clock_speed =
14419 i945_get_display_clock_speed;
14420 else if (IS_GM45(dev))
14421 dev_priv->display.get_display_clock_speed =
14422 gm45_get_display_clock_speed;
14423 else if (IS_CRESTLINE(dev))
14424 dev_priv->display.get_display_clock_speed =
14425 i965gm_get_display_clock_speed;
14426 else if (IS_PINEVIEW(dev))
14427 dev_priv->display.get_display_clock_speed =
14428 pnv_get_display_clock_speed;
14429 else if (IS_G33(dev) || IS_G4X(dev))
14430 dev_priv->display.get_display_clock_speed =
14431 g33_get_display_clock_speed;
14432 else if (IS_I915G(dev))
14433 dev_priv->display.get_display_clock_speed =
14434 i915_get_display_clock_speed;
14435 else if (IS_I945GM(dev) || IS_845G(dev))
14436 dev_priv->display.get_display_clock_speed =
14437 i9xx_misc_get_display_clock_speed;
14438 else if (IS_PINEVIEW(dev))
14439 dev_priv->display.get_display_clock_speed =
14440 pnv_get_display_clock_speed;
14441 else if (IS_I915GM(dev))
14442 dev_priv->display.get_display_clock_speed =
14443 i915gm_get_display_clock_speed;
14444 else if (IS_I865G(dev))
14445 dev_priv->display.get_display_clock_speed =
14446 i865_get_display_clock_speed;
14447 else if (IS_I85X(dev))
14448 dev_priv->display.get_display_clock_speed =
14449 i85x_get_display_clock_speed;
14450 else { /* 830 */
14451 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14452 dev_priv->display.get_display_clock_speed =
14453 i830_get_display_clock_speed;
14454 }
14455
14456 if (IS_GEN5(dev)) {
14457 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14458 } else if (IS_GEN6(dev)) {
14459 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14460 } else if (IS_IVYBRIDGE(dev)) {
14461 /* FIXME: detect B0+ stepping and use auto training */
14462 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14463 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14464 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14465 if (IS_BROADWELL(dev)) {
14466 dev_priv->display.modeset_commit_cdclk =
14467 broadwell_modeset_commit_cdclk;
14468 dev_priv->display.modeset_calc_cdclk =
14469 broadwell_modeset_calc_cdclk;
14470 }
14471 } else if (IS_VALLEYVIEW(dev)) {
14472 dev_priv->display.modeset_commit_cdclk =
14473 valleyview_modeset_commit_cdclk;
14474 dev_priv->display.modeset_calc_cdclk =
14475 valleyview_modeset_calc_cdclk;
14476 } else if (IS_BROXTON(dev)) {
14477 dev_priv->display.modeset_commit_cdclk =
14478 broxton_modeset_commit_cdclk;
14479 dev_priv->display.modeset_calc_cdclk =
14480 broxton_modeset_calc_cdclk;
14481 }
14482
14483 switch (INTEL_INFO(dev)->gen) {
14484 case 2:
14485 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14486 break;
14487
14488 case 3:
14489 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14490 break;
14491
14492 case 4:
14493 case 5:
14494 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14495 break;
14496
14497 case 6:
14498 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14499 break;
14500 case 7:
14501 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14502 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14503 break;
14504 case 9:
14505 /* Drop through - unsupported since execlist only. */
14506 default:
14507 /* Default just returns -ENODEV to indicate unsupported */
14508 dev_priv->display.queue_flip = intel_default_queue_flip;
14509 }
14510
14511 intel_panel_init_backlight_funcs(dev);
14512
14513 mutex_init(&dev_priv->pps_mutex);
14514 }
14515
14516 /*
14517 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14518 * resume, or other times. This quirk makes sure that's the case for
14519 * affected systems.
14520 */
14521 static void quirk_pipea_force(struct drm_device *dev)
14522 {
14523 struct drm_i915_private *dev_priv = dev->dev_private;
14524
14525 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14526 DRM_INFO("applying pipe a force quirk\n");
14527 }
14528
14529 static void quirk_pipeb_force(struct drm_device *dev)
14530 {
14531 struct drm_i915_private *dev_priv = dev->dev_private;
14532
14533 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14534 DRM_INFO("applying pipe b force quirk\n");
14535 }
14536
14537 /*
14538 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14539 */
14540 static void quirk_ssc_force_disable(struct drm_device *dev)
14541 {
14542 struct drm_i915_private *dev_priv = dev->dev_private;
14543 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14544 DRM_INFO("applying lvds SSC disable quirk\n");
14545 }
14546
14547 /*
14548 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14549 * brightness value
14550 */
14551 static void quirk_invert_brightness(struct drm_device *dev)
14552 {
14553 struct drm_i915_private *dev_priv = dev->dev_private;
14554 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14555 DRM_INFO("applying inverted panel brightness quirk\n");
14556 }
14557
14558 /* Some VBT's incorrectly indicate no backlight is present */
14559 static void quirk_backlight_present(struct drm_device *dev)
14560 {
14561 struct drm_i915_private *dev_priv = dev->dev_private;
14562 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14563 DRM_INFO("applying backlight present quirk\n");
14564 }
14565
14566 struct intel_quirk {
14567 int device;
14568 int subsystem_vendor;
14569 int subsystem_device;
14570 void (*hook)(struct drm_device *dev);
14571 };
14572
14573 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14574 struct intel_dmi_quirk {
14575 void (*hook)(struct drm_device *dev);
14576 const struct dmi_system_id (*dmi_id_list)[];
14577 };
14578
14579 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14580 {
14581 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14582 return 1;
14583 }
14584
14585 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14586 {
14587 .dmi_id_list = &(const struct dmi_system_id[]) {
14588 {
14589 .callback = intel_dmi_reverse_brightness,
14590 .ident = "NCR Corporation",
14591 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14592 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14593 },
14594 },
14595 { } /* terminating entry */
14596 },
14597 .hook = quirk_invert_brightness,
14598 },
14599 };
14600
14601 static struct intel_quirk intel_quirks[] = {
14602 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14603 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14604
14605 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14606 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14607
14608 /* 830 needs to leave pipe A & dpll A up */
14609 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14610
14611 /* 830 needs to leave pipe B & dpll B up */
14612 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14613
14614 /* Lenovo U160 cannot use SSC on LVDS */
14615 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14616
14617 /* Sony Vaio Y cannot use SSC on LVDS */
14618 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14619
14620 /* Acer Aspire 5734Z must invert backlight brightness */
14621 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14622
14623 /* Acer/eMachines G725 */
14624 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14625
14626 /* Acer/eMachines e725 */
14627 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14628
14629 /* Acer/Packard Bell NCL20 */
14630 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14631
14632 /* Acer Aspire 4736Z */
14633 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14634
14635 /* Acer Aspire 5336 */
14636 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14637
14638 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14639 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14640
14641 /* Acer C720 Chromebook (Core i3 4005U) */
14642 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14643
14644 /* Apple Macbook 2,1 (Core 2 T7400) */
14645 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14646
14647 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14648 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14649
14650 /* HP Chromebook 14 (Celeron 2955U) */
14651 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14652
14653 /* Dell Chromebook 11 */
14654 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14655 };
14656
14657 static void intel_init_quirks(struct drm_device *dev)
14658 {
14659 struct pci_dev *d = dev->pdev;
14660 int i;
14661
14662 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14663 struct intel_quirk *q = &intel_quirks[i];
14664
14665 if (d->device == q->device &&
14666 (d->subsystem_vendor == q->subsystem_vendor ||
14667 q->subsystem_vendor == PCI_ANY_ID) &&
14668 (d->subsystem_device == q->subsystem_device ||
14669 q->subsystem_device == PCI_ANY_ID))
14670 q->hook(dev);
14671 }
14672 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14673 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14674 intel_dmi_quirks[i].hook(dev);
14675 }
14676 }
14677
14678 /* Disable the VGA plane that we never use */
14679 static void i915_disable_vga(struct drm_device *dev)
14680 {
14681 struct drm_i915_private *dev_priv = dev->dev_private;
14682 u8 sr1;
14683 u32 vga_reg = i915_vgacntrl_reg(dev);
14684
14685 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14686 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14687 outb(SR01, VGA_SR_INDEX);
14688 sr1 = inb(VGA_SR_DATA);
14689 outb(sr1 | 1<<5, VGA_SR_DATA);
14690 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14691 udelay(300);
14692
14693 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14694 POSTING_READ(vga_reg);
14695 }
14696
14697 void intel_modeset_init_hw(struct drm_device *dev)
14698 {
14699 intel_update_cdclk(dev);
14700 intel_prepare_ddi(dev);
14701 intel_init_clock_gating(dev);
14702 intel_enable_gt_powersave(dev);
14703 }
14704
14705 void intel_modeset_init(struct drm_device *dev)
14706 {
14707 struct drm_i915_private *dev_priv = dev->dev_private;
14708 int sprite, ret;
14709 enum pipe pipe;
14710 struct intel_crtc *crtc;
14711
14712 drm_mode_config_init(dev);
14713
14714 dev->mode_config.min_width = 0;
14715 dev->mode_config.min_height = 0;
14716
14717 dev->mode_config.preferred_depth = 24;
14718 dev->mode_config.prefer_shadow = 1;
14719
14720 dev->mode_config.allow_fb_modifiers = true;
14721
14722 dev->mode_config.funcs = &intel_mode_funcs;
14723
14724 intel_init_quirks(dev);
14725
14726 intel_init_pm(dev);
14727
14728 if (INTEL_INFO(dev)->num_pipes == 0)
14729 return;
14730
14731 intel_init_display(dev);
14732 intel_init_audio(dev);
14733
14734 if (IS_GEN2(dev)) {
14735 dev->mode_config.max_width = 2048;
14736 dev->mode_config.max_height = 2048;
14737 } else if (IS_GEN3(dev)) {
14738 dev->mode_config.max_width = 4096;
14739 dev->mode_config.max_height = 4096;
14740 } else {
14741 dev->mode_config.max_width = 8192;
14742 dev->mode_config.max_height = 8192;
14743 }
14744
14745 if (IS_845G(dev) || IS_I865G(dev)) {
14746 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14747 dev->mode_config.cursor_height = 1023;
14748 } else if (IS_GEN2(dev)) {
14749 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14750 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14751 } else {
14752 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14753 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14754 }
14755
14756 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14757
14758 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14759 INTEL_INFO(dev)->num_pipes,
14760 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14761
14762 for_each_pipe(dev_priv, pipe) {
14763 intel_crtc_init(dev, pipe);
14764 for_each_sprite(dev_priv, pipe, sprite) {
14765 ret = intel_plane_init(dev, pipe, sprite);
14766 if (ret)
14767 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14768 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14769 }
14770 }
14771
14772 intel_init_dpio(dev);
14773
14774 intel_shared_dpll_init(dev);
14775
14776 /* Just disable it once at startup */
14777 i915_disable_vga(dev);
14778 intel_setup_outputs(dev);
14779
14780 /* Just in case the BIOS is doing something questionable. */
14781 intel_fbc_disable(dev_priv);
14782
14783 drm_modeset_lock_all(dev);
14784 intel_modeset_setup_hw_state(dev);
14785 drm_modeset_unlock_all(dev);
14786
14787 for_each_intel_crtc(dev, crtc) {
14788 struct intel_initial_plane_config plane_config = {};
14789
14790 if (!crtc->active)
14791 continue;
14792
14793 /*
14794 * Note that reserving the BIOS fb up front prevents us
14795 * from stuffing other stolen allocations like the ring
14796 * on top. This prevents some ugliness at boot time, and
14797 * can even allow for smooth boot transitions if the BIOS
14798 * fb is large enough for the active pipe configuration.
14799 */
14800 dev_priv->display.get_initial_plane_config(crtc,
14801 &plane_config);
14802
14803 /*
14804 * If the fb is shared between multiple heads, we'll
14805 * just get the first one.
14806 */
14807 intel_find_initial_plane_obj(crtc, &plane_config);
14808 }
14809 }
14810
14811 static void intel_enable_pipe_a(struct drm_device *dev)
14812 {
14813 struct intel_connector *connector;
14814 struct drm_connector *crt = NULL;
14815 struct intel_load_detect_pipe load_detect_temp;
14816 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14817
14818 /* We can't just switch on the pipe A, we need to set things up with a
14819 * proper mode and output configuration. As a gross hack, enable pipe A
14820 * by enabling the load detect pipe once. */
14821 for_each_intel_connector(dev, connector) {
14822 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14823 crt = &connector->base;
14824 break;
14825 }
14826 }
14827
14828 if (!crt)
14829 return;
14830
14831 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14832 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14833 }
14834
14835 static bool
14836 intel_check_plane_mapping(struct intel_crtc *crtc)
14837 {
14838 struct drm_device *dev = crtc->base.dev;
14839 struct drm_i915_private *dev_priv = dev->dev_private;
14840 u32 reg, val;
14841
14842 if (INTEL_INFO(dev)->num_pipes == 1)
14843 return true;
14844
14845 reg = DSPCNTR(!crtc->plane);
14846 val = I915_READ(reg);
14847
14848 if ((val & DISPLAY_PLANE_ENABLE) &&
14849 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14850 return false;
14851
14852 return true;
14853 }
14854
14855 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14856 {
14857 struct drm_device *dev = crtc->base.dev;
14858 struct drm_i915_private *dev_priv = dev->dev_private;
14859 struct intel_encoder *encoder;
14860 u32 reg;
14861 bool enable;
14862
14863 /* Clear any frame start delays used for debugging left by the BIOS */
14864 reg = PIPECONF(crtc->config->cpu_transcoder);
14865 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14866
14867 /* restore vblank interrupts to correct state */
14868 drm_crtc_vblank_reset(&crtc->base);
14869 if (crtc->active) {
14870 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
14871 update_scanline_offset(crtc);
14872 drm_crtc_vblank_on(&crtc->base);
14873 }
14874
14875 /* We need to sanitize the plane -> pipe mapping first because this will
14876 * disable the crtc (and hence change the state) if it is wrong. Note
14877 * that gen4+ has a fixed plane -> pipe mapping. */
14878 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14879 bool plane;
14880
14881 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14882 crtc->base.base.id);
14883
14884 /* Pipe has the wrong plane attached and the plane is active.
14885 * Temporarily change the plane mapping and disable everything
14886 * ... */
14887 plane = crtc->plane;
14888 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14889 crtc->plane = !plane;
14890 intel_crtc_disable_noatomic(&crtc->base);
14891 crtc->plane = plane;
14892 }
14893
14894 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14895 crtc->pipe == PIPE_A && !crtc->active) {
14896 /* BIOS forgot to enable pipe A, this mostly happens after
14897 * resume. Force-enable the pipe to fix this, the update_dpms
14898 * call below we restore the pipe to the right state, but leave
14899 * the required bits on. */
14900 intel_enable_pipe_a(dev);
14901 }
14902
14903 /* Adjust the state of the output pipe according to whether we
14904 * have active connectors/encoders. */
14905 enable = false;
14906 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14907 enable = true;
14908 break;
14909 }
14910
14911 if (!enable)
14912 intel_crtc_disable_noatomic(&crtc->base);
14913
14914 if (crtc->active != crtc->base.state->active) {
14915
14916 /* This can happen either due to bugs in the get_hw_state
14917 * functions or because of calls to intel_crtc_disable_noatomic,
14918 * or because the pipe is force-enabled due to the
14919 * pipe A quirk. */
14920 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14921 crtc->base.base.id,
14922 crtc->base.state->enable ? "enabled" : "disabled",
14923 crtc->active ? "enabled" : "disabled");
14924
14925 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
14926 crtc->base.state->active = crtc->active;
14927 crtc->base.enabled = crtc->active;
14928
14929 /* Because we only establish the connector -> encoder ->
14930 * crtc links if something is active, this means the
14931 * crtc is now deactivated. Break the links. connector
14932 * -> encoder links are only establish when things are
14933 * actually up, hence no need to break them. */
14934 WARN_ON(crtc->active);
14935
14936 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14937 encoder->base.crtc = NULL;
14938 }
14939
14940 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
14941 /*
14942 * We start out with underrun reporting disabled to avoid races.
14943 * For correct bookkeeping mark this on active crtcs.
14944 *
14945 * Also on gmch platforms we dont have any hardware bits to
14946 * disable the underrun reporting. Which means we need to start
14947 * out with underrun reporting disabled also on inactive pipes,
14948 * since otherwise we'll complain about the garbage we read when
14949 * e.g. coming up after runtime pm.
14950 *
14951 * No protection against concurrent access is required - at
14952 * worst a fifo underrun happens which also sets this to false.
14953 */
14954 crtc->cpu_fifo_underrun_disabled = true;
14955 crtc->pch_fifo_underrun_disabled = true;
14956 }
14957 }
14958
14959 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14960 {
14961 struct intel_connector *connector;
14962 struct drm_device *dev = encoder->base.dev;
14963 bool active = false;
14964
14965 /* We need to check both for a crtc link (meaning that the
14966 * encoder is active and trying to read from a pipe) and the
14967 * pipe itself being active. */
14968 bool has_active_crtc = encoder->base.crtc &&
14969 to_intel_crtc(encoder->base.crtc)->active;
14970
14971 for_each_intel_connector(dev, connector) {
14972 if (connector->base.encoder != &encoder->base)
14973 continue;
14974
14975 active = true;
14976 break;
14977 }
14978
14979 if (active && !has_active_crtc) {
14980 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14981 encoder->base.base.id,
14982 encoder->base.name);
14983
14984 /* Connector is active, but has no active pipe. This is
14985 * fallout from our resume register restoring. Disable
14986 * the encoder manually again. */
14987 if (encoder->base.crtc) {
14988 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14989 encoder->base.base.id,
14990 encoder->base.name);
14991 encoder->disable(encoder);
14992 if (encoder->post_disable)
14993 encoder->post_disable(encoder);
14994 }
14995 encoder->base.crtc = NULL;
14996
14997 /* Inconsistent output/port/pipe state happens presumably due to
14998 * a bug in one of the get_hw_state functions. Or someplace else
14999 * in our code, like the register restore mess on resume. Clamp
15000 * things to off as a safer default. */
15001 for_each_intel_connector(dev, connector) {
15002 if (connector->encoder != encoder)
15003 continue;
15004 connector->base.dpms = DRM_MODE_DPMS_OFF;
15005 connector->base.encoder = NULL;
15006 }
15007 }
15008 /* Enabled encoders without active connectors will be fixed in
15009 * the crtc fixup. */
15010 }
15011
15012 void i915_redisable_vga_power_on(struct drm_device *dev)
15013 {
15014 struct drm_i915_private *dev_priv = dev->dev_private;
15015 u32 vga_reg = i915_vgacntrl_reg(dev);
15016
15017 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15018 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15019 i915_disable_vga(dev);
15020 }
15021 }
15022
15023 void i915_redisable_vga(struct drm_device *dev)
15024 {
15025 struct drm_i915_private *dev_priv = dev->dev_private;
15026
15027 /* This function can be called both from intel_modeset_setup_hw_state or
15028 * at a very early point in our resume sequence, where the power well
15029 * structures are not yet restored. Since this function is at a very
15030 * paranoid "someone might have enabled VGA while we were not looking"
15031 * level, just check if the power well is enabled instead of trying to
15032 * follow the "don't touch the power well if we don't need it" policy
15033 * the rest of the driver uses. */
15034 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15035 return;
15036
15037 i915_redisable_vga_power_on(dev);
15038 }
15039
15040 static bool primary_get_hw_state(struct intel_crtc *crtc)
15041 {
15042 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15043
15044 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15045 }
15046
15047 static void readout_plane_state(struct intel_crtc *crtc,
15048 struct intel_crtc_state *crtc_state)
15049 {
15050 struct intel_plane *p;
15051 struct intel_plane_state *plane_state;
15052 bool active = crtc_state->base.active;
15053
15054 for_each_intel_plane(crtc->base.dev, p) {
15055 if (crtc->pipe != p->pipe)
15056 continue;
15057
15058 plane_state = to_intel_plane_state(p->base.state);
15059
15060 if (p->base.type == DRM_PLANE_TYPE_PRIMARY)
15061 plane_state->visible = primary_get_hw_state(crtc);
15062 else {
15063 if (active)
15064 p->disable_plane(&p->base, &crtc->base);
15065
15066 plane_state->visible = false;
15067 }
15068 }
15069 }
15070
15071 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15072 {
15073 struct drm_i915_private *dev_priv = dev->dev_private;
15074 enum pipe pipe;
15075 struct intel_crtc *crtc;
15076 struct intel_encoder *encoder;
15077 struct intel_connector *connector;
15078 int i;
15079
15080 for_each_intel_crtc(dev, crtc) {
15081 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15082 memset(crtc->config, 0, sizeof(*crtc->config));
15083 crtc->config->base.crtc = &crtc->base;
15084
15085 crtc->active = dev_priv->display.get_pipe_config(crtc,
15086 crtc->config);
15087
15088 crtc->base.state->active = crtc->active;
15089 crtc->base.enabled = crtc->active;
15090
15091 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15092 if (crtc->base.state->active) {
15093 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15094 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15095 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15096
15097 /*
15098 * The initial mode needs to be set in order to keep
15099 * the atomic core happy. It wants a valid mode if the
15100 * crtc's enabled, so we do the above call.
15101 *
15102 * At this point some state updated by the connectors
15103 * in their ->detect() callback has not run yet, so
15104 * no recalculation can be done yet.
15105 *
15106 * Even if we could do a recalculation and modeset
15107 * right now it would cause a double modeset if
15108 * fbdev or userspace chooses a different initial mode.
15109 *
15110 * If that happens, someone indicated they wanted a
15111 * mode change, which means it's safe to do a full
15112 * recalculation.
15113 */
15114 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15115 }
15116
15117 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15118 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
15119
15120 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15121 crtc->base.base.id,
15122 crtc->active ? "enabled" : "disabled");
15123 }
15124
15125 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15126 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15127
15128 pll->on = pll->get_hw_state(dev_priv, pll,
15129 &pll->config.hw_state);
15130 pll->active = 0;
15131 pll->config.crtc_mask = 0;
15132 for_each_intel_crtc(dev, crtc) {
15133 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15134 pll->active++;
15135 pll->config.crtc_mask |= 1 << crtc->pipe;
15136 }
15137 }
15138
15139 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15140 pll->name, pll->config.crtc_mask, pll->on);
15141
15142 if (pll->config.crtc_mask)
15143 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15144 }
15145
15146 for_each_intel_encoder(dev, encoder) {
15147 pipe = 0;
15148
15149 if (encoder->get_hw_state(encoder, &pipe)) {
15150 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15151 encoder->base.crtc = &crtc->base;
15152 encoder->get_config(encoder, crtc->config);
15153 } else {
15154 encoder->base.crtc = NULL;
15155 }
15156
15157 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15158 encoder->base.base.id,
15159 encoder->base.name,
15160 encoder->base.crtc ? "enabled" : "disabled",
15161 pipe_name(pipe));
15162 }
15163
15164 for_each_intel_connector(dev, connector) {
15165 if (connector->get_hw_state(connector)) {
15166 connector->base.dpms = DRM_MODE_DPMS_ON;
15167 connector->base.encoder = &connector->encoder->base;
15168 } else {
15169 connector->base.dpms = DRM_MODE_DPMS_OFF;
15170 connector->base.encoder = NULL;
15171 }
15172 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15173 connector->base.base.id,
15174 connector->base.name,
15175 connector->base.encoder ? "enabled" : "disabled");
15176 }
15177 }
15178
15179 /* Scan out the current hw modeset state,
15180 * and sanitizes it to the current state
15181 */
15182 static void
15183 intel_modeset_setup_hw_state(struct drm_device *dev)
15184 {
15185 struct drm_i915_private *dev_priv = dev->dev_private;
15186 enum pipe pipe;
15187 struct intel_crtc *crtc;
15188 struct intel_encoder *encoder;
15189 int i;
15190
15191 intel_modeset_readout_hw_state(dev);
15192
15193 /* HW state is read out, now we need to sanitize this mess. */
15194 for_each_intel_encoder(dev, encoder) {
15195 intel_sanitize_encoder(encoder);
15196 }
15197
15198 for_each_pipe(dev_priv, pipe) {
15199 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15200 intel_sanitize_crtc(crtc);
15201 intel_dump_pipe_config(crtc, crtc->config,
15202 "[setup_hw_state]");
15203 }
15204
15205 intel_modeset_update_connector_atomic_state(dev);
15206
15207 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15208 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15209
15210 if (!pll->on || pll->active)
15211 continue;
15212
15213 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15214
15215 pll->disable(dev_priv, pll);
15216 pll->on = false;
15217 }
15218
15219 if (IS_VALLEYVIEW(dev))
15220 vlv_wm_get_hw_state(dev);
15221 else if (IS_GEN9(dev))
15222 skl_wm_get_hw_state(dev);
15223 else if (HAS_PCH_SPLIT(dev))
15224 ilk_wm_get_hw_state(dev);
15225
15226 for_each_intel_crtc(dev, crtc) {
15227 unsigned long put_domains;
15228
15229 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15230 if (WARN_ON(put_domains))
15231 modeset_put_power_domains(dev_priv, put_domains);
15232 }
15233 intel_display_set_init_power(dev_priv, false);
15234 }
15235
15236 void intel_display_resume(struct drm_device *dev)
15237 {
15238 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15239 struct intel_connector *conn;
15240 struct intel_plane *plane;
15241 struct drm_crtc *crtc;
15242 int ret;
15243
15244 if (!state)
15245 return;
15246
15247 state->acquire_ctx = dev->mode_config.acquire_ctx;
15248
15249 /* preserve complete old state, including dpll */
15250 intel_atomic_get_shared_dpll_state(state);
15251
15252 for_each_crtc(dev, crtc) {
15253 struct drm_crtc_state *crtc_state =
15254 drm_atomic_get_crtc_state(state, crtc);
15255
15256 ret = PTR_ERR_OR_ZERO(crtc_state);
15257 if (ret)
15258 goto err;
15259
15260 /* force a restore */
15261 crtc_state->mode_changed = true;
15262 }
15263
15264 for_each_intel_plane(dev, plane) {
15265 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15266 if (ret)
15267 goto err;
15268 }
15269
15270 for_each_intel_connector(dev, conn) {
15271 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15272 if (ret)
15273 goto err;
15274 }
15275
15276 intel_modeset_setup_hw_state(dev);
15277
15278 i915_redisable_vga(dev);
15279 ret = drm_atomic_commit(state);
15280 if (!ret)
15281 return;
15282
15283 err:
15284 DRM_ERROR("Restoring old state failed with %i\n", ret);
15285 drm_atomic_state_free(state);
15286 }
15287
15288 void intel_modeset_gem_init(struct drm_device *dev)
15289 {
15290 struct drm_i915_private *dev_priv = dev->dev_private;
15291 struct drm_crtc *c;
15292 struct drm_i915_gem_object *obj;
15293 int ret;
15294
15295 mutex_lock(&dev->struct_mutex);
15296 intel_init_gt_powersave(dev);
15297 mutex_unlock(&dev->struct_mutex);
15298
15299 /*
15300 * There may be no VBT; and if the BIOS enabled SSC we can
15301 * just keep using it to avoid unnecessary flicker. Whereas if the
15302 * BIOS isn't using it, don't assume it will work even if the VBT
15303 * indicates as much.
15304 */
15305 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15306 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15307 DREF_SSC1_ENABLE);
15308
15309 intel_modeset_init_hw(dev);
15310
15311 intel_setup_overlay(dev);
15312
15313 /*
15314 * Make sure any fbs we allocated at startup are properly
15315 * pinned & fenced. When we do the allocation it's too early
15316 * for this.
15317 */
15318 for_each_crtc(dev, c) {
15319 obj = intel_fb_obj(c->primary->fb);
15320 if (obj == NULL)
15321 continue;
15322
15323 mutex_lock(&dev->struct_mutex);
15324 ret = intel_pin_and_fence_fb_obj(c->primary,
15325 c->primary->fb,
15326 c->primary->state,
15327 NULL, NULL);
15328 mutex_unlock(&dev->struct_mutex);
15329 if (ret) {
15330 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15331 to_intel_crtc(c)->pipe);
15332 drm_framebuffer_unreference(c->primary->fb);
15333 c->primary->fb = NULL;
15334 c->primary->crtc = c->primary->state->crtc = NULL;
15335 update_state_fb(c->primary);
15336 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15337 }
15338 }
15339
15340 intel_backlight_register(dev);
15341 }
15342
15343 void intel_connector_unregister(struct intel_connector *intel_connector)
15344 {
15345 struct drm_connector *connector = &intel_connector->base;
15346
15347 intel_panel_destroy_backlight(connector);
15348 drm_connector_unregister(connector);
15349 }
15350
15351 void intel_modeset_cleanup(struct drm_device *dev)
15352 {
15353 struct drm_i915_private *dev_priv = dev->dev_private;
15354 struct drm_connector *connector;
15355
15356 intel_disable_gt_powersave(dev);
15357
15358 intel_backlight_unregister(dev);
15359
15360 /*
15361 * Interrupts and polling as the first thing to avoid creating havoc.
15362 * Too much stuff here (turning of connectors, ...) would
15363 * experience fancy races otherwise.
15364 */
15365 intel_irq_uninstall(dev_priv);
15366
15367 /*
15368 * Due to the hpd irq storm handling the hotplug work can re-arm the
15369 * poll handlers. Hence disable polling after hpd handling is shut down.
15370 */
15371 drm_kms_helper_poll_fini(dev);
15372
15373 intel_unregister_dsm_handler();
15374
15375 intel_fbc_disable(dev_priv);
15376
15377 /* flush any delayed tasks or pending work */
15378 flush_scheduled_work();
15379
15380 /* destroy the backlight and sysfs files before encoders/connectors */
15381 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15382 struct intel_connector *intel_connector;
15383
15384 intel_connector = to_intel_connector(connector);
15385 intel_connector->unregister(intel_connector);
15386 }
15387
15388 drm_mode_config_cleanup(dev);
15389
15390 intel_cleanup_overlay(dev);
15391
15392 mutex_lock(&dev->struct_mutex);
15393 intel_cleanup_gt_powersave(dev);
15394 mutex_unlock(&dev->struct_mutex);
15395 }
15396
15397 /*
15398 * Return which encoder is currently attached for connector.
15399 */
15400 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15401 {
15402 return &intel_attached_encoder(connector)->base;
15403 }
15404
15405 void intel_connector_attach_encoder(struct intel_connector *connector,
15406 struct intel_encoder *encoder)
15407 {
15408 connector->encoder = encoder;
15409 drm_mode_connector_attach_encoder(&connector->base,
15410 &encoder->base);
15411 }
15412
15413 /*
15414 * set vga decode state - true == enable VGA decode
15415 */
15416 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15417 {
15418 struct drm_i915_private *dev_priv = dev->dev_private;
15419 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15420 u16 gmch_ctrl;
15421
15422 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15423 DRM_ERROR("failed to read control word\n");
15424 return -EIO;
15425 }
15426
15427 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15428 return 0;
15429
15430 if (state)
15431 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15432 else
15433 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15434
15435 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15436 DRM_ERROR("failed to write control word\n");
15437 return -EIO;
15438 }
15439
15440 return 0;
15441 }
15442
15443 struct intel_display_error_state {
15444
15445 u32 power_well_driver;
15446
15447 int num_transcoders;
15448
15449 struct intel_cursor_error_state {
15450 u32 control;
15451 u32 position;
15452 u32 base;
15453 u32 size;
15454 } cursor[I915_MAX_PIPES];
15455
15456 struct intel_pipe_error_state {
15457 bool power_domain_on;
15458 u32 source;
15459 u32 stat;
15460 } pipe[I915_MAX_PIPES];
15461
15462 struct intel_plane_error_state {
15463 u32 control;
15464 u32 stride;
15465 u32 size;
15466 u32 pos;
15467 u32 addr;
15468 u32 surface;
15469 u32 tile_offset;
15470 } plane[I915_MAX_PIPES];
15471
15472 struct intel_transcoder_error_state {
15473 bool power_domain_on;
15474 enum transcoder cpu_transcoder;
15475
15476 u32 conf;
15477
15478 u32 htotal;
15479 u32 hblank;
15480 u32 hsync;
15481 u32 vtotal;
15482 u32 vblank;
15483 u32 vsync;
15484 } transcoder[4];
15485 };
15486
15487 struct intel_display_error_state *
15488 intel_display_capture_error_state(struct drm_device *dev)
15489 {
15490 struct drm_i915_private *dev_priv = dev->dev_private;
15491 struct intel_display_error_state *error;
15492 int transcoders[] = {
15493 TRANSCODER_A,
15494 TRANSCODER_B,
15495 TRANSCODER_C,
15496 TRANSCODER_EDP,
15497 };
15498 int i;
15499
15500 if (INTEL_INFO(dev)->num_pipes == 0)
15501 return NULL;
15502
15503 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15504 if (error == NULL)
15505 return NULL;
15506
15507 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15508 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15509
15510 for_each_pipe(dev_priv, i) {
15511 error->pipe[i].power_domain_on =
15512 __intel_display_power_is_enabled(dev_priv,
15513 POWER_DOMAIN_PIPE(i));
15514 if (!error->pipe[i].power_domain_on)
15515 continue;
15516
15517 error->cursor[i].control = I915_READ(CURCNTR(i));
15518 error->cursor[i].position = I915_READ(CURPOS(i));
15519 error->cursor[i].base = I915_READ(CURBASE(i));
15520
15521 error->plane[i].control = I915_READ(DSPCNTR(i));
15522 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15523 if (INTEL_INFO(dev)->gen <= 3) {
15524 error->plane[i].size = I915_READ(DSPSIZE(i));
15525 error->plane[i].pos = I915_READ(DSPPOS(i));
15526 }
15527 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15528 error->plane[i].addr = I915_READ(DSPADDR(i));
15529 if (INTEL_INFO(dev)->gen >= 4) {
15530 error->plane[i].surface = I915_READ(DSPSURF(i));
15531 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15532 }
15533
15534 error->pipe[i].source = I915_READ(PIPESRC(i));
15535
15536 if (HAS_GMCH_DISPLAY(dev))
15537 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15538 }
15539
15540 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15541 if (HAS_DDI(dev_priv->dev))
15542 error->num_transcoders++; /* Account for eDP. */
15543
15544 for (i = 0; i < error->num_transcoders; i++) {
15545 enum transcoder cpu_transcoder = transcoders[i];
15546
15547 error->transcoder[i].power_domain_on =
15548 __intel_display_power_is_enabled(dev_priv,
15549 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15550 if (!error->transcoder[i].power_domain_on)
15551 continue;
15552
15553 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15554
15555 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15556 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15557 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15558 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15559 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15560 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15561 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15562 }
15563
15564 return error;
15565 }
15566
15567 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15568
15569 void
15570 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15571 struct drm_device *dev,
15572 struct intel_display_error_state *error)
15573 {
15574 struct drm_i915_private *dev_priv = dev->dev_private;
15575 int i;
15576
15577 if (!error)
15578 return;
15579
15580 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15581 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15582 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15583 error->power_well_driver);
15584 for_each_pipe(dev_priv, i) {
15585 err_printf(m, "Pipe [%d]:\n", i);
15586 err_printf(m, " Power: %s\n",
15587 error->pipe[i].power_domain_on ? "on" : "off");
15588 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15589 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15590
15591 err_printf(m, "Plane [%d]:\n", i);
15592 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15593 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15594 if (INTEL_INFO(dev)->gen <= 3) {
15595 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15596 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15597 }
15598 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15599 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15600 if (INTEL_INFO(dev)->gen >= 4) {
15601 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15602 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15603 }
15604
15605 err_printf(m, "Cursor [%d]:\n", i);
15606 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15607 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15608 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15609 }
15610
15611 for (i = 0; i < error->num_transcoders; i++) {
15612 err_printf(m, "CPU transcoder: %c\n",
15613 transcoder_name(error->transcoder[i].cpu_transcoder));
15614 err_printf(m, " Power: %s\n",
15615 error->transcoder[i].power_domain_on ? "on" : "off");
15616 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15617 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15618 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15619 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15620 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15621 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15622 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15623 }
15624 }
15625
15626 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15627 {
15628 struct intel_crtc *crtc;
15629
15630 for_each_intel_crtc(dev, crtc) {
15631 struct intel_unpin_work *work;
15632
15633 spin_lock_irq(&dev->event_lock);
15634
15635 work = crtc->unpin_work;
15636
15637 if (work && work->event &&
15638 work->event->base.file_priv == file) {
15639 kfree(work->event);
15640 work->event = NULL;
15641 }
15642
15643 spin_unlock_irq(&dev->event_lock);
15644 }
15645 }
Linux kernel - Deliverables
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