2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
34 #include "intel_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
40 #include "drm_crtc_helper.h"
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
44 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
);
45 static void intel_update_watermarks(struct drm_device
*dev
);
46 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
47 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t
;
73 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
75 bool (* find_pll
)(const intel_limit_t
*, struct drm_crtc
*,
76 int, int, intel_clock_t
*);
79 #define I8XX_DOT_MIN 25000
80 #define I8XX_DOT_MAX 350000
81 #define I8XX_VCO_MIN 930000
82 #define I8XX_VCO_MAX 1400000
86 #define I8XX_M_MAX 140
87 #define I8XX_M1_MIN 18
88 #define I8XX_M1_MAX 26
90 #define I8XX_M2_MAX 16
92 #define I8XX_P_MAX 128
94 #define I8XX_P1_MAX 33
95 #define I8XX_P1_LVDS_MIN 1
96 #define I8XX_P1_LVDS_MAX 6
97 #define I8XX_P2_SLOW 4
98 #define I8XX_P2_FAST 2
99 #define I8XX_P2_LVDS_SLOW 14
100 #define I8XX_P2_LVDS_FAST 7
101 #define I8XX_P2_SLOW_LIMIT 165000
103 #define I9XX_DOT_MIN 20000
104 #define I9XX_DOT_MAX 400000
105 #define I9XX_VCO_MIN 1400000
106 #define I9XX_VCO_MAX 2800000
107 #define PINEVIEW_VCO_MIN 1700000
108 #define PINEVIEW_VCO_MAX 3500000
111 /* Pineview's Ncounter is a ring counter */
112 #define PINEVIEW_N_MIN 3
113 #define PINEVIEW_N_MAX 6
114 #define I9XX_M_MIN 70
115 #define I9XX_M_MAX 120
116 #define PINEVIEW_M_MIN 2
117 #define PINEVIEW_M_MAX 256
118 #define I9XX_M1_MIN 10
119 #define I9XX_M1_MAX 22
120 #define I9XX_M2_MIN 5
121 #define I9XX_M2_MAX 9
122 /* Pineview M1 is reserved, and must be 0 */
123 #define PINEVIEW_M1_MIN 0
124 #define PINEVIEW_M1_MAX 0
125 #define PINEVIEW_M2_MIN 0
126 #define PINEVIEW_M2_MAX 254
127 #define I9XX_P_SDVO_DAC_MIN 5
128 #define I9XX_P_SDVO_DAC_MAX 80
129 #define I9XX_P_LVDS_MIN 7
130 #define I9XX_P_LVDS_MAX 98
131 #define PINEVIEW_P_LVDS_MIN 7
132 #define PINEVIEW_P_LVDS_MAX 112
133 #define I9XX_P1_MIN 1
134 #define I9XX_P1_MAX 8
135 #define I9XX_P2_SDVO_DAC_SLOW 10
136 #define I9XX_P2_SDVO_DAC_FAST 5
137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138 #define I9XX_P2_LVDS_SLOW 14
139 #define I9XX_P2_LVDS_FAST 7
140 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
142 /*The parameter is for SDVO on G4x platform*/
143 #define G4X_DOT_SDVO_MIN 25000
144 #define G4X_DOT_SDVO_MAX 270000
145 #define G4X_VCO_MIN 1750000
146 #define G4X_VCO_MAX 3500000
147 #define G4X_N_SDVO_MIN 1
148 #define G4X_N_SDVO_MAX 4
149 #define G4X_M_SDVO_MIN 104
150 #define G4X_M_SDVO_MAX 138
151 #define G4X_M1_SDVO_MIN 17
152 #define G4X_M1_SDVO_MAX 23
153 #define G4X_M2_SDVO_MIN 5
154 #define G4X_M2_SDVO_MAX 11
155 #define G4X_P_SDVO_MIN 10
156 #define G4X_P_SDVO_MAX 30
157 #define G4X_P1_SDVO_MIN 1
158 #define G4X_P1_SDVO_MAX 3
159 #define G4X_P2_SDVO_SLOW 10
160 #define G4X_P2_SDVO_FAST 10
161 #define G4X_P2_SDVO_LIMIT 270000
163 /*The parameter is for HDMI_DAC on G4x platform*/
164 #define G4X_DOT_HDMI_DAC_MIN 22000
165 #define G4X_DOT_HDMI_DAC_MAX 400000
166 #define G4X_N_HDMI_DAC_MIN 1
167 #define G4X_N_HDMI_DAC_MAX 4
168 #define G4X_M_HDMI_DAC_MIN 104
169 #define G4X_M_HDMI_DAC_MAX 138
170 #define G4X_M1_HDMI_DAC_MIN 16
171 #define G4X_M1_HDMI_DAC_MAX 23
172 #define G4X_M2_HDMI_DAC_MIN 5
173 #define G4X_M2_HDMI_DAC_MAX 11
174 #define G4X_P_HDMI_DAC_MIN 5
175 #define G4X_P_HDMI_DAC_MAX 80
176 #define G4X_P1_HDMI_DAC_MIN 1
177 #define G4X_P1_HDMI_DAC_MAX 8
178 #define G4X_P2_HDMI_DAC_SLOW 10
179 #define G4X_P2_HDMI_DAC_FAST 5
180 #define G4X_P2_HDMI_DAC_LIMIT 165000
182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
220 /*The parameter is for DISPLAY PORT on G4x platform*/
221 #define G4X_DOT_DISPLAY_PORT_MIN 161670
222 #define G4X_DOT_DISPLAY_PORT_MAX 227000
223 #define G4X_N_DISPLAY_PORT_MIN 1
224 #define G4X_N_DISPLAY_PORT_MAX 2
225 #define G4X_M_DISPLAY_PORT_MIN 97
226 #define G4X_M_DISPLAY_PORT_MAX 108
227 #define G4X_M1_DISPLAY_PORT_MIN 0x10
228 #define G4X_M1_DISPLAY_PORT_MAX 0x12
229 #define G4X_M2_DISPLAY_PORT_MIN 0x05
230 #define G4X_M2_DISPLAY_PORT_MAX 0x06
231 #define G4X_P_DISPLAY_PORT_MIN 10
232 #define G4X_P_DISPLAY_PORT_MAX 20
233 #define G4X_P1_DISPLAY_PORT_MIN 1
234 #define G4X_P1_DISPLAY_PORT_MAX 2
235 #define G4X_P2_DISPLAY_PORT_SLOW 10
236 #define G4X_P2_DISPLAY_PORT_FAST 10
237 #define G4X_P2_DISPLAY_PORT_LIMIT 0
239 /* Ironlake / Sandybridge */
240 /* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
243 #define IRONLAKE_DOT_MIN 25000
244 #define IRONLAKE_DOT_MAX 350000
245 #define IRONLAKE_VCO_MIN 1760000
246 #define IRONLAKE_VCO_MAX 3510000
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
253 /* We have parameter ranges for different type of outputs. */
255 /* DAC & HDMI Refclk 120Mhz */
256 #define IRONLAKE_DAC_N_MIN 1
257 #define IRONLAKE_DAC_N_MAX 5
258 #define IRONLAKE_DAC_M_MIN 79
259 #define IRONLAKE_DAC_M_MAX 127
260 #define IRONLAKE_DAC_P_MIN 5
261 #define IRONLAKE_DAC_P_MAX 80
262 #define IRONLAKE_DAC_P1_MIN 1
263 #define IRONLAKE_DAC_P1_MAX 8
264 #define IRONLAKE_DAC_P2_SLOW 10
265 #define IRONLAKE_DAC_P2_FAST 5
267 /* LVDS single-channel 120Mhz refclk */
268 #define IRONLAKE_LVDS_S_N_MIN 1
269 #define IRONLAKE_LVDS_S_N_MAX 3
270 #define IRONLAKE_LVDS_S_M_MIN 79
271 #define IRONLAKE_LVDS_S_M_MAX 118
272 #define IRONLAKE_LVDS_S_P_MIN 28
273 #define IRONLAKE_LVDS_S_P_MAX 112
274 #define IRONLAKE_LVDS_S_P1_MIN 2
275 #define IRONLAKE_LVDS_S_P1_MAX 8
276 #define IRONLAKE_LVDS_S_P2_SLOW 14
277 #define IRONLAKE_LVDS_S_P2_FAST 14
279 /* LVDS dual-channel 120Mhz refclk */
280 #define IRONLAKE_LVDS_D_N_MIN 1
281 #define IRONLAKE_LVDS_D_N_MAX 3
282 #define IRONLAKE_LVDS_D_M_MIN 79
283 #define IRONLAKE_LVDS_D_M_MAX 127
284 #define IRONLAKE_LVDS_D_P_MIN 14
285 #define IRONLAKE_LVDS_D_P_MAX 56
286 #define IRONLAKE_LVDS_D_P1_MIN 2
287 #define IRONLAKE_LVDS_D_P1_MAX 8
288 #define IRONLAKE_LVDS_D_P2_SLOW 7
289 #define IRONLAKE_LVDS_D_P2_FAST 7
291 /* LVDS single-channel 100Mhz refclk */
292 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
293 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
294 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
295 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
296 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
297 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
298 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
303 /* LVDS dual-channel 100Mhz refclk */
304 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
305 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
306 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
307 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
308 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
309 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
310 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
316 #define IRONLAKE_DP_N_MIN 1
317 #define IRONLAKE_DP_N_MAX 2
318 #define IRONLAKE_DP_M_MIN 81
319 #define IRONLAKE_DP_M_MAX 90
320 #define IRONLAKE_DP_P_MIN 10
321 #define IRONLAKE_DP_P_MAX 20
322 #define IRONLAKE_DP_P2_FAST 10
323 #define IRONLAKE_DP_P2_SLOW 10
324 #define IRONLAKE_DP_P2_LIMIT 0
325 #define IRONLAKE_DP_P1_MIN 1
326 #define IRONLAKE_DP_P1_MAX 2
329 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
332 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
333 int target
, int refclk
, intel_clock_t
*best_clock
);
335 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
336 int target
, int refclk
, intel_clock_t
*best_clock
);
339 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
340 int target
, int refclk
, intel_clock_t
*best_clock
);
342 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
343 int target
, int refclk
, intel_clock_t
*best_clock
);
345 static inline u32
/* units of 100MHz */
346 intel_fdi_link_freq(struct drm_device
*dev
)
349 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
350 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
355 static const intel_limit_t intel_limits_i8xx_dvo
= {
356 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
357 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
358 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
359 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
360 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
361 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
362 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
363 .p1
= { .min
= I8XX_P1_MIN
, .max
= I8XX_P1_MAX
},
364 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
365 .p2_slow
= I8XX_P2_SLOW
, .p2_fast
= I8XX_P2_FAST
},
366 .find_pll
= intel_find_best_PLL
,
369 static const intel_limit_t intel_limits_i8xx_lvds
= {
370 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
371 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
372 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
373 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
374 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
375 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
376 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
377 .p1
= { .min
= I8XX_P1_LVDS_MIN
, .max
= I8XX_P1_LVDS_MAX
},
378 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
379 .p2_slow
= I8XX_P2_LVDS_SLOW
, .p2_fast
= I8XX_P2_LVDS_FAST
},
380 .find_pll
= intel_find_best_PLL
,
383 static const intel_limit_t intel_limits_i9xx_sdvo
= {
384 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
385 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
386 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
387 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
388 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
389 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
390 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
391 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
392 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
393 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
394 .find_pll
= intel_find_best_PLL
,
397 static const intel_limit_t intel_limits_i9xx_lvds
= {
398 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
399 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
400 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
401 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
402 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
403 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
404 .p
= { .min
= I9XX_P_LVDS_MIN
, .max
= I9XX_P_LVDS_MAX
},
405 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
406 /* The single-channel range is 25-112Mhz, and dual-channel
407 * is 80-224Mhz. Prefer single channel as much as possible.
409 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
410 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_FAST
},
411 .find_pll
= intel_find_best_PLL
,
414 /* below parameter and function is for G4X Chipset Family*/
415 static const intel_limit_t intel_limits_g4x_sdvo
= {
416 .dot
= { .min
= G4X_DOT_SDVO_MIN
, .max
= G4X_DOT_SDVO_MAX
},
417 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
418 .n
= { .min
= G4X_N_SDVO_MIN
, .max
= G4X_N_SDVO_MAX
},
419 .m
= { .min
= G4X_M_SDVO_MIN
, .max
= G4X_M_SDVO_MAX
},
420 .m1
= { .min
= G4X_M1_SDVO_MIN
, .max
= G4X_M1_SDVO_MAX
},
421 .m2
= { .min
= G4X_M2_SDVO_MIN
, .max
= G4X_M2_SDVO_MAX
},
422 .p
= { .min
= G4X_P_SDVO_MIN
, .max
= G4X_P_SDVO_MAX
},
423 .p1
= { .min
= G4X_P1_SDVO_MIN
, .max
= G4X_P1_SDVO_MAX
},
424 .p2
= { .dot_limit
= G4X_P2_SDVO_LIMIT
,
425 .p2_slow
= G4X_P2_SDVO_SLOW
,
426 .p2_fast
= G4X_P2_SDVO_FAST
428 .find_pll
= intel_g4x_find_best_PLL
,
431 static const intel_limit_t intel_limits_g4x_hdmi
= {
432 .dot
= { .min
= G4X_DOT_HDMI_DAC_MIN
, .max
= G4X_DOT_HDMI_DAC_MAX
},
433 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
434 .n
= { .min
= G4X_N_HDMI_DAC_MIN
, .max
= G4X_N_HDMI_DAC_MAX
},
435 .m
= { .min
= G4X_M_HDMI_DAC_MIN
, .max
= G4X_M_HDMI_DAC_MAX
},
436 .m1
= { .min
= G4X_M1_HDMI_DAC_MIN
, .max
= G4X_M1_HDMI_DAC_MAX
},
437 .m2
= { .min
= G4X_M2_HDMI_DAC_MIN
, .max
= G4X_M2_HDMI_DAC_MAX
},
438 .p
= { .min
= G4X_P_HDMI_DAC_MIN
, .max
= G4X_P_HDMI_DAC_MAX
},
439 .p1
= { .min
= G4X_P1_HDMI_DAC_MIN
, .max
= G4X_P1_HDMI_DAC_MAX
},
440 .p2
= { .dot_limit
= G4X_P2_HDMI_DAC_LIMIT
,
441 .p2_slow
= G4X_P2_HDMI_DAC_SLOW
,
442 .p2_fast
= G4X_P2_HDMI_DAC_FAST
444 .find_pll
= intel_g4x_find_best_PLL
,
447 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
448 .dot
= { .min
= G4X_DOT_SINGLE_CHANNEL_LVDS_MIN
,
449 .max
= G4X_DOT_SINGLE_CHANNEL_LVDS_MAX
},
450 .vco
= { .min
= G4X_VCO_MIN
,
451 .max
= G4X_VCO_MAX
},
452 .n
= { .min
= G4X_N_SINGLE_CHANNEL_LVDS_MIN
,
453 .max
= G4X_N_SINGLE_CHANNEL_LVDS_MAX
},
454 .m
= { .min
= G4X_M_SINGLE_CHANNEL_LVDS_MIN
,
455 .max
= G4X_M_SINGLE_CHANNEL_LVDS_MAX
},
456 .m1
= { .min
= G4X_M1_SINGLE_CHANNEL_LVDS_MIN
,
457 .max
= G4X_M1_SINGLE_CHANNEL_LVDS_MAX
},
458 .m2
= { .min
= G4X_M2_SINGLE_CHANNEL_LVDS_MIN
,
459 .max
= G4X_M2_SINGLE_CHANNEL_LVDS_MAX
},
460 .p
= { .min
= G4X_P_SINGLE_CHANNEL_LVDS_MIN
,
461 .max
= G4X_P_SINGLE_CHANNEL_LVDS_MAX
},
462 .p1
= { .min
= G4X_P1_SINGLE_CHANNEL_LVDS_MIN
,
463 .max
= G4X_P1_SINGLE_CHANNEL_LVDS_MAX
},
464 .p2
= { .dot_limit
= G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT
,
465 .p2_slow
= G4X_P2_SINGLE_CHANNEL_LVDS_SLOW
,
466 .p2_fast
= G4X_P2_SINGLE_CHANNEL_LVDS_FAST
468 .find_pll
= intel_g4x_find_best_PLL
,
471 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
472 .dot
= { .min
= G4X_DOT_DUAL_CHANNEL_LVDS_MIN
,
473 .max
= G4X_DOT_DUAL_CHANNEL_LVDS_MAX
},
474 .vco
= { .min
= G4X_VCO_MIN
,
475 .max
= G4X_VCO_MAX
},
476 .n
= { .min
= G4X_N_DUAL_CHANNEL_LVDS_MIN
,
477 .max
= G4X_N_DUAL_CHANNEL_LVDS_MAX
},
478 .m
= { .min
= G4X_M_DUAL_CHANNEL_LVDS_MIN
,
479 .max
= G4X_M_DUAL_CHANNEL_LVDS_MAX
},
480 .m1
= { .min
= G4X_M1_DUAL_CHANNEL_LVDS_MIN
,
481 .max
= G4X_M1_DUAL_CHANNEL_LVDS_MAX
},
482 .m2
= { .min
= G4X_M2_DUAL_CHANNEL_LVDS_MIN
,
483 .max
= G4X_M2_DUAL_CHANNEL_LVDS_MAX
},
484 .p
= { .min
= G4X_P_DUAL_CHANNEL_LVDS_MIN
,
485 .max
= G4X_P_DUAL_CHANNEL_LVDS_MAX
},
486 .p1
= { .min
= G4X_P1_DUAL_CHANNEL_LVDS_MIN
,
487 .max
= G4X_P1_DUAL_CHANNEL_LVDS_MAX
},
488 .p2
= { .dot_limit
= G4X_P2_DUAL_CHANNEL_LVDS_LIMIT
,
489 .p2_slow
= G4X_P2_DUAL_CHANNEL_LVDS_SLOW
,
490 .p2_fast
= G4X_P2_DUAL_CHANNEL_LVDS_FAST
492 .find_pll
= intel_g4x_find_best_PLL
,
495 static const intel_limit_t intel_limits_g4x_display_port
= {
496 .dot
= { .min
= G4X_DOT_DISPLAY_PORT_MIN
,
497 .max
= G4X_DOT_DISPLAY_PORT_MAX
},
498 .vco
= { .min
= G4X_VCO_MIN
,
500 .n
= { .min
= G4X_N_DISPLAY_PORT_MIN
,
501 .max
= G4X_N_DISPLAY_PORT_MAX
},
502 .m
= { .min
= G4X_M_DISPLAY_PORT_MIN
,
503 .max
= G4X_M_DISPLAY_PORT_MAX
},
504 .m1
= { .min
= G4X_M1_DISPLAY_PORT_MIN
,
505 .max
= G4X_M1_DISPLAY_PORT_MAX
},
506 .m2
= { .min
= G4X_M2_DISPLAY_PORT_MIN
,
507 .max
= G4X_M2_DISPLAY_PORT_MAX
},
508 .p
= { .min
= G4X_P_DISPLAY_PORT_MIN
,
509 .max
= G4X_P_DISPLAY_PORT_MAX
},
510 .p1
= { .min
= G4X_P1_DISPLAY_PORT_MIN
,
511 .max
= G4X_P1_DISPLAY_PORT_MAX
},
512 .p2
= { .dot_limit
= G4X_P2_DISPLAY_PORT_LIMIT
,
513 .p2_slow
= G4X_P2_DISPLAY_PORT_SLOW
,
514 .p2_fast
= G4X_P2_DISPLAY_PORT_FAST
},
515 .find_pll
= intel_find_pll_g4x_dp
,
518 static const intel_limit_t intel_limits_pineview_sdvo
= {
519 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
520 .vco
= { .min
= PINEVIEW_VCO_MIN
, .max
= PINEVIEW_VCO_MAX
},
521 .n
= { .min
= PINEVIEW_N_MIN
, .max
= PINEVIEW_N_MAX
},
522 .m
= { .min
= PINEVIEW_M_MIN
, .max
= PINEVIEW_M_MAX
},
523 .m1
= { .min
= PINEVIEW_M1_MIN
, .max
= PINEVIEW_M1_MAX
},
524 .m2
= { .min
= PINEVIEW_M2_MIN
, .max
= PINEVIEW_M2_MAX
},
525 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
526 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
527 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
528 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
529 .find_pll
= intel_find_best_PLL
,
532 static const intel_limit_t intel_limits_pineview_lvds
= {
533 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
534 .vco
= { .min
= PINEVIEW_VCO_MIN
, .max
= PINEVIEW_VCO_MAX
},
535 .n
= { .min
= PINEVIEW_N_MIN
, .max
= PINEVIEW_N_MAX
},
536 .m
= { .min
= PINEVIEW_M_MIN
, .max
= PINEVIEW_M_MAX
},
537 .m1
= { .min
= PINEVIEW_M1_MIN
, .max
= PINEVIEW_M1_MAX
},
538 .m2
= { .min
= PINEVIEW_M2_MIN
, .max
= PINEVIEW_M2_MAX
},
539 .p
= { .min
= PINEVIEW_P_LVDS_MIN
, .max
= PINEVIEW_P_LVDS_MAX
},
540 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
541 /* Pineview only supports single-channel mode. */
542 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
543 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_SLOW
},
544 .find_pll
= intel_find_best_PLL
,
547 static const intel_limit_t intel_limits_ironlake_dac
= {
548 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
549 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
550 .n
= { .min
= IRONLAKE_DAC_N_MIN
, .max
= IRONLAKE_DAC_N_MAX
},
551 .m
= { .min
= IRONLAKE_DAC_M_MIN
, .max
= IRONLAKE_DAC_M_MAX
},
552 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
553 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
554 .p
= { .min
= IRONLAKE_DAC_P_MIN
, .max
= IRONLAKE_DAC_P_MAX
},
555 .p1
= { .min
= IRONLAKE_DAC_P1_MIN
, .max
= IRONLAKE_DAC_P1_MAX
},
556 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
557 .p2_slow
= IRONLAKE_DAC_P2_SLOW
,
558 .p2_fast
= IRONLAKE_DAC_P2_FAST
},
559 .find_pll
= intel_g4x_find_best_PLL
,
562 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
563 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
564 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
565 .n
= { .min
= IRONLAKE_LVDS_S_N_MIN
, .max
= IRONLAKE_LVDS_S_N_MAX
},
566 .m
= { .min
= IRONLAKE_LVDS_S_M_MIN
, .max
= IRONLAKE_LVDS_S_M_MAX
},
567 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
568 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
569 .p
= { .min
= IRONLAKE_LVDS_S_P_MIN
, .max
= IRONLAKE_LVDS_S_P_MAX
},
570 .p1
= { .min
= IRONLAKE_LVDS_S_P1_MIN
, .max
= IRONLAKE_LVDS_S_P1_MAX
},
571 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
572 .p2_slow
= IRONLAKE_LVDS_S_P2_SLOW
,
573 .p2_fast
= IRONLAKE_LVDS_S_P2_FAST
},
574 .find_pll
= intel_g4x_find_best_PLL
,
577 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
578 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
579 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
580 .n
= { .min
= IRONLAKE_LVDS_D_N_MIN
, .max
= IRONLAKE_LVDS_D_N_MAX
},
581 .m
= { .min
= IRONLAKE_LVDS_D_M_MIN
, .max
= IRONLAKE_LVDS_D_M_MAX
},
582 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
583 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
584 .p
= { .min
= IRONLAKE_LVDS_D_P_MIN
, .max
= IRONLAKE_LVDS_D_P_MAX
},
585 .p1
= { .min
= IRONLAKE_LVDS_D_P1_MIN
, .max
= IRONLAKE_LVDS_D_P1_MAX
},
586 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
587 .p2_slow
= IRONLAKE_LVDS_D_P2_SLOW
,
588 .p2_fast
= IRONLAKE_LVDS_D_P2_FAST
},
589 .find_pll
= intel_g4x_find_best_PLL
,
592 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
593 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
594 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
595 .n
= { .min
= IRONLAKE_LVDS_S_SSC_N_MIN
, .max
= IRONLAKE_LVDS_S_SSC_N_MAX
},
596 .m
= { .min
= IRONLAKE_LVDS_S_SSC_M_MIN
, .max
= IRONLAKE_LVDS_S_SSC_M_MAX
},
597 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
598 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
599 .p
= { .min
= IRONLAKE_LVDS_S_SSC_P_MIN
, .max
= IRONLAKE_LVDS_S_SSC_P_MAX
},
600 .p1
= { .min
= IRONLAKE_LVDS_S_SSC_P1_MIN
,.max
= IRONLAKE_LVDS_S_SSC_P1_MAX
},
601 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
602 .p2_slow
= IRONLAKE_LVDS_S_SSC_P2_SLOW
,
603 .p2_fast
= IRONLAKE_LVDS_S_SSC_P2_FAST
},
604 .find_pll
= intel_g4x_find_best_PLL
,
607 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
608 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
609 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
610 .n
= { .min
= IRONLAKE_LVDS_D_SSC_N_MIN
, .max
= IRONLAKE_LVDS_D_SSC_N_MAX
},
611 .m
= { .min
= IRONLAKE_LVDS_D_SSC_M_MIN
, .max
= IRONLAKE_LVDS_D_SSC_M_MAX
},
612 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
613 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
614 .p
= { .min
= IRONLAKE_LVDS_D_SSC_P_MIN
, .max
= IRONLAKE_LVDS_D_SSC_P_MAX
},
615 .p1
= { .min
= IRONLAKE_LVDS_D_SSC_P1_MIN
,.max
= IRONLAKE_LVDS_D_SSC_P1_MAX
},
616 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
617 .p2_slow
= IRONLAKE_LVDS_D_SSC_P2_SLOW
,
618 .p2_fast
= IRONLAKE_LVDS_D_SSC_P2_FAST
},
619 .find_pll
= intel_g4x_find_best_PLL
,
622 static const intel_limit_t intel_limits_ironlake_display_port
= {
623 .dot
= { .min
= IRONLAKE_DOT_MIN
,
624 .max
= IRONLAKE_DOT_MAX
},
625 .vco
= { .min
= IRONLAKE_VCO_MIN
,
626 .max
= IRONLAKE_VCO_MAX
},
627 .n
= { .min
= IRONLAKE_DP_N_MIN
,
628 .max
= IRONLAKE_DP_N_MAX
},
629 .m
= { .min
= IRONLAKE_DP_M_MIN
,
630 .max
= IRONLAKE_DP_M_MAX
},
631 .m1
= { .min
= IRONLAKE_M1_MIN
,
632 .max
= IRONLAKE_M1_MAX
},
633 .m2
= { .min
= IRONLAKE_M2_MIN
,
634 .max
= IRONLAKE_M2_MAX
},
635 .p
= { .min
= IRONLAKE_DP_P_MIN
,
636 .max
= IRONLAKE_DP_P_MAX
},
637 .p1
= { .min
= IRONLAKE_DP_P1_MIN
,
638 .max
= IRONLAKE_DP_P1_MAX
},
639 .p2
= { .dot_limit
= IRONLAKE_DP_P2_LIMIT
,
640 .p2_slow
= IRONLAKE_DP_P2_SLOW
,
641 .p2_fast
= IRONLAKE_DP_P2_FAST
},
642 .find_pll
= intel_find_pll_ironlake_dp
,
645 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
648 struct drm_device
*dev
= crtc
->dev
;
649 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
650 const intel_limit_t
*limit
;
652 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
653 if ((I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) ==
654 LVDS_CLKB_POWER_UP
) {
655 /* LVDS dual channel */
656 if (refclk
== 100000)
657 limit
= &intel_limits_ironlake_dual_lvds_100m
;
659 limit
= &intel_limits_ironlake_dual_lvds
;
661 if (refclk
== 100000)
662 limit
= &intel_limits_ironlake_single_lvds_100m
;
664 limit
= &intel_limits_ironlake_single_lvds
;
666 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
668 limit
= &intel_limits_ironlake_display_port
;
670 limit
= &intel_limits_ironlake_dac
;
675 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
677 struct drm_device
*dev
= crtc
->dev
;
678 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
679 const intel_limit_t
*limit
;
681 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
682 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
684 /* LVDS with dual channel */
685 limit
= &intel_limits_g4x_dual_channel_lvds
;
687 /* LVDS with dual channel */
688 limit
= &intel_limits_g4x_single_channel_lvds
;
689 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
690 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
691 limit
= &intel_limits_g4x_hdmi
;
692 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
693 limit
= &intel_limits_g4x_sdvo
;
694 } else if (intel_pipe_has_type (crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
695 limit
= &intel_limits_g4x_display_port
;
696 } else /* The option is for other outputs */
697 limit
= &intel_limits_i9xx_sdvo
;
702 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
704 struct drm_device
*dev
= crtc
->dev
;
705 const intel_limit_t
*limit
;
707 if (HAS_PCH_SPLIT(dev
))
708 limit
= intel_ironlake_limit(crtc
, refclk
);
709 else if (IS_G4X(dev
)) {
710 limit
= intel_g4x_limit(crtc
);
711 } else if (IS_PINEVIEW(dev
)) {
712 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
713 limit
= &intel_limits_pineview_lvds
;
715 limit
= &intel_limits_pineview_sdvo
;
716 } else if (!IS_GEN2(dev
)) {
717 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
718 limit
= &intel_limits_i9xx_lvds
;
720 limit
= &intel_limits_i9xx_sdvo
;
722 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
723 limit
= &intel_limits_i8xx_lvds
;
725 limit
= &intel_limits_i8xx_dvo
;
730 /* m1 is reserved as 0 in Pineview, n is a ring counter */
731 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
733 clock
->m
= clock
->m2
+ 2;
734 clock
->p
= clock
->p1
* clock
->p2
;
735 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
736 clock
->dot
= clock
->vco
/ clock
->p
;
739 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
741 if (IS_PINEVIEW(dev
)) {
742 pineview_clock(refclk
, clock
);
745 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
746 clock
->p
= clock
->p1
* clock
->p2
;
747 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
748 clock
->dot
= clock
->vco
/ clock
->p
;
752 * Returns whether any output on the specified pipe is of the specified type
754 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
756 struct drm_device
*dev
= crtc
->dev
;
757 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
758 struct intel_encoder
*encoder
;
760 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
)
761 if (encoder
->base
.crtc
== crtc
&& encoder
->type
== type
)
767 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
769 * Returns whether the given set of divisors are valid for a given refclk with
770 * the given connectors.
773 static bool intel_PLL_is_valid(struct drm_device
*dev
,
774 const intel_limit_t
*limit
,
775 const intel_clock_t
*clock
)
777 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
778 INTELPllInvalid ("p1 out of range\n");
779 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
780 INTELPllInvalid ("p out of range\n");
781 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
782 INTELPllInvalid ("m2 out of range\n");
783 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
784 INTELPllInvalid ("m1 out of range\n");
785 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
786 INTELPllInvalid ("m1 <= m2\n");
787 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
788 INTELPllInvalid ("m out of range\n");
789 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
790 INTELPllInvalid ("n out of range\n");
791 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
792 INTELPllInvalid ("vco out of range\n");
793 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
794 * connector, etc., rather than just a single range.
796 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
797 INTELPllInvalid ("dot out of range\n");
803 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
804 int target
, int refclk
, intel_clock_t
*best_clock
)
807 struct drm_device
*dev
= crtc
->dev
;
808 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
812 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
813 (I915_READ(LVDS
)) != 0) {
815 * For LVDS, if the panel is on, just rely on its current
816 * settings for dual-channel. We haven't figured out how to
817 * reliably set up different single/dual channel state, if we
820 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
822 clock
.p2
= limit
->p2
.p2_fast
;
824 clock
.p2
= limit
->p2
.p2_slow
;
826 if (target
< limit
->p2
.dot_limit
)
827 clock
.p2
= limit
->p2
.p2_slow
;
829 clock
.p2
= limit
->p2
.p2_fast
;
832 memset (best_clock
, 0, sizeof (*best_clock
));
834 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
836 for (clock
.m2
= limit
->m2
.min
;
837 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
838 /* m1 is always 0 in Pineview */
839 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
841 for (clock
.n
= limit
->n
.min
;
842 clock
.n
<= limit
->n
.max
; clock
.n
++) {
843 for (clock
.p1
= limit
->p1
.min
;
844 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
847 intel_clock(dev
, refclk
, &clock
);
848 if (!intel_PLL_is_valid(dev
, limit
,
852 this_err
= abs(clock
.dot
- target
);
853 if (this_err
< err
) {
862 return (err
!= target
);
866 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
867 int target
, int refclk
, intel_clock_t
*best_clock
)
869 struct drm_device
*dev
= crtc
->dev
;
870 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
874 /* approximately equals target * 0.00585 */
875 int err_most
= (target
>> 8) + (target
>> 9);
878 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
881 if (HAS_PCH_SPLIT(dev
))
885 if ((I915_READ(lvds_reg
) & LVDS_CLKB_POWER_MASK
) ==
887 clock
.p2
= limit
->p2
.p2_fast
;
889 clock
.p2
= limit
->p2
.p2_slow
;
891 if (target
< limit
->p2
.dot_limit
)
892 clock
.p2
= limit
->p2
.p2_slow
;
894 clock
.p2
= limit
->p2
.p2_fast
;
897 memset(best_clock
, 0, sizeof(*best_clock
));
898 max_n
= limit
->n
.max
;
899 /* based on hardware requirement, prefer smaller n to precision */
900 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
901 /* based on hardware requirement, prefere larger m1,m2 */
902 for (clock
.m1
= limit
->m1
.max
;
903 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
904 for (clock
.m2
= limit
->m2
.max
;
905 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
906 for (clock
.p1
= limit
->p1
.max
;
907 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
910 intel_clock(dev
, refclk
, &clock
);
911 if (!intel_PLL_is_valid(dev
, limit
,
915 this_err
= abs(clock
.dot
- target
);
916 if (this_err
< err_most
) {
930 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
931 int target
, int refclk
, intel_clock_t
*best_clock
)
933 struct drm_device
*dev
= crtc
->dev
;
936 if (target
< 200000) {
949 intel_clock(dev
, refclk
, &clock
);
950 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
954 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
956 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
957 int target
, int refclk
, intel_clock_t
*best_clock
)
960 if (target
< 200000) {
973 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
974 clock
.p
= (clock
.p1
* clock
.p2
);
975 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
977 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
982 * intel_wait_for_vblank - wait for vblank on a given pipe
984 * @pipe: pipe to wait for
986 * Wait for vblank to occur on a given pipe. Needed for various bits of
989 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
991 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
992 int pipestat_reg
= (pipe
== 0 ? PIPEASTAT
: PIPEBSTAT
);
994 /* Clear existing vblank status. Note this will clear any other
995 * sticky status fields as well.
997 * This races with i915_driver_irq_handler() with the result
998 * that either function could miss a vblank event. Here it is not
999 * fatal, as we will either wait upon the next vblank interrupt or
1000 * timeout. Generally speaking intel_wait_for_vblank() is only
1001 * called during modeset at which time the GPU should be idle and
1002 * should *not* be performing page flips and thus not waiting on
1004 * Currently, the result of us stealing a vblank from the irq
1005 * handler is that a single frame will be skipped during swapbuffers.
1007 I915_WRITE(pipestat_reg
,
1008 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
1010 /* Wait for vblank interrupt bit to set */
1011 if (wait_for(I915_READ(pipestat_reg
) &
1012 PIPE_VBLANK_INTERRUPT_STATUS
,
1014 DRM_DEBUG_KMS("vblank wait timed out\n");
1018 * intel_wait_for_pipe_off - wait for pipe to turn off
1020 * @pipe: pipe to wait for
1022 * After disabling a pipe, we can't wait for vblank in the usual way,
1023 * spinning on the vblank interrupt status bit, since we won't actually
1024 * see an interrupt when the pipe is disabled.
1026 * On Gen4 and above:
1027 * wait for the pipe register state bit to turn off
1030 * wait for the display line value to settle (it usually
1031 * ends up stopping at the start of the next frame).
1034 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
1036 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1038 if (INTEL_INFO(dev
)->gen
>= 4) {
1039 int reg
= PIPECONF(pipe
);
1041 /* Wait for the Pipe State to go off */
1042 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
1044 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1047 int reg
= PIPEDSL(pipe
);
1048 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
1050 /* Wait for the display line to settle */
1052 last_line
= I915_READ(reg
) & DSL_LINEMASK
;
1054 } while (((I915_READ(reg
) & DSL_LINEMASK
) != last_line
) &&
1055 time_after(timeout
, jiffies
));
1056 if (time_after(jiffies
, timeout
))
1057 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1061 static const char *state_string(bool enabled
)
1063 return enabled
? "on" : "off";
1066 /* Only for pre-ILK configs */
1067 static void assert_pll(struct drm_i915_private
*dev_priv
,
1068 enum pipe pipe
, bool state
)
1075 val
= I915_READ(reg
);
1076 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1077 WARN(cur_state
!= state
,
1078 "PLL state assertion failure (expected %s, current %s)\n",
1079 state_string(state
), state_string(cur_state
));
1081 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1082 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1085 static void assert_pch_pll(struct drm_i915_private
*dev_priv
,
1086 enum pipe pipe
, bool state
)
1092 reg
= PCH_DPLL(pipe
);
1093 val
= I915_READ(reg
);
1094 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1095 WARN(cur_state
!= state
,
1096 "PCH PLL state assertion failure (expected %s, current %s)\n",
1097 state_string(state
), state_string(cur_state
));
1099 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
1100 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
1102 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1103 enum pipe pipe
, bool state
)
1109 reg
= FDI_TX_CTL(pipe
);
1110 val
= I915_READ(reg
);
1111 cur_state
= !!(val
& FDI_TX_ENABLE
);
1112 WARN(cur_state
!= state
,
1113 "FDI TX state assertion failure (expected %s, current %s)\n",
1114 state_string(state
), state_string(cur_state
));
1116 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1117 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1119 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1120 enum pipe pipe
, bool state
)
1126 reg
= FDI_RX_CTL(pipe
);
1127 val
= I915_READ(reg
);
1128 cur_state
= !!(val
& FDI_RX_ENABLE
);
1129 WARN(cur_state
!= state
,
1130 "FDI RX state assertion failure (expected %s, current %s)\n",
1131 state_string(state
), state_string(cur_state
));
1133 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1134 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1136 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1142 /* ILK FDI PLL is always enabled */
1143 if (dev_priv
->info
->gen
== 5)
1146 reg
= FDI_TX_CTL(pipe
);
1147 val
= I915_READ(reg
);
1148 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1151 static void assert_fdi_rx_pll_enabled(struct drm_i915_private
*dev_priv
,
1157 reg
= FDI_RX_CTL(pipe
);
1158 val
= I915_READ(reg
);
1159 WARN(!(val
& FDI_RX_PLL_ENABLE
), "FDI RX PLL assertion failure, should be active but is disabled\n");
1162 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1165 int pp_reg
, lvds_reg
;
1167 enum pipe panel_pipe
= PIPE_A
;
1168 bool locked
= locked
;
1170 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1171 pp_reg
= PCH_PP_CONTROL
;
1172 lvds_reg
= PCH_LVDS
;
1174 pp_reg
= PP_CONTROL
;
1178 val
= I915_READ(pp_reg
);
1179 if (!(val
& PANEL_POWER_ON
) ||
1180 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1183 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1184 panel_pipe
= PIPE_B
;
1186 WARN(panel_pipe
== pipe
&& locked
,
1187 "panel assertion failure, pipe %c regs locked\n",
1191 static void assert_pipe(struct drm_i915_private
*dev_priv
,
1192 enum pipe pipe
, bool state
)
1198 reg
= PIPECONF(pipe
);
1199 val
= I915_READ(reg
);
1200 cur_state
= !!(val
& PIPECONF_ENABLE
);
1201 WARN(cur_state
!= state
,
1202 "pipe %c assertion failure (expected %s, current %s)\n",
1203 pipe
? 'B' : 'A', state_string(state
), state_string(cur_state
));
1205 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1206 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1208 static void assert_plane_enabled(struct drm_i915_private
*dev_priv
,
1214 reg
= DSPCNTR(plane
);
1215 val
= I915_READ(reg
);
1216 WARN(!(val
& DISPLAY_PLANE_ENABLE
),
1217 "plane %c assertion failure, should be active but is disabled\n",
1221 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1228 /* Need to check both planes against the pipe */
1229 for (i
= 0; i
< 2; i
++) {
1231 val
= I915_READ(reg
);
1232 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1233 DISPPLANE_SEL_PIPE_SHIFT
;
1234 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1235 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1236 i
, pipe
? 'B' : 'A');
1240 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1245 val
= I915_READ(PCH_DREF_CONTROL
);
1246 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1247 DREF_SUPERSPREAD_SOURCE_MASK
));
1248 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1251 static void assert_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1258 reg
= TRANSCONF(pipe
);
1259 val
= I915_READ(reg
);
1260 enabled
= !!(val
& TRANS_ENABLE
);
1261 WARN(enabled
, "transcoder assertion failed, should be off on pipe %c but is still active\n", pipe
? 'B' :'A');
1265 * intel_enable_pll - enable a PLL
1266 * @dev_priv: i915 private structure
1267 * @pipe: pipe PLL to enable
1269 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1270 * make sure the PLL reg is writable first though, since the panel write
1271 * protect mechanism may be enabled.
1273 * Note! This is for pre-ILK only.
1275 static void intel_enable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1280 /* No really, not for ILK+ */
1281 BUG_ON(dev_priv
->info
->gen
>= 5);
1283 /* PLL is protected by panel, make sure we can write it */
1284 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1285 assert_panel_unlocked(dev_priv
, pipe
);
1288 val
= I915_READ(reg
);
1289 val
|= DPLL_VCO_ENABLE
;
1291 /* We do this three times for luck */
1292 I915_WRITE(reg
, val
);
1294 udelay(150); /* wait for warmup */
1295 I915_WRITE(reg
, val
);
1297 udelay(150); /* wait for warmup */
1298 I915_WRITE(reg
, val
);
1300 udelay(150); /* wait for warmup */
1304 * intel_disable_pll - disable a PLL
1305 * @dev_priv: i915 private structure
1306 * @pipe: pipe PLL to disable
1308 * Disable the PLL for @pipe, making sure the pipe is off first.
1310 * Note! This is for pre-ILK only.
1312 static void intel_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1317 /* Don't disable pipe A or pipe A PLLs if needed */
1318 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1321 /* Make sure the pipe isn't still relying on us */
1322 assert_pipe_disabled(dev_priv
, pipe
);
1325 val
= I915_READ(reg
);
1326 val
&= ~DPLL_VCO_ENABLE
;
1327 I915_WRITE(reg
, val
);
1332 * intel_enable_pch_pll - enable PCH PLL
1333 * @dev_priv: i915 private structure
1334 * @pipe: pipe PLL to enable
1336 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1337 * drives the transcoder clock.
1339 static void intel_enable_pch_pll(struct drm_i915_private
*dev_priv
,
1345 /* PCH only available on ILK+ */
1346 BUG_ON(dev_priv
->info
->gen
< 5);
1348 /* PCH refclock must be enabled first */
1349 assert_pch_refclk_enabled(dev_priv
);
1351 reg
= PCH_DPLL(pipe
);
1352 val
= I915_READ(reg
);
1353 val
|= DPLL_VCO_ENABLE
;
1354 I915_WRITE(reg
, val
);
1359 static void intel_disable_pch_pll(struct drm_i915_private
*dev_priv
,
1365 /* PCH only available on ILK+ */
1366 BUG_ON(dev_priv
->info
->gen
< 5);
1368 /* Make sure transcoder isn't still depending on us */
1369 assert_transcoder_disabled(dev_priv
, pipe
);
1371 reg
= PCH_DPLL(pipe
);
1372 val
= I915_READ(reg
);
1373 val
&= ~DPLL_VCO_ENABLE
;
1374 I915_WRITE(reg
, val
);
1379 static void intel_enable_transcoder(struct drm_i915_private
*dev_priv
,
1385 /* PCH only available on ILK+ */
1386 BUG_ON(dev_priv
->info
->gen
< 5);
1388 /* Make sure PCH DPLL is enabled */
1389 assert_pch_pll_enabled(dev_priv
, pipe
);
1391 /* FDI must be feeding us bits for PCH ports */
1392 assert_fdi_tx_enabled(dev_priv
, pipe
);
1393 assert_fdi_rx_enabled(dev_priv
, pipe
);
1395 reg
= TRANSCONF(pipe
);
1396 val
= I915_READ(reg
);
1398 * make the BPC in transcoder be consistent with
1399 * that in pipeconf reg.
1401 val
&= ~PIPE_BPC_MASK
;
1402 val
|= I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
;
1403 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1404 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1405 DRM_ERROR("failed to enable transcoder %d\n", pipe
);
1408 static void intel_disable_transcoder(struct drm_i915_private
*dev_priv
,
1414 /* FDI relies on the transcoder */
1415 assert_fdi_tx_disabled(dev_priv
, pipe
);
1416 assert_fdi_rx_disabled(dev_priv
, pipe
);
1418 reg
= TRANSCONF(pipe
);
1419 val
= I915_READ(reg
);
1420 val
&= ~TRANS_ENABLE
;
1421 I915_WRITE(reg
, val
);
1422 /* wait for PCH transcoder off, transcoder state */
1423 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1424 DRM_ERROR("failed to disable transcoder\n");
1428 * intel_enable_pipe - enable a pipe, assertiing requirements
1429 * @dev_priv: i915 private structure
1430 * @pipe: pipe to enable
1431 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1433 * Enable @pipe, making sure that various hardware specific requirements
1434 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1436 * @pipe should be %PIPE_A or %PIPE_B.
1438 * Will wait until the pipe is actually running (i.e. first vblank) before
1441 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1448 * A pipe without a PLL won't actually be able to drive bits from
1449 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1452 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1453 assert_pll_enabled(dev_priv
, pipe
);
1456 /* if driving the PCH, we need FDI enabled */
1457 assert_fdi_rx_pll_enabled(dev_priv
, pipe
);
1458 assert_fdi_tx_pll_enabled(dev_priv
, pipe
);
1460 /* FIXME: assert CPU port conditions for SNB+ */
1463 reg
= PIPECONF(pipe
);
1464 val
= I915_READ(reg
);
1465 val
|= PIPECONF_ENABLE
;
1466 I915_WRITE(reg
, val
);
1468 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1472 * intel_disable_pipe - disable a pipe, assertiing requirements
1473 * @dev_priv: i915 private structure
1474 * @pipe: pipe to disable
1476 * Disable @pipe, making sure that various hardware specific requirements
1477 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1479 * @pipe should be %PIPE_A or %PIPE_B.
1481 * Will wait until the pipe has shut down before returning.
1483 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1490 * Make sure planes won't keep trying to pump pixels to us,
1491 * or we might hang the display.
1493 assert_planes_disabled(dev_priv
, pipe
);
1495 /* Don't disable pipe A or pipe A PLLs if needed */
1496 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1499 reg
= PIPECONF(pipe
);
1500 val
= I915_READ(reg
);
1501 val
&= ~PIPECONF_ENABLE
;
1502 I915_WRITE(reg
, val
);
1504 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1508 * intel_enable_plane - enable a display plane on a given pipe
1509 * @dev_priv: i915 private structure
1510 * @plane: plane to enable
1511 * @pipe: pipe being fed
1513 * Enable @plane on @pipe, making sure that @pipe is running first.
1515 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1516 enum plane plane
, enum pipe pipe
)
1521 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1522 assert_pipe_enabled(dev_priv
, pipe
);
1524 reg
= DSPCNTR(plane
);
1525 val
= I915_READ(reg
);
1526 val
|= DISPLAY_PLANE_ENABLE
;
1527 I915_WRITE(reg
, val
);
1529 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1533 * Plane regs are double buffered, going from enabled->disabled needs a
1534 * trigger in order to latch. The display address reg provides this.
1536 static void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1539 u32 reg
= DSPADDR(plane
);
1540 I915_WRITE(reg
, I915_READ(reg
));
1544 * intel_disable_plane - disable a display plane
1545 * @dev_priv: i915 private structure
1546 * @plane: plane to disable
1547 * @pipe: pipe consuming the data
1549 * Disable @plane; should be an independent operation.
1551 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1552 enum plane plane
, enum pipe pipe
)
1557 reg
= DSPCNTR(plane
);
1558 val
= I915_READ(reg
);
1559 val
&= ~DISPLAY_PLANE_ENABLE
;
1560 I915_WRITE(reg
, val
);
1562 intel_flush_display_plane(dev_priv
, plane
);
1563 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1566 static void i8xx_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1568 struct drm_device
*dev
= crtc
->dev
;
1569 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1570 struct drm_framebuffer
*fb
= crtc
->fb
;
1571 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1572 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
1573 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1575 u32 fbc_ctl
, fbc_ctl2
;
1577 if (fb
->pitch
== dev_priv
->cfb_pitch
&&
1578 obj
->fence_reg
== dev_priv
->cfb_fence
&&
1579 intel_crtc
->plane
== dev_priv
->cfb_plane
&&
1580 I915_READ(FBC_CONTROL
) & FBC_CTL_EN
)
1583 i8xx_disable_fbc(dev
);
1585 dev_priv
->cfb_pitch
= dev_priv
->cfb_size
/ FBC_LL_SIZE
;
1587 if (fb
->pitch
< dev_priv
->cfb_pitch
)
1588 dev_priv
->cfb_pitch
= fb
->pitch
;
1590 /* FBC_CTL wants 64B units */
1591 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1592 dev_priv
->cfb_fence
= obj
->fence_reg
;
1593 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1594 plane
= dev_priv
->cfb_plane
== 0 ? FBC_CTL_PLANEA
: FBC_CTL_PLANEB
;
1596 /* Clear old tags */
1597 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
1598 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
1601 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| plane
;
1602 if (obj
->tiling_mode
!= I915_TILING_NONE
)
1603 fbc_ctl2
|= FBC_CTL_CPU_FENCE
;
1604 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
1605 I915_WRITE(FBC_FENCE_OFF
, crtc
->y
);
1608 fbc_ctl
= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
1610 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
1611 fbc_ctl
|= (dev_priv
->cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
1612 fbc_ctl
|= (interval
& 0x2fff) << FBC_CTL_INTERVAL_SHIFT
;
1613 if (obj
->tiling_mode
!= I915_TILING_NONE
)
1614 fbc_ctl
|= dev_priv
->cfb_fence
;
1615 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1617 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1618 dev_priv
->cfb_pitch
, crtc
->y
, dev_priv
->cfb_plane
);
1621 void i8xx_disable_fbc(struct drm_device
*dev
)
1623 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1626 /* Disable compression */
1627 fbc_ctl
= I915_READ(FBC_CONTROL
);
1628 if ((fbc_ctl
& FBC_CTL_EN
) == 0)
1631 fbc_ctl
&= ~FBC_CTL_EN
;
1632 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1634 /* Wait for compressing bit to clear */
1635 if (wait_for((I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) == 0, 10)) {
1636 DRM_DEBUG_KMS("FBC idle timed out\n");
1640 DRM_DEBUG_KMS("disabled FBC\n");
1643 static bool i8xx_fbc_enabled(struct drm_device
*dev
)
1645 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1647 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
1650 static void g4x_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1652 struct drm_device
*dev
= crtc
->dev
;
1653 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1654 struct drm_framebuffer
*fb
= crtc
->fb
;
1655 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1656 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
1657 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1658 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
1659 unsigned long stall_watermark
= 200;
1662 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
1663 if (dpfc_ctl
& DPFC_CTL_EN
) {
1664 if (dev_priv
->cfb_pitch
== dev_priv
->cfb_pitch
/ 64 - 1 &&
1665 dev_priv
->cfb_fence
== obj
->fence_reg
&&
1666 dev_priv
->cfb_plane
== intel_crtc
->plane
&&
1667 dev_priv
->cfb_y
== crtc
->y
)
1670 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
& ~DPFC_CTL_EN
);
1671 POSTING_READ(DPFC_CONTROL
);
1672 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
1675 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1676 dev_priv
->cfb_fence
= obj
->fence_reg
;
1677 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1678 dev_priv
->cfb_y
= crtc
->y
;
1680 dpfc_ctl
= plane
| DPFC_SR_EN
| DPFC_CTL_LIMIT_1X
;
1681 if (obj
->tiling_mode
!= I915_TILING_NONE
) {
1682 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| dev_priv
->cfb_fence
;
1683 I915_WRITE(DPFC_CHICKEN
, DPFC_HT_MODIFY
);
1685 I915_WRITE(DPFC_CHICKEN
, ~DPFC_HT_MODIFY
);
1688 I915_WRITE(DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
1689 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
1690 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
1691 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->y
);
1694 I915_WRITE(DPFC_CONTROL
, I915_READ(DPFC_CONTROL
) | DPFC_CTL_EN
);
1696 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
1699 void g4x_disable_fbc(struct drm_device
*dev
)
1701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1704 /* Disable compression */
1705 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
1706 if (dpfc_ctl
& DPFC_CTL_EN
) {
1707 dpfc_ctl
&= ~DPFC_CTL_EN
;
1708 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
1710 DRM_DEBUG_KMS("disabled FBC\n");
1714 static bool g4x_fbc_enabled(struct drm_device
*dev
)
1716 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1718 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
1721 static void ironlake_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1723 struct drm_device
*dev
= crtc
->dev
;
1724 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1725 struct drm_framebuffer
*fb
= crtc
->fb
;
1726 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1727 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
1728 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1729 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
1730 unsigned long stall_watermark
= 200;
1733 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
1734 if (dpfc_ctl
& DPFC_CTL_EN
) {
1735 if (dev_priv
->cfb_pitch
== dev_priv
->cfb_pitch
/ 64 - 1 &&
1736 dev_priv
->cfb_fence
== obj
->fence_reg
&&
1737 dev_priv
->cfb_plane
== intel_crtc
->plane
&&
1738 dev_priv
->cfb_offset
== obj
->gtt_offset
&&
1739 dev_priv
->cfb_y
== crtc
->y
)
1742 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
& ~DPFC_CTL_EN
);
1743 POSTING_READ(ILK_DPFC_CONTROL
);
1744 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
1747 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1748 dev_priv
->cfb_fence
= obj
->fence_reg
;
1749 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1750 dev_priv
->cfb_offset
= obj
->gtt_offset
;
1751 dev_priv
->cfb_y
= crtc
->y
;
1753 dpfc_ctl
&= DPFC_RESERVED
;
1754 dpfc_ctl
|= (plane
| DPFC_CTL_LIMIT_1X
);
1755 if (obj
->tiling_mode
!= I915_TILING_NONE
) {
1756 dpfc_ctl
|= (DPFC_CTL_FENCE_EN
| dev_priv
->cfb_fence
);
1757 I915_WRITE(ILK_DPFC_CHICKEN
, DPFC_HT_MODIFY
);
1759 I915_WRITE(ILK_DPFC_CHICKEN
, ~DPFC_HT_MODIFY
);
1762 I915_WRITE(ILK_DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
1763 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
1764 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
1765 I915_WRITE(ILK_DPFC_FENCE_YOFF
, crtc
->y
);
1766 I915_WRITE(ILK_FBC_RT_BASE
, obj
->gtt_offset
| ILK_FBC_RT_VALID
);
1768 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
1771 I915_WRITE(SNB_DPFC_CTL_SA
,
1772 SNB_CPU_FENCE_ENABLE
| dev_priv
->cfb_fence
);
1773 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->y
);
1776 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
1779 void ironlake_disable_fbc(struct drm_device
*dev
)
1781 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1784 /* Disable compression */
1785 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
1786 if (dpfc_ctl
& DPFC_CTL_EN
) {
1787 dpfc_ctl
&= ~DPFC_CTL_EN
;
1788 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
1790 DRM_DEBUG_KMS("disabled FBC\n");
1794 static bool ironlake_fbc_enabled(struct drm_device
*dev
)
1796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1798 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
1801 bool intel_fbc_enabled(struct drm_device
*dev
)
1803 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1805 if (!dev_priv
->display
.fbc_enabled
)
1808 return dev_priv
->display
.fbc_enabled(dev
);
1811 void intel_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1813 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1815 if (!dev_priv
->display
.enable_fbc
)
1818 dev_priv
->display
.enable_fbc(crtc
, interval
);
1821 void intel_disable_fbc(struct drm_device
*dev
)
1823 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1825 if (!dev_priv
->display
.disable_fbc
)
1828 dev_priv
->display
.disable_fbc(dev
);
1832 * intel_update_fbc - enable/disable FBC as needed
1833 * @dev: the drm_device
1835 * Set up the framebuffer compression hardware at mode set time. We
1836 * enable it if possible:
1837 * - plane A only (on pre-965)
1838 * - no pixel mulitply/line duplication
1839 * - no alpha buffer discard
1841 * - framebuffer <= 2048 in width, 1536 in height
1843 * We can't assume that any compression will take place (worst case),
1844 * so the compressed buffer has to be the same size as the uncompressed
1845 * one. It also must reside (along with the line length buffer) in
1848 * We need to enable/disable FBC on a global basis.
1850 static void intel_update_fbc(struct drm_device
*dev
)
1852 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1853 struct drm_crtc
*crtc
= NULL
, *tmp_crtc
;
1854 struct intel_crtc
*intel_crtc
;
1855 struct drm_framebuffer
*fb
;
1856 struct intel_framebuffer
*intel_fb
;
1857 struct drm_i915_gem_object
*obj
;
1859 DRM_DEBUG_KMS("\n");
1861 if (!i915_powersave
)
1864 if (!I915_HAS_FBC(dev
))
1868 * If FBC is already on, we just have to verify that we can
1869 * keep it that way...
1870 * Need to disable if:
1871 * - more than one pipe is active
1872 * - changing FBC params (stride, fence, mode)
1873 * - new fb is too large to fit in compressed buffer
1874 * - going to an unsupported config (interlace, pixel multiply, etc.)
1876 list_for_each_entry(tmp_crtc
, &dev
->mode_config
.crtc_list
, head
) {
1877 if (tmp_crtc
->enabled
) {
1879 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1880 dev_priv
->no_fbc_reason
= FBC_MULTIPLE_PIPES
;
1887 if (!crtc
|| crtc
->fb
== NULL
) {
1888 DRM_DEBUG_KMS("no output, disabling\n");
1889 dev_priv
->no_fbc_reason
= FBC_NO_OUTPUT
;
1893 intel_crtc
= to_intel_crtc(crtc
);
1895 intel_fb
= to_intel_framebuffer(fb
);
1896 obj
= intel_fb
->obj
;
1898 if (intel_fb
->obj
->base
.size
> dev_priv
->cfb_size
) {
1899 DRM_DEBUG_KMS("framebuffer too large, disabling "
1901 dev_priv
->no_fbc_reason
= FBC_STOLEN_TOO_SMALL
;
1904 if ((crtc
->mode
.flags
& DRM_MODE_FLAG_INTERLACE
) ||
1905 (crtc
->mode
.flags
& DRM_MODE_FLAG_DBLSCAN
)) {
1906 DRM_DEBUG_KMS("mode incompatible with compression, "
1908 dev_priv
->no_fbc_reason
= FBC_UNSUPPORTED_MODE
;
1911 if ((crtc
->mode
.hdisplay
> 2048) ||
1912 (crtc
->mode
.vdisplay
> 1536)) {
1913 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1914 dev_priv
->no_fbc_reason
= FBC_MODE_TOO_LARGE
;
1917 if ((IS_I915GM(dev
) || IS_I945GM(dev
)) && intel_crtc
->plane
!= 0) {
1918 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1919 dev_priv
->no_fbc_reason
= FBC_BAD_PLANE
;
1922 if (obj
->tiling_mode
!= I915_TILING_X
) {
1923 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1924 dev_priv
->no_fbc_reason
= FBC_NOT_TILED
;
1928 /* If the kernel debugger is active, always disable compression */
1929 if (in_dbg_master())
1932 intel_enable_fbc(crtc
, 500);
1936 /* Multiple disables should be harmless */
1937 if (intel_fbc_enabled(dev
)) {
1938 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1939 intel_disable_fbc(dev
);
1944 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1945 struct drm_i915_gem_object
*obj
,
1946 struct intel_ring_buffer
*pipelined
)
1951 switch (obj
->tiling_mode
) {
1952 case I915_TILING_NONE
:
1953 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1954 alignment
= 128 * 1024;
1955 else if (INTEL_INFO(dev
)->gen
>= 4)
1956 alignment
= 4 * 1024;
1958 alignment
= 64 * 1024;
1961 /* pin() will align the object as required by fence */
1965 /* FIXME: Is this true? */
1966 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1972 ret
= i915_gem_object_pin(obj
, alignment
, true);
1976 ret
= i915_gem_object_set_to_display_plane(obj
, pipelined
);
1980 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1981 * fence, whereas 965+ only requires a fence if using
1982 * framebuffer compression. For simplicity, we always install
1983 * a fence as the cost is not that onerous.
1985 if (obj
->tiling_mode
!= I915_TILING_NONE
) {
1986 ret
= i915_gem_object_get_fence(obj
, pipelined
, false);
1994 i915_gem_object_unpin(obj
);
1998 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2000 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2001 int x
, int y
, enum mode_set_atomic state
)
2003 struct drm_device
*dev
= crtc
->dev
;
2004 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2005 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2006 struct intel_framebuffer
*intel_fb
;
2007 struct drm_i915_gem_object
*obj
;
2008 int plane
= intel_crtc
->plane
;
2009 unsigned long Start
, Offset
;
2018 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2022 intel_fb
= to_intel_framebuffer(fb
);
2023 obj
= intel_fb
->obj
;
2025 reg
= DSPCNTR(plane
);
2026 dspcntr
= I915_READ(reg
);
2027 /* Mask out pixel format bits in case we change it */
2028 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2029 switch (fb
->bits_per_pixel
) {
2031 dspcntr
|= DISPPLANE_8BPP
;
2034 if (fb
->depth
== 15)
2035 dspcntr
|= DISPPLANE_15_16BPP
;
2037 dspcntr
|= DISPPLANE_16BPP
;
2041 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
2044 DRM_ERROR("Unknown color depth\n");
2047 if (INTEL_INFO(dev
)->gen
>= 4) {
2048 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2049 dspcntr
|= DISPPLANE_TILED
;
2051 dspcntr
&= ~DISPPLANE_TILED
;
2054 if (HAS_PCH_SPLIT(dev
))
2056 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2058 I915_WRITE(reg
, dspcntr
);
2060 Start
= obj
->gtt_offset
;
2061 Offset
= y
* fb
->pitch
+ x
* (fb
->bits_per_pixel
/ 8);
2063 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2064 Start
, Offset
, x
, y
, fb
->pitch
);
2065 I915_WRITE(DSPSTRIDE(plane
), fb
->pitch
);
2066 if (INTEL_INFO(dev
)->gen
>= 4) {
2067 I915_WRITE(DSPSURF(plane
), Start
);
2068 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2069 I915_WRITE(DSPADDR(plane
), Offset
);
2071 I915_WRITE(DSPADDR(plane
), Start
+ Offset
);
2074 intel_update_fbc(dev
);
2075 intel_increase_pllclock(crtc
);
2081 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2082 struct drm_framebuffer
*old_fb
)
2084 struct drm_device
*dev
= crtc
->dev
;
2085 struct drm_i915_master_private
*master_priv
;
2086 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2091 DRM_DEBUG_KMS("No FB bound\n");
2095 switch (intel_crtc
->plane
) {
2103 mutex_lock(&dev
->struct_mutex
);
2104 ret
= intel_pin_and_fence_fb_obj(dev
,
2105 to_intel_framebuffer(crtc
->fb
)->obj
,
2108 mutex_unlock(&dev
->struct_mutex
);
2113 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2114 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2116 wait_event(dev_priv
->pending_flip_queue
,
2117 atomic_read(&obj
->pending_flip
) == 0);
2119 /* Big Hammer, we also need to ensure that any pending
2120 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2121 * current scanout is retired before unpinning the old
2124 ret
= i915_gem_object_flush_gpu(obj
, false);
2126 i915_gem_object_unpin(to_intel_framebuffer(crtc
->fb
)->obj
);
2127 mutex_unlock(&dev
->struct_mutex
);
2132 ret
= intel_pipe_set_base_atomic(crtc
, crtc
->fb
, x
, y
,
2133 LEAVE_ATOMIC_MODE_SET
);
2135 i915_gem_object_unpin(to_intel_framebuffer(crtc
->fb
)->obj
);
2136 mutex_unlock(&dev
->struct_mutex
);
2141 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2142 i915_gem_object_unpin(to_intel_framebuffer(old_fb
)->obj
);
2145 mutex_unlock(&dev
->struct_mutex
);
2147 if (!dev
->primary
->master
)
2150 master_priv
= dev
->primary
->master
->driver_priv
;
2151 if (!master_priv
->sarea_priv
)
2154 if (intel_crtc
->pipe
) {
2155 master_priv
->sarea_priv
->pipeB_x
= x
;
2156 master_priv
->sarea_priv
->pipeB_y
= y
;
2158 master_priv
->sarea_priv
->pipeA_x
= x
;
2159 master_priv
->sarea_priv
->pipeA_y
= y
;
2165 static void ironlake_set_pll_edp(struct drm_crtc
*crtc
, int clock
)
2167 struct drm_device
*dev
= crtc
->dev
;
2168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2171 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock
);
2172 dpa_ctl
= I915_READ(DP_A
);
2173 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
2175 if (clock
< 200000) {
2177 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
2178 /* workaround for 160Mhz:
2179 1) program 0x4600c bits 15:0 = 0x8124
2180 2) program 0x46010 bit 0 = 1
2181 3) program 0x46034 bit 24 = 1
2182 4) program 0x64000 bit 14 = 1
2184 temp
= I915_READ(0x4600c);
2186 I915_WRITE(0x4600c, temp
| 0x8124);
2188 temp
= I915_READ(0x46010);
2189 I915_WRITE(0x46010, temp
| 1);
2191 temp
= I915_READ(0x46034);
2192 I915_WRITE(0x46034, temp
| (1 << 24));
2194 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
2196 I915_WRITE(DP_A
, dpa_ctl
);
2202 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2204 struct drm_device
*dev
= crtc
->dev
;
2205 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2206 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2207 int pipe
= intel_crtc
->pipe
;
2210 /* enable normal train */
2211 reg
= FDI_TX_CTL(pipe
);
2212 temp
= I915_READ(reg
);
2213 temp
&= ~FDI_LINK_TRAIN_NONE
;
2214 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2215 I915_WRITE(reg
, temp
);
2217 reg
= FDI_RX_CTL(pipe
);
2218 temp
= I915_READ(reg
);
2219 if (HAS_PCH_CPT(dev
)) {
2220 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2221 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2223 temp
&= ~FDI_LINK_TRAIN_NONE
;
2224 temp
|= FDI_LINK_TRAIN_NONE
;
2226 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2228 /* wait one idle pattern time */
2233 /* The FDI link training functions for ILK/Ibexpeak. */
2234 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2236 struct drm_device
*dev
= crtc
->dev
;
2237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2238 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2239 int pipe
= intel_crtc
->pipe
;
2240 int plane
= intel_crtc
->plane
;
2241 u32 reg
, temp
, tries
;
2243 /* FDI needs bits from pipe & plane first */
2244 assert_pipe_enabled(dev_priv
, pipe
);
2245 assert_plane_enabled(dev_priv
, plane
);
2247 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2249 reg
= FDI_RX_IMR(pipe
);
2250 temp
= I915_READ(reg
);
2251 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2252 temp
&= ~FDI_RX_BIT_LOCK
;
2253 I915_WRITE(reg
, temp
);
2257 /* enable CPU FDI TX and PCH FDI RX */
2258 reg
= FDI_TX_CTL(pipe
);
2259 temp
= I915_READ(reg
);
2261 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2262 temp
&= ~FDI_LINK_TRAIN_NONE
;
2263 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2264 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2266 reg
= FDI_RX_CTL(pipe
);
2267 temp
= I915_READ(reg
);
2268 temp
&= ~FDI_LINK_TRAIN_NONE
;
2269 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2270 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2275 /* Ironlake workaround, enable clock pointer after FDI enable*/
2276 if (HAS_PCH_IBX(dev
)) {
2277 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2278 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2279 FDI_RX_PHASE_SYNC_POINTER_EN
);
2282 reg
= FDI_RX_IIR(pipe
);
2283 for (tries
= 0; tries
< 5; tries
++) {
2284 temp
= I915_READ(reg
);
2285 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2287 if ((temp
& FDI_RX_BIT_LOCK
)) {
2288 DRM_DEBUG_KMS("FDI train 1 done.\n");
2289 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2294 DRM_ERROR("FDI train 1 fail!\n");
2297 reg
= FDI_TX_CTL(pipe
);
2298 temp
= I915_READ(reg
);
2299 temp
&= ~FDI_LINK_TRAIN_NONE
;
2300 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2301 I915_WRITE(reg
, temp
);
2303 reg
= FDI_RX_CTL(pipe
);
2304 temp
= I915_READ(reg
);
2305 temp
&= ~FDI_LINK_TRAIN_NONE
;
2306 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2307 I915_WRITE(reg
, temp
);
2312 reg
= FDI_RX_IIR(pipe
);
2313 for (tries
= 0; tries
< 5; tries
++) {
2314 temp
= I915_READ(reg
);
2315 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2317 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2318 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2319 DRM_DEBUG_KMS("FDI train 2 done.\n");
2324 DRM_ERROR("FDI train 2 fail!\n");
2326 DRM_DEBUG_KMS("FDI train done\n");
2330 static const int snb_b_fdi_train_param
[] = {
2331 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2332 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2333 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2334 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2337 /* The FDI link training functions for SNB/Cougarpoint. */
2338 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2340 struct drm_device
*dev
= crtc
->dev
;
2341 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2342 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2343 int pipe
= intel_crtc
->pipe
;
2346 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2348 reg
= FDI_RX_IMR(pipe
);
2349 temp
= I915_READ(reg
);
2350 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2351 temp
&= ~FDI_RX_BIT_LOCK
;
2352 I915_WRITE(reg
, temp
);
2357 /* enable CPU FDI TX and PCH FDI RX */
2358 reg
= FDI_TX_CTL(pipe
);
2359 temp
= I915_READ(reg
);
2361 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2362 temp
&= ~FDI_LINK_TRAIN_NONE
;
2363 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2364 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2366 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2367 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2369 reg
= FDI_RX_CTL(pipe
);
2370 temp
= I915_READ(reg
);
2371 if (HAS_PCH_CPT(dev
)) {
2372 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2373 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2375 temp
&= ~FDI_LINK_TRAIN_NONE
;
2376 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2378 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2383 for (i
= 0; i
< 4; i
++ ) {
2384 reg
= FDI_TX_CTL(pipe
);
2385 temp
= I915_READ(reg
);
2386 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2387 temp
|= snb_b_fdi_train_param
[i
];
2388 I915_WRITE(reg
, temp
);
2393 reg
= FDI_RX_IIR(pipe
);
2394 temp
= I915_READ(reg
);
2395 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2397 if (temp
& FDI_RX_BIT_LOCK
) {
2398 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2399 DRM_DEBUG_KMS("FDI train 1 done.\n");
2404 DRM_ERROR("FDI train 1 fail!\n");
2407 reg
= FDI_TX_CTL(pipe
);
2408 temp
= I915_READ(reg
);
2409 temp
&= ~FDI_LINK_TRAIN_NONE
;
2410 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2412 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2414 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2416 I915_WRITE(reg
, temp
);
2418 reg
= FDI_RX_CTL(pipe
);
2419 temp
= I915_READ(reg
);
2420 if (HAS_PCH_CPT(dev
)) {
2421 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2422 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2424 temp
&= ~FDI_LINK_TRAIN_NONE
;
2425 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2427 I915_WRITE(reg
, temp
);
2432 for (i
= 0; i
< 4; i
++ ) {
2433 reg
= FDI_TX_CTL(pipe
);
2434 temp
= I915_READ(reg
);
2435 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2436 temp
|= snb_b_fdi_train_param
[i
];
2437 I915_WRITE(reg
, temp
);
2442 reg
= FDI_RX_IIR(pipe
);
2443 temp
= I915_READ(reg
);
2444 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2446 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2447 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2448 DRM_DEBUG_KMS("FDI train 2 done.\n");
2453 DRM_ERROR("FDI train 2 fail!\n");
2455 DRM_DEBUG_KMS("FDI train done.\n");
2458 static void ironlake_fdi_enable(struct drm_crtc
*crtc
)
2460 struct drm_device
*dev
= crtc
->dev
;
2461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2462 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2463 int pipe
= intel_crtc
->pipe
;
2466 /* Write the TU size bits so error detection works */
2467 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
2468 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
2470 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2471 reg
= FDI_RX_CTL(pipe
);
2472 temp
= I915_READ(reg
);
2473 temp
&= ~((0x7 << 19) | (0x7 << 16));
2474 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2475 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2476 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2481 /* Switch from Rawclk to PCDclk */
2482 temp
= I915_READ(reg
);
2483 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2488 /* Enable CPU FDI TX PLL, always on for Ironlake */
2489 reg
= FDI_TX_CTL(pipe
);
2490 temp
= I915_READ(reg
);
2491 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2492 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2499 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2501 struct drm_device
*dev
= crtc
->dev
;
2502 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2503 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2504 int pipe
= intel_crtc
->pipe
;
2507 /* disable CPU FDI tx and PCH FDI rx */
2508 reg
= FDI_TX_CTL(pipe
);
2509 temp
= I915_READ(reg
);
2510 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2513 reg
= FDI_RX_CTL(pipe
);
2514 temp
= I915_READ(reg
);
2515 temp
&= ~(0x7 << 16);
2516 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2517 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2522 /* Ironlake workaround, disable clock pointer after downing FDI */
2523 if (HAS_PCH_IBX(dev
)) {
2524 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2525 I915_WRITE(FDI_RX_CHICKEN(pipe
),
2526 I915_READ(FDI_RX_CHICKEN(pipe
) &
2527 ~FDI_RX_PHASE_SYNC_POINTER_EN
));
2530 /* still set train pattern 1 */
2531 reg
= FDI_TX_CTL(pipe
);
2532 temp
= I915_READ(reg
);
2533 temp
&= ~FDI_LINK_TRAIN_NONE
;
2534 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2535 I915_WRITE(reg
, temp
);
2537 reg
= FDI_RX_CTL(pipe
);
2538 temp
= I915_READ(reg
);
2539 if (HAS_PCH_CPT(dev
)) {
2540 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2541 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2543 temp
&= ~FDI_LINK_TRAIN_NONE
;
2544 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2546 /* BPC in FDI rx is consistent with that in PIPECONF */
2547 temp
&= ~(0x07 << 16);
2548 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2549 I915_WRITE(reg
, temp
);
2556 * When we disable a pipe, we need to clear any pending scanline wait events
2557 * to avoid hanging the ring, which we assume we are waiting on.
2559 static void intel_clear_scanline_wait(struct drm_device
*dev
)
2561 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2562 struct intel_ring_buffer
*ring
;
2566 /* Can't break the hang on i8xx */
2569 ring
= LP_RING(dev_priv
);
2570 tmp
= I915_READ_CTL(ring
);
2571 if (tmp
& RING_WAIT
)
2572 I915_WRITE_CTL(ring
, tmp
);
2575 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2577 struct drm_i915_gem_object
*obj
;
2578 struct drm_i915_private
*dev_priv
;
2580 if (crtc
->fb
== NULL
)
2583 obj
= to_intel_framebuffer(crtc
->fb
)->obj
;
2584 dev_priv
= crtc
->dev
->dev_private
;
2585 wait_event(dev_priv
->pending_flip_queue
,
2586 atomic_read(&obj
->pending_flip
) == 0);
2589 static bool intel_crtc_driving_pch(struct drm_crtc
*crtc
)
2591 struct drm_device
*dev
= crtc
->dev
;
2592 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2593 struct intel_encoder
*encoder
;
2596 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2597 * must be driven by its own crtc; no sharing is possible.
2599 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
2600 if (encoder
->base
.crtc
!= crtc
)
2603 switch (encoder
->type
) {
2604 case INTEL_OUTPUT_EDP
:
2605 if (!intel_encoder_is_pch_edp(&encoder
->base
))
2615 * Enable PCH resources required for PCH ports:
2617 * - FDI training & RX/TX
2618 * - update transcoder timings
2619 * - DP transcoding bits
2622 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
2624 struct drm_device
*dev
= crtc
->dev
;
2625 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2626 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2627 int pipe
= intel_crtc
->pipe
;
2630 /* For PCH output, training FDI link */
2632 gen6_fdi_link_train(crtc
);
2634 ironlake_fdi_link_train(crtc
);
2636 intel_enable_pch_pll(dev_priv
, pipe
);
2638 if (HAS_PCH_CPT(dev
)) {
2639 /* Be sure PCH DPLL SEL is set */
2640 temp
= I915_READ(PCH_DPLL_SEL
);
2641 if (pipe
== 0 && (temp
& TRANSA_DPLL_ENABLE
) == 0)
2642 temp
|= (TRANSA_DPLL_ENABLE
| TRANSA_DPLLA_SEL
);
2643 else if (pipe
== 1 && (temp
& TRANSB_DPLL_ENABLE
) == 0)
2644 temp
|= (TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
2645 I915_WRITE(PCH_DPLL_SEL
, temp
);
2648 /* set transcoder timing, panel must allow it */
2649 assert_panel_unlocked(dev_priv
, pipe
);
2650 I915_WRITE(TRANS_HTOTAL(pipe
), I915_READ(HTOTAL(pipe
)));
2651 I915_WRITE(TRANS_HBLANK(pipe
), I915_READ(HBLANK(pipe
)));
2652 I915_WRITE(TRANS_HSYNC(pipe
), I915_READ(HSYNC(pipe
)));
2654 I915_WRITE(TRANS_VTOTAL(pipe
), I915_READ(VTOTAL(pipe
)));
2655 I915_WRITE(TRANS_VBLANK(pipe
), I915_READ(VBLANK(pipe
)));
2656 I915_WRITE(TRANS_VSYNC(pipe
), I915_READ(VSYNC(pipe
)));
2658 intel_fdi_normal_train(crtc
);
2660 /* For PCH DP, enable TRANS_DP_CTL */
2661 if (HAS_PCH_CPT(dev
) &&
2662 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
2663 reg
= TRANS_DP_CTL(pipe
);
2664 temp
= I915_READ(reg
);
2665 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
2666 TRANS_DP_SYNC_MASK
|
2668 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
2669 TRANS_DP_ENH_FRAMING
);
2670 temp
|= TRANS_DP_8BPC
;
2672 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
2673 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
2674 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
2675 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
2677 switch (intel_trans_dp_port_sel(crtc
)) {
2679 temp
|= TRANS_DP_PORT_SEL_B
;
2682 temp
|= TRANS_DP_PORT_SEL_C
;
2685 temp
|= TRANS_DP_PORT_SEL_D
;
2688 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2689 temp
|= TRANS_DP_PORT_SEL_B
;
2693 I915_WRITE(reg
, temp
);
2696 intel_enable_transcoder(dev_priv
, pipe
);
2699 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
2701 struct drm_device
*dev
= crtc
->dev
;
2702 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2703 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2704 int pipe
= intel_crtc
->pipe
;
2705 int plane
= intel_crtc
->plane
;
2709 if (intel_crtc
->active
)
2712 intel_crtc
->active
= true;
2713 intel_update_watermarks(dev
);
2715 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
2716 temp
= I915_READ(PCH_LVDS
);
2717 if ((temp
& LVDS_PORT_EN
) == 0)
2718 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
2721 is_pch_port
= intel_crtc_driving_pch(crtc
);
2724 ironlake_fdi_enable(crtc
);
2726 ironlake_fdi_disable(crtc
);
2728 /* Enable panel fitting for LVDS */
2729 if (dev_priv
->pch_pf_size
&&
2730 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) || HAS_eDP
)) {
2731 /* Force use of hard-coded filter coefficients
2732 * as some pre-programmed values are broken,
2735 I915_WRITE(pipe
? PFB_CTL_1
: PFA_CTL_1
,
2736 PF_ENABLE
| PF_FILTER_MED_3x3
);
2737 I915_WRITE(pipe
? PFB_WIN_POS
: PFA_WIN_POS
,
2738 dev_priv
->pch_pf_pos
);
2739 I915_WRITE(pipe
? PFB_WIN_SZ
: PFA_WIN_SZ
,
2740 dev_priv
->pch_pf_size
);
2743 intel_enable_pipe(dev_priv
, pipe
, is_pch_port
);
2744 intel_enable_plane(dev_priv
, plane
, pipe
);
2747 ironlake_pch_enable(crtc
);
2749 intel_crtc_load_lut(crtc
);
2750 intel_update_fbc(dev
);
2751 intel_crtc_update_cursor(crtc
, true);
2754 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
2756 struct drm_device
*dev
= crtc
->dev
;
2757 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2758 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2759 int pipe
= intel_crtc
->pipe
;
2760 int plane
= intel_crtc
->plane
;
2763 if (!intel_crtc
->active
)
2766 intel_crtc_wait_for_pending_flips(crtc
);
2767 drm_vblank_off(dev
, pipe
);
2768 intel_crtc_update_cursor(crtc
, false);
2770 intel_disable_plane(dev_priv
, plane
, pipe
);
2772 if (dev_priv
->cfb_plane
== plane
&&
2773 dev_priv
->display
.disable_fbc
)
2774 dev_priv
->display
.disable_fbc(dev
);
2776 intel_disable_pipe(dev_priv
, pipe
);
2779 I915_WRITE(pipe
? PFB_CTL_1
: PFA_CTL_1
, 0);
2780 I915_WRITE(pipe
? PFB_WIN_SZ
: PFA_WIN_SZ
, 0);
2782 ironlake_fdi_disable(crtc
);
2784 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
2785 temp
= I915_READ(PCH_LVDS
);
2786 if (temp
& LVDS_PORT_EN
) {
2787 I915_WRITE(PCH_LVDS
, temp
& ~LVDS_PORT_EN
);
2788 POSTING_READ(PCH_LVDS
);
2793 intel_disable_transcoder(dev_priv
, pipe
);
2795 if (HAS_PCH_CPT(dev
)) {
2796 /* disable TRANS_DP_CTL */
2797 reg
= TRANS_DP_CTL(pipe
);
2798 temp
= I915_READ(reg
);
2799 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
2800 I915_WRITE(reg
, temp
);
2802 /* disable DPLL_SEL */
2803 temp
= I915_READ(PCH_DPLL_SEL
);
2805 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
2807 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
2808 I915_WRITE(PCH_DPLL_SEL
, temp
);
2811 /* disable PCH DPLL */
2812 intel_disable_pch_pll(dev_priv
, pipe
);
2814 /* Switch from PCDclk to Rawclk */
2815 reg
= FDI_RX_CTL(pipe
);
2816 temp
= I915_READ(reg
);
2817 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2819 /* Disable CPU FDI TX PLL */
2820 reg
= FDI_TX_CTL(pipe
);
2821 temp
= I915_READ(reg
);
2822 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2827 reg
= FDI_RX_CTL(pipe
);
2828 temp
= I915_READ(reg
);
2829 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2831 /* Wait for the clocks to turn off. */
2835 intel_crtc
->active
= false;
2836 intel_update_watermarks(dev
);
2837 intel_update_fbc(dev
);
2838 intel_clear_scanline_wait(dev
);
2841 static void ironlake_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2843 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2844 int pipe
= intel_crtc
->pipe
;
2845 int plane
= intel_crtc
->plane
;
2847 /* XXX: When our outputs are all unaware of DPMS modes other than off
2848 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2851 case DRM_MODE_DPMS_ON
:
2852 case DRM_MODE_DPMS_STANDBY
:
2853 case DRM_MODE_DPMS_SUSPEND
:
2854 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe
, plane
);
2855 ironlake_crtc_enable(crtc
);
2858 case DRM_MODE_DPMS_OFF
:
2859 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe
, plane
);
2860 ironlake_crtc_disable(crtc
);
2865 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
2867 if (!enable
&& intel_crtc
->overlay
) {
2868 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2870 mutex_lock(&dev
->struct_mutex
);
2871 (void) intel_overlay_switch_off(intel_crtc
->overlay
, false);
2872 mutex_unlock(&dev
->struct_mutex
);
2875 /* Let userspace switch the overlay on again. In most cases userspace
2876 * has to recompute where to put it anyway.
2880 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
2882 struct drm_device
*dev
= crtc
->dev
;
2883 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2884 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2885 int pipe
= intel_crtc
->pipe
;
2886 int plane
= intel_crtc
->plane
;
2888 if (intel_crtc
->active
)
2891 intel_crtc
->active
= true;
2892 intel_update_watermarks(dev
);
2894 intel_enable_pll(dev_priv
, pipe
);
2895 intel_enable_pipe(dev_priv
, pipe
, false);
2896 intel_enable_plane(dev_priv
, plane
, pipe
);
2898 intel_crtc_load_lut(crtc
);
2899 intel_update_fbc(dev
);
2901 /* Give the overlay scaler a chance to enable if it's on this pipe */
2902 intel_crtc_dpms_overlay(intel_crtc
, true);
2903 intel_crtc_update_cursor(crtc
, true);
2906 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
2908 struct drm_device
*dev
= crtc
->dev
;
2909 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2910 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2911 int pipe
= intel_crtc
->pipe
;
2912 int plane
= intel_crtc
->plane
;
2914 if (!intel_crtc
->active
)
2917 /* Give the overlay scaler a chance to disable if it's on this pipe */
2918 intel_crtc_wait_for_pending_flips(crtc
);
2919 drm_vblank_off(dev
, pipe
);
2920 intel_crtc_dpms_overlay(intel_crtc
, false);
2921 intel_crtc_update_cursor(crtc
, false);
2923 if (dev_priv
->cfb_plane
== plane
&&
2924 dev_priv
->display
.disable_fbc
)
2925 dev_priv
->display
.disable_fbc(dev
);
2927 intel_disable_plane(dev_priv
, plane
, pipe
);
2928 intel_disable_pipe(dev_priv
, pipe
);
2929 intel_disable_pll(dev_priv
, pipe
);
2931 intel_crtc
->active
= false;
2932 intel_update_fbc(dev
);
2933 intel_update_watermarks(dev
);
2934 intel_clear_scanline_wait(dev
);
2937 static void i9xx_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2939 /* XXX: When our outputs are all unaware of DPMS modes other than off
2940 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2943 case DRM_MODE_DPMS_ON
:
2944 case DRM_MODE_DPMS_STANDBY
:
2945 case DRM_MODE_DPMS_SUSPEND
:
2946 i9xx_crtc_enable(crtc
);
2948 case DRM_MODE_DPMS_OFF
:
2949 i9xx_crtc_disable(crtc
);
2955 * Sets the power management mode of the pipe and plane.
2957 static void intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2959 struct drm_device
*dev
= crtc
->dev
;
2960 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2961 struct drm_i915_master_private
*master_priv
;
2962 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2963 int pipe
= intel_crtc
->pipe
;
2966 if (intel_crtc
->dpms_mode
== mode
)
2969 intel_crtc
->dpms_mode
= mode
;
2971 dev_priv
->display
.dpms(crtc
, mode
);
2973 if (!dev
->primary
->master
)
2976 master_priv
= dev
->primary
->master
->driver_priv
;
2977 if (!master_priv
->sarea_priv
)
2980 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
2984 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
2985 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
2988 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
2989 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
2992 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe
);
2997 static void intel_crtc_disable(struct drm_crtc
*crtc
)
2999 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
3000 struct drm_device
*dev
= crtc
->dev
;
3002 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
3005 mutex_lock(&dev
->struct_mutex
);
3006 i915_gem_object_unpin(to_intel_framebuffer(crtc
->fb
)->obj
);
3007 mutex_unlock(&dev
->struct_mutex
);
3011 /* Prepare for a mode set.
3013 * Note we could be a lot smarter here. We need to figure out which outputs
3014 * will be enabled, which disabled (in short, how the config will changes)
3015 * and perform the minimum necessary steps to accomplish that, e.g. updating
3016 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3017 * panel fitting is in the proper state, etc.
3019 static void i9xx_crtc_prepare(struct drm_crtc
*crtc
)
3021 i9xx_crtc_disable(crtc
);
3024 static void i9xx_crtc_commit(struct drm_crtc
*crtc
)
3026 i9xx_crtc_enable(crtc
);
3029 static void ironlake_crtc_prepare(struct drm_crtc
*crtc
)
3031 ironlake_crtc_disable(crtc
);
3034 static void ironlake_crtc_commit(struct drm_crtc
*crtc
)
3036 ironlake_crtc_enable(crtc
);
3039 void intel_encoder_prepare (struct drm_encoder
*encoder
)
3041 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
3042 /* lvds has its own version of prepare see intel_lvds_prepare */
3043 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
3046 void intel_encoder_commit (struct drm_encoder
*encoder
)
3048 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
3049 /* lvds has its own version of commit see intel_lvds_commit */
3050 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
3053 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3055 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3057 drm_encoder_cleanup(encoder
);
3058 kfree(intel_encoder
);
3061 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
3062 struct drm_display_mode
*mode
,
3063 struct drm_display_mode
*adjusted_mode
)
3065 struct drm_device
*dev
= crtc
->dev
;
3067 if (HAS_PCH_SPLIT(dev
)) {
3068 /* FDI link clock is fixed at 2.7G */
3069 if (mode
->clock
* 3 > IRONLAKE_FDI_FREQ
* 4)
3073 /* XXX some encoders set the crtcinfo, others don't.
3074 * Obviously we need some form of conflict resolution here...
3076 if (adjusted_mode
->crtc_htotal
== 0)
3077 drm_mode_set_crtcinfo(adjusted_mode
, 0);
3082 static int i945_get_display_clock_speed(struct drm_device
*dev
)
3087 static int i915_get_display_clock_speed(struct drm_device
*dev
)
3092 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
3097 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
3101 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
3103 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
3106 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
3107 case GC_DISPLAY_CLOCK_333_MHZ
:
3110 case GC_DISPLAY_CLOCK_190_200_MHZ
:
3116 static int i865_get_display_clock_speed(struct drm_device
*dev
)
3121 static int i855_get_display_clock_speed(struct drm_device
*dev
)
3124 /* Assume that the hardware is in the high speed state. This
3125 * should be the default.
3127 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
3128 case GC_CLOCK_133_200
:
3129 case GC_CLOCK_100_200
:
3131 case GC_CLOCK_166_250
:
3133 case GC_CLOCK_100_133
:
3137 /* Shouldn't happen */
3141 static int i830_get_display_clock_speed(struct drm_device
*dev
)
3155 fdi_reduce_ratio(u32
*num
, u32
*den
)
3157 while (*num
> 0xffffff || *den
> 0xffffff) {
3164 ironlake_compute_m_n(int bits_per_pixel
, int nlanes
, int pixel_clock
,
3165 int link_clock
, struct fdi_m_n
*m_n
)
3167 m_n
->tu
= 64; /* default size */
3169 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3170 m_n
->gmch_m
= bits_per_pixel
* pixel_clock
;
3171 m_n
->gmch_n
= link_clock
* nlanes
* 8;
3172 fdi_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
3174 m_n
->link_m
= pixel_clock
;
3175 m_n
->link_n
= link_clock
;
3176 fdi_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
3180 struct intel_watermark_params
{
3181 unsigned long fifo_size
;
3182 unsigned long max_wm
;
3183 unsigned long default_wm
;
3184 unsigned long guard_size
;
3185 unsigned long cacheline_size
;
3188 /* Pineview has different values for various configs */
3189 static struct intel_watermark_params pineview_display_wm
= {
3190 PINEVIEW_DISPLAY_FIFO
,
3194 PINEVIEW_FIFO_LINE_SIZE
3196 static struct intel_watermark_params pineview_display_hplloff_wm
= {
3197 PINEVIEW_DISPLAY_FIFO
,
3199 PINEVIEW_DFT_HPLLOFF_WM
,
3201 PINEVIEW_FIFO_LINE_SIZE
3203 static struct intel_watermark_params pineview_cursor_wm
= {
3204 PINEVIEW_CURSOR_FIFO
,
3205 PINEVIEW_CURSOR_MAX_WM
,
3206 PINEVIEW_CURSOR_DFT_WM
,
3207 PINEVIEW_CURSOR_GUARD_WM
,
3208 PINEVIEW_FIFO_LINE_SIZE
,
3210 static struct intel_watermark_params pineview_cursor_hplloff_wm
= {
3211 PINEVIEW_CURSOR_FIFO
,
3212 PINEVIEW_CURSOR_MAX_WM
,
3213 PINEVIEW_CURSOR_DFT_WM
,
3214 PINEVIEW_CURSOR_GUARD_WM
,
3215 PINEVIEW_FIFO_LINE_SIZE
3217 static struct intel_watermark_params g4x_wm_info
= {
3224 static struct intel_watermark_params g4x_cursor_wm_info
= {
3231 static struct intel_watermark_params i965_cursor_wm_info
= {
3236 I915_FIFO_LINE_SIZE
,
3238 static struct intel_watermark_params i945_wm_info
= {
3245 static struct intel_watermark_params i915_wm_info
= {
3252 static struct intel_watermark_params i855_wm_info
= {
3259 static struct intel_watermark_params i830_wm_info
= {
3267 static struct intel_watermark_params ironlake_display_wm_info
= {
3275 static struct intel_watermark_params ironlake_cursor_wm_info
= {
3283 static struct intel_watermark_params ironlake_display_srwm_info
= {
3284 ILK_DISPLAY_SR_FIFO
,
3285 ILK_DISPLAY_MAX_SRWM
,
3286 ILK_DISPLAY_DFT_SRWM
,
3291 static struct intel_watermark_params ironlake_cursor_srwm_info
= {
3293 ILK_CURSOR_MAX_SRWM
,
3294 ILK_CURSOR_DFT_SRWM
,
3299 static struct intel_watermark_params sandybridge_display_wm_info
= {
3307 static struct intel_watermark_params sandybridge_cursor_wm_info
= {
3315 static struct intel_watermark_params sandybridge_display_srwm_info
= {
3316 SNB_DISPLAY_SR_FIFO
,
3317 SNB_DISPLAY_MAX_SRWM
,
3318 SNB_DISPLAY_DFT_SRWM
,
3323 static struct intel_watermark_params sandybridge_cursor_srwm_info
= {
3325 SNB_CURSOR_MAX_SRWM
,
3326 SNB_CURSOR_DFT_SRWM
,
3333 * intel_calculate_wm - calculate watermark level
3334 * @clock_in_khz: pixel clock
3335 * @wm: chip FIFO params
3336 * @pixel_size: display pixel size
3337 * @latency_ns: memory latency for the platform
3339 * Calculate the watermark level (the level at which the display plane will
3340 * start fetching from memory again). Each chip has a different display
3341 * FIFO size and allocation, so the caller needs to figure that out and pass
3342 * in the correct intel_watermark_params structure.
3344 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3345 * on the pixel size. When it reaches the watermark level, it'll start
3346 * fetching FIFO line sized based chunks from memory until the FIFO fills
3347 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3348 * will occur, and a display engine hang could result.
3350 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
3351 struct intel_watermark_params
*wm
,
3353 unsigned long latency_ns
)
3355 long entries_required
, wm_size
;
3358 * Note: we need to make sure we don't overflow for various clock &
3360 * clocks go from a few thousand to several hundred thousand.
3361 * latency is usually a few thousand
3363 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
3365 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
3367 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required
);
3369 wm_size
= wm
->fifo_size
- (entries_required
+ wm
->guard_size
);
3371 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size
);
3373 /* Don't promote wm_size to unsigned... */
3374 if (wm_size
> (long)wm
->max_wm
)
3375 wm_size
= wm
->max_wm
;
3377 wm_size
= wm
->default_wm
;
3381 struct cxsr_latency
{
3384 unsigned long fsb_freq
;
3385 unsigned long mem_freq
;
3386 unsigned long display_sr
;
3387 unsigned long display_hpll_disable
;
3388 unsigned long cursor_sr
;
3389 unsigned long cursor_hpll_disable
;
3392 static const struct cxsr_latency cxsr_latency_table
[] = {
3393 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3394 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3395 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3396 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3397 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3399 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3400 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3401 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3402 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3403 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3405 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3406 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3407 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3408 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3409 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3411 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3412 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3413 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3414 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3415 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3417 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3418 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3419 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3420 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3421 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3423 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3424 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3425 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3426 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3427 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3430 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
3435 const struct cxsr_latency
*latency
;
3438 if (fsb
== 0 || mem
== 0)
3441 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
3442 latency
= &cxsr_latency_table
[i
];
3443 if (is_desktop
== latency
->is_desktop
&&
3444 is_ddr3
== latency
->is_ddr3
&&
3445 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
3449 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3454 static void pineview_disable_cxsr(struct drm_device
*dev
)
3456 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3458 /* deactivate cxsr */
3459 I915_WRITE(DSPFW3
, I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
);
3463 * Latency for FIFO fetches is dependent on several factors:
3464 * - memory configuration (speed, channels)
3466 * - current MCH state
3467 * It can be fairly high in some situations, so here we assume a fairly
3468 * pessimal value. It's a tradeoff between extra memory fetches (if we
3469 * set this value too high, the FIFO will fetch frequently to stay full)
3470 * and power consumption (set it too low to save power and we might see
3471 * FIFO underruns and display "flicker").
3473 * A value of 5us seems to be a good balance; safe for very low end
3474 * platforms but not overly aggressive on lower latency configs.
3476 static const int latency_ns
= 5000;
3478 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
3480 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3481 uint32_t dsparb
= I915_READ(DSPARB
);
3484 size
= dsparb
& 0x7f;
3486 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
3488 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3489 plane
? "B" : "A", size
);
3494 static int i85x_get_fifo_size(struct drm_device
*dev
, int plane
)
3496 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3497 uint32_t dsparb
= I915_READ(DSPARB
);
3500 size
= dsparb
& 0x1ff;
3502 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
3503 size
>>= 1; /* Convert to cachelines */
3505 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3506 plane
? "B" : "A", size
);
3511 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
3513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3514 uint32_t dsparb
= I915_READ(DSPARB
);
3517 size
= dsparb
& 0x7f;
3518 size
>>= 2; /* Convert to cachelines */
3520 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3527 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
3529 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3530 uint32_t dsparb
= I915_READ(DSPARB
);
3533 size
= dsparb
& 0x7f;
3534 size
>>= 1; /* Convert to cachelines */
3536 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3537 plane
? "B" : "A", size
);
3542 static void pineview_update_wm(struct drm_device
*dev
, int planea_clock
,
3543 int planeb_clock
, int sr_hdisplay
, int unused
,
3546 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3547 const struct cxsr_latency
*latency
;
3552 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
3553 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
3555 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3556 pineview_disable_cxsr(dev
);
3560 if (!planea_clock
|| !planeb_clock
) {
3561 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3564 wm
= intel_calculate_wm(sr_clock
, &pineview_display_wm
,
3565 pixel_size
, latency
->display_sr
);
3566 reg
= I915_READ(DSPFW1
);
3567 reg
&= ~DSPFW_SR_MASK
;
3568 reg
|= wm
<< DSPFW_SR_SHIFT
;
3569 I915_WRITE(DSPFW1
, reg
);
3570 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
3573 wm
= intel_calculate_wm(sr_clock
, &pineview_cursor_wm
,
3574 pixel_size
, latency
->cursor_sr
);
3575 reg
= I915_READ(DSPFW3
);
3576 reg
&= ~DSPFW_CURSOR_SR_MASK
;
3577 reg
|= (wm
& 0x3f) << DSPFW_CURSOR_SR_SHIFT
;
3578 I915_WRITE(DSPFW3
, reg
);
3580 /* Display HPLL off SR */
3581 wm
= intel_calculate_wm(sr_clock
, &pineview_display_hplloff_wm
,
3582 pixel_size
, latency
->display_hpll_disable
);
3583 reg
= I915_READ(DSPFW3
);
3584 reg
&= ~DSPFW_HPLL_SR_MASK
;
3585 reg
|= wm
& DSPFW_HPLL_SR_MASK
;
3586 I915_WRITE(DSPFW3
, reg
);
3588 /* cursor HPLL off SR */
3589 wm
= intel_calculate_wm(sr_clock
, &pineview_cursor_hplloff_wm
,
3590 pixel_size
, latency
->cursor_hpll_disable
);
3591 reg
= I915_READ(DSPFW3
);
3592 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
3593 reg
|= (wm
& 0x3f) << DSPFW_HPLL_CURSOR_SHIFT
;
3594 I915_WRITE(DSPFW3
, reg
);
3595 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
3599 I915_READ(DSPFW3
) | PINEVIEW_SELF_REFRESH_EN
);
3600 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3602 pineview_disable_cxsr(dev
);
3603 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3607 static void g4x_update_wm(struct drm_device
*dev
, int planea_clock
,
3608 int planeb_clock
, int sr_hdisplay
, int sr_htotal
,
3611 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3612 int total_size
, cacheline_size
;
3613 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
, cursor_sr
;
3614 struct intel_watermark_params planea_params
, planeb_params
;
3615 unsigned long line_time_us
;
3616 int sr_clock
, sr_entries
= 0, entries_required
;
3618 /* Create copies of the base settings for each pipe */
3619 planea_params
= planeb_params
= g4x_wm_info
;
3621 /* Grab a couple of global values before we overwrite them */
3622 total_size
= planea_params
.fifo_size
;
3623 cacheline_size
= planea_params
.cacheline_size
;
3626 * Note: we need to make sure we don't overflow for various clock &
3628 * clocks go from a few thousand to several hundred thousand.
3629 * latency is usually a few thousand
3631 entries_required
= ((planea_clock
/ 1000) * pixel_size
* latency_ns
) /
3633 entries_required
= DIV_ROUND_UP(entries_required
, G4X_FIFO_LINE_SIZE
);
3634 planea_wm
= entries_required
+ planea_params
.guard_size
;
3636 entries_required
= ((planeb_clock
/ 1000) * pixel_size
* latency_ns
) /
3638 entries_required
= DIV_ROUND_UP(entries_required
, G4X_FIFO_LINE_SIZE
);
3639 planeb_wm
= entries_required
+ planeb_params
.guard_size
;
3641 cursora_wm
= cursorb_wm
= 16;
3644 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
3646 /* Calc sr entries for one plane configs */
3647 if (sr_hdisplay
&& (!planea_clock
|| !planeb_clock
)) {
3648 /* self-refresh has much higher latency */
3649 static const int sr_latency_ns
= 12000;
3651 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3652 line_time_us
= ((sr_htotal
* 1000) / sr_clock
);
3654 /* Use ns/us then divide to preserve precision */
3655 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3656 pixel_size
* sr_hdisplay
;
3657 sr_entries
= DIV_ROUND_UP(sr_entries
, cacheline_size
);
3659 entries_required
= (((sr_latency_ns
/ line_time_us
) +
3660 1000) / 1000) * pixel_size
* 64;
3661 entries_required
= DIV_ROUND_UP(entries_required
,
3662 g4x_cursor_wm_info
.cacheline_size
);
3663 cursor_sr
= entries_required
+ g4x_cursor_wm_info
.guard_size
;
3665 if (cursor_sr
> g4x_cursor_wm_info
.max_wm
)
3666 cursor_sr
= g4x_cursor_wm_info
.max_wm
;
3667 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3668 "cursor %d\n", sr_entries
, cursor_sr
);
3670 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
3672 /* Turn off self refresh if both pipes are enabled */
3673 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
3677 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3678 planea_wm
, planeb_wm
, sr_entries
);
3683 I915_WRITE(DSPFW1
, (sr_entries
<< DSPFW_SR_SHIFT
) |
3684 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
3685 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) | planea_wm
);
3686 I915_WRITE(DSPFW2
, (I915_READ(DSPFW2
) & DSPFW_CURSORA_MASK
) |
3687 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
3688 /* HPLL off in SR has some issues on G4x... disable it */
3689 I915_WRITE(DSPFW3
, (I915_READ(DSPFW3
) & ~DSPFW_HPLL_SR_EN
) |
3690 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
3693 static void i965_update_wm(struct drm_device
*dev
, int planea_clock
,
3694 int planeb_clock
, int sr_hdisplay
, int sr_htotal
,
3697 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3698 unsigned long line_time_us
;
3699 int sr_clock
, sr_entries
, srwm
= 1;
3702 /* Calc sr entries for one plane configs */
3703 if (sr_hdisplay
&& (!planea_clock
|| !planeb_clock
)) {
3704 /* self-refresh has much higher latency */
3705 static const int sr_latency_ns
= 12000;
3707 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3708 line_time_us
= ((sr_htotal
* 1000) / sr_clock
);
3710 /* Use ns/us then divide to preserve precision */
3711 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3712 pixel_size
* sr_hdisplay
;
3713 sr_entries
= DIV_ROUND_UP(sr_entries
, I915_FIFO_LINE_SIZE
);
3714 DRM_DEBUG("self-refresh entries: %d\n", sr_entries
);
3715 srwm
= I965_FIFO_SIZE
- sr_entries
;
3720 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3722 sr_entries
= DIV_ROUND_UP(sr_entries
,
3723 i965_cursor_wm_info
.cacheline_size
);
3724 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
3725 (sr_entries
+ i965_cursor_wm_info
.guard_size
);
3727 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
3728 cursor_sr
= i965_cursor_wm_info
.max_wm
;
3730 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3731 "cursor %d\n", srwm
, cursor_sr
);
3733 if (IS_CRESTLINE(dev
))
3734 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
3736 /* Turn off self refresh if both pipes are enabled */
3737 if (IS_CRESTLINE(dev
))
3738 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
3742 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3745 /* 965 has limitations... */
3746 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) | (8 << 16) | (8 << 8) |
3748 I915_WRITE(DSPFW2
, (8 << 8) | (8 << 0));
3749 /* update cursor SR watermark */
3750 I915_WRITE(DSPFW3
, (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
3753 static void i9xx_update_wm(struct drm_device
*dev
, int planea_clock
,
3754 int planeb_clock
, int sr_hdisplay
, int sr_htotal
,
3757 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3760 int total_size
, cacheline_size
, cwm
, srwm
= 1;
3761 int planea_wm
, planeb_wm
;
3762 struct intel_watermark_params planea_params
, planeb_params
;
3763 unsigned long line_time_us
;
3764 int sr_clock
, sr_entries
= 0, sr_enabled
= 0;
3766 /* Create copies of the base settings for each pipe */
3767 if (IS_CRESTLINE(dev
) || IS_I945GM(dev
))
3768 planea_params
= planeb_params
= i945_wm_info
;
3769 else if (!IS_GEN2(dev
))
3770 planea_params
= planeb_params
= i915_wm_info
;
3772 planea_params
= planeb_params
= i855_wm_info
;
3774 /* Grab a couple of global values before we overwrite them */
3775 total_size
= planea_params
.fifo_size
;
3776 cacheline_size
= planea_params
.cacheline_size
;
3778 /* Update per-plane FIFO sizes */
3779 planea_params
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
3780 planeb_params
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
3782 planea_wm
= intel_calculate_wm(planea_clock
, &planea_params
,
3783 pixel_size
, latency_ns
);
3784 planeb_wm
= intel_calculate_wm(planeb_clock
, &planeb_params
,
3785 pixel_size
, latency_ns
);
3786 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
3789 * Overlay gets an aggressive default since video jitter is bad.
3793 /* Play safe and disable self-refresh before adjusting watermarks. */
3794 if (IS_I945G(dev
) || IS_I945GM(dev
))
3795 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN_MASK
| 0);
3796 else if (IS_I915GM(dev
))
3797 I915_WRITE(INSTPM
, I915_READ(INSTPM
) & ~INSTPM_SELF_EN
);
3799 /* Calc sr entries for one plane configs */
3800 if (HAS_FW_BLC(dev
) && sr_hdisplay
&&
3801 (!planea_clock
|| !planeb_clock
)) {
3802 /* self-refresh has much higher latency */
3803 static const int sr_latency_ns
= 6000;
3805 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3806 line_time_us
= ((sr_htotal
* 1000) / sr_clock
);
3808 /* Use ns/us then divide to preserve precision */
3809 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3810 pixel_size
* sr_hdisplay
;
3811 sr_entries
= DIV_ROUND_UP(sr_entries
, cacheline_size
);
3812 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries
);
3813 srwm
= total_size
- sr_entries
;
3817 if (IS_I945G(dev
) || IS_I945GM(dev
))
3818 I915_WRITE(FW_BLC_SELF
,
3819 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
3820 else if (IS_I915GM(dev
))
3821 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
3826 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3827 planea_wm
, planeb_wm
, cwm
, srwm
);
3829 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
3830 fwater_hi
= (cwm
& 0x1f);
3832 /* Set request length to 8 cachelines per fetch */
3833 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
3834 fwater_hi
= fwater_hi
| (1 << 8);
3836 I915_WRITE(FW_BLC
, fwater_lo
);
3837 I915_WRITE(FW_BLC2
, fwater_hi
);
3840 if (IS_I945G(dev
) || IS_I945GM(dev
))
3841 I915_WRITE(FW_BLC_SELF
,
3842 FW_BLC_SELF_EN_MASK
| FW_BLC_SELF_EN
);
3843 else if (IS_I915GM(dev
))
3844 I915_WRITE(INSTPM
, I915_READ(INSTPM
) | INSTPM_SELF_EN
);
3845 DRM_DEBUG_KMS("memory self refresh enabled\n");
3847 DRM_DEBUG_KMS("memory self refresh disabled\n");
3850 static void i830_update_wm(struct drm_device
*dev
, int planea_clock
, int unused
,
3851 int unused2
, int unused3
, int pixel_size
)
3853 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3854 uint32_t fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
3857 i830_wm_info
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
3859 planea_wm
= intel_calculate_wm(planea_clock
, &i830_wm_info
,
3860 pixel_size
, latency_ns
);
3861 fwater_lo
|= (3<<8) | planea_wm
;
3863 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
3865 I915_WRITE(FW_BLC
, fwater_lo
);
3868 #define ILK_LP0_PLANE_LATENCY 700
3869 #define ILK_LP0_CURSOR_LATENCY 1300
3871 static bool ironlake_compute_wm0(struct drm_device
*dev
,
3873 const struct intel_watermark_params
*display
,
3874 int display_latency_ns
,
3875 const struct intel_watermark_params
*cursor
,
3876 int cursor_latency_ns
,
3880 struct drm_crtc
*crtc
;
3881 int htotal
, hdisplay
, clock
, pixel_size
;
3882 int line_time_us
, line_count
;
3883 int entries
, tlb_miss
;
3885 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
3886 if (crtc
->fb
== NULL
|| !crtc
->enabled
)
3889 htotal
= crtc
->mode
.htotal
;
3890 hdisplay
= crtc
->mode
.hdisplay
;
3891 clock
= crtc
->mode
.clock
;
3892 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
3894 /* Use the small buffer method to calculate plane watermark */
3895 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
3896 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
3898 entries
+= tlb_miss
;
3899 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
3900 *plane_wm
= entries
+ display
->guard_size
;
3901 if (*plane_wm
> (int)display
->max_wm
)
3902 *plane_wm
= display
->max_wm
;
3904 /* Use the large buffer method to calculate cursor watermark */
3905 line_time_us
= ((htotal
* 1000) / clock
);
3906 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
3907 entries
= line_count
* 64 * pixel_size
;
3908 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
3910 entries
+= tlb_miss
;
3911 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
3912 *cursor_wm
= entries
+ cursor
->guard_size
;
3913 if (*cursor_wm
> (int)cursor
->max_wm
)
3914 *cursor_wm
= (int)cursor
->max_wm
;
3920 * Check the wm result.
3922 * If any calculated watermark values is larger than the maximum value that
3923 * can be programmed into the associated watermark register, that watermark
3926 static bool ironlake_check_srwm(struct drm_device
*dev
, int level
,
3927 int fbc_wm
, int display_wm
, int cursor_wm
,
3928 const struct intel_watermark_params
*display
,
3929 const struct intel_watermark_params
*cursor
)
3931 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3933 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
3934 " cursor %d\n", level
, display_wm
, fbc_wm
, cursor_wm
);
3936 if (fbc_wm
> SNB_FBC_MAX_SRWM
) {
3937 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
3938 fbc_wm
, SNB_FBC_MAX_SRWM
, level
);
3940 /* fbc has it's own way to disable FBC WM */
3941 I915_WRITE(DISP_ARB_CTL
,
3942 I915_READ(DISP_ARB_CTL
) | DISP_FBC_WM_DIS
);
3946 if (display_wm
> display
->max_wm
) {
3947 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
3948 display_wm
, SNB_DISPLAY_MAX_SRWM
, level
);
3952 if (cursor_wm
> cursor
->max_wm
) {
3953 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
3954 cursor_wm
, SNB_CURSOR_MAX_SRWM
, level
);
3958 if (!(fbc_wm
|| display_wm
|| cursor_wm
)) {
3959 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level
, level
);
3967 * Compute watermark values of WM[1-3],
3969 static bool ironlake_compute_srwm(struct drm_device
*dev
, int level
,
3970 int hdisplay
, int htotal
,
3971 int pixel_size
, int clock
, int latency_ns
,
3972 const struct intel_watermark_params
*display
,
3973 const struct intel_watermark_params
*cursor
,
3974 int *fbc_wm
, int *display_wm
, int *cursor_wm
)
3977 unsigned long line_time_us
;
3978 int line_count
, line_size
;
3983 *fbc_wm
= *display_wm
= *cursor_wm
= 0;
3987 line_time_us
= (htotal
* 1000) / clock
;
3988 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
3989 line_size
= hdisplay
* pixel_size
;
3991 /* Use the minimum of the small and large buffer method for primary */
3992 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
3993 large
= line_count
* line_size
;
3995 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
3996 *display_wm
= entries
+ display
->guard_size
;
4000 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4002 *fbc_wm
= DIV_ROUND_UP(*display_wm
* 64, line_size
) + 2;
4004 /* calculate the self-refresh watermark for display cursor */
4005 entries
= line_count
* pixel_size
* 64;
4006 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
4007 *cursor_wm
= entries
+ cursor
->guard_size
;
4009 return ironlake_check_srwm(dev
, level
,
4010 *fbc_wm
, *display_wm
, *cursor_wm
,
4014 static void ironlake_update_wm(struct drm_device
*dev
,
4015 int planea_clock
, int planeb_clock
,
4016 int hdisplay
, int htotal
,
4019 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4020 int fbc_wm
, plane_wm
, cursor_wm
, enabled
;
4024 if (ironlake_compute_wm0(dev
, 0,
4025 &ironlake_display_wm_info
,
4026 ILK_LP0_PLANE_LATENCY
,
4027 &ironlake_cursor_wm_info
,
4028 ILK_LP0_CURSOR_LATENCY
,
4029 &plane_wm
, &cursor_wm
)) {
4030 I915_WRITE(WM0_PIPEA_ILK
,
4031 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
4032 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4033 " plane %d, " "cursor: %d\n",
4034 plane_wm
, cursor_wm
);
4038 if (ironlake_compute_wm0(dev
, 1,
4039 &ironlake_display_wm_info
,
4040 ILK_LP0_PLANE_LATENCY
,
4041 &ironlake_cursor_wm_info
,
4042 ILK_LP0_CURSOR_LATENCY
,
4043 &plane_wm
, &cursor_wm
)) {
4044 I915_WRITE(WM0_PIPEB_ILK
,
4045 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
4046 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4047 " plane %d, cursor: %d\n",
4048 plane_wm
, cursor_wm
);
4053 * Calculate and update the self-refresh watermark only when one
4054 * display plane is used.
4056 I915_WRITE(WM3_LP_ILK
, 0);
4057 I915_WRITE(WM2_LP_ILK
, 0);
4058 I915_WRITE(WM1_LP_ILK
, 0);
4063 clock
= planea_clock
? planea_clock
: planeb_clock
;
4066 if (!ironlake_compute_srwm(dev
, 1, hdisplay
, htotal
, pixel_size
,
4067 clock
, ILK_READ_WM1_LATENCY() * 500,
4068 &ironlake_display_srwm_info
,
4069 &ironlake_cursor_srwm_info
,
4070 &fbc_wm
, &plane_wm
, &cursor_wm
))
4073 I915_WRITE(WM1_LP_ILK
,
4075 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
4076 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
4077 (plane_wm
<< WM1_LP_SR_SHIFT
) |
4081 if (!ironlake_compute_srwm(dev
, 2, hdisplay
, htotal
, pixel_size
,
4082 clock
, ILK_READ_WM2_LATENCY() * 500,
4083 &ironlake_display_srwm_info
,
4084 &ironlake_cursor_srwm_info
,
4085 &fbc_wm
, &plane_wm
, &cursor_wm
))
4088 I915_WRITE(WM2_LP_ILK
,
4090 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
4091 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
4092 (plane_wm
<< WM1_LP_SR_SHIFT
) |
4096 * WM3 is unsupported on ILK, probably because we don't have latency
4097 * data for that power state
4101 static void sandybridge_update_wm(struct drm_device
*dev
,
4102 int planea_clock
, int planeb_clock
,
4103 int hdisplay
, int htotal
,
4106 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4107 int latency
= SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4108 int fbc_wm
, plane_wm
, cursor_wm
, enabled
;
4112 if (ironlake_compute_wm0(dev
, 0,
4113 &sandybridge_display_wm_info
, latency
,
4114 &sandybridge_cursor_wm_info
, latency
,
4115 &plane_wm
, &cursor_wm
)) {
4116 I915_WRITE(WM0_PIPEA_ILK
,
4117 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
4118 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4119 " plane %d, " "cursor: %d\n",
4120 plane_wm
, cursor_wm
);
4124 if (ironlake_compute_wm0(dev
, 1,
4125 &sandybridge_display_wm_info
, latency
,
4126 &sandybridge_cursor_wm_info
, latency
,
4127 &plane_wm
, &cursor_wm
)) {
4128 I915_WRITE(WM0_PIPEB_ILK
,
4129 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
4130 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4131 " plane %d, cursor: %d\n",
4132 plane_wm
, cursor_wm
);
4137 * Calculate and update the self-refresh watermark only when one
4138 * display plane is used.
4140 * SNB support 3 levels of watermark.
4142 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4143 * and disabled in the descending order
4146 I915_WRITE(WM3_LP_ILK
, 0);
4147 I915_WRITE(WM2_LP_ILK
, 0);
4148 I915_WRITE(WM1_LP_ILK
, 0);
4153 clock
= planea_clock
? planea_clock
: planeb_clock
;
4156 if (!ironlake_compute_srwm(dev
, 1, hdisplay
, htotal
, pixel_size
,
4157 clock
, SNB_READ_WM1_LATENCY() * 500,
4158 &sandybridge_display_srwm_info
,
4159 &sandybridge_cursor_srwm_info
,
4160 &fbc_wm
, &plane_wm
, &cursor_wm
))
4163 I915_WRITE(WM1_LP_ILK
,
4165 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
4166 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
4167 (plane_wm
<< WM1_LP_SR_SHIFT
) |
4171 if (!ironlake_compute_srwm(dev
, 2,
4172 hdisplay
, htotal
, pixel_size
,
4173 clock
, SNB_READ_WM2_LATENCY() * 500,
4174 &sandybridge_display_srwm_info
,
4175 &sandybridge_cursor_srwm_info
,
4176 &fbc_wm
, &plane_wm
, &cursor_wm
))
4179 I915_WRITE(WM2_LP_ILK
,
4181 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
4182 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
4183 (plane_wm
<< WM1_LP_SR_SHIFT
) |
4187 if (!ironlake_compute_srwm(dev
, 3,
4188 hdisplay
, htotal
, pixel_size
,
4189 clock
, SNB_READ_WM3_LATENCY() * 500,
4190 &sandybridge_display_srwm_info
,
4191 &sandybridge_cursor_srwm_info
,
4192 &fbc_wm
, &plane_wm
, &cursor_wm
))
4195 I915_WRITE(WM3_LP_ILK
,
4197 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
4198 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
4199 (plane_wm
<< WM1_LP_SR_SHIFT
) |
4204 * intel_update_watermarks - update FIFO watermark values based on current modes
4206 * Calculate watermark values for the various WM regs based on current mode
4207 * and plane configuration.
4209 * There are several cases to deal with here:
4210 * - normal (i.e. non-self-refresh)
4211 * - self-refresh (SR) mode
4212 * - lines are large relative to FIFO size (buffer can hold up to 2)
4213 * - lines are small relative to FIFO size (buffer can hold more than 2
4214 * lines), so need to account for TLB latency
4216 * The normal calculation is:
4217 * watermark = dotclock * bytes per pixel * latency
4218 * where latency is platform & configuration dependent (we assume pessimal
4221 * The SR calculation is:
4222 * watermark = (trunc(latency/line time)+1) * surface width *
4225 * line time = htotal / dotclock
4226 * surface width = hdisplay for normal plane and 64 for cursor
4227 * and latency is assumed to be high, as above.
4229 * The final value programmed to the register should always be rounded up,
4230 * and include an extra 2 entries to account for clock crossings.
4232 * We don't use the sprite, so we can ignore that. And on Crestline we have
4233 * to set the non-SR watermarks to 8.
4235 static void intel_update_watermarks(struct drm_device
*dev
)
4237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4238 struct drm_crtc
*crtc
;
4239 int sr_hdisplay
= 0;
4240 unsigned long planea_clock
= 0, planeb_clock
= 0, sr_clock
= 0;
4241 int enabled
= 0, pixel_size
= 0;
4244 if (!dev_priv
->display
.update_wm
)
4247 /* Get the clock config from both planes */
4248 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4249 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4250 if (intel_crtc
->active
) {
4252 if (intel_crtc
->plane
== 0) {
4253 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
4254 intel_crtc
->pipe
, crtc
->mode
.clock
);
4255 planea_clock
= crtc
->mode
.clock
;
4257 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
4258 intel_crtc
->pipe
, crtc
->mode
.clock
);
4259 planeb_clock
= crtc
->mode
.clock
;
4261 sr_hdisplay
= crtc
->mode
.hdisplay
;
4262 sr_clock
= crtc
->mode
.clock
;
4263 sr_htotal
= crtc
->mode
.htotal
;
4265 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
4267 pixel_size
= 4; /* by default */
4274 dev_priv
->display
.update_wm(dev
, planea_clock
, planeb_clock
,
4275 sr_hdisplay
, sr_htotal
, pixel_size
);
4278 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
4280 return dev_priv
->lvds_use_ssc
&& i915_panel_use_ssc
;
4283 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
4284 struct drm_display_mode
*mode
,
4285 struct drm_display_mode
*adjusted_mode
,
4287 struct drm_framebuffer
*old_fb
)
4289 struct drm_device
*dev
= crtc
->dev
;
4290 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4291 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4292 int pipe
= intel_crtc
->pipe
;
4293 int plane
= intel_crtc
->plane
;
4294 u32 fp_reg
, dpll_reg
;
4295 int refclk
, num_connectors
= 0;
4296 intel_clock_t clock
, reduced_clock
;
4297 u32 dpll
, fp
= 0, fp2
= 0, dspcntr
, pipeconf
;
4298 bool ok
, has_reduced_clock
= false, is_sdvo
= false, is_dvo
= false;
4299 bool is_crt
= false, is_lvds
= false, is_tv
= false, is_dp
= false;
4300 struct intel_encoder
*has_edp_encoder
= NULL
;
4301 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4302 struct intel_encoder
*encoder
;
4303 const intel_limit_t
*limit
;
4305 struct fdi_m_n m_n
= {0};
4310 drm_vblank_pre_modeset(dev
, pipe
);
4312 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
4313 if (encoder
->base
.crtc
!= crtc
)
4316 switch (encoder
->type
) {
4317 case INTEL_OUTPUT_LVDS
:
4320 case INTEL_OUTPUT_SDVO
:
4321 case INTEL_OUTPUT_HDMI
:
4323 if (encoder
->needs_tv_clock
)
4326 case INTEL_OUTPUT_DVO
:
4329 case INTEL_OUTPUT_TVOUT
:
4332 case INTEL_OUTPUT_ANALOG
:
4335 case INTEL_OUTPUT_DISPLAYPORT
:
4338 case INTEL_OUTPUT_EDP
:
4339 has_edp_encoder
= encoder
;
4346 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4347 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
4348 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4350 } else if (!IS_GEN2(dev
)) {
4352 if (HAS_PCH_SPLIT(dev
) &&
4353 (!has_edp_encoder
|| intel_encoder_is_pch_edp(&has_edp_encoder
->base
)))
4354 refclk
= 120000; /* 120Mhz refclk */
4360 * Returns a set of divisors for the desired target clock with the given
4361 * refclk, or FALSE. The returned values represent the clock equation:
4362 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4364 limit
= intel_limit(crtc
, refclk
);
4365 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, &clock
);
4367 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4368 drm_vblank_post_modeset(dev
, pipe
);
4372 /* Ensure that the cursor is valid for the new mode before changing... */
4373 intel_crtc_update_cursor(crtc
, true);
4375 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4376 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4377 dev_priv
->lvds_downclock
,
4380 if (has_reduced_clock
&& (clock
.p
!= reduced_clock
.p
)) {
4382 * If the different P is found, it means that we can't
4383 * switch the display clock by using the FP0/FP1.
4384 * In such case we will disable the LVDS downclock
4387 DRM_DEBUG_KMS("Different P is found for "
4388 "LVDS clock/downclock\n");
4389 has_reduced_clock
= 0;
4392 /* SDVO TV has fixed PLL values depend on its clock range,
4393 this mirrors vbios setting. */
4394 if (is_sdvo
&& is_tv
) {
4395 if (adjusted_mode
->clock
>= 100000
4396 && adjusted_mode
->clock
< 140500) {
4402 } else if (adjusted_mode
->clock
>= 140500
4403 && adjusted_mode
->clock
<= 200000) {
4413 if (HAS_PCH_SPLIT(dev
)) {
4414 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4415 int lane
= 0, link_bw
, bpp
;
4416 /* CPU eDP doesn't require FDI link, so just set DP M/N
4417 according to current link config */
4418 if (has_edp_encoder
&& !intel_encoder_is_pch_edp(&has_edp_encoder
->base
)) {
4419 target_clock
= mode
->clock
;
4420 intel_edp_link_config(has_edp_encoder
,
4423 /* [e]DP over FDI requires target mode clock
4424 instead of link clock */
4425 if (is_dp
|| intel_encoder_is_pch_edp(&has_edp_encoder
->base
))
4426 target_clock
= mode
->clock
;
4428 target_clock
= adjusted_mode
->clock
;
4430 /* FDI is a binary signal running at ~2.7GHz, encoding
4431 * each output octet as 10 bits. The actual frequency
4432 * is stored as a divider into a 100MHz clock, and the
4433 * mode pixel clock is stored in units of 1KHz.
4434 * Hence the bw of each lane in terms of the mode signal
4437 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
4440 /* determine panel color depth */
4441 temp
= I915_READ(PIPECONF(pipe
));
4442 temp
&= ~PIPE_BPC_MASK
;
4444 /* the BPC will be 6 if it is 18-bit LVDS panel */
4445 if ((I915_READ(PCH_LVDS
) & LVDS_A3_POWER_MASK
) == LVDS_A3_POWER_UP
)
4449 } else if (has_edp_encoder
) {
4450 switch (dev_priv
->edp
.bpp
/3) {
4466 I915_WRITE(PIPECONF(pipe
), temp
);
4468 switch (temp
& PIPE_BPC_MASK
) {
4482 DRM_ERROR("unknown pipe bpc value\n");
4488 * Account for spread spectrum to avoid
4489 * oversubscribing the link. Max center spread
4490 * is 2.5%; use 5% for safety's sake.
4492 u32 bps
= target_clock
* bpp
* 21 / 20;
4493 lane
= bps
/ (link_bw
* 8) + 1;
4496 intel_crtc
->fdi_lanes
= lane
;
4498 if (pixel_multiplier
> 1)
4499 link_bw
*= pixel_multiplier
;
4500 ironlake_compute_m_n(bpp
, lane
, target_clock
, link_bw
, &m_n
);
4503 /* Ironlake: try to setup display ref clock before DPLL
4504 * enabling. This is only under driver's control after
4505 * PCH B stepping, previous chipset stepping should be
4506 * ignoring this setting.
4508 if (HAS_PCH_SPLIT(dev
)) {
4509 temp
= I915_READ(PCH_DREF_CONTROL
);
4510 /* Always enable nonspread source */
4511 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
4512 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
4513 temp
&= ~DREF_SSC_SOURCE_MASK
;
4514 temp
|= DREF_SSC_SOURCE_ENABLE
;
4515 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4517 POSTING_READ(PCH_DREF_CONTROL
);
4520 if (has_edp_encoder
) {
4521 if (intel_panel_use_ssc(dev_priv
)) {
4522 temp
|= DREF_SSC1_ENABLE
;
4523 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4525 POSTING_READ(PCH_DREF_CONTROL
);
4528 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4530 /* Enable CPU source on CPU attached eDP */
4531 if (!intel_encoder_is_pch_edp(&has_edp_encoder
->base
)) {
4532 if (intel_panel_use_ssc(dev_priv
))
4533 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
4535 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
4537 /* Enable SSC on PCH eDP if needed */
4538 if (intel_panel_use_ssc(dev_priv
)) {
4539 DRM_ERROR("enabling SSC on PCH\n");
4540 temp
|= DREF_SUPERSPREAD_SOURCE_ENABLE
;
4543 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4544 POSTING_READ(PCH_DREF_CONTROL
);
4549 if (IS_PINEVIEW(dev
)) {
4550 fp
= (1 << clock
.n
) << 16 | clock
.m1
<< 8 | clock
.m2
;
4551 if (has_reduced_clock
)
4552 fp2
= (1 << reduced_clock
.n
) << 16 |
4553 reduced_clock
.m1
<< 8 | reduced_clock
.m2
;
4555 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
4556 if (has_reduced_clock
)
4557 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
4561 /* Enable autotuning of the PLL clock (if permissible) */
4562 if (HAS_PCH_SPLIT(dev
)) {
4566 if ((intel_panel_use_ssc(dev_priv
) &&
4567 dev_priv
->lvds_ssc_freq
== 100) ||
4568 (I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) == LVDS_CLKB_POWER_UP
)
4570 } else if (is_sdvo
&& is_tv
)
4573 if (clock
.m1
< factor
* clock
.n
)
4578 if (!HAS_PCH_SPLIT(dev
))
4579 dpll
= DPLL_VGA_MODE_DIS
;
4581 if (!IS_GEN2(dev
)) {
4583 dpll
|= DPLLB_MODE_LVDS
;
4585 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4587 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4588 if (pixel_multiplier
> 1) {
4589 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4590 dpll
|= (pixel_multiplier
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
4591 else if (HAS_PCH_SPLIT(dev
))
4592 dpll
|= (pixel_multiplier
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
4594 dpll
|= DPLL_DVO_HIGH_SPEED
;
4596 if (is_dp
|| intel_encoder_is_pch_edp(&has_edp_encoder
->base
))
4597 dpll
|= DPLL_DVO_HIGH_SPEED
;
4599 /* compute bitmask from p1 value */
4600 if (IS_PINEVIEW(dev
))
4601 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4603 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4605 if (HAS_PCH_SPLIT(dev
))
4606 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4607 if (IS_G4X(dev
) && has_reduced_clock
)
4608 dpll
|= (1 << (reduced_clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4612 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4615 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4618 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4621 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4624 if (INTEL_INFO(dev
)->gen
>= 4 && !HAS_PCH_SPLIT(dev
))
4625 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4628 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4631 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4633 dpll
|= (clock
.p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4635 dpll
|= PLL_P2_DIVIDE_BY_4
;
4639 if (is_sdvo
&& is_tv
)
4640 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4642 /* XXX: just matching BIOS for now */
4643 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4645 else if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4646 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4648 dpll
|= PLL_REF_INPUT_DREFCLK
;
4650 /* setup pipeconf */
4651 pipeconf
= I915_READ(PIPECONF(pipe
));
4653 /* Set up the display plane register */
4654 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4656 /* Ironlake's plane is forced to pipe, bit 24 is to
4657 enable color space conversion */
4658 if (!HAS_PCH_SPLIT(dev
)) {
4660 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4662 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4665 if (pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
4666 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4669 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4673 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
4674 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4676 pipeconf
&= ~PIPECONF_DOUBLE_WIDE
;
4679 if (!HAS_PCH_SPLIT(dev
))
4680 dpll
|= DPLL_VCO_ENABLE
;
4682 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
4683 drm_mode_debug_printmodeline(mode
);
4685 /* assign to Ironlake registers */
4686 if (HAS_PCH_SPLIT(dev
)) {
4687 fp_reg
= PCH_FP0(pipe
);
4688 dpll_reg
= PCH_DPLL(pipe
);
4691 dpll_reg
= DPLL(pipe
);
4694 /* PCH eDP needs FDI, but CPU eDP does not */
4695 if (!has_edp_encoder
|| intel_encoder_is_pch_edp(&has_edp_encoder
->base
)) {
4696 I915_WRITE(fp_reg
, fp
);
4697 I915_WRITE(dpll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
4699 POSTING_READ(dpll_reg
);
4703 /* enable transcoder DPLL */
4704 if (HAS_PCH_CPT(dev
)) {
4705 temp
= I915_READ(PCH_DPLL_SEL
);
4707 temp
|= TRANSA_DPLL_ENABLE
| TRANSA_DPLLA_SEL
;
4709 temp
|= TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
;
4710 I915_WRITE(PCH_DPLL_SEL
, temp
);
4712 POSTING_READ(PCH_DPLL_SEL
);
4716 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4717 * This is an exception to the general rule that mode_set doesn't turn
4722 if (HAS_PCH_SPLIT(dev
))
4725 temp
= I915_READ(reg
);
4726 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
4728 if (HAS_PCH_CPT(dev
))
4729 temp
|= PORT_TRANS_B_SEL_CPT
;
4731 temp
|= LVDS_PIPEB_SELECT
;
4733 if (HAS_PCH_CPT(dev
))
4734 temp
&= ~PORT_TRANS_SEL_MASK
;
4736 temp
&= ~LVDS_PIPEB_SELECT
;
4738 /* set the corresponsding LVDS_BORDER bit */
4739 temp
|= dev_priv
->lvds_border_bits
;
4740 /* Set the B0-B3 data pairs corresponding to whether we're going to
4741 * set the DPLLs for dual-channel mode or not.
4744 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
4746 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
4748 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4749 * appropriately here, but we need to look more thoroughly into how
4750 * panels behave in the two modes.
4752 /* set the dithering flag on non-PCH LVDS as needed */
4753 if (INTEL_INFO(dev
)->gen
>= 4 && !HAS_PCH_SPLIT(dev
)) {
4754 if (dev_priv
->lvds_dither
)
4755 temp
|= LVDS_ENABLE_DITHER
;
4757 temp
&= ~LVDS_ENABLE_DITHER
;
4759 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
4760 lvds_sync
|= LVDS_HSYNC_POLARITY
;
4761 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
4762 lvds_sync
|= LVDS_VSYNC_POLARITY
;
4763 if ((temp
& (LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
))
4765 char flags
[2] = "-+";
4766 DRM_INFO("Changing LVDS panel from "
4767 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4768 flags
[!(temp
& LVDS_HSYNC_POLARITY
)],
4769 flags
[!(temp
& LVDS_VSYNC_POLARITY
)],
4770 flags
[!(lvds_sync
& LVDS_HSYNC_POLARITY
)],
4771 flags
[!(lvds_sync
& LVDS_VSYNC_POLARITY
)]);
4772 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
4775 I915_WRITE(reg
, temp
);
4778 /* set the dithering flag and clear for anything other than a panel. */
4779 if (HAS_PCH_SPLIT(dev
)) {
4780 pipeconf
&= ~PIPECONF_DITHER_EN
;
4781 pipeconf
&= ~PIPECONF_DITHER_TYPE_MASK
;
4782 if (dev_priv
->lvds_dither
&& (is_lvds
|| has_edp_encoder
)) {
4783 pipeconf
|= PIPECONF_DITHER_EN
;
4784 pipeconf
|= PIPECONF_DITHER_TYPE_ST1
;
4788 if (is_dp
|| intel_encoder_is_pch_edp(&has_edp_encoder
->base
)) {
4789 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4790 } else if (HAS_PCH_SPLIT(dev
)) {
4791 /* For non-DP output, clear any trans DP clock recovery setting.*/
4793 I915_WRITE(TRANSA_DATA_M1
, 0);
4794 I915_WRITE(TRANSA_DATA_N1
, 0);
4795 I915_WRITE(TRANSA_DP_LINK_M1
, 0);
4796 I915_WRITE(TRANSA_DP_LINK_N1
, 0);
4798 I915_WRITE(TRANSB_DATA_M1
, 0);
4799 I915_WRITE(TRANSB_DATA_N1
, 0);
4800 I915_WRITE(TRANSB_DP_LINK_M1
, 0);
4801 I915_WRITE(TRANSB_DP_LINK_N1
, 0);
4805 if (!has_edp_encoder
|| intel_encoder_is_pch_edp(&has_edp_encoder
->base
)) {
4806 I915_WRITE(dpll_reg
, dpll
);
4808 /* Wait for the clocks to stabilize. */
4809 POSTING_READ(dpll_reg
);
4812 if (INTEL_INFO(dev
)->gen
>= 4 && !HAS_PCH_SPLIT(dev
)) {
4815 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4817 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4821 I915_WRITE(DPLL_MD(pipe
), temp
);
4823 /* The pixel multiplier can only be updated once the
4824 * DPLL is enabled and the clocks are stable.
4826 * So write it again.
4828 I915_WRITE(dpll_reg
, dpll
);
4832 intel_crtc
->lowfreq_avail
= false;
4833 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
4834 I915_WRITE(fp_reg
+ 4, fp2
);
4835 intel_crtc
->lowfreq_avail
= true;
4836 if (HAS_PIPE_CXSR(dev
)) {
4837 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4838 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4841 I915_WRITE(fp_reg
+ 4, fp
);
4842 if (HAS_PIPE_CXSR(dev
)) {
4843 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4844 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
4848 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4849 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4850 /* the chip adds 2 halflines automatically */
4851 adjusted_mode
->crtc_vdisplay
-= 1;
4852 adjusted_mode
->crtc_vtotal
-= 1;
4853 adjusted_mode
->crtc_vblank_start
-= 1;
4854 adjusted_mode
->crtc_vblank_end
-= 1;
4855 adjusted_mode
->crtc_vsync_end
-= 1;
4856 adjusted_mode
->crtc_vsync_start
-= 1;
4858 pipeconf
&= ~PIPECONF_INTERLACE_W_FIELD_INDICATION
; /* progressive */
4860 I915_WRITE(HTOTAL(pipe
),
4861 (adjusted_mode
->crtc_hdisplay
- 1) |
4862 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4863 I915_WRITE(HBLANK(pipe
),
4864 (adjusted_mode
->crtc_hblank_start
- 1) |
4865 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4866 I915_WRITE(HSYNC(pipe
),
4867 (adjusted_mode
->crtc_hsync_start
- 1) |
4868 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4870 I915_WRITE(VTOTAL(pipe
),
4871 (adjusted_mode
->crtc_vdisplay
- 1) |
4872 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4873 I915_WRITE(VBLANK(pipe
),
4874 (adjusted_mode
->crtc_vblank_start
- 1) |
4875 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4876 I915_WRITE(VSYNC(pipe
),
4877 (adjusted_mode
->crtc_vsync_start
- 1) |
4878 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4880 /* pipesrc and dspsize control the size that is scaled from,
4881 * which should always be the user's requested size.
4883 if (!HAS_PCH_SPLIT(dev
)) {
4884 I915_WRITE(DSPSIZE(plane
),
4885 ((mode
->vdisplay
- 1) << 16) |
4886 (mode
->hdisplay
- 1));
4887 I915_WRITE(DSPPOS(plane
), 0);
4889 I915_WRITE(PIPESRC(pipe
),
4890 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4892 if (HAS_PCH_SPLIT(dev
)) {
4893 I915_WRITE(PIPE_DATA_M1(pipe
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
4894 I915_WRITE(PIPE_DATA_N1(pipe
), m_n
.gmch_n
);
4895 I915_WRITE(PIPE_LINK_M1(pipe
), m_n
.link_m
);
4896 I915_WRITE(PIPE_LINK_N1(pipe
), m_n
.link_n
);
4898 if (has_edp_encoder
&& !intel_encoder_is_pch_edp(&has_edp_encoder
->base
)) {
4899 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
4903 I915_WRITE(PIPECONF(pipe
), pipeconf
);
4904 POSTING_READ(PIPECONF(pipe
));
4905 if (!HAS_PCH_SPLIT(dev
))
4906 intel_enable_pipe(dev_priv
, pipe
, false);
4908 intel_wait_for_vblank(dev
, pipe
);
4911 /* enable address swizzle for tiling buffer */
4912 temp
= I915_READ(DISP_ARB_CTL
);
4913 I915_WRITE(DISP_ARB_CTL
, temp
| DISP_TILE_SURFACE_SWIZZLING
);
4916 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4917 POSTING_READ(DSPCNTR(plane
));
4918 if (!HAS_PCH_SPLIT(dev
))
4919 intel_enable_plane(dev_priv
, plane
, pipe
);
4921 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
4923 intel_update_watermarks(dev
);
4925 drm_vblank_post_modeset(dev
, pipe
);
4930 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4931 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
4933 struct drm_device
*dev
= crtc
->dev
;
4934 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4935 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4936 int palreg
= (intel_crtc
->pipe
== 0) ? PALETTE_A
: PALETTE_B
;
4939 /* The clocks have to be on to load the palette. */
4943 /* use legacy palette for Ironlake */
4944 if (HAS_PCH_SPLIT(dev
))
4945 palreg
= (intel_crtc
->pipe
== 0) ? LGC_PALETTE_A
:
4948 for (i
= 0; i
< 256; i
++) {
4949 I915_WRITE(palreg
+ 4 * i
,
4950 (intel_crtc
->lut_r
[i
] << 16) |
4951 (intel_crtc
->lut_g
[i
] << 8) |
4952 intel_crtc
->lut_b
[i
]);
4956 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
4958 struct drm_device
*dev
= crtc
->dev
;
4959 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4960 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4961 bool visible
= base
!= 0;
4964 if (intel_crtc
->cursor_visible
== visible
)
4967 cntl
= I915_READ(CURACNTR
);
4969 /* On these chipsets we can only modify the base whilst
4970 * the cursor is disabled.
4972 I915_WRITE(CURABASE
, base
);
4974 cntl
&= ~(CURSOR_FORMAT_MASK
);
4975 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4976 cntl
|= CURSOR_ENABLE
|
4977 CURSOR_GAMMA_ENABLE
|
4980 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
4981 I915_WRITE(CURACNTR
, cntl
);
4983 intel_crtc
->cursor_visible
= visible
;
4986 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
4988 struct drm_device
*dev
= crtc
->dev
;
4989 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4990 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4991 int pipe
= intel_crtc
->pipe
;
4992 bool visible
= base
!= 0;
4994 if (intel_crtc
->cursor_visible
!= visible
) {
4995 uint32_t cntl
= I915_READ(pipe
== 0 ? CURACNTR
: CURBCNTR
);
4997 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
4998 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
4999 cntl
|= pipe
<< 28; /* Connect to correct pipe */
5001 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
5002 cntl
|= CURSOR_MODE_DISABLE
;
5004 I915_WRITE(pipe
== 0 ? CURACNTR
: CURBCNTR
, cntl
);
5006 intel_crtc
->cursor_visible
= visible
;
5008 /* and commit changes on next vblank */
5009 I915_WRITE(pipe
== 0 ? CURABASE
: CURBBASE
, base
);
5012 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5013 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
5016 struct drm_device
*dev
= crtc
->dev
;
5017 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5018 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5019 int pipe
= intel_crtc
->pipe
;
5020 int x
= intel_crtc
->cursor_x
;
5021 int y
= intel_crtc
->cursor_y
;
5027 if (on
&& crtc
->enabled
&& crtc
->fb
) {
5028 base
= intel_crtc
->cursor_addr
;
5029 if (x
> (int) crtc
->fb
->width
)
5032 if (y
> (int) crtc
->fb
->height
)
5038 if (x
+ intel_crtc
->cursor_width
< 0)
5041 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
5044 pos
|= x
<< CURSOR_X_SHIFT
;
5047 if (y
+ intel_crtc
->cursor_height
< 0)
5050 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
5053 pos
|= y
<< CURSOR_Y_SHIFT
;
5055 visible
= base
!= 0;
5056 if (!visible
&& !intel_crtc
->cursor_visible
)
5059 I915_WRITE(pipe
== 0 ? CURAPOS
: CURBPOS
, pos
);
5060 if (IS_845G(dev
) || IS_I865G(dev
))
5061 i845_update_cursor(crtc
, base
);
5063 i9xx_update_cursor(crtc
, base
);
5066 intel_mark_busy(dev
, to_intel_framebuffer(crtc
->fb
)->obj
);
5069 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
5070 struct drm_file
*file
,
5072 uint32_t width
, uint32_t height
)
5074 struct drm_device
*dev
= crtc
->dev
;
5075 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5076 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5077 struct drm_i915_gem_object
*obj
;
5081 DRM_DEBUG_KMS("\n");
5083 /* if we want to turn off the cursor ignore width and height */
5085 DRM_DEBUG_KMS("cursor off\n");
5088 mutex_lock(&dev
->struct_mutex
);
5092 /* Currently we only support 64x64 cursors */
5093 if (width
!= 64 || height
!= 64) {
5094 DRM_ERROR("we currently only support 64x64 cursors\n");
5098 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
5102 if (obj
->base
.size
< width
* height
* 4) {
5103 DRM_ERROR("buffer is to small\n");
5108 /* we only need to pin inside GTT if cursor is non-phy */
5109 mutex_lock(&dev
->struct_mutex
);
5110 if (!dev_priv
->info
->cursor_needs_physical
) {
5111 if (obj
->tiling_mode
) {
5112 DRM_ERROR("cursor cannot be tiled\n");
5117 ret
= i915_gem_object_pin(obj
, PAGE_SIZE
, true);
5119 DRM_ERROR("failed to pin cursor bo\n");
5123 ret
= i915_gem_object_set_to_gtt_domain(obj
, 0);
5125 DRM_ERROR("failed to move cursor bo into the GTT\n");
5129 ret
= i915_gem_object_put_fence(obj
);
5131 DRM_ERROR("failed to move cursor bo into the GTT\n");
5135 addr
= obj
->gtt_offset
;
5137 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
5138 ret
= i915_gem_attach_phys_object(dev
, obj
,
5139 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
5142 DRM_ERROR("failed to attach phys object\n");
5145 addr
= obj
->phys_obj
->handle
->busaddr
;
5149 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
5152 if (intel_crtc
->cursor_bo
) {
5153 if (dev_priv
->info
->cursor_needs_physical
) {
5154 if (intel_crtc
->cursor_bo
!= obj
)
5155 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
5157 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
5158 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
5161 mutex_unlock(&dev
->struct_mutex
);
5163 intel_crtc
->cursor_addr
= addr
;
5164 intel_crtc
->cursor_bo
= obj
;
5165 intel_crtc
->cursor_width
= width
;
5166 intel_crtc
->cursor_height
= height
;
5168 intel_crtc_update_cursor(crtc
, true);
5172 i915_gem_object_unpin(obj
);
5174 mutex_unlock(&dev
->struct_mutex
);
5176 drm_gem_object_unreference_unlocked(&obj
->base
);
5180 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
5182 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5184 intel_crtc
->cursor_x
= x
;
5185 intel_crtc
->cursor_y
= y
;
5187 intel_crtc_update_cursor(crtc
, true);
5192 /** Sets the color ramps on behalf of RandR */
5193 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
5194 u16 blue
, int regno
)
5196 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5198 intel_crtc
->lut_r
[regno
] = red
>> 8;
5199 intel_crtc
->lut_g
[regno
] = green
>> 8;
5200 intel_crtc
->lut_b
[regno
] = blue
>> 8;
5203 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
5204 u16
*blue
, int regno
)
5206 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5208 *red
= intel_crtc
->lut_r
[regno
] << 8;
5209 *green
= intel_crtc
->lut_g
[regno
] << 8;
5210 *blue
= intel_crtc
->lut_b
[regno
] << 8;
5213 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
5214 u16
*blue
, uint32_t start
, uint32_t size
)
5216 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
5217 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5219 for (i
= start
; i
< end
; i
++) {
5220 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
5221 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
5222 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
5225 intel_crtc_load_lut(crtc
);
5229 * Get a pipe with a simple mode set on it for doing load-based monitor
5232 * It will be up to the load-detect code to adjust the pipe as appropriate for
5233 * its requirements. The pipe will be connected to no other encoders.
5235 * Currently this code will only succeed if there is a pipe with no encoders
5236 * configured for it. In the future, it could choose to temporarily disable
5237 * some outputs to free up a pipe for its use.
5239 * \return crtc, or NULL if no pipes are available.
5242 /* VESA 640x480x72Hz mode to set on the pipe */
5243 static struct drm_display_mode load_detect_mode
= {
5244 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
5245 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
5248 struct drm_crtc
*intel_get_load_detect_pipe(struct intel_encoder
*intel_encoder
,
5249 struct drm_connector
*connector
,
5250 struct drm_display_mode
*mode
,
5253 struct intel_crtc
*intel_crtc
;
5254 struct drm_crtc
*possible_crtc
;
5255 struct drm_crtc
*supported_crtc
=NULL
;
5256 struct drm_encoder
*encoder
= &intel_encoder
->base
;
5257 struct drm_crtc
*crtc
= NULL
;
5258 struct drm_device
*dev
= encoder
->dev
;
5259 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
5260 struct drm_crtc_helper_funcs
*crtc_funcs
;
5264 * Algorithm gets a little messy:
5265 * - if the connector already has an assigned crtc, use it (but make
5266 * sure it's on first)
5267 * - try to find the first unused crtc that can drive this connector,
5268 * and use that if we find one
5269 * - if there are no unused crtcs available, try to use the first
5270 * one we found that supports the connector
5273 /* See if we already have a CRTC for this connector */
5274 if (encoder
->crtc
) {
5275 crtc
= encoder
->crtc
;
5276 /* Make sure the crtc and connector are running */
5277 intel_crtc
= to_intel_crtc(crtc
);
5278 *dpms_mode
= intel_crtc
->dpms_mode
;
5279 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
5280 crtc_funcs
= crtc
->helper_private
;
5281 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
5282 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
5287 /* Find an unused one (if possible) */
5288 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
5290 if (!(encoder
->possible_crtcs
& (1 << i
)))
5292 if (!possible_crtc
->enabled
) {
5293 crtc
= possible_crtc
;
5296 if (!supported_crtc
)
5297 supported_crtc
= possible_crtc
;
5301 * If we didn't find an unused CRTC, don't use any.
5307 encoder
->crtc
= crtc
;
5308 connector
->encoder
= encoder
;
5309 intel_encoder
->load_detect_temp
= true;
5311 intel_crtc
= to_intel_crtc(crtc
);
5312 *dpms_mode
= intel_crtc
->dpms_mode
;
5314 if (!crtc
->enabled
) {
5316 mode
= &load_detect_mode
;
5317 drm_crtc_helper_set_mode(crtc
, mode
, 0, 0, crtc
->fb
);
5319 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
5320 crtc_funcs
= crtc
->helper_private
;
5321 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
5324 /* Add this connector to the crtc */
5325 encoder_funcs
->mode_set(encoder
, &crtc
->mode
, &crtc
->mode
);
5326 encoder_funcs
->commit(encoder
);
5328 /* let the connector get through one full cycle before testing */
5329 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
5334 void intel_release_load_detect_pipe(struct intel_encoder
*intel_encoder
,
5335 struct drm_connector
*connector
, int dpms_mode
)
5337 struct drm_encoder
*encoder
= &intel_encoder
->base
;
5338 struct drm_device
*dev
= encoder
->dev
;
5339 struct drm_crtc
*crtc
= encoder
->crtc
;
5340 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
5341 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
5343 if (intel_encoder
->load_detect_temp
) {
5344 encoder
->crtc
= NULL
;
5345 connector
->encoder
= NULL
;
5346 intel_encoder
->load_detect_temp
= false;
5347 crtc
->enabled
= drm_helper_crtc_in_use(crtc
);
5348 drm_helper_disable_unused_functions(dev
);
5351 /* Switch crtc and encoder back off if necessary */
5352 if (crtc
->enabled
&& dpms_mode
!= DRM_MODE_DPMS_ON
) {
5353 if (encoder
->crtc
== crtc
)
5354 encoder_funcs
->dpms(encoder
, dpms_mode
);
5355 crtc_funcs
->dpms(crtc
, dpms_mode
);
5359 /* Returns the clock of the currently programmed mode of the given pipe. */
5360 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
5362 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5363 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5364 int pipe
= intel_crtc
->pipe
;
5365 u32 dpll
= I915_READ((pipe
== 0) ? DPLL_A
: DPLL_B
);
5367 intel_clock_t clock
;
5369 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
5370 fp
= I915_READ((pipe
== 0) ? FPA0
: FPB0
);
5372 fp
= I915_READ((pipe
== 0) ? FPA1
: FPB1
);
5374 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
5375 if (IS_PINEVIEW(dev
)) {
5376 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
5377 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
5379 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
5380 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
5383 if (!IS_GEN2(dev
)) {
5384 if (IS_PINEVIEW(dev
))
5385 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
5386 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
5388 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
5389 DPLL_FPA01_P1_POST_DIV_SHIFT
);
5391 switch (dpll
& DPLL_MODE_MASK
) {
5392 case DPLLB_MODE_DAC_SERIAL
:
5393 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
5396 case DPLLB_MODE_LVDS
:
5397 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
5401 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5402 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
5406 /* XXX: Handle the 100Mhz refclk */
5407 intel_clock(dev
, 96000, &clock
);
5409 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
5412 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
5413 DPLL_FPA01_P1_POST_DIV_SHIFT
);
5416 if ((dpll
& PLL_REF_INPUT_MASK
) ==
5417 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
5418 /* XXX: might not be 66MHz */
5419 intel_clock(dev
, 66000, &clock
);
5421 intel_clock(dev
, 48000, &clock
);
5423 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
5426 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
5427 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
5429 if (dpll
& PLL_P2_DIVIDE_BY_4
)
5434 intel_clock(dev
, 48000, &clock
);
5438 /* XXX: It would be nice to validate the clocks, but we can't reuse
5439 * i830PllIsValid() because it relies on the xf86_config connector
5440 * configuration being accurate, which it isn't necessarily.
5446 /** Returns the currently programmed mode of the given pipe. */
5447 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
5448 struct drm_crtc
*crtc
)
5450 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5451 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5452 int pipe
= intel_crtc
->pipe
;
5453 struct drm_display_mode
*mode
;
5454 int htot
= I915_READ((pipe
== 0) ? HTOTAL_A
: HTOTAL_B
);
5455 int hsync
= I915_READ((pipe
== 0) ? HSYNC_A
: HSYNC_B
);
5456 int vtot
= I915_READ((pipe
== 0) ? VTOTAL_A
: VTOTAL_B
);
5457 int vsync
= I915_READ((pipe
== 0) ? VSYNC_A
: VSYNC_B
);
5459 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
5463 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
5464 mode
->hdisplay
= (htot
& 0xffff) + 1;
5465 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
5466 mode
->hsync_start
= (hsync
& 0xffff) + 1;
5467 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
5468 mode
->vdisplay
= (vtot
& 0xffff) + 1;
5469 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
5470 mode
->vsync_start
= (vsync
& 0xffff) + 1;
5471 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
5473 drm_mode_set_name(mode
);
5474 drm_mode_set_crtcinfo(mode
, 0);
5479 #define GPU_IDLE_TIMEOUT 500 /* ms */
5481 /* When this timer fires, we've been idle for awhile */
5482 static void intel_gpu_idle_timer(unsigned long arg
)
5484 struct drm_device
*dev
= (struct drm_device
*)arg
;
5485 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5487 if (!list_empty(&dev_priv
->mm
.active_list
)) {
5488 /* Still processing requests, so just re-arm the timer. */
5489 mod_timer(&dev_priv
->idle_timer
, jiffies
+
5490 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
5494 dev_priv
->busy
= false;
5495 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
5498 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5500 static void intel_crtc_idle_timer(unsigned long arg
)
5502 struct intel_crtc
*intel_crtc
= (struct intel_crtc
*)arg
;
5503 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5504 drm_i915_private_t
*dev_priv
= crtc
->dev
->dev_private
;
5505 struct intel_framebuffer
*intel_fb
;
5507 intel_fb
= to_intel_framebuffer(crtc
->fb
);
5508 if (intel_fb
&& intel_fb
->obj
->active
) {
5509 /* The framebuffer is still being accessed by the GPU. */
5510 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
5511 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
5515 intel_crtc
->busy
= false;
5516 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
5519 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
5521 struct drm_device
*dev
= crtc
->dev
;
5522 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5523 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5524 int pipe
= intel_crtc
->pipe
;
5525 int dpll_reg
= DPLL(pipe
);
5528 if (HAS_PCH_SPLIT(dev
))
5531 if (!dev_priv
->lvds_downclock_avail
)
5534 dpll
= I915_READ(dpll_reg
);
5535 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
5536 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5538 /* Unlock panel regs */
5539 I915_WRITE(PP_CONTROL
,
5540 I915_READ(PP_CONTROL
) | PANEL_UNLOCK_REGS
);
5542 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
5543 I915_WRITE(dpll_reg
, dpll
);
5544 POSTING_READ(dpll_reg
);
5545 intel_wait_for_vblank(dev
, pipe
);
5547 dpll
= I915_READ(dpll_reg
);
5548 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
5549 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5551 /* ...and lock them again */
5552 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
5555 /* Schedule downclock */
5556 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
5557 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
5560 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
5562 struct drm_device
*dev
= crtc
->dev
;
5563 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5564 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5565 int pipe
= intel_crtc
->pipe
;
5566 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
5567 int dpll
= I915_READ(dpll_reg
);
5569 if (HAS_PCH_SPLIT(dev
))
5572 if (!dev_priv
->lvds_downclock_avail
)
5576 * Since this is called by a timer, we should never get here in
5579 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
5580 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5582 /* Unlock panel regs */
5583 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) |
5586 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
5587 I915_WRITE(dpll_reg
, dpll
);
5588 dpll
= I915_READ(dpll_reg
);
5589 intel_wait_for_vblank(dev
, pipe
);
5590 dpll
= I915_READ(dpll_reg
);
5591 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
5592 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5594 /* ...and lock them again */
5595 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
5601 * intel_idle_update - adjust clocks for idleness
5602 * @work: work struct
5604 * Either the GPU or display (or both) went idle. Check the busy status
5605 * here and adjust the CRTC and GPU clocks as necessary.
5607 static void intel_idle_update(struct work_struct
*work
)
5609 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
5611 struct drm_device
*dev
= dev_priv
->dev
;
5612 struct drm_crtc
*crtc
;
5613 struct intel_crtc
*intel_crtc
;
5615 if (!i915_powersave
)
5618 mutex_lock(&dev
->struct_mutex
);
5620 i915_update_gfx_val(dev_priv
);
5622 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
5623 /* Skip inactive CRTCs */
5627 intel_crtc
= to_intel_crtc(crtc
);
5628 if (!intel_crtc
->busy
)
5629 intel_decrease_pllclock(crtc
);
5633 mutex_unlock(&dev
->struct_mutex
);
5637 * intel_mark_busy - mark the GPU and possibly the display busy
5639 * @obj: object we're operating on
5641 * Callers can use this function to indicate that the GPU is busy processing
5642 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5643 * buffer), we'll also mark the display as busy, so we know to increase its
5646 void intel_mark_busy(struct drm_device
*dev
, struct drm_i915_gem_object
*obj
)
5648 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5649 struct drm_crtc
*crtc
= NULL
;
5650 struct intel_framebuffer
*intel_fb
;
5651 struct intel_crtc
*intel_crtc
;
5653 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
5656 if (!dev_priv
->busy
)
5657 dev_priv
->busy
= true;
5659 mod_timer(&dev_priv
->idle_timer
, jiffies
+
5660 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
5662 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
5666 intel_crtc
= to_intel_crtc(crtc
);
5667 intel_fb
= to_intel_framebuffer(crtc
->fb
);
5668 if (intel_fb
->obj
== obj
) {
5669 if (!intel_crtc
->busy
) {
5670 /* Non-busy -> busy, upclock */
5671 intel_increase_pllclock(crtc
);
5672 intel_crtc
->busy
= true;
5674 /* Busy -> busy, put off timer */
5675 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
5676 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
5682 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
5684 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5685 struct drm_device
*dev
= crtc
->dev
;
5686 struct intel_unpin_work
*work
;
5687 unsigned long flags
;
5689 spin_lock_irqsave(&dev
->event_lock
, flags
);
5690 work
= intel_crtc
->unpin_work
;
5691 intel_crtc
->unpin_work
= NULL
;
5692 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5695 cancel_work_sync(&work
->work
);
5699 drm_crtc_cleanup(crtc
);
5704 static void intel_unpin_work_fn(struct work_struct
*__work
)
5706 struct intel_unpin_work
*work
=
5707 container_of(__work
, struct intel_unpin_work
, work
);
5709 mutex_lock(&work
->dev
->struct_mutex
);
5710 i915_gem_object_unpin(work
->old_fb_obj
);
5711 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
5712 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
5714 mutex_unlock(&work
->dev
->struct_mutex
);
5718 static void do_intel_finish_page_flip(struct drm_device
*dev
,
5719 struct drm_crtc
*crtc
)
5721 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5722 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5723 struct intel_unpin_work
*work
;
5724 struct drm_i915_gem_object
*obj
;
5725 struct drm_pending_vblank_event
*e
;
5726 struct timeval tnow
, tvbl
;
5727 unsigned long flags
;
5729 /* Ignore early vblank irqs */
5730 if (intel_crtc
== NULL
)
5733 do_gettimeofday(&tnow
);
5735 spin_lock_irqsave(&dev
->event_lock
, flags
);
5736 work
= intel_crtc
->unpin_work
;
5737 if (work
== NULL
|| !work
->pending
) {
5738 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5742 intel_crtc
->unpin_work
= NULL
;
5746 e
->event
.sequence
= drm_vblank_count_and_time(dev
, intel_crtc
->pipe
, &tvbl
);
5748 /* Called before vblank count and timestamps have
5749 * been updated for the vblank interval of flip
5750 * completion? Need to increment vblank count and
5751 * add one videorefresh duration to returned timestamp
5752 * to account for this. We assume this happened if we
5753 * get called over 0.9 frame durations after the last
5754 * timestamped vblank.
5756 * This calculation can not be used with vrefresh rates
5757 * below 5Hz (10Hz to be on the safe side) without
5758 * promoting to 64 integers.
5760 if (10 * (timeval_to_ns(&tnow
) - timeval_to_ns(&tvbl
)) >
5761 9 * crtc
->framedur_ns
) {
5762 e
->event
.sequence
++;
5763 tvbl
= ns_to_timeval(timeval_to_ns(&tvbl
) +
5767 e
->event
.tv_sec
= tvbl
.tv_sec
;
5768 e
->event
.tv_usec
= tvbl
.tv_usec
;
5770 list_add_tail(&e
->base
.link
,
5771 &e
->base
.file_priv
->event_list
);
5772 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
5775 drm_vblank_put(dev
, intel_crtc
->pipe
);
5777 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5779 obj
= work
->old_fb_obj
;
5781 atomic_clear_mask(1 << intel_crtc
->plane
,
5782 &obj
->pending_flip
.counter
);
5783 if (atomic_read(&obj
->pending_flip
) == 0)
5784 wake_up(&dev_priv
->pending_flip_queue
);
5786 schedule_work(&work
->work
);
5788 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
5791 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
5793 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5794 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
5796 do_intel_finish_page_flip(dev
, crtc
);
5799 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
5801 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5802 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
5804 do_intel_finish_page_flip(dev
, crtc
);
5807 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
5809 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5810 struct intel_crtc
*intel_crtc
=
5811 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
5812 unsigned long flags
;
5814 spin_lock_irqsave(&dev
->event_lock
, flags
);
5815 if (intel_crtc
->unpin_work
) {
5816 if ((++intel_crtc
->unpin_work
->pending
) > 1)
5817 DRM_ERROR("Prepared flip multiple times\n");
5819 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5821 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5824 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
5825 struct drm_framebuffer
*fb
,
5826 struct drm_pending_vblank_event
*event
)
5828 struct drm_device
*dev
= crtc
->dev
;
5829 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5830 struct intel_framebuffer
*intel_fb
;
5831 struct drm_i915_gem_object
*obj
;
5832 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5833 struct intel_unpin_work
*work
;
5834 unsigned long flags
, offset
;
5835 int pipe
= intel_crtc
->pipe
;
5839 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
5843 work
->event
= event
;
5844 work
->dev
= crtc
->dev
;
5845 intel_fb
= to_intel_framebuffer(crtc
->fb
);
5846 work
->old_fb_obj
= intel_fb
->obj
;
5847 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
5849 /* We borrow the event spin lock for protecting unpin_work */
5850 spin_lock_irqsave(&dev
->event_lock
, flags
);
5851 if (intel_crtc
->unpin_work
) {
5852 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5855 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5858 intel_crtc
->unpin_work
= work
;
5859 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5861 intel_fb
= to_intel_framebuffer(fb
);
5862 obj
= intel_fb
->obj
;
5864 mutex_lock(&dev
->struct_mutex
);
5865 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, LP_RING(dev_priv
));
5869 /* Reference the objects for the scheduled work. */
5870 drm_gem_object_reference(&work
->old_fb_obj
->base
);
5871 drm_gem_object_reference(&obj
->base
);
5875 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
5879 if (IS_GEN3(dev
) || IS_GEN2(dev
)) {
5882 /* Can't queue multiple flips, so wait for the previous
5883 * one to finish before executing the next.
5885 ret
= BEGIN_LP_RING(2);
5889 if (intel_crtc
->plane
)
5890 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
5892 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
5893 OUT_RING(MI_WAIT_FOR_EVENT
| flip_mask
);
5898 work
->pending_flip_obj
= obj
;
5900 work
->enable_stall_check
= true;
5902 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5903 offset
= crtc
->y
* fb
->pitch
+ crtc
->x
* fb
->bits_per_pixel
/8;
5905 ret
= BEGIN_LP_RING(4);
5909 /* Block clients from rendering to the new back buffer until
5910 * the flip occurs and the object is no longer visible.
5912 atomic_add(1 << intel_crtc
->plane
, &work
->old_fb_obj
->pending_flip
);
5914 switch (INTEL_INFO(dev
)->gen
) {
5916 OUT_RING(MI_DISPLAY_FLIP
|
5917 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
5918 OUT_RING(fb
->pitch
);
5919 OUT_RING(obj
->gtt_offset
+ offset
);
5924 OUT_RING(MI_DISPLAY_FLIP_I915
|
5925 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
5926 OUT_RING(fb
->pitch
);
5927 OUT_RING(obj
->gtt_offset
+ offset
);
5933 /* i965+ uses the linear or tiled offsets from the
5934 * Display Registers (which do not change across a page-flip)
5935 * so we need only reprogram the base address.
5937 OUT_RING(MI_DISPLAY_FLIP
|
5938 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
5939 OUT_RING(fb
->pitch
);
5940 OUT_RING(obj
->gtt_offset
| obj
->tiling_mode
);
5942 /* XXX Enabling the panel-fitter across page-flip is so far
5943 * untested on non-native modes, so ignore it for now.
5944 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5947 pipesrc
= I915_READ(pipe
== 0 ? PIPEASRC
: PIPEBSRC
) & 0x0fff0fff;
5948 OUT_RING(pf
| pipesrc
);
5952 OUT_RING(MI_DISPLAY_FLIP
|
5953 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
5954 OUT_RING(fb
->pitch
| obj
->tiling_mode
);
5955 OUT_RING(obj
->gtt_offset
);
5957 pf
= I915_READ(pipe
== 0 ? PFA_CTL_1
: PFB_CTL_1
) & PF_ENABLE
;
5958 pipesrc
= I915_READ(pipe
== 0 ? PIPEASRC
: PIPEBSRC
) & 0x0fff0fff;
5959 OUT_RING(pf
| pipesrc
);
5964 mutex_unlock(&dev
->struct_mutex
);
5966 trace_i915_flip_request(intel_crtc
->plane
, obj
);
5971 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
5972 drm_gem_object_unreference(&obj
->base
);
5974 mutex_unlock(&dev
->struct_mutex
);
5976 spin_lock_irqsave(&dev
->event_lock
, flags
);
5977 intel_crtc
->unpin_work
= NULL
;
5978 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5985 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
5986 .dpms
= intel_crtc_dpms
,
5987 .mode_fixup
= intel_crtc_mode_fixup
,
5988 .mode_set
= intel_crtc_mode_set
,
5989 .mode_set_base
= intel_pipe_set_base
,
5990 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
5991 .load_lut
= intel_crtc_load_lut
,
5992 .disable
= intel_crtc_disable
,
5995 static const struct drm_crtc_funcs intel_crtc_funcs
= {
5996 .cursor_set
= intel_crtc_cursor_set
,
5997 .cursor_move
= intel_crtc_cursor_move
,
5998 .gamma_set
= intel_crtc_gamma_set
,
5999 .set_config
= drm_crtc_helper_set_config
,
6000 .destroy
= intel_crtc_destroy
,
6001 .page_flip
= intel_crtc_page_flip
,
6004 static void intel_sanitize_modesetting(struct drm_device
*dev
,
6005 int pipe
, int plane
)
6007 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6010 if (HAS_PCH_SPLIT(dev
))
6013 /* Who knows what state these registers were left in by the BIOS or
6016 * If we leave the registers in a conflicting state (e.g. with the
6017 * display plane reading from the other pipe than the one we intend
6018 * to use) then when we attempt to teardown the active mode, we will
6019 * not disable the pipes and planes in the correct order -- leaving
6020 * a plane reading from a disabled pipe and possibly leading to
6021 * undefined behaviour.
6024 reg
= DSPCNTR(plane
);
6025 val
= I915_READ(reg
);
6027 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
6029 if (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == pipe
)
6032 /* This display plane is active and attached to the other CPU pipe. */
6035 /* Disable the plane and wait for it to stop reading from the pipe. */
6036 intel_disable_plane(dev_priv
, plane
, pipe
);
6037 intel_disable_pipe(dev_priv
, pipe
);
6040 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
6042 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6043 struct intel_crtc
*intel_crtc
;
6046 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
6047 if (intel_crtc
== NULL
)
6050 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
6052 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
6053 for (i
= 0; i
< 256; i
++) {
6054 intel_crtc
->lut_r
[i
] = i
;
6055 intel_crtc
->lut_g
[i
] = i
;
6056 intel_crtc
->lut_b
[i
] = i
;
6059 /* Swap pipes & planes for FBC on pre-965 */
6060 intel_crtc
->pipe
= pipe
;
6061 intel_crtc
->plane
= pipe
;
6062 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
6063 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6064 intel_crtc
->plane
= !pipe
;
6067 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
6068 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
6069 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
6070 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
6072 intel_crtc
->cursor_addr
= 0;
6073 intel_crtc
->dpms_mode
= -1;
6074 intel_crtc
->active
= true; /* force the pipe off on setup_init_config */
6076 if (HAS_PCH_SPLIT(dev
)) {
6077 intel_helper_funcs
.prepare
= ironlake_crtc_prepare
;
6078 intel_helper_funcs
.commit
= ironlake_crtc_commit
;
6080 intel_helper_funcs
.prepare
= i9xx_crtc_prepare
;
6081 intel_helper_funcs
.commit
= i9xx_crtc_commit
;
6084 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
6086 intel_crtc
->busy
= false;
6088 setup_timer(&intel_crtc
->idle_timer
, intel_crtc_idle_timer
,
6089 (unsigned long)intel_crtc
);
6091 intel_sanitize_modesetting(dev
, intel_crtc
->pipe
, intel_crtc
->plane
);
6094 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
6095 struct drm_file
*file
)
6097 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6098 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
6099 struct drm_mode_object
*drmmode_obj
;
6100 struct intel_crtc
*crtc
;
6103 DRM_ERROR("called with no initialization\n");
6107 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
6108 DRM_MODE_OBJECT_CRTC
);
6111 DRM_ERROR("no such CRTC id\n");
6115 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
6116 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
6121 static int intel_encoder_clones(struct drm_device
*dev
, int type_mask
)
6123 struct intel_encoder
*encoder
;
6127 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
6128 if (type_mask
& encoder
->clone_mask
)
6129 index_mask
|= (1 << entry
);
6136 static bool has_edp_a(struct drm_device
*dev
)
6138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6140 if (!IS_MOBILE(dev
))
6143 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
6147 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
6153 static void intel_setup_outputs(struct drm_device
*dev
)
6155 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6156 struct intel_encoder
*encoder
;
6157 bool dpd_is_edp
= false;
6158 bool has_lvds
= false;
6160 if (IS_MOBILE(dev
) && !IS_I830(dev
))
6161 has_lvds
= intel_lvds_init(dev
);
6162 if (!has_lvds
&& !HAS_PCH_SPLIT(dev
)) {
6163 /* disable the panel fitter on everything but LVDS */
6164 I915_WRITE(PFIT_CONTROL
, 0);
6167 if (HAS_PCH_SPLIT(dev
)) {
6168 dpd_is_edp
= intel_dpd_is_edp(dev
);
6171 intel_dp_init(dev
, DP_A
);
6173 if (dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
6174 intel_dp_init(dev
, PCH_DP_D
);
6177 intel_crt_init(dev
);
6179 if (HAS_PCH_SPLIT(dev
)) {
6182 if (I915_READ(HDMIB
) & PORT_DETECTED
) {
6183 /* PCH SDVOB multiplex with HDMIB */
6184 found
= intel_sdvo_init(dev
, PCH_SDVOB
);
6186 intel_hdmi_init(dev
, HDMIB
);
6187 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
6188 intel_dp_init(dev
, PCH_DP_B
);
6191 if (I915_READ(HDMIC
) & PORT_DETECTED
)
6192 intel_hdmi_init(dev
, HDMIC
);
6194 if (I915_READ(HDMID
) & PORT_DETECTED
)
6195 intel_hdmi_init(dev
, HDMID
);
6197 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
6198 intel_dp_init(dev
, PCH_DP_C
);
6200 if (!dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
6201 intel_dp_init(dev
, PCH_DP_D
);
6203 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
6206 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
6207 DRM_DEBUG_KMS("probing SDVOB\n");
6208 found
= intel_sdvo_init(dev
, SDVOB
);
6209 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
6210 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6211 intel_hdmi_init(dev
, SDVOB
);
6214 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
6215 DRM_DEBUG_KMS("probing DP_B\n");
6216 intel_dp_init(dev
, DP_B
);
6220 /* Before G4X SDVOC doesn't have its own detect register */
6222 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
6223 DRM_DEBUG_KMS("probing SDVOC\n");
6224 found
= intel_sdvo_init(dev
, SDVOC
);
6227 if (!found
&& (I915_READ(SDVOC
) & SDVO_DETECTED
)) {
6229 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
6230 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6231 intel_hdmi_init(dev
, SDVOC
);
6233 if (SUPPORTS_INTEGRATED_DP(dev
)) {
6234 DRM_DEBUG_KMS("probing DP_C\n");
6235 intel_dp_init(dev
, DP_C
);
6239 if (SUPPORTS_INTEGRATED_DP(dev
) &&
6240 (I915_READ(DP_D
) & DP_DETECTED
)) {
6241 DRM_DEBUG_KMS("probing DP_D\n");
6242 intel_dp_init(dev
, DP_D
);
6244 } else if (IS_GEN2(dev
))
6245 intel_dvo_init(dev
);
6247 if (SUPPORTS_TV(dev
))
6250 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
6251 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
6252 encoder
->base
.possible_clones
=
6253 intel_encoder_clones(dev
, encoder
->clone_mask
);
6256 intel_panel_setup_backlight(dev
);
6259 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
6261 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
6263 drm_framebuffer_cleanup(fb
);
6264 drm_gem_object_unreference_unlocked(&intel_fb
->obj
->base
);
6269 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
6270 struct drm_file
*file
,
6271 unsigned int *handle
)
6273 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
6274 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
6276 return drm_gem_handle_create(file
, &obj
->base
, handle
);
6279 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
6280 .destroy
= intel_user_framebuffer_destroy
,
6281 .create_handle
= intel_user_framebuffer_create_handle
,
6284 int intel_framebuffer_init(struct drm_device
*dev
,
6285 struct intel_framebuffer
*intel_fb
,
6286 struct drm_mode_fb_cmd
*mode_cmd
,
6287 struct drm_i915_gem_object
*obj
)
6291 if (obj
->tiling_mode
== I915_TILING_Y
)
6294 if (mode_cmd
->pitch
& 63)
6297 switch (mode_cmd
->bpp
) {
6307 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
6309 DRM_ERROR("framebuffer init failed %d\n", ret
);
6313 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
6314 intel_fb
->obj
= obj
;
6318 static struct drm_framebuffer
*
6319 intel_user_framebuffer_create(struct drm_device
*dev
,
6320 struct drm_file
*filp
,
6321 struct drm_mode_fb_cmd
*mode_cmd
)
6323 struct drm_i915_gem_object
*obj
;
6324 struct intel_framebuffer
*intel_fb
;
6327 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
, mode_cmd
->handle
));
6329 return ERR_PTR(-ENOENT
);
6331 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
6333 return ERR_PTR(-ENOMEM
);
6335 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
6337 drm_gem_object_unreference_unlocked(&obj
->base
);
6339 return ERR_PTR(ret
);
6342 return &intel_fb
->base
;
6345 static const struct drm_mode_config_funcs intel_mode_funcs
= {
6346 .fb_create
= intel_user_framebuffer_create
,
6347 .output_poll_changed
= intel_fb_output_poll_changed
,
6350 static struct drm_i915_gem_object
*
6351 intel_alloc_context_page(struct drm_device
*dev
)
6353 struct drm_i915_gem_object
*ctx
;
6356 ctx
= i915_gem_alloc_object(dev
, 4096);
6358 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6362 mutex_lock(&dev
->struct_mutex
);
6363 ret
= i915_gem_object_pin(ctx
, 4096, true);
6365 DRM_ERROR("failed to pin power context: %d\n", ret
);
6369 ret
= i915_gem_object_set_to_gtt_domain(ctx
, 1);
6371 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
6374 mutex_unlock(&dev
->struct_mutex
);
6379 i915_gem_object_unpin(ctx
);
6381 drm_gem_object_unreference(&ctx
->base
);
6382 mutex_unlock(&dev
->struct_mutex
);
6386 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
6388 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6391 rgvswctl
= I915_READ16(MEMSWCTL
);
6392 if (rgvswctl
& MEMCTL_CMD_STS
) {
6393 DRM_DEBUG("gpu busy, RCS change rejected\n");
6394 return false; /* still busy with another command */
6397 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
6398 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
6399 I915_WRITE16(MEMSWCTL
, rgvswctl
);
6400 POSTING_READ16(MEMSWCTL
);
6402 rgvswctl
|= MEMCTL_CMD_STS
;
6403 I915_WRITE16(MEMSWCTL
, rgvswctl
);
6408 void ironlake_enable_drps(struct drm_device
*dev
)
6410 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6411 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
6412 u8 fmax
, fmin
, fstart
, vstart
;
6414 /* Enable temp reporting */
6415 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
6416 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
6418 /* 100ms RC evaluation intervals */
6419 I915_WRITE(RCUPEI
, 100000);
6420 I915_WRITE(RCDNEI
, 100000);
6422 /* Set max/min thresholds to 90ms and 80ms respectively */
6423 I915_WRITE(RCBMAXAVG
, 90000);
6424 I915_WRITE(RCBMINAVG
, 80000);
6426 I915_WRITE(MEMIHYST
, 1);
6428 /* Set up min, max, and cur for interrupt handling */
6429 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
6430 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
6431 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
6432 MEMMODE_FSTART_SHIFT
;
6434 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
6437 dev_priv
->fmax
= fmax
; /* IPS callback will increase this */
6438 dev_priv
->fstart
= fstart
;
6440 dev_priv
->max_delay
= fstart
;
6441 dev_priv
->min_delay
= fmin
;
6442 dev_priv
->cur_delay
= fstart
;
6444 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6445 fmax
, fmin
, fstart
);
6447 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
6450 * Interrupts will be enabled in ironlake_irq_postinstall
6453 I915_WRITE(VIDSTART
, vstart
);
6454 POSTING_READ(VIDSTART
);
6456 rgvmodectl
|= MEMMODE_SWMODE_EN
;
6457 I915_WRITE(MEMMODECTL
, rgvmodectl
);
6459 if (wait_for((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
6460 DRM_ERROR("stuck trying to change perf mode\n");
6463 ironlake_set_drps(dev
, fstart
);
6465 dev_priv
->last_count1
= I915_READ(0x112e4) + I915_READ(0x112e8) +
6467 dev_priv
->last_time1
= jiffies_to_msecs(jiffies
);
6468 dev_priv
->last_count2
= I915_READ(0x112f4);
6469 getrawmonotonic(&dev_priv
->last_time2
);
6472 void ironlake_disable_drps(struct drm_device
*dev
)
6474 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6475 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
6477 /* Ack interrupts, disable EFC interrupt */
6478 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
6479 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
6480 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
6481 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
6482 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
6484 /* Go back to the starting frequency */
6485 ironlake_set_drps(dev
, dev_priv
->fstart
);
6487 rgvswctl
|= MEMCTL_CMD_STS
;
6488 I915_WRITE(MEMSWCTL
, rgvswctl
);
6493 void gen6_set_rps(struct drm_device
*dev
, u8 val
)
6495 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6498 swreq
= (val
& 0x3ff) << 25;
6499 I915_WRITE(GEN6_RPNSWREQ
, swreq
);
6502 void gen6_disable_rps(struct drm_device
*dev
)
6504 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6506 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
6507 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
6508 I915_WRITE(GEN6_PMIER
, 0);
6509 I915_WRITE(GEN6_PMIIR
, I915_READ(GEN6_PMIIR
));
6512 static unsigned long intel_pxfreq(u32 vidfreq
)
6515 int div
= (vidfreq
& 0x3f0000) >> 16;
6516 int post
= (vidfreq
& 0x3000) >> 12;
6517 int pre
= (vidfreq
& 0x7);
6522 freq
= ((div
* 133333) / ((1<<post
) * pre
));
6527 void intel_init_emon(struct drm_device
*dev
)
6529 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6534 /* Disable to program */
6538 /* Program energy weights for various events */
6539 I915_WRITE(SDEW
, 0x15040d00);
6540 I915_WRITE(CSIEW0
, 0x007f0000);
6541 I915_WRITE(CSIEW1
, 0x1e220004);
6542 I915_WRITE(CSIEW2
, 0x04000004);
6544 for (i
= 0; i
< 5; i
++)
6545 I915_WRITE(PEW
+ (i
* 4), 0);
6546 for (i
= 0; i
< 3; i
++)
6547 I915_WRITE(DEW
+ (i
* 4), 0);
6549 /* Program P-state weights to account for frequency power adjustment */
6550 for (i
= 0; i
< 16; i
++) {
6551 u32 pxvidfreq
= I915_READ(PXVFREQ_BASE
+ (i
* 4));
6552 unsigned long freq
= intel_pxfreq(pxvidfreq
);
6553 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
6558 val
*= (freq
/ 1000);
6560 val
/= (127*127*900);
6562 DRM_ERROR("bad pxval: %ld\n", val
);
6565 /* Render standby states get 0 weight */
6569 for (i
= 0; i
< 4; i
++) {
6570 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
6571 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
6572 I915_WRITE(PXW
+ (i
* 4), val
);
6575 /* Adjust magic regs to magic values (more experimental results) */
6576 I915_WRITE(OGW0
, 0);
6577 I915_WRITE(OGW1
, 0);
6578 I915_WRITE(EG0
, 0x00007f00);
6579 I915_WRITE(EG1
, 0x0000000e);
6580 I915_WRITE(EG2
, 0x000e0000);
6581 I915_WRITE(EG3
, 0x68000300);
6582 I915_WRITE(EG4
, 0x42000000);
6583 I915_WRITE(EG5
, 0x00140031);
6587 for (i
= 0; i
< 8; i
++)
6588 I915_WRITE(PXWL
+ (i
* 4), 0);
6590 /* Enable PMON + select events */
6591 I915_WRITE(ECR
, 0x80000019);
6593 lcfuse
= I915_READ(LCFUSE02
);
6595 dev_priv
->corr
= (lcfuse
& LCFUSE_HIV_MASK
);
6598 void gen6_enable_rps(struct drm_i915_private
*dev_priv
)
6600 u32 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
6601 u32 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
6603 int cur_freq
, min_freq
, max_freq
;
6606 /* Here begins a magic sequence of register writes to enable
6607 * auto-downclocking.
6609 * Perhaps there might be some value in exposing these to
6612 I915_WRITE(GEN6_RC_STATE
, 0);
6613 __gen6_force_wake_get(dev_priv
);
6615 /* disable the counters and set deterministic thresholds */
6616 I915_WRITE(GEN6_RC_CONTROL
, 0);
6618 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
6619 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
6620 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
6621 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
6622 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
6624 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
6625 I915_WRITE(RING_MAX_IDLE(dev_priv
->ring
[i
].mmio_base
), 10);
6627 I915_WRITE(GEN6_RC_SLEEP
, 0);
6628 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
6629 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
6630 I915_WRITE(GEN6_RC6p_THRESHOLD
, 100000);
6631 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
6633 I915_WRITE(GEN6_RC_CONTROL
,
6634 GEN6_RC_CTL_RC6p_ENABLE
|
6635 GEN6_RC_CTL_RC6_ENABLE
|
6636 GEN6_RC_CTL_EI_MODE(1) |
6637 GEN6_RC_CTL_HW_ENABLE
);
6639 I915_WRITE(GEN6_RPNSWREQ
,
6640 GEN6_FREQUENCY(10) |
6642 GEN6_AGGRESSIVE_TURBO
);
6643 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
6644 GEN6_FREQUENCY(12));
6646 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
6647 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
6650 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 10000);
6651 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 1000000);
6652 I915_WRITE(GEN6_RP_UP_EI
, 100000);
6653 I915_WRITE(GEN6_RP_DOWN_EI
, 5000000);
6654 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
6655 I915_WRITE(GEN6_RP_CONTROL
,
6656 GEN6_RP_MEDIA_TURBO
|
6657 GEN6_RP_USE_NORMAL_FREQ
|
6658 GEN6_RP_MEDIA_IS_GFX
|
6660 GEN6_RP_UP_BUSY_AVG
|
6661 GEN6_RP_DOWN_IDLE_CONT
);
6663 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
6665 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6667 I915_WRITE(GEN6_PCODE_DATA
, 0);
6668 I915_WRITE(GEN6_PCODE_MAILBOX
,
6670 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
);
6671 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
6673 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6675 min_freq
= (rp_state_cap
& 0xff0000) >> 16;
6676 max_freq
= rp_state_cap
& 0xff;
6677 cur_freq
= (gt_perf_status
& 0xff00) >> 8;
6679 /* Check for overclock support */
6680 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
6682 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6683 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_READ_OC_PARAMS
);
6684 pcu_mbox
= I915_READ(GEN6_PCODE_DATA
);
6685 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
6687 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6688 if (pcu_mbox
& (1<<31)) { /* OC supported */
6689 max_freq
= pcu_mbox
& 0xff;
6690 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox
* 100);
6693 /* In units of 100MHz */
6694 dev_priv
->max_delay
= max_freq
;
6695 dev_priv
->min_delay
= min_freq
;
6696 dev_priv
->cur_delay
= cur_freq
;
6698 /* requires MSI enabled */
6699 I915_WRITE(GEN6_PMIER
,
6700 GEN6_PM_MBOX_EVENT
|
6701 GEN6_PM_THERMAL_EVENT
|
6702 GEN6_PM_RP_DOWN_TIMEOUT
|
6703 GEN6_PM_RP_UP_THRESHOLD
|
6704 GEN6_PM_RP_DOWN_THRESHOLD
|
6705 GEN6_PM_RP_UP_EI_EXPIRED
|
6706 GEN6_PM_RP_DOWN_EI_EXPIRED
);
6707 I915_WRITE(GEN6_PMIMR
, 0);
6708 /* enable all PM interrupts */
6709 I915_WRITE(GEN6_PMINTRMSK
, 0);
6711 __gen6_force_wake_put(dev_priv
);
6714 void intel_enable_clock_gating(struct drm_device
*dev
)
6716 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6719 * Disable clock gating reported to work incorrectly according to the
6720 * specs, but enable as much else as we can.
6722 if (HAS_PCH_SPLIT(dev
)) {
6723 uint32_t dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
;
6726 /* Required for FBC */
6727 dspclk_gate
|= DPFDUNIT_CLOCK_GATE_DISABLE
;
6728 /* Required for CxSR */
6729 dspclk_gate
|= DPARBUNIT_CLOCK_GATE_DISABLE
;
6731 I915_WRITE(PCH_3DCGDIS0
,
6732 MARIUNIT_CLOCK_GATE_DISABLE
|
6733 SVSMUNIT_CLOCK_GATE_DISABLE
);
6734 I915_WRITE(PCH_3DCGDIS1
,
6735 VFMUNIT_CLOCK_GATE_DISABLE
);
6738 I915_WRITE(PCH_DSPCLK_GATE_D
, dspclk_gate
);
6741 * On Ibex Peak and Cougar Point, we need to disable clock
6742 * gating for the panel power sequencer or it will fail to
6743 * start up when no ports are active.
6745 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
6748 * According to the spec the following bits should be set in
6749 * order to enable memory self-refresh
6750 * The bit 22/21 of 0x42004
6751 * The bit 5 of 0x42020
6752 * The bit 15 of 0x45000
6755 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6756 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
6757 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
6758 I915_WRITE(ILK_DSPCLK_GATE
,
6759 (I915_READ(ILK_DSPCLK_GATE
) |
6760 ILK_DPARB_CLK_GATE
));
6761 I915_WRITE(DISP_ARB_CTL
,
6762 (I915_READ(DISP_ARB_CTL
) |
6764 I915_WRITE(WM3_LP_ILK
, 0);
6765 I915_WRITE(WM2_LP_ILK
, 0);
6766 I915_WRITE(WM1_LP_ILK
, 0);
6769 * Based on the document from hardware guys the following bits
6770 * should be set unconditionally in order to enable FBC.
6771 * The bit 22 of 0x42000
6772 * The bit 22 of 0x42004
6773 * The bit 7,8,9 of 0x42020.
6775 if (IS_IRONLAKE_M(dev
)) {
6776 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
6777 I915_READ(ILK_DISPLAY_CHICKEN1
) |
6779 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6780 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6782 I915_WRITE(ILK_DSPCLK_GATE
,
6783 I915_READ(ILK_DSPCLK_GATE
) |
6789 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6790 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6791 ILK_ELPIN_409_SELECT
);
6794 I915_WRITE(_3D_CHICKEN2
,
6795 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
6796 _3D_CHICKEN2_WM_READ_PIPELINED
);
6800 I915_WRITE(WM3_LP_ILK
, 0);
6801 I915_WRITE(WM2_LP_ILK
, 0);
6802 I915_WRITE(WM1_LP_ILK
, 0);
6805 * According to the spec the following bits should be
6806 * set in order to enable memory self-refresh and fbc:
6807 * The bit21 and bit22 of 0x42000
6808 * The bit21 and bit22 of 0x42004
6809 * The bit5 and bit7 of 0x42020
6810 * The bit14 of 0x70180
6811 * The bit14 of 0x71180
6813 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
6814 I915_READ(ILK_DISPLAY_CHICKEN1
) |
6815 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
6816 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6817 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6818 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
6819 I915_WRITE(ILK_DSPCLK_GATE
,
6820 I915_READ(ILK_DSPCLK_GATE
) |
6821 ILK_DPARB_CLK_GATE
|
6824 I915_WRITE(DSPACNTR
,
6825 I915_READ(DSPACNTR
) |
6826 DISPPLANE_TRICKLE_FEED_DISABLE
);
6827 I915_WRITE(DSPBCNTR
,
6828 I915_READ(DSPBCNTR
) |
6829 DISPPLANE_TRICKLE_FEED_DISABLE
);
6831 } else if (IS_G4X(dev
)) {
6832 uint32_t dspclk_gate
;
6833 I915_WRITE(RENCLK_GATE_D1
, 0);
6834 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
6835 GS_UNIT_CLOCK_GATE_DISABLE
|
6836 CL_UNIT_CLOCK_GATE_DISABLE
);
6837 I915_WRITE(RAMCLK_GATE_D
, 0);
6838 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
6839 OVRUNIT_CLOCK_GATE_DISABLE
|
6840 OVCUNIT_CLOCK_GATE_DISABLE
;
6842 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
6843 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
6844 } else if (IS_CRESTLINE(dev
)) {
6845 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
6846 I915_WRITE(RENCLK_GATE_D2
, 0);
6847 I915_WRITE(DSPCLK_GATE_D
, 0);
6848 I915_WRITE(RAMCLK_GATE_D
, 0);
6849 I915_WRITE16(DEUC
, 0);
6850 } else if (IS_BROADWATER(dev
)) {
6851 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
6852 I965_RCC_CLOCK_GATE_DISABLE
|
6853 I965_RCPB_CLOCK_GATE_DISABLE
|
6854 I965_ISC_CLOCK_GATE_DISABLE
|
6855 I965_FBC_CLOCK_GATE_DISABLE
);
6856 I915_WRITE(RENCLK_GATE_D2
, 0);
6857 } else if (IS_GEN3(dev
)) {
6858 u32 dstate
= I915_READ(D_STATE
);
6860 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
6861 DSTATE_DOT_CLOCK_GATING
;
6862 I915_WRITE(D_STATE
, dstate
);
6863 } else if (IS_I85X(dev
) || IS_I865G(dev
)) {
6864 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
6865 } else if (IS_I830(dev
)) {
6866 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
6870 void intel_disable_clock_gating(struct drm_device
*dev
)
6872 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6874 if (dev_priv
->renderctx
) {
6875 struct drm_i915_gem_object
*obj
= dev_priv
->renderctx
;
6877 I915_WRITE(CCID
, 0);
6880 i915_gem_object_unpin(obj
);
6881 drm_gem_object_unreference(&obj
->base
);
6882 dev_priv
->renderctx
= NULL
;
6885 if (dev_priv
->pwrctx
) {
6886 struct drm_i915_gem_object
*obj
= dev_priv
->pwrctx
;
6888 I915_WRITE(PWRCTXA
, 0);
6889 POSTING_READ(PWRCTXA
);
6891 i915_gem_object_unpin(obj
);
6892 drm_gem_object_unreference(&obj
->base
);
6893 dev_priv
->pwrctx
= NULL
;
6897 static void ironlake_disable_rc6(struct drm_device
*dev
)
6899 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6901 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
6902 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) | RCX_SW_EXIT
);
6903 wait_for(((I915_READ(RSTDBYCTL
) & RSX_STATUS_MASK
) == RSX_STATUS_ON
),
6906 I915_WRITE(PWRCTXA
, 0);
6907 POSTING_READ(PWRCTXA
);
6908 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
6909 POSTING_READ(RSTDBYCTL
);
6910 i915_gem_object_unpin(dev_priv
->renderctx
);
6911 drm_gem_object_unreference(&dev_priv
->renderctx
->base
);
6912 dev_priv
->renderctx
= NULL
;
6913 i915_gem_object_unpin(dev_priv
->pwrctx
);
6914 drm_gem_object_unreference(&dev_priv
->pwrctx
->base
);
6915 dev_priv
->pwrctx
= NULL
;
6918 void ironlake_enable_rc6(struct drm_device
*dev
)
6920 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6924 * GPU can automatically power down the render unit if given a page
6927 ret
= BEGIN_LP_RING(6);
6929 ironlake_disable_rc6(dev
);
6932 OUT_RING(MI_SUSPEND_FLUSH
| MI_SUSPEND_FLUSH_EN
);
6933 OUT_RING(MI_SET_CONTEXT
);
6934 OUT_RING(dev_priv
->renderctx
->gtt_offset
|
6936 MI_SAVE_EXT_STATE_EN
|
6937 MI_RESTORE_EXT_STATE_EN
|
6938 MI_RESTORE_INHIBIT
);
6939 OUT_RING(MI_SUSPEND_FLUSH
);
6944 I915_WRITE(PWRCTXA
, dev_priv
->pwrctx
->gtt_offset
| PWRCTX_EN
);
6945 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
6948 /* Set up chip specific display functions */
6949 static void intel_init_display(struct drm_device
*dev
)
6951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6953 /* We always want a DPMS function */
6954 if (HAS_PCH_SPLIT(dev
))
6955 dev_priv
->display
.dpms
= ironlake_crtc_dpms
;
6957 dev_priv
->display
.dpms
= i9xx_crtc_dpms
;
6959 if (I915_HAS_FBC(dev
)) {
6960 if (HAS_PCH_SPLIT(dev
)) {
6961 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
6962 dev_priv
->display
.enable_fbc
= ironlake_enable_fbc
;
6963 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
6964 } else if (IS_GM45(dev
)) {
6965 dev_priv
->display
.fbc_enabled
= g4x_fbc_enabled
;
6966 dev_priv
->display
.enable_fbc
= g4x_enable_fbc
;
6967 dev_priv
->display
.disable_fbc
= g4x_disable_fbc
;
6968 } else if (IS_CRESTLINE(dev
)) {
6969 dev_priv
->display
.fbc_enabled
= i8xx_fbc_enabled
;
6970 dev_priv
->display
.enable_fbc
= i8xx_enable_fbc
;
6971 dev_priv
->display
.disable_fbc
= i8xx_disable_fbc
;
6973 /* 855GM needs testing */
6976 /* Returns the core display clock speed */
6977 if (IS_I945G(dev
) || (IS_G33(dev
) && ! IS_PINEVIEW_M(dev
)))
6978 dev_priv
->display
.get_display_clock_speed
=
6979 i945_get_display_clock_speed
;
6980 else if (IS_I915G(dev
))
6981 dev_priv
->display
.get_display_clock_speed
=
6982 i915_get_display_clock_speed
;
6983 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
6984 dev_priv
->display
.get_display_clock_speed
=
6985 i9xx_misc_get_display_clock_speed
;
6986 else if (IS_I915GM(dev
))
6987 dev_priv
->display
.get_display_clock_speed
=
6988 i915gm_get_display_clock_speed
;
6989 else if (IS_I865G(dev
))
6990 dev_priv
->display
.get_display_clock_speed
=
6991 i865_get_display_clock_speed
;
6992 else if (IS_I85X(dev
))
6993 dev_priv
->display
.get_display_clock_speed
=
6994 i855_get_display_clock_speed
;
6996 dev_priv
->display
.get_display_clock_speed
=
6997 i830_get_display_clock_speed
;
6999 /* For FIFO watermark updates */
7000 if (HAS_PCH_SPLIT(dev
)) {
7002 if (I915_READ(MLTR_ILK
) & ILK_SRLT_MASK
)
7003 dev_priv
->display
.update_wm
= ironlake_update_wm
;
7005 DRM_DEBUG_KMS("Failed to get proper latency. "
7007 dev_priv
->display
.update_wm
= NULL
;
7009 } else if (IS_GEN6(dev
)) {
7010 if (SNB_READ_WM0_LATENCY()) {
7011 dev_priv
->display
.update_wm
= sandybridge_update_wm
;
7013 DRM_DEBUG_KMS("Failed to read display plane latency. "
7015 dev_priv
->display
.update_wm
= NULL
;
7018 dev_priv
->display
.update_wm
= NULL
;
7019 } else if (IS_PINEVIEW(dev
)) {
7020 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
7023 dev_priv
->mem_freq
)) {
7024 DRM_INFO("failed to find known CxSR latency "
7025 "(found ddr%s fsb freq %d, mem freq %d), "
7027 (dev_priv
->is_ddr3
== 1) ? "3": "2",
7028 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
7029 /* Disable CxSR and never update its watermark again */
7030 pineview_disable_cxsr(dev
);
7031 dev_priv
->display
.update_wm
= NULL
;
7033 dev_priv
->display
.update_wm
= pineview_update_wm
;
7034 } else if (IS_G4X(dev
))
7035 dev_priv
->display
.update_wm
= g4x_update_wm
;
7036 else if (IS_GEN4(dev
))
7037 dev_priv
->display
.update_wm
= i965_update_wm
;
7038 else if (IS_GEN3(dev
)) {
7039 dev_priv
->display
.update_wm
= i9xx_update_wm
;
7040 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
7041 } else if (IS_I85X(dev
)) {
7042 dev_priv
->display
.update_wm
= i9xx_update_wm
;
7043 dev_priv
->display
.get_fifo_size
= i85x_get_fifo_size
;
7045 dev_priv
->display
.update_wm
= i830_update_wm
;
7047 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
7049 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
7054 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7055 * resume, or other times. This quirk makes sure that's the case for
7058 static void quirk_pipea_force (struct drm_device
*dev
)
7060 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7062 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
7063 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7066 struct intel_quirk
{
7068 int subsystem_vendor
;
7069 int subsystem_device
;
7070 void (*hook
)(struct drm_device
*dev
);
7073 struct intel_quirk intel_quirks
[] = {
7074 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7075 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force
},
7076 /* HP Mini needs pipe A force quirk (LP: #322104) */
7077 { 0x27ae,0x103c, 0x361a, quirk_pipea_force
},
7079 /* Thinkpad R31 needs pipe A force quirk */
7080 { 0x3577, 0x1014, 0x0505, quirk_pipea_force
},
7081 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7082 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
7084 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7085 { 0x3577, 0x1014, 0x0513, quirk_pipea_force
},
7086 /* ThinkPad X40 needs pipe A force quirk */
7088 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7089 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
7091 /* 855 & before need to leave pipe A & dpll A up */
7092 { 0x3582, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
7093 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
7096 static void intel_init_quirks(struct drm_device
*dev
)
7098 struct pci_dev
*d
= dev
->pdev
;
7101 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
7102 struct intel_quirk
*q
= &intel_quirks
[i
];
7104 if (d
->device
== q
->device
&&
7105 (d
->subsystem_vendor
== q
->subsystem_vendor
||
7106 q
->subsystem_vendor
== PCI_ANY_ID
) &&
7107 (d
->subsystem_device
== q
->subsystem_device
||
7108 q
->subsystem_device
== PCI_ANY_ID
))
7113 /* Disable the VGA plane that we never use */
7114 static void i915_disable_vga(struct drm_device
*dev
)
7116 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7120 if (HAS_PCH_SPLIT(dev
))
7121 vga_reg
= CPU_VGACNTRL
;
7125 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
7126 outb(1, VGA_SR_INDEX
);
7127 sr1
= inb(VGA_SR_DATA
);
7128 outb(sr1
| 1<<5, VGA_SR_DATA
);
7129 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
7132 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
7133 POSTING_READ(vga_reg
);
7136 void intel_modeset_init(struct drm_device
*dev
)
7138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7141 drm_mode_config_init(dev
);
7143 dev
->mode_config
.min_width
= 0;
7144 dev
->mode_config
.min_height
= 0;
7146 dev
->mode_config
.funcs
= (void *)&intel_mode_funcs
;
7148 intel_init_quirks(dev
);
7150 intel_init_display(dev
);
7153 dev
->mode_config
.max_width
= 2048;
7154 dev
->mode_config
.max_height
= 2048;
7155 } else if (IS_GEN3(dev
)) {
7156 dev
->mode_config
.max_width
= 4096;
7157 dev
->mode_config
.max_height
= 4096;
7159 dev
->mode_config
.max_width
= 8192;
7160 dev
->mode_config
.max_height
= 8192;
7162 dev
->mode_config
.fb_base
= dev
->agp
->base
;
7164 if (IS_MOBILE(dev
) || !IS_GEN2(dev
))
7165 dev_priv
->num_pipe
= 2;
7167 dev_priv
->num_pipe
= 1;
7168 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7169 dev_priv
->num_pipe
, dev_priv
->num_pipe
> 1 ? "s" : "");
7171 for (i
= 0; i
< dev_priv
->num_pipe
; i
++) {
7172 intel_crtc_init(dev
, i
);
7175 intel_setup_outputs(dev
);
7177 intel_enable_clock_gating(dev
);
7179 /* Just disable it once at startup */
7180 i915_disable_vga(dev
);
7182 if (IS_IRONLAKE_M(dev
)) {
7183 ironlake_enable_drps(dev
);
7184 intel_init_emon(dev
);
7188 gen6_enable_rps(dev_priv
);
7190 if (IS_IRONLAKE_M(dev
)) {
7191 dev_priv
->renderctx
= intel_alloc_context_page(dev
);
7192 if (!dev_priv
->renderctx
)
7194 dev_priv
->pwrctx
= intel_alloc_context_page(dev
);
7195 if (!dev_priv
->pwrctx
) {
7196 i915_gem_object_unpin(dev_priv
->renderctx
);
7197 drm_gem_object_unreference(&dev_priv
->renderctx
->base
);
7198 dev_priv
->renderctx
= NULL
;
7201 ironlake_enable_rc6(dev
);
7205 INIT_WORK(&dev_priv
->idle_work
, intel_idle_update
);
7206 setup_timer(&dev_priv
->idle_timer
, intel_gpu_idle_timer
,
7207 (unsigned long)dev
);
7209 intel_setup_overlay(dev
);
7212 void intel_modeset_cleanup(struct drm_device
*dev
)
7214 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7215 struct drm_crtc
*crtc
;
7216 struct intel_crtc
*intel_crtc
;
7218 drm_kms_helper_poll_fini(dev
);
7219 mutex_lock(&dev
->struct_mutex
);
7221 intel_unregister_dsm_handler();
7224 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7225 /* Skip inactive CRTCs */
7229 intel_crtc
= to_intel_crtc(crtc
);
7230 intel_increase_pllclock(crtc
);
7233 if (dev_priv
->display
.disable_fbc
)
7234 dev_priv
->display
.disable_fbc(dev
);
7236 if (IS_IRONLAKE_M(dev
))
7237 ironlake_disable_drps(dev
);
7239 gen6_disable_rps(dev
);
7241 if (IS_IRONLAKE_M(dev
))
7242 ironlake_disable_rc6(dev
);
7244 mutex_unlock(&dev
->struct_mutex
);
7246 /* Disable the irq before mode object teardown, for the irq might
7247 * enqueue unpin/hotplug work. */
7248 drm_irq_uninstall(dev
);
7249 cancel_work_sync(&dev_priv
->hotplug_work
);
7251 /* Shut off idle work before the crtcs get freed. */
7252 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7253 intel_crtc
= to_intel_crtc(crtc
);
7254 del_timer_sync(&intel_crtc
->idle_timer
);
7256 del_timer_sync(&dev_priv
->idle_timer
);
7257 cancel_work_sync(&dev_priv
->idle_work
);
7259 drm_mode_config_cleanup(dev
);
7263 * Return which encoder is currently attached for connector.
7265 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
7267 return &intel_attached_encoder(connector
)->base
;
7270 void intel_connector_attach_encoder(struct intel_connector
*connector
,
7271 struct intel_encoder
*encoder
)
7273 connector
->encoder
= encoder
;
7274 drm_mode_connector_attach_encoder(&connector
->base
,
7279 * set vga decode state - true == enable VGA decode
7281 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
7283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7286 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
7288 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
7290 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
7291 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
7295 #ifdef CONFIG_DEBUG_FS
7296 #include <linux/seq_file.h>
7298 struct intel_display_error_state
{
7299 struct intel_cursor_error_state
{
7306 struct intel_pipe_error_state
{
7318 struct intel_plane_error_state
{
7329 struct intel_display_error_state
*
7330 intel_display_capture_error_state(struct drm_device
*dev
)
7332 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7333 struct intel_display_error_state
*error
;
7336 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
7340 for (i
= 0; i
< 2; i
++) {
7341 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
7342 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
7343 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
7345 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
7346 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
7347 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
7348 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
7349 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
7350 if (INTEL_INFO(dev
)->gen
>= 4) {
7351 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
7352 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
7355 error
->pipe
[i
].conf
= I915_READ(PIPECONF(i
));
7356 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
7357 error
->pipe
[i
].htotal
= I915_READ(HTOTAL(i
));
7358 error
->pipe
[i
].hblank
= I915_READ(HBLANK(i
));
7359 error
->pipe
[i
].hsync
= I915_READ(HSYNC(i
));
7360 error
->pipe
[i
].vtotal
= I915_READ(VTOTAL(i
));
7361 error
->pipe
[i
].vblank
= I915_READ(VBLANK(i
));
7362 error
->pipe
[i
].vsync
= I915_READ(VSYNC(i
));
7369 intel_display_print_error_state(struct seq_file
*m
,
7370 struct drm_device
*dev
,
7371 struct intel_display_error_state
*error
)
7375 for (i
= 0; i
< 2; i
++) {
7376 seq_printf(m
, "Pipe [%d]:\n", i
);
7377 seq_printf(m
, " CONF: %08x\n", error
->pipe
[i
].conf
);
7378 seq_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
7379 seq_printf(m
, " HTOTAL: %08x\n", error
->pipe
[i
].htotal
);
7380 seq_printf(m
, " HBLANK: %08x\n", error
->pipe
[i
].hblank
);
7381 seq_printf(m
, " HSYNC: %08x\n", error
->pipe
[i
].hsync
);
7382 seq_printf(m
, " VTOTAL: %08x\n", error
->pipe
[i
].vtotal
);
7383 seq_printf(m
, " VBLANK: %08x\n", error
->pipe
[i
].vblank
);
7384 seq_printf(m
, " VSYNC: %08x\n", error
->pipe
[i
].vsync
);
7386 seq_printf(m
, "Plane [%d]:\n", i
);
7387 seq_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
7388 seq_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
7389 seq_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
7390 seq_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
7391 seq_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
7392 if (INTEL_INFO(dev
)->gen
>= 4) {
7393 seq_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
7394 seq_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
7397 seq_printf(m
, "Cursor [%d]:\n", i
);
7398 seq_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
7399 seq_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
7400 seq_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);