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drm/i915: Remove connectors_active from sanitization, v2.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
52 DRM_FORMAT_XRGB1555,
53 DRM_FORMAT_XRGB8888,
54 };
55
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64 };
65
66 static const uint32_t skl_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_ARGB8888,
72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
75 };
76
77 /* Cursor formats */
78 static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80 };
81
82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
83
84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
85 struct intel_crtc_state *pipe_config);
86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
87 struct intel_crtc_state *pipe_config);
88
89 static int intel_framebuffer_init(struct drm_device *dev,
90 struct intel_framebuffer *ifb,
91 struct drm_mode_fb_cmd2 *mode_cmd,
92 struct drm_i915_gem_object *obj);
93 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
94 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
95 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
96 struct intel_link_m_n *m_n,
97 struct intel_link_m_n *m2_n2);
98 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
99 static void haswell_set_pipeconf(struct drm_crtc *crtc);
100 static void intel_set_pipe_csc(struct drm_crtc *crtc);
101 static void vlv_prepare_pll(struct intel_crtc *crtc,
102 const struct intel_crtc_state *pipe_config);
103 static void chv_prepare_pll(struct intel_crtc *crtc,
104 const struct intel_crtc_state *pipe_config);
105 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
106 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
107 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
108 struct intel_crtc_state *crtc_state);
109 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
110 int num_connectors);
111 static void intel_modeset_setup_hw_state(struct drm_device *dev);
112
113 typedef struct {
114 int min, max;
115 } intel_range_t;
116
117 typedef struct {
118 int dot_limit;
119 int p2_slow, p2_fast;
120 } intel_p2_t;
121
122 typedef struct intel_limit intel_limit_t;
123 struct intel_limit {
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
126 };
127
128 int
129 intel_pch_rawclk(struct drm_device *dev)
130 {
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136 }
137
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
140 {
141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
146 }
147
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
159 };
160
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172 };
173
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
185 };
186
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
211 };
212
213
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
226 },
227 };
228
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
253 },
254 };
255
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
267 },
268 };
269
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
283 };
284
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
296 };
297
298 /* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
314 };
315
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 };
328
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340 };
341
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
354 };
355
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
367 };
368
369 static const intel_limit_t intel_limits_vlv = {
370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
383 };
384
385 static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4800000, .max = 6480000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399 };
400
401 static const intel_limit_t intel_limits_bxt = {
402 /* FIXME: find real dot limits */
403 .dot = { .min = 0, .max = INT_MAX },
404 .vco = { .min = 4800000, .max = 6700000 },
405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 /* FIXME: find real m2 limits */
408 .m2 = { .min = 2 << 22, .max = 255 << 22 },
409 .p1 = { .min = 2, .max = 4 },
410 .p2 = { .p2_slow = 1, .p2_fast = 20 },
411 };
412
413 static bool
414 needs_modeset(struct drm_crtc_state *state)
415 {
416 return drm_atomic_crtc_needs_modeset(state);
417 }
418
419 /**
420 * Returns whether any output on the specified pipe is of the specified type
421 */
422 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
423 {
424 struct drm_device *dev = crtc->base.dev;
425 struct intel_encoder *encoder;
426
427 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
428 if (encoder->type == type)
429 return true;
430
431 return false;
432 }
433
434 /**
435 * Returns whether any output on the specified pipe will have the specified
436 * type after a staged modeset is complete, i.e., the same as
437 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
438 * encoder->crtc.
439 */
440 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
441 int type)
442 {
443 struct drm_atomic_state *state = crtc_state->base.state;
444 struct drm_connector *connector;
445 struct drm_connector_state *connector_state;
446 struct intel_encoder *encoder;
447 int i, num_connectors = 0;
448
449 for_each_connector_in_state(state, connector, connector_state, i) {
450 if (connector_state->crtc != crtc_state->base.crtc)
451 continue;
452
453 num_connectors++;
454
455 encoder = to_intel_encoder(connector_state->best_encoder);
456 if (encoder->type == type)
457 return true;
458 }
459
460 WARN_ON(num_connectors == 0);
461
462 return false;
463 }
464
465 static const intel_limit_t *
466 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
467 {
468 struct drm_device *dev = crtc_state->base.crtc->dev;
469 const intel_limit_t *limit;
470
471 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
472 if (intel_is_dual_link_lvds(dev)) {
473 if (refclk == 100000)
474 limit = &intel_limits_ironlake_dual_lvds_100m;
475 else
476 limit = &intel_limits_ironlake_dual_lvds;
477 } else {
478 if (refclk == 100000)
479 limit = &intel_limits_ironlake_single_lvds_100m;
480 else
481 limit = &intel_limits_ironlake_single_lvds;
482 }
483 } else
484 limit = &intel_limits_ironlake_dac;
485
486 return limit;
487 }
488
489 static const intel_limit_t *
490 intel_g4x_limit(struct intel_crtc_state *crtc_state)
491 {
492 struct drm_device *dev = crtc_state->base.crtc->dev;
493 const intel_limit_t *limit;
494
495 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
496 if (intel_is_dual_link_lvds(dev))
497 limit = &intel_limits_g4x_dual_channel_lvds;
498 else
499 limit = &intel_limits_g4x_single_channel_lvds;
500 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
501 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
502 limit = &intel_limits_g4x_hdmi;
503 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
504 limit = &intel_limits_g4x_sdvo;
505 } else /* The option is for other outputs */
506 limit = &intel_limits_i9xx_sdvo;
507
508 return limit;
509 }
510
511 static const intel_limit_t *
512 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
513 {
514 struct drm_device *dev = crtc_state->base.crtc->dev;
515 const intel_limit_t *limit;
516
517 if (IS_BROXTON(dev))
518 limit = &intel_limits_bxt;
519 else if (HAS_PCH_SPLIT(dev))
520 limit = intel_ironlake_limit(crtc_state, refclk);
521 else if (IS_G4X(dev)) {
522 limit = intel_g4x_limit(crtc_state);
523 } else if (IS_PINEVIEW(dev)) {
524 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
525 limit = &intel_limits_pineview_lvds;
526 else
527 limit = &intel_limits_pineview_sdvo;
528 } else if (IS_CHERRYVIEW(dev)) {
529 limit = &intel_limits_chv;
530 } else if (IS_VALLEYVIEW(dev)) {
531 limit = &intel_limits_vlv;
532 } else if (!IS_GEN2(dev)) {
533 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
534 limit = &intel_limits_i9xx_lvds;
535 else
536 limit = &intel_limits_i9xx_sdvo;
537 } else {
538 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
539 limit = &intel_limits_i8xx_lvds;
540 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
541 limit = &intel_limits_i8xx_dvo;
542 else
543 limit = &intel_limits_i8xx_dac;
544 }
545 return limit;
546 }
547
548 /*
549 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
550 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
551 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
552 * The helpers' return value is the rate of the clock that is fed to the
553 * display engine's pipe which can be the above fast dot clock rate or a
554 * divided-down version of it.
555 */
556 /* m1 is reserved as 0 in Pineview, n is a ring counter */
557 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
558 {
559 clock->m = clock->m2 + 2;
560 clock->p = clock->p1 * clock->p2;
561 if (WARN_ON(clock->n == 0 || clock->p == 0))
562 return 0;
563 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
564 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
565
566 return clock->dot;
567 }
568
569 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
570 {
571 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
572 }
573
574 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
575 {
576 clock->m = i9xx_dpll_compute_m(clock);
577 clock->p = clock->p1 * clock->p2;
578 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
579 return 0;
580 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
581 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
582
583 return clock->dot;
584 }
585
586 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
587 {
588 clock->m = clock->m1 * clock->m2;
589 clock->p = clock->p1 * clock->p2;
590 if (WARN_ON(clock->n == 0 || clock->p == 0))
591 return 0;
592 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
593 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
594
595 return clock->dot / 5;
596 }
597
598 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
599 {
600 clock->m = clock->m1 * clock->m2;
601 clock->p = clock->p1 * clock->p2;
602 if (WARN_ON(clock->n == 0 || clock->p == 0))
603 return 0;
604 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
605 clock->n << 22);
606 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
607
608 return clock->dot / 5;
609 }
610
611 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
612 /**
613 * Returns whether the given set of divisors are valid for a given refclk with
614 * the given connectors.
615 */
616
617 static bool intel_PLL_is_valid(struct drm_device *dev,
618 const intel_limit_t *limit,
619 const intel_clock_t *clock)
620 {
621 if (clock->n < limit->n.min || limit->n.max < clock->n)
622 INTELPllInvalid("n out of range\n");
623 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
624 INTELPllInvalid("p1 out of range\n");
625 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
626 INTELPllInvalid("m2 out of range\n");
627 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
628 INTELPllInvalid("m1 out of range\n");
629
630 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
631 if (clock->m1 <= clock->m2)
632 INTELPllInvalid("m1 <= m2\n");
633
634 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
635 if (clock->p < limit->p.min || limit->p.max < clock->p)
636 INTELPllInvalid("p out of range\n");
637 if (clock->m < limit->m.min || limit->m.max < clock->m)
638 INTELPllInvalid("m out of range\n");
639 }
640
641 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
642 INTELPllInvalid("vco out of range\n");
643 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
644 * connector, etc., rather than just a single range.
645 */
646 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
647 INTELPllInvalid("dot out of range\n");
648
649 return true;
650 }
651
652 static int
653 i9xx_select_p2_div(const intel_limit_t *limit,
654 const struct intel_crtc_state *crtc_state,
655 int target)
656 {
657 struct drm_device *dev = crtc_state->base.crtc->dev;
658
659 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
660 /*
661 * For LVDS just rely on its current settings for dual-channel.
662 * We haven't figured out how to reliably set up different
663 * single/dual channel state, if we even can.
664 */
665 if (intel_is_dual_link_lvds(dev))
666 return limit->p2.p2_fast;
667 else
668 return limit->p2.p2_slow;
669 } else {
670 if (target < limit->p2.dot_limit)
671 return limit->p2.p2_slow;
672 else
673 return limit->p2.p2_fast;
674 }
675 }
676
677 static bool
678 i9xx_find_best_dpll(const intel_limit_t *limit,
679 struct intel_crtc_state *crtc_state,
680 int target, int refclk, intel_clock_t *match_clock,
681 intel_clock_t *best_clock)
682 {
683 struct drm_device *dev = crtc_state->base.crtc->dev;
684 intel_clock_t clock;
685 int err = target;
686
687 memset(best_clock, 0, sizeof(*best_clock));
688
689 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
690
691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
692 clock.m1++) {
693 for (clock.m2 = limit->m2.min;
694 clock.m2 <= limit->m2.max; clock.m2++) {
695 if (clock.m2 >= clock.m1)
696 break;
697 for (clock.n = limit->n.min;
698 clock.n <= limit->n.max; clock.n++) {
699 for (clock.p1 = limit->p1.min;
700 clock.p1 <= limit->p1.max; clock.p1++) {
701 int this_err;
702
703 i9xx_calc_dpll_params(refclk, &clock);
704 if (!intel_PLL_is_valid(dev, limit,
705 &clock))
706 continue;
707 if (match_clock &&
708 clock.p != match_clock->p)
709 continue;
710
711 this_err = abs(clock.dot - target);
712 if (this_err < err) {
713 *best_clock = clock;
714 err = this_err;
715 }
716 }
717 }
718 }
719 }
720
721 return (err != target);
722 }
723
724 static bool
725 pnv_find_best_dpll(const intel_limit_t *limit,
726 struct intel_crtc_state *crtc_state,
727 int target, int refclk, intel_clock_t *match_clock,
728 intel_clock_t *best_clock)
729 {
730 struct drm_device *dev = crtc_state->base.crtc->dev;
731 intel_clock_t clock;
732 int err = target;
733
734 memset(best_clock, 0, sizeof(*best_clock));
735
736 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
737
738 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
739 clock.m1++) {
740 for (clock.m2 = limit->m2.min;
741 clock.m2 <= limit->m2.max; clock.m2++) {
742 for (clock.n = limit->n.min;
743 clock.n <= limit->n.max; clock.n++) {
744 for (clock.p1 = limit->p1.min;
745 clock.p1 <= limit->p1.max; clock.p1++) {
746 int this_err;
747
748 pnv_calc_dpll_params(refclk, &clock);
749 if (!intel_PLL_is_valid(dev, limit,
750 &clock))
751 continue;
752 if (match_clock &&
753 clock.p != match_clock->p)
754 continue;
755
756 this_err = abs(clock.dot - target);
757 if (this_err < err) {
758 *best_clock = clock;
759 err = this_err;
760 }
761 }
762 }
763 }
764 }
765
766 return (err != target);
767 }
768
769 static bool
770 g4x_find_best_dpll(const intel_limit_t *limit,
771 struct intel_crtc_state *crtc_state,
772 int target, int refclk, intel_clock_t *match_clock,
773 intel_clock_t *best_clock)
774 {
775 struct drm_device *dev = crtc_state->base.crtc->dev;
776 intel_clock_t clock;
777 int max_n;
778 bool found = false;
779 /* approximately equals target * 0.00585 */
780 int err_most = (target >> 8) + (target >> 9);
781
782 memset(best_clock, 0, sizeof(*best_clock));
783
784 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
785
786 max_n = limit->n.max;
787 /* based on hardware requirement, prefer smaller n to precision */
788 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
789 /* based on hardware requirement, prefere larger m1,m2 */
790 for (clock.m1 = limit->m1.max;
791 clock.m1 >= limit->m1.min; clock.m1--) {
792 for (clock.m2 = limit->m2.max;
793 clock.m2 >= limit->m2.min; clock.m2--) {
794 for (clock.p1 = limit->p1.max;
795 clock.p1 >= limit->p1.min; clock.p1--) {
796 int this_err;
797
798 i9xx_calc_dpll_params(refclk, &clock);
799 if (!intel_PLL_is_valid(dev, limit,
800 &clock))
801 continue;
802
803 this_err = abs(clock.dot - target);
804 if (this_err < err_most) {
805 *best_clock = clock;
806 err_most = this_err;
807 max_n = clock.n;
808 found = true;
809 }
810 }
811 }
812 }
813 }
814 return found;
815 }
816
817 /*
818 * Check if the calculated PLL configuration is more optimal compared to the
819 * best configuration and error found so far. Return the calculated error.
820 */
821 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
822 const intel_clock_t *calculated_clock,
823 const intel_clock_t *best_clock,
824 unsigned int best_error_ppm,
825 unsigned int *error_ppm)
826 {
827 /*
828 * For CHV ignore the error and consider only the P value.
829 * Prefer a bigger P value based on HW requirements.
830 */
831 if (IS_CHERRYVIEW(dev)) {
832 *error_ppm = 0;
833
834 return calculated_clock->p > best_clock->p;
835 }
836
837 if (WARN_ON_ONCE(!target_freq))
838 return false;
839
840 *error_ppm = div_u64(1000000ULL *
841 abs(target_freq - calculated_clock->dot),
842 target_freq);
843 /*
844 * Prefer a better P value over a better (smaller) error if the error
845 * is small. Ensure this preference for future configurations too by
846 * setting the error to 0.
847 */
848 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
849 *error_ppm = 0;
850
851 return true;
852 }
853
854 return *error_ppm + 10 < best_error_ppm;
855 }
856
857 static bool
858 vlv_find_best_dpll(const intel_limit_t *limit,
859 struct intel_crtc_state *crtc_state,
860 int target, int refclk, intel_clock_t *match_clock,
861 intel_clock_t *best_clock)
862 {
863 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
864 struct drm_device *dev = crtc->base.dev;
865 intel_clock_t clock;
866 unsigned int bestppm = 1000000;
867 /* min update 19.2 MHz */
868 int max_n = min(limit->n.max, refclk / 19200);
869 bool found = false;
870
871 target *= 5; /* fast clock */
872
873 memset(best_clock, 0, sizeof(*best_clock));
874
875 /* based on hardware requirement, prefer smaller n to precision */
876 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
877 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
878 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
879 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
880 clock.p = clock.p1 * clock.p2;
881 /* based on hardware requirement, prefer bigger m1,m2 values */
882 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
883 unsigned int ppm;
884
885 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
886 refclk * clock.m1);
887
888 vlv_calc_dpll_params(refclk, &clock);
889
890 if (!intel_PLL_is_valid(dev, limit,
891 &clock))
892 continue;
893
894 if (!vlv_PLL_is_optimal(dev, target,
895 &clock,
896 best_clock,
897 bestppm, &ppm))
898 continue;
899
900 *best_clock = clock;
901 bestppm = ppm;
902 found = true;
903 }
904 }
905 }
906 }
907
908 return found;
909 }
910
911 static bool
912 chv_find_best_dpll(const intel_limit_t *limit,
913 struct intel_crtc_state *crtc_state,
914 int target, int refclk, intel_clock_t *match_clock,
915 intel_clock_t *best_clock)
916 {
917 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
918 struct drm_device *dev = crtc->base.dev;
919 unsigned int best_error_ppm;
920 intel_clock_t clock;
921 uint64_t m2;
922 int found = false;
923
924 memset(best_clock, 0, sizeof(*best_clock));
925 best_error_ppm = 1000000;
926
927 /*
928 * Based on hardware doc, the n always set to 1, and m1 always
929 * set to 2. If requires to support 200Mhz refclk, we need to
930 * revisit this because n may not 1 anymore.
931 */
932 clock.n = 1, clock.m1 = 2;
933 target *= 5; /* fast clock */
934
935 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
936 for (clock.p2 = limit->p2.p2_fast;
937 clock.p2 >= limit->p2.p2_slow;
938 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
939 unsigned int error_ppm;
940
941 clock.p = clock.p1 * clock.p2;
942
943 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
944 clock.n) << 22, refclk * clock.m1);
945
946 if (m2 > INT_MAX/clock.m1)
947 continue;
948
949 clock.m2 = m2;
950
951 chv_calc_dpll_params(refclk, &clock);
952
953 if (!intel_PLL_is_valid(dev, limit, &clock))
954 continue;
955
956 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
957 best_error_ppm, &error_ppm))
958 continue;
959
960 *best_clock = clock;
961 best_error_ppm = error_ppm;
962 found = true;
963 }
964 }
965
966 return found;
967 }
968
969 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
970 intel_clock_t *best_clock)
971 {
972 int refclk = i9xx_get_refclk(crtc_state, 0);
973
974 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
975 target_clock, refclk, NULL, best_clock);
976 }
977
978 bool intel_crtc_active(struct drm_crtc *crtc)
979 {
980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
981
982 /* Be paranoid as we can arrive here with only partial
983 * state retrieved from the hardware during setup.
984 *
985 * We can ditch the adjusted_mode.crtc_clock check as soon
986 * as Haswell has gained clock readout/fastboot support.
987 *
988 * We can ditch the crtc->primary->fb check as soon as we can
989 * properly reconstruct framebuffers.
990 *
991 * FIXME: The intel_crtc->active here should be switched to
992 * crtc->state->active once we have proper CRTC states wired up
993 * for atomic.
994 */
995 return intel_crtc->active && crtc->primary->state->fb &&
996 intel_crtc->config->base.adjusted_mode.crtc_clock;
997 }
998
999 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1000 enum pipe pipe)
1001 {
1002 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1004
1005 return intel_crtc->config->cpu_transcoder;
1006 }
1007
1008 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1009 {
1010 struct drm_i915_private *dev_priv = dev->dev_private;
1011 u32 reg = PIPEDSL(pipe);
1012 u32 line1, line2;
1013 u32 line_mask;
1014
1015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
1020 line1 = I915_READ(reg) & line_mask;
1021 msleep(5);
1022 line2 = I915_READ(reg) & line_mask;
1023
1024 return line1 == line2;
1025 }
1026
1027 /*
1028 * intel_wait_for_pipe_off - wait for pipe to turn off
1029 * @crtc: crtc whose pipe to wait for
1030 *
1031 * After disabling a pipe, we can't wait for vblank in the usual way,
1032 * spinning on the vblank interrupt status bit, since we won't actually
1033 * see an interrupt when the pipe is disabled.
1034 *
1035 * On Gen4 and above:
1036 * wait for the pipe register state bit to turn off
1037 *
1038 * Otherwise:
1039 * wait for the display line value to settle (it usually
1040 * ends up stopping at the start of the next frame).
1041 *
1042 */
1043 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1044 {
1045 struct drm_device *dev = crtc->base.dev;
1046 struct drm_i915_private *dev_priv = dev->dev_private;
1047 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1048 enum pipe pipe = crtc->pipe;
1049
1050 if (INTEL_INFO(dev)->gen >= 4) {
1051 int reg = PIPECONF(cpu_transcoder);
1052
1053 /* Wait for the Pipe State to go off */
1054 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1055 100))
1056 WARN(1, "pipe_off wait timed out\n");
1057 } else {
1058 /* Wait for the display line to settle */
1059 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1060 WARN(1, "pipe_off wait timed out\n");
1061 }
1062 }
1063
1064 /*
1065 * ibx_digital_port_connected - is the specified port connected?
1066 * @dev_priv: i915 private structure
1067 * @port: the port to test
1068 *
1069 * Returns true if @port is connected, false otherwise.
1070 */
1071 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1072 struct intel_digital_port *port)
1073 {
1074 u32 bit;
1075
1076 if (HAS_PCH_IBX(dev_priv->dev)) {
1077 switch (port->port) {
1078 case PORT_B:
1079 bit = SDE_PORTB_HOTPLUG;
1080 break;
1081 case PORT_C:
1082 bit = SDE_PORTC_HOTPLUG;
1083 break;
1084 case PORT_D:
1085 bit = SDE_PORTD_HOTPLUG;
1086 break;
1087 default:
1088 return true;
1089 }
1090 } else {
1091 switch (port->port) {
1092 case PORT_B:
1093 bit = SDE_PORTB_HOTPLUG_CPT;
1094 break;
1095 case PORT_C:
1096 bit = SDE_PORTC_HOTPLUG_CPT;
1097 break;
1098 case PORT_D:
1099 bit = SDE_PORTD_HOTPLUG_CPT;
1100 break;
1101 default:
1102 return true;
1103 }
1104 }
1105
1106 return I915_READ(SDEISR) & bit;
1107 }
1108
1109 static const char *state_string(bool enabled)
1110 {
1111 return enabled ? "on" : "off";
1112 }
1113
1114 /* Only for pre-ILK configs */
1115 void assert_pll(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1117 {
1118 int reg;
1119 u32 val;
1120 bool cur_state;
1121
1122 reg = DPLL(pipe);
1123 val = I915_READ(reg);
1124 cur_state = !!(val & DPLL_VCO_ENABLE);
1125 I915_STATE_WARN(cur_state != state,
1126 "PLL state assertion failure (expected %s, current %s)\n",
1127 state_string(state), state_string(cur_state));
1128 }
1129
1130 /* XXX: the dsi pll is shared between MIPI DSI ports */
1131 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1132 {
1133 u32 val;
1134 bool cur_state;
1135
1136 mutex_lock(&dev_priv->sb_lock);
1137 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1138 mutex_unlock(&dev_priv->sb_lock);
1139
1140 cur_state = val & DSI_PLL_VCO_EN;
1141 I915_STATE_WARN(cur_state != state,
1142 "DSI PLL state assertion failure (expected %s, current %s)\n",
1143 state_string(state), state_string(cur_state));
1144 }
1145 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1146 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1147
1148 struct intel_shared_dpll *
1149 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1150 {
1151 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1152
1153 if (crtc->config->shared_dpll < 0)
1154 return NULL;
1155
1156 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1157 }
1158
1159 /* For ILK+ */
1160 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1161 struct intel_shared_dpll *pll,
1162 bool state)
1163 {
1164 bool cur_state;
1165 struct intel_dpll_hw_state hw_state;
1166
1167 if (WARN (!pll,
1168 "asserting DPLL %s with no DPLL\n", state_string(state)))
1169 return;
1170
1171 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1172 I915_STATE_WARN(cur_state != state,
1173 "%s assertion failure (expected %s, current %s)\n",
1174 pll->name, state_string(state), state_string(cur_state));
1175 }
1176
1177 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1178 enum pipe pipe, bool state)
1179 {
1180 int reg;
1181 u32 val;
1182 bool cur_state;
1183 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1184 pipe);
1185
1186 if (HAS_DDI(dev_priv->dev)) {
1187 /* DDI does not have a specific FDI_TX register */
1188 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1189 val = I915_READ(reg);
1190 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1191 } else {
1192 reg = FDI_TX_CTL(pipe);
1193 val = I915_READ(reg);
1194 cur_state = !!(val & FDI_TX_ENABLE);
1195 }
1196 I915_STATE_WARN(cur_state != state,
1197 "FDI TX state assertion failure (expected %s, current %s)\n",
1198 state_string(state), state_string(cur_state));
1199 }
1200 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1201 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1202
1203 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1204 enum pipe pipe, bool state)
1205 {
1206 int reg;
1207 u32 val;
1208 bool cur_state;
1209
1210 reg = FDI_RX_CTL(pipe);
1211 val = I915_READ(reg);
1212 cur_state = !!(val & FDI_RX_ENABLE);
1213 I915_STATE_WARN(cur_state != state,
1214 "FDI RX state assertion failure (expected %s, current %s)\n",
1215 state_string(state), state_string(cur_state));
1216 }
1217 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1218 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1219
1220 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1221 enum pipe pipe)
1222 {
1223 int reg;
1224 u32 val;
1225
1226 /* ILK FDI PLL is always enabled */
1227 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1228 return;
1229
1230 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1231 if (HAS_DDI(dev_priv->dev))
1232 return;
1233
1234 reg = FDI_TX_CTL(pipe);
1235 val = I915_READ(reg);
1236 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1237 }
1238
1239 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, bool state)
1241 {
1242 int reg;
1243 u32 val;
1244 bool cur_state;
1245
1246 reg = FDI_RX_CTL(pipe);
1247 val = I915_READ(reg);
1248 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1249 I915_STATE_WARN(cur_state != state,
1250 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1251 state_string(state), state_string(cur_state));
1252 }
1253
1254 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1255 enum pipe pipe)
1256 {
1257 struct drm_device *dev = dev_priv->dev;
1258 int pp_reg;
1259 u32 val;
1260 enum pipe panel_pipe = PIPE_A;
1261 bool locked = true;
1262
1263 if (WARN_ON(HAS_DDI(dev)))
1264 return;
1265
1266 if (HAS_PCH_SPLIT(dev)) {
1267 u32 port_sel;
1268
1269 pp_reg = PCH_PP_CONTROL;
1270 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1271
1272 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1273 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1274 panel_pipe = PIPE_B;
1275 /* XXX: else fix for eDP */
1276 } else if (IS_VALLEYVIEW(dev)) {
1277 /* presumably write lock depends on pipe, not port select */
1278 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1279 panel_pipe = pipe;
1280 } else {
1281 pp_reg = PP_CONTROL;
1282 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1283 panel_pipe = PIPE_B;
1284 }
1285
1286 val = I915_READ(pp_reg);
1287 if (!(val & PANEL_POWER_ON) ||
1288 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1289 locked = false;
1290
1291 I915_STATE_WARN(panel_pipe == pipe && locked,
1292 "panel assertion failure, pipe %c regs locked\n",
1293 pipe_name(pipe));
1294 }
1295
1296 static void assert_cursor(struct drm_i915_private *dev_priv,
1297 enum pipe pipe, bool state)
1298 {
1299 struct drm_device *dev = dev_priv->dev;
1300 bool cur_state;
1301
1302 if (IS_845G(dev) || IS_I865G(dev))
1303 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1304 else
1305 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1306
1307 I915_STATE_WARN(cur_state != state,
1308 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1309 pipe_name(pipe), state_string(state), state_string(cur_state));
1310 }
1311 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1312 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1313
1314 void assert_pipe(struct drm_i915_private *dev_priv,
1315 enum pipe pipe, bool state)
1316 {
1317 int reg;
1318 u32 val;
1319 bool cur_state;
1320 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1321 pipe);
1322
1323 /* if we need the pipe quirk it must be always on */
1324 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1325 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1326 state = true;
1327
1328 if (!intel_display_power_is_enabled(dev_priv,
1329 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1330 cur_state = false;
1331 } else {
1332 reg = PIPECONF(cpu_transcoder);
1333 val = I915_READ(reg);
1334 cur_state = !!(val & PIPECONF_ENABLE);
1335 }
1336
1337 I915_STATE_WARN(cur_state != state,
1338 "pipe %c assertion failure (expected %s, current %s)\n",
1339 pipe_name(pipe), state_string(state), state_string(cur_state));
1340 }
1341
1342 static void assert_plane(struct drm_i915_private *dev_priv,
1343 enum plane plane, bool state)
1344 {
1345 int reg;
1346 u32 val;
1347 bool cur_state;
1348
1349 reg = DSPCNTR(plane);
1350 val = I915_READ(reg);
1351 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1352 I915_STATE_WARN(cur_state != state,
1353 "plane %c assertion failure (expected %s, current %s)\n",
1354 plane_name(plane), state_string(state), state_string(cur_state));
1355 }
1356
1357 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1358 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1359
1360 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1361 enum pipe pipe)
1362 {
1363 struct drm_device *dev = dev_priv->dev;
1364 int reg, i;
1365 u32 val;
1366 int cur_pipe;
1367
1368 /* Primary planes are fixed to pipes on gen4+ */
1369 if (INTEL_INFO(dev)->gen >= 4) {
1370 reg = DSPCNTR(pipe);
1371 val = I915_READ(reg);
1372 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1373 "plane %c assertion failure, should be disabled but not\n",
1374 plane_name(pipe));
1375 return;
1376 }
1377
1378 /* Need to check both planes against the pipe */
1379 for_each_pipe(dev_priv, i) {
1380 reg = DSPCNTR(i);
1381 val = I915_READ(reg);
1382 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1383 DISPPLANE_SEL_PIPE_SHIFT;
1384 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1385 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1386 plane_name(i), pipe_name(pipe));
1387 }
1388 }
1389
1390 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1391 enum pipe pipe)
1392 {
1393 struct drm_device *dev = dev_priv->dev;
1394 int reg, sprite;
1395 u32 val;
1396
1397 if (INTEL_INFO(dev)->gen >= 9) {
1398 for_each_sprite(dev_priv, pipe, sprite) {
1399 val = I915_READ(PLANE_CTL(pipe, sprite));
1400 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1401 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1402 sprite, pipe_name(pipe));
1403 }
1404 } else if (IS_VALLEYVIEW(dev)) {
1405 for_each_sprite(dev_priv, pipe, sprite) {
1406 reg = SPCNTR(pipe, sprite);
1407 val = I915_READ(reg);
1408 I915_STATE_WARN(val & SP_ENABLE,
1409 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1410 sprite_name(pipe, sprite), pipe_name(pipe));
1411 }
1412 } else if (INTEL_INFO(dev)->gen >= 7) {
1413 reg = SPRCTL(pipe);
1414 val = I915_READ(reg);
1415 I915_STATE_WARN(val & SPRITE_ENABLE,
1416 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1417 plane_name(pipe), pipe_name(pipe));
1418 } else if (INTEL_INFO(dev)->gen >= 5) {
1419 reg = DVSCNTR(pipe);
1420 val = I915_READ(reg);
1421 I915_STATE_WARN(val & DVS_ENABLE,
1422 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1423 plane_name(pipe), pipe_name(pipe));
1424 }
1425 }
1426
1427 static void assert_vblank_disabled(struct drm_crtc *crtc)
1428 {
1429 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1430 drm_crtc_vblank_put(crtc);
1431 }
1432
1433 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1434 {
1435 u32 val;
1436 bool enabled;
1437
1438 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1439
1440 val = I915_READ(PCH_DREF_CONTROL);
1441 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1442 DREF_SUPERSPREAD_SOURCE_MASK));
1443 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1444 }
1445
1446 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1447 enum pipe pipe)
1448 {
1449 int reg;
1450 u32 val;
1451 bool enabled;
1452
1453 reg = PCH_TRANSCONF(pipe);
1454 val = I915_READ(reg);
1455 enabled = !!(val & TRANS_ENABLE);
1456 I915_STATE_WARN(enabled,
1457 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1458 pipe_name(pipe));
1459 }
1460
1461 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1462 enum pipe pipe, u32 port_sel, u32 val)
1463 {
1464 if ((val & DP_PORT_EN) == 0)
1465 return false;
1466
1467 if (HAS_PCH_CPT(dev_priv->dev)) {
1468 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1469 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1470 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1471 return false;
1472 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1473 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1474 return false;
1475 } else {
1476 if ((val & DP_PIPE_MASK) != (pipe << 30))
1477 return false;
1478 }
1479 return true;
1480 }
1481
1482 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1483 enum pipe pipe, u32 val)
1484 {
1485 if ((val & SDVO_ENABLE) == 0)
1486 return false;
1487
1488 if (HAS_PCH_CPT(dev_priv->dev)) {
1489 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1490 return false;
1491 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1492 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1493 return false;
1494 } else {
1495 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1496 return false;
1497 }
1498 return true;
1499 }
1500
1501 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1502 enum pipe pipe, u32 val)
1503 {
1504 if ((val & LVDS_PORT_EN) == 0)
1505 return false;
1506
1507 if (HAS_PCH_CPT(dev_priv->dev)) {
1508 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1509 return false;
1510 } else {
1511 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1512 return false;
1513 }
1514 return true;
1515 }
1516
1517 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1518 enum pipe pipe, u32 val)
1519 {
1520 if ((val & ADPA_DAC_ENABLE) == 0)
1521 return false;
1522 if (HAS_PCH_CPT(dev_priv->dev)) {
1523 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1524 return false;
1525 } else {
1526 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1527 return false;
1528 }
1529 return true;
1530 }
1531
1532 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1533 enum pipe pipe, int reg, u32 port_sel)
1534 {
1535 u32 val = I915_READ(reg);
1536 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1537 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1538 reg, pipe_name(pipe));
1539
1540 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1541 && (val & DP_PIPEB_SELECT),
1542 "IBX PCH dp port still using transcoder B\n");
1543 }
1544
1545 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1546 enum pipe pipe, int reg)
1547 {
1548 u32 val = I915_READ(reg);
1549 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1550 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1551 reg, pipe_name(pipe));
1552
1553 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1554 && (val & SDVO_PIPE_B_SELECT),
1555 "IBX PCH hdmi port still using transcoder B\n");
1556 }
1557
1558 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1559 enum pipe pipe)
1560 {
1561 int reg;
1562 u32 val;
1563
1564 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1565 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1566 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1567
1568 reg = PCH_ADPA;
1569 val = I915_READ(reg);
1570 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1571 "PCH VGA enabled on transcoder %c, should be disabled\n",
1572 pipe_name(pipe));
1573
1574 reg = PCH_LVDS;
1575 val = I915_READ(reg);
1576 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1577 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1578 pipe_name(pipe));
1579
1580 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1581 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1582 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1583 }
1584
1585 static void intel_init_dpio(struct drm_device *dev)
1586 {
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1588
1589 if (!IS_VALLEYVIEW(dev))
1590 return;
1591
1592 /*
1593 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1594 * CHV x1 PHY (DP/HDMI D)
1595 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1596 */
1597 if (IS_CHERRYVIEW(dev)) {
1598 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1599 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1600 } else {
1601 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1602 }
1603 }
1604
1605 static void vlv_enable_pll(struct intel_crtc *crtc,
1606 const struct intel_crtc_state *pipe_config)
1607 {
1608 struct drm_device *dev = crtc->base.dev;
1609 struct drm_i915_private *dev_priv = dev->dev_private;
1610 int reg = DPLL(crtc->pipe);
1611 u32 dpll = pipe_config->dpll_hw_state.dpll;
1612
1613 assert_pipe_disabled(dev_priv, crtc->pipe);
1614
1615 /* No really, not for ILK+ */
1616 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1617
1618 /* PLL is protected by panel, make sure we can write it */
1619 if (IS_MOBILE(dev_priv->dev))
1620 assert_panel_unlocked(dev_priv, crtc->pipe);
1621
1622 I915_WRITE(reg, dpll);
1623 POSTING_READ(reg);
1624 udelay(150);
1625
1626 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1627 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1628
1629 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1630 POSTING_READ(DPLL_MD(crtc->pipe));
1631
1632 /* We do this three times for luck */
1633 I915_WRITE(reg, dpll);
1634 POSTING_READ(reg);
1635 udelay(150); /* wait for warmup */
1636 I915_WRITE(reg, dpll);
1637 POSTING_READ(reg);
1638 udelay(150); /* wait for warmup */
1639 I915_WRITE(reg, dpll);
1640 POSTING_READ(reg);
1641 udelay(150); /* wait for warmup */
1642 }
1643
1644 static void chv_enable_pll(struct intel_crtc *crtc,
1645 const struct intel_crtc_state *pipe_config)
1646 {
1647 struct drm_device *dev = crtc->base.dev;
1648 struct drm_i915_private *dev_priv = dev->dev_private;
1649 int pipe = crtc->pipe;
1650 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1651 u32 tmp;
1652
1653 assert_pipe_disabled(dev_priv, crtc->pipe);
1654
1655 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1656
1657 mutex_lock(&dev_priv->sb_lock);
1658
1659 /* Enable back the 10bit clock to display controller */
1660 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1661 tmp |= DPIO_DCLKP_EN;
1662 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1663
1664 mutex_unlock(&dev_priv->sb_lock);
1665
1666 /*
1667 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1668 */
1669 udelay(1);
1670
1671 /* Enable PLL */
1672 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1673
1674 /* Check PLL is locked */
1675 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1676 DRM_ERROR("PLL %d failed to lock\n", pipe);
1677
1678 /* not sure when this should be written */
1679 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1680 POSTING_READ(DPLL_MD(pipe));
1681 }
1682
1683 static int intel_num_dvo_pipes(struct drm_device *dev)
1684 {
1685 struct intel_crtc *crtc;
1686 int count = 0;
1687
1688 for_each_intel_crtc(dev, crtc)
1689 count += crtc->base.state->active &&
1690 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1691
1692 return count;
1693 }
1694
1695 static void i9xx_enable_pll(struct intel_crtc *crtc)
1696 {
1697 struct drm_device *dev = crtc->base.dev;
1698 struct drm_i915_private *dev_priv = dev->dev_private;
1699 int reg = DPLL(crtc->pipe);
1700 u32 dpll = crtc->config->dpll_hw_state.dpll;
1701
1702 assert_pipe_disabled(dev_priv, crtc->pipe);
1703
1704 /* No really, not for ILK+ */
1705 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1706
1707 /* PLL is protected by panel, make sure we can write it */
1708 if (IS_MOBILE(dev) && !IS_I830(dev))
1709 assert_panel_unlocked(dev_priv, crtc->pipe);
1710
1711 /* Enable DVO 2x clock on both PLLs if necessary */
1712 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1713 /*
1714 * It appears to be important that we don't enable this
1715 * for the current pipe before otherwise configuring the
1716 * PLL. No idea how this should be handled if multiple
1717 * DVO outputs are enabled simultaneosly.
1718 */
1719 dpll |= DPLL_DVO_2X_MODE;
1720 I915_WRITE(DPLL(!crtc->pipe),
1721 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1722 }
1723
1724 /* Wait for the clocks to stabilize. */
1725 POSTING_READ(reg);
1726 udelay(150);
1727
1728 if (INTEL_INFO(dev)->gen >= 4) {
1729 I915_WRITE(DPLL_MD(crtc->pipe),
1730 crtc->config->dpll_hw_state.dpll_md);
1731 } else {
1732 /* The pixel multiplier can only be updated once the
1733 * DPLL is enabled and the clocks are stable.
1734 *
1735 * So write it again.
1736 */
1737 I915_WRITE(reg, dpll);
1738 }
1739
1740 /* We do this three times for luck */
1741 I915_WRITE(reg, dpll);
1742 POSTING_READ(reg);
1743 udelay(150); /* wait for warmup */
1744 I915_WRITE(reg, dpll);
1745 POSTING_READ(reg);
1746 udelay(150); /* wait for warmup */
1747 I915_WRITE(reg, dpll);
1748 POSTING_READ(reg);
1749 udelay(150); /* wait for warmup */
1750 }
1751
1752 /**
1753 * i9xx_disable_pll - disable a PLL
1754 * @dev_priv: i915 private structure
1755 * @pipe: pipe PLL to disable
1756 *
1757 * Disable the PLL for @pipe, making sure the pipe is off first.
1758 *
1759 * Note! This is for pre-ILK only.
1760 */
1761 static void i9xx_disable_pll(struct intel_crtc *crtc)
1762 {
1763 struct drm_device *dev = crtc->base.dev;
1764 struct drm_i915_private *dev_priv = dev->dev_private;
1765 enum pipe pipe = crtc->pipe;
1766
1767 /* Disable DVO 2x clock on both PLLs if necessary */
1768 if (IS_I830(dev) &&
1769 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1770 !intel_num_dvo_pipes(dev)) {
1771 I915_WRITE(DPLL(PIPE_B),
1772 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1773 I915_WRITE(DPLL(PIPE_A),
1774 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1775 }
1776
1777 /* Don't disable pipe or pipe PLLs if needed */
1778 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1779 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1780 return;
1781
1782 /* Make sure the pipe isn't still relying on us */
1783 assert_pipe_disabled(dev_priv, pipe);
1784
1785 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1786 POSTING_READ(DPLL(pipe));
1787 }
1788
1789 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1790 {
1791 u32 val;
1792
1793 /* Make sure the pipe isn't still relying on us */
1794 assert_pipe_disabled(dev_priv, pipe);
1795
1796 /*
1797 * Leave integrated clock source and reference clock enabled for pipe B.
1798 * The latter is needed for VGA hotplug / manual detection.
1799 */
1800 val = DPLL_VGA_MODE_DIS;
1801 if (pipe == PIPE_B)
1802 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1803 I915_WRITE(DPLL(pipe), val);
1804 POSTING_READ(DPLL(pipe));
1805
1806 }
1807
1808 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1809 {
1810 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1811 u32 val;
1812
1813 /* Make sure the pipe isn't still relying on us */
1814 assert_pipe_disabled(dev_priv, pipe);
1815
1816 /* Set PLL en = 0 */
1817 val = DPLL_SSC_REF_CLK_CHV |
1818 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1819 if (pipe != PIPE_A)
1820 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1821 I915_WRITE(DPLL(pipe), val);
1822 POSTING_READ(DPLL(pipe));
1823
1824 mutex_lock(&dev_priv->sb_lock);
1825
1826 /* Disable 10bit clock to display controller */
1827 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1828 val &= ~DPIO_DCLKP_EN;
1829 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1830
1831 /* disable left/right clock distribution */
1832 if (pipe != PIPE_B) {
1833 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1834 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1835 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1836 } else {
1837 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1838 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1839 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1840 }
1841
1842 mutex_unlock(&dev_priv->sb_lock);
1843 }
1844
1845 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1846 struct intel_digital_port *dport,
1847 unsigned int expected_mask)
1848 {
1849 u32 port_mask;
1850 int dpll_reg;
1851
1852 switch (dport->port) {
1853 case PORT_B:
1854 port_mask = DPLL_PORTB_READY_MASK;
1855 dpll_reg = DPLL(0);
1856 break;
1857 case PORT_C:
1858 port_mask = DPLL_PORTC_READY_MASK;
1859 dpll_reg = DPLL(0);
1860 expected_mask <<= 4;
1861 break;
1862 case PORT_D:
1863 port_mask = DPLL_PORTD_READY_MASK;
1864 dpll_reg = DPIO_PHY_STATUS;
1865 break;
1866 default:
1867 BUG();
1868 }
1869
1870 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1871 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1872 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1873 }
1874
1875 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1876 {
1877 struct drm_device *dev = crtc->base.dev;
1878 struct drm_i915_private *dev_priv = dev->dev_private;
1879 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1880
1881 if (WARN_ON(pll == NULL))
1882 return;
1883
1884 WARN_ON(!pll->config.crtc_mask);
1885 if (pll->active == 0) {
1886 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1887 WARN_ON(pll->on);
1888 assert_shared_dpll_disabled(dev_priv, pll);
1889
1890 pll->mode_set(dev_priv, pll);
1891 }
1892 }
1893
1894 /**
1895 * intel_enable_shared_dpll - enable PCH PLL
1896 * @dev_priv: i915 private structure
1897 * @pipe: pipe PLL to enable
1898 *
1899 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1900 * drives the transcoder clock.
1901 */
1902 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1903 {
1904 struct drm_device *dev = crtc->base.dev;
1905 struct drm_i915_private *dev_priv = dev->dev_private;
1906 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1907
1908 if (WARN_ON(pll == NULL))
1909 return;
1910
1911 if (WARN_ON(pll->config.crtc_mask == 0))
1912 return;
1913
1914 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1915 pll->name, pll->active, pll->on,
1916 crtc->base.base.id);
1917
1918 if (pll->active++) {
1919 WARN_ON(!pll->on);
1920 assert_shared_dpll_enabled(dev_priv, pll);
1921 return;
1922 }
1923 WARN_ON(pll->on);
1924
1925 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1926
1927 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1928 pll->enable(dev_priv, pll);
1929 pll->on = true;
1930 }
1931
1932 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1933 {
1934 struct drm_device *dev = crtc->base.dev;
1935 struct drm_i915_private *dev_priv = dev->dev_private;
1936 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1937
1938 /* PCH only available on ILK+ */
1939 if (INTEL_INFO(dev)->gen < 5)
1940 return;
1941
1942 if (pll == NULL)
1943 return;
1944
1945 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1946 return;
1947
1948 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1949 pll->name, pll->active, pll->on,
1950 crtc->base.base.id);
1951
1952 if (WARN_ON(pll->active == 0)) {
1953 assert_shared_dpll_disabled(dev_priv, pll);
1954 return;
1955 }
1956
1957 assert_shared_dpll_enabled(dev_priv, pll);
1958 WARN_ON(!pll->on);
1959 if (--pll->active)
1960 return;
1961
1962 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1963 pll->disable(dev_priv, pll);
1964 pll->on = false;
1965
1966 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1967 }
1968
1969 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1970 enum pipe pipe)
1971 {
1972 struct drm_device *dev = dev_priv->dev;
1973 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1975 uint32_t reg, val, pipeconf_val;
1976
1977 /* PCH only available on ILK+ */
1978 BUG_ON(!HAS_PCH_SPLIT(dev));
1979
1980 /* Make sure PCH DPLL is enabled */
1981 assert_shared_dpll_enabled(dev_priv,
1982 intel_crtc_to_shared_dpll(intel_crtc));
1983
1984 /* FDI must be feeding us bits for PCH ports */
1985 assert_fdi_tx_enabled(dev_priv, pipe);
1986 assert_fdi_rx_enabled(dev_priv, pipe);
1987
1988 if (HAS_PCH_CPT(dev)) {
1989 /* Workaround: Set the timing override bit before enabling the
1990 * pch transcoder. */
1991 reg = TRANS_CHICKEN2(pipe);
1992 val = I915_READ(reg);
1993 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1994 I915_WRITE(reg, val);
1995 }
1996
1997 reg = PCH_TRANSCONF(pipe);
1998 val = I915_READ(reg);
1999 pipeconf_val = I915_READ(PIPECONF(pipe));
2000
2001 if (HAS_PCH_IBX(dev_priv->dev)) {
2002 /*
2003 * Make the BPC in transcoder be consistent with
2004 * that in pipeconf reg. For HDMI we must use 8bpc
2005 * here for both 8bpc and 12bpc.
2006 */
2007 val &= ~PIPECONF_BPC_MASK;
2008 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2009 val |= PIPECONF_8BPC;
2010 else
2011 val |= pipeconf_val & PIPECONF_BPC_MASK;
2012 }
2013
2014 val &= ~TRANS_INTERLACE_MASK;
2015 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2016 if (HAS_PCH_IBX(dev_priv->dev) &&
2017 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2018 val |= TRANS_LEGACY_INTERLACED_ILK;
2019 else
2020 val |= TRANS_INTERLACED;
2021 else
2022 val |= TRANS_PROGRESSIVE;
2023
2024 I915_WRITE(reg, val | TRANS_ENABLE);
2025 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2026 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2027 }
2028
2029 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2030 enum transcoder cpu_transcoder)
2031 {
2032 u32 val, pipeconf_val;
2033
2034 /* PCH only available on ILK+ */
2035 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2036
2037 /* FDI must be feeding us bits for PCH ports */
2038 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2039 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2040
2041 /* Workaround: set timing override bit. */
2042 val = I915_READ(_TRANSA_CHICKEN2);
2043 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2044 I915_WRITE(_TRANSA_CHICKEN2, val);
2045
2046 val = TRANS_ENABLE;
2047 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2048
2049 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2050 PIPECONF_INTERLACED_ILK)
2051 val |= TRANS_INTERLACED;
2052 else
2053 val |= TRANS_PROGRESSIVE;
2054
2055 I915_WRITE(LPT_TRANSCONF, val);
2056 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2057 DRM_ERROR("Failed to enable PCH transcoder\n");
2058 }
2059
2060 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2061 enum pipe pipe)
2062 {
2063 struct drm_device *dev = dev_priv->dev;
2064 uint32_t reg, val;
2065
2066 /* FDI relies on the transcoder */
2067 assert_fdi_tx_disabled(dev_priv, pipe);
2068 assert_fdi_rx_disabled(dev_priv, pipe);
2069
2070 /* Ports must be off as well */
2071 assert_pch_ports_disabled(dev_priv, pipe);
2072
2073 reg = PCH_TRANSCONF(pipe);
2074 val = I915_READ(reg);
2075 val &= ~TRANS_ENABLE;
2076 I915_WRITE(reg, val);
2077 /* wait for PCH transcoder off, transcoder state */
2078 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2079 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2080
2081 if (!HAS_PCH_IBX(dev)) {
2082 /* Workaround: Clear the timing override chicken bit again. */
2083 reg = TRANS_CHICKEN2(pipe);
2084 val = I915_READ(reg);
2085 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2086 I915_WRITE(reg, val);
2087 }
2088 }
2089
2090 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2091 {
2092 u32 val;
2093
2094 val = I915_READ(LPT_TRANSCONF);
2095 val &= ~TRANS_ENABLE;
2096 I915_WRITE(LPT_TRANSCONF, val);
2097 /* wait for PCH transcoder off, transcoder state */
2098 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2099 DRM_ERROR("Failed to disable PCH transcoder\n");
2100
2101 /* Workaround: clear timing override bit. */
2102 val = I915_READ(_TRANSA_CHICKEN2);
2103 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2104 I915_WRITE(_TRANSA_CHICKEN2, val);
2105 }
2106
2107 /**
2108 * intel_enable_pipe - enable a pipe, asserting requirements
2109 * @crtc: crtc responsible for the pipe
2110 *
2111 * Enable @crtc's pipe, making sure that various hardware specific requirements
2112 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2113 */
2114 static void intel_enable_pipe(struct intel_crtc *crtc)
2115 {
2116 struct drm_device *dev = crtc->base.dev;
2117 struct drm_i915_private *dev_priv = dev->dev_private;
2118 enum pipe pipe = crtc->pipe;
2119 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2120 pipe);
2121 enum pipe pch_transcoder;
2122 int reg;
2123 u32 val;
2124
2125 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2126
2127 assert_planes_disabled(dev_priv, pipe);
2128 assert_cursor_disabled(dev_priv, pipe);
2129 assert_sprites_disabled(dev_priv, pipe);
2130
2131 if (HAS_PCH_LPT(dev_priv->dev))
2132 pch_transcoder = TRANSCODER_A;
2133 else
2134 pch_transcoder = pipe;
2135
2136 /*
2137 * A pipe without a PLL won't actually be able to drive bits from
2138 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2139 * need the check.
2140 */
2141 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2142 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2143 assert_dsi_pll_enabled(dev_priv);
2144 else
2145 assert_pll_enabled(dev_priv, pipe);
2146 else {
2147 if (crtc->config->has_pch_encoder) {
2148 /* if driving the PCH, we need FDI enabled */
2149 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2150 assert_fdi_tx_pll_enabled(dev_priv,
2151 (enum pipe) cpu_transcoder);
2152 }
2153 /* FIXME: assert CPU port conditions for SNB+ */
2154 }
2155
2156 reg = PIPECONF(cpu_transcoder);
2157 val = I915_READ(reg);
2158 if (val & PIPECONF_ENABLE) {
2159 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2160 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2161 return;
2162 }
2163
2164 I915_WRITE(reg, val | PIPECONF_ENABLE);
2165 POSTING_READ(reg);
2166 }
2167
2168 /**
2169 * intel_disable_pipe - disable a pipe, asserting requirements
2170 * @crtc: crtc whose pipes is to be disabled
2171 *
2172 * Disable the pipe of @crtc, making sure that various hardware
2173 * specific requirements are met, if applicable, e.g. plane
2174 * disabled, panel fitter off, etc.
2175 *
2176 * Will wait until the pipe has shut down before returning.
2177 */
2178 static void intel_disable_pipe(struct intel_crtc *crtc)
2179 {
2180 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2181 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2182 enum pipe pipe = crtc->pipe;
2183 int reg;
2184 u32 val;
2185
2186 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2187
2188 /*
2189 * Make sure planes won't keep trying to pump pixels to us,
2190 * or we might hang the display.
2191 */
2192 assert_planes_disabled(dev_priv, pipe);
2193 assert_cursor_disabled(dev_priv, pipe);
2194 assert_sprites_disabled(dev_priv, pipe);
2195
2196 reg = PIPECONF(cpu_transcoder);
2197 val = I915_READ(reg);
2198 if ((val & PIPECONF_ENABLE) == 0)
2199 return;
2200
2201 /*
2202 * Double wide has implications for planes
2203 * so best keep it disabled when not needed.
2204 */
2205 if (crtc->config->double_wide)
2206 val &= ~PIPECONF_DOUBLE_WIDE;
2207
2208 /* Don't disable pipe or pipe PLLs if needed */
2209 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2210 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2211 val &= ~PIPECONF_ENABLE;
2212
2213 I915_WRITE(reg, val);
2214 if ((val & PIPECONF_ENABLE) == 0)
2215 intel_wait_for_pipe_off(crtc);
2216 }
2217
2218 static bool need_vtd_wa(struct drm_device *dev)
2219 {
2220 #ifdef CONFIG_INTEL_IOMMU
2221 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2222 return true;
2223 #endif
2224 return false;
2225 }
2226
2227 unsigned int
2228 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2229 uint64_t fb_format_modifier)
2230 {
2231 unsigned int tile_height;
2232 uint32_t pixel_bytes;
2233
2234 switch (fb_format_modifier) {
2235 case DRM_FORMAT_MOD_NONE:
2236 tile_height = 1;
2237 break;
2238 case I915_FORMAT_MOD_X_TILED:
2239 tile_height = IS_GEN2(dev) ? 16 : 8;
2240 break;
2241 case I915_FORMAT_MOD_Y_TILED:
2242 tile_height = 32;
2243 break;
2244 case I915_FORMAT_MOD_Yf_TILED:
2245 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2246 switch (pixel_bytes) {
2247 default:
2248 case 1:
2249 tile_height = 64;
2250 break;
2251 case 2:
2252 case 4:
2253 tile_height = 32;
2254 break;
2255 case 8:
2256 tile_height = 16;
2257 break;
2258 case 16:
2259 WARN_ONCE(1,
2260 "128-bit pixels are not supported for display!");
2261 tile_height = 16;
2262 break;
2263 }
2264 break;
2265 default:
2266 MISSING_CASE(fb_format_modifier);
2267 tile_height = 1;
2268 break;
2269 }
2270
2271 return tile_height;
2272 }
2273
2274 unsigned int
2275 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2276 uint32_t pixel_format, uint64_t fb_format_modifier)
2277 {
2278 return ALIGN(height, intel_tile_height(dev, pixel_format,
2279 fb_format_modifier));
2280 }
2281
2282 static int
2283 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2284 const struct drm_plane_state *plane_state)
2285 {
2286 struct intel_rotation_info *info = &view->rotation_info;
2287 unsigned int tile_height, tile_pitch;
2288
2289 *view = i915_ggtt_view_normal;
2290
2291 if (!plane_state)
2292 return 0;
2293
2294 if (!intel_rotation_90_or_270(plane_state->rotation))
2295 return 0;
2296
2297 *view = i915_ggtt_view_rotated;
2298
2299 info->height = fb->height;
2300 info->pixel_format = fb->pixel_format;
2301 info->pitch = fb->pitches[0];
2302 info->fb_modifier = fb->modifier[0];
2303
2304 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2305 fb->modifier[0]);
2306 tile_pitch = PAGE_SIZE / tile_height;
2307 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2308 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2309 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2310
2311 return 0;
2312 }
2313
2314 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2315 {
2316 if (INTEL_INFO(dev_priv)->gen >= 9)
2317 return 256 * 1024;
2318 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2319 IS_VALLEYVIEW(dev_priv))
2320 return 128 * 1024;
2321 else if (INTEL_INFO(dev_priv)->gen >= 4)
2322 return 4 * 1024;
2323 else
2324 return 0;
2325 }
2326
2327 int
2328 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2329 struct drm_framebuffer *fb,
2330 const struct drm_plane_state *plane_state,
2331 struct intel_engine_cs *pipelined,
2332 struct drm_i915_gem_request **pipelined_request)
2333 {
2334 struct drm_device *dev = fb->dev;
2335 struct drm_i915_private *dev_priv = dev->dev_private;
2336 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2337 struct i915_ggtt_view view;
2338 u32 alignment;
2339 int ret;
2340
2341 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2342
2343 switch (fb->modifier[0]) {
2344 case DRM_FORMAT_MOD_NONE:
2345 alignment = intel_linear_alignment(dev_priv);
2346 break;
2347 case I915_FORMAT_MOD_X_TILED:
2348 if (INTEL_INFO(dev)->gen >= 9)
2349 alignment = 256 * 1024;
2350 else {
2351 /* pin() will align the object as required by fence */
2352 alignment = 0;
2353 }
2354 break;
2355 case I915_FORMAT_MOD_Y_TILED:
2356 case I915_FORMAT_MOD_Yf_TILED:
2357 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2358 "Y tiling bo slipped through, driver bug!\n"))
2359 return -EINVAL;
2360 alignment = 1 * 1024 * 1024;
2361 break;
2362 default:
2363 MISSING_CASE(fb->modifier[0]);
2364 return -EINVAL;
2365 }
2366
2367 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2368 if (ret)
2369 return ret;
2370
2371 /* Note that the w/a also requires 64 PTE of padding following the
2372 * bo. We currently fill all unused PTE with the shadow page and so
2373 * we should always have valid PTE following the scanout preventing
2374 * the VT-d warning.
2375 */
2376 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2377 alignment = 256 * 1024;
2378
2379 /*
2380 * Global gtt pte registers are special registers which actually forward
2381 * writes to a chunk of system memory. Which means that there is no risk
2382 * that the register values disappear as soon as we call
2383 * intel_runtime_pm_put(), so it is correct to wrap only the
2384 * pin/unpin/fence and not more.
2385 */
2386 intel_runtime_pm_get(dev_priv);
2387
2388 dev_priv->mm.interruptible = false;
2389 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2390 pipelined_request, &view);
2391 if (ret)
2392 goto err_interruptible;
2393
2394 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2395 * fence, whereas 965+ only requires a fence if using
2396 * framebuffer compression. For simplicity, we always install
2397 * a fence as the cost is not that onerous.
2398 */
2399 ret = i915_gem_object_get_fence(obj);
2400 if (ret)
2401 goto err_unpin;
2402
2403 i915_gem_object_pin_fence(obj);
2404
2405 dev_priv->mm.interruptible = true;
2406 intel_runtime_pm_put(dev_priv);
2407 return 0;
2408
2409 err_unpin:
2410 i915_gem_object_unpin_from_display_plane(obj, &view);
2411 err_interruptible:
2412 dev_priv->mm.interruptible = true;
2413 intel_runtime_pm_put(dev_priv);
2414 return ret;
2415 }
2416
2417 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2418 const struct drm_plane_state *plane_state)
2419 {
2420 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2421 struct i915_ggtt_view view;
2422 int ret;
2423
2424 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2425
2426 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2427 WARN_ONCE(ret, "Couldn't get view from plane state!");
2428
2429 i915_gem_object_unpin_fence(obj);
2430 i915_gem_object_unpin_from_display_plane(obj, &view);
2431 }
2432
2433 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2434 * is assumed to be a power-of-two. */
2435 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2436 int *x, int *y,
2437 unsigned int tiling_mode,
2438 unsigned int cpp,
2439 unsigned int pitch)
2440 {
2441 if (tiling_mode != I915_TILING_NONE) {
2442 unsigned int tile_rows, tiles;
2443
2444 tile_rows = *y / 8;
2445 *y %= 8;
2446
2447 tiles = *x / (512/cpp);
2448 *x %= 512/cpp;
2449
2450 return tile_rows * pitch * 8 + tiles * 4096;
2451 } else {
2452 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2453 unsigned int offset;
2454
2455 offset = *y * pitch + *x * cpp;
2456 *y = (offset & alignment) / pitch;
2457 *x = ((offset & alignment) - *y * pitch) / cpp;
2458 return offset & ~alignment;
2459 }
2460 }
2461
2462 static int i9xx_format_to_fourcc(int format)
2463 {
2464 switch (format) {
2465 case DISPPLANE_8BPP:
2466 return DRM_FORMAT_C8;
2467 case DISPPLANE_BGRX555:
2468 return DRM_FORMAT_XRGB1555;
2469 case DISPPLANE_BGRX565:
2470 return DRM_FORMAT_RGB565;
2471 default:
2472 case DISPPLANE_BGRX888:
2473 return DRM_FORMAT_XRGB8888;
2474 case DISPPLANE_RGBX888:
2475 return DRM_FORMAT_XBGR8888;
2476 case DISPPLANE_BGRX101010:
2477 return DRM_FORMAT_XRGB2101010;
2478 case DISPPLANE_RGBX101010:
2479 return DRM_FORMAT_XBGR2101010;
2480 }
2481 }
2482
2483 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2484 {
2485 switch (format) {
2486 case PLANE_CTL_FORMAT_RGB_565:
2487 return DRM_FORMAT_RGB565;
2488 default:
2489 case PLANE_CTL_FORMAT_XRGB_8888:
2490 if (rgb_order) {
2491 if (alpha)
2492 return DRM_FORMAT_ABGR8888;
2493 else
2494 return DRM_FORMAT_XBGR8888;
2495 } else {
2496 if (alpha)
2497 return DRM_FORMAT_ARGB8888;
2498 else
2499 return DRM_FORMAT_XRGB8888;
2500 }
2501 case PLANE_CTL_FORMAT_XRGB_2101010:
2502 if (rgb_order)
2503 return DRM_FORMAT_XBGR2101010;
2504 else
2505 return DRM_FORMAT_XRGB2101010;
2506 }
2507 }
2508
2509 static bool
2510 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2511 struct intel_initial_plane_config *plane_config)
2512 {
2513 struct drm_device *dev = crtc->base.dev;
2514 struct drm_i915_gem_object *obj = NULL;
2515 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2516 struct drm_framebuffer *fb = &plane_config->fb->base;
2517 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2518 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2519 PAGE_SIZE);
2520
2521 size_aligned -= base_aligned;
2522
2523 if (plane_config->size == 0)
2524 return false;
2525
2526 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2527 base_aligned,
2528 base_aligned,
2529 size_aligned);
2530 if (!obj)
2531 return false;
2532
2533 obj->tiling_mode = plane_config->tiling;
2534 if (obj->tiling_mode == I915_TILING_X)
2535 obj->stride = fb->pitches[0];
2536
2537 mode_cmd.pixel_format = fb->pixel_format;
2538 mode_cmd.width = fb->width;
2539 mode_cmd.height = fb->height;
2540 mode_cmd.pitches[0] = fb->pitches[0];
2541 mode_cmd.modifier[0] = fb->modifier[0];
2542 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2543
2544 mutex_lock(&dev->struct_mutex);
2545 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2546 &mode_cmd, obj)) {
2547 DRM_DEBUG_KMS("intel fb init failed\n");
2548 goto out_unref_obj;
2549 }
2550 mutex_unlock(&dev->struct_mutex);
2551
2552 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2553 return true;
2554
2555 out_unref_obj:
2556 drm_gem_object_unreference(&obj->base);
2557 mutex_unlock(&dev->struct_mutex);
2558 return false;
2559 }
2560
2561 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2562 static void
2563 update_state_fb(struct drm_plane *plane)
2564 {
2565 if (plane->fb == plane->state->fb)
2566 return;
2567
2568 if (plane->state->fb)
2569 drm_framebuffer_unreference(plane->state->fb);
2570 plane->state->fb = plane->fb;
2571 if (plane->state->fb)
2572 drm_framebuffer_reference(plane->state->fb);
2573 }
2574
2575 static void
2576 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2577 struct intel_initial_plane_config *plane_config)
2578 {
2579 struct drm_device *dev = intel_crtc->base.dev;
2580 struct drm_i915_private *dev_priv = dev->dev_private;
2581 struct drm_crtc *c;
2582 struct intel_crtc *i;
2583 struct drm_i915_gem_object *obj;
2584 struct drm_plane *primary = intel_crtc->base.primary;
2585 struct drm_plane_state *plane_state = primary->state;
2586 struct drm_framebuffer *fb;
2587
2588 if (!plane_config->fb)
2589 return;
2590
2591 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2592 fb = &plane_config->fb->base;
2593 goto valid_fb;
2594 }
2595
2596 kfree(plane_config->fb);
2597
2598 /*
2599 * Failed to alloc the obj, check to see if we should share
2600 * an fb with another CRTC instead
2601 */
2602 for_each_crtc(dev, c) {
2603 i = to_intel_crtc(c);
2604
2605 if (c == &intel_crtc->base)
2606 continue;
2607
2608 if (!i->active)
2609 continue;
2610
2611 fb = c->primary->fb;
2612 if (!fb)
2613 continue;
2614
2615 obj = intel_fb_obj(fb);
2616 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2617 drm_framebuffer_reference(fb);
2618 goto valid_fb;
2619 }
2620 }
2621
2622 return;
2623
2624 valid_fb:
2625 plane_state->src_x = plane_state->src_y = 0;
2626 plane_state->src_w = fb->width << 16;
2627 plane_state->src_h = fb->height << 16;
2628
2629 plane_state->crtc_x = plane_state->src_y = 0;
2630 plane_state->crtc_w = fb->width;
2631 plane_state->crtc_h = fb->height;
2632
2633 obj = intel_fb_obj(fb);
2634 if (obj->tiling_mode != I915_TILING_NONE)
2635 dev_priv->preserve_bios_swizzle = true;
2636
2637 drm_framebuffer_reference(fb);
2638 primary->fb = primary->state->fb = fb;
2639 primary->crtc = primary->state->crtc = &intel_crtc->base;
2640 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2641 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2642 }
2643
2644 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2645 struct drm_framebuffer *fb,
2646 int x, int y)
2647 {
2648 struct drm_device *dev = crtc->dev;
2649 struct drm_i915_private *dev_priv = dev->dev_private;
2650 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2651 struct drm_plane *primary = crtc->primary;
2652 bool visible = to_intel_plane_state(primary->state)->visible;
2653 struct drm_i915_gem_object *obj;
2654 int plane = intel_crtc->plane;
2655 unsigned long linear_offset;
2656 u32 dspcntr;
2657 u32 reg = DSPCNTR(plane);
2658 int pixel_size;
2659
2660 if (!visible || !fb) {
2661 I915_WRITE(reg, 0);
2662 if (INTEL_INFO(dev)->gen >= 4)
2663 I915_WRITE(DSPSURF(plane), 0);
2664 else
2665 I915_WRITE(DSPADDR(plane), 0);
2666 POSTING_READ(reg);
2667 return;
2668 }
2669
2670 obj = intel_fb_obj(fb);
2671 if (WARN_ON(obj == NULL))
2672 return;
2673
2674 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2675
2676 dspcntr = DISPPLANE_GAMMA_ENABLE;
2677
2678 dspcntr |= DISPLAY_PLANE_ENABLE;
2679
2680 if (INTEL_INFO(dev)->gen < 4) {
2681 if (intel_crtc->pipe == PIPE_B)
2682 dspcntr |= DISPPLANE_SEL_PIPE_B;
2683
2684 /* pipesrc and dspsize control the size that is scaled from,
2685 * which should always be the user's requested size.
2686 */
2687 I915_WRITE(DSPSIZE(plane),
2688 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2689 (intel_crtc->config->pipe_src_w - 1));
2690 I915_WRITE(DSPPOS(plane), 0);
2691 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2692 I915_WRITE(PRIMSIZE(plane),
2693 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2694 (intel_crtc->config->pipe_src_w - 1));
2695 I915_WRITE(PRIMPOS(plane), 0);
2696 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2697 }
2698
2699 switch (fb->pixel_format) {
2700 case DRM_FORMAT_C8:
2701 dspcntr |= DISPPLANE_8BPP;
2702 break;
2703 case DRM_FORMAT_XRGB1555:
2704 dspcntr |= DISPPLANE_BGRX555;
2705 break;
2706 case DRM_FORMAT_RGB565:
2707 dspcntr |= DISPPLANE_BGRX565;
2708 break;
2709 case DRM_FORMAT_XRGB8888:
2710 dspcntr |= DISPPLANE_BGRX888;
2711 break;
2712 case DRM_FORMAT_XBGR8888:
2713 dspcntr |= DISPPLANE_RGBX888;
2714 break;
2715 case DRM_FORMAT_XRGB2101010:
2716 dspcntr |= DISPPLANE_BGRX101010;
2717 break;
2718 case DRM_FORMAT_XBGR2101010:
2719 dspcntr |= DISPPLANE_RGBX101010;
2720 break;
2721 default:
2722 BUG();
2723 }
2724
2725 if (INTEL_INFO(dev)->gen >= 4 &&
2726 obj->tiling_mode != I915_TILING_NONE)
2727 dspcntr |= DISPPLANE_TILED;
2728
2729 if (IS_G4X(dev))
2730 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2731
2732 linear_offset = y * fb->pitches[0] + x * pixel_size;
2733
2734 if (INTEL_INFO(dev)->gen >= 4) {
2735 intel_crtc->dspaddr_offset =
2736 intel_gen4_compute_page_offset(dev_priv,
2737 &x, &y, obj->tiling_mode,
2738 pixel_size,
2739 fb->pitches[0]);
2740 linear_offset -= intel_crtc->dspaddr_offset;
2741 } else {
2742 intel_crtc->dspaddr_offset = linear_offset;
2743 }
2744
2745 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2746 dspcntr |= DISPPLANE_ROTATE_180;
2747
2748 x += (intel_crtc->config->pipe_src_w - 1);
2749 y += (intel_crtc->config->pipe_src_h - 1);
2750
2751 /* Finding the last pixel of the last line of the display
2752 data and adding to linear_offset*/
2753 linear_offset +=
2754 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2755 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2756 }
2757
2758 I915_WRITE(reg, dspcntr);
2759
2760 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2761 if (INTEL_INFO(dev)->gen >= 4) {
2762 I915_WRITE(DSPSURF(plane),
2763 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2764 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2765 I915_WRITE(DSPLINOFF(plane), linear_offset);
2766 } else
2767 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2768 POSTING_READ(reg);
2769 }
2770
2771 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2772 struct drm_framebuffer *fb,
2773 int x, int y)
2774 {
2775 struct drm_device *dev = crtc->dev;
2776 struct drm_i915_private *dev_priv = dev->dev_private;
2777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2778 struct drm_plane *primary = crtc->primary;
2779 bool visible = to_intel_plane_state(primary->state)->visible;
2780 struct drm_i915_gem_object *obj;
2781 int plane = intel_crtc->plane;
2782 unsigned long linear_offset;
2783 u32 dspcntr;
2784 u32 reg = DSPCNTR(plane);
2785 int pixel_size;
2786
2787 if (!visible || !fb) {
2788 I915_WRITE(reg, 0);
2789 I915_WRITE(DSPSURF(plane), 0);
2790 POSTING_READ(reg);
2791 return;
2792 }
2793
2794 obj = intel_fb_obj(fb);
2795 if (WARN_ON(obj == NULL))
2796 return;
2797
2798 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2799
2800 dspcntr = DISPPLANE_GAMMA_ENABLE;
2801
2802 dspcntr |= DISPLAY_PLANE_ENABLE;
2803
2804 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2805 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2806
2807 switch (fb->pixel_format) {
2808 case DRM_FORMAT_C8:
2809 dspcntr |= DISPPLANE_8BPP;
2810 break;
2811 case DRM_FORMAT_RGB565:
2812 dspcntr |= DISPPLANE_BGRX565;
2813 break;
2814 case DRM_FORMAT_XRGB8888:
2815 dspcntr |= DISPPLANE_BGRX888;
2816 break;
2817 case DRM_FORMAT_XBGR8888:
2818 dspcntr |= DISPPLANE_RGBX888;
2819 break;
2820 case DRM_FORMAT_XRGB2101010:
2821 dspcntr |= DISPPLANE_BGRX101010;
2822 break;
2823 case DRM_FORMAT_XBGR2101010:
2824 dspcntr |= DISPPLANE_RGBX101010;
2825 break;
2826 default:
2827 BUG();
2828 }
2829
2830 if (obj->tiling_mode != I915_TILING_NONE)
2831 dspcntr |= DISPPLANE_TILED;
2832
2833 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2834 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2835
2836 linear_offset = y * fb->pitches[0] + x * pixel_size;
2837 intel_crtc->dspaddr_offset =
2838 intel_gen4_compute_page_offset(dev_priv,
2839 &x, &y, obj->tiling_mode,
2840 pixel_size,
2841 fb->pitches[0]);
2842 linear_offset -= intel_crtc->dspaddr_offset;
2843 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2844 dspcntr |= DISPPLANE_ROTATE_180;
2845
2846 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2847 x += (intel_crtc->config->pipe_src_w - 1);
2848 y += (intel_crtc->config->pipe_src_h - 1);
2849
2850 /* Finding the last pixel of the last line of the display
2851 data and adding to linear_offset*/
2852 linear_offset +=
2853 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2854 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2855 }
2856 }
2857
2858 I915_WRITE(reg, dspcntr);
2859
2860 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2861 I915_WRITE(DSPSURF(plane),
2862 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2863 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2864 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2865 } else {
2866 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2867 I915_WRITE(DSPLINOFF(plane), linear_offset);
2868 }
2869 POSTING_READ(reg);
2870 }
2871
2872 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2873 uint32_t pixel_format)
2874 {
2875 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2876
2877 /*
2878 * The stride is either expressed as a multiple of 64 bytes
2879 * chunks for linear buffers or in number of tiles for tiled
2880 * buffers.
2881 */
2882 switch (fb_modifier) {
2883 case DRM_FORMAT_MOD_NONE:
2884 return 64;
2885 case I915_FORMAT_MOD_X_TILED:
2886 if (INTEL_INFO(dev)->gen == 2)
2887 return 128;
2888 return 512;
2889 case I915_FORMAT_MOD_Y_TILED:
2890 /* No need to check for old gens and Y tiling since this is
2891 * about the display engine and those will be blocked before
2892 * we get here.
2893 */
2894 return 128;
2895 case I915_FORMAT_MOD_Yf_TILED:
2896 if (bits_per_pixel == 8)
2897 return 64;
2898 else
2899 return 128;
2900 default:
2901 MISSING_CASE(fb_modifier);
2902 return 64;
2903 }
2904 }
2905
2906 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2907 struct drm_i915_gem_object *obj)
2908 {
2909 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2910
2911 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2912 view = &i915_ggtt_view_rotated;
2913
2914 return i915_gem_obj_ggtt_offset_view(obj, view);
2915 }
2916
2917 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2918 {
2919 struct drm_device *dev = intel_crtc->base.dev;
2920 struct drm_i915_private *dev_priv = dev->dev_private;
2921
2922 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2923 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2924 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2925 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2926 intel_crtc->base.base.id, intel_crtc->pipe, id);
2927 }
2928
2929 /*
2930 * This function detaches (aka. unbinds) unused scalers in hardware
2931 */
2932 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2933 {
2934 struct intel_crtc_scaler_state *scaler_state;
2935 int i;
2936
2937 scaler_state = &intel_crtc->config->scaler_state;
2938
2939 /* loop through and disable scalers that aren't in use */
2940 for (i = 0; i < intel_crtc->num_scalers; i++) {
2941 if (!scaler_state->scalers[i].in_use)
2942 skl_detach_scaler(intel_crtc, i);
2943 }
2944 }
2945
2946 u32 skl_plane_ctl_format(uint32_t pixel_format)
2947 {
2948 switch (pixel_format) {
2949 case DRM_FORMAT_C8:
2950 return PLANE_CTL_FORMAT_INDEXED;
2951 case DRM_FORMAT_RGB565:
2952 return PLANE_CTL_FORMAT_RGB_565;
2953 case DRM_FORMAT_XBGR8888:
2954 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2955 case DRM_FORMAT_XRGB8888:
2956 return PLANE_CTL_FORMAT_XRGB_8888;
2957 /*
2958 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2959 * to be already pre-multiplied. We need to add a knob (or a different
2960 * DRM_FORMAT) for user-space to configure that.
2961 */
2962 case DRM_FORMAT_ABGR8888:
2963 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2964 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2965 case DRM_FORMAT_ARGB8888:
2966 return PLANE_CTL_FORMAT_XRGB_8888 |
2967 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2968 case DRM_FORMAT_XRGB2101010:
2969 return PLANE_CTL_FORMAT_XRGB_2101010;
2970 case DRM_FORMAT_XBGR2101010:
2971 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2972 case DRM_FORMAT_YUYV:
2973 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2974 case DRM_FORMAT_YVYU:
2975 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2976 case DRM_FORMAT_UYVY:
2977 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2978 case DRM_FORMAT_VYUY:
2979 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2980 default:
2981 MISSING_CASE(pixel_format);
2982 }
2983
2984 return 0;
2985 }
2986
2987 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2988 {
2989 switch (fb_modifier) {
2990 case DRM_FORMAT_MOD_NONE:
2991 break;
2992 case I915_FORMAT_MOD_X_TILED:
2993 return PLANE_CTL_TILED_X;
2994 case I915_FORMAT_MOD_Y_TILED:
2995 return PLANE_CTL_TILED_Y;
2996 case I915_FORMAT_MOD_Yf_TILED:
2997 return PLANE_CTL_TILED_YF;
2998 default:
2999 MISSING_CASE(fb_modifier);
3000 }
3001
3002 return 0;
3003 }
3004
3005 u32 skl_plane_ctl_rotation(unsigned int rotation)
3006 {
3007 switch (rotation) {
3008 case BIT(DRM_ROTATE_0):
3009 break;
3010 /*
3011 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3012 * while i915 HW rotation is clockwise, thats why this swapping.
3013 */
3014 case BIT(DRM_ROTATE_90):
3015 return PLANE_CTL_ROTATE_270;
3016 case BIT(DRM_ROTATE_180):
3017 return PLANE_CTL_ROTATE_180;
3018 case BIT(DRM_ROTATE_270):
3019 return PLANE_CTL_ROTATE_90;
3020 default:
3021 MISSING_CASE(rotation);
3022 }
3023
3024 return 0;
3025 }
3026
3027 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3028 struct drm_framebuffer *fb,
3029 int x, int y)
3030 {
3031 struct drm_device *dev = crtc->dev;
3032 struct drm_i915_private *dev_priv = dev->dev_private;
3033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3034 struct drm_plane *plane = crtc->primary;
3035 bool visible = to_intel_plane_state(plane->state)->visible;
3036 struct drm_i915_gem_object *obj;
3037 int pipe = intel_crtc->pipe;
3038 u32 plane_ctl, stride_div, stride;
3039 u32 tile_height, plane_offset, plane_size;
3040 unsigned int rotation;
3041 int x_offset, y_offset;
3042 unsigned long surf_addr;
3043 struct intel_crtc_state *crtc_state = intel_crtc->config;
3044 struct intel_plane_state *plane_state;
3045 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3046 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3047 int scaler_id = -1;
3048
3049 plane_state = to_intel_plane_state(plane->state);
3050
3051 if (!visible || !fb) {
3052 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3053 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3054 POSTING_READ(PLANE_CTL(pipe, 0));
3055 return;
3056 }
3057
3058 plane_ctl = PLANE_CTL_ENABLE |
3059 PLANE_CTL_PIPE_GAMMA_ENABLE |
3060 PLANE_CTL_PIPE_CSC_ENABLE;
3061
3062 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3063 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3064 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3065
3066 rotation = plane->state->rotation;
3067 plane_ctl |= skl_plane_ctl_rotation(rotation);
3068
3069 obj = intel_fb_obj(fb);
3070 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3071 fb->pixel_format);
3072 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3073
3074 /*
3075 * FIXME: intel_plane_state->src, dst aren't set when transitional
3076 * update_plane helpers are called from legacy paths.
3077 * Once full atomic crtc is available, below check can be avoided.
3078 */
3079 if (drm_rect_width(&plane_state->src)) {
3080 scaler_id = plane_state->scaler_id;
3081 src_x = plane_state->src.x1 >> 16;
3082 src_y = plane_state->src.y1 >> 16;
3083 src_w = drm_rect_width(&plane_state->src) >> 16;
3084 src_h = drm_rect_height(&plane_state->src) >> 16;
3085 dst_x = plane_state->dst.x1;
3086 dst_y = plane_state->dst.y1;
3087 dst_w = drm_rect_width(&plane_state->dst);
3088 dst_h = drm_rect_height(&plane_state->dst);
3089
3090 WARN_ON(x != src_x || y != src_y);
3091 } else {
3092 src_w = intel_crtc->config->pipe_src_w;
3093 src_h = intel_crtc->config->pipe_src_h;
3094 }
3095
3096 if (intel_rotation_90_or_270(rotation)) {
3097 /* stride = Surface height in tiles */
3098 tile_height = intel_tile_height(dev, fb->pixel_format,
3099 fb->modifier[0]);
3100 stride = DIV_ROUND_UP(fb->height, tile_height);
3101 x_offset = stride * tile_height - y - src_h;
3102 y_offset = x;
3103 plane_size = (src_w - 1) << 16 | (src_h - 1);
3104 } else {
3105 stride = fb->pitches[0] / stride_div;
3106 x_offset = x;
3107 y_offset = y;
3108 plane_size = (src_h - 1) << 16 | (src_w - 1);
3109 }
3110 plane_offset = y_offset << 16 | x_offset;
3111
3112 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3113 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3114 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3115 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3116
3117 if (scaler_id >= 0) {
3118 uint32_t ps_ctrl = 0;
3119
3120 WARN_ON(!dst_w || !dst_h);
3121 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3122 crtc_state->scaler_state.scalers[scaler_id].mode;
3123 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3124 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3125 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3126 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3127 I915_WRITE(PLANE_POS(pipe, 0), 0);
3128 } else {
3129 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3130 }
3131
3132 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3133
3134 POSTING_READ(PLANE_SURF(pipe, 0));
3135 }
3136
3137 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3138 static int
3139 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3140 int x, int y, enum mode_set_atomic state)
3141 {
3142 struct drm_device *dev = crtc->dev;
3143 struct drm_i915_private *dev_priv = dev->dev_private;
3144
3145 if (dev_priv->fbc.disable_fbc)
3146 dev_priv->fbc.disable_fbc(dev_priv);
3147
3148 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3149
3150 return 0;
3151 }
3152
3153 static void intel_complete_page_flips(struct drm_device *dev)
3154 {
3155 struct drm_crtc *crtc;
3156
3157 for_each_crtc(dev, crtc) {
3158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3159 enum plane plane = intel_crtc->plane;
3160
3161 intel_prepare_page_flip(dev, plane);
3162 intel_finish_page_flip_plane(dev, plane);
3163 }
3164 }
3165
3166 static void intel_update_primary_planes(struct drm_device *dev)
3167 {
3168 struct drm_i915_private *dev_priv = dev->dev_private;
3169 struct drm_crtc *crtc;
3170
3171 for_each_crtc(dev, crtc) {
3172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3173
3174 drm_modeset_lock(&crtc->mutex, NULL);
3175 /*
3176 * FIXME: Once we have proper support for primary planes (and
3177 * disabling them without disabling the entire crtc) allow again
3178 * a NULL crtc->primary->fb.
3179 */
3180 if (intel_crtc->active && crtc->primary->fb)
3181 dev_priv->display.update_primary_plane(crtc,
3182 crtc->primary->fb,
3183 crtc->x,
3184 crtc->y);
3185 drm_modeset_unlock(&crtc->mutex);
3186 }
3187 }
3188
3189 void intel_prepare_reset(struct drm_device *dev)
3190 {
3191 /* no reset support for gen2 */
3192 if (IS_GEN2(dev))
3193 return;
3194
3195 /* reset doesn't touch the display */
3196 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3197 return;
3198
3199 drm_modeset_lock_all(dev);
3200 /*
3201 * Disabling the crtcs gracefully seems nicer. Also the
3202 * g33 docs say we should at least disable all the planes.
3203 */
3204 intel_display_suspend(dev);
3205 }
3206
3207 void intel_finish_reset(struct drm_device *dev)
3208 {
3209 struct drm_i915_private *dev_priv = to_i915(dev);
3210
3211 /*
3212 * Flips in the rings will be nuked by the reset,
3213 * so complete all pending flips so that user space
3214 * will get its events and not get stuck.
3215 */
3216 intel_complete_page_flips(dev);
3217
3218 /* no reset support for gen2 */
3219 if (IS_GEN2(dev))
3220 return;
3221
3222 /* reset doesn't touch the display */
3223 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3224 /*
3225 * Flips in the rings have been nuked by the reset,
3226 * so update the base address of all primary
3227 * planes to the the last fb to make sure we're
3228 * showing the correct fb after a reset.
3229 */
3230 intel_update_primary_planes(dev);
3231 return;
3232 }
3233
3234 /*
3235 * The display has been reset as well,
3236 * so need a full re-initialization.
3237 */
3238 intel_runtime_pm_disable_interrupts(dev_priv);
3239 intel_runtime_pm_enable_interrupts(dev_priv);
3240
3241 intel_modeset_init_hw(dev);
3242
3243 spin_lock_irq(&dev_priv->irq_lock);
3244 if (dev_priv->display.hpd_irq_setup)
3245 dev_priv->display.hpd_irq_setup(dev);
3246 spin_unlock_irq(&dev_priv->irq_lock);
3247
3248 intel_display_resume(dev);
3249
3250 intel_hpd_init(dev_priv);
3251
3252 drm_modeset_unlock_all(dev);
3253 }
3254
3255 static void
3256 intel_finish_fb(struct drm_framebuffer *old_fb)
3257 {
3258 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3259 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3260 bool was_interruptible = dev_priv->mm.interruptible;
3261 int ret;
3262
3263 /* Big Hammer, we also need to ensure that any pending
3264 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3265 * current scanout is retired before unpinning the old
3266 * framebuffer. Note that we rely on userspace rendering
3267 * into the buffer attached to the pipe they are waiting
3268 * on. If not, userspace generates a GPU hang with IPEHR
3269 * point to the MI_WAIT_FOR_EVENT.
3270 *
3271 * This should only fail upon a hung GPU, in which case we
3272 * can safely continue.
3273 */
3274 dev_priv->mm.interruptible = false;
3275 ret = i915_gem_object_wait_rendering(obj, true);
3276 dev_priv->mm.interruptible = was_interruptible;
3277
3278 WARN_ON(ret);
3279 }
3280
3281 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3282 {
3283 struct drm_device *dev = crtc->dev;
3284 struct drm_i915_private *dev_priv = dev->dev_private;
3285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3286 bool pending;
3287
3288 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3289 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3290 return false;
3291
3292 spin_lock_irq(&dev->event_lock);
3293 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3294 spin_unlock_irq(&dev->event_lock);
3295
3296 return pending;
3297 }
3298
3299 static void intel_update_pipe_size(struct intel_crtc *crtc)
3300 {
3301 struct drm_device *dev = crtc->base.dev;
3302 struct drm_i915_private *dev_priv = dev->dev_private;
3303 const struct drm_display_mode *adjusted_mode;
3304
3305 if (!i915.fastboot)
3306 return;
3307
3308 /*
3309 * Update pipe size and adjust fitter if needed: the reason for this is
3310 * that in compute_mode_changes we check the native mode (not the pfit
3311 * mode) to see if we can flip rather than do a full mode set. In the
3312 * fastboot case, we'll flip, but if we don't update the pipesrc and
3313 * pfit state, we'll end up with a big fb scanned out into the wrong
3314 * sized surface.
3315 *
3316 * To fix this properly, we need to hoist the checks up into
3317 * compute_mode_changes (or above), check the actual pfit state and
3318 * whether the platform allows pfit disable with pipe active, and only
3319 * then update the pipesrc and pfit state, even on the flip path.
3320 */
3321
3322 adjusted_mode = &crtc->config->base.adjusted_mode;
3323
3324 I915_WRITE(PIPESRC(crtc->pipe),
3325 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3326 (adjusted_mode->crtc_vdisplay - 1));
3327 if (!crtc->config->pch_pfit.enabled &&
3328 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3329 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3330 I915_WRITE(PF_CTL(crtc->pipe), 0);
3331 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3332 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3333 }
3334 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3335 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3336 }
3337
3338 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3339 {
3340 struct drm_device *dev = crtc->dev;
3341 struct drm_i915_private *dev_priv = dev->dev_private;
3342 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3343 int pipe = intel_crtc->pipe;
3344 u32 reg, temp;
3345
3346 /* enable normal train */
3347 reg = FDI_TX_CTL(pipe);
3348 temp = I915_READ(reg);
3349 if (IS_IVYBRIDGE(dev)) {
3350 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3351 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3352 } else {
3353 temp &= ~FDI_LINK_TRAIN_NONE;
3354 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3355 }
3356 I915_WRITE(reg, temp);
3357
3358 reg = FDI_RX_CTL(pipe);
3359 temp = I915_READ(reg);
3360 if (HAS_PCH_CPT(dev)) {
3361 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3362 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3363 } else {
3364 temp &= ~FDI_LINK_TRAIN_NONE;
3365 temp |= FDI_LINK_TRAIN_NONE;
3366 }
3367 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3368
3369 /* wait one idle pattern time */
3370 POSTING_READ(reg);
3371 udelay(1000);
3372
3373 /* IVB wants error correction enabled */
3374 if (IS_IVYBRIDGE(dev))
3375 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3376 FDI_FE_ERRC_ENABLE);
3377 }
3378
3379 /* The FDI link training functions for ILK/Ibexpeak. */
3380 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3381 {
3382 struct drm_device *dev = crtc->dev;
3383 struct drm_i915_private *dev_priv = dev->dev_private;
3384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3385 int pipe = intel_crtc->pipe;
3386 u32 reg, temp, tries;
3387
3388 /* FDI needs bits from pipe first */
3389 assert_pipe_enabled(dev_priv, pipe);
3390
3391 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3392 for train result */
3393 reg = FDI_RX_IMR(pipe);
3394 temp = I915_READ(reg);
3395 temp &= ~FDI_RX_SYMBOL_LOCK;
3396 temp &= ~FDI_RX_BIT_LOCK;
3397 I915_WRITE(reg, temp);
3398 I915_READ(reg);
3399 udelay(150);
3400
3401 /* enable CPU FDI TX and PCH FDI RX */
3402 reg = FDI_TX_CTL(pipe);
3403 temp = I915_READ(reg);
3404 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3405 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3406 temp &= ~FDI_LINK_TRAIN_NONE;
3407 temp |= FDI_LINK_TRAIN_PATTERN_1;
3408 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3409
3410 reg = FDI_RX_CTL(pipe);
3411 temp = I915_READ(reg);
3412 temp &= ~FDI_LINK_TRAIN_NONE;
3413 temp |= FDI_LINK_TRAIN_PATTERN_1;
3414 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3415
3416 POSTING_READ(reg);
3417 udelay(150);
3418
3419 /* Ironlake workaround, enable clock pointer after FDI enable*/
3420 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3421 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3422 FDI_RX_PHASE_SYNC_POINTER_EN);
3423
3424 reg = FDI_RX_IIR(pipe);
3425 for (tries = 0; tries < 5; tries++) {
3426 temp = I915_READ(reg);
3427 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3428
3429 if ((temp & FDI_RX_BIT_LOCK)) {
3430 DRM_DEBUG_KMS("FDI train 1 done.\n");
3431 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3432 break;
3433 }
3434 }
3435 if (tries == 5)
3436 DRM_ERROR("FDI train 1 fail!\n");
3437
3438 /* Train 2 */
3439 reg = FDI_TX_CTL(pipe);
3440 temp = I915_READ(reg);
3441 temp &= ~FDI_LINK_TRAIN_NONE;
3442 temp |= FDI_LINK_TRAIN_PATTERN_2;
3443 I915_WRITE(reg, temp);
3444
3445 reg = FDI_RX_CTL(pipe);
3446 temp = I915_READ(reg);
3447 temp &= ~FDI_LINK_TRAIN_NONE;
3448 temp |= FDI_LINK_TRAIN_PATTERN_2;
3449 I915_WRITE(reg, temp);
3450
3451 POSTING_READ(reg);
3452 udelay(150);
3453
3454 reg = FDI_RX_IIR(pipe);
3455 for (tries = 0; tries < 5; tries++) {
3456 temp = I915_READ(reg);
3457 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3458
3459 if (temp & FDI_RX_SYMBOL_LOCK) {
3460 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3461 DRM_DEBUG_KMS("FDI train 2 done.\n");
3462 break;
3463 }
3464 }
3465 if (tries == 5)
3466 DRM_ERROR("FDI train 2 fail!\n");
3467
3468 DRM_DEBUG_KMS("FDI train done\n");
3469
3470 }
3471
3472 static const int snb_b_fdi_train_param[] = {
3473 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3474 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3475 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3476 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3477 };
3478
3479 /* The FDI link training functions for SNB/Cougarpoint. */
3480 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3481 {
3482 struct drm_device *dev = crtc->dev;
3483 struct drm_i915_private *dev_priv = dev->dev_private;
3484 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3485 int pipe = intel_crtc->pipe;
3486 u32 reg, temp, i, retry;
3487
3488 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3489 for train result */
3490 reg = FDI_RX_IMR(pipe);
3491 temp = I915_READ(reg);
3492 temp &= ~FDI_RX_SYMBOL_LOCK;
3493 temp &= ~FDI_RX_BIT_LOCK;
3494 I915_WRITE(reg, temp);
3495
3496 POSTING_READ(reg);
3497 udelay(150);
3498
3499 /* enable CPU FDI TX and PCH FDI RX */
3500 reg = FDI_TX_CTL(pipe);
3501 temp = I915_READ(reg);
3502 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3503 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3504 temp &= ~FDI_LINK_TRAIN_NONE;
3505 temp |= FDI_LINK_TRAIN_PATTERN_1;
3506 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3507 /* SNB-B */
3508 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3509 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3510
3511 I915_WRITE(FDI_RX_MISC(pipe),
3512 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3513
3514 reg = FDI_RX_CTL(pipe);
3515 temp = I915_READ(reg);
3516 if (HAS_PCH_CPT(dev)) {
3517 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3518 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3519 } else {
3520 temp &= ~FDI_LINK_TRAIN_NONE;
3521 temp |= FDI_LINK_TRAIN_PATTERN_1;
3522 }
3523 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3524
3525 POSTING_READ(reg);
3526 udelay(150);
3527
3528 for (i = 0; i < 4; i++) {
3529 reg = FDI_TX_CTL(pipe);
3530 temp = I915_READ(reg);
3531 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3532 temp |= snb_b_fdi_train_param[i];
3533 I915_WRITE(reg, temp);
3534
3535 POSTING_READ(reg);
3536 udelay(500);
3537
3538 for (retry = 0; retry < 5; retry++) {
3539 reg = FDI_RX_IIR(pipe);
3540 temp = I915_READ(reg);
3541 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3542 if (temp & FDI_RX_BIT_LOCK) {
3543 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3544 DRM_DEBUG_KMS("FDI train 1 done.\n");
3545 break;
3546 }
3547 udelay(50);
3548 }
3549 if (retry < 5)
3550 break;
3551 }
3552 if (i == 4)
3553 DRM_ERROR("FDI train 1 fail!\n");
3554
3555 /* Train 2 */
3556 reg = FDI_TX_CTL(pipe);
3557 temp = I915_READ(reg);
3558 temp &= ~FDI_LINK_TRAIN_NONE;
3559 temp |= FDI_LINK_TRAIN_PATTERN_2;
3560 if (IS_GEN6(dev)) {
3561 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3562 /* SNB-B */
3563 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3564 }
3565 I915_WRITE(reg, temp);
3566
3567 reg = FDI_RX_CTL(pipe);
3568 temp = I915_READ(reg);
3569 if (HAS_PCH_CPT(dev)) {
3570 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3571 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3572 } else {
3573 temp &= ~FDI_LINK_TRAIN_NONE;
3574 temp |= FDI_LINK_TRAIN_PATTERN_2;
3575 }
3576 I915_WRITE(reg, temp);
3577
3578 POSTING_READ(reg);
3579 udelay(150);
3580
3581 for (i = 0; i < 4; i++) {
3582 reg = FDI_TX_CTL(pipe);
3583 temp = I915_READ(reg);
3584 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3585 temp |= snb_b_fdi_train_param[i];
3586 I915_WRITE(reg, temp);
3587
3588 POSTING_READ(reg);
3589 udelay(500);
3590
3591 for (retry = 0; retry < 5; retry++) {
3592 reg = FDI_RX_IIR(pipe);
3593 temp = I915_READ(reg);
3594 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3595 if (temp & FDI_RX_SYMBOL_LOCK) {
3596 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3597 DRM_DEBUG_KMS("FDI train 2 done.\n");
3598 break;
3599 }
3600 udelay(50);
3601 }
3602 if (retry < 5)
3603 break;
3604 }
3605 if (i == 4)
3606 DRM_ERROR("FDI train 2 fail!\n");
3607
3608 DRM_DEBUG_KMS("FDI train done.\n");
3609 }
3610
3611 /* Manual link training for Ivy Bridge A0 parts */
3612 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3613 {
3614 struct drm_device *dev = crtc->dev;
3615 struct drm_i915_private *dev_priv = dev->dev_private;
3616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3617 int pipe = intel_crtc->pipe;
3618 u32 reg, temp, i, j;
3619
3620 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3621 for train result */
3622 reg = FDI_RX_IMR(pipe);
3623 temp = I915_READ(reg);
3624 temp &= ~FDI_RX_SYMBOL_LOCK;
3625 temp &= ~FDI_RX_BIT_LOCK;
3626 I915_WRITE(reg, temp);
3627
3628 POSTING_READ(reg);
3629 udelay(150);
3630
3631 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3632 I915_READ(FDI_RX_IIR(pipe)));
3633
3634 /* Try each vswing and preemphasis setting twice before moving on */
3635 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3636 /* disable first in case we need to retry */
3637 reg = FDI_TX_CTL(pipe);
3638 temp = I915_READ(reg);
3639 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3640 temp &= ~FDI_TX_ENABLE;
3641 I915_WRITE(reg, temp);
3642
3643 reg = FDI_RX_CTL(pipe);
3644 temp = I915_READ(reg);
3645 temp &= ~FDI_LINK_TRAIN_AUTO;
3646 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3647 temp &= ~FDI_RX_ENABLE;
3648 I915_WRITE(reg, temp);
3649
3650 /* enable CPU FDI TX and PCH FDI RX */
3651 reg = FDI_TX_CTL(pipe);
3652 temp = I915_READ(reg);
3653 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3654 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3655 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3656 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3657 temp |= snb_b_fdi_train_param[j/2];
3658 temp |= FDI_COMPOSITE_SYNC;
3659 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3660
3661 I915_WRITE(FDI_RX_MISC(pipe),
3662 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3663
3664 reg = FDI_RX_CTL(pipe);
3665 temp = I915_READ(reg);
3666 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3667 temp |= FDI_COMPOSITE_SYNC;
3668 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3669
3670 POSTING_READ(reg);
3671 udelay(1); /* should be 0.5us */
3672
3673 for (i = 0; i < 4; i++) {
3674 reg = FDI_RX_IIR(pipe);
3675 temp = I915_READ(reg);
3676 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3677
3678 if (temp & FDI_RX_BIT_LOCK ||
3679 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3680 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3681 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3682 i);
3683 break;
3684 }
3685 udelay(1); /* should be 0.5us */
3686 }
3687 if (i == 4) {
3688 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3689 continue;
3690 }
3691
3692 /* Train 2 */
3693 reg = FDI_TX_CTL(pipe);
3694 temp = I915_READ(reg);
3695 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3696 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3697 I915_WRITE(reg, temp);
3698
3699 reg = FDI_RX_CTL(pipe);
3700 temp = I915_READ(reg);
3701 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3702 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3703 I915_WRITE(reg, temp);
3704
3705 POSTING_READ(reg);
3706 udelay(2); /* should be 1.5us */
3707
3708 for (i = 0; i < 4; i++) {
3709 reg = FDI_RX_IIR(pipe);
3710 temp = I915_READ(reg);
3711 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3712
3713 if (temp & FDI_RX_SYMBOL_LOCK ||
3714 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3715 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3716 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3717 i);
3718 goto train_done;
3719 }
3720 udelay(2); /* should be 1.5us */
3721 }
3722 if (i == 4)
3723 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3724 }
3725
3726 train_done:
3727 DRM_DEBUG_KMS("FDI train done.\n");
3728 }
3729
3730 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3731 {
3732 struct drm_device *dev = intel_crtc->base.dev;
3733 struct drm_i915_private *dev_priv = dev->dev_private;
3734 int pipe = intel_crtc->pipe;
3735 u32 reg, temp;
3736
3737
3738 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3739 reg = FDI_RX_CTL(pipe);
3740 temp = I915_READ(reg);
3741 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3742 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3743 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3744 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3745
3746 POSTING_READ(reg);
3747 udelay(200);
3748
3749 /* Switch from Rawclk to PCDclk */
3750 temp = I915_READ(reg);
3751 I915_WRITE(reg, temp | FDI_PCDCLK);
3752
3753 POSTING_READ(reg);
3754 udelay(200);
3755
3756 /* Enable CPU FDI TX PLL, always on for Ironlake */
3757 reg = FDI_TX_CTL(pipe);
3758 temp = I915_READ(reg);
3759 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3760 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3761
3762 POSTING_READ(reg);
3763 udelay(100);
3764 }
3765 }
3766
3767 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3768 {
3769 struct drm_device *dev = intel_crtc->base.dev;
3770 struct drm_i915_private *dev_priv = dev->dev_private;
3771 int pipe = intel_crtc->pipe;
3772 u32 reg, temp;
3773
3774 /* Switch from PCDclk to Rawclk */
3775 reg = FDI_RX_CTL(pipe);
3776 temp = I915_READ(reg);
3777 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3778
3779 /* Disable CPU FDI TX PLL */
3780 reg = FDI_TX_CTL(pipe);
3781 temp = I915_READ(reg);
3782 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3783
3784 POSTING_READ(reg);
3785 udelay(100);
3786
3787 reg = FDI_RX_CTL(pipe);
3788 temp = I915_READ(reg);
3789 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3790
3791 /* Wait for the clocks to turn off. */
3792 POSTING_READ(reg);
3793 udelay(100);
3794 }
3795
3796 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3797 {
3798 struct drm_device *dev = crtc->dev;
3799 struct drm_i915_private *dev_priv = dev->dev_private;
3800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3801 int pipe = intel_crtc->pipe;
3802 u32 reg, temp;
3803
3804 /* disable CPU FDI tx and PCH FDI rx */
3805 reg = FDI_TX_CTL(pipe);
3806 temp = I915_READ(reg);
3807 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3808 POSTING_READ(reg);
3809
3810 reg = FDI_RX_CTL(pipe);
3811 temp = I915_READ(reg);
3812 temp &= ~(0x7 << 16);
3813 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3814 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3815
3816 POSTING_READ(reg);
3817 udelay(100);
3818
3819 /* Ironlake workaround, disable clock pointer after downing FDI */
3820 if (HAS_PCH_IBX(dev))
3821 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3822
3823 /* still set train pattern 1 */
3824 reg = FDI_TX_CTL(pipe);
3825 temp = I915_READ(reg);
3826 temp &= ~FDI_LINK_TRAIN_NONE;
3827 temp |= FDI_LINK_TRAIN_PATTERN_1;
3828 I915_WRITE(reg, temp);
3829
3830 reg = FDI_RX_CTL(pipe);
3831 temp = I915_READ(reg);
3832 if (HAS_PCH_CPT(dev)) {
3833 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3834 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3835 } else {
3836 temp &= ~FDI_LINK_TRAIN_NONE;
3837 temp |= FDI_LINK_TRAIN_PATTERN_1;
3838 }
3839 /* BPC in FDI rx is consistent with that in PIPECONF */
3840 temp &= ~(0x07 << 16);
3841 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3842 I915_WRITE(reg, temp);
3843
3844 POSTING_READ(reg);
3845 udelay(100);
3846 }
3847
3848 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3849 {
3850 struct intel_crtc *crtc;
3851
3852 /* Note that we don't need to be called with mode_config.lock here
3853 * as our list of CRTC objects is static for the lifetime of the
3854 * device and so cannot disappear as we iterate. Similarly, we can
3855 * happily treat the predicates as racy, atomic checks as userspace
3856 * cannot claim and pin a new fb without at least acquring the
3857 * struct_mutex and so serialising with us.
3858 */
3859 for_each_intel_crtc(dev, crtc) {
3860 if (atomic_read(&crtc->unpin_work_count) == 0)
3861 continue;
3862
3863 if (crtc->unpin_work)
3864 intel_wait_for_vblank(dev, crtc->pipe);
3865
3866 return true;
3867 }
3868
3869 return false;
3870 }
3871
3872 static void page_flip_completed(struct intel_crtc *intel_crtc)
3873 {
3874 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3875 struct intel_unpin_work *work = intel_crtc->unpin_work;
3876
3877 /* ensure that the unpin work is consistent wrt ->pending. */
3878 smp_rmb();
3879 intel_crtc->unpin_work = NULL;
3880
3881 if (work->event)
3882 drm_send_vblank_event(intel_crtc->base.dev,
3883 intel_crtc->pipe,
3884 work->event);
3885
3886 drm_crtc_vblank_put(&intel_crtc->base);
3887
3888 wake_up_all(&dev_priv->pending_flip_queue);
3889 queue_work(dev_priv->wq, &work->work);
3890
3891 trace_i915_flip_complete(intel_crtc->plane,
3892 work->pending_flip_obj);
3893 }
3894
3895 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3896 {
3897 struct drm_device *dev = crtc->dev;
3898 struct drm_i915_private *dev_priv = dev->dev_private;
3899
3900 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3901 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3902 !intel_crtc_has_pending_flip(crtc),
3903 60*HZ) == 0)) {
3904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3905
3906 spin_lock_irq(&dev->event_lock);
3907 if (intel_crtc->unpin_work) {
3908 WARN_ONCE(1, "Removing stuck page flip\n");
3909 page_flip_completed(intel_crtc);
3910 }
3911 spin_unlock_irq(&dev->event_lock);
3912 }
3913
3914 if (crtc->primary->fb) {
3915 mutex_lock(&dev->struct_mutex);
3916 intel_finish_fb(crtc->primary->fb);
3917 mutex_unlock(&dev->struct_mutex);
3918 }
3919 }
3920
3921 /* Program iCLKIP clock to the desired frequency */
3922 static void lpt_program_iclkip(struct drm_crtc *crtc)
3923 {
3924 struct drm_device *dev = crtc->dev;
3925 struct drm_i915_private *dev_priv = dev->dev_private;
3926 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3927 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3928 u32 temp;
3929
3930 mutex_lock(&dev_priv->sb_lock);
3931
3932 /* It is necessary to ungate the pixclk gate prior to programming
3933 * the divisors, and gate it back when it is done.
3934 */
3935 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3936
3937 /* Disable SSCCTL */
3938 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3939 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3940 SBI_SSCCTL_DISABLE,
3941 SBI_ICLK);
3942
3943 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3944 if (clock == 20000) {
3945 auxdiv = 1;
3946 divsel = 0x41;
3947 phaseinc = 0x20;
3948 } else {
3949 /* The iCLK virtual clock root frequency is in MHz,
3950 * but the adjusted_mode->crtc_clock in in KHz. To get the
3951 * divisors, it is necessary to divide one by another, so we
3952 * convert the virtual clock precision to KHz here for higher
3953 * precision.
3954 */
3955 u32 iclk_virtual_root_freq = 172800 * 1000;
3956 u32 iclk_pi_range = 64;
3957 u32 desired_divisor, msb_divisor_value, pi_value;
3958
3959 desired_divisor = (iclk_virtual_root_freq / clock);
3960 msb_divisor_value = desired_divisor / iclk_pi_range;
3961 pi_value = desired_divisor % iclk_pi_range;
3962
3963 auxdiv = 0;
3964 divsel = msb_divisor_value - 2;
3965 phaseinc = pi_value;
3966 }
3967
3968 /* This should not happen with any sane values */
3969 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3970 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3971 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3972 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3973
3974 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3975 clock,
3976 auxdiv,
3977 divsel,
3978 phasedir,
3979 phaseinc);
3980
3981 /* Program SSCDIVINTPHASE6 */
3982 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3983 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3984 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3985 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3986 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3987 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3988 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3989 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3990
3991 /* Program SSCAUXDIV */
3992 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3993 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3994 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3995 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3996
3997 /* Enable modulator and associated divider */
3998 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3999 temp &= ~SBI_SSCCTL_DISABLE;
4000 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4001
4002 /* Wait for initialization time */
4003 udelay(24);
4004
4005 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4006
4007 mutex_unlock(&dev_priv->sb_lock);
4008 }
4009
4010 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4011 enum pipe pch_transcoder)
4012 {
4013 struct drm_device *dev = crtc->base.dev;
4014 struct drm_i915_private *dev_priv = dev->dev_private;
4015 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4016
4017 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4018 I915_READ(HTOTAL(cpu_transcoder)));
4019 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4020 I915_READ(HBLANK(cpu_transcoder)));
4021 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4022 I915_READ(HSYNC(cpu_transcoder)));
4023
4024 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4025 I915_READ(VTOTAL(cpu_transcoder)));
4026 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4027 I915_READ(VBLANK(cpu_transcoder)));
4028 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4029 I915_READ(VSYNC(cpu_transcoder)));
4030 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4031 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4032 }
4033
4034 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4035 {
4036 struct drm_i915_private *dev_priv = dev->dev_private;
4037 uint32_t temp;
4038
4039 temp = I915_READ(SOUTH_CHICKEN1);
4040 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4041 return;
4042
4043 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4044 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4045
4046 temp &= ~FDI_BC_BIFURCATION_SELECT;
4047 if (enable)
4048 temp |= FDI_BC_BIFURCATION_SELECT;
4049
4050 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4051 I915_WRITE(SOUTH_CHICKEN1, temp);
4052 POSTING_READ(SOUTH_CHICKEN1);
4053 }
4054
4055 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4056 {
4057 struct drm_device *dev = intel_crtc->base.dev;
4058
4059 switch (intel_crtc->pipe) {
4060 case PIPE_A:
4061 break;
4062 case PIPE_B:
4063 if (intel_crtc->config->fdi_lanes > 2)
4064 cpt_set_fdi_bc_bifurcation(dev, false);
4065 else
4066 cpt_set_fdi_bc_bifurcation(dev, true);
4067
4068 break;
4069 case PIPE_C:
4070 cpt_set_fdi_bc_bifurcation(dev, true);
4071
4072 break;
4073 default:
4074 BUG();
4075 }
4076 }
4077
4078 /*
4079 * Enable PCH resources required for PCH ports:
4080 * - PCH PLLs
4081 * - FDI training & RX/TX
4082 * - update transcoder timings
4083 * - DP transcoding bits
4084 * - transcoder
4085 */
4086 static void ironlake_pch_enable(struct drm_crtc *crtc)
4087 {
4088 struct drm_device *dev = crtc->dev;
4089 struct drm_i915_private *dev_priv = dev->dev_private;
4090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4091 int pipe = intel_crtc->pipe;
4092 u32 reg, temp;
4093
4094 assert_pch_transcoder_disabled(dev_priv, pipe);
4095
4096 if (IS_IVYBRIDGE(dev))
4097 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4098
4099 /* Write the TU size bits before fdi link training, so that error
4100 * detection works. */
4101 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4102 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4103
4104 /* For PCH output, training FDI link */
4105 dev_priv->display.fdi_link_train(crtc);
4106
4107 /* We need to program the right clock selection before writing the pixel
4108 * mutliplier into the DPLL. */
4109 if (HAS_PCH_CPT(dev)) {
4110 u32 sel;
4111
4112 temp = I915_READ(PCH_DPLL_SEL);
4113 temp |= TRANS_DPLL_ENABLE(pipe);
4114 sel = TRANS_DPLLB_SEL(pipe);
4115 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4116 temp |= sel;
4117 else
4118 temp &= ~sel;
4119 I915_WRITE(PCH_DPLL_SEL, temp);
4120 }
4121
4122 /* XXX: pch pll's can be enabled any time before we enable the PCH
4123 * transcoder, and we actually should do this to not upset any PCH
4124 * transcoder that already use the clock when we share it.
4125 *
4126 * Note that enable_shared_dpll tries to do the right thing, but
4127 * get_shared_dpll unconditionally resets the pll - we need that to have
4128 * the right LVDS enable sequence. */
4129 intel_enable_shared_dpll(intel_crtc);
4130
4131 /* set transcoder timing, panel must allow it */
4132 assert_panel_unlocked(dev_priv, pipe);
4133 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4134
4135 intel_fdi_normal_train(crtc);
4136
4137 /* For PCH DP, enable TRANS_DP_CTL */
4138 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4139 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4140 reg = TRANS_DP_CTL(pipe);
4141 temp = I915_READ(reg);
4142 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4143 TRANS_DP_SYNC_MASK |
4144 TRANS_DP_BPC_MASK);
4145 temp |= TRANS_DP_OUTPUT_ENABLE;
4146 temp |= bpc << 9; /* same format but at 11:9 */
4147
4148 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4149 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4150 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4151 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4152
4153 switch (intel_trans_dp_port_sel(crtc)) {
4154 case PCH_DP_B:
4155 temp |= TRANS_DP_PORT_SEL_B;
4156 break;
4157 case PCH_DP_C:
4158 temp |= TRANS_DP_PORT_SEL_C;
4159 break;
4160 case PCH_DP_D:
4161 temp |= TRANS_DP_PORT_SEL_D;
4162 break;
4163 default:
4164 BUG();
4165 }
4166
4167 I915_WRITE(reg, temp);
4168 }
4169
4170 ironlake_enable_pch_transcoder(dev_priv, pipe);
4171 }
4172
4173 static void lpt_pch_enable(struct drm_crtc *crtc)
4174 {
4175 struct drm_device *dev = crtc->dev;
4176 struct drm_i915_private *dev_priv = dev->dev_private;
4177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4178 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4179
4180 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4181
4182 lpt_program_iclkip(crtc);
4183
4184 /* Set transcoder timing. */
4185 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4186
4187 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4188 }
4189
4190 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4191 struct intel_crtc_state *crtc_state)
4192 {
4193 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4194 struct intel_shared_dpll *pll;
4195 struct intel_shared_dpll_config *shared_dpll;
4196 enum intel_dpll_id i;
4197
4198 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4199
4200 if (HAS_PCH_IBX(dev_priv->dev)) {
4201 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4202 i = (enum intel_dpll_id) crtc->pipe;
4203 pll = &dev_priv->shared_dplls[i];
4204
4205 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4206 crtc->base.base.id, pll->name);
4207
4208 WARN_ON(shared_dpll[i].crtc_mask);
4209
4210 goto found;
4211 }
4212
4213 if (IS_BROXTON(dev_priv->dev)) {
4214 /* PLL is attached to port in bxt */
4215 struct intel_encoder *encoder;
4216 struct intel_digital_port *intel_dig_port;
4217
4218 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4219 if (WARN_ON(!encoder))
4220 return NULL;
4221
4222 intel_dig_port = enc_to_dig_port(&encoder->base);
4223 /* 1:1 mapping between ports and PLLs */
4224 i = (enum intel_dpll_id)intel_dig_port->port;
4225 pll = &dev_priv->shared_dplls[i];
4226 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4227 crtc->base.base.id, pll->name);
4228 WARN_ON(shared_dpll[i].crtc_mask);
4229
4230 goto found;
4231 }
4232
4233 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4234 pll = &dev_priv->shared_dplls[i];
4235
4236 /* Only want to check enabled timings first */
4237 if (shared_dpll[i].crtc_mask == 0)
4238 continue;
4239
4240 if (memcmp(&crtc_state->dpll_hw_state,
4241 &shared_dpll[i].hw_state,
4242 sizeof(crtc_state->dpll_hw_state)) == 0) {
4243 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4244 crtc->base.base.id, pll->name,
4245 shared_dpll[i].crtc_mask,
4246 pll->active);
4247 goto found;
4248 }
4249 }
4250
4251 /* Ok no matching timings, maybe there's a free one? */
4252 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4253 pll = &dev_priv->shared_dplls[i];
4254 if (shared_dpll[i].crtc_mask == 0) {
4255 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4256 crtc->base.base.id, pll->name);
4257 goto found;
4258 }
4259 }
4260
4261 return NULL;
4262
4263 found:
4264 if (shared_dpll[i].crtc_mask == 0)
4265 shared_dpll[i].hw_state =
4266 crtc_state->dpll_hw_state;
4267
4268 crtc_state->shared_dpll = i;
4269 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4270 pipe_name(crtc->pipe));
4271
4272 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4273
4274 return pll;
4275 }
4276
4277 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4278 {
4279 struct drm_i915_private *dev_priv = to_i915(state->dev);
4280 struct intel_shared_dpll_config *shared_dpll;
4281 struct intel_shared_dpll *pll;
4282 enum intel_dpll_id i;
4283
4284 if (!to_intel_atomic_state(state)->dpll_set)
4285 return;
4286
4287 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4288 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4289 pll = &dev_priv->shared_dplls[i];
4290 pll->config = shared_dpll[i];
4291 }
4292 }
4293
4294 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4295 {
4296 struct drm_i915_private *dev_priv = dev->dev_private;
4297 int dslreg = PIPEDSL(pipe);
4298 u32 temp;
4299
4300 temp = I915_READ(dslreg);
4301 udelay(500);
4302 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4303 if (wait_for(I915_READ(dslreg) != temp, 5))
4304 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4305 }
4306 }
4307
4308 static int
4309 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4310 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4311 int src_w, int src_h, int dst_w, int dst_h)
4312 {
4313 struct intel_crtc_scaler_state *scaler_state =
4314 &crtc_state->scaler_state;
4315 struct intel_crtc *intel_crtc =
4316 to_intel_crtc(crtc_state->base.crtc);
4317 int need_scaling;
4318
4319 need_scaling = intel_rotation_90_or_270(rotation) ?
4320 (src_h != dst_w || src_w != dst_h):
4321 (src_w != dst_w || src_h != dst_h);
4322
4323 /*
4324 * if plane is being disabled or scaler is no more required or force detach
4325 * - free scaler binded to this plane/crtc
4326 * - in order to do this, update crtc->scaler_usage
4327 *
4328 * Here scaler state in crtc_state is set free so that
4329 * scaler can be assigned to other user. Actual register
4330 * update to free the scaler is done in plane/panel-fit programming.
4331 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4332 */
4333 if (force_detach || !need_scaling) {
4334 if (*scaler_id >= 0) {
4335 scaler_state->scaler_users &= ~(1 << scaler_user);
4336 scaler_state->scalers[*scaler_id].in_use = 0;
4337
4338 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4339 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4340 intel_crtc->pipe, scaler_user, *scaler_id,
4341 scaler_state->scaler_users);
4342 *scaler_id = -1;
4343 }
4344 return 0;
4345 }
4346
4347 /* range checks */
4348 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4349 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4350
4351 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4352 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4353 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4354 "size is out of scaler range\n",
4355 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4356 return -EINVAL;
4357 }
4358
4359 /* mark this plane as a scaler user in crtc_state */
4360 scaler_state->scaler_users |= (1 << scaler_user);
4361 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4362 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4363 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4364 scaler_state->scaler_users);
4365
4366 return 0;
4367 }
4368
4369 /**
4370 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4371 *
4372 * @state: crtc's scaler state
4373 *
4374 * Return
4375 * 0 - scaler_usage updated successfully
4376 * error - requested scaling cannot be supported or other error condition
4377 */
4378 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4379 {
4380 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4381 struct drm_display_mode *adjusted_mode =
4382 &state->base.adjusted_mode;
4383
4384 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4385 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4386
4387 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4388 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4389 state->pipe_src_w, state->pipe_src_h,
4390 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
4391 }
4392
4393 /**
4394 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4395 *
4396 * @state: crtc's scaler state
4397 * @plane_state: atomic plane state to update
4398 *
4399 * Return
4400 * 0 - scaler_usage updated successfully
4401 * error - requested scaling cannot be supported or other error condition
4402 */
4403 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4404 struct intel_plane_state *plane_state)
4405 {
4406
4407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4408 struct intel_plane *intel_plane =
4409 to_intel_plane(plane_state->base.plane);
4410 struct drm_framebuffer *fb = plane_state->base.fb;
4411 int ret;
4412
4413 bool force_detach = !fb || !plane_state->visible;
4414
4415 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4416 intel_plane->base.base.id, intel_crtc->pipe,
4417 drm_plane_index(&intel_plane->base));
4418
4419 ret = skl_update_scaler(crtc_state, force_detach,
4420 drm_plane_index(&intel_plane->base),
4421 &plane_state->scaler_id,
4422 plane_state->base.rotation,
4423 drm_rect_width(&plane_state->src) >> 16,
4424 drm_rect_height(&plane_state->src) >> 16,
4425 drm_rect_width(&plane_state->dst),
4426 drm_rect_height(&plane_state->dst));
4427
4428 if (ret || plane_state->scaler_id < 0)
4429 return ret;
4430
4431 /* check colorkey */
4432 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4433 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4434 intel_plane->base.base.id);
4435 return -EINVAL;
4436 }
4437
4438 /* Check src format */
4439 switch (fb->pixel_format) {
4440 case DRM_FORMAT_RGB565:
4441 case DRM_FORMAT_XBGR8888:
4442 case DRM_FORMAT_XRGB8888:
4443 case DRM_FORMAT_ABGR8888:
4444 case DRM_FORMAT_ARGB8888:
4445 case DRM_FORMAT_XRGB2101010:
4446 case DRM_FORMAT_XBGR2101010:
4447 case DRM_FORMAT_YUYV:
4448 case DRM_FORMAT_YVYU:
4449 case DRM_FORMAT_UYVY:
4450 case DRM_FORMAT_VYUY:
4451 break;
4452 default:
4453 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4454 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4455 return -EINVAL;
4456 }
4457
4458 return 0;
4459 }
4460
4461 static void skylake_scaler_disable(struct intel_crtc *crtc)
4462 {
4463 int i;
4464
4465 for (i = 0; i < crtc->num_scalers; i++)
4466 skl_detach_scaler(crtc, i);
4467 }
4468
4469 static void skylake_pfit_enable(struct intel_crtc *crtc)
4470 {
4471 struct drm_device *dev = crtc->base.dev;
4472 struct drm_i915_private *dev_priv = dev->dev_private;
4473 int pipe = crtc->pipe;
4474 struct intel_crtc_scaler_state *scaler_state =
4475 &crtc->config->scaler_state;
4476
4477 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4478
4479 if (crtc->config->pch_pfit.enabled) {
4480 int id;
4481
4482 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4483 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4484 return;
4485 }
4486
4487 id = scaler_state->scaler_id;
4488 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4489 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4490 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4491 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4492
4493 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4494 }
4495 }
4496
4497 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4498 {
4499 struct drm_device *dev = crtc->base.dev;
4500 struct drm_i915_private *dev_priv = dev->dev_private;
4501 int pipe = crtc->pipe;
4502
4503 if (crtc->config->pch_pfit.enabled) {
4504 /* Force use of hard-coded filter coefficients
4505 * as some pre-programmed values are broken,
4506 * e.g. x201.
4507 */
4508 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4509 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4510 PF_PIPE_SEL_IVB(pipe));
4511 else
4512 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4513 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4514 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4515 }
4516 }
4517
4518 void hsw_enable_ips(struct intel_crtc *crtc)
4519 {
4520 struct drm_device *dev = crtc->base.dev;
4521 struct drm_i915_private *dev_priv = dev->dev_private;
4522
4523 if (!crtc->config->ips_enabled)
4524 return;
4525
4526 /* We can only enable IPS after we enable a plane and wait for a vblank */
4527 intel_wait_for_vblank(dev, crtc->pipe);
4528
4529 assert_plane_enabled(dev_priv, crtc->plane);
4530 if (IS_BROADWELL(dev)) {
4531 mutex_lock(&dev_priv->rps.hw_lock);
4532 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4533 mutex_unlock(&dev_priv->rps.hw_lock);
4534 /* Quoting Art Runyan: "its not safe to expect any particular
4535 * value in IPS_CTL bit 31 after enabling IPS through the
4536 * mailbox." Moreover, the mailbox may return a bogus state,
4537 * so we need to just enable it and continue on.
4538 */
4539 } else {
4540 I915_WRITE(IPS_CTL, IPS_ENABLE);
4541 /* The bit only becomes 1 in the next vblank, so this wait here
4542 * is essentially intel_wait_for_vblank. If we don't have this
4543 * and don't wait for vblanks until the end of crtc_enable, then
4544 * the HW state readout code will complain that the expected
4545 * IPS_CTL value is not the one we read. */
4546 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4547 DRM_ERROR("Timed out waiting for IPS enable\n");
4548 }
4549 }
4550
4551 void hsw_disable_ips(struct intel_crtc *crtc)
4552 {
4553 struct drm_device *dev = crtc->base.dev;
4554 struct drm_i915_private *dev_priv = dev->dev_private;
4555
4556 if (!crtc->config->ips_enabled)
4557 return;
4558
4559 assert_plane_enabled(dev_priv, crtc->plane);
4560 if (IS_BROADWELL(dev)) {
4561 mutex_lock(&dev_priv->rps.hw_lock);
4562 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4563 mutex_unlock(&dev_priv->rps.hw_lock);
4564 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4565 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4566 DRM_ERROR("Timed out waiting for IPS disable\n");
4567 } else {
4568 I915_WRITE(IPS_CTL, 0);
4569 POSTING_READ(IPS_CTL);
4570 }
4571
4572 /* We need to wait for a vblank before we can disable the plane. */
4573 intel_wait_for_vblank(dev, crtc->pipe);
4574 }
4575
4576 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4577 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4578 {
4579 struct drm_device *dev = crtc->dev;
4580 struct drm_i915_private *dev_priv = dev->dev_private;
4581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4582 enum pipe pipe = intel_crtc->pipe;
4583 int palreg = PALETTE(pipe);
4584 int i;
4585 bool reenable_ips = false;
4586
4587 /* The clocks have to be on to load the palette. */
4588 if (!crtc->state->active)
4589 return;
4590
4591 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4592 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4593 assert_dsi_pll_enabled(dev_priv);
4594 else
4595 assert_pll_enabled(dev_priv, pipe);
4596 }
4597
4598 /* use legacy palette for Ironlake */
4599 if (!HAS_GMCH_DISPLAY(dev))
4600 palreg = LGC_PALETTE(pipe);
4601
4602 /* Workaround : Do not read or write the pipe palette/gamma data while
4603 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4604 */
4605 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4606 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4607 GAMMA_MODE_MODE_SPLIT)) {
4608 hsw_disable_ips(intel_crtc);
4609 reenable_ips = true;
4610 }
4611
4612 for (i = 0; i < 256; i++) {
4613 I915_WRITE(palreg + 4 * i,
4614 (intel_crtc->lut_r[i] << 16) |
4615 (intel_crtc->lut_g[i] << 8) |
4616 intel_crtc->lut_b[i]);
4617 }
4618
4619 if (reenable_ips)
4620 hsw_enable_ips(intel_crtc);
4621 }
4622
4623 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4624 {
4625 if (intel_crtc->overlay) {
4626 struct drm_device *dev = intel_crtc->base.dev;
4627 struct drm_i915_private *dev_priv = dev->dev_private;
4628
4629 mutex_lock(&dev->struct_mutex);
4630 dev_priv->mm.interruptible = false;
4631 (void) intel_overlay_switch_off(intel_crtc->overlay);
4632 dev_priv->mm.interruptible = true;
4633 mutex_unlock(&dev->struct_mutex);
4634 }
4635
4636 /* Let userspace switch the overlay on again. In most cases userspace
4637 * has to recompute where to put it anyway.
4638 */
4639 }
4640
4641 /**
4642 * intel_post_enable_primary - Perform operations after enabling primary plane
4643 * @crtc: the CRTC whose primary plane was just enabled
4644 *
4645 * Performs potentially sleeping operations that must be done after the primary
4646 * plane is enabled, such as updating FBC and IPS. Note that this may be
4647 * called due to an explicit primary plane update, or due to an implicit
4648 * re-enable that is caused when a sprite plane is updated to no longer
4649 * completely hide the primary plane.
4650 */
4651 static void
4652 intel_post_enable_primary(struct drm_crtc *crtc)
4653 {
4654 struct drm_device *dev = crtc->dev;
4655 struct drm_i915_private *dev_priv = dev->dev_private;
4656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4657 int pipe = intel_crtc->pipe;
4658
4659 /*
4660 * BDW signals flip done immediately if the plane
4661 * is disabled, even if the plane enable is already
4662 * armed to occur at the next vblank :(
4663 */
4664 if (IS_BROADWELL(dev))
4665 intel_wait_for_vblank(dev, pipe);
4666
4667 /*
4668 * FIXME IPS should be fine as long as one plane is
4669 * enabled, but in practice it seems to have problems
4670 * when going from primary only to sprite only and vice
4671 * versa.
4672 */
4673 hsw_enable_ips(intel_crtc);
4674
4675 /*
4676 * Gen2 reports pipe underruns whenever all planes are disabled.
4677 * So don't enable underrun reporting before at least some planes
4678 * are enabled.
4679 * FIXME: Need to fix the logic to work when we turn off all planes
4680 * but leave the pipe running.
4681 */
4682 if (IS_GEN2(dev))
4683 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4684
4685 /* Underruns don't raise interrupts, so check manually. */
4686 if (HAS_GMCH_DISPLAY(dev))
4687 i9xx_check_fifo_underruns(dev_priv);
4688 }
4689
4690 /**
4691 * intel_pre_disable_primary - Perform operations before disabling primary plane
4692 * @crtc: the CRTC whose primary plane is to be disabled
4693 *
4694 * Performs potentially sleeping operations that must be done before the
4695 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4696 * be called due to an explicit primary plane update, or due to an implicit
4697 * disable that is caused when a sprite plane completely hides the primary
4698 * plane.
4699 */
4700 static void
4701 intel_pre_disable_primary(struct drm_crtc *crtc)
4702 {
4703 struct drm_device *dev = crtc->dev;
4704 struct drm_i915_private *dev_priv = dev->dev_private;
4705 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4706 int pipe = intel_crtc->pipe;
4707
4708 /*
4709 * Gen2 reports pipe underruns whenever all planes are disabled.
4710 * So diasble underrun reporting before all the planes get disabled.
4711 * FIXME: Need to fix the logic to work when we turn off all planes
4712 * but leave the pipe running.
4713 */
4714 if (IS_GEN2(dev))
4715 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4716
4717 /*
4718 * Vblank time updates from the shadow to live plane control register
4719 * are blocked if the memory self-refresh mode is active at that
4720 * moment. So to make sure the plane gets truly disabled, disable
4721 * first the self-refresh mode. The self-refresh enable bit in turn
4722 * will be checked/applied by the HW only at the next frame start
4723 * event which is after the vblank start event, so we need to have a
4724 * wait-for-vblank between disabling the plane and the pipe.
4725 */
4726 if (HAS_GMCH_DISPLAY(dev)) {
4727 intel_set_memory_cxsr(dev_priv, false);
4728 dev_priv->wm.vlv.cxsr = false;
4729 intel_wait_for_vblank(dev, pipe);
4730 }
4731
4732 /*
4733 * FIXME IPS should be fine as long as one plane is
4734 * enabled, but in practice it seems to have problems
4735 * when going from primary only to sprite only and vice
4736 * versa.
4737 */
4738 hsw_disable_ips(intel_crtc);
4739 }
4740
4741 static void intel_post_plane_update(struct intel_crtc *crtc)
4742 {
4743 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4744 struct drm_device *dev = crtc->base.dev;
4745 struct drm_i915_private *dev_priv = dev->dev_private;
4746 struct drm_plane *plane;
4747
4748 if (atomic->wait_vblank)
4749 intel_wait_for_vblank(dev, crtc->pipe);
4750
4751 intel_frontbuffer_flip(dev, atomic->fb_bits);
4752
4753 if (atomic->disable_cxsr)
4754 crtc->wm.cxsr_allowed = true;
4755
4756 if (crtc->atomic.update_wm_post)
4757 intel_update_watermarks(&crtc->base);
4758
4759 if (atomic->update_fbc)
4760 intel_fbc_update(dev_priv);
4761
4762 if (atomic->post_enable_primary)
4763 intel_post_enable_primary(&crtc->base);
4764
4765 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4766 intel_update_sprite_watermarks(plane, &crtc->base,
4767 0, 0, 0, false, false);
4768
4769 memset(atomic, 0, sizeof(*atomic));
4770 }
4771
4772 static void intel_pre_plane_update(struct intel_crtc *crtc)
4773 {
4774 struct drm_device *dev = crtc->base.dev;
4775 struct drm_i915_private *dev_priv = dev->dev_private;
4776 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4777 struct drm_plane *p;
4778
4779 /* Track fb's for any planes being disabled */
4780 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4781 struct intel_plane *plane = to_intel_plane(p);
4782
4783 mutex_lock(&dev->struct_mutex);
4784 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4785 plane->frontbuffer_bit);
4786 mutex_unlock(&dev->struct_mutex);
4787 }
4788
4789 if (atomic->wait_for_flips)
4790 intel_crtc_wait_for_pending_flips(&crtc->base);
4791
4792 if (atomic->disable_fbc)
4793 intel_fbc_disable_crtc(crtc);
4794
4795 if (crtc->atomic.disable_ips)
4796 hsw_disable_ips(crtc);
4797
4798 if (atomic->pre_disable_primary)
4799 intel_pre_disable_primary(&crtc->base);
4800
4801 if (atomic->disable_cxsr) {
4802 crtc->wm.cxsr_allowed = false;
4803 intel_set_memory_cxsr(dev_priv, false);
4804 }
4805 }
4806
4807 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4808 {
4809 struct drm_device *dev = crtc->dev;
4810 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4811 struct drm_plane *p;
4812 int pipe = intel_crtc->pipe;
4813
4814 intel_crtc_dpms_overlay_disable(intel_crtc);
4815
4816 drm_for_each_plane_mask(p, dev, plane_mask)
4817 to_intel_plane(p)->disable_plane(p, crtc);
4818
4819 /*
4820 * FIXME: Once we grow proper nuclear flip support out of this we need
4821 * to compute the mask of flip planes precisely. For the time being
4822 * consider this a flip to a NULL plane.
4823 */
4824 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4825 }
4826
4827 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4828 {
4829 struct drm_device *dev = crtc->dev;
4830 struct drm_i915_private *dev_priv = dev->dev_private;
4831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4832 struct intel_encoder *encoder;
4833 int pipe = intel_crtc->pipe;
4834
4835 if (WARN_ON(intel_crtc->active))
4836 return;
4837
4838 if (intel_crtc->config->has_pch_encoder)
4839 intel_prepare_shared_dpll(intel_crtc);
4840
4841 if (intel_crtc->config->has_dp_encoder)
4842 intel_dp_set_m_n(intel_crtc, M1_N1);
4843
4844 intel_set_pipe_timings(intel_crtc);
4845
4846 if (intel_crtc->config->has_pch_encoder) {
4847 intel_cpu_transcoder_set_m_n(intel_crtc,
4848 &intel_crtc->config->fdi_m_n, NULL);
4849 }
4850
4851 ironlake_set_pipeconf(crtc);
4852
4853 intel_crtc->active = true;
4854
4855 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4856 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4857
4858 for_each_encoder_on_crtc(dev, crtc, encoder)
4859 if (encoder->pre_enable)
4860 encoder->pre_enable(encoder);
4861
4862 if (intel_crtc->config->has_pch_encoder) {
4863 /* Note: FDI PLL enabling _must_ be done before we enable the
4864 * cpu pipes, hence this is separate from all the other fdi/pch
4865 * enabling. */
4866 ironlake_fdi_pll_enable(intel_crtc);
4867 } else {
4868 assert_fdi_tx_disabled(dev_priv, pipe);
4869 assert_fdi_rx_disabled(dev_priv, pipe);
4870 }
4871
4872 ironlake_pfit_enable(intel_crtc);
4873
4874 /*
4875 * On ILK+ LUT must be loaded before the pipe is running but with
4876 * clocks enabled
4877 */
4878 intel_crtc_load_lut(crtc);
4879
4880 intel_update_watermarks(crtc);
4881 intel_enable_pipe(intel_crtc);
4882
4883 if (intel_crtc->config->has_pch_encoder)
4884 ironlake_pch_enable(crtc);
4885
4886 assert_vblank_disabled(crtc);
4887 drm_crtc_vblank_on(crtc);
4888
4889 for_each_encoder_on_crtc(dev, crtc, encoder)
4890 encoder->enable(encoder);
4891
4892 if (HAS_PCH_CPT(dev))
4893 cpt_verify_modeset(dev, intel_crtc->pipe);
4894 }
4895
4896 /* IPS only exists on ULT machines and is tied to pipe A. */
4897 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4898 {
4899 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4900 }
4901
4902 static void haswell_crtc_enable(struct drm_crtc *crtc)
4903 {
4904 struct drm_device *dev = crtc->dev;
4905 struct drm_i915_private *dev_priv = dev->dev_private;
4906 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4907 struct intel_encoder *encoder;
4908 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4909 struct intel_crtc_state *pipe_config =
4910 to_intel_crtc_state(crtc->state);
4911
4912 if (WARN_ON(intel_crtc->active))
4913 return;
4914
4915 if (intel_crtc_to_shared_dpll(intel_crtc))
4916 intel_enable_shared_dpll(intel_crtc);
4917
4918 if (intel_crtc->config->has_dp_encoder)
4919 intel_dp_set_m_n(intel_crtc, M1_N1);
4920
4921 intel_set_pipe_timings(intel_crtc);
4922
4923 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4924 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4925 intel_crtc->config->pixel_multiplier - 1);
4926 }
4927
4928 if (intel_crtc->config->has_pch_encoder) {
4929 intel_cpu_transcoder_set_m_n(intel_crtc,
4930 &intel_crtc->config->fdi_m_n, NULL);
4931 }
4932
4933 haswell_set_pipeconf(crtc);
4934
4935 intel_set_pipe_csc(crtc);
4936
4937 intel_crtc->active = true;
4938
4939 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4940 for_each_encoder_on_crtc(dev, crtc, encoder)
4941 if (encoder->pre_enable)
4942 encoder->pre_enable(encoder);
4943
4944 if (intel_crtc->config->has_pch_encoder) {
4945 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4946 true);
4947 dev_priv->display.fdi_link_train(crtc);
4948 }
4949
4950 intel_ddi_enable_pipe_clock(intel_crtc);
4951
4952 if (INTEL_INFO(dev)->gen == 9)
4953 skylake_pfit_enable(intel_crtc);
4954 else if (INTEL_INFO(dev)->gen < 9)
4955 ironlake_pfit_enable(intel_crtc);
4956 else
4957 MISSING_CASE(INTEL_INFO(dev)->gen);
4958
4959 /*
4960 * On ILK+ LUT must be loaded before the pipe is running but with
4961 * clocks enabled
4962 */
4963 intel_crtc_load_lut(crtc);
4964
4965 intel_ddi_set_pipe_settings(crtc);
4966 intel_ddi_enable_transcoder_func(crtc);
4967
4968 intel_update_watermarks(crtc);
4969 intel_enable_pipe(intel_crtc);
4970
4971 if (intel_crtc->config->has_pch_encoder)
4972 lpt_pch_enable(crtc);
4973
4974 if (intel_crtc->config->dp_encoder_is_mst)
4975 intel_ddi_set_vc_payload_alloc(crtc, true);
4976
4977 assert_vblank_disabled(crtc);
4978 drm_crtc_vblank_on(crtc);
4979
4980 for_each_encoder_on_crtc(dev, crtc, encoder) {
4981 encoder->enable(encoder);
4982 intel_opregion_notify_encoder(encoder, true);
4983 }
4984
4985 /* If we change the relative order between pipe/planes enabling, we need
4986 * to change the workaround. */
4987 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4988 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4989 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4990 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4991 }
4992 }
4993
4994 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4995 {
4996 struct drm_device *dev = crtc->base.dev;
4997 struct drm_i915_private *dev_priv = dev->dev_private;
4998 int pipe = crtc->pipe;
4999
5000 /* To avoid upsetting the power well on haswell only disable the pfit if
5001 * it's in use. The hw state code will make sure we get this right. */
5002 if (crtc->config->pch_pfit.enabled) {
5003 I915_WRITE(PF_CTL(pipe), 0);
5004 I915_WRITE(PF_WIN_POS(pipe), 0);
5005 I915_WRITE(PF_WIN_SZ(pipe), 0);
5006 }
5007 }
5008
5009 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5010 {
5011 struct drm_device *dev = crtc->dev;
5012 struct drm_i915_private *dev_priv = dev->dev_private;
5013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5014 struct intel_encoder *encoder;
5015 int pipe = intel_crtc->pipe;
5016 u32 reg, temp;
5017
5018 for_each_encoder_on_crtc(dev, crtc, encoder)
5019 encoder->disable(encoder);
5020
5021 drm_crtc_vblank_off(crtc);
5022 assert_vblank_disabled(crtc);
5023
5024 if (intel_crtc->config->has_pch_encoder)
5025 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5026
5027 intel_disable_pipe(intel_crtc);
5028
5029 ironlake_pfit_disable(intel_crtc);
5030
5031 if (intel_crtc->config->has_pch_encoder)
5032 ironlake_fdi_disable(crtc);
5033
5034 for_each_encoder_on_crtc(dev, crtc, encoder)
5035 if (encoder->post_disable)
5036 encoder->post_disable(encoder);
5037
5038 if (intel_crtc->config->has_pch_encoder) {
5039 ironlake_disable_pch_transcoder(dev_priv, pipe);
5040
5041 if (HAS_PCH_CPT(dev)) {
5042 /* disable TRANS_DP_CTL */
5043 reg = TRANS_DP_CTL(pipe);
5044 temp = I915_READ(reg);
5045 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5046 TRANS_DP_PORT_SEL_MASK);
5047 temp |= TRANS_DP_PORT_SEL_NONE;
5048 I915_WRITE(reg, temp);
5049
5050 /* disable DPLL_SEL */
5051 temp = I915_READ(PCH_DPLL_SEL);
5052 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5053 I915_WRITE(PCH_DPLL_SEL, temp);
5054 }
5055
5056 ironlake_fdi_pll_disable(intel_crtc);
5057 }
5058
5059 intel_crtc->active = false;
5060 intel_update_watermarks(crtc);
5061 }
5062
5063 static void haswell_crtc_disable(struct drm_crtc *crtc)
5064 {
5065 struct drm_device *dev = crtc->dev;
5066 struct drm_i915_private *dev_priv = dev->dev_private;
5067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5068 struct intel_encoder *encoder;
5069 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5070
5071 for_each_encoder_on_crtc(dev, crtc, encoder) {
5072 intel_opregion_notify_encoder(encoder, false);
5073 encoder->disable(encoder);
5074 }
5075
5076 drm_crtc_vblank_off(crtc);
5077 assert_vblank_disabled(crtc);
5078
5079 if (intel_crtc->config->has_pch_encoder)
5080 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5081 false);
5082 intel_disable_pipe(intel_crtc);
5083
5084 if (intel_crtc->config->dp_encoder_is_mst)
5085 intel_ddi_set_vc_payload_alloc(crtc, false);
5086
5087 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5088
5089 if (INTEL_INFO(dev)->gen == 9)
5090 skylake_scaler_disable(intel_crtc);
5091 else if (INTEL_INFO(dev)->gen < 9)
5092 ironlake_pfit_disable(intel_crtc);
5093 else
5094 MISSING_CASE(INTEL_INFO(dev)->gen);
5095
5096 intel_ddi_disable_pipe_clock(intel_crtc);
5097
5098 if (intel_crtc->config->has_pch_encoder) {
5099 lpt_disable_pch_transcoder(dev_priv);
5100 intel_ddi_fdi_disable(crtc);
5101 }
5102
5103 for_each_encoder_on_crtc(dev, crtc, encoder)
5104 if (encoder->post_disable)
5105 encoder->post_disable(encoder);
5106
5107 intel_crtc->active = false;
5108 intel_update_watermarks(crtc);
5109 }
5110
5111 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5112 {
5113 struct drm_device *dev = crtc->base.dev;
5114 struct drm_i915_private *dev_priv = dev->dev_private;
5115 struct intel_crtc_state *pipe_config = crtc->config;
5116
5117 if (!pipe_config->gmch_pfit.control)
5118 return;
5119
5120 /*
5121 * The panel fitter should only be adjusted whilst the pipe is disabled,
5122 * according to register description and PRM.
5123 */
5124 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5125 assert_pipe_disabled(dev_priv, crtc->pipe);
5126
5127 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5128 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5129
5130 /* Border color in case we don't scale up to the full screen. Black by
5131 * default, change to something else for debugging. */
5132 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5133 }
5134
5135 static enum intel_display_power_domain port_to_power_domain(enum port port)
5136 {
5137 switch (port) {
5138 case PORT_A:
5139 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5140 case PORT_B:
5141 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5142 case PORT_C:
5143 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5144 case PORT_D:
5145 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5146 default:
5147 WARN_ON_ONCE(1);
5148 return POWER_DOMAIN_PORT_OTHER;
5149 }
5150 }
5151
5152 #define for_each_power_domain(domain, mask) \
5153 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5154 if ((1 << (domain)) & (mask))
5155
5156 enum intel_display_power_domain
5157 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5158 {
5159 struct drm_device *dev = intel_encoder->base.dev;
5160 struct intel_digital_port *intel_dig_port;
5161
5162 switch (intel_encoder->type) {
5163 case INTEL_OUTPUT_UNKNOWN:
5164 /* Only DDI platforms should ever use this output type */
5165 WARN_ON_ONCE(!HAS_DDI(dev));
5166 case INTEL_OUTPUT_DISPLAYPORT:
5167 case INTEL_OUTPUT_HDMI:
5168 case INTEL_OUTPUT_EDP:
5169 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5170 return port_to_power_domain(intel_dig_port->port);
5171 case INTEL_OUTPUT_DP_MST:
5172 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5173 return port_to_power_domain(intel_dig_port->port);
5174 case INTEL_OUTPUT_ANALOG:
5175 return POWER_DOMAIN_PORT_CRT;
5176 case INTEL_OUTPUT_DSI:
5177 return POWER_DOMAIN_PORT_DSI;
5178 default:
5179 return POWER_DOMAIN_PORT_OTHER;
5180 }
5181 }
5182
5183 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5184 {
5185 struct drm_device *dev = crtc->dev;
5186 struct intel_encoder *intel_encoder;
5187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5188 enum pipe pipe = intel_crtc->pipe;
5189 unsigned long mask;
5190 enum transcoder transcoder;
5191
5192 if (!crtc->state->active)
5193 return 0;
5194
5195 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5196
5197 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5198 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5199 if (intel_crtc->config->pch_pfit.enabled ||
5200 intel_crtc->config->pch_pfit.force_thru)
5201 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5202
5203 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5204 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5205
5206 return mask;
5207 }
5208
5209 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5210 {
5211 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5213 enum intel_display_power_domain domain;
5214 unsigned long domains, new_domains, old_domains;
5215
5216 old_domains = intel_crtc->enabled_power_domains;
5217 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5218
5219 domains = new_domains & ~old_domains;
5220
5221 for_each_power_domain(domain, domains)
5222 intel_display_power_get(dev_priv, domain);
5223
5224 return old_domains & ~new_domains;
5225 }
5226
5227 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5228 unsigned long domains)
5229 {
5230 enum intel_display_power_domain domain;
5231
5232 for_each_power_domain(domain, domains)
5233 intel_display_power_put(dev_priv, domain);
5234 }
5235
5236 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5237 {
5238 struct drm_device *dev = state->dev;
5239 struct drm_i915_private *dev_priv = dev->dev_private;
5240 unsigned long put_domains[I915_MAX_PIPES] = {};
5241 struct drm_crtc_state *crtc_state;
5242 struct drm_crtc *crtc;
5243 int i;
5244
5245 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5246 if (needs_modeset(crtc->state))
5247 put_domains[to_intel_crtc(crtc)->pipe] =
5248 modeset_get_crtc_power_domains(crtc);
5249 }
5250
5251 if (dev_priv->display.modeset_commit_cdclk) {
5252 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5253
5254 if (cdclk != dev_priv->cdclk_freq &&
5255 !WARN_ON(!state->allow_modeset))
5256 dev_priv->display.modeset_commit_cdclk(state);
5257 }
5258
5259 for (i = 0; i < I915_MAX_PIPES; i++)
5260 if (put_domains[i])
5261 modeset_put_power_domains(dev_priv, put_domains[i]);
5262 }
5263
5264 static void intel_update_max_cdclk(struct drm_device *dev)
5265 {
5266 struct drm_i915_private *dev_priv = dev->dev_private;
5267
5268 if (IS_SKYLAKE(dev)) {
5269 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5270
5271 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5272 dev_priv->max_cdclk_freq = 675000;
5273 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5274 dev_priv->max_cdclk_freq = 540000;
5275 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5276 dev_priv->max_cdclk_freq = 450000;
5277 else
5278 dev_priv->max_cdclk_freq = 337500;
5279 } else if (IS_BROADWELL(dev)) {
5280 /*
5281 * FIXME with extra cooling we can allow
5282 * 540 MHz for ULX and 675 Mhz for ULT.
5283 * How can we know if extra cooling is
5284 * available? PCI ID, VTB, something else?
5285 */
5286 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5287 dev_priv->max_cdclk_freq = 450000;
5288 else if (IS_BDW_ULX(dev))
5289 dev_priv->max_cdclk_freq = 450000;
5290 else if (IS_BDW_ULT(dev))
5291 dev_priv->max_cdclk_freq = 540000;
5292 else
5293 dev_priv->max_cdclk_freq = 675000;
5294 } else if (IS_CHERRYVIEW(dev)) {
5295 dev_priv->max_cdclk_freq = 320000;
5296 } else if (IS_VALLEYVIEW(dev)) {
5297 dev_priv->max_cdclk_freq = 400000;
5298 } else {
5299 /* otherwise assume cdclk is fixed */
5300 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5301 }
5302
5303 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5304 dev_priv->max_cdclk_freq);
5305 }
5306
5307 static void intel_update_cdclk(struct drm_device *dev)
5308 {
5309 struct drm_i915_private *dev_priv = dev->dev_private;
5310
5311 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5312 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5313 dev_priv->cdclk_freq);
5314
5315 /*
5316 * Program the gmbus_freq based on the cdclk frequency.
5317 * BSpec erroneously claims we should aim for 4MHz, but
5318 * in fact 1MHz is the correct frequency.
5319 */
5320 if (IS_VALLEYVIEW(dev)) {
5321 /*
5322 * Program the gmbus_freq based on the cdclk frequency.
5323 * BSpec erroneously claims we should aim for 4MHz, but
5324 * in fact 1MHz is the correct frequency.
5325 */
5326 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5327 }
5328
5329 if (dev_priv->max_cdclk_freq == 0)
5330 intel_update_max_cdclk(dev);
5331 }
5332
5333 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5334 {
5335 struct drm_i915_private *dev_priv = dev->dev_private;
5336 uint32_t divider;
5337 uint32_t ratio;
5338 uint32_t current_freq;
5339 int ret;
5340
5341 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5342 switch (frequency) {
5343 case 144000:
5344 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5345 ratio = BXT_DE_PLL_RATIO(60);
5346 break;
5347 case 288000:
5348 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5349 ratio = BXT_DE_PLL_RATIO(60);
5350 break;
5351 case 384000:
5352 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5353 ratio = BXT_DE_PLL_RATIO(60);
5354 break;
5355 case 576000:
5356 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5357 ratio = BXT_DE_PLL_RATIO(60);
5358 break;
5359 case 624000:
5360 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5361 ratio = BXT_DE_PLL_RATIO(65);
5362 break;
5363 case 19200:
5364 /*
5365 * Bypass frequency with DE PLL disabled. Init ratio, divider
5366 * to suppress GCC warning.
5367 */
5368 ratio = 0;
5369 divider = 0;
5370 break;
5371 default:
5372 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5373
5374 return;
5375 }
5376
5377 mutex_lock(&dev_priv->rps.hw_lock);
5378 /* Inform power controller of upcoming frequency change */
5379 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5380 0x80000000);
5381 mutex_unlock(&dev_priv->rps.hw_lock);
5382
5383 if (ret) {
5384 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5385 ret, frequency);
5386 return;
5387 }
5388
5389 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5390 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5391 current_freq = current_freq * 500 + 1000;
5392
5393 /*
5394 * DE PLL has to be disabled when
5395 * - setting to 19.2MHz (bypass, PLL isn't used)
5396 * - before setting to 624MHz (PLL needs toggling)
5397 * - before setting to any frequency from 624MHz (PLL needs toggling)
5398 */
5399 if (frequency == 19200 || frequency == 624000 ||
5400 current_freq == 624000) {
5401 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5402 /* Timeout 200us */
5403 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5404 1))
5405 DRM_ERROR("timout waiting for DE PLL unlock\n");
5406 }
5407
5408 if (frequency != 19200) {
5409 uint32_t val;
5410
5411 val = I915_READ(BXT_DE_PLL_CTL);
5412 val &= ~BXT_DE_PLL_RATIO_MASK;
5413 val |= ratio;
5414 I915_WRITE(BXT_DE_PLL_CTL, val);
5415
5416 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5417 /* Timeout 200us */
5418 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5419 DRM_ERROR("timeout waiting for DE PLL lock\n");
5420
5421 val = I915_READ(CDCLK_CTL);
5422 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5423 val |= divider;
5424 /*
5425 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5426 * enable otherwise.
5427 */
5428 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5429 if (frequency >= 500000)
5430 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5431
5432 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5433 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5434 val |= (frequency - 1000) / 500;
5435 I915_WRITE(CDCLK_CTL, val);
5436 }
5437
5438 mutex_lock(&dev_priv->rps.hw_lock);
5439 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5440 DIV_ROUND_UP(frequency, 25000));
5441 mutex_unlock(&dev_priv->rps.hw_lock);
5442
5443 if (ret) {
5444 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5445 ret, frequency);
5446 return;
5447 }
5448
5449 intel_update_cdclk(dev);
5450 }
5451
5452 void broxton_init_cdclk(struct drm_device *dev)
5453 {
5454 struct drm_i915_private *dev_priv = dev->dev_private;
5455 uint32_t val;
5456
5457 /*
5458 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5459 * or else the reset will hang because there is no PCH to respond.
5460 * Move the handshake programming to initialization sequence.
5461 * Previously was left up to BIOS.
5462 */
5463 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5464 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5465 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5466
5467 /* Enable PG1 for cdclk */
5468 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5469
5470 /* check if cd clock is enabled */
5471 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5472 DRM_DEBUG_KMS("Display already initialized\n");
5473 return;
5474 }
5475
5476 /*
5477 * FIXME:
5478 * - The initial CDCLK needs to be read from VBT.
5479 * Need to make this change after VBT has changes for BXT.
5480 * - check if setting the max (or any) cdclk freq is really necessary
5481 * here, it belongs to modeset time
5482 */
5483 broxton_set_cdclk(dev, 624000);
5484
5485 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5486 POSTING_READ(DBUF_CTL);
5487
5488 udelay(10);
5489
5490 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5491 DRM_ERROR("DBuf power enable timeout!\n");
5492 }
5493
5494 void broxton_uninit_cdclk(struct drm_device *dev)
5495 {
5496 struct drm_i915_private *dev_priv = dev->dev_private;
5497
5498 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5499 POSTING_READ(DBUF_CTL);
5500
5501 udelay(10);
5502
5503 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5504 DRM_ERROR("DBuf power disable timeout!\n");
5505
5506 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5507 broxton_set_cdclk(dev, 19200);
5508
5509 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5510 }
5511
5512 static const struct skl_cdclk_entry {
5513 unsigned int freq;
5514 unsigned int vco;
5515 } skl_cdclk_frequencies[] = {
5516 { .freq = 308570, .vco = 8640 },
5517 { .freq = 337500, .vco = 8100 },
5518 { .freq = 432000, .vco = 8640 },
5519 { .freq = 450000, .vco = 8100 },
5520 { .freq = 540000, .vco = 8100 },
5521 { .freq = 617140, .vco = 8640 },
5522 { .freq = 675000, .vco = 8100 },
5523 };
5524
5525 static unsigned int skl_cdclk_decimal(unsigned int freq)
5526 {
5527 return (freq - 1000) / 500;
5528 }
5529
5530 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5531 {
5532 unsigned int i;
5533
5534 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5535 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5536
5537 if (e->freq == freq)
5538 return e->vco;
5539 }
5540
5541 return 8100;
5542 }
5543
5544 static void
5545 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5546 {
5547 unsigned int min_freq;
5548 u32 val;
5549
5550 /* select the minimum CDCLK before enabling DPLL 0 */
5551 val = I915_READ(CDCLK_CTL);
5552 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5553 val |= CDCLK_FREQ_337_308;
5554
5555 if (required_vco == 8640)
5556 min_freq = 308570;
5557 else
5558 min_freq = 337500;
5559
5560 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5561
5562 I915_WRITE(CDCLK_CTL, val);
5563 POSTING_READ(CDCLK_CTL);
5564
5565 /*
5566 * We always enable DPLL0 with the lowest link rate possible, but still
5567 * taking into account the VCO required to operate the eDP panel at the
5568 * desired frequency. The usual DP link rates operate with a VCO of
5569 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5570 * The modeset code is responsible for the selection of the exact link
5571 * rate later on, with the constraint of choosing a frequency that
5572 * works with required_vco.
5573 */
5574 val = I915_READ(DPLL_CTRL1);
5575
5576 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5577 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5578 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5579 if (required_vco == 8640)
5580 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5581 SKL_DPLL0);
5582 else
5583 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5584 SKL_DPLL0);
5585
5586 I915_WRITE(DPLL_CTRL1, val);
5587 POSTING_READ(DPLL_CTRL1);
5588
5589 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5590
5591 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5592 DRM_ERROR("DPLL0 not locked\n");
5593 }
5594
5595 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5596 {
5597 int ret;
5598 u32 val;
5599
5600 /* inform PCU we want to change CDCLK */
5601 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5602 mutex_lock(&dev_priv->rps.hw_lock);
5603 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5604 mutex_unlock(&dev_priv->rps.hw_lock);
5605
5606 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5607 }
5608
5609 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5610 {
5611 unsigned int i;
5612
5613 for (i = 0; i < 15; i++) {
5614 if (skl_cdclk_pcu_ready(dev_priv))
5615 return true;
5616 udelay(10);
5617 }
5618
5619 return false;
5620 }
5621
5622 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5623 {
5624 struct drm_device *dev = dev_priv->dev;
5625 u32 freq_select, pcu_ack;
5626
5627 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5628
5629 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5630 DRM_ERROR("failed to inform PCU about cdclk change\n");
5631 return;
5632 }
5633
5634 /* set CDCLK_CTL */
5635 switch(freq) {
5636 case 450000:
5637 case 432000:
5638 freq_select = CDCLK_FREQ_450_432;
5639 pcu_ack = 1;
5640 break;
5641 case 540000:
5642 freq_select = CDCLK_FREQ_540;
5643 pcu_ack = 2;
5644 break;
5645 case 308570:
5646 case 337500:
5647 default:
5648 freq_select = CDCLK_FREQ_337_308;
5649 pcu_ack = 0;
5650 break;
5651 case 617140:
5652 case 675000:
5653 freq_select = CDCLK_FREQ_675_617;
5654 pcu_ack = 3;
5655 break;
5656 }
5657
5658 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5659 POSTING_READ(CDCLK_CTL);
5660
5661 /* inform PCU of the change */
5662 mutex_lock(&dev_priv->rps.hw_lock);
5663 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5664 mutex_unlock(&dev_priv->rps.hw_lock);
5665
5666 intel_update_cdclk(dev);
5667 }
5668
5669 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5670 {
5671 /* disable DBUF power */
5672 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5673 POSTING_READ(DBUF_CTL);
5674
5675 udelay(10);
5676
5677 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5678 DRM_ERROR("DBuf power disable timeout\n");
5679
5680 /* disable DPLL0 */
5681 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5682 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5683 DRM_ERROR("Couldn't disable DPLL0\n");
5684
5685 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5686 }
5687
5688 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5689 {
5690 u32 val;
5691 unsigned int required_vco;
5692
5693 /* enable PCH reset handshake */
5694 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5695 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5696
5697 /* enable PG1 and Misc I/O */
5698 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5699
5700 /* DPLL0 already enabed !? */
5701 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5702 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5703 return;
5704 }
5705
5706 /* enable DPLL0 */
5707 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5708 skl_dpll0_enable(dev_priv, required_vco);
5709
5710 /* set CDCLK to the frequency the BIOS chose */
5711 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5712
5713 /* enable DBUF power */
5714 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5715 POSTING_READ(DBUF_CTL);
5716
5717 udelay(10);
5718
5719 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5720 DRM_ERROR("DBuf power enable timeout\n");
5721 }
5722
5723 /* returns HPLL frequency in kHz */
5724 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5725 {
5726 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5727
5728 /* Obtain SKU information */
5729 mutex_lock(&dev_priv->sb_lock);
5730 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5731 CCK_FUSE_HPLL_FREQ_MASK;
5732 mutex_unlock(&dev_priv->sb_lock);
5733
5734 return vco_freq[hpll_freq] * 1000;
5735 }
5736
5737 /* Adjust CDclk dividers to allow high res or save power if possible */
5738 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5739 {
5740 struct drm_i915_private *dev_priv = dev->dev_private;
5741 u32 val, cmd;
5742
5743 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5744 != dev_priv->cdclk_freq);
5745
5746 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5747 cmd = 2;
5748 else if (cdclk == 266667)
5749 cmd = 1;
5750 else
5751 cmd = 0;
5752
5753 mutex_lock(&dev_priv->rps.hw_lock);
5754 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5755 val &= ~DSPFREQGUAR_MASK;
5756 val |= (cmd << DSPFREQGUAR_SHIFT);
5757 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5758 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5759 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5760 50)) {
5761 DRM_ERROR("timed out waiting for CDclk change\n");
5762 }
5763 mutex_unlock(&dev_priv->rps.hw_lock);
5764
5765 mutex_lock(&dev_priv->sb_lock);
5766
5767 if (cdclk == 400000) {
5768 u32 divider;
5769
5770 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5771
5772 /* adjust cdclk divider */
5773 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5774 val &= ~DISPLAY_FREQUENCY_VALUES;
5775 val |= divider;
5776 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5777
5778 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5779 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5780 50))
5781 DRM_ERROR("timed out waiting for CDclk change\n");
5782 }
5783
5784 /* adjust self-refresh exit latency value */
5785 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5786 val &= ~0x7f;
5787
5788 /*
5789 * For high bandwidth configs, we set a higher latency in the bunit
5790 * so that the core display fetch happens in time to avoid underruns.
5791 */
5792 if (cdclk == 400000)
5793 val |= 4500 / 250; /* 4.5 usec */
5794 else
5795 val |= 3000 / 250; /* 3.0 usec */
5796 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5797
5798 mutex_unlock(&dev_priv->sb_lock);
5799
5800 intel_update_cdclk(dev);
5801 }
5802
5803 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5804 {
5805 struct drm_i915_private *dev_priv = dev->dev_private;
5806 u32 val, cmd;
5807
5808 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5809 != dev_priv->cdclk_freq);
5810
5811 switch (cdclk) {
5812 case 333333:
5813 case 320000:
5814 case 266667:
5815 case 200000:
5816 break;
5817 default:
5818 MISSING_CASE(cdclk);
5819 return;
5820 }
5821
5822 /*
5823 * Specs are full of misinformation, but testing on actual
5824 * hardware has shown that we just need to write the desired
5825 * CCK divider into the Punit register.
5826 */
5827 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5828
5829 mutex_lock(&dev_priv->rps.hw_lock);
5830 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5831 val &= ~DSPFREQGUAR_MASK_CHV;
5832 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5833 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5834 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5835 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5836 50)) {
5837 DRM_ERROR("timed out waiting for CDclk change\n");
5838 }
5839 mutex_unlock(&dev_priv->rps.hw_lock);
5840
5841 intel_update_cdclk(dev);
5842 }
5843
5844 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5845 int max_pixclk)
5846 {
5847 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5848 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5849
5850 /*
5851 * Really only a few cases to deal with, as only 4 CDclks are supported:
5852 * 200MHz
5853 * 267MHz
5854 * 320/333MHz (depends on HPLL freq)
5855 * 400MHz (VLV only)
5856 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5857 * of the lower bin and adjust if needed.
5858 *
5859 * We seem to get an unstable or solid color picture at 200MHz.
5860 * Not sure what's wrong. For now use 200MHz only when all pipes
5861 * are off.
5862 */
5863 if (!IS_CHERRYVIEW(dev_priv) &&
5864 max_pixclk > freq_320*limit/100)
5865 return 400000;
5866 else if (max_pixclk > 266667*limit/100)
5867 return freq_320;
5868 else if (max_pixclk > 0)
5869 return 266667;
5870 else
5871 return 200000;
5872 }
5873
5874 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5875 int max_pixclk)
5876 {
5877 /*
5878 * FIXME:
5879 * - remove the guardband, it's not needed on BXT
5880 * - set 19.2MHz bypass frequency if there are no active pipes
5881 */
5882 if (max_pixclk > 576000*9/10)
5883 return 624000;
5884 else if (max_pixclk > 384000*9/10)
5885 return 576000;
5886 else if (max_pixclk > 288000*9/10)
5887 return 384000;
5888 else if (max_pixclk > 144000*9/10)
5889 return 288000;
5890 else
5891 return 144000;
5892 }
5893
5894 /* Compute the max pixel clock for new configuration. Uses atomic state if
5895 * that's non-NULL, look at current state otherwise. */
5896 static int intel_mode_max_pixclk(struct drm_device *dev,
5897 struct drm_atomic_state *state)
5898 {
5899 struct intel_crtc *intel_crtc;
5900 struct intel_crtc_state *crtc_state;
5901 int max_pixclk = 0;
5902
5903 for_each_intel_crtc(dev, intel_crtc) {
5904 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5905 if (IS_ERR(crtc_state))
5906 return PTR_ERR(crtc_state);
5907
5908 if (!crtc_state->base.enable)
5909 continue;
5910
5911 max_pixclk = max(max_pixclk,
5912 crtc_state->base.adjusted_mode.crtc_clock);
5913 }
5914
5915 return max_pixclk;
5916 }
5917
5918 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5919 {
5920 struct drm_device *dev = state->dev;
5921 struct drm_i915_private *dev_priv = dev->dev_private;
5922 int max_pixclk = intel_mode_max_pixclk(dev, state);
5923
5924 if (max_pixclk < 0)
5925 return max_pixclk;
5926
5927 to_intel_atomic_state(state)->cdclk =
5928 valleyview_calc_cdclk(dev_priv, max_pixclk);
5929
5930 return 0;
5931 }
5932
5933 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5934 {
5935 struct drm_device *dev = state->dev;
5936 struct drm_i915_private *dev_priv = dev->dev_private;
5937 int max_pixclk = intel_mode_max_pixclk(dev, state);
5938
5939 if (max_pixclk < 0)
5940 return max_pixclk;
5941
5942 to_intel_atomic_state(state)->cdclk =
5943 broxton_calc_cdclk(dev_priv, max_pixclk);
5944
5945 return 0;
5946 }
5947
5948 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5949 {
5950 unsigned int credits, default_credits;
5951
5952 if (IS_CHERRYVIEW(dev_priv))
5953 default_credits = PFI_CREDIT(12);
5954 else
5955 default_credits = PFI_CREDIT(8);
5956
5957 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5958 /* CHV suggested value is 31 or 63 */
5959 if (IS_CHERRYVIEW(dev_priv))
5960 credits = PFI_CREDIT_63;
5961 else
5962 credits = PFI_CREDIT(15);
5963 } else {
5964 credits = default_credits;
5965 }
5966
5967 /*
5968 * WA - write default credits before re-programming
5969 * FIXME: should we also set the resend bit here?
5970 */
5971 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5972 default_credits);
5973
5974 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5975 credits | PFI_CREDIT_RESEND);
5976
5977 /*
5978 * FIXME is this guaranteed to clear
5979 * immediately or should we poll for it?
5980 */
5981 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5982 }
5983
5984 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
5985 {
5986 struct drm_device *dev = old_state->dev;
5987 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
5988 struct drm_i915_private *dev_priv = dev->dev_private;
5989
5990 /*
5991 * FIXME: We can end up here with all power domains off, yet
5992 * with a CDCLK frequency other than the minimum. To account
5993 * for this take the PIPE-A power domain, which covers the HW
5994 * blocks needed for the following programming. This can be
5995 * removed once it's guaranteed that we get here either with
5996 * the minimum CDCLK set, or the required power domains
5997 * enabled.
5998 */
5999 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6000
6001 if (IS_CHERRYVIEW(dev))
6002 cherryview_set_cdclk(dev, req_cdclk);
6003 else
6004 valleyview_set_cdclk(dev, req_cdclk);
6005
6006 vlv_program_pfi_credits(dev_priv);
6007
6008 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6009 }
6010
6011 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6012 {
6013 struct drm_device *dev = crtc->dev;
6014 struct drm_i915_private *dev_priv = to_i915(dev);
6015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6016 struct intel_encoder *encoder;
6017 int pipe = intel_crtc->pipe;
6018 bool is_dsi;
6019
6020 if (WARN_ON(intel_crtc->active))
6021 return;
6022
6023 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6024
6025 if (!is_dsi) {
6026 if (IS_CHERRYVIEW(dev))
6027 chv_prepare_pll(intel_crtc, intel_crtc->config);
6028 else
6029 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6030 }
6031
6032 if (intel_crtc->config->has_dp_encoder)
6033 intel_dp_set_m_n(intel_crtc, M1_N1);
6034
6035 intel_set_pipe_timings(intel_crtc);
6036
6037 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6038 struct drm_i915_private *dev_priv = dev->dev_private;
6039
6040 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6041 I915_WRITE(CHV_CANVAS(pipe), 0);
6042 }
6043
6044 i9xx_set_pipeconf(intel_crtc);
6045
6046 intel_crtc->active = true;
6047
6048 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6049
6050 for_each_encoder_on_crtc(dev, crtc, encoder)
6051 if (encoder->pre_pll_enable)
6052 encoder->pre_pll_enable(encoder);
6053
6054 if (!is_dsi) {
6055 if (IS_CHERRYVIEW(dev))
6056 chv_enable_pll(intel_crtc, intel_crtc->config);
6057 else
6058 vlv_enable_pll(intel_crtc, intel_crtc->config);
6059 }
6060
6061 for_each_encoder_on_crtc(dev, crtc, encoder)
6062 if (encoder->pre_enable)
6063 encoder->pre_enable(encoder);
6064
6065 i9xx_pfit_enable(intel_crtc);
6066
6067 intel_crtc_load_lut(crtc);
6068
6069 intel_enable_pipe(intel_crtc);
6070
6071 assert_vblank_disabled(crtc);
6072 drm_crtc_vblank_on(crtc);
6073
6074 for_each_encoder_on_crtc(dev, crtc, encoder)
6075 encoder->enable(encoder);
6076 }
6077
6078 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6079 {
6080 struct drm_device *dev = crtc->base.dev;
6081 struct drm_i915_private *dev_priv = dev->dev_private;
6082
6083 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6084 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6085 }
6086
6087 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6088 {
6089 struct drm_device *dev = crtc->dev;
6090 struct drm_i915_private *dev_priv = to_i915(dev);
6091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6092 struct intel_encoder *encoder;
6093 int pipe = intel_crtc->pipe;
6094
6095 if (WARN_ON(intel_crtc->active))
6096 return;
6097
6098 i9xx_set_pll_dividers(intel_crtc);
6099
6100 if (intel_crtc->config->has_dp_encoder)
6101 intel_dp_set_m_n(intel_crtc, M1_N1);
6102
6103 intel_set_pipe_timings(intel_crtc);
6104
6105 i9xx_set_pipeconf(intel_crtc);
6106
6107 intel_crtc->active = true;
6108
6109 if (!IS_GEN2(dev))
6110 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6111
6112 for_each_encoder_on_crtc(dev, crtc, encoder)
6113 if (encoder->pre_enable)
6114 encoder->pre_enable(encoder);
6115
6116 i9xx_enable_pll(intel_crtc);
6117
6118 i9xx_pfit_enable(intel_crtc);
6119
6120 intel_crtc_load_lut(crtc);
6121
6122 intel_update_watermarks(crtc);
6123 intel_enable_pipe(intel_crtc);
6124
6125 assert_vblank_disabled(crtc);
6126 drm_crtc_vblank_on(crtc);
6127
6128 for_each_encoder_on_crtc(dev, crtc, encoder)
6129 encoder->enable(encoder);
6130 }
6131
6132 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6133 {
6134 struct drm_device *dev = crtc->base.dev;
6135 struct drm_i915_private *dev_priv = dev->dev_private;
6136
6137 if (!crtc->config->gmch_pfit.control)
6138 return;
6139
6140 assert_pipe_disabled(dev_priv, crtc->pipe);
6141
6142 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6143 I915_READ(PFIT_CONTROL));
6144 I915_WRITE(PFIT_CONTROL, 0);
6145 }
6146
6147 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6148 {
6149 struct drm_device *dev = crtc->dev;
6150 struct drm_i915_private *dev_priv = dev->dev_private;
6151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6152 struct intel_encoder *encoder;
6153 int pipe = intel_crtc->pipe;
6154
6155 /*
6156 * On gen2 planes are double buffered but the pipe isn't, so we must
6157 * wait for planes to fully turn off before disabling the pipe.
6158 * We also need to wait on all gmch platforms because of the
6159 * self-refresh mode constraint explained above.
6160 */
6161 intel_wait_for_vblank(dev, pipe);
6162
6163 for_each_encoder_on_crtc(dev, crtc, encoder)
6164 encoder->disable(encoder);
6165
6166 drm_crtc_vblank_off(crtc);
6167 assert_vblank_disabled(crtc);
6168
6169 intel_disable_pipe(intel_crtc);
6170
6171 i9xx_pfit_disable(intel_crtc);
6172
6173 for_each_encoder_on_crtc(dev, crtc, encoder)
6174 if (encoder->post_disable)
6175 encoder->post_disable(encoder);
6176
6177 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6178 if (IS_CHERRYVIEW(dev))
6179 chv_disable_pll(dev_priv, pipe);
6180 else if (IS_VALLEYVIEW(dev))
6181 vlv_disable_pll(dev_priv, pipe);
6182 else
6183 i9xx_disable_pll(intel_crtc);
6184 }
6185
6186 if (!IS_GEN2(dev))
6187 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6188
6189 intel_crtc->active = false;
6190 intel_update_watermarks(crtc);
6191 }
6192
6193 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6194 {
6195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6196 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6197 enum intel_display_power_domain domain;
6198 unsigned long domains;
6199
6200 if (!intel_crtc->active)
6201 return;
6202
6203 if (to_intel_plane_state(crtc->primary->state)->visible) {
6204 intel_crtc_wait_for_pending_flips(crtc);
6205 intel_pre_disable_primary(crtc);
6206 }
6207
6208 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6209 dev_priv->display.crtc_disable(crtc);
6210 intel_disable_shared_dpll(intel_crtc);
6211
6212 domains = intel_crtc->enabled_power_domains;
6213 for_each_power_domain(domain, domains)
6214 intel_display_power_put(dev_priv, domain);
6215 intel_crtc->enabled_power_domains = 0;
6216 }
6217
6218 /*
6219 * turn all crtc's off, but do not adjust state
6220 * This has to be paired with a call to intel_modeset_setup_hw_state.
6221 */
6222 int intel_display_suspend(struct drm_device *dev)
6223 {
6224 struct drm_mode_config *config = &dev->mode_config;
6225 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6226 struct drm_atomic_state *state;
6227 struct drm_crtc *crtc;
6228 unsigned crtc_mask = 0;
6229 int ret = 0;
6230
6231 if (WARN_ON(!ctx))
6232 return 0;
6233
6234 lockdep_assert_held(&ctx->ww_ctx);
6235 state = drm_atomic_state_alloc(dev);
6236 if (WARN_ON(!state))
6237 return -ENOMEM;
6238
6239 state->acquire_ctx = ctx;
6240 state->allow_modeset = true;
6241
6242 for_each_crtc(dev, crtc) {
6243 struct drm_crtc_state *crtc_state =
6244 drm_atomic_get_crtc_state(state, crtc);
6245
6246 ret = PTR_ERR_OR_ZERO(crtc_state);
6247 if (ret)
6248 goto free;
6249
6250 if (!crtc_state->active)
6251 continue;
6252
6253 crtc_state->active = false;
6254 crtc_mask |= 1 << drm_crtc_index(crtc);
6255 }
6256
6257 if (crtc_mask) {
6258 ret = drm_atomic_commit(state);
6259
6260 if (!ret) {
6261 for_each_crtc(dev, crtc)
6262 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6263 crtc->state->active = true;
6264
6265 return ret;
6266 }
6267 }
6268
6269 free:
6270 if (ret)
6271 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6272 drm_atomic_state_free(state);
6273 return ret;
6274 }
6275
6276 void intel_encoder_destroy(struct drm_encoder *encoder)
6277 {
6278 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6279
6280 drm_encoder_cleanup(encoder);
6281 kfree(intel_encoder);
6282 }
6283
6284 /* Cross check the actual hw state with our own modeset state tracking (and it's
6285 * internal consistency). */
6286 static void intel_connector_check_state(struct intel_connector *connector)
6287 {
6288 struct drm_crtc *crtc = connector->base.state->crtc;
6289
6290 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6291 connector->base.base.id,
6292 connector->base.name);
6293
6294 if (connector->get_hw_state(connector)) {
6295 struct drm_encoder *encoder = &connector->encoder->base;
6296 struct drm_connector_state *conn_state = connector->base.state;
6297
6298 I915_STATE_WARN(!crtc,
6299 "connector enabled without attached crtc\n");
6300
6301 if (!crtc)
6302 return;
6303
6304 I915_STATE_WARN(!crtc->state->active,
6305 "connector is active, but attached crtc isn't\n");
6306
6307 if (!encoder)
6308 return;
6309
6310 I915_STATE_WARN(conn_state->best_encoder != encoder,
6311 "atomic encoder doesn't match attached encoder\n");
6312
6313 I915_STATE_WARN(conn_state->crtc != encoder->crtc,
6314 "attached encoder crtc differs from connector crtc\n");
6315 } else {
6316 I915_STATE_WARN(crtc && crtc->state->active,
6317 "attached crtc is active, but connector isn't\n");
6318 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6319 "best encoder set without crtc!\n");
6320 }
6321 }
6322
6323 int intel_connector_init(struct intel_connector *connector)
6324 {
6325 struct drm_connector_state *connector_state;
6326
6327 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6328 if (!connector_state)
6329 return -ENOMEM;
6330
6331 connector->base.state = connector_state;
6332 return 0;
6333 }
6334
6335 struct intel_connector *intel_connector_alloc(void)
6336 {
6337 struct intel_connector *connector;
6338
6339 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6340 if (!connector)
6341 return NULL;
6342
6343 if (intel_connector_init(connector) < 0) {
6344 kfree(connector);
6345 return NULL;
6346 }
6347
6348 return connector;
6349 }
6350
6351 /* Simple connector->get_hw_state implementation for encoders that support only
6352 * one connector and no cloning and hence the encoder state determines the state
6353 * of the connector. */
6354 bool intel_connector_get_hw_state(struct intel_connector *connector)
6355 {
6356 enum pipe pipe = 0;
6357 struct intel_encoder *encoder = connector->encoder;
6358
6359 return encoder->get_hw_state(encoder, &pipe);
6360 }
6361
6362 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6363 {
6364 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6365 return crtc_state->fdi_lanes;
6366
6367 return 0;
6368 }
6369
6370 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6371 struct intel_crtc_state *pipe_config)
6372 {
6373 struct drm_atomic_state *state = pipe_config->base.state;
6374 struct intel_crtc *other_crtc;
6375 struct intel_crtc_state *other_crtc_state;
6376
6377 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6378 pipe_name(pipe), pipe_config->fdi_lanes);
6379 if (pipe_config->fdi_lanes > 4) {
6380 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6381 pipe_name(pipe), pipe_config->fdi_lanes);
6382 return -EINVAL;
6383 }
6384
6385 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6386 if (pipe_config->fdi_lanes > 2) {
6387 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6388 pipe_config->fdi_lanes);
6389 return -EINVAL;
6390 } else {
6391 return 0;
6392 }
6393 }
6394
6395 if (INTEL_INFO(dev)->num_pipes == 2)
6396 return 0;
6397
6398 /* Ivybridge 3 pipe is really complicated */
6399 switch (pipe) {
6400 case PIPE_A:
6401 return 0;
6402 case PIPE_B:
6403 if (pipe_config->fdi_lanes <= 2)
6404 return 0;
6405
6406 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6407 other_crtc_state =
6408 intel_atomic_get_crtc_state(state, other_crtc);
6409 if (IS_ERR(other_crtc_state))
6410 return PTR_ERR(other_crtc_state);
6411
6412 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6413 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6414 pipe_name(pipe), pipe_config->fdi_lanes);
6415 return -EINVAL;
6416 }
6417 return 0;
6418 case PIPE_C:
6419 if (pipe_config->fdi_lanes > 2) {
6420 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6421 pipe_name(pipe), pipe_config->fdi_lanes);
6422 return -EINVAL;
6423 }
6424
6425 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6426 other_crtc_state =
6427 intel_atomic_get_crtc_state(state, other_crtc);
6428 if (IS_ERR(other_crtc_state))
6429 return PTR_ERR(other_crtc_state);
6430
6431 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6432 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6433 return -EINVAL;
6434 }
6435 return 0;
6436 default:
6437 BUG();
6438 }
6439 }
6440
6441 #define RETRY 1
6442 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6443 struct intel_crtc_state *pipe_config)
6444 {
6445 struct drm_device *dev = intel_crtc->base.dev;
6446 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6447 int lane, link_bw, fdi_dotclock, ret;
6448 bool needs_recompute = false;
6449
6450 retry:
6451 /* FDI is a binary signal running at ~2.7GHz, encoding
6452 * each output octet as 10 bits. The actual frequency
6453 * is stored as a divider into a 100MHz clock, and the
6454 * mode pixel clock is stored in units of 1KHz.
6455 * Hence the bw of each lane in terms of the mode signal
6456 * is:
6457 */
6458 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6459
6460 fdi_dotclock = adjusted_mode->crtc_clock;
6461
6462 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6463 pipe_config->pipe_bpp);
6464
6465 pipe_config->fdi_lanes = lane;
6466
6467 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6468 link_bw, &pipe_config->fdi_m_n);
6469
6470 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6471 intel_crtc->pipe, pipe_config);
6472 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6473 pipe_config->pipe_bpp -= 2*3;
6474 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6475 pipe_config->pipe_bpp);
6476 needs_recompute = true;
6477 pipe_config->bw_constrained = true;
6478
6479 goto retry;
6480 }
6481
6482 if (needs_recompute)
6483 return RETRY;
6484
6485 return ret;
6486 }
6487
6488 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6489 struct intel_crtc_state *pipe_config)
6490 {
6491 if (pipe_config->pipe_bpp > 24)
6492 return false;
6493
6494 /* HSW can handle pixel rate up to cdclk? */
6495 if (IS_HASWELL(dev_priv->dev))
6496 return true;
6497
6498 /*
6499 * We compare against max which means we must take
6500 * the increased cdclk requirement into account when
6501 * calculating the new cdclk.
6502 *
6503 * Should measure whether using a lower cdclk w/o IPS
6504 */
6505 return ilk_pipe_pixel_rate(pipe_config) <=
6506 dev_priv->max_cdclk_freq * 95 / 100;
6507 }
6508
6509 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6510 struct intel_crtc_state *pipe_config)
6511 {
6512 struct drm_device *dev = crtc->base.dev;
6513 struct drm_i915_private *dev_priv = dev->dev_private;
6514
6515 pipe_config->ips_enabled = i915.enable_ips &&
6516 hsw_crtc_supports_ips(crtc) &&
6517 pipe_config_supports_ips(dev_priv, pipe_config);
6518 }
6519
6520 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6521 struct intel_crtc_state *pipe_config)
6522 {
6523 struct drm_device *dev = crtc->base.dev;
6524 struct drm_i915_private *dev_priv = dev->dev_private;
6525 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6526
6527 /* FIXME should check pixel clock limits on all platforms */
6528 if (INTEL_INFO(dev)->gen < 4) {
6529 int clock_limit = dev_priv->max_cdclk_freq;
6530
6531 /*
6532 * Enable pixel doubling when the dot clock
6533 * is > 90% of the (display) core speed.
6534 *
6535 * GDG double wide on either pipe,
6536 * otherwise pipe A only.
6537 */
6538 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6539 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6540 clock_limit *= 2;
6541 pipe_config->double_wide = true;
6542 }
6543
6544 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6545 return -EINVAL;
6546 }
6547
6548 /*
6549 * Pipe horizontal size must be even in:
6550 * - DVO ganged mode
6551 * - LVDS dual channel mode
6552 * - Double wide pipe
6553 */
6554 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6555 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6556 pipe_config->pipe_src_w &= ~1;
6557
6558 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6559 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6560 */
6561 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6562 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6563 return -EINVAL;
6564
6565 if (HAS_IPS(dev))
6566 hsw_compute_ips_config(crtc, pipe_config);
6567
6568 if (pipe_config->has_pch_encoder)
6569 return ironlake_fdi_compute_config(crtc, pipe_config);
6570
6571 return 0;
6572 }
6573
6574 static int skylake_get_display_clock_speed(struct drm_device *dev)
6575 {
6576 struct drm_i915_private *dev_priv = to_i915(dev);
6577 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6578 uint32_t cdctl = I915_READ(CDCLK_CTL);
6579 uint32_t linkrate;
6580
6581 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6582 return 24000; /* 24MHz is the cd freq with NSSC ref */
6583
6584 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6585 return 540000;
6586
6587 linkrate = (I915_READ(DPLL_CTRL1) &
6588 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6589
6590 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6591 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6592 /* vco 8640 */
6593 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6594 case CDCLK_FREQ_450_432:
6595 return 432000;
6596 case CDCLK_FREQ_337_308:
6597 return 308570;
6598 case CDCLK_FREQ_675_617:
6599 return 617140;
6600 default:
6601 WARN(1, "Unknown cd freq selection\n");
6602 }
6603 } else {
6604 /* vco 8100 */
6605 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6606 case CDCLK_FREQ_450_432:
6607 return 450000;
6608 case CDCLK_FREQ_337_308:
6609 return 337500;
6610 case CDCLK_FREQ_675_617:
6611 return 675000;
6612 default:
6613 WARN(1, "Unknown cd freq selection\n");
6614 }
6615 }
6616
6617 /* error case, do as if DPLL0 isn't enabled */
6618 return 24000;
6619 }
6620
6621 static int broxton_get_display_clock_speed(struct drm_device *dev)
6622 {
6623 struct drm_i915_private *dev_priv = to_i915(dev);
6624 uint32_t cdctl = I915_READ(CDCLK_CTL);
6625 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6626 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6627 int cdclk;
6628
6629 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6630 return 19200;
6631
6632 cdclk = 19200 * pll_ratio / 2;
6633
6634 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6635 case BXT_CDCLK_CD2X_DIV_SEL_1:
6636 return cdclk; /* 576MHz or 624MHz */
6637 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6638 return cdclk * 2 / 3; /* 384MHz */
6639 case BXT_CDCLK_CD2X_DIV_SEL_2:
6640 return cdclk / 2; /* 288MHz */
6641 case BXT_CDCLK_CD2X_DIV_SEL_4:
6642 return cdclk / 4; /* 144MHz */
6643 }
6644
6645 /* error case, do as if DE PLL isn't enabled */
6646 return 19200;
6647 }
6648
6649 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6650 {
6651 struct drm_i915_private *dev_priv = dev->dev_private;
6652 uint32_t lcpll = I915_READ(LCPLL_CTL);
6653 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6654
6655 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6656 return 800000;
6657 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6658 return 450000;
6659 else if (freq == LCPLL_CLK_FREQ_450)
6660 return 450000;
6661 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6662 return 540000;
6663 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6664 return 337500;
6665 else
6666 return 675000;
6667 }
6668
6669 static int haswell_get_display_clock_speed(struct drm_device *dev)
6670 {
6671 struct drm_i915_private *dev_priv = dev->dev_private;
6672 uint32_t lcpll = I915_READ(LCPLL_CTL);
6673 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6674
6675 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6676 return 800000;
6677 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6678 return 450000;
6679 else if (freq == LCPLL_CLK_FREQ_450)
6680 return 450000;
6681 else if (IS_HSW_ULT(dev))
6682 return 337500;
6683 else
6684 return 540000;
6685 }
6686
6687 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6688 {
6689 struct drm_i915_private *dev_priv = dev->dev_private;
6690 u32 val;
6691 int divider;
6692
6693 if (dev_priv->hpll_freq == 0)
6694 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6695
6696 mutex_lock(&dev_priv->sb_lock);
6697 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6698 mutex_unlock(&dev_priv->sb_lock);
6699
6700 divider = val & DISPLAY_FREQUENCY_VALUES;
6701
6702 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6703 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6704 "cdclk change in progress\n");
6705
6706 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6707 }
6708
6709 static int ilk_get_display_clock_speed(struct drm_device *dev)
6710 {
6711 return 450000;
6712 }
6713
6714 static int i945_get_display_clock_speed(struct drm_device *dev)
6715 {
6716 return 400000;
6717 }
6718
6719 static int i915_get_display_clock_speed(struct drm_device *dev)
6720 {
6721 return 333333;
6722 }
6723
6724 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6725 {
6726 return 200000;
6727 }
6728
6729 static int pnv_get_display_clock_speed(struct drm_device *dev)
6730 {
6731 u16 gcfgc = 0;
6732
6733 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6734
6735 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6736 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6737 return 266667;
6738 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6739 return 333333;
6740 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6741 return 444444;
6742 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6743 return 200000;
6744 default:
6745 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6746 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6747 return 133333;
6748 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6749 return 166667;
6750 }
6751 }
6752
6753 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6754 {
6755 u16 gcfgc = 0;
6756
6757 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6758
6759 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6760 return 133333;
6761 else {
6762 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6763 case GC_DISPLAY_CLOCK_333_MHZ:
6764 return 333333;
6765 default:
6766 case GC_DISPLAY_CLOCK_190_200_MHZ:
6767 return 190000;
6768 }
6769 }
6770 }
6771
6772 static int i865_get_display_clock_speed(struct drm_device *dev)
6773 {
6774 return 266667;
6775 }
6776
6777 static int i85x_get_display_clock_speed(struct drm_device *dev)
6778 {
6779 u16 hpllcc = 0;
6780
6781 /*
6782 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6783 * encoding is different :(
6784 * FIXME is this the right way to detect 852GM/852GMV?
6785 */
6786 if (dev->pdev->revision == 0x1)
6787 return 133333;
6788
6789 pci_bus_read_config_word(dev->pdev->bus,
6790 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6791
6792 /* Assume that the hardware is in the high speed state. This
6793 * should be the default.
6794 */
6795 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6796 case GC_CLOCK_133_200:
6797 case GC_CLOCK_133_200_2:
6798 case GC_CLOCK_100_200:
6799 return 200000;
6800 case GC_CLOCK_166_250:
6801 return 250000;
6802 case GC_CLOCK_100_133:
6803 return 133333;
6804 case GC_CLOCK_133_266:
6805 case GC_CLOCK_133_266_2:
6806 case GC_CLOCK_166_266:
6807 return 266667;
6808 }
6809
6810 /* Shouldn't happen */
6811 return 0;
6812 }
6813
6814 static int i830_get_display_clock_speed(struct drm_device *dev)
6815 {
6816 return 133333;
6817 }
6818
6819 static unsigned int intel_hpll_vco(struct drm_device *dev)
6820 {
6821 struct drm_i915_private *dev_priv = dev->dev_private;
6822 static const unsigned int blb_vco[8] = {
6823 [0] = 3200000,
6824 [1] = 4000000,
6825 [2] = 5333333,
6826 [3] = 4800000,
6827 [4] = 6400000,
6828 };
6829 static const unsigned int pnv_vco[8] = {
6830 [0] = 3200000,
6831 [1] = 4000000,
6832 [2] = 5333333,
6833 [3] = 4800000,
6834 [4] = 2666667,
6835 };
6836 static const unsigned int cl_vco[8] = {
6837 [0] = 3200000,
6838 [1] = 4000000,
6839 [2] = 5333333,
6840 [3] = 6400000,
6841 [4] = 3333333,
6842 [5] = 3566667,
6843 [6] = 4266667,
6844 };
6845 static const unsigned int elk_vco[8] = {
6846 [0] = 3200000,
6847 [1] = 4000000,
6848 [2] = 5333333,
6849 [3] = 4800000,
6850 };
6851 static const unsigned int ctg_vco[8] = {
6852 [0] = 3200000,
6853 [1] = 4000000,
6854 [2] = 5333333,
6855 [3] = 6400000,
6856 [4] = 2666667,
6857 [5] = 4266667,
6858 };
6859 const unsigned int *vco_table;
6860 unsigned int vco;
6861 uint8_t tmp = 0;
6862
6863 /* FIXME other chipsets? */
6864 if (IS_GM45(dev))
6865 vco_table = ctg_vco;
6866 else if (IS_G4X(dev))
6867 vco_table = elk_vco;
6868 else if (IS_CRESTLINE(dev))
6869 vco_table = cl_vco;
6870 else if (IS_PINEVIEW(dev))
6871 vco_table = pnv_vco;
6872 else if (IS_G33(dev))
6873 vco_table = blb_vco;
6874 else
6875 return 0;
6876
6877 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6878
6879 vco = vco_table[tmp & 0x7];
6880 if (vco == 0)
6881 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6882 else
6883 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6884
6885 return vco;
6886 }
6887
6888 static int gm45_get_display_clock_speed(struct drm_device *dev)
6889 {
6890 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6891 uint16_t tmp = 0;
6892
6893 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6894
6895 cdclk_sel = (tmp >> 12) & 0x1;
6896
6897 switch (vco) {
6898 case 2666667:
6899 case 4000000:
6900 case 5333333:
6901 return cdclk_sel ? 333333 : 222222;
6902 case 3200000:
6903 return cdclk_sel ? 320000 : 228571;
6904 default:
6905 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6906 return 222222;
6907 }
6908 }
6909
6910 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6911 {
6912 static const uint8_t div_3200[] = { 16, 10, 8 };
6913 static const uint8_t div_4000[] = { 20, 12, 10 };
6914 static const uint8_t div_5333[] = { 24, 16, 14 };
6915 const uint8_t *div_table;
6916 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6917 uint16_t tmp = 0;
6918
6919 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6920
6921 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6922
6923 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6924 goto fail;
6925
6926 switch (vco) {
6927 case 3200000:
6928 div_table = div_3200;
6929 break;
6930 case 4000000:
6931 div_table = div_4000;
6932 break;
6933 case 5333333:
6934 div_table = div_5333;
6935 break;
6936 default:
6937 goto fail;
6938 }
6939
6940 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6941
6942 fail:
6943 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6944 return 200000;
6945 }
6946
6947 static int g33_get_display_clock_speed(struct drm_device *dev)
6948 {
6949 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6950 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6951 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6952 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6953 const uint8_t *div_table;
6954 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6955 uint16_t tmp = 0;
6956
6957 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6958
6959 cdclk_sel = (tmp >> 4) & 0x7;
6960
6961 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6962 goto fail;
6963
6964 switch (vco) {
6965 case 3200000:
6966 div_table = div_3200;
6967 break;
6968 case 4000000:
6969 div_table = div_4000;
6970 break;
6971 case 4800000:
6972 div_table = div_4800;
6973 break;
6974 case 5333333:
6975 div_table = div_5333;
6976 break;
6977 default:
6978 goto fail;
6979 }
6980
6981 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6982
6983 fail:
6984 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6985 return 190476;
6986 }
6987
6988 static void
6989 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6990 {
6991 while (*num > DATA_LINK_M_N_MASK ||
6992 *den > DATA_LINK_M_N_MASK) {
6993 *num >>= 1;
6994 *den >>= 1;
6995 }
6996 }
6997
6998 static void compute_m_n(unsigned int m, unsigned int n,
6999 uint32_t *ret_m, uint32_t *ret_n)
7000 {
7001 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7002 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7003 intel_reduce_m_n_ratio(ret_m, ret_n);
7004 }
7005
7006 void
7007 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7008 int pixel_clock, int link_clock,
7009 struct intel_link_m_n *m_n)
7010 {
7011 m_n->tu = 64;
7012
7013 compute_m_n(bits_per_pixel * pixel_clock,
7014 link_clock * nlanes * 8,
7015 &m_n->gmch_m, &m_n->gmch_n);
7016
7017 compute_m_n(pixel_clock, link_clock,
7018 &m_n->link_m, &m_n->link_n);
7019 }
7020
7021 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7022 {
7023 if (i915.panel_use_ssc >= 0)
7024 return i915.panel_use_ssc != 0;
7025 return dev_priv->vbt.lvds_use_ssc
7026 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7027 }
7028
7029 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7030 int num_connectors)
7031 {
7032 struct drm_device *dev = crtc_state->base.crtc->dev;
7033 struct drm_i915_private *dev_priv = dev->dev_private;
7034 int refclk;
7035
7036 WARN_ON(!crtc_state->base.state);
7037
7038 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7039 refclk = 100000;
7040 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7041 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7042 refclk = dev_priv->vbt.lvds_ssc_freq;
7043 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7044 } else if (!IS_GEN2(dev)) {
7045 refclk = 96000;
7046 } else {
7047 refclk = 48000;
7048 }
7049
7050 return refclk;
7051 }
7052
7053 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7054 {
7055 return (1 << dpll->n) << 16 | dpll->m2;
7056 }
7057
7058 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7059 {
7060 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7061 }
7062
7063 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7064 struct intel_crtc_state *crtc_state,
7065 intel_clock_t *reduced_clock)
7066 {
7067 struct drm_device *dev = crtc->base.dev;
7068 u32 fp, fp2 = 0;
7069
7070 if (IS_PINEVIEW(dev)) {
7071 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7072 if (reduced_clock)
7073 fp2 = pnv_dpll_compute_fp(reduced_clock);
7074 } else {
7075 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7076 if (reduced_clock)
7077 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7078 }
7079
7080 crtc_state->dpll_hw_state.fp0 = fp;
7081
7082 crtc->lowfreq_avail = false;
7083 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7084 reduced_clock) {
7085 crtc_state->dpll_hw_state.fp1 = fp2;
7086 crtc->lowfreq_avail = true;
7087 } else {
7088 crtc_state->dpll_hw_state.fp1 = fp;
7089 }
7090 }
7091
7092 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7093 pipe)
7094 {
7095 u32 reg_val;
7096
7097 /*
7098 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7099 * and set it to a reasonable value instead.
7100 */
7101 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7102 reg_val &= 0xffffff00;
7103 reg_val |= 0x00000030;
7104 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7105
7106 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7107 reg_val &= 0x8cffffff;
7108 reg_val = 0x8c000000;
7109 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7110
7111 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7112 reg_val &= 0xffffff00;
7113 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7114
7115 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7116 reg_val &= 0x00ffffff;
7117 reg_val |= 0xb0000000;
7118 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7119 }
7120
7121 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7122 struct intel_link_m_n *m_n)
7123 {
7124 struct drm_device *dev = crtc->base.dev;
7125 struct drm_i915_private *dev_priv = dev->dev_private;
7126 int pipe = crtc->pipe;
7127
7128 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7129 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7130 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7131 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7132 }
7133
7134 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7135 struct intel_link_m_n *m_n,
7136 struct intel_link_m_n *m2_n2)
7137 {
7138 struct drm_device *dev = crtc->base.dev;
7139 struct drm_i915_private *dev_priv = dev->dev_private;
7140 int pipe = crtc->pipe;
7141 enum transcoder transcoder = crtc->config->cpu_transcoder;
7142
7143 if (INTEL_INFO(dev)->gen >= 5) {
7144 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7145 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7146 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7147 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7148 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7149 * for gen < 8) and if DRRS is supported (to make sure the
7150 * registers are not unnecessarily accessed).
7151 */
7152 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7153 crtc->config->has_drrs) {
7154 I915_WRITE(PIPE_DATA_M2(transcoder),
7155 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7156 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7157 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7158 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7159 }
7160 } else {
7161 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7162 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7163 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7164 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7165 }
7166 }
7167
7168 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7169 {
7170 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7171
7172 if (m_n == M1_N1) {
7173 dp_m_n = &crtc->config->dp_m_n;
7174 dp_m2_n2 = &crtc->config->dp_m2_n2;
7175 } else if (m_n == M2_N2) {
7176
7177 /*
7178 * M2_N2 registers are not supported. Hence m2_n2 divider value
7179 * needs to be programmed into M1_N1.
7180 */
7181 dp_m_n = &crtc->config->dp_m2_n2;
7182 } else {
7183 DRM_ERROR("Unsupported divider value\n");
7184 return;
7185 }
7186
7187 if (crtc->config->has_pch_encoder)
7188 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7189 else
7190 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7191 }
7192
7193 static void vlv_compute_dpll(struct intel_crtc *crtc,
7194 struct intel_crtc_state *pipe_config)
7195 {
7196 u32 dpll, dpll_md;
7197
7198 /*
7199 * Enable DPIO clock input. We should never disable the reference
7200 * clock for pipe B, since VGA hotplug / manual detection depends
7201 * on it.
7202 */
7203 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7204 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7205 /* We should never disable this, set it here for state tracking */
7206 if (crtc->pipe == PIPE_B)
7207 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7208 dpll |= DPLL_VCO_ENABLE;
7209 pipe_config->dpll_hw_state.dpll = dpll;
7210
7211 dpll_md = (pipe_config->pixel_multiplier - 1)
7212 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7213 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7214 }
7215
7216 static void vlv_prepare_pll(struct intel_crtc *crtc,
7217 const struct intel_crtc_state *pipe_config)
7218 {
7219 struct drm_device *dev = crtc->base.dev;
7220 struct drm_i915_private *dev_priv = dev->dev_private;
7221 int pipe = crtc->pipe;
7222 u32 mdiv;
7223 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7224 u32 coreclk, reg_val;
7225
7226 mutex_lock(&dev_priv->sb_lock);
7227
7228 bestn = pipe_config->dpll.n;
7229 bestm1 = pipe_config->dpll.m1;
7230 bestm2 = pipe_config->dpll.m2;
7231 bestp1 = pipe_config->dpll.p1;
7232 bestp2 = pipe_config->dpll.p2;
7233
7234 /* See eDP HDMI DPIO driver vbios notes doc */
7235
7236 /* PLL B needs special handling */
7237 if (pipe == PIPE_B)
7238 vlv_pllb_recal_opamp(dev_priv, pipe);
7239
7240 /* Set up Tx target for periodic Rcomp update */
7241 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7242
7243 /* Disable target IRef on PLL */
7244 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7245 reg_val &= 0x00ffffff;
7246 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7247
7248 /* Disable fast lock */
7249 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7250
7251 /* Set idtafcrecal before PLL is enabled */
7252 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7253 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7254 mdiv |= ((bestn << DPIO_N_SHIFT));
7255 mdiv |= (1 << DPIO_K_SHIFT);
7256
7257 /*
7258 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7259 * but we don't support that).
7260 * Note: don't use the DAC post divider as it seems unstable.
7261 */
7262 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7263 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7264
7265 mdiv |= DPIO_ENABLE_CALIBRATION;
7266 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7267
7268 /* Set HBR and RBR LPF coefficients */
7269 if (pipe_config->port_clock == 162000 ||
7270 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7271 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7272 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7273 0x009f0003);
7274 else
7275 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7276 0x00d0000f);
7277
7278 if (pipe_config->has_dp_encoder) {
7279 /* Use SSC source */
7280 if (pipe == PIPE_A)
7281 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7282 0x0df40000);
7283 else
7284 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7285 0x0df70000);
7286 } else { /* HDMI or VGA */
7287 /* Use bend source */
7288 if (pipe == PIPE_A)
7289 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7290 0x0df70000);
7291 else
7292 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7293 0x0df40000);
7294 }
7295
7296 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7297 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7298 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7299 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7300 coreclk |= 0x01000000;
7301 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7302
7303 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7304 mutex_unlock(&dev_priv->sb_lock);
7305 }
7306
7307 static void chv_compute_dpll(struct intel_crtc *crtc,
7308 struct intel_crtc_state *pipe_config)
7309 {
7310 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7311 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7312 DPLL_VCO_ENABLE;
7313 if (crtc->pipe != PIPE_A)
7314 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7315
7316 pipe_config->dpll_hw_state.dpll_md =
7317 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7318 }
7319
7320 static void chv_prepare_pll(struct intel_crtc *crtc,
7321 const struct intel_crtc_state *pipe_config)
7322 {
7323 struct drm_device *dev = crtc->base.dev;
7324 struct drm_i915_private *dev_priv = dev->dev_private;
7325 int pipe = crtc->pipe;
7326 int dpll_reg = DPLL(crtc->pipe);
7327 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7328 u32 loopfilter, tribuf_calcntr;
7329 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7330 u32 dpio_val;
7331 int vco;
7332
7333 bestn = pipe_config->dpll.n;
7334 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7335 bestm1 = pipe_config->dpll.m1;
7336 bestm2 = pipe_config->dpll.m2 >> 22;
7337 bestp1 = pipe_config->dpll.p1;
7338 bestp2 = pipe_config->dpll.p2;
7339 vco = pipe_config->dpll.vco;
7340 dpio_val = 0;
7341 loopfilter = 0;
7342
7343 /*
7344 * Enable Refclk and SSC
7345 */
7346 I915_WRITE(dpll_reg,
7347 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7348
7349 mutex_lock(&dev_priv->sb_lock);
7350
7351 /* p1 and p2 divider */
7352 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7353 5 << DPIO_CHV_S1_DIV_SHIFT |
7354 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7355 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7356 1 << DPIO_CHV_K_DIV_SHIFT);
7357
7358 /* Feedback post-divider - m2 */
7359 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7360
7361 /* Feedback refclk divider - n and m1 */
7362 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7363 DPIO_CHV_M1_DIV_BY_2 |
7364 1 << DPIO_CHV_N_DIV_SHIFT);
7365
7366 /* M2 fraction division */
7367 if (bestm2_frac)
7368 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7369
7370 /* M2 fraction division enable */
7371 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7372 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7373 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7374 if (bestm2_frac)
7375 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7376 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7377
7378 /* Program digital lock detect threshold */
7379 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7380 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7381 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7382 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7383 if (!bestm2_frac)
7384 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7385 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7386
7387 /* Loop filter */
7388 if (vco == 5400000) {
7389 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7390 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7391 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7392 tribuf_calcntr = 0x9;
7393 } else if (vco <= 6200000) {
7394 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7395 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7396 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7397 tribuf_calcntr = 0x9;
7398 } else if (vco <= 6480000) {
7399 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7400 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7401 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7402 tribuf_calcntr = 0x8;
7403 } else {
7404 /* Not supported. Apply the same limits as in the max case */
7405 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7406 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7407 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7408 tribuf_calcntr = 0;
7409 }
7410 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7411
7412 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7413 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7414 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7415 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7416
7417 /* AFC Recal */
7418 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7419 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7420 DPIO_AFC_RECAL);
7421
7422 mutex_unlock(&dev_priv->sb_lock);
7423 }
7424
7425 /**
7426 * vlv_force_pll_on - forcibly enable just the PLL
7427 * @dev_priv: i915 private structure
7428 * @pipe: pipe PLL to enable
7429 * @dpll: PLL configuration
7430 *
7431 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7432 * in cases where we need the PLL enabled even when @pipe is not going to
7433 * be enabled.
7434 */
7435 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7436 const struct dpll *dpll)
7437 {
7438 struct intel_crtc *crtc =
7439 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7440 struct intel_crtc_state pipe_config = {
7441 .base.crtc = &crtc->base,
7442 .pixel_multiplier = 1,
7443 .dpll = *dpll,
7444 };
7445
7446 if (IS_CHERRYVIEW(dev)) {
7447 chv_compute_dpll(crtc, &pipe_config);
7448 chv_prepare_pll(crtc, &pipe_config);
7449 chv_enable_pll(crtc, &pipe_config);
7450 } else {
7451 vlv_compute_dpll(crtc, &pipe_config);
7452 vlv_prepare_pll(crtc, &pipe_config);
7453 vlv_enable_pll(crtc, &pipe_config);
7454 }
7455 }
7456
7457 /**
7458 * vlv_force_pll_off - forcibly disable just the PLL
7459 * @dev_priv: i915 private structure
7460 * @pipe: pipe PLL to disable
7461 *
7462 * Disable the PLL for @pipe. To be used in cases where we need
7463 * the PLL enabled even when @pipe is not going to be enabled.
7464 */
7465 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7466 {
7467 if (IS_CHERRYVIEW(dev))
7468 chv_disable_pll(to_i915(dev), pipe);
7469 else
7470 vlv_disable_pll(to_i915(dev), pipe);
7471 }
7472
7473 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7474 struct intel_crtc_state *crtc_state,
7475 intel_clock_t *reduced_clock,
7476 int num_connectors)
7477 {
7478 struct drm_device *dev = crtc->base.dev;
7479 struct drm_i915_private *dev_priv = dev->dev_private;
7480 u32 dpll;
7481 bool is_sdvo;
7482 struct dpll *clock = &crtc_state->dpll;
7483
7484 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7485
7486 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7487 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7488
7489 dpll = DPLL_VGA_MODE_DIS;
7490
7491 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7492 dpll |= DPLLB_MODE_LVDS;
7493 else
7494 dpll |= DPLLB_MODE_DAC_SERIAL;
7495
7496 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7497 dpll |= (crtc_state->pixel_multiplier - 1)
7498 << SDVO_MULTIPLIER_SHIFT_HIRES;
7499 }
7500
7501 if (is_sdvo)
7502 dpll |= DPLL_SDVO_HIGH_SPEED;
7503
7504 if (crtc_state->has_dp_encoder)
7505 dpll |= DPLL_SDVO_HIGH_SPEED;
7506
7507 /* compute bitmask from p1 value */
7508 if (IS_PINEVIEW(dev))
7509 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7510 else {
7511 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7512 if (IS_G4X(dev) && reduced_clock)
7513 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7514 }
7515 switch (clock->p2) {
7516 case 5:
7517 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7518 break;
7519 case 7:
7520 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7521 break;
7522 case 10:
7523 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7524 break;
7525 case 14:
7526 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7527 break;
7528 }
7529 if (INTEL_INFO(dev)->gen >= 4)
7530 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7531
7532 if (crtc_state->sdvo_tv_clock)
7533 dpll |= PLL_REF_INPUT_TVCLKINBC;
7534 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7535 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7536 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7537 else
7538 dpll |= PLL_REF_INPUT_DREFCLK;
7539
7540 dpll |= DPLL_VCO_ENABLE;
7541 crtc_state->dpll_hw_state.dpll = dpll;
7542
7543 if (INTEL_INFO(dev)->gen >= 4) {
7544 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7545 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7546 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7547 }
7548 }
7549
7550 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7551 struct intel_crtc_state *crtc_state,
7552 intel_clock_t *reduced_clock,
7553 int num_connectors)
7554 {
7555 struct drm_device *dev = crtc->base.dev;
7556 struct drm_i915_private *dev_priv = dev->dev_private;
7557 u32 dpll;
7558 struct dpll *clock = &crtc_state->dpll;
7559
7560 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7561
7562 dpll = DPLL_VGA_MODE_DIS;
7563
7564 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7565 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7566 } else {
7567 if (clock->p1 == 2)
7568 dpll |= PLL_P1_DIVIDE_BY_TWO;
7569 else
7570 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7571 if (clock->p2 == 4)
7572 dpll |= PLL_P2_DIVIDE_BY_4;
7573 }
7574
7575 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7576 dpll |= DPLL_DVO_2X_MODE;
7577
7578 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7579 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7580 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7581 else
7582 dpll |= PLL_REF_INPUT_DREFCLK;
7583
7584 dpll |= DPLL_VCO_ENABLE;
7585 crtc_state->dpll_hw_state.dpll = dpll;
7586 }
7587
7588 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7589 {
7590 struct drm_device *dev = intel_crtc->base.dev;
7591 struct drm_i915_private *dev_priv = dev->dev_private;
7592 enum pipe pipe = intel_crtc->pipe;
7593 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7594 struct drm_display_mode *adjusted_mode =
7595 &intel_crtc->config->base.adjusted_mode;
7596 uint32_t crtc_vtotal, crtc_vblank_end;
7597 int vsyncshift = 0;
7598
7599 /* We need to be careful not to changed the adjusted mode, for otherwise
7600 * the hw state checker will get angry at the mismatch. */
7601 crtc_vtotal = adjusted_mode->crtc_vtotal;
7602 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7603
7604 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7605 /* the chip adds 2 halflines automatically */
7606 crtc_vtotal -= 1;
7607 crtc_vblank_end -= 1;
7608
7609 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7610 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7611 else
7612 vsyncshift = adjusted_mode->crtc_hsync_start -
7613 adjusted_mode->crtc_htotal / 2;
7614 if (vsyncshift < 0)
7615 vsyncshift += adjusted_mode->crtc_htotal;
7616 }
7617
7618 if (INTEL_INFO(dev)->gen > 3)
7619 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7620
7621 I915_WRITE(HTOTAL(cpu_transcoder),
7622 (adjusted_mode->crtc_hdisplay - 1) |
7623 ((adjusted_mode->crtc_htotal - 1) << 16));
7624 I915_WRITE(HBLANK(cpu_transcoder),
7625 (adjusted_mode->crtc_hblank_start - 1) |
7626 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7627 I915_WRITE(HSYNC(cpu_transcoder),
7628 (adjusted_mode->crtc_hsync_start - 1) |
7629 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7630
7631 I915_WRITE(VTOTAL(cpu_transcoder),
7632 (adjusted_mode->crtc_vdisplay - 1) |
7633 ((crtc_vtotal - 1) << 16));
7634 I915_WRITE(VBLANK(cpu_transcoder),
7635 (adjusted_mode->crtc_vblank_start - 1) |
7636 ((crtc_vblank_end - 1) << 16));
7637 I915_WRITE(VSYNC(cpu_transcoder),
7638 (adjusted_mode->crtc_vsync_start - 1) |
7639 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7640
7641 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7642 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7643 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7644 * bits. */
7645 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7646 (pipe == PIPE_B || pipe == PIPE_C))
7647 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7648
7649 /* pipesrc controls the size that is scaled from, which should
7650 * always be the user's requested size.
7651 */
7652 I915_WRITE(PIPESRC(pipe),
7653 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7654 (intel_crtc->config->pipe_src_h - 1));
7655 }
7656
7657 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7658 struct intel_crtc_state *pipe_config)
7659 {
7660 struct drm_device *dev = crtc->base.dev;
7661 struct drm_i915_private *dev_priv = dev->dev_private;
7662 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7663 uint32_t tmp;
7664
7665 tmp = I915_READ(HTOTAL(cpu_transcoder));
7666 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7667 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7668 tmp = I915_READ(HBLANK(cpu_transcoder));
7669 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7670 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7671 tmp = I915_READ(HSYNC(cpu_transcoder));
7672 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7673 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7674
7675 tmp = I915_READ(VTOTAL(cpu_transcoder));
7676 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7677 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7678 tmp = I915_READ(VBLANK(cpu_transcoder));
7679 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7680 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7681 tmp = I915_READ(VSYNC(cpu_transcoder));
7682 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7683 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7684
7685 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7686 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7687 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7688 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7689 }
7690
7691 tmp = I915_READ(PIPESRC(crtc->pipe));
7692 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7693 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7694
7695 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7696 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7697 }
7698
7699 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7700 struct intel_crtc_state *pipe_config)
7701 {
7702 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7703 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7704 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7705 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7706
7707 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7708 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7709 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7710 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7711
7712 mode->flags = pipe_config->base.adjusted_mode.flags;
7713 mode->type = DRM_MODE_TYPE_DRIVER;
7714
7715 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7716 mode->flags |= pipe_config->base.adjusted_mode.flags;
7717
7718 mode->hsync = drm_mode_hsync(mode);
7719 mode->vrefresh = drm_mode_vrefresh(mode);
7720 drm_mode_set_name(mode);
7721 }
7722
7723 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7724 {
7725 struct drm_device *dev = intel_crtc->base.dev;
7726 struct drm_i915_private *dev_priv = dev->dev_private;
7727 uint32_t pipeconf;
7728
7729 pipeconf = 0;
7730
7731 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7732 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7733 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7734
7735 if (intel_crtc->config->double_wide)
7736 pipeconf |= PIPECONF_DOUBLE_WIDE;
7737
7738 /* only g4x and later have fancy bpc/dither controls */
7739 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7740 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7741 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7742 pipeconf |= PIPECONF_DITHER_EN |
7743 PIPECONF_DITHER_TYPE_SP;
7744
7745 switch (intel_crtc->config->pipe_bpp) {
7746 case 18:
7747 pipeconf |= PIPECONF_6BPC;
7748 break;
7749 case 24:
7750 pipeconf |= PIPECONF_8BPC;
7751 break;
7752 case 30:
7753 pipeconf |= PIPECONF_10BPC;
7754 break;
7755 default:
7756 /* Case prevented by intel_choose_pipe_bpp_dither. */
7757 BUG();
7758 }
7759 }
7760
7761 if (HAS_PIPE_CXSR(dev)) {
7762 if (intel_crtc->lowfreq_avail) {
7763 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7764 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7765 } else {
7766 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7767 }
7768 }
7769
7770 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7771 if (INTEL_INFO(dev)->gen < 4 ||
7772 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7773 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7774 else
7775 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7776 } else
7777 pipeconf |= PIPECONF_PROGRESSIVE;
7778
7779 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7780 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7781
7782 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7783 POSTING_READ(PIPECONF(intel_crtc->pipe));
7784 }
7785
7786 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7787 struct intel_crtc_state *crtc_state)
7788 {
7789 struct drm_device *dev = crtc->base.dev;
7790 struct drm_i915_private *dev_priv = dev->dev_private;
7791 int refclk, num_connectors = 0;
7792 intel_clock_t clock;
7793 bool ok;
7794 bool is_dsi = false;
7795 struct intel_encoder *encoder;
7796 const intel_limit_t *limit;
7797 struct drm_atomic_state *state = crtc_state->base.state;
7798 struct drm_connector *connector;
7799 struct drm_connector_state *connector_state;
7800 int i;
7801
7802 memset(&crtc_state->dpll_hw_state, 0,
7803 sizeof(crtc_state->dpll_hw_state));
7804
7805 for_each_connector_in_state(state, connector, connector_state, i) {
7806 if (connector_state->crtc != &crtc->base)
7807 continue;
7808
7809 encoder = to_intel_encoder(connector_state->best_encoder);
7810
7811 switch (encoder->type) {
7812 case INTEL_OUTPUT_DSI:
7813 is_dsi = true;
7814 break;
7815 default:
7816 break;
7817 }
7818
7819 num_connectors++;
7820 }
7821
7822 if (is_dsi)
7823 return 0;
7824
7825 if (!crtc_state->clock_set) {
7826 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7827
7828 /*
7829 * Returns a set of divisors for the desired target clock with
7830 * the given refclk, or FALSE. The returned values represent
7831 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7832 * 2) / p1 / p2.
7833 */
7834 limit = intel_limit(crtc_state, refclk);
7835 ok = dev_priv->display.find_dpll(limit, crtc_state,
7836 crtc_state->port_clock,
7837 refclk, NULL, &clock);
7838 if (!ok) {
7839 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7840 return -EINVAL;
7841 }
7842
7843 /* Compat-code for transition, will disappear. */
7844 crtc_state->dpll.n = clock.n;
7845 crtc_state->dpll.m1 = clock.m1;
7846 crtc_state->dpll.m2 = clock.m2;
7847 crtc_state->dpll.p1 = clock.p1;
7848 crtc_state->dpll.p2 = clock.p2;
7849 }
7850
7851 if (IS_GEN2(dev)) {
7852 i8xx_compute_dpll(crtc, crtc_state, NULL,
7853 num_connectors);
7854 } else if (IS_CHERRYVIEW(dev)) {
7855 chv_compute_dpll(crtc, crtc_state);
7856 } else if (IS_VALLEYVIEW(dev)) {
7857 vlv_compute_dpll(crtc, crtc_state);
7858 } else {
7859 i9xx_compute_dpll(crtc, crtc_state, NULL,
7860 num_connectors);
7861 }
7862
7863 return 0;
7864 }
7865
7866 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7867 struct intel_crtc_state *pipe_config)
7868 {
7869 struct drm_device *dev = crtc->base.dev;
7870 struct drm_i915_private *dev_priv = dev->dev_private;
7871 uint32_t tmp;
7872
7873 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7874 return;
7875
7876 tmp = I915_READ(PFIT_CONTROL);
7877 if (!(tmp & PFIT_ENABLE))
7878 return;
7879
7880 /* Check whether the pfit is attached to our pipe. */
7881 if (INTEL_INFO(dev)->gen < 4) {
7882 if (crtc->pipe != PIPE_B)
7883 return;
7884 } else {
7885 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7886 return;
7887 }
7888
7889 pipe_config->gmch_pfit.control = tmp;
7890 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7891 if (INTEL_INFO(dev)->gen < 5)
7892 pipe_config->gmch_pfit.lvds_border_bits =
7893 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7894 }
7895
7896 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7897 struct intel_crtc_state *pipe_config)
7898 {
7899 struct drm_device *dev = crtc->base.dev;
7900 struct drm_i915_private *dev_priv = dev->dev_private;
7901 int pipe = pipe_config->cpu_transcoder;
7902 intel_clock_t clock;
7903 u32 mdiv;
7904 int refclk = 100000;
7905
7906 /* In case of MIPI DPLL will not even be used */
7907 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7908 return;
7909
7910 mutex_lock(&dev_priv->sb_lock);
7911 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7912 mutex_unlock(&dev_priv->sb_lock);
7913
7914 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7915 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7916 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7917 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7918 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7919
7920 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7921 }
7922
7923 static void
7924 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7925 struct intel_initial_plane_config *plane_config)
7926 {
7927 struct drm_device *dev = crtc->base.dev;
7928 struct drm_i915_private *dev_priv = dev->dev_private;
7929 u32 val, base, offset;
7930 int pipe = crtc->pipe, plane = crtc->plane;
7931 int fourcc, pixel_format;
7932 unsigned int aligned_height;
7933 struct drm_framebuffer *fb;
7934 struct intel_framebuffer *intel_fb;
7935
7936 val = I915_READ(DSPCNTR(plane));
7937 if (!(val & DISPLAY_PLANE_ENABLE))
7938 return;
7939
7940 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7941 if (!intel_fb) {
7942 DRM_DEBUG_KMS("failed to alloc fb\n");
7943 return;
7944 }
7945
7946 fb = &intel_fb->base;
7947
7948 if (INTEL_INFO(dev)->gen >= 4) {
7949 if (val & DISPPLANE_TILED) {
7950 plane_config->tiling = I915_TILING_X;
7951 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7952 }
7953 }
7954
7955 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7956 fourcc = i9xx_format_to_fourcc(pixel_format);
7957 fb->pixel_format = fourcc;
7958 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7959
7960 if (INTEL_INFO(dev)->gen >= 4) {
7961 if (plane_config->tiling)
7962 offset = I915_READ(DSPTILEOFF(plane));
7963 else
7964 offset = I915_READ(DSPLINOFF(plane));
7965 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7966 } else {
7967 base = I915_READ(DSPADDR(plane));
7968 }
7969 plane_config->base = base;
7970
7971 val = I915_READ(PIPESRC(pipe));
7972 fb->width = ((val >> 16) & 0xfff) + 1;
7973 fb->height = ((val >> 0) & 0xfff) + 1;
7974
7975 val = I915_READ(DSPSTRIDE(pipe));
7976 fb->pitches[0] = val & 0xffffffc0;
7977
7978 aligned_height = intel_fb_align_height(dev, fb->height,
7979 fb->pixel_format,
7980 fb->modifier[0]);
7981
7982 plane_config->size = fb->pitches[0] * aligned_height;
7983
7984 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7985 pipe_name(pipe), plane, fb->width, fb->height,
7986 fb->bits_per_pixel, base, fb->pitches[0],
7987 plane_config->size);
7988
7989 plane_config->fb = intel_fb;
7990 }
7991
7992 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7993 struct intel_crtc_state *pipe_config)
7994 {
7995 struct drm_device *dev = crtc->base.dev;
7996 struct drm_i915_private *dev_priv = dev->dev_private;
7997 int pipe = pipe_config->cpu_transcoder;
7998 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7999 intel_clock_t clock;
8000 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8001 int refclk = 100000;
8002
8003 mutex_lock(&dev_priv->sb_lock);
8004 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8005 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8006 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8007 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8008 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8009 mutex_unlock(&dev_priv->sb_lock);
8010
8011 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8012 clock.m2 = (pll_dw0 & 0xff) << 22;
8013 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8014 clock.m2 |= pll_dw2 & 0x3fffff;
8015 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8016 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8017 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8018
8019 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8020 }
8021
8022 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8023 struct intel_crtc_state *pipe_config)
8024 {
8025 struct drm_device *dev = crtc->base.dev;
8026 struct drm_i915_private *dev_priv = dev->dev_private;
8027 uint32_t tmp;
8028
8029 if (!intel_display_power_is_enabled(dev_priv,
8030 POWER_DOMAIN_PIPE(crtc->pipe)))
8031 return false;
8032
8033 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8034 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8035
8036 tmp = I915_READ(PIPECONF(crtc->pipe));
8037 if (!(tmp & PIPECONF_ENABLE))
8038 return false;
8039
8040 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8041 switch (tmp & PIPECONF_BPC_MASK) {
8042 case PIPECONF_6BPC:
8043 pipe_config->pipe_bpp = 18;
8044 break;
8045 case PIPECONF_8BPC:
8046 pipe_config->pipe_bpp = 24;
8047 break;
8048 case PIPECONF_10BPC:
8049 pipe_config->pipe_bpp = 30;
8050 break;
8051 default:
8052 break;
8053 }
8054 }
8055
8056 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8057 pipe_config->limited_color_range = true;
8058
8059 if (INTEL_INFO(dev)->gen < 4)
8060 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8061
8062 intel_get_pipe_timings(crtc, pipe_config);
8063
8064 i9xx_get_pfit_config(crtc, pipe_config);
8065
8066 if (INTEL_INFO(dev)->gen >= 4) {
8067 tmp = I915_READ(DPLL_MD(crtc->pipe));
8068 pipe_config->pixel_multiplier =
8069 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8070 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8071 pipe_config->dpll_hw_state.dpll_md = tmp;
8072 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8073 tmp = I915_READ(DPLL(crtc->pipe));
8074 pipe_config->pixel_multiplier =
8075 ((tmp & SDVO_MULTIPLIER_MASK)
8076 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8077 } else {
8078 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8079 * port and will be fixed up in the encoder->get_config
8080 * function. */
8081 pipe_config->pixel_multiplier = 1;
8082 }
8083 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8084 if (!IS_VALLEYVIEW(dev)) {
8085 /*
8086 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8087 * on 830. Filter it out here so that we don't
8088 * report errors due to that.
8089 */
8090 if (IS_I830(dev))
8091 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8092
8093 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8094 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8095 } else {
8096 /* Mask out read-only status bits. */
8097 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8098 DPLL_PORTC_READY_MASK |
8099 DPLL_PORTB_READY_MASK);
8100 }
8101
8102 if (IS_CHERRYVIEW(dev))
8103 chv_crtc_clock_get(crtc, pipe_config);
8104 else if (IS_VALLEYVIEW(dev))
8105 vlv_crtc_clock_get(crtc, pipe_config);
8106 else
8107 i9xx_crtc_clock_get(crtc, pipe_config);
8108
8109 return true;
8110 }
8111
8112 static void ironlake_init_pch_refclk(struct drm_device *dev)
8113 {
8114 struct drm_i915_private *dev_priv = dev->dev_private;
8115 struct intel_encoder *encoder;
8116 u32 val, final;
8117 bool has_lvds = false;
8118 bool has_cpu_edp = false;
8119 bool has_panel = false;
8120 bool has_ck505 = false;
8121 bool can_ssc = false;
8122
8123 /* We need to take the global config into account */
8124 for_each_intel_encoder(dev, encoder) {
8125 switch (encoder->type) {
8126 case INTEL_OUTPUT_LVDS:
8127 has_panel = true;
8128 has_lvds = true;
8129 break;
8130 case INTEL_OUTPUT_EDP:
8131 has_panel = true;
8132 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8133 has_cpu_edp = true;
8134 break;
8135 default:
8136 break;
8137 }
8138 }
8139
8140 if (HAS_PCH_IBX(dev)) {
8141 has_ck505 = dev_priv->vbt.display_clock_mode;
8142 can_ssc = has_ck505;
8143 } else {
8144 has_ck505 = false;
8145 can_ssc = true;
8146 }
8147
8148 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8149 has_panel, has_lvds, has_ck505);
8150
8151 /* Ironlake: try to setup display ref clock before DPLL
8152 * enabling. This is only under driver's control after
8153 * PCH B stepping, previous chipset stepping should be
8154 * ignoring this setting.
8155 */
8156 val = I915_READ(PCH_DREF_CONTROL);
8157
8158 /* As we must carefully and slowly disable/enable each source in turn,
8159 * compute the final state we want first and check if we need to
8160 * make any changes at all.
8161 */
8162 final = val;
8163 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8164 if (has_ck505)
8165 final |= DREF_NONSPREAD_CK505_ENABLE;
8166 else
8167 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8168
8169 final &= ~DREF_SSC_SOURCE_MASK;
8170 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8171 final &= ~DREF_SSC1_ENABLE;
8172
8173 if (has_panel) {
8174 final |= DREF_SSC_SOURCE_ENABLE;
8175
8176 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8177 final |= DREF_SSC1_ENABLE;
8178
8179 if (has_cpu_edp) {
8180 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8181 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8182 else
8183 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8184 } else
8185 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8186 } else {
8187 final |= DREF_SSC_SOURCE_DISABLE;
8188 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8189 }
8190
8191 if (final == val)
8192 return;
8193
8194 /* Always enable nonspread source */
8195 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8196
8197 if (has_ck505)
8198 val |= DREF_NONSPREAD_CK505_ENABLE;
8199 else
8200 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8201
8202 if (has_panel) {
8203 val &= ~DREF_SSC_SOURCE_MASK;
8204 val |= DREF_SSC_SOURCE_ENABLE;
8205
8206 /* SSC must be turned on before enabling the CPU output */
8207 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8208 DRM_DEBUG_KMS("Using SSC on panel\n");
8209 val |= DREF_SSC1_ENABLE;
8210 } else
8211 val &= ~DREF_SSC1_ENABLE;
8212
8213 /* Get SSC going before enabling the outputs */
8214 I915_WRITE(PCH_DREF_CONTROL, val);
8215 POSTING_READ(PCH_DREF_CONTROL);
8216 udelay(200);
8217
8218 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8219
8220 /* Enable CPU source on CPU attached eDP */
8221 if (has_cpu_edp) {
8222 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8223 DRM_DEBUG_KMS("Using SSC on eDP\n");
8224 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8225 } else
8226 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8227 } else
8228 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8229
8230 I915_WRITE(PCH_DREF_CONTROL, val);
8231 POSTING_READ(PCH_DREF_CONTROL);
8232 udelay(200);
8233 } else {
8234 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8235
8236 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8237
8238 /* Turn off CPU output */
8239 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8240
8241 I915_WRITE(PCH_DREF_CONTROL, val);
8242 POSTING_READ(PCH_DREF_CONTROL);
8243 udelay(200);
8244
8245 /* Turn off the SSC source */
8246 val &= ~DREF_SSC_SOURCE_MASK;
8247 val |= DREF_SSC_SOURCE_DISABLE;
8248
8249 /* Turn off SSC1 */
8250 val &= ~DREF_SSC1_ENABLE;
8251
8252 I915_WRITE(PCH_DREF_CONTROL, val);
8253 POSTING_READ(PCH_DREF_CONTROL);
8254 udelay(200);
8255 }
8256
8257 BUG_ON(val != final);
8258 }
8259
8260 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8261 {
8262 uint32_t tmp;
8263
8264 tmp = I915_READ(SOUTH_CHICKEN2);
8265 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8266 I915_WRITE(SOUTH_CHICKEN2, tmp);
8267
8268 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8269 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8270 DRM_ERROR("FDI mPHY reset assert timeout\n");
8271
8272 tmp = I915_READ(SOUTH_CHICKEN2);
8273 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8274 I915_WRITE(SOUTH_CHICKEN2, tmp);
8275
8276 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8277 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8278 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8279 }
8280
8281 /* WaMPhyProgramming:hsw */
8282 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8283 {
8284 uint32_t tmp;
8285
8286 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8287 tmp &= ~(0xFF << 24);
8288 tmp |= (0x12 << 24);
8289 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8290
8291 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8292 tmp |= (1 << 11);
8293 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8294
8295 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8296 tmp |= (1 << 11);
8297 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8298
8299 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8300 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8301 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8302
8303 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8304 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8305 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8306
8307 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8308 tmp &= ~(7 << 13);
8309 tmp |= (5 << 13);
8310 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8311
8312 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8313 tmp &= ~(7 << 13);
8314 tmp |= (5 << 13);
8315 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8316
8317 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8318 tmp &= ~0xFF;
8319 tmp |= 0x1C;
8320 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8321
8322 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8323 tmp &= ~0xFF;
8324 tmp |= 0x1C;
8325 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8326
8327 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8328 tmp &= ~(0xFF << 16);
8329 tmp |= (0x1C << 16);
8330 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8331
8332 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8333 tmp &= ~(0xFF << 16);
8334 tmp |= (0x1C << 16);
8335 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8336
8337 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8338 tmp |= (1 << 27);
8339 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8340
8341 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8342 tmp |= (1 << 27);
8343 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8344
8345 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8346 tmp &= ~(0xF << 28);
8347 tmp |= (4 << 28);
8348 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8349
8350 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8351 tmp &= ~(0xF << 28);
8352 tmp |= (4 << 28);
8353 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8354 }
8355
8356 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8357 * Programming" based on the parameters passed:
8358 * - Sequence to enable CLKOUT_DP
8359 * - Sequence to enable CLKOUT_DP without spread
8360 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8361 */
8362 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8363 bool with_fdi)
8364 {
8365 struct drm_i915_private *dev_priv = dev->dev_private;
8366 uint32_t reg, tmp;
8367
8368 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8369 with_spread = true;
8370 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8371 with_fdi, "LP PCH doesn't have FDI\n"))
8372 with_fdi = false;
8373
8374 mutex_lock(&dev_priv->sb_lock);
8375
8376 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8377 tmp &= ~SBI_SSCCTL_DISABLE;
8378 tmp |= SBI_SSCCTL_PATHALT;
8379 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8380
8381 udelay(24);
8382
8383 if (with_spread) {
8384 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8385 tmp &= ~SBI_SSCCTL_PATHALT;
8386 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8387
8388 if (with_fdi) {
8389 lpt_reset_fdi_mphy(dev_priv);
8390 lpt_program_fdi_mphy(dev_priv);
8391 }
8392 }
8393
8394 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8395 SBI_GEN0 : SBI_DBUFF0;
8396 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8397 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8398 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8399
8400 mutex_unlock(&dev_priv->sb_lock);
8401 }
8402
8403 /* Sequence to disable CLKOUT_DP */
8404 static void lpt_disable_clkout_dp(struct drm_device *dev)
8405 {
8406 struct drm_i915_private *dev_priv = dev->dev_private;
8407 uint32_t reg, tmp;
8408
8409 mutex_lock(&dev_priv->sb_lock);
8410
8411 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8412 SBI_GEN0 : SBI_DBUFF0;
8413 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8414 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8415 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8416
8417 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8418 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8419 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8420 tmp |= SBI_SSCCTL_PATHALT;
8421 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8422 udelay(32);
8423 }
8424 tmp |= SBI_SSCCTL_DISABLE;
8425 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8426 }
8427
8428 mutex_unlock(&dev_priv->sb_lock);
8429 }
8430
8431 static void lpt_init_pch_refclk(struct drm_device *dev)
8432 {
8433 struct intel_encoder *encoder;
8434 bool has_vga = false;
8435
8436 for_each_intel_encoder(dev, encoder) {
8437 switch (encoder->type) {
8438 case INTEL_OUTPUT_ANALOG:
8439 has_vga = true;
8440 break;
8441 default:
8442 break;
8443 }
8444 }
8445
8446 if (has_vga)
8447 lpt_enable_clkout_dp(dev, true, true);
8448 else
8449 lpt_disable_clkout_dp(dev);
8450 }
8451
8452 /*
8453 * Initialize reference clocks when the driver loads
8454 */
8455 void intel_init_pch_refclk(struct drm_device *dev)
8456 {
8457 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8458 ironlake_init_pch_refclk(dev);
8459 else if (HAS_PCH_LPT(dev))
8460 lpt_init_pch_refclk(dev);
8461 }
8462
8463 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8464 {
8465 struct drm_device *dev = crtc_state->base.crtc->dev;
8466 struct drm_i915_private *dev_priv = dev->dev_private;
8467 struct drm_atomic_state *state = crtc_state->base.state;
8468 struct drm_connector *connector;
8469 struct drm_connector_state *connector_state;
8470 struct intel_encoder *encoder;
8471 int num_connectors = 0, i;
8472 bool is_lvds = false;
8473
8474 for_each_connector_in_state(state, connector, connector_state, i) {
8475 if (connector_state->crtc != crtc_state->base.crtc)
8476 continue;
8477
8478 encoder = to_intel_encoder(connector_state->best_encoder);
8479
8480 switch (encoder->type) {
8481 case INTEL_OUTPUT_LVDS:
8482 is_lvds = true;
8483 break;
8484 default:
8485 break;
8486 }
8487 num_connectors++;
8488 }
8489
8490 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8491 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8492 dev_priv->vbt.lvds_ssc_freq);
8493 return dev_priv->vbt.lvds_ssc_freq;
8494 }
8495
8496 return 120000;
8497 }
8498
8499 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8500 {
8501 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8503 int pipe = intel_crtc->pipe;
8504 uint32_t val;
8505
8506 val = 0;
8507
8508 switch (intel_crtc->config->pipe_bpp) {
8509 case 18:
8510 val |= PIPECONF_6BPC;
8511 break;
8512 case 24:
8513 val |= PIPECONF_8BPC;
8514 break;
8515 case 30:
8516 val |= PIPECONF_10BPC;
8517 break;
8518 case 36:
8519 val |= PIPECONF_12BPC;
8520 break;
8521 default:
8522 /* Case prevented by intel_choose_pipe_bpp_dither. */
8523 BUG();
8524 }
8525
8526 if (intel_crtc->config->dither)
8527 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8528
8529 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8530 val |= PIPECONF_INTERLACED_ILK;
8531 else
8532 val |= PIPECONF_PROGRESSIVE;
8533
8534 if (intel_crtc->config->limited_color_range)
8535 val |= PIPECONF_COLOR_RANGE_SELECT;
8536
8537 I915_WRITE(PIPECONF(pipe), val);
8538 POSTING_READ(PIPECONF(pipe));
8539 }
8540
8541 /*
8542 * Set up the pipe CSC unit.
8543 *
8544 * Currently only full range RGB to limited range RGB conversion
8545 * is supported, but eventually this should handle various
8546 * RGB<->YCbCr scenarios as well.
8547 */
8548 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8549 {
8550 struct drm_device *dev = crtc->dev;
8551 struct drm_i915_private *dev_priv = dev->dev_private;
8552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8553 int pipe = intel_crtc->pipe;
8554 uint16_t coeff = 0x7800; /* 1.0 */
8555
8556 /*
8557 * TODO: Check what kind of values actually come out of the pipe
8558 * with these coeff/postoff values and adjust to get the best
8559 * accuracy. Perhaps we even need to take the bpc value into
8560 * consideration.
8561 */
8562
8563 if (intel_crtc->config->limited_color_range)
8564 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8565
8566 /*
8567 * GY/GU and RY/RU should be the other way around according
8568 * to BSpec, but reality doesn't agree. Just set them up in
8569 * a way that results in the correct picture.
8570 */
8571 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8572 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8573
8574 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8575 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8576
8577 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8578 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8579
8580 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8581 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8582 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8583
8584 if (INTEL_INFO(dev)->gen > 6) {
8585 uint16_t postoff = 0;
8586
8587 if (intel_crtc->config->limited_color_range)
8588 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8589
8590 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8591 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8592 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8593
8594 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8595 } else {
8596 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8597
8598 if (intel_crtc->config->limited_color_range)
8599 mode |= CSC_BLACK_SCREEN_OFFSET;
8600
8601 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8602 }
8603 }
8604
8605 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8606 {
8607 struct drm_device *dev = crtc->dev;
8608 struct drm_i915_private *dev_priv = dev->dev_private;
8609 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8610 enum pipe pipe = intel_crtc->pipe;
8611 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8612 uint32_t val;
8613
8614 val = 0;
8615
8616 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8617 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8618
8619 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8620 val |= PIPECONF_INTERLACED_ILK;
8621 else
8622 val |= PIPECONF_PROGRESSIVE;
8623
8624 I915_WRITE(PIPECONF(cpu_transcoder), val);
8625 POSTING_READ(PIPECONF(cpu_transcoder));
8626
8627 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8628 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8629
8630 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8631 val = 0;
8632
8633 switch (intel_crtc->config->pipe_bpp) {
8634 case 18:
8635 val |= PIPEMISC_DITHER_6_BPC;
8636 break;
8637 case 24:
8638 val |= PIPEMISC_DITHER_8_BPC;
8639 break;
8640 case 30:
8641 val |= PIPEMISC_DITHER_10_BPC;
8642 break;
8643 case 36:
8644 val |= PIPEMISC_DITHER_12_BPC;
8645 break;
8646 default:
8647 /* Case prevented by pipe_config_set_bpp. */
8648 BUG();
8649 }
8650
8651 if (intel_crtc->config->dither)
8652 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8653
8654 I915_WRITE(PIPEMISC(pipe), val);
8655 }
8656 }
8657
8658 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8659 struct intel_crtc_state *crtc_state,
8660 intel_clock_t *clock,
8661 bool *has_reduced_clock,
8662 intel_clock_t *reduced_clock)
8663 {
8664 struct drm_device *dev = crtc->dev;
8665 struct drm_i915_private *dev_priv = dev->dev_private;
8666 int refclk;
8667 const intel_limit_t *limit;
8668 bool ret;
8669
8670 refclk = ironlake_get_refclk(crtc_state);
8671
8672 /*
8673 * Returns a set of divisors for the desired target clock with the given
8674 * refclk, or FALSE. The returned values represent the clock equation:
8675 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8676 */
8677 limit = intel_limit(crtc_state, refclk);
8678 ret = dev_priv->display.find_dpll(limit, crtc_state,
8679 crtc_state->port_clock,
8680 refclk, NULL, clock);
8681 if (!ret)
8682 return false;
8683
8684 return true;
8685 }
8686
8687 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8688 {
8689 /*
8690 * Account for spread spectrum to avoid
8691 * oversubscribing the link. Max center spread
8692 * is 2.5%; use 5% for safety's sake.
8693 */
8694 u32 bps = target_clock * bpp * 21 / 20;
8695 return DIV_ROUND_UP(bps, link_bw * 8);
8696 }
8697
8698 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8699 {
8700 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8701 }
8702
8703 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8704 struct intel_crtc_state *crtc_state,
8705 u32 *fp,
8706 intel_clock_t *reduced_clock, u32 *fp2)
8707 {
8708 struct drm_crtc *crtc = &intel_crtc->base;
8709 struct drm_device *dev = crtc->dev;
8710 struct drm_i915_private *dev_priv = dev->dev_private;
8711 struct drm_atomic_state *state = crtc_state->base.state;
8712 struct drm_connector *connector;
8713 struct drm_connector_state *connector_state;
8714 struct intel_encoder *encoder;
8715 uint32_t dpll;
8716 int factor, num_connectors = 0, i;
8717 bool is_lvds = false, is_sdvo = false;
8718
8719 for_each_connector_in_state(state, connector, connector_state, i) {
8720 if (connector_state->crtc != crtc_state->base.crtc)
8721 continue;
8722
8723 encoder = to_intel_encoder(connector_state->best_encoder);
8724
8725 switch (encoder->type) {
8726 case INTEL_OUTPUT_LVDS:
8727 is_lvds = true;
8728 break;
8729 case INTEL_OUTPUT_SDVO:
8730 case INTEL_OUTPUT_HDMI:
8731 is_sdvo = true;
8732 break;
8733 default:
8734 break;
8735 }
8736
8737 num_connectors++;
8738 }
8739
8740 /* Enable autotuning of the PLL clock (if permissible) */
8741 factor = 21;
8742 if (is_lvds) {
8743 if ((intel_panel_use_ssc(dev_priv) &&
8744 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8745 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8746 factor = 25;
8747 } else if (crtc_state->sdvo_tv_clock)
8748 factor = 20;
8749
8750 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8751 *fp |= FP_CB_TUNE;
8752
8753 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8754 *fp2 |= FP_CB_TUNE;
8755
8756 dpll = 0;
8757
8758 if (is_lvds)
8759 dpll |= DPLLB_MODE_LVDS;
8760 else
8761 dpll |= DPLLB_MODE_DAC_SERIAL;
8762
8763 dpll |= (crtc_state->pixel_multiplier - 1)
8764 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8765
8766 if (is_sdvo)
8767 dpll |= DPLL_SDVO_HIGH_SPEED;
8768 if (crtc_state->has_dp_encoder)
8769 dpll |= DPLL_SDVO_HIGH_SPEED;
8770
8771 /* compute bitmask from p1 value */
8772 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8773 /* also FPA1 */
8774 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8775
8776 switch (crtc_state->dpll.p2) {
8777 case 5:
8778 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8779 break;
8780 case 7:
8781 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8782 break;
8783 case 10:
8784 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8785 break;
8786 case 14:
8787 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8788 break;
8789 }
8790
8791 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8792 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8793 else
8794 dpll |= PLL_REF_INPUT_DREFCLK;
8795
8796 return dpll | DPLL_VCO_ENABLE;
8797 }
8798
8799 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8800 struct intel_crtc_state *crtc_state)
8801 {
8802 struct drm_device *dev = crtc->base.dev;
8803 intel_clock_t clock, reduced_clock;
8804 u32 dpll = 0, fp = 0, fp2 = 0;
8805 bool ok, has_reduced_clock = false;
8806 bool is_lvds = false;
8807 struct intel_shared_dpll *pll;
8808
8809 memset(&crtc_state->dpll_hw_state, 0,
8810 sizeof(crtc_state->dpll_hw_state));
8811
8812 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8813
8814 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8815 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8816
8817 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8818 &has_reduced_clock, &reduced_clock);
8819 if (!ok && !crtc_state->clock_set) {
8820 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8821 return -EINVAL;
8822 }
8823 /* Compat-code for transition, will disappear. */
8824 if (!crtc_state->clock_set) {
8825 crtc_state->dpll.n = clock.n;
8826 crtc_state->dpll.m1 = clock.m1;
8827 crtc_state->dpll.m2 = clock.m2;
8828 crtc_state->dpll.p1 = clock.p1;
8829 crtc_state->dpll.p2 = clock.p2;
8830 }
8831
8832 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8833 if (crtc_state->has_pch_encoder) {
8834 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8835 if (has_reduced_clock)
8836 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8837
8838 dpll = ironlake_compute_dpll(crtc, crtc_state,
8839 &fp, &reduced_clock,
8840 has_reduced_clock ? &fp2 : NULL);
8841
8842 crtc_state->dpll_hw_state.dpll = dpll;
8843 crtc_state->dpll_hw_state.fp0 = fp;
8844 if (has_reduced_clock)
8845 crtc_state->dpll_hw_state.fp1 = fp2;
8846 else
8847 crtc_state->dpll_hw_state.fp1 = fp;
8848
8849 pll = intel_get_shared_dpll(crtc, crtc_state);
8850 if (pll == NULL) {
8851 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8852 pipe_name(crtc->pipe));
8853 return -EINVAL;
8854 }
8855 }
8856
8857 if (is_lvds && has_reduced_clock)
8858 crtc->lowfreq_avail = true;
8859 else
8860 crtc->lowfreq_avail = false;
8861
8862 return 0;
8863 }
8864
8865 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8866 struct intel_link_m_n *m_n)
8867 {
8868 struct drm_device *dev = crtc->base.dev;
8869 struct drm_i915_private *dev_priv = dev->dev_private;
8870 enum pipe pipe = crtc->pipe;
8871
8872 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8873 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8874 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8875 & ~TU_SIZE_MASK;
8876 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8877 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8878 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8879 }
8880
8881 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8882 enum transcoder transcoder,
8883 struct intel_link_m_n *m_n,
8884 struct intel_link_m_n *m2_n2)
8885 {
8886 struct drm_device *dev = crtc->base.dev;
8887 struct drm_i915_private *dev_priv = dev->dev_private;
8888 enum pipe pipe = crtc->pipe;
8889
8890 if (INTEL_INFO(dev)->gen >= 5) {
8891 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8892 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8893 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8894 & ~TU_SIZE_MASK;
8895 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8896 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8897 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8898 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8899 * gen < 8) and if DRRS is supported (to make sure the
8900 * registers are not unnecessarily read).
8901 */
8902 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8903 crtc->config->has_drrs) {
8904 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8905 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8906 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8907 & ~TU_SIZE_MASK;
8908 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8909 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8910 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8911 }
8912 } else {
8913 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8914 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8915 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8916 & ~TU_SIZE_MASK;
8917 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8918 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8919 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8920 }
8921 }
8922
8923 void intel_dp_get_m_n(struct intel_crtc *crtc,
8924 struct intel_crtc_state *pipe_config)
8925 {
8926 if (pipe_config->has_pch_encoder)
8927 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8928 else
8929 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8930 &pipe_config->dp_m_n,
8931 &pipe_config->dp_m2_n2);
8932 }
8933
8934 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8935 struct intel_crtc_state *pipe_config)
8936 {
8937 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8938 &pipe_config->fdi_m_n, NULL);
8939 }
8940
8941 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8942 struct intel_crtc_state *pipe_config)
8943 {
8944 struct drm_device *dev = crtc->base.dev;
8945 struct drm_i915_private *dev_priv = dev->dev_private;
8946 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8947 uint32_t ps_ctrl = 0;
8948 int id = -1;
8949 int i;
8950
8951 /* find scaler attached to this pipe */
8952 for (i = 0; i < crtc->num_scalers; i++) {
8953 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8954 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8955 id = i;
8956 pipe_config->pch_pfit.enabled = true;
8957 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8958 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8959 break;
8960 }
8961 }
8962
8963 scaler_state->scaler_id = id;
8964 if (id >= 0) {
8965 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8966 } else {
8967 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8968 }
8969 }
8970
8971 static void
8972 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8973 struct intel_initial_plane_config *plane_config)
8974 {
8975 struct drm_device *dev = crtc->base.dev;
8976 struct drm_i915_private *dev_priv = dev->dev_private;
8977 u32 val, base, offset, stride_mult, tiling;
8978 int pipe = crtc->pipe;
8979 int fourcc, pixel_format;
8980 unsigned int aligned_height;
8981 struct drm_framebuffer *fb;
8982 struct intel_framebuffer *intel_fb;
8983
8984 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8985 if (!intel_fb) {
8986 DRM_DEBUG_KMS("failed to alloc fb\n");
8987 return;
8988 }
8989
8990 fb = &intel_fb->base;
8991
8992 val = I915_READ(PLANE_CTL(pipe, 0));
8993 if (!(val & PLANE_CTL_ENABLE))
8994 goto error;
8995
8996 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8997 fourcc = skl_format_to_fourcc(pixel_format,
8998 val & PLANE_CTL_ORDER_RGBX,
8999 val & PLANE_CTL_ALPHA_MASK);
9000 fb->pixel_format = fourcc;
9001 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9002
9003 tiling = val & PLANE_CTL_TILED_MASK;
9004 switch (tiling) {
9005 case PLANE_CTL_TILED_LINEAR:
9006 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9007 break;
9008 case PLANE_CTL_TILED_X:
9009 plane_config->tiling = I915_TILING_X;
9010 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9011 break;
9012 case PLANE_CTL_TILED_Y:
9013 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9014 break;
9015 case PLANE_CTL_TILED_YF:
9016 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9017 break;
9018 default:
9019 MISSING_CASE(tiling);
9020 goto error;
9021 }
9022
9023 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9024 plane_config->base = base;
9025
9026 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9027
9028 val = I915_READ(PLANE_SIZE(pipe, 0));
9029 fb->height = ((val >> 16) & 0xfff) + 1;
9030 fb->width = ((val >> 0) & 0x1fff) + 1;
9031
9032 val = I915_READ(PLANE_STRIDE(pipe, 0));
9033 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9034 fb->pixel_format);
9035 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9036
9037 aligned_height = intel_fb_align_height(dev, fb->height,
9038 fb->pixel_format,
9039 fb->modifier[0]);
9040
9041 plane_config->size = fb->pitches[0] * aligned_height;
9042
9043 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9044 pipe_name(pipe), fb->width, fb->height,
9045 fb->bits_per_pixel, base, fb->pitches[0],
9046 plane_config->size);
9047
9048 plane_config->fb = intel_fb;
9049 return;
9050
9051 error:
9052 kfree(fb);
9053 }
9054
9055 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9056 struct intel_crtc_state *pipe_config)
9057 {
9058 struct drm_device *dev = crtc->base.dev;
9059 struct drm_i915_private *dev_priv = dev->dev_private;
9060 uint32_t tmp;
9061
9062 tmp = I915_READ(PF_CTL(crtc->pipe));
9063
9064 if (tmp & PF_ENABLE) {
9065 pipe_config->pch_pfit.enabled = true;
9066 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9067 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9068
9069 /* We currently do not free assignements of panel fitters on
9070 * ivb/hsw (since we don't use the higher upscaling modes which
9071 * differentiates them) so just WARN about this case for now. */
9072 if (IS_GEN7(dev)) {
9073 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9074 PF_PIPE_SEL_IVB(crtc->pipe));
9075 }
9076 }
9077 }
9078
9079 static void
9080 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9081 struct intel_initial_plane_config *plane_config)
9082 {
9083 struct drm_device *dev = crtc->base.dev;
9084 struct drm_i915_private *dev_priv = dev->dev_private;
9085 u32 val, base, offset;
9086 int pipe = crtc->pipe;
9087 int fourcc, pixel_format;
9088 unsigned int aligned_height;
9089 struct drm_framebuffer *fb;
9090 struct intel_framebuffer *intel_fb;
9091
9092 val = I915_READ(DSPCNTR(pipe));
9093 if (!(val & DISPLAY_PLANE_ENABLE))
9094 return;
9095
9096 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9097 if (!intel_fb) {
9098 DRM_DEBUG_KMS("failed to alloc fb\n");
9099 return;
9100 }
9101
9102 fb = &intel_fb->base;
9103
9104 if (INTEL_INFO(dev)->gen >= 4) {
9105 if (val & DISPPLANE_TILED) {
9106 plane_config->tiling = I915_TILING_X;
9107 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9108 }
9109 }
9110
9111 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9112 fourcc = i9xx_format_to_fourcc(pixel_format);
9113 fb->pixel_format = fourcc;
9114 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9115
9116 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9117 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9118 offset = I915_READ(DSPOFFSET(pipe));
9119 } else {
9120 if (plane_config->tiling)
9121 offset = I915_READ(DSPTILEOFF(pipe));
9122 else
9123 offset = I915_READ(DSPLINOFF(pipe));
9124 }
9125 plane_config->base = base;
9126
9127 val = I915_READ(PIPESRC(pipe));
9128 fb->width = ((val >> 16) & 0xfff) + 1;
9129 fb->height = ((val >> 0) & 0xfff) + 1;
9130
9131 val = I915_READ(DSPSTRIDE(pipe));
9132 fb->pitches[0] = val & 0xffffffc0;
9133
9134 aligned_height = intel_fb_align_height(dev, fb->height,
9135 fb->pixel_format,
9136 fb->modifier[0]);
9137
9138 plane_config->size = fb->pitches[0] * aligned_height;
9139
9140 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9141 pipe_name(pipe), fb->width, fb->height,
9142 fb->bits_per_pixel, base, fb->pitches[0],
9143 plane_config->size);
9144
9145 plane_config->fb = intel_fb;
9146 }
9147
9148 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9149 struct intel_crtc_state *pipe_config)
9150 {
9151 struct drm_device *dev = crtc->base.dev;
9152 struct drm_i915_private *dev_priv = dev->dev_private;
9153 uint32_t tmp;
9154
9155 if (!intel_display_power_is_enabled(dev_priv,
9156 POWER_DOMAIN_PIPE(crtc->pipe)))
9157 return false;
9158
9159 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9160 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9161
9162 tmp = I915_READ(PIPECONF(crtc->pipe));
9163 if (!(tmp & PIPECONF_ENABLE))
9164 return false;
9165
9166 switch (tmp & PIPECONF_BPC_MASK) {
9167 case PIPECONF_6BPC:
9168 pipe_config->pipe_bpp = 18;
9169 break;
9170 case PIPECONF_8BPC:
9171 pipe_config->pipe_bpp = 24;
9172 break;
9173 case PIPECONF_10BPC:
9174 pipe_config->pipe_bpp = 30;
9175 break;
9176 case PIPECONF_12BPC:
9177 pipe_config->pipe_bpp = 36;
9178 break;
9179 default:
9180 break;
9181 }
9182
9183 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9184 pipe_config->limited_color_range = true;
9185
9186 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9187 struct intel_shared_dpll *pll;
9188
9189 pipe_config->has_pch_encoder = true;
9190
9191 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9192 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9193 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9194
9195 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9196
9197 if (HAS_PCH_IBX(dev_priv->dev)) {
9198 pipe_config->shared_dpll =
9199 (enum intel_dpll_id) crtc->pipe;
9200 } else {
9201 tmp = I915_READ(PCH_DPLL_SEL);
9202 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9203 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9204 else
9205 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9206 }
9207
9208 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9209
9210 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9211 &pipe_config->dpll_hw_state));
9212
9213 tmp = pipe_config->dpll_hw_state.dpll;
9214 pipe_config->pixel_multiplier =
9215 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9216 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9217
9218 ironlake_pch_clock_get(crtc, pipe_config);
9219 } else {
9220 pipe_config->pixel_multiplier = 1;
9221 }
9222
9223 intel_get_pipe_timings(crtc, pipe_config);
9224
9225 ironlake_get_pfit_config(crtc, pipe_config);
9226
9227 return true;
9228 }
9229
9230 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9231 {
9232 struct drm_device *dev = dev_priv->dev;
9233 struct intel_crtc *crtc;
9234
9235 for_each_intel_crtc(dev, crtc)
9236 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9237 pipe_name(crtc->pipe));
9238
9239 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9240 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9241 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9242 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9243 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9244 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9245 "CPU PWM1 enabled\n");
9246 if (IS_HASWELL(dev))
9247 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9248 "CPU PWM2 enabled\n");
9249 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9250 "PCH PWM1 enabled\n");
9251 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9252 "Utility pin enabled\n");
9253 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9254
9255 /*
9256 * In theory we can still leave IRQs enabled, as long as only the HPD
9257 * interrupts remain enabled. We used to check for that, but since it's
9258 * gen-specific and since we only disable LCPLL after we fully disable
9259 * the interrupts, the check below should be enough.
9260 */
9261 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9262 }
9263
9264 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9265 {
9266 struct drm_device *dev = dev_priv->dev;
9267
9268 if (IS_HASWELL(dev))
9269 return I915_READ(D_COMP_HSW);
9270 else
9271 return I915_READ(D_COMP_BDW);
9272 }
9273
9274 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9275 {
9276 struct drm_device *dev = dev_priv->dev;
9277
9278 if (IS_HASWELL(dev)) {
9279 mutex_lock(&dev_priv->rps.hw_lock);
9280 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9281 val))
9282 DRM_ERROR("Failed to write to D_COMP\n");
9283 mutex_unlock(&dev_priv->rps.hw_lock);
9284 } else {
9285 I915_WRITE(D_COMP_BDW, val);
9286 POSTING_READ(D_COMP_BDW);
9287 }
9288 }
9289
9290 /*
9291 * This function implements pieces of two sequences from BSpec:
9292 * - Sequence for display software to disable LCPLL
9293 * - Sequence for display software to allow package C8+
9294 * The steps implemented here are just the steps that actually touch the LCPLL
9295 * register. Callers should take care of disabling all the display engine
9296 * functions, doing the mode unset, fixing interrupts, etc.
9297 */
9298 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9299 bool switch_to_fclk, bool allow_power_down)
9300 {
9301 uint32_t val;
9302
9303 assert_can_disable_lcpll(dev_priv);
9304
9305 val = I915_READ(LCPLL_CTL);
9306
9307 if (switch_to_fclk) {
9308 val |= LCPLL_CD_SOURCE_FCLK;
9309 I915_WRITE(LCPLL_CTL, val);
9310
9311 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9312 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9313 DRM_ERROR("Switching to FCLK failed\n");
9314
9315 val = I915_READ(LCPLL_CTL);
9316 }
9317
9318 val |= LCPLL_PLL_DISABLE;
9319 I915_WRITE(LCPLL_CTL, val);
9320 POSTING_READ(LCPLL_CTL);
9321
9322 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9323 DRM_ERROR("LCPLL still locked\n");
9324
9325 val = hsw_read_dcomp(dev_priv);
9326 val |= D_COMP_COMP_DISABLE;
9327 hsw_write_dcomp(dev_priv, val);
9328 ndelay(100);
9329
9330 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9331 1))
9332 DRM_ERROR("D_COMP RCOMP still in progress\n");
9333
9334 if (allow_power_down) {
9335 val = I915_READ(LCPLL_CTL);
9336 val |= LCPLL_POWER_DOWN_ALLOW;
9337 I915_WRITE(LCPLL_CTL, val);
9338 POSTING_READ(LCPLL_CTL);
9339 }
9340 }
9341
9342 /*
9343 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9344 * source.
9345 */
9346 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9347 {
9348 uint32_t val;
9349
9350 val = I915_READ(LCPLL_CTL);
9351
9352 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9353 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9354 return;
9355
9356 /*
9357 * Make sure we're not on PC8 state before disabling PC8, otherwise
9358 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9359 */
9360 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9361
9362 if (val & LCPLL_POWER_DOWN_ALLOW) {
9363 val &= ~LCPLL_POWER_DOWN_ALLOW;
9364 I915_WRITE(LCPLL_CTL, val);
9365 POSTING_READ(LCPLL_CTL);
9366 }
9367
9368 val = hsw_read_dcomp(dev_priv);
9369 val |= D_COMP_COMP_FORCE;
9370 val &= ~D_COMP_COMP_DISABLE;
9371 hsw_write_dcomp(dev_priv, val);
9372
9373 val = I915_READ(LCPLL_CTL);
9374 val &= ~LCPLL_PLL_DISABLE;
9375 I915_WRITE(LCPLL_CTL, val);
9376
9377 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9378 DRM_ERROR("LCPLL not locked yet\n");
9379
9380 if (val & LCPLL_CD_SOURCE_FCLK) {
9381 val = I915_READ(LCPLL_CTL);
9382 val &= ~LCPLL_CD_SOURCE_FCLK;
9383 I915_WRITE(LCPLL_CTL, val);
9384
9385 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9386 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9387 DRM_ERROR("Switching back to LCPLL failed\n");
9388 }
9389
9390 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9391 intel_update_cdclk(dev_priv->dev);
9392 }
9393
9394 /*
9395 * Package states C8 and deeper are really deep PC states that can only be
9396 * reached when all the devices on the system allow it, so even if the graphics
9397 * device allows PC8+, it doesn't mean the system will actually get to these
9398 * states. Our driver only allows PC8+ when going into runtime PM.
9399 *
9400 * The requirements for PC8+ are that all the outputs are disabled, the power
9401 * well is disabled and most interrupts are disabled, and these are also
9402 * requirements for runtime PM. When these conditions are met, we manually do
9403 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9404 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9405 * hang the machine.
9406 *
9407 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9408 * the state of some registers, so when we come back from PC8+ we need to
9409 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9410 * need to take care of the registers kept by RC6. Notice that this happens even
9411 * if we don't put the device in PCI D3 state (which is what currently happens
9412 * because of the runtime PM support).
9413 *
9414 * For more, read "Display Sequences for Package C8" on the hardware
9415 * documentation.
9416 */
9417 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9418 {
9419 struct drm_device *dev = dev_priv->dev;
9420 uint32_t val;
9421
9422 DRM_DEBUG_KMS("Enabling package C8+\n");
9423
9424 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9425 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9426 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9427 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9428 }
9429
9430 lpt_disable_clkout_dp(dev);
9431 hsw_disable_lcpll(dev_priv, true, true);
9432 }
9433
9434 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9435 {
9436 struct drm_device *dev = dev_priv->dev;
9437 uint32_t val;
9438
9439 DRM_DEBUG_KMS("Disabling package C8+\n");
9440
9441 hsw_restore_lcpll(dev_priv);
9442 lpt_init_pch_refclk(dev);
9443
9444 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9445 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9446 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9447 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9448 }
9449
9450 intel_prepare_ddi(dev);
9451 }
9452
9453 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9454 {
9455 struct drm_device *dev = old_state->dev;
9456 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9457
9458 broxton_set_cdclk(dev, req_cdclk);
9459 }
9460
9461 /* compute the max rate for new configuration */
9462 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9463 {
9464 struct intel_crtc *intel_crtc;
9465 struct intel_crtc_state *crtc_state;
9466 int max_pixel_rate = 0;
9467
9468 for_each_intel_crtc(state->dev, intel_crtc) {
9469 int pixel_rate;
9470
9471 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9472 if (IS_ERR(crtc_state))
9473 return PTR_ERR(crtc_state);
9474
9475 if (!crtc_state->base.enable)
9476 continue;
9477
9478 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9479
9480 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9481 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9482 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9483
9484 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9485 }
9486
9487 return max_pixel_rate;
9488 }
9489
9490 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9491 {
9492 struct drm_i915_private *dev_priv = dev->dev_private;
9493 uint32_t val, data;
9494 int ret;
9495
9496 if (WARN((I915_READ(LCPLL_CTL) &
9497 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9498 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9499 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9500 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9501 "trying to change cdclk frequency with cdclk not enabled\n"))
9502 return;
9503
9504 mutex_lock(&dev_priv->rps.hw_lock);
9505 ret = sandybridge_pcode_write(dev_priv,
9506 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9507 mutex_unlock(&dev_priv->rps.hw_lock);
9508 if (ret) {
9509 DRM_ERROR("failed to inform pcode about cdclk change\n");
9510 return;
9511 }
9512
9513 val = I915_READ(LCPLL_CTL);
9514 val |= LCPLL_CD_SOURCE_FCLK;
9515 I915_WRITE(LCPLL_CTL, val);
9516
9517 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9518 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9519 DRM_ERROR("Switching to FCLK failed\n");
9520
9521 val = I915_READ(LCPLL_CTL);
9522 val &= ~LCPLL_CLK_FREQ_MASK;
9523
9524 switch (cdclk) {
9525 case 450000:
9526 val |= LCPLL_CLK_FREQ_450;
9527 data = 0;
9528 break;
9529 case 540000:
9530 val |= LCPLL_CLK_FREQ_54O_BDW;
9531 data = 1;
9532 break;
9533 case 337500:
9534 val |= LCPLL_CLK_FREQ_337_5_BDW;
9535 data = 2;
9536 break;
9537 case 675000:
9538 val |= LCPLL_CLK_FREQ_675_BDW;
9539 data = 3;
9540 break;
9541 default:
9542 WARN(1, "invalid cdclk frequency\n");
9543 return;
9544 }
9545
9546 I915_WRITE(LCPLL_CTL, val);
9547
9548 val = I915_READ(LCPLL_CTL);
9549 val &= ~LCPLL_CD_SOURCE_FCLK;
9550 I915_WRITE(LCPLL_CTL, val);
9551
9552 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9553 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9554 DRM_ERROR("Switching back to LCPLL failed\n");
9555
9556 mutex_lock(&dev_priv->rps.hw_lock);
9557 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9558 mutex_unlock(&dev_priv->rps.hw_lock);
9559
9560 intel_update_cdclk(dev);
9561
9562 WARN(cdclk != dev_priv->cdclk_freq,
9563 "cdclk requested %d kHz but got %d kHz\n",
9564 cdclk, dev_priv->cdclk_freq);
9565 }
9566
9567 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9568 {
9569 struct drm_i915_private *dev_priv = to_i915(state->dev);
9570 int max_pixclk = ilk_max_pixel_rate(state);
9571 int cdclk;
9572
9573 /*
9574 * FIXME should also account for plane ratio
9575 * once 64bpp pixel formats are supported.
9576 */
9577 if (max_pixclk > 540000)
9578 cdclk = 675000;
9579 else if (max_pixclk > 450000)
9580 cdclk = 540000;
9581 else if (max_pixclk > 337500)
9582 cdclk = 450000;
9583 else
9584 cdclk = 337500;
9585
9586 /*
9587 * FIXME move the cdclk caclulation to
9588 * compute_config() so we can fail gracegully.
9589 */
9590 if (cdclk > dev_priv->max_cdclk_freq) {
9591 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9592 cdclk, dev_priv->max_cdclk_freq);
9593 cdclk = dev_priv->max_cdclk_freq;
9594 }
9595
9596 to_intel_atomic_state(state)->cdclk = cdclk;
9597
9598 return 0;
9599 }
9600
9601 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9602 {
9603 struct drm_device *dev = old_state->dev;
9604 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9605
9606 broadwell_set_cdclk(dev, req_cdclk);
9607 }
9608
9609 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9610 struct intel_crtc_state *crtc_state)
9611 {
9612 if (!intel_ddi_pll_select(crtc, crtc_state))
9613 return -EINVAL;
9614
9615 crtc->lowfreq_avail = false;
9616
9617 return 0;
9618 }
9619
9620 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9621 enum port port,
9622 struct intel_crtc_state *pipe_config)
9623 {
9624 switch (port) {
9625 case PORT_A:
9626 pipe_config->ddi_pll_sel = SKL_DPLL0;
9627 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9628 break;
9629 case PORT_B:
9630 pipe_config->ddi_pll_sel = SKL_DPLL1;
9631 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9632 break;
9633 case PORT_C:
9634 pipe_config->ddi_pll_sel = SKL_DPLL2;
9635 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9636 break;
9637 default:
9638 DRM_ERROR("Incorrect port type\n");
9639 }
9640 }
9641
9642 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9643 enum port port,
9644 struct intel_crtc_state *pipe_config)
9645 {
9646 u32 temp, dpll_ctl1;
9647
9648 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9649 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9650
9651 switch (pipe_config->ddi_pll_sel) {
9652 case SKL_DPLL0:
9653 /*
9654 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9655 * of the shared DPLL framework and thus needs to be read out
9656 * separately
9657 */
9658 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9659 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9660 break;
9661 case SKL_DPLL1:
9662 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9663 break;
9664 case SKL_DPLL2:
9665 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9666 break;
9667 case SKL_DPLL3:
9668 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9669 break;
9670 }
9671 }
9672
9673 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9674 enum port port,
9675 struct intel_crtc_state *pipe_config)
9676 {
9677 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9678
9679 switch (pipe_config->ddi_pll_sel) {
9680 case PORT_CLK_SEL_WRPLL1:
9681 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9682 break;
9683 case PORT_CLK_SEL_WRPLL2:
9684 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9685 break;
9686 }
9687 }
9688
9689 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9690 struct intel_crtc_state *pipe_config)
9691 {
9692 struct drm_device *dev = crtc->base.dev;
9693 struct drm_i915_private *dev_priv = dev->dev_private;
9694 struct intel_shared_dpll *pll;
9695 enum port port;
9696 uint32_t tmp;
9697
9698 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9699
9700 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9701
9702 if (IS_SKYLAKE(dev))
9703 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9704 else if (IS_BROXTON(dev))
9705 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9706 else
9707 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9708
9709 if (pipe_config->shared_dpll >= 0) {
9710 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9711
9712 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9713 &pipe_config->dpll_hw_state));
9714 }
9715
9716 /*
9717 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9718 * DDI E. So just check whether this pipe is wired to DDI E and whether
9719 * the PCH transcoder is on.
9720 */
9721 if (INTEL_INFO(dev)->gen < 9 &&
9722 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9723 pipe_config->has_pch_encoder = true;
9724
9725 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9726 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9727 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9728
9729 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9730 }
9731 }
9732
9733 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9734 struct intel_crtc_state *pipe_config)
9735 {
9736 struct drm_device *dev = crtc->base.dev;
9737 struct drm_i915_private *dev_priv = dev->dev_private;
9738 enum intel_display_power_domain pfit_domain;
9739 uint32_t tmp;
9740
9741 if (!intel_display_power_is_enabled(dev_priv,
9742 POWER_DOMAIN_PIPE(crtc->pipe)))
9743 return false;
9744
9745 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9746 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9747
9748 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9749 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9750 enum pipe trans_edp_pipe;
9751 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9752 default:
9753 WARN(1, "unknown pipe linked to edp transcoder\n");
9754 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9755 case TRANS_DDI_EDP_INPUT_A_ON:
9756 trans_edp_pipe = PIPE_A;
9757 break;
9758 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9759 trans_edp_pipe = PIPE_B;
9760 break;
9761 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9762 trans_edp_pipe = PIPE_C;
9763 break;
9764 }
9765
9766 if (trans_edp_pipe == crtc->pipe)
9767 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9768 }
9769
9770 if (!intel_display_power_is_enabled(dev_priv,
9771 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9772 return false;
9773
9774 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9775 if (!(tmp & PIPECONF_ENABLE))
9776 return false;
9777
9778 haswell_get_ddi_port_state(crtc, pipe_config);
9779
9780 intel_get_pipe_timings(crtc, pipe_config);
9781
9782 if (INTEL_INFO(dev)->gen >= 9) {
9783 skl_init_scalers(dev, crtc, pipe_config);
9784 }
9785
9786 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9787
9788 if (INTEL_INFO(dev)->gen >= 9) {
9789 pipe_config->scaler_state.scaler_id = -1;
9790 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9791 }
9792
9793 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9794 if (INTEL_INFO(dev)->gen == 9)
9795 skylake_get_pfit_config(crtc, pipe_config);
9796 else if (INTEL_INFO(dev)->gen < 9)
9797 ironlake_get_pfit_config(crtc, pipe_config);
9798 else
9799 MISSING_CASE(INTEL_INFO(dev)->gen);
9800 }
9801
9802 if (IS_HASWELL(dev))
9803 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9804 (I915_READ(IPS_CTL) & IPS_ENABLE);
9805
9806 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9807 pipe_config->pixel_multiplier =
9808 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9809 } else {
9810 pipe_config->pixel_multiplier = 1;
9811 }
9812
9813 return true;
9814 }
9815
9816 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9817 {
9818 struct drm_device *dev = crtc->dev;
9819 struct drm_i915_private *dev_priv = dev->dev_private;
9820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9821 uint32_t cntl = 0, size = 0;
9822
9823 if (base) {
9824 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9825 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9826 unsigned int stride = roundup_pow_of_two(width) * 4;
9827
9828 switch (stride) {
9829 default:
9830 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9831 width, stride);
9832 stride = 256;
9833 /* fallthrough */
9834 case 256:
9835 case 512:
9836 case 1024:
9837 case 2048:
9838 break;
9839 }
9840
9841 cntl |= CURSOR_ENABLE |
9842 CURSOR_GAMMA_ENABLE |
9843 CURSOR_FORMAT_ARGB |
9844 CURSOR_STRIDE(stride);
9845
9846 size = (height << 12) | width;
9847 }
9848
9849 if (intel_crtc->cursor_cntl != 0 &&
9850 (intel_crtc->cursor_base != base ||
9851 intel_crtc->cursor_size != size ||
9852 intel_crtc->cursor_cntl != cntl)) {
9853 /* On these chipsets we can only modify the base/size/stride
9854 * whilst the cursor is disabled.
9855 */
9856 I915_WRITE(_CURACNTR, 0);
9857 POSTING_READ(_CURACNTR);
9858 intel_crtc->cursor_cntl = 0;
9859 }
9860
9861 if (intel_crtc->cursor_base != base) {
9862 I915_WRITE(_CURABASE, base);
9863 intel_crtc->cursor_base = base;
9864 }
9865
9866 if (intel_crtc->cursor_size != size) {
9867 I915_WRITE(CURSIZE, size);
9868 intel_crtc->cursor_size = size;
9869 }
9870
9871 if (intel_crtc->cursor_cntl != cntl) {
9872 I915_WRITE(_CURACNTR, cntl);
9873 POSTING_READ(_CURACNTR);
9874 intel_crtc->cursor_cntl = cntl;
9875 }
9876 }
9877
9878 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9879 {
9880 struct drm_device *dev = crtc->dev;
9881 struct drm_i915_private *dev_priv = dev->dev_private;
9882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9883 int pipe = intel_crtc->pipe;
9884 uint32_t cntl;
9885
9886 cntl = 0;
9887 if (base) {
9888 cntl = MCURSOR_GAMMA_ENABLE;
9889 switch (intel_crtc->base.cursor->state->crtc_w) {
9890 case 64:
9891 cntl |= CURSOR_MODE_64_ARGB_AX;
9892 break;
9893 case 128:
9894 cntl |= CURSOR_MODE_128_ARGB_AX;
9895 break;
9896 case 256:
9897 cntl |= CURSOR_MODE_256_ARGB_AX;
9898 break;
9899 default:
9900 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9901 return;
9902 }
9903 cntl |= pipe << 28; /* Connect to correct pipe */
9904
9905 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9906 cntl |= CURSOR_PIPE_CSC_ENABLE;
9907 }
9908
9909 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9910 cntl |= CURSOR_ROTATE_180;
9911
9912 if (intel_crtc->cursor_cntl != cntl) {
9913 I915_WRITE(CURCNTR(pipe), cntl);
9914 POSTING_READ(CURCNTR(pipe));
9915 intel_crtc->cursor_cntl = cntl;
9916 }
9917
9918 /* and commit changes on next vblank */
9919 I915_WRITE(CURBASE(pipe), base);
9920 POSTING_READ(CURBASE(pipe));
9921
9922 intel_crtc->cursor_base = base;
9923 }
9924
9925 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9926 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9927 bool on)
9928 {
9929 struct drm_device *dev = crtc->dev;
9930 struct drm_i915_private *dev_priv = dev->dev_private;
9931 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9932 int pipe = intel_crtc->pipe;
9933 int x = crtc->cursor_x;
9934 int y = crtc->cursor_y;
9935 u32 base = 0, pos = 0;
9936
9937 if (on)
9938 base = intel_crtc->cursor_addr;
9939
9940 if (x >= intel_crtc->config->pipe_src_w)
9941 base = 0;
9942
9943 if (y >= intel_crtc->config->pipe_src_h)
9944 base = 0;
9945
9946 if (x < 0) {
9947 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9948 base = 0;
9949
9950 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9951 x = -x;
9952 }
9953 pos |= x << CURSOR_X_SHIFT;
9954
9955 if (y < 0) {
9956 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9957 base = 0;
9958
9959 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9960 y = -y;
9961 }
9962 pos |= y << CURSOR_Y_SHIFT;
9963
9964 if (base == 0 && intel_crtc->cursor_base == 0)
9965 return;
9966
9967 I915_WRITE(CURPOS(pipe), pos);
9968
9969 /* ILK+ do this automagically */
9970 if (HAS_GMCH_DISPLAY(dev) &&
9971 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9972 base += (intel_crtc->base.cursor->state->crtc_h *
9973 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9974 }
9975
9976 if (IS_845G(dev) || IS_I865G(dev))
9977 i845_update_cursor(crtc, base);
9978 else
9979 i9xx_update_cursor(crtc, base);
9980 }
9981
9982 static bool cursor_size_ok(struct drm_device *dev,
9983 uint32_t width, uint32_t height)
9984 {
9985 if (width == 0 || height == 0)
9986 return false;
9987
9988 /*
9989 * 845g/865g are special in that they are only limited by
9990 * the width of their cursors, the height is arbitrary up to
9991 * the precision of the register. Everything else requires
9992 * square cursors, limited to a few power-of-two sizes.
9993 */
9994 if (IS_845G(dev) || IS_I865G(dev)) {
9995 if ((width & 63) != 0)
9996 return false;
9997
9998 if (width > (IS_845G(dev) ? 64 : 512))
9999 return false;
10000
10001 if (height > 1023)
10002 return false;
10003 } else {
10004 switch (width | height) {
10005 case 256:
10006 case 128:
10007 if (IS_GEN2(dev))
10008 return false;
10009 case 64:
10010 break;
10011 default:
10012 return false;
10013 }
10014 }
10015
10016 return true;
10017 }
10018
10019 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10020 u16 *blue, uint32_t start, uint32_t size)
10021 {
10022 int end = (start + size > 256) ? 256 : start + size, i;
10023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10024
10025 for (i = start; i < end; i++) {
10026 intel_crtc->lut_r[i] = red[i] >> 8;
10027 intel_crtc->lut_g[i] = green[i] >> 8;
10028 intel_crtc->lut_b[i] = blue[i] >> 8;
10029 }
10030
10031 intel_crtc_load_lut(crtc);
10032 }
10033
10034 /* VESA 640x480x72Hz mode to set on the pipe */
10035 static struct drm_display_mode load_detect_mode = {
10036 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10037 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10038 };
10039
10040 struct drm_framebuffer *
10041 __intel_framebuffer_create(struct drm_device *dev,
10042 struct drm_mode_fb_cmd2 *mode_cmd,
10043 struct drm_i915_gem_object *obj)
10044 {
10045 struct intel_framebuffer *intel_fb;
10046 int ret;
10047
10048 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10049 if (!intel_fb) {
10050 drm_gem_object_unreference(&obj->base);
10051 return ERR_PTR(-ENOMEM);
10052 }
10053
10054 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10055 if (ret)
10056 goto err;
10057
10058 return &intel_fb->base;
10059 err:
10060 drm_gem_object_unreference(&obj->base);
10061 kfree(intel_fb);
10062
10063 return ERR_PTR(ret);
10064 }
10065
10066 static struct drm_framebuffer *
10067 intel_framebuffer_create(struct drm_device *dev,
10068 struct drm_mode_fb_cmd2 *mode_cmd,
10069 struct drm_i915_gem_object *obj)
10070 {
10071 struct drm_framebuffer *fb;
10072 int ret;
10073
10074 ret = i915_mutex_lock_interruptible(dev);
10075 if (ret)
10076 return ERR_PTR(ret);
10077 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10078 mutex_unlock(&dev->struct_mutex);
10079
10080 return fb;
10081 }
10082
10083 static u32
10084 intel_framebuffer_pitch_for_width(int width, int bpp)
10085 {
10086 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10087 return ALIGN(pitch, 64);
10088 }
10089
10090 static u32
10091 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10092 {
10093 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10094 return PAGE_ALIGN(pitch * mode->vdisplay);
10095 }
10096
10097 static struct drm_framebuffer *
10098 intel_framebuffer_create_for_mode(struct drm_device *dev,
10099 struct drm_display_mode *mode,
10100 int depth, int bpp)
10101 {
10102 struct drm_i915_gem_object *obj;
10103 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10104
10105 obj = i915_gem_alloc_object(dev,
10106 intel_framebuffer_size_for_mode(mode, bpp));
10107 if (obj == NULL)
10108 return ERR_PTR(-ENOMEM);
10109
10110 mode_cmd.width = mode->hdisplay;
10111 mode_cmd.height = mode->vdisplay;
10112 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10113 bpp);
10114 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10115
10116 return intel_framebuffer_create(dev, &mode_cmd, obj);
10117 }
10118
10119 static struct drm_framebuffer *
10120 mode_fits_in_fbdev(struct drm_device *dev,
10121 struct drm_display_mode *mode)
10122 {
10123 #ifdef CONFIG_DRM_I915_FBDEV
10124 struct drm_i915_private *dev_priv = dev->dev_private;
10125 struct drm_i915_gem_object *obj;
10126 struct drm_framebuffer *fb;
10127
10128 if (!dev_priv->fbdev)
10129 return NULL;
10130
10131 if (!dev_priv->fbdev->fb)
10132 return NULL;
10133
10134 obj = dev_priv->fbdev->fb->obj;
10135 BUG_ON(!obj);
10136
10137 fb = &dev_priv->fbdev->fb->base;
10138 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10139 fb->bits_per_pixel))
10140 return NULL;
10141
10142 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10143 return NULL;
10144
10145 return fb;
10146 #else
10147 return NULL;
10148 #endif
10149 }
10150
10151 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10152 struct drm_crtc *crtc,
10153 struct drm_display_mode *mode,
10154 struct drm_framebuffer *fb,
10155 int x, int y)
10156 {
10157 struct drm_plane_state *plane_state;
10158 int hdisplay, vdisplay;
10159 int ret;
10160
10161 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10162 if (IS_ERR(plane_state))
10163 return PTR_ERR(plane_state);
10164
10165 if (mode)
10166 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10167 else
10168 hdisplay = vdisplay = 0;
10169
10170 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10171 if (ret)
10172 return ret;
10173 drm_atomic_set_fb_for_plane(plane_state, fb);
10174 plane_state->crtc_x = 0;
10175 plane_state->crtc_y = 0;
10176 plane_state->crtc_w = hdisplay;
10177 plane_state->crtc_h = vdisplay;
10178 plane_state->src_x = x << 16;
10179 plane_state->src_y = y << 16;
10180 plane_state->src_w = hdisplay << 16;
10181 plane_state->src_h = vdisplay << 16;
10182
10183 return 0;
10184 }
10185
10186 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10187 struct drm_display_mode *mode,
10188 struct intel_load_detect_pipe *old,
10189 struct drm_modeset_acquire_ctx *ctx)
10190 {
10191 struct intel_crtc *intel_crtc;
10192 struct intel_encoder *intel_encoder =
10193 intel_attached_encoder(connector);
10194 struct drm_crtc *possible_crtc;
10195 struct drm_encoder *encoder = &intel_encoder->base;
10196 struct drm_crtc *crtc = NULL;
10197 struct drm_device *dev = encoder->dev;
10198 struct drm_framebuffer *fb;
10199 struct drm_mode_config *config = &dev->mode_config;
10200 struct drm_atomic_state *state = NULL;
10201 struct drm_connector_state *connector_state;
10202 struct intel_crtc_state *crtc_state;
10203 int ret, i = -1;
10204
10205 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10206 connector->base.id, connector->name,
10207 encoder->base.id, encoder->name);
10208
10209 retry:
10210 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10211 if (ret)
10212 goto fail;
10213
10214 /*
10215 * Algorithm gets a little messy:
10216 *
10217 * - if the connector already has an assigned crtc, use it (but make
10218 * sure it's on first)
10219 *
10220 * - try to find the first unused crtc that can drive this connector,
10221 * and use that if we find one
10222 */
10223
10224 /* See if we already have a CRTC for this connector */
10225 if (encoder->crtc) {
10226 crtc = encoder->crtc;
10227
10228 ret = drm_modeset_lock(&crtc->mutex, ctx);
10229 if (ret)
10230 goto fail;
10231 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10232 if (ret)
10233 goto fail;
10234
10235 old->dpms_mode = connector->dpms;
10236 old->load_detect_temp = false;
10237
10238 /* Make sure the crtc and connector are running */
10239 if (connector->dpms != DRM_MODE_DPMS_ON)
10240 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10241
10242 return true;
10243 }
10244
10245 /* Find an unused one (if possible) */
10246 for_each_crtc(dev, possible_crtc) {
10247 i++;
10248 if (!(encoder->possible_crtcs & (1 << i)))
10249 continue;
10250 if (possible_crtc->state->enable)
10251 continue;
10252
10253 crtc = possible_crtc;
10254 break;
10255 }
10256
10257 /*
10258 * If we didn't find an unused CRTC, don't use any.
10259 */
10260 if (!crtc) {
10261 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10262 goto fail;
10263 }
10264
10265 ret = drm_modeset_lock(&crtc->mutex, ctx);
10266 if (ret)
10267 goto fail;
10268 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10269 if (ret)
10270 goto fail;
10271
10272 intel_crtc = to_intel_crtc(crtc);
10273 old->dpms_mode = connector->dpms;
10274 old->load_detect_temp = true;
10275 old->release_fb = NULL;
10276
10277 state = drm_atomic_state_alloc(dev);
10278 if (!state)
10279 return false;
10280
10281 state->acquire_ctx = ctx;
10282
10283 connector_state = drm_atomic_get_connector_state(state, connector);
10284 if (IS_ERR(connector_state)) {
10285 ret = PTR_ERR(connector_state);
10286 goto fail;
10287 }
10288
10289 connector_state->crtc = crtc;
10290 connector_state->best_encoder = &intel_encoder->base;
10291
10292 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10293 if (IS_ERR(crtc_state)) {
10294 ret = PTR_ERR(crtc_state);
10295 goto fail;
10296 }
10297
10298 crtc_state->base.active = crtc_state->base.enable = true;
10299
10300 if (!mode)
10301 mode = &load_detect_mode;
10302
10303 /* We need a framebuffer large enough to accommodate all accesses
10304 * that the plane may generate whilst we perform load detection.
10305 * We can not rely on the fbcon either being present (we get called
10306 * during its initialisation to detect all boot displays, or it may
10307 * not even exist) or that it is large enough to satisfy the
10308 * requested mode.
10309 */
10310 fb = mode_fits_in_fbdev(dev, mode);
10311 if (fb == NULL) {
10312 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10313 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10314 old->release_fb = fb;
10315 } else
10316 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10317 if (IS_ERR(fb)) {
10318 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10319 goto fail;
10320 }
10321
10322 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10323 if (ret)
10324 goto fail;
10325
10326 drm_mode_copy(&crtc_state->base.mode, mode);
10327
10328 if (drm_atomic_commit(state)) {
10329 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10330 if (old->release_fb)
10331 old->release_fb->funcs->destroy(old->release_fb);
10332 goto fail;
10333 }
10334 crtc->primary->crtc = crtc;
10335
10336 /* let the connector get through one full cycle before testing */
10337 intel_wait_for_vblank(dev, intel_crtc->pipe);
10338 return true;
10339
10340 fail:
10341 drm_atomic_state_free(state);
10342 state = NULL;
10343
10344 if (ret == -EDEADLK) {
10345 drm_modeset_backoff(ctx);
10346 goto retry;
10347 }
10348
10349 return false;
10350 }
10351
10352 void intel_release_load_detect_pipe(struct drm_connector *connector,
10353 struct intel_load_detect_pipe *old,
10354 struct drm_modeset_acquire_ctx *ctx)
10355 {
10356 struct drm_device *dev = connector->dev;
10357 struct intel_encoder *intel_encoder =
10358 intel_attached_encoder(connector);
10359 struct drm_encoder *encoder = &intel_encoder->base;
10360 struct drm_crtc *crtc = encoder->crtc;
10361 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10362 struct drm_atomic_state *state;
10363 struct drm_connector_state *connector_state;
10364 struct intel_crtc_state *crtc_state;
10365 int ret;
10366
10367 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10368 connector->base.id, connector->name,
10369 encoder->base.id, encoder->name);
10370
10371 if (old->load_detect_temp) {
10372 state = drm_atomic_state_alloc(dev);
10373 if (!state)
10374 goto fail;
10375
10376 state->acquire_ctx = ctx;
10377
10378 connector_state = drm_atomic_get_connector_state(state, connector);
10379 if (IS_ERR(connector_state))
10380 goto fail;
10381
10382 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10383 if (IS_ERR(crtc_state))
10384 goto fail;
10385
10386 connector_state->best_encoder = NULL;
10387 connector_state->crtc = NULL;
10388
10389 crtc_state->base.enable = crtc_state->base.active = false;
10390
10391 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10392 0, 0);
10393 if (ret)
10394 goto fail;
10395
10396 ret = drm_atomic_commit(state);
10397 if (ret)
10398 goto fail;
10399
10400 if (old->release_fb) {
10401 drm_framebuffer_unregister_private(old->release_fb);
10402 drm_framebuffer_unreference(old->release_fb);
10403 }
10404
10405 return;
10406 }
10407
10408 /* Switch crtc and encoder back off if necessary */
10409 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10410 connector->funcs->dpms(connector, old->dpms_mode);
10411
10412 return;
10413 fail:
10414 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10415 drm_atomic_state_free(state);
10416 }
10417
10418 static int i9xx_pll_refclk(struct drm_device *dev,
10419 const struct intel_crtc_state *pipe_config)
10420 {
10421 struct drm_i915_private *dev_priv = dev->dev_private;
10422 u32 dpll = pipe_config->dpll_hw_state.dpll;
10423
10424 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10425 return dev_priv->vbt.lvds_ssc_freq;
10426 else if (HAS_PCH_SPLIT(dev))
10427 return 120000;
10428 else if (!IS_GEN2(dev))
10429 return 96000;
10430 else
10431 return 48000;
10432 }
10433
10434 /* Returns the clock of the currently programmed mode of the given pipe. */
10435 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10436 struct intel_crtc_state *pipe_config)
10437 {
10438 struct drm_device *dev = crtc->base.dev;
10439 struct drm_i915_private *dev_priv = dev->dev_private;
10440 int pipe = pipe_config->cpu_transcoder;
10441 u32 dpll = pipe_config->dpll_hw_state.dpll;
10442 u32 fp;
10443 intel_clock_t clock;
10444 int port_clock;
10445 int refclk = i9xx_pll_refclk(dev, pipe_config);
10446
10447 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10448 fp = pipe_config->dpll_hw_state.fp0;
10449 else
10450 fp = pipe_config->dpll_hw_state.fp1;
10451
10452 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10453 if (IS_PINEVIEW(dev)) {
10454 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10455 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10456 } else {
10457 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10458 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10459 }
10460
10461 if (!IS_GEN2(dev)) {
10462 if (IS_PINEVIEW(dev))
10463 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10464 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10465 else
10466 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10467 DPLL_FPA01_P1_POST_DIV_SHIFT);
10468
10469 switch (dpll & DPLL_MODE_MASK) {
10470 case DPLLB_MODE_DAC_SERIAL:
10471 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10472 5 : 10;
10473 break;
10474 case DPLLB_MODE_LVDS:
10475 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10476 7 : 14;
10477 break;
10478 default:
10479 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10480 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10481 return;
10482 }
10483
10484 if (IS_PINEVIEW(dev))
10485 port_clock = pnv_calc_dpll_params(refclk, &clock);
10486 else
10487 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10488 } else {
10489 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10490 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10491
10492 if (is_lvds) {
10493 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10494 DPLL_FPA01_P1_POST_DIV_SHIFT);
10495
10496 if (lvds & LVDS_CLKB_POWER_UP)
10497 clock.p2 = 7;
10498 else
10499 clock.p2 = 14;
10500 } else {
10501 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10502 clock.p1 = 2;
10503 else {
10504 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10505 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10506 }
10507 if (dpll & PLL_P2_DIVIDE_BY_4)
10508 clock.p2 = 4;
10509 else
10510 clock.p2 = 2;
10511 }
10512
10513 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10514 }
10515
10516 /*
10517 * This value includes pixel_multiplier. We will use
10518 * port_clock to compute adjusted_mode.crtc_clock in the
10519 * encoder's get_config() function.
10520 */
10521 pipe_config->port_clock = port_clock;
10522 }
10523
10524 int intel_dotclock_calculate(int link_freq,
10525 const struct intel_link_m_n *m_n)
10526 {
10527 /*
10528 * The calculation for the data clock is:
10529 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10530 * But we want to avoid losing precison if possible, so:
10531 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10532 *
10533 * and the link clock is simpler:
10534 * link_clock = (m * link_clock) / n
10535 */
10536
10537 if (!m_n->link_n)
10538 return 0;
10539
10540 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10541 }
10542
10543 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10544 struct intel_crtc_state *pipe_config)
10545 {
10546 struct drm_device *dev = crtc->base.dev;
10547
10548 /* read out port_clock from the DPLL */
10549 i9xx_crtc_clock_get(crtc, pipe_config);
10550
10551 /*
10552 * This value does not include pixel_multiplier.
10553 * We will check that port_clock and adjusted_mode.crtc_clock
10554 * agree once we know their relationship in the encoder's
10555 * get_config() function.
10556 */
10557 pipe_config->base.adjusted_mode.crtc_clock =
10558 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10559 &pipe_config->fdi_m_n);
10560 }
10561
10562 /** Returns the currently programmed mode of the given pipe. */
10563 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10564 struct drm_crtc *crtc)
10565 {
10566 struct drm_i915_private *dev_priv = dev->dev_private;
10567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10568 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10569 struct drm_display_mode *mode;
10570 struct intel_crtc_state pipe_config;
10571 int htot = I915_READ(HTOTAL(cpu_transcoder));
10572 int hsync = I915_READ(HSYNC(cpu_transcoder));
10573 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10574 int vsync = I915_READ(VSYNC(cpu_transcoder));
10575 enum pipe pipe = intel_crtc->pipe;
10576
10577 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10578 if (!mode)
10579 return NULL;
10580
10581 /*
10582 * Construct a pipe_config sufficient for getting the clock info
10583 * back out of crtc_clock_get.
10584 *
10585 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10586 * to use a real value here instead.
10587 */
10588 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10589 pipe_config.pixel_multiplier = 1;
10590 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10591 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10592 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10593 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10594
10595 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10596 mode->hdisplay = (htot & 0xffff) + 1;
10597 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10598 mode->hsync_start = (hsync & 0xffff) + 1;
10599 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10600 mode->vdisplay = (vtot & 0xffff) + 1;
10601 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10602 mode->vsync_start = (vsync & 0xffff) + 1;
10603 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10604
10605 drm_mode_set_name(mode);
10606
10607 return mode;
10608 }
10609
10610 void intel_mark_busy(struct drm_device *dev)
10611 {
10612 struct drm_i915_private *dev_priv = dev->dev_private;
10613
10614 if (dev_priv->mm.busy)
10615 return;
10616
10617 intel_runtime_pm_get(dev_priv);
10618 i915_update_gfx_val(dev_priv);
10619 if (INTEL_INFO(dev)->gen >= 6)
10620 gen6_rps_busy(dev_priv);
10621 dev_priv->mm.busy = true;
10622 }
10623
10624 void intel_mark_idle(struct drm_device *dev)
10625 {
10626 struct drm_i915_private *dev_priv = dev->dev_private;
10627
10628 if (!dev_priv->mm.busy)
10629 return;
10630
10631 dev_priv->mm.busy = false;
10632
10633 if (INTEL_INFO(dev)->gen >= 6)
10634 gen6_rps_idle(dev->dev_private);
10635
10636 intel_runtime_pm_put(dev_priv);
10637 }
10638
10639 static void intel_crtc_destroy(struct drm_crtc *crtc)
10640 {
10641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10642 struct drm_device *dev = crtc->dev;
10643 struct intel_unpin_work *work;
10644
10645 spin_lock_irq(&dev->event_lock);
10646 work = intel_crtc->unpin_work;
10647 intel_crtc->unpin_work = NULL;
10648 spin_unlock_irq(&dev->event_lock);
10649
10650 if (work) {
10651 cancel_work_sync(&work->work);
10652 kfree(work);
10653 }
10654
10655 drm_crtc_cleanup(crtc);
10656
10657 kfree(intel_crtc);
10658 }
10659
10660 static void intel_unpin_work_fn(struct work_struct *__work)
10661 {
10662 struct intel_unpin_work *work =
10663 container_of(__work, struct intel_unpin_work, work);
10664 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10665 struct drm_device *dev = crtc->base.dev;
10666 struct drm_plane *primary = crtc->base.primary;
10667
10668 mutex_lock(&dev->struct_mutex);
10669 intel_unpin_fb_obj(work->old_fb, primary->state);
10670 drm_gem_object_unreference(&work->pending_flip_obj->base);
10671
10672 if (work->flip_queued_req)
10673 i915_gem_request_assign(&work->flip_queued_req, NULL);
10674 mutex_unlock(&dev->struct_mutex);
10675
10676 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10677 drm_framebuffer_unreference(work->old_fb);
10678
10679 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10680 atomic_dec(&crtc->unpin_work_count);
10681
10682 kfree(work);
10683 }
10684
10685 static void do_intel_finish_page_flip(struct drm_device *dev,
10686 struct drm_crtc *crtc)
10687 {
10688 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10689 struct intel_unpin_work *work;
10690 unsigned long flags;
10691
10692 /* Ignore early vblank irqs */
10693 if (intel_crtc == NULL)
10694 return;
10695
10696 /*
10697 * This is called both by irq handlers and the reset code (to complete
10698 * lost pageflips) so needs the full irqsave spinlocks.
10699 */
10700 spin_lock_irqsave(&dev->event_lock, flags);
10701 work = intel_crtc->unpin_work;
10702
10703 /* Ensure we don't miss a work->pending update ... */
10704 smp_rmb();
10705
10706 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10707 spin_unlock_irqrestore(&dev->event_lock, flags);
10708 return;
10709 }
10710
10711 page_flip_completed(intel_crtc);
10712
10713 spin_unlock_irqrestore(&dev->event_lock, flags);
10714 }
10715
10716 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10717 {
10718 struct drm_i915_private *dev_priv = dev->dev_private;
10719 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10720
10721 do_intel_finish_page_flip(dev, crtc);
10722 }
10723
10724 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10725 {
10726 struct drm_i915_private *dev_priv = dev->dev_private;
10727 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10728
10729 do_intel_finish_page_flip(dev, crtc);
10730 }
10731
10732 /* Is 'a' after or equal to 'b'? */
10733 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10734 {
10735 return !((a - b) & 0x80000000);
10736 }
10737
10738 static bool page_flip_finished(struct intel_crtc *crtc)
10739 {
10740 struct drm_device *dev = crtc->base.dev;
10741 struct drm_i915_private *dev_priv = dev->dev_private;
10742
10743 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10744 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10745 return true;
10746
10747 /*
10748 * The relevant registers doen't exist on pre-ctg.
10749 * As the flip done interrupt doesn't trigger for mmio
10750 * flips on gmch platforms, a flip count check isn't
10751 * really needed there. But since ctg has the registers,
10752 * include it in the check anyway.
10753 */
10754 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10755 return true;
10756
10757 /*
10758 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10759 * used the same base address. In that case the mmio flip might
10760 * have completed, but the CS hasn't even executed the flip yet.
10761 *
10762 * A flip count check isn't enough as the CS might have updated
10763 * the base address just after start of vblank, but before we
10764 * managed to process the interrupt. This means we'd complete the
10765 * CS flip too soon.
10766 *
10767 * Combining both checks should get us a good enough result. It may
10768 * still happen that the CS flip has been executed, but has not
10769 * yet actually completed. But in case the base address is the same
10770 * anyway, we don't really care.
10771 */
10772 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10773 crtc->unpin_work->gtt_offset &&
10774 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10775 crtc->unpin_work->flip_count);
10776 }
10777
10778 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10779 {
10780 struct drm_i915_private *dev_priv = dev->dev_private;
10781 struct intel_crtc *intel_crtc =
10782 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10783 unsigned long flags;
10784
10785
10786 /*
10787 * This is called both by irq handlers and the reset code (to complete
10788 * lost pageflips) so needs the full irqsave spinlocks.
10789 *
10790 * NB: An MMIO update of the plane base pointer will also
10791 * generate a page-flip completion irq, i.e. every modeset
10792 * is also accompanied by a spurious intel_prepare_page_flip().
10793 */
10794 spin_lock_irqsave(&dev->event_lock, flags);
10795 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10796 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10797 spin_unlock_irqrestore(&dev->event_lock, flags);
10798 }
10799
10800 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10801 {
10802 /* Ensure that the work item is consistent when activating it ... */
10803 smp_wmb();
10804 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10805 /* and that it is marked active as soon as the irq could fire. */
10806 smp_wmb();
10807 }
10808
10809 static int intel_gen2_queue_flip(struct drm_device *dev,
10810 struct drm_crtc *crtc,
10811 struct drm_framebuffer *fb,
10812 struct drm_i915_gem_object *obj,
10813 struct drm_i915_gem_request *req,
10814 uint32_t flags)
10815 {
10816 struct intel_engine_cs *ring = req->ring;
10817 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10818 u32 flip_mask;
10819 int ret;
10820
10821 ret = intel_ring_begin(req, 6);
10822 if (ret)
10823 return ret;
10824
10825 /* Can't queue multiple flips, so wait for the previous
10826 * one to finish before executing the next.
10827 */
10828 if (intel_crtc->plane)
10829 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10830 else
10831 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10832 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10833 intel_ring_emit(ring, MI_NOOP);
10834 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10835 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10836 intel_ring_emit(ring, fb->pitches[0]);
10837 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10838 intel_ring_emit(ring, 0); /* aux display base address, unused */
10839
10840 intel_mark_page_flip_active(intel_crtc);
10841 return 0;
10842 }
10843
10844 static int intel_gen3_queue_flip(struct drm_device *dev,
10845 struct drm_crtc *crtc,
10846 struct drm_framebuffer *fb,
10847 struct drm_i915_gem_object *obj,
10848 struct drm_i915_gem_request *req,
10849 uint32_t flags)
10850 {
10851 struct intel_engine_cs *ring = req->ring;
10852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10853 u32 flip_mask;
10854 int ret;
10855
10856 ret = intel_ring_begin(req, 6);
10857 if (ret)
10858 return ret;
10859
10860 if (intel_crtc->plane)
10861 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10862 else
10863 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10864 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10865 intel_ring_emit(ring, MI_NOOP);
10866 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10867 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10868 intel_ring_emit(ring, fb->pitches[0]);
10869 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10870 intel_ring_emit(ring, MI_NOOP);
10871
10872 intel_mark_page_flip_active(intel_crtc);
10873 return 0;
10874 }
10875
10876 static int intel_gen4_queue_flip(struct drm_device *dev,
10877 struct drm_crtc *crtc,
10878 struct drm_framebuffer *fb,
10879 struct drm_i915_gem_object *obj,
10880 struct drm_i915_gem_request *req,
10881 uint32_t flags)
10882 {
10883 struct intel_engine_cs *ring = req->ring;
10884 struct drm_i915_private *dev_priv = dev->dev_private;
10885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10886 uint32_t pf, pipesrc;
10887 int ret;
10888
10889 ret = intel_ring_begin(req, 4);
10890 if (ret)
10891 return ret;
10892
10893 /* i965+ uses the linear or tiled offsets from the
10894 * Display Registers (which do not change across a page-flip)
10895 * so we need only reprogram the base address.
10896 */
10897 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10898 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10899 intel_ring_emit(ring, fb->pitches[0]);
10900 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10901 obj->tiling_mode);
10902
10903 /* XXX Enabling the panel-fitter across page-flip is so far
10904 * untested on non-native modes, so ignore it for now.
10905 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10906 */
10907 pf = 0;
10908 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10909 intel_ring_emit(ring, pf | pipesrc);
10910
10911 intel_mark_page_flip_active(intel_crtc);
10912 return 0;
10913 }
10914
10915 static int intel_gen6_queue_flip(struct drm_device *dev,
10916 struct drm_crtc *crtc,
10917 struct drm_framebuffer *fb,
10918 struct drm_i915_gem_object *obj,
10919 struct drm_i915_gem_request *req,
10920 uint32_t flags)
10921 {
10922 struct intel_engine_cs *ring = req->ring;
10923 struct drm_i915_private *dev_priv = dev->dev_private;
10924 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10925 uint32_t pf, pipesrc;
10926 int ret;
10927
10928 ret = intel_ring_begin(req, 4);
10929 if (ret)
10930 return ret;
10931
10932 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10933 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10934 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10935 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10936
10937 /* Contrary to the suggestions in the documentation,
10938 * "Enable Panel Fitter" does not seem to be required when page
10939 * flipping with a non-native mode, and worse causes a normal
10940 * modeset to fail.
10941 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10942 */
10943 pf = 0;
10944 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10945 intel_ring_emit(ring, pf | pipesrc);
10946
10947 intel_mark_page_flip_active(intel_crtc);
10948 return 0;
10949 }
10950
10951 static int intel_gen7_queue_flip(struct drm_device *dev,
10952 struct drm_crtc *crtc,
10953 struct drm_framebuffer *fb,
10954 struct drm_i915_gem_object *obj,
10955 struct drm_i915_gem_request *req,
10956 uint32_t flags)
10957 {
10958 struct intel_engine_cs *ring = req->ring;
10959 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10960 uint32_t plane_bit = 0;
10961 int len, ret;
10962
10963 switch (intel_crtc->plane) {
10964 case PLANE_A:
10965 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10966 break;
10967 case PLANE_B:
10968 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10969 break;
10970 case PLANE_C:
10971 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10972 break;
10973 default:
10974 WARN_ONCE(1, "unknown plane in flip command\n");
10975 return -ENODEV;
10976 }
10977
10978 len = 4;
10979 if (ring->id == RCS) {
10980 len += 6;
10981 /*
10982 * On Gen 8, SRM is now taking an extra dword to accommodate
10983 * 48bits addresses, and we need a NOOP for the batch size to
10984 * stay even.
10985 */
10986 if (IS_GEN8(dev))
10987 len += 2;
10988 }
10989
10990 /*
10991 * BSpec MI_DISPLAY_FLIP for IVB:
10992 * "The full packet must be contained within the same cache line."
10993 *
10994 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10995 * cacheline, if we ever start emitting more commands before
10996 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10997 * then do the cacheline alignment, and finally emit the
10998 * MI_DISPLAY_FLIP.
10999 */
11000 ret = intel_ring_cacheline_align(req);
11001 if (ret)
11002 return ret;
11003
11004 ret = intel_ring_begin(req, len);
11005 if (ret)
11006 return ret;
11007
11008 /* Unmask the flip-done completion message. Note that the bspec says that
11009 * we should do this for both the BCS and RCS, and that we must not unmask
11010 * more than one flip event at any time (or ensure that one flip message
11011 * can be sent by waiting for flip-done prior to queueing new flips).
11012 * Experimentation says that BCS works despite DERRMR masking all
11013 * flip-done completion events and that unmasking all planes at once
11014 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11015 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11016 */
11017 if (ring->id == RCS) {
11018 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11019 intel_ring_emit(ring, DERRMR);
11020 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11021 DERRMR_PIPEB_PRI_FLIP_DONE |
11022 DERRMR_PIPEC_PRI_FLIP_DONE));
11023 if (IS_GEN8(dev))
11024 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11025 MI_SRM_LRM_GLOBAL_GTT);
11026 else
11027 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11028 MI_SRM_LRM_GLOBAL_GTT);
11029 intel_ring_emit(ring, DERRMR);
11030 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11031 if (IS_GEN8(dev)) {
11032 intel_ring_emit(ring, 0);
11033 intel_ring_emit(ring, MI_NOOP);
11034 }
11035 }
11036
11037 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11038 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11039 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11040 intel_ring_emit(ring, (MI_NOOP));
11041
11042 intel_mark_page_flip_active(intel_crtc);
11043 return 0;
11044 }
11045
11046 static bool use_mmio_flip(struct intel_engine_cs *ring,
11047 struct drm_i915_gem_object *obj)
11048 {
11049 /*
11050 * This is not being used for older platforms, because
11051 * non-availability of flip done interrupt forces us to use
11052 * CS flips. Older platforms derive flip done using some clever
11053 * tricks involving the flip_pending status bits and vblank irqs.
11054 * So using MMIO flips there would disrupt this mechanism.
11055 */
11056
11057 if (ring == NULL)
11058 return true;
11059
11060 if (INTEL_INFO(ring->dev)->gen < 5)
11061 return false;
11062
11063 if (i915.use_mmio_flip < 0)
11064 return false;
11065 else if (i915.use_mmio_flip > 0)
11066 return true;
11067 else if (i915.enable_execlists)
11068 return true;
11069 else
11070 return ring != i915_gem_request_get_ring(obj->last_write_req);
11071 }
11072
11073 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11074 {
11075 struct drm_device *dev = intel_crtc->base.dev;
11076 struct drm_i915_private *dev_priv = dev->dev_private;
11077 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11078 const enum pipe pipe = intel_crtc->pipe;
11079 u32 ctl, stride;
11080
11081 ctl = I915_READ(PLANE_CTL(pipe, 0));
11082 ctl &= ~PLANE_CTL_TILED_MASK;
11083 switch (fb->modifier[0]) {
11084 case DRM_FORMAT_MOD_NONE:
11085 break;
11086 case I915_FORMAT_MOD_X_TILED:
11087 ctl |= PLANE_CTL_TILED_X;
11088 break;
11089 case I915_FORMAT_MOD_Y_TILED:
11090 ctl |= PLANE_CTL_TILED_Y;
11091 break;
11092 case I915_FORMAT_MOD_Yf_TILED:
11093 ctl |= PLANE_CTL_TILED_YF;
11094 break;
11095 default:
11096 MISSING_CASE(fb->modifier[0]);
11097 }
11098
11099 /*
11100 * The stride is either expressed as a multiple of 64 bytes chunks for
11101 * linear buffers or in number of tiles for tiled buffers.
11102 */
11103 stride = fb->pitches[0] /
11104 intel_fb_stride_alignment(dev, fb->modifier[0],
11105 fb->pixel_format);
11106
11107 /*
11108 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11109 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11110 */
11111 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11112 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11113
11114 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11115 POSTING_READ(PLANE_SURF(pipe, 0));
11116 }
11117
11118 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11119 {
11120 struct drm_device *dev = intel_crtc->base.dev;
11121 struct drm_i915_private *dev_priv = dev->dev_private;
11122 struct intel_framebuffer *intel_fb =
11123 to_intel_framebuffer(intel_crtc->base.primary->fb);
11124 struct drm_i915_gem_object *obj = intel_fb->obj;
11125 u32 dspcntr;
11126 u32 reg;
11127
11128 reg = DSPCNTR(intel_crtc->plane);
11129 dspcntr = I915_READ(reg);
11130
11131 if (obj->tiling_mode != I915_TILING_NONE)
11132 dspcntr |= DISPPLANE_TILED;
11133 else
11134 dspcntr &= ~DISPPLANE_TILED;
11135
11136 I915_WRITE(reg, dspcntr);
11137
11138 I915_WRITE(DSPSURF(intel_crtc->plane),
11139 intel_crtc->unpin_work->gtt_offset);
11140 POSTING_READ(DSPSURF(intel_crtc->plane));
11141
11142 }
11143
11144 /*
11145 * XXX: This is the temporary way to update the plane registers until we get
11146 * around to using the usual plane update functions for MMIO flips
11147 */
11148 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11149 {
11150 struct drm_device *dev = intel_crtc->base.dev;
11151 u32 start_vbl_count;
11152
11153 intel_mark_page_flip_active(intel_crtc);
11154
11155 intel_pipe_update_start(intel_crtc, &start_vbl_count);
11156
11157 if (INTEL_INFO(dev)->gen >= 9)
11158 skl_do_mmio_flip(intel_crtc);
11159 else
11160 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11161 ilk_do_mmio_flip(intel_crtc);
11162
11163 intel_pipe_update_end(intel_crtc, start_vbl_count);
11164 }
11165
11166 static void intel_mmio_flip_work_func(struct work_struct *work)
11167 {
11168 struct intel_mmio_flip *mmio_flip =
11169 container_of(work, struct intel_mmio_flip, work);
11170
11171 if (mmio_flip->req)
11172 WARN_ON(__i915_wait_request(mmio_flip->req,
11173 mmio_flip->crtc->reset_counter,
11174 false, NULL,
11175 &mmio_flip->i915->rps.mmioflips));
11176
11177 intel_do_mmio_flip(mmio_flip->crtc);
11178
11179 i915_gem_request_unreference__unlocked(mmio_flip->req);
11180 kfree(mmio_flip);
11181 }
11182
11183 static int intel_queue_mmio_flip(struct drm_device *dev,
11184 struct drm_crtc *crtc,
11185 struct drm_framebuffer *fb,
11186 struct drm_i915_gem_object *obj,
11187 struct intel_engine_cs *ring,
11188 uint32_t flags)
11189 {
11190 struct intel_mmio_flip *mmio_flip;
11191
11192 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11193 if (mmio_flip == NULL)
11194 return -ENOMEM;
11195
11196 mmio_flip->i915 = to_i915(dev);
11197 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11198 mmio_flip->crtc = to_intel_crtc(crtc);
11199
11200 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11201 schedule_work(&mmio_flip->work);
11202
11203 return 0;
11204 }
11205
11206 static int intel_default_queue_flip(struct drm_device *dev,
11207 struct drm_crtc *crtc,
11208 struct drm_framebuffer *fb,
11209 struct drm_i915_gem_object *obj,
11210 struct drm_i915_gem_request *req,
11211 uint32_t flags)
11212 {
11213 return -ENODEV;
11214 }
11215
11216 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11217 struct drm_crtc *crtc)
11218 {
11219 struct drm_i915_private *dev_priv = dev->dev_private;
11220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11221 struct intel_unpin_work *work = intel_crtc->unpin_work;
11222 u32 addr;
11223
11224 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11225 return true;
11226
11227 if (!work->enable_stall_check)
11228 return false;
11229
11230 if (work->flip_ready_vblank == 0) {
11231 if (work->flip_queued_req &&
11232 !i915_gem_request_completed(work->flip_queued_req, true))
11233 return false;
11234
11235 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11236 }
11237
11238 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11239 return false;
11240
11241 /* Potential stall - if we see that the flip has happened,
11242 * assume a missed interrupt. */
11243 if (INTEL_INFO(dev)->gen >= 4)
11244 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11245 else
11246 addr = I915_READ(DSPADDR(intel_crtc->plane));
11247
11248 /* There is a potential issue here with a false positive after a flip
11249 * to the same address. We could address this by checking for a
11250 * non-incrementing frame counter.
11251 */
11252 return addr == work->gtt_offset;
11253 }
11254
11255 void intel_check_page_flip(struct drm_device *dev, int pipe)
11256 {
11257 struct drm_i915_private *dev_priv = dev->dev_private;
11258 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11260 struct intel_unpin_work *work;
11261
11262 WARN_ON(!in_interrupt());
11263
11264 if (crtc == NULL)
11265 return;
11266
11267 spin_lock(&dev->event_lock);
11268 work = intel_crtc->unpin_work;
11269 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11270 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11271 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11272 page_flip_completed(intel_crtc);
11273 work = NULL;
11274 }
11275 if (work != NULL &&
11276 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11277 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11278 spin_unlock(&dev->event_lock);
11279 }
11280
11281 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11282 struct drm_framebuffer *fb,
11283 struct drm_pending_vblank_event *event,
11284 uint32_t page_flip_flags)
11285 {
11286 struct drm_device *dev = crtc->dev;
11287 struct drm_i915_private *dev_priv = dev->dev_private;
11288 struct drm_framebuffer *old_fb = crtc->primary->fb;
11289 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11291 struct drm_plane *primary = crtc->primary;
11292 enum pipe pipe = intel_crtc->pipe;
11293 struct intel_unpin_work *work;
11294 struct intel_engine_cs *ring;
11295 bool mmio_flip;
11296 struct drm_i915_gem_request *request = NULL;
11297 int ret;
11298
11299 /*
11300 * drm_mode_page_flip_ioctl() should already catch this, but double
11301 * check to be safe. In the future we may enable pageflipping from
11302 * a disabled primary plane.
11303 */
11304 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11305 return -EBUSY;
11306
11307 /* Can't change pixel format via MI display flips. */
11308 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11309 return -EINVAL;
11310
11311 /*
11312 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11313 * Note that pitch changes could also affect these register.
11314 */
11315 if (INTEL_INFO(dev)->gen > 3 &&
11316 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11317 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11318 return -EINVAL;
11319
11320 if (i915_terminally_wedged(&dev_priv->gpu_error))
11321 goto out_hang;
11322
11323 work = kzalloc(sizeof(*work), GFP_KERNEL);
11324 if (work == NULL)
11325 return -ENOMEM;
11326
11327 work->event = event;
11328 work->crtc = crtc;
11329 work->old_fb = old_fb;
11330 INIT_WORK(&work->work, intel_unpin_work_fn);
11331
11332 ret = drm_crtc_vblank_get(crtc);
11333 if (ret)
11334 goto free_work;
11335
11336 /* We borrow the event spin lock for protecting unpin_work */
11337 spin_lock_irq(&dev->event_lock);
11338 if (intel_crtc->unpin_work) {
11339 /* Before declaring the flip queue wedged, check if
11340 * the hardware completed the operation behind our backs.
11341 */
11342 if (__intel_pageflip_stall_check(dev, crtc)) {
11343 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11344 page_flip_completed(intel_crtc);
11345 } else {
11346 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11347 spin_unlock_irq(&dev->event_lock);
11348
11349 drm_crtc_vblank_put(crtc);
11350 kfree(work);
11351 return -EBUSY;
11352 }
11353 }
11354 intel_crtc->unpin_work = work;
11355 spin_unlock_irq(&dev->event_lock);
11356
11357 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11358 flush_workqueue(dev_priv->wq);
11359
11360 /* Reference the objects for the scheduled work. */
11361 drm_framebuffer_reference(work->old_fb);
11362 drm_gem_object_reference(&obj->base);
11363
11364 crtc->primary->fb = fb;
11365 update_state_fb(crtc->primary);
11366
11367 work->pending_flip_obj = obj;
11368
11369 ret = i915_mutex_lock_interruptible(dev);
11370 if (ret)
11371 goto cleanup;
11372
11373 atomic_inc(&intel_crtc->unpin_work_count);
11374 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11375
11376 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11377 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11378
11379 if (IS_VALLEYVIEW(dev)) {
11380 ring = &dev_priv->ring[BCS];
11381 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11382 /* vlv: DISPLAY_FLIP fails to change tiling */
11383 ring = NULL;
11384 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11385 ring = &dev_priv->ring[BCS];
11386 } else if (INTEL_INFO(dev)->gen >= 7) {
11387 ring = i915_gem_request_get_ring(obj->last_write_req);
11388 if (ring == NULL || ring->id != RCS)
11389 ring = &dev_priv->ring[BCS];
11390 } else {
11391 ring = &dev_priv->ring[RCS];
11392 }
11393
11394 mmio_flip = use_mmio_flip(ring, obj);
11395
11396 /* When using CS flips, we want to emit semaphores between rings.
11397 * However, when using mmio flips we will create a task to do the
11398 * synchronisation, so all we want here is to pin the framebuffer
11399 * into the display plane and skip any waits.
11400 */
11401 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11402 crtc->primary->state,
11403 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11404 if (ret)
11405 goto cleanup_pending;
11406
11407 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11408 + intel_crtc->dspaddr_offset;
11409
11410 if (mmio_flip) {
11411 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11412 page_flip_flags);
11413 if (ret)
11414 goto cleanup_unpin;
11415
11416 i915_gem_request_assign(&work->flip_queued_req,
11417 obj->last_write_req);
11418 } else {
11419 if (!request) {
11420 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11421 if (ret)
11422 goto cleanup_unpin;
11423 }
11424
11425 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11426 page_flip_flags);
11427 if (ret)
11428 goto cleanup_unpin;
11429
11430 i915_gem_request_assign(&work->flip_queued_req, request);
11431 }
11432
11433 if (request)
11434 i915_add_request_no_flush(request);
11435
11436 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11437 work->enable_stall_check = true;
11438
11439 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11440 to_intel_plane(primary)->frontbuffer_bit);
11441 mutex_unlock(&dev->struct_mutex);
11442
11443 intel_fbc_disable_crtc(intel_crtc);
11444 intel_frontbuffer_flip_prepare(dev,
11445 to_intel_plane(primary)->frontbuffer_bit);
11446
11447 trace_i915_flip_request(intel_crtc->plane, obj);
11448
11449 return 0;
11450
11451 cleanup_unpin:
11452 intel_unpin_fb_obj(fb, crtc->primary->state);
11453 cleanup_pending:
11454 if (request)
11455 i915_gem_request_cancel(request);
11456 atomic_dec(&intel_crtc->unpin_work_count);
11457 mutex_unlock(&dev->struct_mutex);
11458 cleanup:
11459 crtc->primary->fb = old_fb;
11460 update_state_fb(crtc->primary);
11461
11462 drm_gem_object_unreference_unlocked(&obj->base);
11463 drm_framebuffer_unreference(work->old_fb);
11464
11465 spin_lock_irq(&dev->event_lock);
11466 intel_crtc->unpin_work = NULL;
11467 spin_unlock_irq(&dev->event_lock);
11468
11469 drm_crtc_vblank_put(crtc);
11470 free_work:
11471 kfree(work);
11472
11473 if (ret == -EIO) {
11474 struct drm_atomic_state *state;
11475 struct drm_plane_state *plane_state;
11476
11477 out_hang:
11478 state = drm_atomic_state_alloc(dev);
11479 if (!state)
11480 return -ENOMEM;
11481 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11482
11483 retry:
11484 plane_state = drm_atomic_get_plane_state(state, primary);
11485 ret = PTR_ERR_OR_ZERO(plane_state);
11486 if (!ret) {
11487 drm_atomic_set_fb_for_plane(plane_state, fb);
11488
11489 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11490 if (!ret)
11491 ret = drm_atomic_commit(state);
11492 }
11493
11494 if (ret == -EDEADLK) {
11495 drm_modeset_backoff(state->acquire_ctx);
11496 drm_atomic_state_clear(state);
11497 goto retry;
11498 }
11499
11500 if (ret)
11501 drm_atomic_state_free(state);
11502
11503 if (ret == 0 && event) {
11504 spin_lock_irq(&dev->event_lock);
11505 drm_send_vblank_event(dev, pipe, event);
11506 spin_unlock_irq(&dev->event_lock);
11507 }
11508 }
11509 return ret;
11510 }
11511
11512
11513 /**
11514 * intel_wm_need_update - Check whether watermarks need updating
11515 * @plane: drm plane
11516 * @state: new plane state
11517 *
11518 * Check current plane state versus the new one to determine whether
11519 * watermarks need to be recalculated.
11520 *
11521 * Returns true or false.
11522 */
11523 static bool intel_wm_need_update(struct drm_plane *plane,
11524 struct drm_plane_state *state)
11525 {
11526 /* Update watermarks on tiling changes. */
11527 if (!plane->state->fb || !state->fb ||
11528 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11529 plane->state->rotation != state->rotation)
11530 return true;
11531
11532 if (plane->state->crtc_w != state->crtc_w)
11533 return true;
11534
11535 return false;
11536 }
11537
11538 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11539 struct drm_plane_state *plane_state)
11540 {
11541 struct drm_crtc *crtc = crtc_state->crtc;
11542 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11543 struct drm_plane *plane = plane_state->plane;
11544 struct drm_device *dev = crtc->dev;
11545 struct drm_i915_private *dev_priv = dev->dev_private;
11546 struct intel_plane_state *old_plane_state =
11547 to_intel_plane_state(plane->state);
11548 int idx = intel_crtc->base.base.id, ret;
11549 int i = drm_plane_index(plane);
11550 bool mode_changed = needs_modeset(crtc_state);
11551 bool was_crtc_enabled = crtc->state->active;
11552 bool is_crtc_enabled = crtc_state->active;
11553
11554 bool turn_off, turn_on, visible, was_visible;
11555 struct drm_framebuffer *fb = plane_state->fb;
11556
11557 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11558 plane->type != DRM_PLANE_TYPE_CURSOR) {
11559 ret = skl_update_scaler_plane(
11560 to_intel_crtc_state(crtc_state),
11561 to_intel_plane_state(plane_state));
11562 if (ret)
11563 return ret;
11564 }
11565
11566 /*
11567 * Disabling a plane is always okay; we just need to update
11568 * fb tracking in a special way since cleanup_fb() won't
11569 * get called by the plane helpers.
11570 */
11571 if (old_plane_state->base.fb && !fb)
11572 intel_crtc->atomic.disabled_planes |= 1 << i;
11573
11574 was_visible = old_plane_state->visible;
11575 visible = to_intel_plane_state(plane_state)->visible;
11576
11577 if (!was_crtc_enabled && WARN_ON(was_visible))
11578 was_visible = false;
11579
11580 if (!is_crtc_enabled && WARN_ON(visible))
11581 visible = false;
11582
11583 if (!was_visible && !visible)
11584 return 0;
11585
11586 turn_off = was_visible && (!visible || mode_changed);
11587 turn_on = visible && (!was_visible || mode_changed);
11588
11589 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11590 plane->base.id, fb ? fb->base.id : -1);
11591
11592 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11593 plane->base.id, was_visible, visible,
11594 turn_off, turn_on, mode_changed);
11595
11596 if (turn_on) {
11597 intel_crtc->atomic.update_wm_pre = true;
11598 /* must disable cxsr around plane enable/disable */
11599 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11600 intel_crtc->atomic.disable_cxsr = true;
11601 /* to potentially re-enable cxsr */
11602 intel_crtc->atomic.wait_vblank = true;
11603 intel_crtc->atomic.update_wm_post = true;
11604 }
11605 } else if (turn_off) {
11606 intel_crtc->atomic.update_wm_post = true;
11607 /* must disable cxsr around plane enable/disable */
11608 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11609 if (is_crtc_enabled)
11610 intel_crtc->atomic.wait_vblank = true;
11611 intel_crtc->atomic.disable_cxsr = true;
11612 }
11613 } else if (intel_wm_need_update(plane, plane_state)) {
11614 intel_crtc->atomic.update_wm_pre = true;
11615 }
11616
11617 if (visible)
11618 intel_crtc->atomic.fb_bits |=
11619 to_intel_plane(plane)->frontbuffer_bit;
11620
11621 switch (plane->type) {
11622 case DRM_PLANE_TYPE_PRIMARY:
11623 intel_crtc->atomic.wait_for_flips = true;
11624 intel_crtc->atomic.pre_disable_primary = turn_off;
11625 intel_crtc->atomic.post_enable_primary = turn_on;
11626
11627 if (turn_off) {
11628 /*
11629 * FIXME: Actually if we will still have any other
11630 * plane enabled on the pipe we could let IPS enabled
11631 * still, but for now lets consider that when we make
11632 * primary invisible by setting DSPCNTR to 0 on
11633 * update_primary_plane function IPS needs to be
11634 * disable.
11635 */
11636 intel_crtc->atomic.disable_ips = true;
11637
11638 intel_crtc->atomic.disable_fbc = true;
11639 }
11640
11641 /*
11642 * FBC does not work on some platforms for rotated
11643 * planes, so disable it when rotation is not 0 and
11644 * update it when rotation is set back to 0.
11645 *
11646 * FIXME: This is redundant with the fbc update done in
11647 * the primary plane enable function except that that
11648 * one is done too late. We eventually need to unify
11649 * this.
11650 */
11651
11652 if (visible &&
11653 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11654 dev_priv->fbc.crtc == intel_crtc &&
11655 plane_state->rotation != BIT(DRM_ROTATE_0))
11656 intel_crtc->atomic.disable_fbc = true;
11657
11658 /*
11659 * BDW signals flip done immediately if the plane
11660 * is disabled, even if the plane enable is already
11661 * armed to occur at the next vblank :(
11662 */
11663 if (turn_on && IS_BROADWELL(dev))
11664 intel_crtc->atomic.wait_vblank = true;
11665
11666 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11667 break;
11668 case DRM_PLANE_TYPE_CURSOR:
11669 break;
11670 case DRM_PLANE_TYPE_OVERLAY:
11671 if (turn_off && !mode_changed) {
11672 intel_crtc->atomic.wait_vblank = true;
11673 intel_crtc->atomic.update_sprite_watermarks |=
11674 1 << i;
11675 }
11676 }
11677 return 0;
11678 }
11679
11680 static bool encoders_cloneable(const struct intel_encoder *a,
11681 const struct intel_encoder *b)
11682 {
11683 /* masks could be asymmetric, so check both ways */
11684 return a == b || (a->cloneable & (1 << b->type) &&
11685 b->cloneable & (1 << a->type));
11686 }
11687
11688 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11689 struct intel_crtc *crtc,
11690 struct intel_encoder *encoder)
11691 {
11692 struct intel_encoder *source_encoder;
11693 struct drm_connector *connector;
11694 struct drm_connector_state *connector_state;
11695 int i;
11696
11697 for_each_connector_in_state(state, connector, connector_state, i) {
11698 if (connector_state->crtc != &crtc->base)
11699 continue;
11700
11701 source_encoder =
11702 to_intel_encoder(connector_state->best_encoder);
11703 if (!encoders_cloneable(encoder, source_encoder))
11704 return false;
11705 }
11706
11707 return true;
11708 }
11709
11710 static bool check_encoder_cloning(struct drm_atomic_state *state,
11711 struct intel_crtc *crtc)
11712 {
11713 struct intel_encoder *encoder;
11714 struct drm_connector *connector;
11715 struct drm_connector_state *connector_state;
11716 int i;
11717
11718 for_each_connector_in_state(state, connector, connector_state, i) {
11719 if (connector_state->crtc != &crtc->base)
11720 continue;
11721
11722 encoder = to_intel_encoder(connector_state->best_encoder);
11723 if (!check_single_encoder_cloning(state, crtc, encoder))
11724 return false;
11725 }
11726
11727 return true;
11728 }
11729
11730 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11731 struct drm_crtc_state *crtc_state)
11732 {
11733 struct drm_device *dev = crtc->dev;
11734 struct drm_i915_private *dev_priv = dev->dev_private;
11735 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11736 struct intel_crtc_state *pipe_config =
11737 to_intel_crtc_state(crtc_state);
11738 struct drm_atomic_state *state = crtc_state->state;
11739 int ret;
11740 bool mode_changed = needs_modeset(crtc_state);
11741
11742 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11743 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11744 return -EINVAL;
11745 }
11746
11747 if (mode_changed && !crtc_state->active)
11748 intel_crtc->atomic.update_wm_post = true;
11749
11750 if (mode_changed && crtc_state->enable &&
11751 dev_priv->display.crtc_compute_clock &&
11752 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11753 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11754 pipe_config);
11755 if (ret)
11756 return ret;
11757 }
11758
11759 ret = 0;
11760 if (INTEL_INFO(dev)->gen >= 9) {
11761 if (mode_changed)
11762 ret = skl_update_scaler_crtc(pipe_config);
11763
11764 if (!ret)
11765 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11766 pipe_config);
11767 }
11768
11769 return ret;
11770 }
11771
11772 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11773 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11774 .load_lut = intel_crtc_load_lut,
11775 .atomic_begin = intel_begin_crtc_commit,
11776 .atomic_flush = intel_finish_crtc_commit,
11777 .atomic_check = intel_crtc_atomic_check,
11778 };
11779
11780 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11781 {
11782 struct intel_connector *connector;
11783
11784 for_each_intel_connector(dev, connector) {
11785 if (connector->base.encoder) {
11786 connector->base.state->best_encoder =
11787 connector->base.encoder;
11788 connector->base.state->crtc =
11789 connector->base.encoder->crtc;
11790 } else {
11791 connector->base.state->best_encoder = NULL;
11792 connector->base.state->crtc = NULL;
11793 }
11794 }
11795 }
11796
11797 static void
11798 connected_sink_compute_bpp(struct intel_connector *connector,
11799 struct intel_crtc_state *pipe_config)
11800 {
11801 int bpp = pipe_config->pipe_bpp;
11802
11803 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11804 connector->base.base.id,
11805 connector->base.name);
11806
11807 /* Don't use an invalid EDID bpc value */
11808 if (connector->base.display_info.bpc &&
11809 connector->base.display_info.bpc * 3 < bpp) {
11810 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11811 bpp, connector->base.display_info.bpc*3);
11812 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11813 }
11814
11815 /* Clamp bpp to 8 on screens without EDID 1.4 */
11816 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11817 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11818 bpp);
11819 pipe_config->pipe_bpp = 24;
11820 }
11821 }
11822
11823 static int
11824 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11825 struct intel_crtc_state *pipe_config)
11826 {
11827 struct drm_device *dev = crtc->base.dev;
11828 struct drm_atomic_state *state;
11829 struct drm_connector *connector;
11830 struct drm_connector_state *connector_state;
11831 int bpp, i;
11832
11833 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11834 bpp = 10*3;
11835 else if (INTEL_INFO(dev)->gen >= 5)
11836 bpp = 12*3;
11837 else
11838 bpp = 8*3;
11839
11840
11841 pipe_config->pipe_bpp = bpp;
11842
11843 state = pipe_config->base.state;
11844
11845 /* Clamp display bpp to EDID value */
11846 for_each_connector_in_state(state, connector, connector_state, i) {
11847 if (connector_state->crtc != &crtc->base)
11848 continue;
11849
11850 connected_sink_compute_bpp(to_intel_connector(connector),
11851 pipe_config);
11852 }
11853
11854 return bpp;
11855 }
11856
11857 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11858 {
11859 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11860 "type: 0x%x flags: 0x%x\n",
11861 mode->crtc_clock,
11862 mode->crtc_hdisplay, mode->crtc_hsync_start,
11863 mode->crtc_hsync_end, mode->crtc_htotal,
11864 mode->crtc_vdisplay, mode->crtc_vsync_start,
11865 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11866 }
11867
11868 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11869 struct intel_crtc_state *pipe_config,
11870 const char *context)
11871 {
11872 struct drm_device *dev = crtc->base.dev;
11873 struct drm_plane *plane;
11874 struct intel_plane *intel_plane;
11875 struct intel_plane_state *state;
11876 struct drm_framebuffer *fb;
11877
11878 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11879 context, pipe_config, pipe_name(crtc->pipe));
11880
11881 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11882 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11883 pipe_config->pipe_bpp, pipe_config->dither);
11884 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11885 pipe_config->has_pch_encoder,
11886 pipe_config->fdi_lanes,
11887 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11888 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11889 pipe_config->fdi_m_n.tu);
11890 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11891 pipe_config->has_dp_encoder,
11892 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11893 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11894 pipe_config->dp_m_n.tu);
11895
11896 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11897 pipe_config->has_dp_encoder,
11898 pipe_config->dp_m2_n2.gmch_m,
11899 pipe_config->dp_m2_n2.gmch_n,
11900 pipe_config->dp_m2_n2.link_m,
11901 pipe_config->dp_m2_n2.link_n,
11902 pipe_config->dp_m2_n2.tu);
11903
11904 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11905 pipe_config->has_audio,
11906 pipe_config->has_infoframe);
11907
11908 DRM_DEBUG_KMS("requested mode:\n");
11909 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11910 DRM_DEBUG_KMS("adjusted mode:\n");
11911 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11912 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11913 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11914 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11915 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11916 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11917 crtc->num_scalers,
11918 pipe_config->scaler_state.scaler_users,
11919 pipe_config->scaler_state.scaler_id);
11920 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11921 pipe_config->gmch_pfit.control,
11922 pipe_config->gmch_pfit.pgm_ratios,
11923 pipe_config->gmch_pfit.lvds_border_bits);
11924 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11925 pipe_config->pch_pfit.pos,
11926 pipe_config->pch_pfit.size,
11927 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11928 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11929 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11930
11931 if (IS_BROXTON(dev)) {
11932 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11933 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11934 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11935 pipe_config->ddi_pll_sel,
11936 pipe_config->dpll_hw_state.ebb0,
11937 pipe_config->dpll_hw_state.ebb4,
11938 pipe_config->dpll_hw_state.pll0,
11939 pipe_config->dpll_hw_state.pll1,
11940 pipe_config->dpll_hw_state.pll2,
11941 pipe_config->dpll_hw_state.pll3,
11942 pipe_config->dpll_hw_state.pll6,
11943 pipe_config->dpll_hw_state.pll8,
11944 pipe_config->dpll_hw_state.pll9,
11945 pipe_config->dpll_hw_state.pll10,
11946 pipe_config->dpll_hw_state.pcsdw12);
11947 } else if (IS_SKYLAKE(dev)) {
11948 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11949 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11950 pipe_config->ddi_pll_sel,
11951 pipe_config->dpll_hw_state.ctrl1,
11952 pipe_config->dpll_hw_state.cfgcr1,
11953 pipe_config->dpll_hw_state.cfgcr2);
11954 } else if (HAS_DDI(dev)) {
11955 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11956 pipe_config->ddi_pll_sel,
11957 pipe_config->dpll_hw_state.wrpll);
11958 } else {
11959 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11960 "fp0: 0x%x, fp1: 0x%x\n",
11961 pipe_config->dpll_hw_state.dpll,
11962 pipe_config->dpll_hw_state.dpll_md,
11963 pipe_config->dpll_hw_state.fp0,
11964 pipe_config->dpll_hw_state.fp1);
11965 }
11966
11967 DRM_DEBUG_KMS("planes on this crtc\n");
11968 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11969 intel_plane = to_intel_plane(plane);
11970 if (intel_plane->pipe != crtc->pipe)
11971 continue;
11972
11973 state = to_intel_plane_state(plane->state);
11974 fb = state->base.fb;
11975 if (!fb) {
11976 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11977 "disabled, scaler_id = %d\n",
11978 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11979 plane->base.id, intel_plane->pipe,
11980 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11981 drm_plane_index(plane), state->scaler_id);
11982 continue;
11983 }
11984
11985 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11986 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11987 plane->base.id, intel_plane->pipe,
11988 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11989 drm_plane_index(plane));
11990 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11991 fb->base.id, fb->width, fb->height, fb->pixel_format);
11992 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11993 state->scaler_id,
11994 state->src.x1 >> 16, state->src.y1 >> 16,
11995 drm_rect_width(&state->src) >> 16,
11996 drm_rect_height(&state->src) >> 16,
11997 state->dst.x1, state->dst.y1,
11998 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11999 }
12000 }
12001
12002 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12003 {
12004 struct drm_device *dev = state->dev;
12005 struct intel_encoder *encoder;
12006 struct drm_connector *connector;
12007 struct drm_connector_state *connector_state;
12008 unsigned int used_ports = 0;
12009 int i;
12010
12011 /*
12012 * Walk the connector list instead of the encoder
12013 * list to detect the problem on ddi platforms
12014 * where there's just one encoder per digital port.
12015 */
12016 for_each_connector_in_state(state, connector, connector_state, i) {
12017 if (!connector_state->best_encoder)
12018 continue;
12019
12020 encoder = to_intel_encoder(connector_state->best_encoder);
12021
12022 WARN_ON(!connector_state->crtc);
12023
12024 switch (encoder->type) {
12025 unsigned int port_mask;
12026 case INTEL_OUTPUT_UNKNOWN:
12027 if (WARN_ON(!HAS_DDI(dev)))
12028 break;
12029 case INTEL_OUTPUT_DISPLAYPORT:
12030 case INTEL_OUTPUT_HDMI:
12031 case INTEL_OUTPUT_EDP:
12032 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12033
12034 /* the same port mustn't appear more than once */
12035 if (used_ports & port_mask)
12036 return false;
12037
12038 used_ports |= port_mask;
12039 default:
12040 break;
12041 }
12042 }
12043
12044 return true;
12045 }
12046
12047 static void
12048 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12049 {
12050 struct drm_crtc_state tmp_state;
12051 struct intel_crtc_scaler_state scaler_state;
12052 struct intel_dpll_hw_state dpll_hw_state;
12053 enum intel_dpll_id shared_dpll;
12054 uint32_t ddi_pll_sel;
12055 bool force_thru;
12056
12057 /* FIXME: before the switch to atomic started, a new pipe_config was
12058 * kzalloc'd. Code that depends on any field being zero should be
12059 * fixed, so that the crtc_state can be safely duplicated. For now,
12060 * only fields that are know to not cause problems are preserved. */
12061
12062 tmp_state = crtc_state->base;
12063 scaler_state = crtc_state->scaler_state;
12064 shared_dpll = crtc_state->shared_dpll;
12065 dpll_hw_state = crtc_state->dpll_hw_state;
12066 ddi_pll_sel = crtc_state->ddi_pll_sel;
12067 force_thru = crtc_state->pch_pfit.force_thru;
12068
12069 memset(crtc_state, 0, sizeof *crtc_state);
12070
12071 crtc_state->base = tmp_state;
12072 crtc_state->scaler_state = scaler_state;
12073 crtc_state->shared_dpll = shared_dpll;
12074 crtc_state->dpll_hw_state = dpll_hw_state;
12075 crtc_state->ddi_pll_sel = ddi_pll_sel;
12076 crtc_state->pch_pfit.force_thru = force_thru;
12077 }
12078
12079 static int
12080 intel_modeset_pipe_config(struct drm_crtc *crtc,
12081 struct intel_crtc_state *pipe_config)
12082 {
12083 struct drm_atomic_state *state = pipe_config->base.state;
12084 struct intel_encoder *encoder;
12085 struct drm_connector *connector;
12086 struct drm_connector_state *connector_state;
12087 int base_bpp, ret = -EINVAL;
12088 int i;
12089 bool retry = true;
12090
12091 clear_intel_crtc_state(pipe_config);
12092
12093 pipe_config->cpu_transcoder =
12094 (enum transcoder) to_intel_crtc(crtc)->pipe;
12095
12096 /*
12097 * Sanitize sync polarity flags based on requested ones. If neither
12098 * positive or negative polarity is requested, treat this as meaning
12099 * negative polarity.
12100 */
12101 if (!(pipe_config->base.adjusted_mode.flags &
12102 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12103 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12104
12105 if (!(pipe_config->base.adjusted_mode.flags &
12106 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12107 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12108
12109 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12110 * plane pixel format and any sink constraints into account. Returns the
12111 * source plane bpp so that dithering can be selected on mismatches
12112 * after encoders and crtc also have had their say. */
12113 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12114 pipe_config);
12115 if (base_bpp < 0)
12116 goto fail;
12117
12118 /*
12119 * Determine the real pipe dimensions. Note that stereo modes can
12120 * increase the actual pipe size due to the frame doubling and
12121 * insertion of additional space for blanks between the frame. This
12122 * is stored in the crtc timings. We use the requested mode to do this
12123 * computation to clearly distinguish it from the adjusted mode, which
12124 * can be changed by the connectors in the below retry loop.
12125 */
12126 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12127 &pipe_config->pipe_src_w,
12128 &pipe_config->pipe_src_h);
12129
12130 encoder_retry:
12131 /* Ensure the port clock defaults are reset when retrying. */
12132 pipe_config->port_clock = 0;
12133 pipe_config->pixel_multiplier = 1;
12134
12135 /* Fill in default crtc timings, allow encoders to overwrite them. */
12136 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12137 CRTC_STEREO_DOUBLE);
12138
12139 /* Pass our mode to the connectors and the CRTC to give them a chance to
12140 * adjust it according to limitations or connector properties, and also
12141 * a chance to reject the mode entirely.
12142 */
12143 for_each_connector_in_state(state, connector, connector_state, i) {
12144 if (connector_state->crtc != crtc)
12145 continue;
12146
12147 encoder = to_intel_encoder(connector_state->best_encoder);
12148
12149 if (!(encoder->compute_config(encoder, pipe_config))) {
12150 DRM_DEBUG_KMS("Encoder config failure\n");
12151 goto fail;
12152 }
12153 }
12154
12155 /* Set default port clock if not overwritten by the encoder. Needs to be
12156 * done afterwards in case the encoder adjusts the mode. */
12157 if (!pipe_config->port_clock)
12158 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12159 * pipe_config->pixel_multiplier;
12160
12161 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12162 if (ret < 0) {
12163 DRM_DEBUG_KMS("CRTC fixup failed\n");
12164 goto fail;
12165 }
12166
12167 if (ret == RETRY) {
12168 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12169 ret = -EINVAL;
12170 goto fail;
12171 }
12172
12173 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12174 retry = false;
12175 goto encoder_retry;
12176 }
12177
12178 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
12179 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12180 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12181
12182 fail:
12183 return ret;
12184 }
12185
12186 static bool intel_crtc_in_use(struct drm_crtc *crtc)
12187 {
12188 struct drm_encoder *encoder;
12189 struct drm_device *dev = crtc->dev;
12190
12191 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12192 if (encoder->crtc == crtc)
12193 return true;
12194
12195 return false;
12196 }
12197
12198 static void
12199 intel_modeset_update_state(struct drm_atomic_state *state)
12200 {
12201 struct drm_device *dev = state->dev;
12202 struct intel_encoder *intel_encoder;
12203 struct drm_crtc *crtc;
12204 struct drm_crtc_state *crtc_state;
12205 struct drm_connector *connector;
12206 int i;
12207
12208 intel_shared_dpll_commit(state);
12209
12210 for_each_intel_encoder(dev, intel_encoder) {
12211 if (!intel_encoder->base.crtc)
12212 continue;
12213
12214 crtc = intel_encoder->base.crtc;
12215 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12216 if (!crtc_state || !needs_modeset(crtc->state))
12217 continue;
12218
12219 intel_encoder->connectors_active = false;
12220 }
12221
12222 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12223
12224 /* Double check state. */
12225 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12226 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
12227
12228 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12229
12230 /* Update hwmode for vblank functions */
12231 if (crtc->state->active)
12232 crtc->hwmode = crtc->state->adjusted_mode;
12233 else
12234 crtc->hwmode.crtc_clock = 0;
12235 }
12236
12237 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12238 if (!connector->encoder || !connector->encoder->crtc)
12239 continue;
12240
12241 crtc = connector->encoder->crtc;
12242 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12243 if (!crtc_state || !needs_modeset(crtc->state))
12244 continue;
12245
12246 if (crtc->state->active) {
12247 intel_encoder = to_intel_encoder(connector->encoder);
12248 intel_encoder->connectors_active = true;
12249 }
12250 }
12251 }
12252
12253 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12254 {
12255 int diff;
12256
12257 if (clock1 == clock2)
12258 return true;
12259
12260 if (!clock1 || !clock2)
12261 return false;
12262
12263 diff = abs(clock1 - clock2);
12264
12265 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12266 return true;
12267
12268 return false;
12269 }
12270
12271 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12272 list_for_each_entry((intel_crtc), \
12273 &(dev)->mode_config.crtc_list, \
12274 base.head) \
12275 if (mask & (1 <<(intel_crtc)->pipe))
12276
12277
12278 static bool
12279 intel_compare_m_n(unsigned int m, unsigned int n,
12280 unsigned int m2, unsigned int n2,
12281 bool exact)
12282 {
12283 if (m == m2 && n == n2)
12284 return true;
12285
12286 if (exact || !m || !n || !m2 || !n2)
12287 return false;
12288
12289 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12290
12291 if (m > m2) {
12292 while (m > m2) {
12293 m2 <<= 1;
12294 n2 <<= 1;
12295 }
12296 } else if (m < m2) {
12297 while (m < m2) {
12298 m <<= 1;
12299 n <<= 1;
12300 }
12301 }
12302
12303 return m == m2 && n == n2;
12304 }
12305
12306 static bool
12307 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12308 struct intel_link_m_n *m2_n2,
12309 bool adjust)
12310 {
12311 if (m_n->tu == m2_n2->tu &&
12312 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12313 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12314 intel_compare_m_n(m_n->link_m, m_n->link_n,
12315 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12316 if (adjust)
12317 *m2_n2 = *m_n;
12318
12319 return true;
12320 }
12321
12322 return false;
12323 }
12324
12325 static bool
12326 intel_pipe_config_compare(struct drm_device *dev,
12327 struct intel_crtc_state *current_config,
12328 struct intel_crtc_state *pipe_config,
12329 bool adjust)
12330 {
12331 bool ret = true;
12332
12333 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12334 do { \
12335 if (!adjust) \
12336 DRM_ERROR(fmt, ##__VA_ARGS__); \
12337 else \
12338 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12339 } while (0)
12340
12341 #define PIPE_CONF_CHECK_X(name) \
12342 if (current_config->name != pipe_config->name) { \
12343 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12344 "(expected 0x%08x, found 0x%08x)\n", \
12345 current_config->name, \
12346 pipe_config->name); \
12347 ret = false; \
12348 }
12349
12350 #define PIPE_CONF_CHECK_I(name) \
12351 if (current_config->name != pipe_config->name) { \
12352 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12353 "(expected %i, found %i)\n", \
12354 current_config->name, \
12355 pipe_config->name); \
12356 ret = false; \
12357 }
12358
12359 #define PIPE_CONF_CHECK_M_N(name) \
12360 if (!intel_compare_link_m_n(&current_config->name, \
12361 &pipe_config->name,\
12362 adjust)) { \
12363 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12364 "(expected tu %i gmch %i/%i link %i/%i, " \
12365 "found tu %i, gmch %i/%i link %i/%i)\n", \
12366 current_config->name.tu, \
12367 current_config->name.gmch_m, \
12368 current_config->name.gmch_n, \
12369 current_config->name.link_m, \
12370 current_config->name.link_n, \
12371 pipe_config->name.tu, \
12372 pipe_config->name.gmch_m, \
12373 pipe_config->name.gmch_n, \
12374 pipe_config->name.link_m, \
12375 pipe_config->name.link_n); \
12376 ret = false; \
12377 }
12378
12379 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12380 if (!intel_compare_link_m_n(&current_config->name, \
12381 &pipe_config->name, adjust) && \
12382 !intel_compare_link_m_n(&current_config->alt_name, \
12383 &pipe_config->name, adjust)) { \
12384 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12385 "(expected tu %i gmch %i/%i link %i/%i, " \
12386 "or tu %i gmch %i/%i link %i/%i, " \
12387 "found tu %i, gmch %i/%i link %i/%i)\n", \
12388 current_config->name.tu, \
12389 current_config->name.gmch_m, \
12390 current_config->name.gmch_n, \
12391 current_config->name.link_m, \
12392 current_config->name.link_n, \
12393 current_config->alt_name.tu, \
12394 current_config->alt_name.gmch_m, \
12395 current_config->alt_name.gmch_n, \
12396 current_config->alt_name.link_m, \
12397 current_config->alt_name.link_n, \
12398 pipe_config->name.tu, \
12399 pipe_config->name.gmch_m, \
12400 pipe_config->name.gmch_n, \
12401 pipe_config->name.link_m, \
12402 pipe_config->name.link_n); \
12403 ret = false; \
12404 }
12405
12406 /* This is required for BDW+ where there is only one set of registers for
12407 * switching between high and low RR.
12408 * This macro can be used whenever a comparison has to be made between one
12409 * hw state and multiple sw state variables.
12410 */
12411 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12412 if ((current_config->name != pipe_config->name) && \
12413 (current_config->alt_name != pipe_config->name)) { \
12414 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12415 "(expected %i or %i, found %i)\n", \
12416 current_config->name, \
12417 current_config->alt_name, \
12418 pipe_config->name); \
12419 ret = false; \
12420 }
12421
12422 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12423 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12424 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12425 "(expected %i, found %i)\n", \
12426 current_config->name & (mask), \
12427 pipe_config->name & (mask)); \
12428 ret = false; \
12429 }
12430
12431 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12432 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12433 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12434 "(expected %i, found %i)\n", \
12435 current_config->name, \
12436 pipe_config->name); \
12437 ret = false; \
12438 }
12439
12440 #define PIPE_CONF_QUIRK(quirk) \
12441 ((current_config->quirks | pipe_config->quirks) & (quirk))
12442
12443 PIPE_CONF_CHECK_I(cpu_transcoder);
12444
12445 PIPE_CONF_CHECK_I(has_pch_encoder);
12446 PIPE_CONF_CHECK_I(fdi_lanes);
12447 PIPE_CONF_CHECK_M_N(fdi_m_n);
12448
12449 PIPE_CONF_CHECK_I(has_dp_encoder);
12450
12451 if (INTEL_INFO(dev)->gen < 8) {
12452 PIPE_CONF_CHECK_M_N(dp_m_n);
12453
12454 PIPE_CONF_CHECK_I(has_drrs);
12455 if (current_config->has_drrs)
12456 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12457 } else
12458 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12459
12460 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12461 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12462 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12463 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12464 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12465 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12466
12467 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12468 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12469 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12470 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12471 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12472 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12473
12474 PIPE_CONF_CHECK_I(pixel_multiplier);
12475 PIPE_CONF_CHECK_I(has_hdmi_sink);
12476 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12477 IS_VALLEYVIEW(dev))
12478 PIPE_CONF_CHECK_I(limited_color_range);
12479 PIPE_CONF_CHECK_I(has_infoframe);
12480
12481 PIPE_CONF_CHECK_I(has_audio);
12482
12483 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12484 DRM_MODE_FLAG_INTERLACE);
12485
12486 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12487 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12488 DRM_MODE_FLAG_PHSYNC);
12489 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12490 DRM_MODE_FLAG_NHSYNC);
12491 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12492 DRM_MODE_FLAG_PVSYNC);
12493 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12494 DRM_MODE_FLAG_NVSYNC);
12495 }
12496
12497 PIPE_CONF_CHECK_I(pipe_src_w);
12498 PIPE_CONF_CHECK_I(pipe_src_h);
12499
12500 PIPE_CONF_CHECK_I(gmch_pfit.control);
12501 /* pfit ratios are autocomputed by the hw on gen4+ */
12502 if (INTEL_INFO(dev)->gen < 4)
12503 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12504 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12505
12506 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12507 if (current_config->pch_pfit.enabled) {
12508 PIPE_CONF_CHECK_I(pch_pfit.pos);
12509 PIPE_CONF_CHECK_I(pch_pfit.size);
12510 }
12511
12512 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12513
12514 /* BDW+ don't expose a synchronous way to read the state */
12515 if (IS_HASWELL(dev))
12516 PIPE_CONF_CHECK_I(ips_enabled);
12517
12518 PIPE_CONF_CHECK_I(double_wide);
12519
12520 PIPE_CONF_CHECK_X(ddi_pll_sel);
12521
12522 PIPE_CONF_CHECK_I(shared_dpll);
12523 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12524 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12525 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12526 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12527 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12528 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12529 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12530 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12531
12532 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12533 PIPE_CONF_CHECK_I(pipe_bpp);
12534
12535 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12536 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12537
12538 #undef PIPE_CONF_CHECK_X
12539 #undef PIPE_CONF_CHECK_I
12540 #undef PIPE_CONF_CHECK_I_ALT
12541 #undef PIPE_CONF_CHECK_FLAGS
12542 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12543 #undef PIPE_CONF_QUIRK
12544 #undef INTEL_ERR_OR_DBG_KMS
12545
12546 return ret;
12547 }
12548
12549 static void check_wm_state(struct drm_device *dev)
12550 {
12551 struct drm_i915_private *dev_priv = dev->dev_private;
12552 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12553 struct intel_crtc *intel_crtc;
12554 int plane;
12555
12556 if (INTEL_INFO(dev)->gen < 9)
12557 return;
12558
12559 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12560 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12561
12562 for_each_intel_crtc(dev, intel_crtc) {
12563 struct skl_ddb_entry *hw_entry, *sw_entry;
12564 const enum pipe pipe = intel_crtc->pipe;
12565
12566 if (!intel_crtc->active)
12567 continue;
12568
12569 /* planes */
12570 for_each_plane(dev_priv, pipe, plane) {
12571 hw_entry = &hw_ddb.plane[pipe][plane];
12572 sw_entry = &sw_ddb->plane[pipe][plane];
12573
12574 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12575 continue;
12576
12577 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12578 "(expected (%u,%u), found (%u,%u))\n",
12579 pipe_name(pipe), plane + 1,
12580 sw_entry->start, sw_entry->end,
12581 hw_entry->start, hw_entry->end);
12582 }
12583
12584 /* cursor */
12585 hw_entry = &hw_ddb.cursor[pipe];
12586 sw_entry = &sw_ddb->cursor[pipe];
12587
12588 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12589 continue;
12590
12591 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12592 "(expected (%u,%u), found (%u,%u))\n",
12593 pipe_name(pipe),
12594 sw_entry->start, sw_entry->end,
12595 hw_entry->start, hw_entry->end);
12596 }
12597 }
12598
12599 static void
12600 check_connector_state(struct drm_device *dev,
12601 struct drm_atomic_state *old_state)
12602 {
12603 struct drm_connector_state *old_conn_state;
12604 struct drm_connector *connector;
12605 int i;
12606
12607 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12608 struct drm_encoder *encoder = connector->encoder;
12609 struct drm_connector_state *state = connector->state;
12610
12611 /* This also checks the encoder/connector hw state with the
12612 * ->get_hw_state callbacks. */
12613 intel_connector_check_state(to_intel_connector(connector));
12614
12615 I915_STATE_WARN(state->best_encoder != encoder,
12616 "connector's atomic encoder doesn't match legacy encoder\n");
12617 }
12618 }
12619
12620 static void
12621 check_encoder_state(struct drm_device *dev)
12622 {
12623 struct intel_encoder *encoder;
12624 struct intel_connector *connector;
12625
12626 for_each_intel_encoder(dev, encoder) {
12627 bool enabled = false;
12628 enum pipe pipe;
12629
12630 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12631 encoder->base.base.id,
12632 encoder->base.name);
12633
12634 for_each_intel_connector(dev, connector) {
12635 if (connector->base.state->best_encoder != &encoder->base)
12636 continue;
12637 enabled = true;
12638
12639 I915_STATE_WARN(connector->base.state->crtc !=
12640 encoder->base.crtc,
12641 "connector's crtc doesn't match encoder crtc\n");
12642 }
12643
12644 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12645 "encoder's enabled state mismatch "
12646 "(expected %i, found %i)\n",
12647 !!encoder->base.crtc, enabled);
12648
12649 if (!encoder->base.crtc) {
12650 bool active;
12651
12652 active = encoder->get_hw_state(encoder, &pipe);
12653 I915_STATE_WARN(active,
12654 "encoder detached but still enabled on pipe %c.\n",
12655 pipe_name(pipe));
12656 }
12657 }
12658 }
12659
12660 static void
12661 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12662 {
12663 struct drm_i915_private *dev_priv = dev->dev_private;
12664 struct intel_encoder *encoder;
12665 struct drm_crtc_state *old_crtc_state;
12666 struct drm_crtc *crtc;
12667 int i;
12668
12669 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12671 struct intel_crtc_state *pipe_config, *sw_config;
12672 bool active;
12673
12674 if (!needs_modeset(crtc->state))
12675 continue;
12676
12677 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12678 pipe_config = to_intel_crtc_state(old_crtc_state);
12679 memset(pipe_config, 0, sizeof(*pipe_config));
12680 pipe_config->base.crtc = crtc;
12681 pipe_config->base.state = old_state;
12682
12683 DRM_DEBUG_KMS("[CRTC:%d]\n",
12684 crtc->base.id);
12685
12686 active = dev_priv->display.get_pipe_config(intel_crtc,
12687 pipe_config);
12688
12689 /* hw state is inconsistent with the pipe quirk */
12690 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12691 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12692 active = crtc->state->active;
12693
12694 I915_STATE_WARN(crtc->state->active != active,
12695 "crtc active state doesn't match with hw state "
12696 "(expected %i, found %i)\n", crtc->state->active, active);
12697
12698 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12699 "transitional active state does not match atomic hw state "
12700 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12701
12702 for_each_encoder_on_crtc(dev, crtc, encoder) {
12703 enum pipe pipe;
12704
12705 active = encoder->get_hw_state(encoder, &pipe);
12706 I915_STATE_WARN(active != crtc->state->active,
12707 "[ENCODER:%i] active %i with crtc active %i\n",
12708 encoder->base.base.id, active, crtc->state->active);
12709
12710 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12711 "Encoder connected to wrong pipe %c\n",
12712 pipe_name(pipe));
12713
12714 if (active)
12715 encoder->get_config(encoder, pipe_config);
12716 }
12717
12718 if (!crtc->state->active)
12719 continue;
12720
12721 sw_config = to_intel_crtc_state(crtc->state);
12722 if (!intel_pipe_config_compare(dev, sw_config,
12723 pipe_config, false)) {
12724 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12725 intel_dump_pipe_config(intel_crtc, pipe_config,
12726 "[hw state]");
12727 intel_dump_pipe_config(intel_crtc, sw_config,
12728 "[sw state]");
12729 }
12730 }
12731 }
12732
12733 static void
12734 check_shared_dpll_state(struct drm_device *dev)
12735 {
12736 struct drm_i915_private *dev_priv = dev->dev_private;
12737 struct intel_crtc *crtc;
12738 struct intel_dpll_hw_state dpll_hw_state;
12739 int i;
12740
12741 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12742 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12743 int enabled_crtcs = 0, active_crtcs = 0;
12744 bool active;
12745
12746 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12747
12748 DRM_DEBUG_KMS("%s\n", pll->name);
12749
12750 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12751
12752 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12753 "more active pll users than references: %i vs %i\n",
12754 pll->active, hweight32(pll->config.crtc_mask));
12755 I915_STATE_WARN(pll->active && !pll->on,
12756 "pll in active use but not on in sw tracking\n");
12757 I915_STATE_WARN(pll->on && !pll->active,
12758 "pll in on but not on in use in sw tracking\n");
12759 I915_STATE_WARN(pll->on != active,
12760 "pll on state mismatch (expected %i, found %i)\n",
12761 pll->on, active);
12762
12763 for_each_intel_crtc(dev, crtc) {
12764 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12765 enabled_crtcs++;
12766 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12767 active_crtcs++;
12768 }
12769 I915_STATE_WARN(pll->active != active_crtcs,
12770 "pll active crtcs mismatch (expected %i, found %i)\n",
12771 pll->active, active_crtcs);
12772 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12773 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12774 hweight32(pll->config.crtc_mask), enabled_crtcs);
12775
12776 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12777 sizeof(dpll_hw_state)),
12778 "pll hw state mismatch\n");
12779 }
12780 }
12781
12782 static void
12783 intel_modeset_check_state(struct drm_device *dev,
12784 struct drm_atomic_state *old_state)
12785 {
12786 check_wm_state(dev);
12787 check_connector_state(dev, old_state);
12788 check_encoder_state(dev);
12789 check_crtc_state(dev, old_state);
12790 check_shared_dpll_state(dev);
12791 }
12792
12793 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12794 int dotclock)
12795 {
12796 /*
12797 * FDI already provided one idea for the dotclock.
12798 * Yell if the encoder disagrees.
12799 */
12800 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12801 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12802 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12803 }
12804
12805 static void update_scanline_offset(struct intel_crtc *crtc)
12806 {
12807 struct drm_device *dev = crtc->base.dev;
12808
12809 /*
12810 * The scanline counter increments at the leading edge of hsync.
12811 *
12812 * On most platforms it starts counting from vtotal-1 on the
12813 * first active line. That means the scanline counter value is
12814 * always one less than what we would expect. Ie. just after
12815 * start of vblank, which also occurs at start of hsync (on the
12816 * last active line), the scanline counter will read vblank_start-1.
12817 *
12818 * On gen2 the scanline counter starts counting from 1 instead
12819 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12820 * to keep the value positive), instead of adding one.
12821 *
12822 * On HSW+ the behaviour of the scanline counter depends on the output
12823 * type. For DP ports it behaves like most other platforms, but on HDMI
12824 * there's an extra 1 line difference. So we need to add two instead of
12825 * one to the value.
12826 */
12827 if (IS_GEN2(dev)) {
12828 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12829 int vtotal;
12830
12831 vtotal = mode->crtc_vtotal;
12832 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12833 vtotal /= 2;
12834
12835 crtc->scanline_offset = vtotal - 1;
12836 } else if (HAS_DDI(dev) &&
12837 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12838 crtc->scanline_offset = 2;
12839 } else
12840 crtc->scanline_offset = 1;
12841 }
12842
12843 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12844 {
12845 struct drm_device *dev = state->dev;
12846 struct drm_i915_private *dev_priv = to_i915(dev);
12847 struct intel_shared_dpll_config *shared_dpll = NULL;
12848 struct intel_crtc *intel_crtc;
12849 struct intel_crtc_state *intel_crtc_state;
12850 struct drm_crtc *crtc;
12851 struct drm_crtc_state *crtc_state;
12852 int i;
12853
12854 if (!dev_priv->display.crtc_compute_clock)
12855 return;
12856
12857 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12858 int dpll;
12859
12860 intel_crtc = to_intel_crtc(crtc);
12861 intel_crtc_state = to_intel_crtc_state(crtc_state);
12862 dpll = intel_crtc_state->shared_dpll;
12863
12864 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12865 continue;
12866
12867 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12868
12869 if (!shared_dpll)
12870 shared_dpll = intel_atomic_get_shared_dpll_state(state);
12871
12872 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12873 }
12874 }
12875
12876 /*
12877 * This implements the workaround described in the "notes" section of the mode
12878 * set sequence documentation. When going from no pipes or single pipe to
12879 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12880 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12881 */
12882 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12883 {
12884 struct drm_crtc_state *crtc_state;
12885 struct intel_crtc *intel_crtc;
12886 struct drm_crtc *crtc;
12887 struct intel_crtc_state *first_crtc_state = NULL;
12888 struct intel_crtc_state *other_crtc_state = NULL;
12889 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12890 int i;
12891
12892 /* look at all crtc's that are going to be enabled in during modeset */
12893 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12894 intel_crtc = to_intel_crtc(crtc);
12895
12896 if (!crtc_state->active || !needs_modeset(crtc_state))
12897 continue;
12898
12899 if (first_crtc_state) {
12900 other_crtc_state = to_intel_crtc_state(crtc_state);
12901 break;
12902 } else {
12903 first_crtc_state = to_intel_crtc_state(crtc_state);
12904 first_pipe = intel_crtc->pipe;
12905 }
12906 }
12907
12908 /* No workaround needed? */
12909 if (!first_crtc_state)
12910 return 0;
12911
12912 /* w/a possibly needed, check how many crtc's are already enabled. */
12913 for_each_intel_crtc(state->dev, intel_crtc) {
12914 struct intel_crtc_state *pipe_config;
12915
12916 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12917 if (IS_ERR(pipe_config))
12918 return PTR_ERR(pipe_config);
12919
12920 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12921
12922 if (!pipe_config->base.active ||
12923 needs_modeset(&pipe_config->base))
12924 continue;
12925
12926 /* 2 or more enabled crtcs means no need for w/a */
12927 if (enabled_pipe != INVALID_PIPE)
12928 return 0;
12929
12930 enabled_pipe = intel_crtc->pipe;
12931 }
12932
12933 if (enabled_pipe != INVALID_PIPE)
12934 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12935 else if (other_crtc_state)
12936 other_crtc_state->hsw_workaround_pipe = first_pipe;
12937
12938 return 0;
12939 }
12940
12941 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12942 {
12943 struct drm_crtc *crtc;
12944 struct drm_crtc_state *crtc_state;
12945 int ret = 0;
12946
12947 /* add all active pipes to the state */
12948 for_each_crtc(state->dev, crtc) {
12949 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12950 if (IS_ERR(crtc_state))
12951 return PTR_ERR(crtc_state);
12952
12953 if (!crtc_state->active || needs_modeset(crtc_state))
12954 continue;
12955
12956 crtc_state->mode_changed = true;
12957
12958 ret = drm_atomic_add_affected_connectors(state, crtc);
12959 if (ret)
12960 break;
12961
12962 ret = drm_atomic_add_affected_planes(state, crtc);
12963 if (ret)
12964 break;
12965 }
12966
12967 return ret;
12968 }
12969
12970
12971 static int intel_modeset_checks(struct drm_atomic_state *state)
12972 {
12973 struct drm_device *dev = state->dev;
12974 struct drm_i915_private *dev_priv = dev->dev_private;
12975 int ret;
12976
12977 if (!check_digital_port_conflicts(state)) {
12978 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12979 return -EINVAL;
12980 }
12981
12982 /*
12983 * See if the config requires any additional preparation, e.g.
12984 * to adjust global state with pipes off. We need to do this
12985 * here so we can get the modeset_pipe updated config for the new
12986 * mode set on this crtc. For other crtcs we need to use the
12987 * adjusted_mode bits in the crtc directly.
12988 */
12989 if (dev_priv->display.modeset_calc_cdclk) {
12990 unsigned int cdclk;
12991
12992 ret = dev_priv->display.modeset_calc_cdclk(state);
12993
12994 cdclk = to_intel_atomic_state(state)->cdclk;
12995 if (!ret && cdclk != dev_priv->cdclk_freq)
12996 ret = intel_modeset_all_pipes(state);
12997
12998 if (ret < 0)
12999 return ret;
13000 } else
13001 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13002
13003 intel_modeset_clear_plls(state);
13004
13005 if (IS_HASWELL(dev))
13006 return haswell_mode_set_planes_workaround(state);
13007
13008 return 0;
13009 }
13010
13011 /**
13012 * intel_atomic_check - validate state object
13013 * @dev: drm device
13014 * @state: state to validate
13015 */
13016 static int intel_atomic_check(struct drm_device *dev,
13017 struct drm_atomic_state *state)
13018 {
13019 struct drm_crtc *crtc;
13020 struct drm_crtc_state *crtc_state;
13021 int ret, i;
13022 bool any_ms = false;
13023
13024 ret = drm_atomic_helper_check_modeset(dev, state);
13025 if (ret)
13026 return ret;
13027
13028 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13029 struct intel_crtc_state *pipe_config =
13030 to_intel_crtc_state(crtc_state);
13031
13032 /* Catch I915_MODE_FLAG_INHERITED */
13033 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13034 crtc_state->mode_changed = true;
13035
13036 if (!crtc_state->enable) {
13037 if (needs_modeset(crtc_state))
13038 any_ms = true;
13039 continue;
13040 }
13041
13042 if (!needs_modeset(crtc_state))
13043 continue;
13044
13045 /* FIXME: For only active_changed we shouldn't need to do any
13046 * state recomputation at all. */
13047
13048 ret = drm_atomic_add_affected_connectors(state, crtc);
13049 if (ret)
13050 return ret;
13051
13052 ret = intel_modeset_pipe_config(crtc, pipe_config);
13053 if (ret)
13054 return ret;
13055
13056 if (i915.fastboot &&
13057 intel_pipe_config_compare(state->dev,
13058 to_intel_crtc_state(crtc->state),
13059 pipe_config, true)) {
13060 crtc_state->mode_changed = false;
13061 }
13062
13063 if (needs_modeset(crtc_state)) {
13064 any_ms = true;
13065
13066 ret = drm_atomic_add_affected_planes(state, crtc);
13067 if (ret)
13068 return ret;
13069 }
13070
13071 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13072 needs_modeset(crtc_state) ?
13073 "[modeset]" : "[fastset]");
13074 }
13075
13076 if (any_ms) {
13077 ret = intel_modeset_checks(state);
13078
13079 if (ret)
13080 return ret;
13081 } else
13082 to_intel_atomic_state(state)->cdclk =
13083 to_i915(state->dev)->cdclk_freq;
13084
13085 return drm_atomic_helper_check_planes(state->dev, state);
13086 }
13087
13088 /**
13089 * intel_atomic_commit - commit validated state object
13090 * @dev: DRM device
13091 * @state: the top-level driver state object
13092 * @async: asynchronous commit
13093 *
13094 * This function commits a top-level state object that has been validated
13095 * with drm_atomic_helper_check().
13096 *
13097 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13098 * we can only handle plane-related operations and do not yet support
13099 * asynchronous commit.
13100 *
13101 * RETURNS
13102 * Zero for success or -errno.
13103 */
13104 static int intel_atomic_commit(struct drm_device *dev,
13105 struct drm_atomic_state *state,
13106 bool async)
13107 {
13108 struct drm_i915_private *dev_priv = dev->dev_private;
13109 struct drm_crtc *crtc;
13110 struct drm_crtc_state *crtc_state;
13111 int ret = 0;
13112 int i;
13113 bool any_ms = false;
13114
13115 if (async) {
13116 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13117 return -EINVAL;
13118 }
13119
13120 ret = drm_atomic_helper_prepare_planes(dev, state);
13121 if (ret)
13122 return ret;
13123
13124 drm_atomic_helper_swap_state(dev, state);
13125
13126 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13128
13129 if (!needs_modeset(crtc->state))
13130 continue;
13131
13132 any_ms = true;
13133 intel_pre_plane_update(intel_crtc);
13134
13135 if (crtc_state->active) {
13136 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13137 dev_priv->display.crtc_disable(crtc);
13138 intel_crtc->active = false;
13139 intel_disable_shared_dpll(intel_crtc);
13140 }
13141 }
13142
13143 /* Only after disabling all output pipelines that will be changed can we
13144 * update the the output configuration. */
13145 intel_modeset_update_state(state);
13146
13147 /* The state has been swaped above, so state actually contains the
13148 * old state now. */
13149 if (any_ms)
13150 modeset_update_crtc_power_domains(state);
13151
13152 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13153 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13155 bool modeset = needs_modeset(crtc->state);
13156
13157 if (modeset && crtc->state->active) {
13158 update_scanline_offset(to_intel_crtc(crtc));
13159 dev_priv->display.crtc_enable(crtc);
13160 }
13161
13162 if (!modeset)
13163 intel_pre_plane_update(intel_crtc);
13164
13165 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13166 intel_post_plane_update(intel_crtc);
13167 }
13168
13169 /* FIXME: add subpixel order */
13170
13171 drm_atomic_helper_wait_for_vblanks(dev, state);
13172 drm_atomic_helper_cleanup_planes(dev, state);
13173
13174 if (any_ms)
13175 intel_modeset_check_state(dev, state);
13176
13177 drm_atomic_state_free(state);
13178
13179 return 0;
13180 }
13181
13182 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13183 {
13184 struct drm_device *dev = crtc->dev;
13185 struct drm_atomic_state *state;
13186 struct drm_crtc_state *crtc_state;
13187 int ret;
13188
13189 state = drm_atomic_state_alloc(dev);
13190 if (!state) {
13191 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13192 crtc->base.id);
13193 return;
13194 }
13195
13196 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13197
13198 retry:
13199 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13200 ret = PTR_ERR_OR_ZERO(crtc_state);
13201 if (!ret) {
13202 if (!crtc_state->active)
13203 goto out;
13204
13205 crtc_state->mode_changed = true;
13206 ret = drm_atomic_commit(state);
13207 }
13208
13209 if (ret == -EDEADLK) {
13210 drm_atomic_state_clear(state);
13211 drm_modeset_backoff(state->acquire_ctx);
13212 goto retry;
13213 }
13214
13215 if (ret)
13216 out:
13217 drm_atomic_state_free(state);
13218 }
13219
13220 #undef for_each_intel_crtc_masked
13221
13222 static const struct drm_crtc_funcs intel_crtc_funcs = {
13223 .gamma_set = intel_crtc_gamma_set,
13224 .set_config = drm_atomic_helper_set_config,
13225 .destroy = intel_crtc_destroy,
13226 .page_flip = intel_crtc_page_flip,
13227 .atomic_duplicate_state = intel_crtc_duplicate_state,
13228 .atomic_destroy_state = intel_crtc_destroy_state,
13229 };
13230
13231 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13232 struct intel_shared_dpll *pll,
13233 struct intel_dpll_hw_state *hw_state)
13234 {
13235 uint32_t val;
13236
13237 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13238 return false;
13239
13240 val = I915_READ(PCH_DPLL(pll->id));
13241 hw_state->dpll = val;
13242 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13243 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13244
13245 return val & DPLL_VCO_ENABLE;
13246 }
13247
13248 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13249 struct intel_shared_dpll *pll)
13250 {
13251 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13252 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13253 }
13254
13255 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13256 struct intel_shared_dpll *pll)
13257 {
13258 /* PCH refclock must be enabled first */
13259 ibx_assert_pch_refclk_enabled(dev_priv);
13260
13261 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13262
13263 /* Wait for the clocks to stabilize. */
13264 POSTING_READ(PCH_DPLL(pll->id));
13265 udelay(150);
13266
13267 /* The pixel multiplier can only be updated once the
13268 * DPLL is enabled and the clocks are stable.
13269 *
13270 * So write it again.
13271 */
13272 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13273 POSTING_READ(PCH_DPLL(pll->id));
13274 udelay(200);
13275 }
13276
13277 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13278 struct intel_shared_dpll *pll)
13279 {
13280 struct drm_device *dev = dev_priv->dev;
13281 struct intel_crtc *crtc;
13282
13283 /* Make sure no transcoder isn't still depending on us. */
13284 for_each_intel_crtc(dev, crtc) {
13285 if (intel_crtc_to_shared_dpll(crtc) == pll)
13286 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13287 }
13288
13289 I915_WRITE(PCH_DPLL(pll->id), 0);
13290 POSTING_READ(PCH_DPLL(pll->id));
13291 udelay(200);
13292 }
13293
13294 static char *ibx_pch_dpll_names[] = {
13295 "PCH DPLL A",
13296 "PCH DPLL B",
13297 };
13298
13299 static void ibx_pch_dpll_init(struct drm_device *dev)
13300 {
13301 struct drm_i915_private *dev_priv = dev->dev_private;
13302 int i;
13303
13304 dev_priv->num_shared_dpll = 2;
13305
13306 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13307 dev_priv->shared_dplls[i].id = i;
13308 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13309 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13310 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13311 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13312 dev_priv->shared_dplls[i].get_hw_state =
13313 ibx_pch_dpll_get_hw_state;
13314 }
13315 }
13316
13317 static void intel_shared_dpll_init(struct drm_device *dev)
13318 {
13319 struct drm_i915_private *dev_priv = dev->dev_private;
13320
13321 intel_update_cdclk(dev);
13322
13323 if (HAS_DDI(dev))
13324 intel_ddi_pll_init(dev);
13325 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13326 ibx_pch_dpll_init(dev);
13327 else
13328 dev_priv->num_shared_dpll = 0;
13329
13330 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13331 }
13332
13333 /**
13334 * intel_prepare_plane_fb - Prepare fb for usage on plane
13335 * @plane: drm plane to prepare for
13336 * @fb: framebuffer to prepare for presentation
13337 *
13338 * Prepares a framebuffer for usage on a display plane. Generally this
13339 * involves pinning the underlying object and updating the frontbuffer tracking
13340 * bits. Some older platforms need special physical address handling for
13341 * cursor planes.
13342 *
13343 * Returns 0 on success, negative error code on failure.
13344 */
13345 int
13346 intel_prepare_plane_fb(struct drm_plane *plane,
13347 struct drm_framebuffer *fb,
13348 const struct drm_plane_state *new_state)
13349 {
13350 struct drm_device *dev = plane->dev;
13351 struct intel_plane *intel_plane = to_intel_plane(plane);
13352 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13353 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13354 int ret = 0;
13355
13356 if (!obj)
13357 return 0;
13358
13359 mutex_lock(&dev->struct_mutex);
13360
13361 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13362 INTEL_INFO(dev)->cursor_needs_physical) {
13363 int align = IS_I830(dev) ? 16 * 1024 : 256;
13364 ret = i915_gem_object_attach_phys(obj, align);
13365 if (ret)
13366 DRM_DEBUG_KMS("failed to attach phys object\n");
13367 } else {
13368 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13369 }
13370
13371 if (ret == 0)
13372 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13373
13374 mutex_unlock(&dev->struct_mutex);
13375
13376 return ret;
13377 }
13378
13379 /**
13380 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13381 * @plane: drm plane to clean up for
13382 * @fb: old framebuffer that was on plane
13383 *
13384 * Cleans up a framebuffer that has just been removed from a plane.
13385 */
13386 void
13387 intel_cleanup_plane_fb(struct drm_plane *plane,
13388 struct drm_framebuffer *fb,
13389 const struct drm_plane_state *old_state)
13390 {
13391 struct drm_device *dev = plane->dev;
13392 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13393
13394 if (WARN_ON(!obj))
13395 return;
13396
13397 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13398 !INTEL_INFO(dev)->cursor_needs_physical) {
13399 mutex_lock(&dev->struct_mutex);
13400 intel_unpin_fb_obj(fb, old_state);
13401 mutex_unlock(&dev->struct_mutex);
13402 }
13403 }
13404
13405 int
13406 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13407 {
13408 int max_scale;
13409 struct drm_device *dev;
13410 struct drm_i915_private *dev_priv;
13411 int crtc_clock, cdclk;
13412
13413 if (!intel_crtc || !crtc_state)
13414 return DRM_PLANE_HELPER_NO_SCALING;
13415
13416 dev = intel_crtc->base.dev;
13417 dev_priv = dev->dev_private;
13418 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13419 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13420
13421 if (!crtc_clock || !cdclk)
13422 return DRM_PLANE_HELPER_NO_SCALING;
13423
13424 /*
13425 * skl max scale is lower of:
13426 * close to 3 but not 3, -1 is for that purpose
13427 * or
13428 * cdclk/crtc_clock
13429 */
13430 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13431
13432 return max_scale;
13433 }
13434
13435 static int
13436 intel_check_primary_plane(struct drm_plane *plane,
13437 struct intel_crtc_state *crtc_state,
13438 struct intel_plane_state *state)
13439 {
13440 struct drm_crtc *crtc = state->base.crtc;
13441 struct drm_framebuffer *fb = state->base.fb;
13442 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13443 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13444 bool can_position = false;
13445
13446 /* use scaler when colorkey is not required */
13447 if (INTEL_INFO(plane->dev)->gen >= 9 &&
13448 state->ckey.flags == I915_SET_COLORKEY_NONE) {
13449 min_scale = 1;
13450 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13451 can_position = true;
13452 }
13453
13454 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13455 &state->dst, &state->clip,
13456 min_scale, max_scale,
13457 can_position, true,
13458 &state->visible);
13459 }
13460
13461 static void
13462 intel_commit_primary_plane(struct drm_plane *plane,
13463 struct intel_plane_state *state)
13464 {
13465 struct drm_crtc *crtc = state->base.crtc;
13466 struct drm_framebuffer *fb = state->base.fb;
13467 struct drm_device *dev = plane->dev;
13468 struct drm_i915_private *dev_priv = dev->dev_private;
13469 struct intel_crtc *intel_crtc;
13470 struct drm_rect *src = &state->src;
13471
13472 crtc = crtc ? crtc : plane->crtc;
13473 intel_crtc = to_intel_crtc(crtc);
13474
13475 plane->fb = fb;
13476 crtc->x = src->x1 >> 16;
13477 crtc->y = src->y1 >> 16;
13478
13479 if (!crtc->state->active)
13480 return;
13481
13482 if (state->visible)
13483 /* FIXME: kill this fastboot hack */
13484 intel_update_pipe_size(intel_crtc);
13485
13486 dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
13487 }
13488
13489 static void
13490 intel_disable_primary_plane(struct drm_plane *plane,
13491 struct drm_crtc *crtc)
13492 {
13493 struct drm_device *dev = plane->dev;
13494 struct drm_i915_private *dev_priv = dev->dev_private;
13495
13496 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13497 }
13498
13499 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13500 struct drm_crtc_state *old_crtc_state)
13501 {
13502 struct drm_device *dev = crtc->dev;
13503 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13504
13505 if (intel_crtc->atomic.update_wm_pre)
13506 intel_update_watermarks(crtc);
13507
13508 /* Perform vblank evasion around commit operation */
13509 if (crtc->state->active)
13510 intel_pipe_update_start(intel_crtc, &intel_crtc->start_vbl_count);
13511
13512 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13513 skl_detach_scalers(intel_crtc);
13514 }
13515
13516 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13517 struct drm_crtc_state *old_crtc_state)
13518 {
13519 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13520
13521 if (crtc->state->active)
13522 intel_pipe_update_end(intel_crtc, intel_crtc->start_vbl_count);
13523 }
13524
13525 /**
13526 * intel_plane_destroy - destroy a plane
13527 * @plane: plane to destroy
13528 *
13529 * Common destruction function for all types of planes (primary, cursor,
13530 * sprite).
13531 */
13532 void intel_plane_destroy(struct drm_plane *plane)
13533 {
13534 struct intel_plane *intel_plane = to_intel_plane(plane);
13535 drm_plane_cleanup(plane);
13536 kfree(intel_plane);
13537 }
13538
13539 const struct drm_plane_funcs intel_plane_funcs = {
13540 .update_plane = drm_atomic_helper_update_plane,
13541 .disable_plane = drm_atomic_helper_disable_plane,
13542 .destroy = intel_plane_destroy,
13543 .set_property = drm_atomic_helper_plane_set_property,
13544 .atomic_get_property = intel_plane_atomic_get_property,
13545 .atomic_set_property = intel_plane_atomic_set_property,
13546 .atomic_duplicate_state = intel_plane_duplicate_state,
13547 .atomic_destroy_state = intel_plane_destroy_state,
13548
13549 };
13550
13551 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13552 int pipe)
13553 {
13554 struct intel_plane *primary;
13555 struct intel_plane_state *state;
13556 const uint32_t *intel_primary_formats;
13557 int num_formats;
13558
13559 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13560 if (primary == NULL)
13561 return NULL;
13562
13563 state = intel_create_plane_state(&primary->base);
13564 if (!state) {
13565 kfree(primary);
13566 return NULL;
13567 }
13568 primary->base.state = &state->base;
13569
13570 primary->can_scale = false;
13571 primary->max_downscale = 1;
13572 if (INTEL_INFO(dev)->gen >= 9) {
13573 primary->can_scale = true;
13574 state->scaler_id = -1;
13575 }
13576 primary->pipe = pipe;
13577 primary->plane = pipe;
13578 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13579 primary->check_plane = intel_check_primary_plane;
13580 primary->commit_plane = intel_commit_primary_plane;
13581 primary->disable_plane = intel_disable_primary_plane;
13582 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13583 primary->plane = !pipe;
13584
13585 if (INTEL_INFO(dev)->gen >= 9) {
13586 intel_primary_formats = skl_primary_formats;
13587 num_formats = ARRAY_SIZE(skl_primary_formats);
13588 } else if (INTEL_INFO(dev)->gen >= 4) {
13589 intel_primary_formats = i965_primary_formats;
13590 num_formats = ARRAY_SIZE(i965_primary_formats);
13591 } else {
13592 intel_primary_formats = i8xx_primary_formats;
13593 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13594 }
13595
13596 drm_universal_plane_init(dev, &primary->base, 0,
13597 &intel_plane_funcs,
13598 intel_primary_formats, num_formats,
13599 DRM_PLANE_TYPE_PRIMARY);
13600
13601 if (INTEL_INFO(dev)->gen >= 4)
13602 intel_create_rotation_property(dev, primary);
13603
13604 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13605
13606 return &primary->base;
13607 }
13608
13609 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13610 {
13611 if (!dev->mode_config.rotation_property) {
13612 unsigned long flags = BIT(DRM_ROTATE_0) |
13613 BIT(DRM_ROTATE_180);
13614
13615 if (INTEL_INFO(dev)->gen >= 9)
13616 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13617
13618 dev->mode_config.rotation_property =
13619 drm_mode_create_rotation_property(dev, flags);
13620 }
13621 if (dev->mode_config.rotation_property)
13622 drm_object_attach_property(&plane->base.base,
13623 dev->mode_config.rotation_property,
13624 plane->base.state->rotation);
13625 }
13626
13627 static int
13628 intel_check_cursor_plane(struct drm_plane *plane,
13629 struct intel_crtc_state *crtc_state,
13630 struct intel_plane_state *state)
13631 {
13632 struct drm_crtc *crtc = crtc_state->base.crtc;
13633 struct drm_framebuffer *fb = state->base.fb;
13634 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13635 unsigned stride;
13636 int ret;
13637
13638 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13639 &state->dst, &state->clip,
13640 DRM_PLANE_HELPER_NO_SCALING,
13641 DRM_PLANE_HELPER_NO_SCALING,
13642 true, true, &state->visible);
13643 if (ret)
13644 return ret;
13645
13646 /* if we want to turn off the cursor ignore width and height */
13647 if (!obj)
13648 return 0;
13649
13650 /* Check for which cursor types we support */
13651 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13652 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13653 state->base.crtc_w, state->base.crtc_h);
13654 return -EINVAL;
13655 }
13656
13657 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13658 if (obj->base.size < stride * state->base.crtc_h) {
13659 DRM_DEBUG_KMS("buffer is too small\n");
13660 return -ENOMEM;
13661 }
13662
13663 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13664 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13665 return -EINVAL;
13666 }
13667
13668 return 0;
13669 }
13670
13671 static void
13672 intel_disable_cursor_plane(struct drm_plane *plane,
13673 struct drm_crtc *crtc)
13674 {
13675 intel_crtc_update_cursor(crtc, false);
13676 }
13677
13678 static void
13679 intel_commit_cursor_plane(struct drm_plane *plane,
13680 struct intel_plane_state *state)
13681 {
13682 struct drm_crtc *crtc = state->base.crtc;
13683 struct drm_device *dev = plane->dev;
13684 struct intel_crtc *intel_crtc;
13685 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13686 uint32_t addr;
13687
13688 crtc = crtc ? crtc : plane->crtc;
13689 intel_crtc = to_intel_crtc(crtc);
13690
13691 plane->fb = state->base.fb;
13692 crtc->cursor_x = state->base.crtc_x;
13693 crtc->cursor_y = state->base.crtc_y;
13694
13695 if (intel_crtc->cursor_bo == obj)
13696 goto update;
13697
13698 if (!obj)
13699 addr = 0;
13700 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13701 addr = i915_gem_obj_ggtt_offset(obj);
13702 else
13703 addr = obj->phys_handle->busaddr;
13704
13705 intel_crtc->cursor_addr = addr;
13706 intel_crtc->cursor_bo = obj;
13707
13708 update:
13709 if (crtc->state->active)
13710 intel_crtc_update_cursor(crtc, state->visible);
13711 }
13712
13713 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13714 int pipe)
13715 {
13716 struct intel_plane *cursor;
13717 struct intel_plane_state *state;
13718
13719 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13720 if (cursor == NULL)
13721 return NULL;
13722
13723 state = intel_create_plane_state(&cursor->base);
13724 if (!state) {
13725 kfree(cursor);
13726 return NULL;
13727 }
13728 cursor->base.state = &state->base;
13729
13730 cursor->can_scale = false;
13731 cursor->max_downscale = 1;
13732 cursor->pipe = pipe;
13733 cursor->plane = pipe;
13734 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13735 cursor->check_plane = intel_check_cursor_plane;
13736 cursor->commit_plane = intel_commit_cursor_plane;
13737 cursor->disable_plane = intel_disable_cursor_plane;
13738
13739 drm_universal_plane_init(dev, &cursor->base, 0,
13740 &intel_plane_funcs,
13741 intel_cursor_formats,
13742 ARRAY_SIZE(intel_cursor_formats),
13743 DRM_PLANE_TYPE_CURSOR);
13744
13745 if (INTEL_INFO(dev)->gen >= 4) {
13746 if (!dev->mode_config.rotation_property)
13747 dev->mode_config.rotation_property =
13748 drm_mode_create_rotation_property(dev,
13749 BIT(DRM_ROTATE_0) |
13750 BIT(DRM_ROTATE_180));
13751 if (dev->mode_config.rotation_property)
13752 drm_object_attach_property(&cursor->base.base,
13753 dev->mode_config.rotation_property,
13754 state->base.rotation);
13755 }
13756
13757 if (INTEL_INFO(dev)->gen >=9)
13758 state->scaler_id = -1;
13759
13760 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13761
13762 return &cursor->base;
13763 }
13764
13765 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13766 struct intel_crtc_state *crtc_state)
13767 {
13768 int i;
13769 struct intel_scaler *intel_scaler;
13770 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13771
13772 for (i = 0; i < intel_crtc->num_scalers; i++) {
13773 intel_scaler = &scaler_state->scalers[i];
13774 intel_scaler->in_use = 0;
13775 intel_scaler->mode = PS_SCALER_MODE_DYN;
13776 }
13777
13778 scaler_state->scaler_id = -1;
13779 }
13780
13781 static void intel_crtc_init(struct drm_device *dev, int pipe)
13782 {
13783 struct drm_i915_private *dev_priv = dev->dev_private;
13784 struct intel_crtc *intel_crtc;
13785 struct intel_crtc_state *crtc_state = NULL;
13786 struct drm_plane *primary = NULL;
13787 struct drm_plane *cursor = NULL;
13788 int i, ret;
13789
13790 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13791 if (intel_crtc == NULL)
13792 return;
13793
13794 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13795 if (!crtc_state)
13796 goto fail;
13797 intel_crtc->config = crtc_state;
13798 intel_crtc->base.state = &crtc_state->base;
13799 crtc_state->base.crtc = &intel_crtc->base;
13800
13801 /* initialize shared scalers */
13802 if (INTEL_INFO(dev)->gen >= 9) {
13803 if (pipe == PIPE_C)
13804 intel_crtc->num_scalers = 1;
13805 else
13806 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13807
13808 skl_init_scalers(dev, intel_crtc, crtc_state);
13809 }
13810
13811 primary = intel_primary_plane_create(dev, pipe);
13812 if (!primary)
13813 goto fail;
13814
13815 cursor = intel_cursor_plane_create(dev, pipe);
13816 if (!cursor)
13817 goto fail;
13818
13819 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13820 cursor, &intel_crtc_funcs);
13821 if (ret)
13822 goto fail;
13823
13824 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13825 for (i = 0; i < 256; i++) {
13826 intel_crtc->lut_r[i] = i;
13827 intel_crtc->lut_g[i] = i;
13828 intel_crtc->lut_b[i] = i;
13829 }
13830
13831 /*
13832 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13833 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13834 */
13835 intel_crtc->pipe = pipe;
13836 intel_crtc->plane = pipe;
13837 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13838 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13839 intel_crtc->plane = !pipe;
13840 }
13841
13842 intel_crtc->cursor_base = ~0;
13843 intel_crtc->cursor_cntl = ~0;
13844 intel_crtc->cursor_size = ~0;
13845
13846 intel_crtc->wm.cxsr_allowed = true;
13847
13848 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13849 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13850 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13851 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13852
13853 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13854
13855 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13856 return;
13857
13858 fail:
13859 if (primary)
13860 drm_plane_cleanup(primary);
13861 if (cursor)
13862 drm_plane_cleanup(cursor);
13863 kfree(crtc_state);
13864 kfree(intel_crtc);
13865 }
13866
13867 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13868 {
13869 struct drm_encoder *encoder = connector->base.encoder;
13870 struct drm_device *dev = connector->base.dev;
13871
13872 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13873
13874 if (!encoder || WARN_ON(!encoder->crtc))
13875 return INVALID_PIPE;
13876
13877 return to_intel_crtc(encoder->crtc)->pipe;
13878 }
13879
13880 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13881 struct drm_file *file)
13882 {
13883 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13884 struct drm_crtc *drmmode_crtc;
13885 struct intel_crtc *crtc;
13886
13887 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13888
13889 if (!drmmode_crtc) {
13890 DRM_ERROR("no such CRTC id\n");
13891 return -ENOENT;
13892 }
13893
13894 crtc = to_intel_crtc(drmmode_crtc);
13895 pipe_from_crtc_id->pipe = crtc->pipe;
13896
13897 return 0;
13898 }
13899
13900 static int intel_encoder_clones(struct intel_encoder *encoder)
13901 {
13902 struct drm_device *dev = encoder->base.dev;
13903 struct intel_encoder *source_encoder;
13904 int index_mask = 0;
13905 int entry = 0;
13906
13907 for_each_intel_encoder(dev, source_encoder) {
13908 if (encoders_cloneable(encoder, source_encoder))
13909 index_mask |= (1 << entry);
13910
13911 entry++;
13912 }
13913
13914 return index_mask;
13915 }
13916
13917 static bool has_edp_a(struct drm_device *dev)
13918 {
13919 struct drm_i915_private *dev_priv = dev->dev_private;
13920
13921 if (!IS_MOBILE(dev))
13922 return false;
13923
13924 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13925 return false;
13926
13927 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13928 return false;
13929
13930 return true;
13931 }
13932
13933 static bool intel_crt_present(struct drm_device *dev)
13934 {
13935 struct drm_i915_private *dev_priv = dev->dev_private;
13936
13937 if (INTEL_INFO(dev)->gen >= 9)
13938 return false;
13939
13940 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13941 return false;
13942
13943 if (IS_CHERRYVIEW(dev))
13944 return false;
13945
13946 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13947 return false;
13948
13949 return true;
13950 }
13951
13952 static void intel_setup_outputs(struct drm_device *dev)
13953 {
13954 struct drm_i915_private *dev_priv = dev->dev_private;
13955 struct intel_encoder *encoder;
13956 bool dpd_is_edp = false;
13957
13958 intel_lvds_init(dev);
13959
13960 if (intel_crt_present(dev))
13961 intel_crt_init(dev);
13962
13963 if (IS_BROXTON(dev)) {
13964 /*
13965 * FIXME: Broxton doesn't support port detection via the
13966 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13967 * detect the ports.
13968 */
13969 intel_ddi_init(dev, PORT_A);
13970 intel_ddi_init(dev, PORT_B);
13971 intel_ddi_init(dev, PORT_C);
13972 } else if (HAS_DDI(dev)) {
13973 int found;
13974
13975 /*
13976 * Haswell uses DDI functions to detect digital outputs.
13977 * On SKL pre-D0 the strap isn't connected, so we assume
13978 * it's there.
13979 */
13980 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13981 /* WaIgnoreDDIAStrap: skl */
13982 if (found ||
13983 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
13984 intel_ddi_init(dev, PORT_A);
13985
13986 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13987 * register */
13988 found = I915_READ(SFUSE_STRAP);
13989
13990 if (found & SFUSE_STRAP_DDIB_DETECTED)
13991 intel_ddi_init(dev, PORT_B);
13992 if (found & SFUSE_STRAP_DDIC_DETECTED)
13993 intel_ddi_init(dev, PORT_C);
13994 if (found & SFUSE_STRAP_DDID_DETECTED)
13995 intel_ddi_init(dev, PORT_D);
13996 } else if (HAS_PCH_SPLIT(dev)) {
13997 int found;
13998 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
13999
14000 if (has_edp_a(dev))
14001 intel_dp_init(dev, DP_A, PORT_A);
14002
14003 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14004 /* PCH SDVOB multiplex with HDMIB */
14005 found = intel_sdvo_init(dev, PCH_SDVOB, true);
14006 if (!found)
14007 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14008 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14009 intel_dp_init(dev, PCH_DP_B, PORT_B);
14010 }
14011
14012 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14013 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14014
14015 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14016 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14017
14018 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14019 intel_dp_init(dev, PCH_DP_C, PORT_C);
14020
14021 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14022 intel_dp_init(dev, PCH_DP_D, PORT_D);
14023 } else if (IS_VALLEYVIEW(dev)) {
14024 /*
14025 * The DP_DETECTED bit is the latched state of the DDC
14026 * SDA pin at boot. However since eDP doesn't require DDC
14027 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14028 * eDP ports may have been muxed to an alternate function.
14029 * Thus we can't rely on the DP_DETECTED bit alone to detect
14030 * eDP ports. Consult the VBT as well as DP_DETECTED to
14031 * detect eDP ports.
14032 */
14033 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14034 !intel_dp_is_edp(dev, PORT_B))
14035 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14036 PORT_B);
14037 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14038 intel_dp_is_edp(dev, PORT_B))
14039 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14040
14041 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14042 !intel_dp_is_edp(dev, PORT_C))
14043 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14044 PORT_C);
14045 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14046 intel_dp_is_edp(dev, PORT_C))
14047 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14048
14049 if (IS_CHERRYVIEW(dev)) {
14050 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14051 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14052 PORT_D);
14053 /* eDP not supported on port D, so don't check VBT */
14054 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14055 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14056 }
14057
14058 intel_dsi_init(dev);
14059 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14060 bool found = false;
14061
14062 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14063 DRM_DEBUG_KMS("probing SDVOB\n");
14064 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14065 if (!found && IS_G4X(dev)) {
14066 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14067 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14068 }
14069
14070 if (!found && IS_G4X(dev))
14071 intel_dp_init(dev, DP_B, PORT_B);
14072 }
14073
14074 /* Before G4X SDVOC doesn't have its own detect register */
14075
14076 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14077 DRM_DEBUG_KMS("probing SDVOC\n");
14078 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14079 }
14080
14081 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14082
14083 if (IS_G4X(dev)) {
14084 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14085 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14086 }
14087 if (IS_G4X(dev))
14088 intel_dp_init(dev, DP_C, PORT_C);
14089 }
14090
14091 if (IS_G4X(dev) &&
14092 (I915_READ(DP_D) & DP_DETECTED))
14093 intel_dp_init(dev, DP_D, PORT_D);
14094 } else if (IS_GEN2(dev))
14095 intel_dvo_init(dev);
14096
14097 if (SUPPORTS_TV(dev))
14098 intel_tv_init(dev);
14099
14100 intel_psr_init(dev);
14101
14102 for_each_intel_encoder(dev, encoder) {
14103 encoder->base.possible_crtcs = encoder->crtc_mask;
14104 encoder->base.possible_clones =
14105 intel_encoder_clones(encoder);
14106 }
14107
14108 intel_init_pch_refclk(dev);
14109
14110 drm_helper_move_panel_connectors_to_head(dev);
14111 }
14112
14113 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14114 {
14115 struct drm_device *dev = fb->dev;
14116 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14117
14118 drm_framebuffer_cleanup(fb);
14119 mutex_lock(&dev->struct_mutex);
14120 WARN_ON(!intel_fb->obj->framebuffer_references--);
14121 drm_gem_object_unreference(&intel_fb->obj->base);
14122 mutex_unlock(&dev->struct_mutex);
14123 kfree(intel_fb);
14124 }
14125
14126 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14127 struct drm_file *file,
14128 unsigned int *handle)
14129 {
14130 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14131 struct drm_i915_gem_object *obj = intel_fb->obj;
14132
14133 return drm_gem_handle_create(file, &obj->base, handle);
14134 }
14135
14136 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14137 struct drm_file *file,
14138 unsigned flags, unsigned color,
14139 struct drm_clip_rect *clips,
14140 unsigned num_clips)
14141 {
14142 struct drm_device *dev = fb->dev;
14143 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14144 struct drm_i915_gem_object *obj = intel_fb->obj;
14145
14146 mutex_lock(&dev->struct_mutex);
14147 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14148 mutex_unlock(&dev->struct_mutex);
14149
14150 return 0;
14151 }
14152
14153 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14154 .destroy = intel_user_framebuffer_destroy,
14155 .create_handle = intel_user_framebuffer_create_handle,
14156 .dirty = intel_user_framebuffer_dirty,
14157 };
14158
14159 static
14160 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14161 uint32_t pixel_format)
14162 {
14163 u32 gen = INTEL_INFO(dev)->gen;
14164
14165 if (gen >= 9) {
14166 /* "The stride in bytes must not exceed the of the size of 8K
14167 * pixels and 32K bytes."
14168 */
14169 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14170 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14171 return 32*1024;
14172 } else if (gen >= 4) {
14173 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14174 return 16*1024;
14175 else
14176 return 32*1024;
14177 } else if (gen >= 3) {
14178 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14179 return 8*1024;
14180 else
14181 return 16*1024;
14182 } else {
14183 /* XXX DSPC is limited to 4k tiled */
14184 return 8*1024;
14185 }
14186 }
14187
14188 static int intel_framebuffer_init(struct drm_device *dev,
14189 struct intel_framebuffer *intel_fb,
14190 struct drm_mode_fb_cmd2 *mode_cmd,
14191 struct drm_i915_gem_object *obj)
14192 {
14193 unsigned int aligned_height;
14194 int ret;
14195 u32 pitch_limit, stride_alignment;
14196
14197 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14198
14199 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14200 /* Enforce that fb modifier and tiling mode match, but only for
14201 * X-tiled. This is needed for FBC. */
14202 if (!!(obj->tiling_mode == I915_TILING_X) !=
14203 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14204 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14205 return -EINVAL;
14206 }
14207 } else {
14208 if (obj->tiling_mode == I915_TILING_X)
14209 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14210 else if (obj->tiling_mode == I915_TILING_Y) {
14211 DRM_DEBUG("No Y tiling for legacy addfb\n");
14212 return -EINVAL;
14213 }
14214 }
14215
14216 /* Passed in modifier sanity checking. */
14217 switch (mode_cmd->modifier[0]) {
14218 case I915_FORMAT_MOD_Y_TILED:
14219 case I915_FORMAT_MOD_Yf_TILED:
14220 if (INTEL_INFO(dev)->gen < 9) {
14221 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14222 mode_cmd->modifier[0]);
14223 return -EINVAL;
14224 }
14225 case DRM_FORMAT_MOD_NONE:
14226 case I915_FORMAT_MOD_X_TILED:
14227 break;
14228 default:
14229 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14230 mode_cmd->modifier[0]);
14231 return -EINVAL;
14232 }
14233
14234 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14235 mode_cmd->pixel_format);
14236 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14237 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14238 mode_cmd->pitches[0], stride_alignment);
14239 return -EINVAL;
14240 }
14241
14242 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14243 mode_cmd->pixel_format);
14244 if (mode_cmd->pitches[0] > pitch_limit) {
14245 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14246 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14247 "tiled" : "linear",
14248 mode_cmd->pitches[0], pitch_limit);
14249 return -EINVAL;
14250 }
14251
14252 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14253 mode_cmd->pitches[0] != obj->stride) {
14254 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14255 mode_cmd->pitches[0], obj->stride);
14256 return -EINVAL;
14257 }
14258
14259 /* Reject formats not supported by any plane early. */
14260 switch (mode_cmd->pixel_format) {
14261 case DRM_FORMAT_C8:
14262 case DRM_FORMAT_RGB565:
14263 case DRM_FORMAT_XRGB8888:
14264 case DRM_FORMAT_ARGB8888:
14265 break;
14266 case DRM_FORMAT_XRGB1555:
14267 if (INTEL_INFO(dev)->gen > 3) {
14268 DRM_DEBUG("unsupported pixel format: %s\n",
14269 drm_get_format_name(mode_cmd->pixel_format));
14270 return -EINVAL;
14271 }
14272 break;
14273 case DRM_FORMAT_ABGR8888:
14274 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14275 DRM_DEBUG("unsupported pixel format: %s\n",
14276 drm_get_format_name(mode_cmd->pixel_format));
14277 return -EINVAL;
14278 }
14279 break;
14280 case DRM_FORMAT_XBGR8888:
14281 case DRM_FORMAT_XRGB2101010:
14282 case DRM_FORMAT_XBGR2101010:
14283 if (INTEL_INFO(dev)->gen < 4) {
14284 DRM_DEBUG("unsupported pixel format: %s\n",
14285 drm_get_format_name(mode_cmd->pixel_format));
14286 return -EINVAL;
14287 }
14288 break;
14289 case DRM_FORMAT_ABGR2101010:
14290 if (!IS_VALLEYVIEW(dev)) {
14291 DRM_DEBUG("unsupported pixel format: %s\n",
14292 drm_get_format_name(mode_cmd->pixel_format));
14293 return -EINVAL;
14294 }
14295 break;
14296 case DRM_FORMAT_YUYV:
14297 case DRM_FORMAT_UYVY:
14298 case DRM_FORMAT_YVYU:
14299 case DRM_FORMAT_VYUY:
14300 if (INTEL_INFO(dev)->gen < 5) {
14301 DRM_DEBUG("unsupported pixel format: %s\n",
14302 drm_get_format_name(mode_cmd->pixel_format));
14303 return -EINVAL;
14304 }
14305 break;
14306 default:
14307 DRM_DEBUG("unsupported pixel format: %s\n",
14308 drm_get_format_name(mode_cmd->pixel_format));
14309 return -EINVAL;
14310 }
14311
14312 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14313 if (mode_cmd->offsets[0] != 0)
14314 return -EINVAL;
14315
14316 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14317 mode_cmd->pixel_format,
14318 mode_cmd->modifier[0]);
14319 /* FIXME drm helper for size checks (especially planar formats)? */
14320 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14321 return -EINVAL;
14322
14323 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14324 intel_fb->obj = obj;
14325 intel_fb->obj->framebuffer_references++;
14326
14327 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14328 if (ret) {
14329 DRM_ERROR("framebuffer init failed %d\n", ret);
14330 return ret;
14331 }
14332
14333 return 0;
14334 }
14335
14336 static struct drm_framebuffer *
14337 intel_user_framebuffer_create(struct drm_device *dev,
14338 struct drm_file *filp,
14339 struct drm_mode_fb_cmd2 *mode_cmd)
14340 {
14341 struct drm_i915_gem_object *obj;
14342
14343 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14344 mode_cmd->handles[0]));
14345 if (&obj->base == NULL)
14346 return ERR_PTR(-ENOENT);
14347
14348 return intel_framebuffer_create(dev, mode_cmd, obj);
14349 }
14350
14351 #ifndef CONFIG_DRM_I915_FBDEV
14352 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14353 {
14354 }
14355 #endif
14356
14357 static const struct drm_mode_config_funcs intel_mode_funcs = {
14358 .fb_create = intel_user_framebuffer_create,
14359 .output_poll_changed = intel_fbdev_output_poll_changed,
14360 .atomic_check = intel_atomic_check,
14361 .atomic_commit = intel_atomic_commit,
14362 .atomic_state_alloc = intel_atomic_state_alloc,
14363 .atomic_state_clear = intel_atomic_state_clear,
14364 };
14365
14366 /* Set up chip specific display functions */
14367 static void intel_init_display(struct drm_device *dev)
14368 {
14369 struct drm_i915_private *dev_priv = dev->dev_private;
14370
14371 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14372 dev_priv->display.find_dpll = g4x_find_best_dpll;
14373 else if (IS_CHERRYVIEW(dev))
14374 dev_priv->display.find_dpll = chv_find_best_dpll;
14375 else if (IS_VALLEYVIEW(dev))
14376 dev_priv->display.find_dpll = vlv_find_best_dpll;
14377 else if (IS_PINEVIEW(dev))
14378 dev_priv->display.find_dpll = pnv_find_best_dpll;
14379 else
14380 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14381
14382 if (INTEL_INFO(dev)->gen >= 9) {
14383 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14384 dev_priv->display.get_initial_plane_config =
14385 skylake_get_initial_plane_config;
14386 dev_priv->display.crtc_compute_clock =
14387 haswell_crtc_compute_clock;
14388 dev_priv->display.crtc_enable = haswell_crtc_enable;
14389 dev_priv->display.crtc_disable = haswell_crtc_disable;
14390 dev_priv->display.update_primary_plane =
14391 skylake_update_primary_plane;
14392 } else if (HAS_DDI(dev)) {
14393 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14394 dev_priv->display.get_initial_plane_config =
14395 ironlake_get_initial_plane_config;
14396 dev_priv->display.crtc_compute_clock =
14397 haswell_crtc_compute_clock;
14398 dev_priv->display.crtc_enable = haswell_crtc_enable;
14399 dev_priv->display.crtc_disable = haswell_crtc_disable;
14400 dev_priv->display.update_primary_plane =
14401 ironlake_update_primary_plane;
14402 } else if (HAS_PCH_SPLIT(dev)) {
14403 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14404 dev_priv->display.get_initial_plane_config =
14405 ironlake_get_initial_plane_config;
14406 dev_priv->display.crtc_compute_clock =
14407 ironlake_crtc_compute_clock;
14408 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14409 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14410 dev_priv->display.update_primary_plane =
14411 ironlake_update_primary_plane;
14412 } else if (IS_VALLEYVIEW(dev)) {
14413 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14414 dev_priv->display.get_initial_plane_config =
14415 i9xx_get_initial_plane_config;
14416 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14417 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14418 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14419 dev_priv->display.update_primary_plane =
14420 i9xx_update_primary_plane;
14421 } else {
14422 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14423 dev_priv->display.get_initial_plane_config =
14424 i9xx_get_initial_plane_config;
14425 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14426 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14427 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14428 dev_priv->display.update_primary_plane =
14429 i9xx_update_primary_plane;
14430 }
14431
14432 /* Returns the core display clock speed */
14433 if (IS_SKYLAKE(dev))
14434 dev_priv->display.get_display_clock_speed =
14435 skylake_get_display_clock_speed;
14436 else if (IS_BROXTON(dev))
14437 dev_priv->display.get_display_clock_speed =
14438 broxton_get_display_clock_speed;
14439 else if (IS_BROADWELL(dev))
14440 dev_priv->display.get_display_clock_speed =
14441 broadwell_get_display_clock_speed;
14442 else if (IS_HASWELL(dev))
14443 dev_priv->display.get_display_clock_speed =
14444 haswell_get_display_clock_speed;
14445 else if (IS_VALLEYVIEW(dev))
14446 dev_priv->display.get_display_clock_speed =
14447 valleyview_get_display_clock_speed;
14448 else if (IS_GEN5(dev))
14449 dev_priv->display.get_display_clock_speed =
14450 ilk_get_display_clock_speed;
14451 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14452 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14453 dev_priv->display.get_display_clock_speed =
14454 i945_get_display_clock_speed;
14455 else if (IS_GM45(dev))
14456 dev_priv->display.get_display_clock_speed =
14457 gm45_get_display_clock_speed;
14458 else if (IS_CRESTLINE(dev))
14459 dev_priv->display.get_display_clock_speed =
14460 i965gm_get_display_clock_speed;
14461 else if (IS_PINEVIEW(dev))
14462 dev_priv->display.get_display_clock_speed =
14463 pnv_get_display_clock_speed;
14464 else if (IS_G33(dev) || IS_G4X(dev))
14465 dev_priv->display.get_display_clock_speed =
14466 g33_get_display_clock_speed;
14467 else if (IS_I915G(dev))
14468 dev_priv->display.get_display_clock_speed =
14469 i915_get_display_clock_speed;
14470 else if (IS_I945GM(dev) || IS_845G(dev))
14471 dev_priv->display.get_display_clock_speed =
14472 i9xx_misc_get_display_clock_speed;
14473 else if (IS_PINEVIEW(dev))
14474 dev_priv->display.get_display_clock_speed =
14475 pnv_get_display_clock_speed;
14476 else if (IS_I915GM(dev))
14477 dev_priv->display.get_display_clock_speed =
14478 i915gm_get_display_clock_speed;
14479 else if (IS_I865G(dev))
14480 dev_priv->display.get_display_clock_speed =
14481 i865_get_display_clock_speed;
14482 else if (IS_I85X(dev))
14483 dev_priv->display.get_display_clock_speed =
14484 i85x_get_display_clock_speed;
14485 else { /* 830 */
14486 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14487 dev_priv->display.get_display_clock_speed =
14488 i830_get_display_clock_speed;
14489 }
14490
14491 if (IS_GEN5(dev)) {
14492 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14493 } else if (IS_GEN6(dev)) {
14494 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14495 } else if (IS_IVYBRIDGE(dev)) {
14496 /* FIXME: detect B0+ stepping and use auto training */
14497 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14498 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14499 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14500 if (IS_BROADWELL(dev)) {
14501 dev_priv->display.modeset_commit_cdclk =
14502 broadwell_modeset_commit_cdclk;
14503 dev_priv->display.modeset_calc_cdclk =
14504 broadwell_modeset_calc_cdclk;
14505 }
14506 } else if (IS_VALLEYVIEW(dev)) {
14507 dev_priv->display.modeset_commit_cdclk =
14508 valleyview_modeset_commit_cdclk;
14509 dev_priv->display.modeset_calc_cdclk =
14510 valleyview_modeset_calc_cdclk;
14511 } else if (IS_BROXTON(dev)) {
14512 dev_priv->display.modeset_commit_cdclk =
14513 broxton_modeset_commit_cdclk;
14514 dev_priv->display.modeset_calc_cdclk =
14515 broxton_modeset_calc_cdclk;
14516 }
14517
14518 switch (INTEL_INFO(dev)->gen) {
14519 case 2:
14520 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14521 break;
14522
14523 case 3:
14524 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14525 break;
14526
14527 case 4:
14528 case 5:
14529 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14530 break;
14531
14532 case 6:
14533 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14534 break;
14535 case 7:
14536 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14537 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14538 break;
14539 case 9:
14540 /* Drop through - unsupported since execlist only. */
14541 default:
14542 /* Default just returns -ENODEV to indicate unsupported */
14543 dev_priv->display.queue_flip = intel_default_queue_flip;
14544 }
14545
14546 intel_panel_init_backlight_funcs(dev);
14547
14548 mutex_init(&dev_priv->pps_mutex);
14549 }
14550
14551 /*
14552 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14553 * resume, or other times. This quirk makes sure that's the case for
14554 * affected systems.
14555 */
14556 static void quirk_pipea_force(struct drm_device *dev)
14557 {
14558 struct drm_i915_private *dev_priv = dev->dev_private;
14559
14560 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14561 DRM_INFO("applying pipe a force quirk\n");
14562 }
14563
14564 static void quirk_pipeb_force(struct drm_device *dev)
14565 {
14566 struct drm_i915_private *dev_priv = dev->dev_private;
14567
14568 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14569 DRM_INFO("applying pipe b force quirk\n");
14570 }
14571
14572 /*
14573 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14574 */
14575 static void quirk_ssc_force_disable(struct drm_device *dev)
14576 {
14577 struct drm_i915_private *dev_priv = dev->dev_private;
14578 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14579 DRM_INFO("applying lvds SSC disable quirk\n");
14580 }
14581
14582 /*
14583 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14584 * brightness value
14585 */
14586 static void quirk_invert_brightness(struct drm_device *dev)
14587 {
14588 struct drm_i915_private *dev_priv = dev->dev_private;
14589 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14590 DRM_INFO("applying inverted panel brightness quirk\n");
14591 }
14592
14593 /* Some VBT's incorrectly indicate no backlight is present */
14594 static void quirk_backlight_present(struct drm_device *dev)
14595 {
14596 struct drm_i915_private *dev_priv = dev->dev_private;
14597 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14598 DRM_INFO("applying backlight present quirk\n");
14599 }
14600
14601 struct intel_quirk {
14602 int device;
14603 int subsystem_vendor;
14604 int subsystem_device;
14605 void (*hook)(struct drm_device *dev);
14606 };
14607
14608 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14609 struct intel_dmi_quirk {
14610 void (*hook)(struct drm_device *dev);
14611 const struct dmi_system_id (*dmi_id_list)[];
14612 };
14613
14614 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14615 {
14616 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14617 return 1;
14618 }
14619
14620 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14621 {
14622 .dmi_id_list = &(const struct dmi_system_id[]) {
14623 {
14624 .callback = intel_dmi_reverse_brightness,
14625 .ident = "NCR Corporation",
14626 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14627 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14628 },
14629 },
14630 { } /* terminating entry */
14631 },
14632 .hook = quirk_invert_brightness,
14633 },
14634 };
14635
14636 static struct intel_quirk intel_quirks[] = {
14637 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14638 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14639
14640 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14641 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14642
14643 /* 830 needs to leave pipe A & dpll A up */
14644 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14645
14646 /* 830 needs to leave pipe B & dpll B up */
14647 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14648
14649 /* Lenovo U160 cannot use SSC on LVDS */
14650 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14651
14652 /* Sony Vaio Y cannot use SSC on LVDS */
14653 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14654
14655 /* Acer Aspire 5734Z must invert backlight brightness */
14656 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14657
14658 /* Acer/eMachines G725 */
14659 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14660
14661 /* Acer/eMachines e725 */
14662 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14663
14664 /* Acer/Packard Bell NCL20 */
14665 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14666
14667 /* Acer Aspire 4736Z */
14668 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14669
14670 /* Acer Aspire 5336 */
14671 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14672
14673 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14674 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14675
14676 /* Acer C720 Chromebook (Core i3 4005U) */
14677 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14678
14679 /* Apple Macbook 2,1 (Core 2 T7400) */
14680 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14681
14682 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14683 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14684
14685 /* HP Chromebook 14 (Celeron 2955U) */
14686 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14687
14688 /* Dell Chromebook 11 */
14689 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14690 };
14691
14692 static void intel_init_quirks(struct drm_device *dev)
14693 {
14694 struct pci_dev *d = dev->pdev;
14695 int i;
14696
14697 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14698 struct intel_quirk *q = &intel_quirks[i];
14699
14700 if (d->device == q->device &&
14701 (d->subsystem_vendor == q->subsystem_vendor ||
14702 q->subsystem_vendor == PCI_ANY_ID) &&
14703 (d->subsystem_device == q->subsystem_device ||
14704 q->subsystem_device == PCI_ANY_ID))
14705 q->hook(dev);
14706 }
14707 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14708 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14709 intel_dmi_quirks[i].hook(dev);
14710 }
14711 }
14712
14713 /* Disable the VGA plane that we never use */
14714 static void i915_disable_vga(struct drm_device *dev)
14715 {
14716 struct drm_i915_private *dev_priv = dev->dev_private;
14717 u8 sr1;
14718 u32 vga_reg = i915_vgacntrl_reg(dev);
14719
14720 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14721 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14722 outb(SR01, VGA_SR_INDEX);
14723 sr1 = inb(VGA_SR_DATA);
14724 outb(sr1 | 1<<5, VGA_SR_DATA);
14725 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14726 udelay(300);
14727
14728 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14729 POSTING_READ(vga_reg);
14730 }
14731
14732 void intel_modeset_init_hw(struct drm_device *dev)
14733 {
14734 intel_update_cdclk(dev);
14735 intel_prepare_ddi(dev);
14736 intel_init_clock_gating(dev);
14737 intel_enable_gt_powersave(dev);
14738 }
14739
14740 void intel_modeset_init(struct drm_device *dev)
14741 {
14742 struct drm_i915_private *dev_priv = dev->dev_private;
14743 int sprite, ret;
14744 enum pipe pipe;
14745 struct intel_crtc *crtc;
14746
14747 drm_mode_config_init(dev);
14748
14749 dev->mode_config.min_width = 0;
14750 dev->mode_config.min_height = 0;
14751
14752 dev->mode_config.preferred_depth = 24;
14753 dev->mode_config.prefer_shadow = 1;
14754
14755 dev->mode_config.allow_fb_modifiers = true;
14756
14757 dev->mode_config.funcs = &intel_mode_funcs;
14758
14759 intel_init_quirks(dev);
14760
14761 intel_init_pm(dev);
14762
14763 if (INTEL_INFO(dev)->num_pipes == 0)
14764 return;
14765
14766 intel_init_display(dev);
14767 intel_init_audio(dev);
14768
14769 if (IS_GEN2(dev)) {
14770 dev->mode_config.max_width = 2048;
14771 dev->mode_config.max_height = 2048;
14772 } else if (IS_GEN3(dev)) {
14773 dev->mode_config.max_width = 4096;
14774 dev->mode_config.max_height = 4096;
14775 } else {
14776 dev->mode_config.max_width = 8192;
14777 dev->mode_config.max_height = 8192;
14778 }
14779
14780 if (IS_845G(dev) || IS_I865G(dev)) {
14781 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14782 dev->mode_config.cursor_height = 1023;
14783 } else if (IS_GEN2(dev)) {
14784 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14785 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14786 } else {
14787 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14788 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14789 }
14790
14791 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14792
14793 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14794 INTEL_INFO(dev)->num_pipes,
14795 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14796
14797 for_each_pipe(dev_priv, pipe) {
14798 intel_crtc_init(dev, pipe);
14799 for_each_sprite(dev_priv, pipe, sprite) {
14800 ret = intel_plane_init(dev, pipe, sprite);
14801 if (ret)
14802 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14803 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14804 }
14805 }
14806
14807 intel_init_dpio(dev);
14808
14809 intel_shared_dpll_init(dev);
14810
14811 /* Just disable it once at startup */
14812 i915_disable_vga(dev);
14813 intel_setup_outputs(dev);
14814
14815 /* Just in case the BIOS is doing something questionable. */
14816 intel_fbc_disable(dev_priv);
14817
14818 drm_modeset_lock_all(dev);
14819 intel_modeset_setup_hw_state(dev);
14820 drm_modeset_unlock_all(dev);
14821
14822 for_each_intel_crtc(dev, crtc) {
14823 struct intel_initial_plane_config plane_config = {};
14824
14825 if (!crtc->active)
14826 continue;
14827
14828 /*
14829 * Note that reserving the BIOS fb up front prevents us
14830 * from stuffing other stolen allocations like the ring
14831 * on top. This prevents some ugliness at boot time, and
14832 * can even allow for smooth boot transitions if the BIOS
14833 * fb is large enough for the active pipe configuration.
14834 */
14835 dev_priv->display.get_initial_plane_config(crtc,
14836 &plane_config);
14837
14838 /*
14839 * If the fb is shared between multiple heads, we'll
14840 * just get the first one.
14841 */
14842 intel_find_initial_plane_obj(crtc, &plane_config);
14843 }
14844 }
14845
14846 static void intel_enable_pipe_a(struct drm_device *dev)
14847 {
14848 struct intel_connector *connector;
14849 struct drm_connector *crt = NULL;
14850 struct intel_load_detect_pipe load_detect_temp;
14851 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14852
14853 /* We can't just switch on the pipe A, we need to set things up with a
14854 * proper mode and output configuration. As a gross hack, enable pipe A
14855 * by enabling the load detect pipe once. */
14856 for_each_intel_connector(dev, connector) {
14857 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14858 crt = &connector->base;
14859 break;
14860 }
14861 }
14862
14863 if (!crt)
14864 return;
14865
14866 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14867 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14868 }
14869
14870 static bool
14871 intel_check_plane_mapping(struct intel_crtc *crtc)
14872 {
14873 struct drm_device *dev = crtc->base.dev;
14874 struct drm_i915_private *dev_priv = dev->dev_private;
14875 u32 reg, val;
14876
14877 if (INTEL_INFO(dev)->num_pipes == 1)
14878 return true;
14879
14880 reg = DSPCNTR(!crtc->plane);
14881 val = I915_READ(reg);
14882
14883 if ((val & DISPLAY_PLANE_ENABLE) &&
14884 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14885 return false;
14886
14887 return true;
14888 }
14889
14890 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14891 {
14892 struct drm_device *dev = crtc->base.dev;
14893 struct drm_i915_private *dev_priv = dev->dev_private;
14894 struct intel_encoder *encoder;
14895 u32 reg;
14896 bool enable;
14897
14898 /* Clear any frame start delays used for debugging left by the BIOS */
14899 reg = PIPECONF(crtc->config->cpu_transcoder);
14900 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14901
14902 /* restore vblank interrupts to correct state */
14903 drm_crtc_vblank_reset(&crtc->base);
14904 if (crtc->active) {
14905 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
14906 update_scanline_offset(crtc);
14907 drm_crtc_vblank_on(&crtc->base);
14908 }
14909
14910 /* We need to sanitize the plane -> pipe mapping first because this will
14911 * disable the crtc (and hence change the state) if it is wrong. Note
14912 * that gen4+ has a fixed plane -> pipe mapping. */
14913 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14914 bool plane;
14915
14916 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14917 crtc->base.base.id);
14918
14919 /* Pipe has the wrong plane attached and the plane is active.
14920 * Temporarily change the plane mapping and disable everything
14921 * ... */
14922 plane = crtc->plane;
14923 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14924 crtc->plane = !plane;
14925 intel_crtc_disable_noatomic(&crtc->base);
14926 crtc->plane = plane;
14927 }
14928
14929 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14930 crtc->pipe == PIPE_A && !crtc->active) {
14931 /* BIOS forgot to enable pipe A, this mostly happens after
14932 * resume. Force-enable the pipe to fix this, the update_dpms
14933 * call below we restore the pipe to the right state, but leave
14934 * the required bits on. */
14935 intel_enable_pipe_a(dev);
14936 }
14937
14938 /* Adjust the state of the output pipe according to whether we
14939 * have active connectors/encoders. */
14940 enable = false;
14941 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14942 enable = true;
14943 break;
14944 }
14945
14946 if (!enable)
14947 intel_crtc_disable_noatomic(&crtc->base);
14948
14949 if (crtc->active != crtc->base.state->active) {
14950
14951 /* This can happen either due to bugs in the get_hw_state
14952 * functions or because of calls to intel_crtc_disable_noatomic,
14953 * or because the pipe is force-enabled due to the
14954 * pipe A quirk. */
14955 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14956 crtc->base.base.id,
14957 crtc->base.state->enable ? "enabled" : "disabled",
14958 crtc->active ? "enabled" : "disabled");
14959
14960 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
14961 crtc->base.state->active = crtc->active;
14962 crtc->base.enabled = crtc->active;
14963
14964 /* Because we only establish the connector -> encoder ->
14965 * crtc links if something is active, this means the
14966 * crtc is now deactivated. Break the links. connector
14967 * -> encoder links are only establish when things are
14968 * actually up, hence no need to break them. */
14969 WARN_ON(crtc->active);
14970
14971 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14972 WARN_ON(encoder->connectors_active);
14973 encoder->base.crtc = NULL;
14974 }
14975 }
14976
14977 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
14978 /*
14979 * We start out with underrun reporting disabled to avoid races.
14980 * For correct bookkeeping mark this on active crtcs.
14981 *
14982 * Also on gmch platforms we dont have any hardware bits to
14983 * disable the underrun reporting. Which means we need to start
14984 * out with underrun reporting disabled also on inactive pipes,
14985 * since otherwise we'll complain about the garbage we read when
14986 * e.g. coming up after runtime pm.
14987 *
14988 * No protection against concurrent access is required - at
14989 * worst a fifo underrun happens which also sets this to false.
14990 */
14991 crtc->cpu_fifo_underrun_disabled = true;
14992 crtc->pch_fifo_underrun_disabled = true;
14993 }
14994 }
14995
14996 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14997 {
14998 struct intel_connector *connector;
14999 struct drm_device *dev = encoder->base.dev;
15000 bool active = false;
15001
15002 /* We need to check both for a crtc link (meaning that the
15003 * encoder is active and trying to read from a pipe) and the
15004 * pipe itself being active. */
15005 bool has_active_crtc = encoder->base.crtc &&
15006 to_intel_crtc(encoder->base.crtc)->active;
15007
15008 for_each_intel_connector(dev, connector) {
15009 if (connector->base.encoder != &encoder->base)
15010 continue;
15011
15012 active = true;
15013 break;
15014 }
15015
15016 if (active && !has_active_crtc) {
15017 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15018 encoder->base.base.id,
15019 encoder->base.name);
15020
15021 /* Connector is active, but has no active pipe. This is
15022 * fallout from our resume register restoring. Disable
15023 * the encoder manually again. */
15024 if (encoder->base.crtc) {
15025 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15026 encoder->base.base.id,
15027 encoder->base.name);
15028 encoder->disable(encoder);
15029 if (encoder->post_disable)
15030 encoder->post_disable(encoder);
15031 }
15032 encoder->base.crtc = NULL;
15033 encoder->connectors_active = false;
15034
15035 /* Inconsistent output/port/pipe state happens presumably due to
15036 * a bug in one of the get_hw_state functions. Or someplace else
15037 * in our code, like the register restore mess on resume. Clamp
15038 * things to off as a safer default. */
15039 for_each_intel_connector(dev, connector) {
15040 if (connector->encoder != encoder)
15041 continue;
15042 connector->base.dpms = DRM_MODE_DPMS_OFF;
15043 connector->base.encoder = NULL;
15044 }
15045 }
15046 /* Enabled encoders without active connectors will be fixed in
15047 * the crtc fixup. */
15048 }
15049
15050 void i915_redisable_vga_power_on(struct drm_device *dev)
15051 {
15052 struct drm_i915_private *dev_priv = dev->dev_private;
15053 u32 vga_reg = i915_vgacntrl_reg(dev);
15054
15055 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15056 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15057 i915_disable_vga(dev);
15058 }
15059 }
15060
15061 void i915_redisable_vga(struct drm_device *dev)
15062 {
15063 struct drm_i915_private *dev_priv = dev->dev_private;
15064
15065 /* This function can be called both from intel_modeset_setup_hw_state or
15066 * at a very early point in our resume sequence, where the power well
15067 * structures are not yet restored. Since this function is at a very
15068 * paranoid "someone might have enabled VGA while we were not looking"
15069 * level, just check if the power well is enabled instead of trying to
15070 * follow the "don't touch the power well if we don't need it" policy
15071 * the rest of the driver uses. */
15072 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15073 return;
15074
15075 i915_redisable_vga_power_on(dev);
15076 }
15077
15078 static bool primary_get_hw_state(struct intel_crtc *crtc)
15079 {
15080 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15081
15082 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15083 }
15084
15085 static void readout_plane_state(struct intel_crtc *crtc,
15086 struct intel_crtc_state *crtc_state)
15087 {
15088 struct intel_plane *p;
15089 struct intel_plane_state *plane_state;
15090 bool active = crtc_state->base.active;
15091
15092 for_each_intel_plane(crtc->base.dev, p) {
15093 if (crtc->pipe != p->pipe)
15094 continue;
15095
15096 plane_state = to_intel_plane_state(p->base.state);
15097
15098 if (p->base.type == DRM_PLANE_TYPE_PRIMARY)
15099 plane_state->visible = primary_get_hw_state(crtc);
15100 else {
15101 if (active)
15102 p->disable_plane(&p->base, &crtc->base);
15103
15104 plane_state->visible = false;
15105 }
15106 }
15107 }
15108
15109 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15110 {
15111 struct drm_i915_private *dev_priv = dev->dev_private;
15112 enum pipe pipe;
15113 struct intel_crtc *crtc;
15114 struct intel_encoder *encoder;
15115 struct intel_connector *connector;
15116 int i;
15117
15118 for_each_intel_crtc(dev, crtc) {
15119 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15120 memset(crtc->config, 0, sizeof(*crtc->config));
15121 crtc->config->base.crtc = &crtc->base;
15122
15123 crtc->active = dev_priv->display.get_pipe_config(crtc,
15124 crtc->config);
15125
15126 crtc->base.state->active = crtc->active;
15127 crtc->base.enabled = crtc->active;
15128
15129 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15130 if (crtc->base.state->active) {
15131 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15132 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15133 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15134
15135 /*
15136 * The initial mode needs to be set in order to keep
15137 * the atomic core happy. It wants a valid mode if the
15138 * crtc's enabled, so we do the above call.
15139 *
15140 * At this point some state updated by the connectors
15141 * in their ->detect() callback has not run yet, so
15142 * no recalculation can be done yet.
15143 *
15144 * Even if we could do a recalculation and modeset
15145 * right now it would cause a double modeset if
15146 * fbdev or userspace chooses a different initial mode.
15147 *
15148 * If that happens, someone indicated they wanted a
15149 * mode change, which means it's safe to do a full
15150 * recalculation.
15151 */
15152 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15153 }
15154
15155 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15156 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
15157
15158 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15159 crtc->base.base.id,
15160 crtc->active ? "enabled" : "disabled");
15161 }
15162
15163 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15164 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15165
15166 pll->on = pll->get_hw_state(dev_priv, pll,
15167 &pll->config.hw_state);
15168 pll->active = 0;
15169 pll->config.crtc_mask = 0;
15170 for_each_intel_crtc(dev, crtc) {
15171 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15172 pll->active++;
15173 pll->config.crtc_mask |= 1 << crtc->pipe;
15174 }
15175 }
15176
15177 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15178 pll->name, pll->config.crtc_mask, pll->on);
15179
15180 if (pll->config.crtc_mask)
15181 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15182 }
15183
15184 for_each_intel_encoder(dev, encoder) {
15185 pipe = 0;
15186
15187 if (encoder->get_hw_state(encoder, &pipe)) {
15188 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15189 encoder->base.crtc = &crtc->base;
15190 encoder->get_config(encoder, crtc->config);
15191 } else {
15192 encoder->base.crtc = NULL;
15193 }
15194
15195 encoder->connectors_active = false;
15196 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15197 encoder->base.base.id,
15198 encoder->base.name,
15199 encoder->base.crtc ? "enabled" : "disabled",
15200 pipe_name(pipe));
15201 }
15202
15203 for_each_intel_connector(dev, connector) {
15204 if (connector->get_hw_state(connector)) {
15205 connector->base.dpms = DRM_MODE_DPMS_ON;
15206 connector->encoder->connectors_active = true;
15207 connector->base.encoder = &connector->encoder->base;
15208 } else {
15209 connector->base.dpms = DRM_MODE_DPMS_OFF;
15210 connector->base.encoder = NULL;
15211 }
15212 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15213 connector->base.base.id,
15214 connector->base.name,
15215 connector->base.encoder ? "enabled" : "disabled");
15216 }
15217 }
15218
15219 /* Scan out the current hw modeset state,
15220 * and sanitizes it to the current state
15221 */
15222 static void
15223 intel_modeset_setup_hw_state(struct drm_device *dev)
15224 {
15225 struct drm_i915_private *dev_priv = dev->dev_private;
15226 enum pipe pipe;
15227 struct intel_crtc *crtc;
15228 struct intel_encoder *encoder;
15229 int i;
15230
15231 intel_modeset_readout_hw_state(dev);
15232
15233 /* HW state is read out, now we need to sanitize this mess. */
15234 for_each_intel_encoder(dev, encoder) {
15235 intel_sanitize_encoder(encoder);
15236 }
15237
15238 for_each_pipe(dev_priv, pipe) {
15239 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15240 intel_sanitize_crtc(crtc);
15241 intel_dump_pipe_config(crtc, crtc->config,
15242 "[setup_hw_state]");
15243 }
15244
15245 intel_modeset_update_connector_atomic_state(dev);
15246
15247 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15248 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15249
15250 if (!pll->on || pll->active)
15251 continue;
15252
15253 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15254
15255 pll->disable(dev_priv, pll);
15256 pll->on = false;
15257 }
15258
15259 if (IS_VALLEYVIEW(dev))
15260 vlv_wm_get_hw_state(dev);
15261 else if (IS_GEN9(dev))
15262 skl_wm_get_hw_state(dev);
15263 else if (HAS_PCH_SPLIT(dev))
15264 ilk_wm_get_hw_state(dev);
15265
15266 for_each_intel_crtc(dev, crtc) {
15267 unsigned long put_domains;
15268
15269 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15270 if (WARN_ON(put_domains))
15271 modeset_put_power_domains(dev_priv, put_domains);
15272 }
15273 intel_display_set_init_power(dev_priv, false);
15274 }
15275
15276 void intel_display_resume(struct drm_device *dev)
15277 {
15278 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15279 struct intel_connector *conn;
15280 struct intel_plane *plane;
15281 struct drm_crtc *crtc;
15282 int ret;
15283
15284 if (!state)
15285 return;
15286
15287 state->acquire_ctx = dev->mode_config.acquire_ctx;
15288
15289 /* preserve complete old state, including dpll */
15290 intel_atomic_get_shared_dpll_state(state);
15291
15292 for_each_crtc(dev, crtc) {
15293 struct drm_crtc_state *crtc_state =
15294 drm_atomic_get_crtc_state(state, crtc);
15295
15296 ret = PTR_ERR_OR_ZERO(crtc_state);
15297 if (ret)
15298 goto err;
15299
15300 /* force a restore */
15301 crtc_state->mode_changed = true;
15302 }
15303
15304 for_each_intel_plane(dev, plane) {
15305 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15306 if (ret)
15307 goto err;
15308 }
15309
15310 for_each_intel_connector(dev, conn) {
15311 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15312 if (ret)
15313 goto err;
15314 }
15315
15316 intel_modeset_setup_hw_state(dev);
15317
15318 i915_redisable_vga(dev);
15319 ret = drm_atomic_commit(state);
15320 if (!ret)
15321 return;
15322
15323 err:
15324 DRM_ERROR("Restoring old state failed with %i\n", ret);
15325 drm_atomic_state_free(state);
15326 }
15327
15328 void intel_modeset_gem_init(struct drm_device *dev)
15329 {
15330 struct drm_i915_private *dev_priv = dev->dev_private;
15331 struct drm_crtc *c;
15332 struct drm_i915_gem_object *obj;
15333 int ret;
15334
15335 mutex_lock(&dev->struct_mutex);
15336 intel_init_gt_powersave(dev);
15337 mutex_unlock(&dev->struct_mutex);
15338
15339 /*
15340 * There may be no VBT; and if the BIOS enabled SSC we can
15341 * just keep using it to avoid unnecessary flicker. Whereas if the
15342 * BIOS isn't using it, don't assume it will work even if the VBT
15343 * indicates as much.
15344 */
15345 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15346 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15347 DREF_SSC1_ENABLE);
15348
15349 intel_modeset_init_hw(dev);
15350
15351 intel_setup_overlay(dev);
15352
15353 /*
15354 * Make sure any fbs we allocated at startup are properly
15355 * pinned & fenced. When we do the allocation it's too early
15356 * for this.
15357 */
15358 for_each_crtc(dev, c) {
15359 obj = intel_fb_obj(c->primary->fb);
15360 if (obj == NULL)
15361 continue;
15362
15363 mutex_lock(&dev->struct_mutex);
15364 ret = intel_pin_and_fence_fb_obj(c->primary,
15365 c->primary->fb,
15366 c->primary->state,
15367 NULL, NULL);
15368 mutex_unlock(&dev->struct_mutex);
15369 if (ret) {
15370 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15371 to_intel_crtc(c)->pipe);
15372 drm_framebuffer_unreference(c->primary->fb);
15373 c->primary->fb = NULL;
15374 c->primary->crtc = c->primary->state->crtc = NULL;
15375 update_state_fb(c->primary);
15376 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15377 }
15378 }
15379
15380 intel_backlight_register(dev);
15381 }
15382
15383 void intel_connector_unregister(struct intel_connector *intel_connector)
15384 {
15385 struct drm_connector *connector = &intel_connector->base;
15386
15387 intel_panel_destroy_backlight(connector);
15388 drm_connector_unregister(connector);
15389 }
15390
15391 void intel_modeset_cleanup(struct drm_device *dev)
15392 {
15393 struct drm_i915_private *dev_priv = dev->dev_private;
15394 struct drm_connector *connector;
15395
15396 intel_disable_gt_powersave(dev);
15397
15398 intel_backlight_unregister(dev);
15399
15400 /*
15401 * Interrupts and polling as the first thing to avoid creating havoc.
15402 * Too much stuff here (turning of connectors, ...) would
15403 * experience fancy races otherwise.
15404 */
15405 intel_irq_uninstall(dev_priv);
15406
15407 /*
15408 * Due to the hpd irq storm handling the hotplug work can re-arm the
15409 * poll handlers. Hence disable polling after hpd handling is shut down.
15410 */
15411 drm_kms_helper_poll_fini(dev);
15412
15413 intel_unregister_dsm_handler();
15414
15415 intel_fbc_disable(dev_priv);
15416
15417 /* flush any delayed tasks or pending work */
15418 flush_scheduled_work();
15419
15420 /* destroy the backlight and sysfs files before encoders/connectors */
15421 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15422 struct intel_connector *intel_connector;
15423
15424 intel_connector = to_intel_connector(connector);
15425 intel_connector->unregister(intel_connector);
15426 }
15427
15428 drm_mode_config_cleanup(dev);
15429
15430 intel_cleanup_overlay(dev);
15431
15432 mutex_lock(&dev->struct_mutex);
15433 intel_cleanup_gt_powersave(dev);
15434 mutex_unlock(&dev->struct_mutex);
15435 }
15436
15437 /*
15438 * Return which encoder is currently attached for connector.
15439 */
15440 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15441 {
15442 return &intel_attached_encoder(connector)->base;
15443 }
15444
15445 void intel_connector_attach_encoder(struct intel_connector *connector,
15446 struct intel_encoder *encoder)
15447 {
15448 connector->encoder = encoder;
15449 drm_mode_connector_attach_encoder(&connector->base,
15450 &encoder->base);
15451 }
15452
15453 /*
15454 * set vga decode state - true == enable VGA decode
15455 */
15456 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15457 {
15458 struct drm_i915_private *dev_priv = dev->dev_private;
15459 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15460 u16 gmch_ctrl;
15461
15462 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15463 DRM_ERROR("failed to read control word\n");
15464 return -EIO;
15465 }
15466
15467 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15468 return 0;
15469
15470 if (state)
15471 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15472 else
15473 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15474
15475 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15476 DRM_ERROR("failed to write control word\n");
15477 return -EIO;
15478 }
15479
15480 return 0;
15481 }
15482
15483 struct intel_display_error_state {
15484
15485 u32 power_well_driver;
15486
15487 int num_transcoders;
15488
15489 struct intel_cursor_error_state {
15490 u32 control;
15491 u32 position;
15492 u32 base;
15493 u32 size;
15494 } cursor[I915_MAX_PIPES];
15495
15496 struct intel_pipe_error_state {
15497 bool power_domain_on;
15498 u32 source;
15499 u32 stat;
15500 } pipe[I915_MAX_PIPES];
15501
15502 struct intel_plane_error_state {
15503 u32 control;
15504 u32 stride;
15505 u32 size;
15506 u32 pos;
15507 u32 addr;
15508 u32 surface;
15509 u32 tile_offset;
15510 } plane[I915_MAX_PIPES];
15511
15512 struct intel_transcoder_error_state {
15513 bool power_domain_on;
15514 enum transcoder cpu_transcoder;
15515
15516 u32 conf;
15517
15518 u32 htotal;
15519 u32 hblank;
15520 u32 hsync;
15521 u32 vtotal;
15522 u32 vblank;
15523 u32 vsync;
15524 } transcoder[4];
15525 };
15526
15527 struct intel_display_error_state *
15528 intel_display_capture_error_state(struct drm_device *dev)
15529 {
15530 struct drm_i915_private *dev_priv = dev->dev_private;
15531 struct intel_display_error_state *error;
15532 int transcoders[] = {
15533 TRANSCODER_A,
15534 TRANSCODER_B,
15535 TRANSCODER_C,
15536 TRANSCODER_EDP,
15537 };
15538 int i;
15539
15540 if (INTEL_INFO(dev)->num_pipes == 0)
15541 return NULL;
15542
15543 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15544 if (error == NULL)
15545 return NULL;
15546
15547 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15548 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15549
15550 for_each_pipe(dev_priv, i) {
15551 error->pipe[i].power_domain_on =
15552 __intel_display_power_is_enabled(dev_priv,
15553 POWER_DOMAIN_PIPE(i));
15554 if (!error->pipe[i].power_domain_on)
15555 continue;
15556
15557 error->cursor[i].control = I915_READ(CURCNTR(i));
15558 error->cursor[i].position = I915_READ(CURPOS(i));
15559 error->cursor[i].base = I915_READ(CURBASE(i));
15560
15561 error->plane[i].control = I915_READ(DSPCNTR(i));
15562 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15563 if (INTEL_INFO(dev)->gen <= 3) {
15564 error->plane[i].size = I915_READ(DSPSIZE(i));
15565 error->plane[i].pos = I915_READ(DSPPOS(i));
15566 }
15567 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15568 error->plane[i].addr = I915_READ(DSPADDR(i));
15569 if (INTEL_INFO(dev)->gen >= 4) {
15570 error->plane[i].surface = I915_READ(DSPSURF(i));
15571 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15572 }
15573
15574 error->pipe[i].source = I915_READ(PIPESRC(i));
15575
15576 if (HAS_GMCH_DISPLAY(dev))
15577 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15578 }
15579
15580 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15581 if (HAS_DDI(dev_priv->dev))
15582 error->num_transcoders++; /* Account for eDP. */
15583
15584 for (i = 0; i < error->num_transcoders; i++) {
15585 enum transcoder cpu_transcoder = transcoders[i];
15586
15587 error->transcoder[i].power_domain_on =
15588 __intel_display_power_is_enabled(dev_priv,
15589 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15590 if (!error->transcoder[i].power_domain_on)
15591 continue;
15592
15593 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15594
15595 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15596 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15597 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15598 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15599 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15600 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15601 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15602 }
15603
15604 return error;
15605 }
15606
15607 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15608
15609 void
15610 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15611 struct drm_device *dev,
15612 struct intel_display_error_state *error)
15613 {
15614 struct drm_i915_private *dev_priv = dev->dev_private;
15615 int i;
15616
15617 if (!error)
15618 return;
15619
15620 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15621 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15622 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15623 error->power_well_driver);
15624 for_each_pipe(dev_priv, i) {
15625 err_printf(m, "Pipe [%d]:\n", i);
15626 err_printf(m, " Power: %s\n",
15627 error->pipe[i].power_domain_on ? "on" : "off");
15628 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15629 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15630
15631 err_printf(m, "Plane [%d]:\n", i);
15632 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15633 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15634 if (INTEL_INFO(dev)->gen <= 3) {
15635 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15636 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15637 }
15638 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15639 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15640 if (INTEL_INFO(dev)->gen >= 4) {
15641 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15642 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15643 }
15644
15645 err_printf(m, "Cursor [%d]:\n", i);
15646 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15647 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15648 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15649 }
15650
15651 for (i = 0; i < error->num_transcoders; i++) {
15652 err_printf(m, "CPU transcoder: %c\n",
15653 transcoder_name(error->transcoder[i].cpu_transcoder));
15654 err_printf(m, " Power: %s\n",
15655 error->transcoder[i].power_domain_on ? "on" : "off");
15656 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15657 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15658 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15659 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15660 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15661 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15662 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15663 }
15664 }
15665
15666 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15667 {
15668 struct intel_crtc *crtc;
15669
15670 for_each_intel_crtc(dev, crtc) {
15671 struct intel_unpin_work *work;
15672
15673 spin_lock_irq(&dev->event_lock);
15674
15675 work = crtc->unpin_work;
15676
15677 if (work && work->event &&
15678 work->event->base.file_priv == file) {
15679 kfree(work->event);
15680 work->event = NULL;
15681 }
15682
15683 spin_unlock_irq(&dev->event_lock);
15684 }
15685 }
Linux kernel - Deliverables
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