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30d8dafb388ded6e6810769973b66d9116bd1df1
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include "drmP.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "drm_dp_helper.h"
37
38 #include "drm_crtc_helper.h"
39
40 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
41
42 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
43 static void intel_update_watermarks(struct drm_device *dev);
44 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
45
46 typedef struct {
47 /* given values */
48 int n;
49 int m1, m2;
50 int p1, p2;
51 /* derived values */
52 int dot;
53 int vco;
54 int m;
55 int p;
56 } intel_clock_t;
57
58 typedef struct {
59 int min, max;
60 } intel_range_t;
61
62 typedef struct {
63 int dot_limit;
64 int p2_slow, p2_fast;
65 } intel_p2_t;
66
67 #define INTEL_P2_NUM 2
68 typedef struct intel_limit intel_limit_t;
69 struct intel_limit {
70 intel_range_t dot, vco, n, m, m1, m2, p, p1;
71 intel_p2_t p2;
72 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
73 int, int, intel_clock_t *);
74 };
75
76 #define I8XX_DOT_MIN 25000
77 #define I8XX_DOT_MAX 350000
78 #define I8XX_VCO_MIN 930000
79 #define I8XX_VCO_MAX 1400000
80 #define I8XX_N_MIN 3
81 #define I8XX_N_MAX 16
82 #define I8XX_M_MIN 96
83 #define I8XX_M_MAX 140
84 #define I8XX_M1_MIN 18
85 #define I8XX_M1_MAX 26
86 #define I8XX_M2_MIN 6
87 #define I8XX_M2_MAX 16
88 #define I8XX_P_MIN 4
89 #define I8XX_P_MAX 128
90 #define I8XX_P1_MIN 2
91 #define I8XX_P1_MAX 33
92 #define I8XX_P1_LVDS_MIN 1
93 #define I8XX_P1_LVDS_MAX 6
94 #define I8XX_P2_SLOW 4
95 #define I8XX_P2_FAST 2
96 #define I8XX_P2_LVDS_SLOW 14
97 #define I8XX_P2_LVDS_FAST 7
98 #define I8XX_P2_SLOW_LIMIT 165000
99
100 #define I9XX_DOT_MIN 20000
101 #define I9XX_DOT_MAX 400000
102 #define I9XX_VCO_MIN 1400000
103 #define I9XX_VCO_MAX 2800000
104 #define PINEVIEW_VCO_MIN 1700000
105 #define PINEVIEW_VCO_MAX 3500000
106 #define I9XX_N_MIN 1
107 #define I9XX_N_MAX 6
108 /* Pineview's Ncounter is a ring counter */
109 #define PINEVIEW_N_MIN 3
110 #define PINEVIEW_N_MAX 6
111 #define I9XX_M_MIN 70
112 #define I9XX_M_MAX 120
113 #define PINEVIEW_M_MIN 2
114 #define PINEVIEW_M_MAX 256
115 #define I9XX_M1_MIN 10
116 #define I9XX_M1_MAX 22
117 #define I9XX_M2_MIN 5
118 #define I9XX_M2_MAX 9
119 /* Pineview M1 is reserved, and must be 0 */
120 #define PINEVIEW_M1_MIN 0
121 #define PINEVIEW_M1_MAX 0
122 #define PINEVIEW_M2_MIN 0
123 #define PINEVIEW_M2_MAX 254
124 #define I9XX_P_SDVO_DAC_MIN 5
125 #define I9XX_P_SDVO_DAC_MAX 80
126 #define I9XX_P_LVDS_MIN 7
127 #define I9XX_P_LVDS_MAX 98
128 #define PINEVIEW_P_LVDS_MIN 7
129 #define PINEVIEW_P_LVDS_MAX 112
130 #define I9XX_P1_MIN 1
131 #define I9XX_P1_MAX 8
132 #define I9XX_P2_SDVO_DAC_SLOW 10
133 #define I9XX_P2_SDVO_DAC_FAST 5
134 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
135 #define I9XX_P2_LVDS_SLOW 14
136 #define I9XX_P2_LVDS_FAST 7
137 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
138
139 /*The parameter is for SDVO on G4x platform*/
140 #define G4X_DOT_SDVO_MIN 25000
141 #define G4X_DOT_SDVO_MAX 270000
142 #define G4X_VCO_MIN 1750000
143 #define G4X_VCO_MAX 3500000
144 #define G4X_N_SDVO_MIN 1
145 #define G4X_N_SDVO_MAX 4
146 #define G4X_M_SDVO_MIN 104
147 #define G4X_M_SDVO_MAX 138
148 #define G4X_M1_SDVO_MIN 17
149 #define G4X_M1_SDVO_MAX 23
150 #define G4X_M2_SDVO_MIN 5
151 #define G4X_M2_SDVO_MAX 11
152 #define G4X_P_SDVO_MIN 10
153 #define G4X_P_SDVO_MAX 30
154 #define G4X_P1_SDVO_MIN 1
155 #define G4X_P1_SDVO_MAX 3
156 #define G4X_P2_SDVO_SLOW 10
157 #define G4X_P2_SDVO_FAST 10
158 #define G4X_P2_SDVO_LIMIT 270000
159
160 /*The parameter is for HDMI_DAC on G4x platform*/
161 #define G4X_DOT_HDMI_DAC_MIN 22000
162 #define G4X_DOT_HDMI_DAC_MAX 400000
163 #define G4X_N_HDMI_DAC_MIN 1
164 #define G4X_N_HDMI_DAC_MAX 4
165 #define G4X_M_HDMI_DAC_MIN 104
166 #define G4X_M_HDMI_DAC_MAX 138
167 #define G4X_M1_HDMI_DAC_MIN 16
168 #define G4X_M1_HDMI_DAC_MAX 23
169 #define G4X_M2_HDMI_DAC_MIN 5
170 #define G4X_M2_HDMI_DAC_MAX 11
171 #define G4X_P_HDMI_DAC_MIN 5
172 #define G4X_P_HDMI_DAC_MAX 80
173 #define G4X_P1_HDMI_DAC_MIN 1
174 #define G4X_P1_HDMI_DAC_MAX 8
175 #define G4X_P2_HDMI_DAC_SLOW 10
176 #define G4X_P2_HDMI_DAC_FAST 5
177 #define G4X_P2_HDMI_DAC_LIMIT 165000
178
179 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
182 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
183 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
184 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
185 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
190 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
191 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
194 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
195 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
196 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
197
198 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
201 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
202 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
203 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
204 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
205 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
206 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
207 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
208 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
209 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
210 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
211 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
212 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
213 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
214 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
215 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
216
217 /*The parameter is for DISPLAY PORT on G4x platform*/
218 #define G4X_DOT_DISPLAY_PORT_MIN 161670
219 #define G4X_DOT_DISPLAY_PORT_MAX 227000
220 #define G4X_N_DISPLAY_PORT_MIN 1
221 #define G4X_N_DISPLAY_PORT_MAX 2
222 #define G4X_M_DISPLAY_PORT_MIN 97
223 #define G4X_M_DISPLAY_PORT_MAX 108
224 #define G4X_M1_DISPLAY_PORT_MIN 0x10
225 #define G4X_M1_DISPLAY_PORT_MAX 0x12
226 #define G4X_M2_DISPLAY_PORT_MIN 0x05
227 #define G4X_M2_DISPLAY_PORT_MAX 0x06
228 #define G4X_P_DISPLAY_PORT_MIN 10
229 #define G4X_P_DISPLAY_PORT_MAX 20
230 #define G4X_P1_DISPLAY_PORT_MIN 1
231 #define G4X_P1_DISPLAY_PORT_MAX 2
232 #define G4X_P2_DISPLAY_PORT_SLOW 10
233 #define G4X_P2_DISPLAY_PORT_FAST 10
234 #define G4X_P2_DISPLAY_PORT_LIMIT 0
235
236 /* Ironlake / Sandybridge */
237 /* as we calculate clock using (register_value + 2) for
238 N/M1/M2, so here the range value for them is (actual_value-2).
239 */
240 #define IRONLAKE_DOT_MIN 25000
241 #define IRONLAKE_DOT_MAX 350000
242 #define IRONLAKE_VCO_MIN 1760000
243 #define IRONLAKE_VCO_MAX 3510000
244 #define IRONLAKE_M1_MIN 12
245 #define IRONLAKE_M1_MAX 22
246 #define IRONLAKE_M2_MIN 5
247 #define IRONLAKE_M2_MAX 9
248 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
249
250 /* We have parameter ranges for different type of outputs. */
251
252 /* DAC & HDMI Refclk 120Mhz */
253 #define IRONLAKE_DAC_N_MIN 1
254 #define IRONLAKE_DAC_N_MAX 5
255 #define IRONLAKE_DAC_M_MIN 79
256 #define IRONLAKE_DAC_M_MAX 127
257 #define IRONLAKE_DAC_P_MIN 5
258 #define IRONLAKE_DAC_P_MAX 80
259 #define IRONLAKE_DAC_P1_MIN 1
260 #define IRONLAKE_DAC_P1_MAX 8
261 #define IRONLAKE_DAC_P2_SLOW 10
262 #define IRONLAKE_DAC_P2_FAST 5
263
264 /* LVDS single-channel 120Mhz refclk */
265 #define IRONLAKE_LVDS_S_N_MIN 1
266 #define IRONLAKE_LVDS_S_N_MAX 3
267 #define IRONLAKE_LVDS_S_M_MIN 79
268 #define IRONLAKE_LVDS_S_M_MAX 118
269 #define IRONLAKE_LVDS_S_P_MIN 28
270 #define IRONLAKE_LVDS_S_P_MAX 112
271 #define IRONLAKE_LVDS_S_P1_MIN 2
272 #define IRONLAKE_LVDS_S_P1_MAX 8
273 #define IRONLAKE_LVDS_S_P2_SLOW 14
274 #define IRONLAKE_LVDS_S_P2_FAST 14
275
276 /* LVDS dual-channel 120Mhz refclk */
277 #define IRONLAKE_LVDS_D_N_MIN 1
278 #define IRONLAKE_LVDS_D_N_MAX 3
279 #define IRONLAKE_LVDS_D_M_MIN 79
280 #define IRONLAKE_LVDS_D_M_MAX 127
281 #define IRONLAKE_LVDS_D_P_MIN 14
282 #define IRONLAKE_LVDS_D_P_MAX 56
283 #define IRONLAKE_LVDS_D_P1_MIN 2
284 #define IRONLAKE_LVDS_D_P1_MAX 8
285 #define IRONLAKE_LVDS_D_P2_SLOW 7
286 #define IRONLAKE_LVDS_D_P2_FAST 7
287
288 /* LVDS single-channel 100Mhz refclk */
289 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
290 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
291 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
292 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
293 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
294 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
295 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
296 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
297 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
298 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
299
300 /* LVDS dual-channel 100Mhz refclk */
301 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
302 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
303 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
304 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
305 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
306 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
307 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
308 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
309 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
310 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
311
312 /* DisplayPort */
313 #define IRONLAKE_DP_N_MIN 1
314 #define IRONLAKE_DP_N_MAX 2
315 #define IRONLAKE_DP_M_MIN 81
316 #define IRONLAKE_DP_M_MAX 90
317 #define IRONLAKE_DP_P_MIN 10
318 #define IRONLAKE_DP_P_MAX 20
319 #define IRONLAKE_DP_P2_FAST 10
320 #define IRONLAKE_DP_P2_SLOW 10
321 #define IRONLAKE_DP_P2_LIMIT 0
322 #define IRONLAKE_DP_P1_MIN 1
323 #define IRONLAKE_DP_P1_MAX 2
324
325 static bool
326 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
327 int target, int refclk, intel_clock_t *best_clock);
328 static bool
329 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
330 int target, int refclk, intel_clock_t *best_clock);
331
332 static bool
333 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
334 int target, int refclk, intel_clock_t *best_clock);
335 static bool
336 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
337 int target, int refclk, intel_clock_t *best_clock);
338
339 static const intel_limit_t intel_limits_i8xx_dvo = {
340 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
341 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
342 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
343 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
344 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
345 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
346 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
347 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
348 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
349 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
350 .find_pll = intel_find_best_PLL,
351 };
352
353 static const intel_limit_t intel_limits_i8xx_lvds = {
354 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
355 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
356 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
357 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
358 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
359 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
360 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
361 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
362 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
363 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
364 .find_pll = intel_find_best_PLL,
365 };
366
367 static const intel_limit_t intel_limits_i9xx_sdvo = {
368 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
369 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
370 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
371 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
372 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
373 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
374 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
375 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
376 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
377 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
378 .find_pll = intel_find_best_PLL,
379 };
380
381 static const intel_limit_t intel_limits_i9xx_lvds = {
382 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
383 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
384 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
385 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
386 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
387 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
388 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
389 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
390 /* The single-channel range is 25-112Mhz, and dual-channel
391 * is 80-224Mhz. Prefer single channel as much as possible.
392 */
393 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
394 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
395 .find_pll = intel_find_best_PLL,
396 };
397
398 /* below parameter and function is for G4X Chipset Family*/
399 static const intel_limit_t intel_limits_g4x_sdvo = {
400 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
401 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
402 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
403 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
404 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
405 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
406 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
407 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
408 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
409 .p2_slow = G4X_P2_SDVO_SLOW,
410 .p2_fast = G4X_P2_SDVO_FAST
411 },
412 .find_pll = intel_g4x_find_best_PLL,
413 };
414
415 static const intel_limit_t intel_limits_g4x_hdmi = {
416 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
417 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
418 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
419 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
420 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
421 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
422 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
423 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
424 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
425 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
426 .p2_fast = G4X_P2_HDMI_DAC_FAST
427 },
428 .find_pll = intel_g4x_find_best_PLL,
429 };
430
431 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
432 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
433 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
434 .vco = { .min = G4X_VCO_MIN,
435 .max = G4X_VCO_MAX },
436 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
437 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
438 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
439 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
440 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
441 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
442 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
443 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
444 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
445 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
446 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
447 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
448 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
449 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
450 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
451 },
452 .find_pll = intel_g4x_find_best_PLL,
453 };
454
455 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
456 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
457 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
458 .vco = { .min = G4X_VCO_MIN,
459 .max = G4X_VCO_MAX },
460 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
461 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
462 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
463 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
464 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
465 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
466 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
467 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
468 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
469 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
470 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
471 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
472 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
473 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
474 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
475 },
476 .find_pll = intel_g4x_find_best_PLL,
477 };
478
479 static const intel_limit_t intel_limits_g4x_display_port = {
480 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
481 .max = G4X_DOT_DISPLAY_PORT_MAX },
482 .vco = { .min = G4X_VCO_MIN,
483 .max = G4X_VCO_MAX},
484 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
485 .max = G4X_N_DISPLAY_PORT_MAX },
486 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
487 .max = G4X_M_DISPLAY_PORT_MAX },
488 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
489 .max = G4X_M1_DISPLAY_PORT_MAX },
490 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
491 .max = G4X_M2_DISPLAY_PORT_MAX },
492 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
493 .max = G4X_P_DISPLAY_PORT_MAX },
494 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
495 .max = G4X_P1_DISPLAY_PORT_MAX},
496 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
497 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
498 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
499 .find_pll = intel_find_pll_g4x_dp,
500 };
501
502 static const intel_limit_t intel_limits_pineview_sdvo = {
503 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
504 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
505 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
506 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
507 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
508 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
509 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
510 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
511 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
512 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
513 .find_pll = intel_find_best_PLL,
514 };
515
516 static const intel_limit_t intel_limits_pineview_lvds = {
517 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
518 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
519 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
520 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
521 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
522 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
523 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
524 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
525 /* Pineview only supports single-channel mode. */
526 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
527 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
528 .find_pll = intel_find_best_PLL,
529 };
530
531 static const intel_limit_t intel_limits_ironlake_dac = {
532 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
533 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
534 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
535 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
536 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
537 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
538 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
539 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
540 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
541 .p2_slow = IRONLAKE_DAC_P2_SLOW,
542 .p2_fast = IRONLAKE_DAC_P2_FAST },
543 .find_pll = intel_g4x_find_best_PLL,
544 };
545
546 static const intel_limit_t intel_limits_ironlake_single_lvds = {
547 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
548 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
549 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
550 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
551 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
552 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
553 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
554 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
555 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
556 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
557 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
558 .find_pll = intel_g4x_find_best_PLL,
559 };
560
561 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
562 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
563 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
564 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
565 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
566 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
567 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
568 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
569 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
570 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
571 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
572 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
573 .find_pll = intel_g4x_find_best_PLL,
574 };
575
576 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
577 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
578 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
579 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
580 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
581 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
582 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
583 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
584 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
585 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
586 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
587 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
588 .find_pll = intel_g4x_find_best_PLL,
589 };
590
591 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
592 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
593 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
594 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
595 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
596 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
597 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
598 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
599 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
600 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
601 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
602 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
603 .find_pll = intel_g4x_find_best_PLL,
604 };
605
606 static const intel_limit_t intel_limits_ironlake_display_port = {
607 .dot = { .min = IRONLAKE_DOT_MIN,
608 .max = IRONLAKE_DOT_MAX },
609 .vco = { .min = IRONLAKE_VCO_MIN,
610 .max = IRONLAKE_VCO_MAX},
611 .n = { .min = IRONLAKE_DP_N_MIN,
612 .max = IRONLAKE_DP_N_MAX },
613 .m = { .min = IRONLAKE_DP_M_MIN,
614 .max = IRONLAKE_DP_M_MAX },
615 .m1 = { .min = IRONLAKE_M1_MIN,
616 .max = IRONLAKE_M1_MAX },
617 .m2 = { .min = IRONLAKE_M2_MIN,
618 .max = IRONLAKE_M2_MAX },
619 .p = { .min = IRONLAKE_DP_P_MIN,
620 .max = IRONLAKE_DP_P_MAX },
621 .p1 = { .min = IRONLAKE_DP_P1_MIN,
622 .max = IRONLAKE_DP_P1_MAX},
623 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
624 .p2_slow = IRONLAKE_DP_P2_SLOW,
625 .p2_fast = IRONLAKE_DP_P2_FAST },
626 .find_pll = intel_find_pll_ironlake_dp,
627 };
628
629 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
630 {
631 struct drm_device *dev = crtc->dev;
632 struct drm_i915_private *dev_priv = dev->dev_private;
633 const intel_limit_t *limit;
634 int refclk = 120;
635
636 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
637 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
638 refclk = 100;
639
640 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
641 LVDS_CLKB_POWER_UP) {
642 /* LVDS dual channel */
643 if (refclk == 100)
644 limit = &intel_limits_ironlake_dual_lvds_100m;
645 else
646 limit = &intel_limits_ironlake_dual_lvds;
647 } else {
648 if (refclk == 100)
649 limit = &intel_limits_ironlake_single_lvds_100m;
650 else
651 limit = &intel_limits_ironlake_single_lvds;
652 }
653 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
654 HAS_eDP)
655 limit = &intel_limits_ironlake_display_port;
656 else
657 limit = &intel_limits_ironlake_dac;
658
659 return limit;
660 }
661
662 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
663 {
664 struct drm_device *dev = crtc->dev;
665 struct drm_i915_private *dev_priv = dev->dev_private;
666 const intel_limit_t *limit;
667
668 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
669 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
670 LVDS_CLKB_POWER_UP)
671 /* LVDS with dual channel */
672 limit = &intel_limits_g4x_dual_channel_lvds;
673 else
674 /* LVDS with dual channel */
675 limit = &intel_limits_g4x_single_channel_lvds;
676 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
677 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
678 limit = &intel_limits_g4x_hdmi;
679 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
680 limit = &intel_limits_g4x_sdvo;
681 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
682 limit = &intel_limits_g4x_display_port;
683 } else /* The option is for other outputs */
684 limit = &intel_limits_i9xx_sdvo;
685
686 return limit;
687 }
688
689 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
690 {
691 struct drm_device *dev = crtc->dev;
692 const intel_limit_t *limit;
693
694 if (HAS_PCH_SPLIT(dev))
695 limit = intel_ironlake_limit(crtc);
696 else if (IS_G4X(dev)) {
697 limit = intel_g4x_limit(crtc);
698 } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
699 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
700 limit = &intel_limits_i9xx_lvds;
701 else
702 limit = &intel_limits_i9xx_sdvo;
703 } else if (IS_PINEVIEW(dev)) {
704 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
705 limit = &intel_limits_pineview_lvds;
706 else
707 limit = &intel_limits_pineview_sdvo;
708 } else {
709 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
710 limit = &intel_limits_i8xx_lvds;
711 else
712 limit = &intel_limits_i8xx_dvo;
713 }
714 return limit;
715 }
716
717 /* m1 is reserved as 0 in Pineview, n is a ring counter */
718 static void pineview_clock(int refclk, intel_clock_t *clock)
719 {
720 clock->m = clock->m2 + 2;
721 clock->p = clock->p1 * clock->p2;
722 clock->vco = refclk * clock->m / clock->n;
723 clock->dot = clock->vco / clock->p;
724 }
725
726 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
727 {
728 if (IS_PINEVIEW(dev)) {
729 pineview_clock(refclk, clock);
730 return;
731 }
732 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
733 clock->p = clock->p1 * clock->p2;
734 clock->vco = refclk * clock->m / (clock->n + 2);
735 clock->dot = clock->vco / clock->p;
736 }
737
738 /**
739 * Returns whether any output on the specified pipe is of the specified type
740 */
741 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
742 {
743 struct drm_device *dev = crtc->dev;
744 struct drm_mode_config *mode_config = &dev->mode_config;
745 struct drm_encoder *l_entry;
746
747 list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
748 if (l_entry && l_entry->crtc == crtc) {
749 struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
750 if (intel_encoder->type == type)
751 return true;
752 }
753 }
754 return false;
755 }
756
757 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
758 /**
759 * Returns whether the given set of divisors are valid for a given refclk with
760 * the given connectors.
761 */
762
763 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
764 {
765 const intel_limit_t *limit = intel_limit (crtc);
766 struct drm_device *dev = crtc->dev;
767
768 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
769 INTELPllInvalid ("p1 out of range\n");
770 if (clock->p < limit->p.min || limit->p.max < clock->p)
771 INTELPllInvalid ("p out of range\n");
772 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
773 INTELPllInvalid ("m2 out of range\n");
774 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
775 INTELPllInvalid ("m1 out of range\n");
776 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
777 INTELPllInvalid ("m1 <= m2\n");
778 if (clock->m < limit->m.min || limit->m.max < clock->m)
779 INTELPllInvalid ("m out of range\n");
780 if (clock->n < limit->n.min || limit->n.max < clock->n)
781 INTELPllInvalid ("n out of range\n");
782 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
783 INTELPllInvalid ("vco out of range\n");
784 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
785 * connector, etc., rather than just a single range.
786 */
787 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
788 INTELPllInvalid ("dot out of range\n");
789
790 return true;
791 }
792
793 static bool
794 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
795 int target, int refclk, intel_clock_t *best_clock)
796
797 {
798 struct drm_device *dev = crtc->dev;
799 struct drm_i915_private *dev_priv = dev->dev_private;
800 intel_clock_t clock;
801 int err = target;
802
803 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
804 (I915_READ(LVDS)) != 0) {
805 /*
806 * For LVDS, if the panel is on, just rely on its current
807 * settings for dual-channel. We haven't figured out how to
808 * reliably set up different single/dual channel state, if we
809 * even can.
810 */
811 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
812 LVDS_CLKB_POWER_UP)
813 clock.p2 = limit->p2.p2_fast;
814 else
815 clock.p2 = limit->p2.p2_slow;
816 } else {
817 if (target < limit->p2.dot_limit)
818 clock.p2 = limit->p2.p2_slow;
819 else
820 clock.p2 = limit->p2.p2_fast;
821 }
822
823 memset (best_clock, 0, sizeof (*best_clock));
824
825 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
826 clock.m1++) {
827 for (clock.m2 = limit->m2.min;
828 clock.m2 <= limit->m2.max; clock.m2++) {
829 /* m1 is always 0 in Pineview */
830 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
831 break;
832 for (clock.n = limit->n.min;
833 clock.n <= limit->n.max; clock.n++) {
834 for (clock.p1 = limit->p1.min;
835 clock.p1 <= limit->p1.max; clock.p1++) {
836 int this_err;
837
838 intel_clock(dev, refclk, &clock);
839
840 if (!intel_PLL_is_valid(crtc, &clock))
841 continue;
842
843 this_err = abs(clock.dot - target);
844 if (this_err < err) {
845 *best_clock = clock;
846 err = this_err;
847 }
848 }
849 }
850 }
851 }
852
853 return (err != target);
854 }
855
856 static bool
857 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
858 int target, int refclk, intel_clock_t *best_clock)
859 {
860 struct drm_device *dev = crtc->dev;
861 struct drm_i915_private *dev_priv = dev->dev_private;
862 intel_clock_t clock;
863 int max_n;
864 bool found;
865 /* approximately equals target * 0.00585 */
866 int err_most = (target >> 8) + (target >> 9);
867 found = false;
868
869 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
870 int lvds_reg;
871
872 if (HAS_PCH_SPLIT(dev))
873 lvds_reg = PCH_LVDS;
874 else
875 lvds_reg = LVDS;
876 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
877 LVDS_CLKB_POWER_UP)
878 clock.p2 = limit->p2.p2_fast;
879 else
880 clock.p2 = limit->p2.p2_slow;
881 } else {
882 if (target < limit->p2.dot_limit)
883 clock.p2 = limit->p2.p2_slow;
884 else
885 clock.p2 = limit->p2.p2_fast;
886 }
887
888 memset(best_clock, 0, sizeof(*best_clock));
889 max_n = limit->n.max;
890 /* based on hardware requirement, prefer smaller n to precision */
891 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
892 /* based on hardware requirement, prefere larger m1,m2 */
893 for (clock.m1 = limit->m1.max;
894 clock.m1 >= limit->m1.min; clock.m1--) {
895 for (clock.m2 = limit->m2.max;
896 clock.m2 >= limit->m2.min; clock.m2--) {
897 for (clock.p1 = limit->p1.max;
898 clock.p1 >= limit->p1.min; clock.p1--) {
899 int this_err;
900
901 intel_clock(dev, refclk, &clock);
902 if (!intel_PLL_is_valid(crtc, &clock))
903 continue;
904 this_err = abs(clock.dot - target) ;
905 if (this_err < err_most) {
906 *best_clock = clock;
907 err_most = this_err;
908 max_n = clock.n;
909 found = true;
910 }
911 }
912 }
913 }
914 }
915 return found;
916 }
917
918 static bool
919 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
920 int target, int refclk, intel_clock_t *best_clock)
921 {
922 struct drm_device *dev = crtc->dev;
923 intel_clock_t clock;
924
925 /* return directly when it is eDP */
926 if (HAS_eDP)
927 return true;
928
929 if (target < 200000) {
930 clock.n = 1;
931 clock.p1 = 2;
932 clock.p2 = 10;
933 clock.m1 = 12;
934 clock.m2 = 9;
935 } else {
936 clock.n = 2;
937 clock.p1 = 1;
938 clock.p2 = 10;
939 clock.m1 = 14;
940 clock.m2 = 8;
941 }
942 intel_clock(dev, refclk, &clock);
943 memcpy(best_clock, &clock, sizeof(intel_clock_t));
944 return true;
945 }
946
947 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
948 static bool
949 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
950 int target, int refclk, intel_clock_t *best_clock)
951 {
952 intel_clock_t clock;
953 if (target < 200000) {
954 clock.p1 = 2;
955 clock.p2 = 10;
956 clock.n = 2;
957 clock.m1 = 23;
958 clock.m2 = 8;
959 } else {
960 clock.p1 = 1;
961 clock.p2 = 10;
962 clock.n = 1;
963 clock.m1 = 14;
964 clock.m2 = 2;
965 }
966 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
967 clock.p = (clock.p1 * clock.p2);
968 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
969 clock.vco = 0;
970 memcpy(best_clock, &clock, sizeof(intel_clock_t));
971 return true;
972 }
973
974 void
975 intel_wait_for_vblank(struct drm_device *dev)
976 {
977 /* Wait for 20ms, i.e. one cycle at 50hz. */
978 msleep(20);
979 }
980
981 /* Parameters have changed, update FBC info */
982 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
983 {
984 struct drm_device *dev = crtc->dev;
985 struct drm_i915_private *dev_priv = dev->dev_private;
986 struct drm_framebuffer *fb = crtc->fb;
987 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
988 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
990 int plane, i;
991 u32 fbc_ctl, fbc_ctl2;
992
993 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
994
995 if (fb->pitch < dev_priv->cfb_pitch)
996 dev_priv->cfb_pitch = fb->pitch;
997
998 /* FBC_CTL wants 64B units */
999 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1000 dev_priv->cfb_fence = obj_priv->fence_reg;
1001 dev_priv->cfb_plane = intel_crtc->plane;
1002 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1003
1004 /* Clear old tags */
1005 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1006 I915_WRITE(FBC_TAG + (i * 4), 0);
1007
1008 /* Set it up... */
1009 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1010 if (obj_priv->tiling_mode != I915_TILING_NONE)
1011 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1012 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1013 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1014
1015 /* enable it... */
1016 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1017 if (IS_I945GM(dev))
1018 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1019 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1020 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1021 if (obj_priv->tiling_mode != I915_TILING_NONE)
1022 fbc_ctl |= dev_priv->cfb_fence;
1023 I915_WRITE(FBC_CONTROL, fbc_ctl);
1024
1025 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1026 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1027 }
1028
1029 void i8xx_disable_fbc(struct drm_device *dev)
1030 {
1031 struct drm_i915_private *dev_priv = dev->dev_private;
1032 unsigned long timeout = jiffies + msecs_to_jiffies(1);
1033 u32 fbc_ctl;
1034
1035 if (!I915_HAS_FBC(dev))
1036 return;
1037
1038 if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1039 return; /* Already off, just return */
1040
1041 /* Disable compression */
1042 fbc_ctl = I915_READ(FBC_CONTROL);
1043 fbc_ctl &= ~FBC_CTL_EN;
1044 I915_WRITE(FBC_CONTROL, fbc_ctl);
1045
1046 /* Wait for compressing bit to clear */
1047 while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) {
1048 if (time_after(jiffies, timeout)) {
1049 DRM_DEBUG_DRIVER("FBC idle timed out\n");
1050 break;
1051 }
1052 ; /* do nothing */
1053 }
1054
1055 intel_wait_for_vblank(dev);
1056
1057 DRM_DEBUG_KMS("disabled FBC\n");
1058 }
1059
1060 static bool i8xx_fbc_enabled(struct drm_device *dev)
1061 {
1062 struct drm_i915_private *dev_priv = dev->dev_private;
1063
1064 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1065 }
1066
1067 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1068 {
1069 struct drm_device *dev = crtc->dev;
1070 struct drm_i915_private *dev_priv = dev->dev_private;
1071 struct drm_framebuffer *fb = crtc->fb;
1072 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1073 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1075 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1076 DPFC_CTL_PLANEB);
1077 unsigned long stall_watermark = 200;
1078 u32 dpfc_ctl;
1079
1080 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1081 dev_priv->cfb_fence = obj_priv->fence_reg;
1082 dev_priv->cfb_plane = intel_crtc->plane;
1083
1084 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1085 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1086 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1087 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1088 } else {
1089 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1090 }
1091
1092 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1093 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1094 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1095 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1096 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1097
1098 /* enable it... */
1099 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1100
1101 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1102 }
1103
1104 void g4x_disable_fbc(struct drm_device *dev)
1105 {
1106 struct drm_i915_private *dev_priv = dev->dev_private;
1107 u32 dpfc_ctl;
1108
1109 /* Disable compression */
1110 dpfc_ctl = I915_READ(DPFC_CONTROL);
1111 dpfc_ctl &= ~DPFC_CTL_EN;
1112 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1113 intel_wait_for_vblank(dev);
1114
1115 DRM_DEBUG_KMS("disabled FBC\n");
1116 }
1117
1118 static bool g4x_fbc_enabled(struct drm_device *dev)
1119 {
1120 struct drm_i915_private *dev_priv = dev->dev_private;
1121
1122 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1123 }
1124
1125 bool intel_fbc_enabled(struct drm_device *dev)
1126 {
1127 struct drm_i915_private *dev_priv = dev->dev_private;
1128
1129 if (!dev_priv->display.fbc_enabled)
1130 return false;
1131
1132 return dev_priv->display.fbc_enabled(dev);
1133 }
1134
1135 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1136 {
1137 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1138
1139 if (!dev_priv->display.enable_fbc)
1140 return;
1141
1142 dev_priv->display.enable_fbc(crtc, interval);
1143 }
1144
1145 void intel_disable_fbc(struct drm_device *dev)
1146 {
1147 struct drm_i915_private *dev_priv = dev->dev_private;
1148
1149 if (!dev_priv->display.disable_fbc)
1150 return;
1151
1152 dev_priv->display.disable_fbc(dev);
1153 }
1154
1155 /**
1156 * intel_update_fbc - enable/disable FBC as needed
1157 * @crtc: CRTC to point the compressor at
1158 * @mode: mode in use
1159 *
1160 * Set up the framebuffer compression hardware at mode set time. We
1161 * enable it if possible:
1162 * - plane A only (on pre-965)
1163 * - no pixel mulitply/line duplication
1164 * - no alpha buffer discard
1165 * - no dual wide
1166 * - framebuffer <= 2048 in width, 1536 in height
1167 *
1168 * We can't assume that any compression will take place (worst case),
1169 * so the compressed buffer has to be the same size as the uncompressed
1170 * one. It also must reside (along with the line length buffer) in
1171 * stolen memory.
1172 *
1173 * We need to enable/disable FBC on a global basis.
1174 */
1175 static void intel_update_fbc(struct drm_crtc *crtc,
1176 struct drm_display_mode *mode)
1177 {
1178 struct drm_device *dev = crtc->dev;
1179 struct drm_i915_private *dev_priv = dev->dev_private;
1180 struct drm_framebuffer *fb = crtc->fb;
1181 struct intel_framebuffer *intel_fb;
1182 struct drm_i915_gem_object *obj_priv;
1183 struct drm_crtc *tmp_crtc;
1184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1185 int plane = intel_crtc->plane;
1186 int crtcs_enabled = 0;
1187
1188 DRM_DEBUG_KMS("\n");
1189
1190 if (!i915_powersave)
1191 return;
1192
1193 if (!I915_HAS_FBC(dev))
1194 return;
1195
1196 if (!crtc->fb)
1197 return;
1198
1199 intel_fb = to_intel_framebuffer(fb);
1200 obj_priv = to_intel_bo(intel_fb->obj);
1201
1202 /*
1203 * If FBC is already on, we just have to verify that we can
1204 * keep it that way...
1205 * Need to disable if:
1206 * - more than one pipe is active
1207 * - changing FBC params (stride, fence, mode)
1208 * - new fb is too large to fit in compressed buffer
1209 * - going to an unsupported config (interlace, pixel multiply, etc.)
1210 */
1211 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1212 if (tmp_crtc->enabled)
1213 crtcs_enabled++;
1214 }
1215 DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1216 if (crtcs_enabled > 1) {
1217 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1218 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1219 goto out_disable;
1220 }
1221 if (intel_fb->obj->size > dev_priv->cfb_size) {
1222 DRM_DEBUG_KMS("framebuffer too large, disabling "
1223 "compression\n");
1224 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1225 goto out_disable;
1226 }
1227 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1228 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1229 DRM_DEBUG_KMS("mode incompatible with compression, "
1230 "disabling\n");
1231 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1232 goto out_disable;
1233 }
1234 if ((mode->hdisplay > 2048) ||
1235 (mode->vdisplay > 1536)) {
1236 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1237 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1238 goto out_disable;
1239 }
1240 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1241 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1242 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1243 goto out_disable;
1244 }
1245 if (obj_priv->tiling_mode != I915_TILING_X) {
1246 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1247 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1248 goto out_disable;
1249 }
1250
1251 if (intel_fbc_enabled(dev)) {
1252 /* We can re-enable it in this case, but need to update pitch */
1253 if ((fb->pitch > dev_priv->cfb_pitch) ||
1254 (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1255 (plane != dev_priv->cfb_plane))
1256 intel_disable_fbc(dev);
1257 }
1258
1259 /* Now try to turn it back on if possible */
1260 if (!intel_fbc_enabled(dev))
1261 intel_enable_fbc(crtc, 500);
1262
1263 return;
1264
1265 out_disable:
1266 /* Multiple disables should be harmless */
1267 if (intel_fbc_enabled(dev)) {
1268 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1269 intel_disable_fbc(dev);
1270 }
1271 }
1272
1273 int
1274 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1275 {
1276 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1277 u32 alignment;
1278 int ret;
1279
1280 switch (obj_priv->tiling_mode) {
1281 case I915_TILING_NONE:
1282 alignment = 64 * 1024;
1283 break;
1284 case I915_TILING_X:
1285 /* pin() will align the object as required by fence */
1286 alignment = 0;
1287 break;
1288 case I915_TILING_Y:
1289 /* FIXME: Is this true? */
1290 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1291 return -EINVAL;
1292 default:
1293 BUG();
1294 }
1295
1296 ret = i915_gem_object_pin(obj, alignment);
1297 if (ret != 0)
1298 return ret;
1299
1300 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1301 * fence, whereas 965+ only requires a fence if using
1302 * framebuffer compression. For simplicity, we always install
1303 * a fence as the cost is not that onerous.
1304 */
1305 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1306 obj_priv->tiling_mode != I915_TILING_NONE) {
1307 ret = i915_gem_object_get_fence_reg(obj);
1308 if (ret != 0) {
1309 i915_gem_object_unpin(obj);
1310 return ret;
1311 }
1312 }
1313
1314 return 0;
1315 }
1316
1317 static int
1318 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1319 struct drm_framebuffer *old_fb)
1320 {
1321 struct drm_device *dev = crtc->dev;
1322 struct drm_i915_private *dev_priv = dev->dev_private;
1323 struct drm_i915_master_private *master_priv;
1324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1325 struct intel_framebuffer *intel_fb;
1326 struct drm_i915_gem_object *obj_priv;
1327 struct drm_gem_object *obj;
1328 int pipe = intel_crtc->pipe;
1329 int plane = intel_crtc->plane;
1330 unsigned long Start, Offset;
1331 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1332 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1333 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1334 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1335 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1336 u32 dspcntr;
1337 int ret;
1338
1339 /* no fb bound */
1340 if (!crtc->fb) {
1341 DRM_DEBUG_KMS("No FB bound\n");
1342 return 0;
1343 }
1344
1345 switch (plane) {
1346 case 0:
1347 case 1:
1348 break;
1349 default:
1350 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1351 return -EINVAL;
1352 }
1353
1354 intel_fb = to_intel_framebuffer(crtc->fb);
1355 obj = intel_fb->obj;
1356 obj_priv = to_intel_bo(obj);
1357
1358 mutex_lock(&dev->struct_mutex);
1359 ret = intel_pin_and_fence_fb_obj(dev, obj);
1360 if (ret != 0) {
1361 mutex_unlock(&dev->struct_mutex);
1362 return ret;
1363 }
1364
1365 ret = i915_gem_object_set_to_display_plane(obj);
1366 if (ret != 0) {
1367 i915_gem_object_unpin(obj);
1368 mutex_unlock(&dev->struct_mutex);
1369 return ret;
1370 }
1371
1372 dspcntr = I915_READ(dspcntr_reg);
1373 /* Mask out pixel format bits in case we change it */
1374 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1375 switch (crtc->fb->bits_per_pixel) {
1376 case 8:
1377 dspcntr |= DISPPLANE_8BPP;
1378 break;
1379 case 16:
1380 if (crtc->fb->depth == 15)
1381 dspcntr |= DISPPLANE_15_16BPP;
1382 else
1383 dspcntr |= DISPPLANE_16BPP;
1384 break;
1385 case 24:
1386 case 32:
1387 if (crtc->fb->depth == 30)
1388 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1389 else
1390 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1391 break;
1392 default:
1393 DRM_ERROR("Unknown color depth\n");
1394 i915_gem_object_unpin(obj);
1395 mutex_unlock(&dev->struct_mutex);
1396 return -EINVAL;
1397 }
1398 if (IS_I965G(dev)) {
1399 if (obj_priv->tiling_mode != I915_TILING_NONE)
1400 dspcntr |= DISPPLANE_TILED;
1401 else
1402 dspcntr &= ~DISPPLANE_TILED;
1403 }
1404
1405 if (HAS_PCH_SPLIT(dev))
1406 /* must disable */
1407 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1408
1409 I915_WRITE(dspcntr_reg, dspcntr);
1410
1411 Start = obj_priv->gtt_offset;
1412 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1413
1414 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1415 Start, Offset, x, y, crtc->fb->pitch);
1416 I915_WRITE(dspstride, crtc->fb->pitch);
1417 if (IS_I965G(dev)) {
1418 I915_WRITE(dspbase, Offset);
1419 I915_READ(dspbase);
1420 I915_WRITE(dspsurf, Start);
1421 I915_READ(dspsurf);
1422 I915_WRITE(dsptileoff, (y << 16) | x);
1423 } else {
1424 I915_WRITE(dspbase, Start + Offset);
1425 I915_READ(dspbase);
1426 }
1427
1428 if ((IS_I965G(dev) || plane == 0))
1429 intel_update_fbc(crtc, &crtc->mode);
1430
1431 intel_wait_for_vblank(dev);
1432
1433 if (old_fb) {
1434 intel_fb = to_intel_framebuffer(old_fb);
1435 obj_priv = to_intel_bo(intel_fb->obj);
1436 i915_gem_object_unpin(intel_fb->obj);
1437 }
1438 intel_increase_pllclock(crtc, true);
1439
1440 mutex_unlock(&dev->struct_mutex);
1441
1442 if (!dev->primary->master)
1443 return 0;
1444
1445 master_priv = dev->primary->master->driver_priv;
1446 if (!master_priv->sarea_priv)
1447 return 0;
1448
1449 if (pipe) {
1450 master_priv->sarea_priv->pipeB_x = x;
1451 master_priv->sarea_priv->pipeB_y = y;
1452 } else {
1453 master_priv->sarea_priv->pipeA_x = x;
1454 master_priv->sarea_priv->pipeA_y = y;
1455 }
1456
1457 return 0;
1458 }
1459
1460 /* Disable the VGA plane that we never use */
1461 static void i915_disable_vga (struct drm_device *dev)
1462 {
1463 struct drm_i915_private *dev_priv = dev->dev_private;
1464 u8 sr1;
1465 u32 vga_reg;
1466
1467 if (HAS_PCH_SPLIT(dev))
1468 vga_reg = CPU_VGACNTRL;
1469 else
1470 vga_reg = VGACNTRL;
1471
1472 if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1473 return;
1474
1475 I915_WRITE8(VGA_SR_INDEX, 1);
1476 sr1 = I915_READ8(VGA_SR_DATA);
1477 I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1478 udelay(100);
1479
1480 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1481 }
1482
1483 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1484 {
1485 struct drm_device *dev = crtc->dev;
1486 struct drm_i915_private *dev_priv = dev->dev_private;
1487 u32 dpa_ctl;
1488
1489 DRM_DEBUG_KMS("\n");
1490 dpa_ctl = I915_READ(DP_A);
1491 dpa_ctl &= ~DP_PLL_ENABLE;
1492 I915_WRITE(DP_A, dpa_ctl);
1493 }
1494
1495 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1496 {
1497 struct drm_device *dev = crtc->dev;
1498 struct drm_i915_private *dev_priv = dev->dev_private;
1499 u32 dpa_ctl;
1500
1501 dpa_ctl = I915_READ(DP_A);
1502 dpa_ctl |= DP_PLL_ENABLE;
1503 I915_WRITE(DP_A, dpa_ctl);
1504 udelay(200);
1505 }
1506
1507
1508 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1509 {
1510 struct drm_device *dev = crtc->dev;
1511 struct drm_i915_private *dev_priv = dev->dev_private;
1512 u32 dpa_ctl;
1513
1514 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1515 dpa_ctl = I915_READ(DP_A);
1516 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1517
1518 if (clock < 200000) {
1519 u32 temp;
1520 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1521 /* workaround for 160Mhz:
1522 1) program 0x4600c bits 15:0 = 0x8124
1523 2) program 0x46010 bit 0 = 1
1524 3) program 0x46034 bit 24 = 1
1525 4) program 0x64000 bit 14 = 1
1526 */
1527 temp = I915_READ(0x4600c);
1528 temp &= 0xffff0000;
1529 I915_WRITE(0x4600c, temp | 0x8124);
1530
1531 temp = I915_READ(0x46010);
1532 I915_WRITE(0x46010, temp | 1);
1533
1534 temp = I915_READ(0x46034);
1535 I915_WRITE(0x46034, temp | (1 << 24));
1536 } else {
1537 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1538 }
1539 I915_WRITE(DP_A, dpa_ctl);
1540
1541 udelay(500);
1542 }
1543
1544 /* The FDI link training functions for ILK/Ibexpeak. */
1545 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1546 {
1547 struct drm_device *dev = crtc->dev;
1548 struct drm_i915_private *dev_priv = dev->dev_private;
1549 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1550 int pipe = intel_crtc->pipe;
1551 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1552 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1553 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1554 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1555 u32 temp, tries = 0;
1556
1557 /* enable CPU FDI TX and PCH FDI RX */
1558 temp = I915_READ(fdi_tx_reg);
1559 temp |= FDI_TX_ENABLE;
1560 temp &= ~(7 << 19);
1561 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1562 temp &= ~FDI_LINK_TRAIN_NONE;
1563 temp |= FDI_LINK_TRAIN_PATTERN_1;
1564 I915_WRITE(fdi_tx_reg, temp);
1565 I915_READ(fdi_tx_reg);
1566
1567 temp = I915_READ(fdi_rx_reg);
1568 temp &= ~FDI_LINK_TRAIN_NONE;
1569 temp |= FDI_LINK_TRAIN_PATTERN_1;
1570 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1571 I915_READ(fdi_rx_reg);
1572 udelay(150);
1573
1574 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1575 for train result */
1576 temp = I915_READ(fdi_rx_imr_reg);
1577 temp &= ~FDI_RX_SYMBOL_LOCK;
1578 temp &= ~FDI_RX_BIT_LOCK;
1579 I915_WRITE(fdi_rx_imr_reg, temp);
1580 I915_READ(fdi_rx_imr_reg);
1581 udelay(150);
1582
1583 for (;;) {
1584 temp = I915_READ(fdi_rx_iir_reg);
1585 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1586
1587 if ((temp & FDI_RX_BIT_LOCK)) {
1588 DRM_DEBUG_KMS("FDI train 1 done.\n");
1589 I915_WRITE(fdi_rx_iir_reg,
1590 temp | FDI_RX_BIT_LOCK);
1591 break;
1592 }
1593
1594 tries++;
1595
1596 if (tries > 5) {
1597 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1598 break;
1599 }
1600 }
1601
1602 /* Train 2 */
1603 temp = I915_READ(fdi_tx_reg);
1604 temp &= ~FDI_LINK_TRAIN_NONE;
1605 temp |= FDI_LINK_TRAIN_PATTERN_2;
1606 I915_WRITE(fdi_tx_reg, temp);
1607
1608 temp = I915_READ(fdi_rx_reg);
1609 temp &= ~FDI_LINK_TRAIN_NONE;
1610 temp |= FDI_LINK_TRAIN_PATTERN_2;
1611 I915_WRITE(fdi_rx_reg, temp);
1612 udelay(150);
1613
1614 tries = 0;
1615
1616 for (;;) {
1617 temp = I915_READ(fdi_rx_iir_reg);
1618 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1619
1620 if (temp & FDI_RX_SYMBOL_LOCK) {
1621 I915_WRITE(fdi_rx_iir_reg,
1622 temp | FDI_RX_SYMBOL_LOCK);
1623 DRM_DEBUG_KMS("FDI train 2 done.\n");
1624 break;
1625 }
1626
1627 tries++;
1628
1629 if (tries > 5) {
1630 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1631 break;
1632 }
1633 }
1634
1635 DRM_DEBUG_KMS("FDI train done\n");
1636 }
1637
1638 static int snb_b_fdi_train_param [] = {
1639 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1640 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1641 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1642 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1643 };
1644
1645 /* The FDI link training functions for SNB/Cougarpoint. */
1646 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1647 {
1648 struct drm_device *dev = crtc->dev;
1649 struct drm_i915_private *dev_priv = dev->dev_private;
1650 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1651 int pipe = intel_crtc->pipe;
1652 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1653 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1654 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1655 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1656 u32 temp, i;
1657
1658 /* enable CPU FDI TX and PCH FDI RX */
1659 temp = I915_READ(fdi_tx_reg);
1660 temp |= FDI_TX_ENABLE;
1661 temp &= ~(7 << 19);
1662 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1663 temp &= ~FDI_LINK_TRAIN_NONE;
1664 temp |= FDI_LINK_TRAIN_PATTERN_1;
1665 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1666 /* SNB-B */
1667 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1668 I915_WRITE(fdi_tx_reg, temp);
1669 I915_READ(fdi_tx_reg);
1670
1671 temp = I915_READ(fdi_rx_reg);
1672 if (HAS_PCH_CPT(dev)) {
1673 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1674 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1675 } else {
1676 temp &= ~FDI_LINK_TRAIN_NONE;
1677 temp |= FDI_LINK_TRAIN_PATTERN_1;
1678 }
1679 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1680 I915_READ(fdi_rx_reg);
1681 udelay(150);
1682
1683 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1684 for train result */
1685 temp = I915_READ(fdi_rx_imr_reg);
1686 temp &= ~FDI_RX_SYMBOL_LOCK;
1687 temp &= ~FDI_RX_BIT_LOCK;
1688 I915_WRITE(fdi_rx_imr_reg, temp);
1689 I915_READ(fdi_rx_imr_reg);
1690 udelay(150);
1691
1692 for (i = 0; i < 4; i++ ) {
1693 temp = I915_READ(fdi_tx_reg);
1694 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1695 temp |= snb_b_fdi_train_param[i];
1696 I915_WRITE(fdi_tx_reg, temp);
1697 udelay(500);
1698
1699 temp = I915_READ(fdi_rx_iir_reg);
1700 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1701
1702 if (temp & FDI_RX_BIT_LOCK) {
1703 I915_WRITE(fdi_rx_iir_reg,
1704 temp | FDI_RX_BIT_LOCK);
1705 DRM_DEBUG_KMS("FDI train 1 done.\n");
1706 break;
1707 }
1708 }
1709 if (i == 4)
1710 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1711
1712 /* Train 2 */
1713 temp = I915_READ(fdi_tx_reg);
1714 temp &= ~FDI_LINK_TRAIN_NONE;
1715 temp |= FDI_LINK_TRAIN_PATTERN_2;
1716 if (IS_GEN6(dev)) {
1717 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1718 /* SNB-B */
1719 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1720 }
1721 I915_WRITE(fdi_tx_reg, temp);
1722
1723 temp = I915_READ(fdi_rx_reg);
1724 if (HAS_PCH_CPT(dev)) {
1725 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1726 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1727 } else {
1728 temp &= ~FDI_LINK_TRAIN_NONE;
1729 temp |= FDI_LINK_TRAIN_PATTERN_2;
1730 }
1731 I915_WRITE(fdi_rx_reg, temp);
1732 udelay(150);
1733
1734 for (i = 0; i < 4; i++ ) {
1735 temp = I915_READ(fdi_tx_reg);
1736 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1737 temp |= snb_b_fdi_train_param[i];
1738 I915_WRITE(fdi_tx_reg, temp);
1739 udelay(500);
1740
1741 temp = I915_READ(fdi_rx_iir_reg);
1742 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1743
1744 if (temp & FDI_RX_SYMBOL_LOCK) {
1745 I915_WRITE(fdi_rx_iir_reg,
1746 temp | FDI_RX_SYMBOL_LOCK);
1747 DRM_DEBUG_KMS("FDI train 2 done.\n");
1748 break;
1749 }
1750 }
1751 if (i == 4)
1752 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1753
1754 DRM_DEBUG_KMS("FDI train done.\n");
1755 }
1756
1757 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1758 {
1759 struct drm_device *dev = crtc->dev;
1760 struct drm_i915_private *dev_priv = dev->dev_private;
1761 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1762 int pipe = intel_crtc->pipe;
1763 int plane = intel_crtc->plane;
1764 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1765 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1766 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1767 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1768 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1769 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1770 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1771 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1772 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1773 int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1774 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1775 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1776 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1777 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1778 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1779 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1780 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1781 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1782 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1783 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1784 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1785 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1786 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1787 u32 temp;
1788 int n;
1789 u32 pipe_bpc;
1790
1791 temp = I915_READ(pipeconf_reg);
1792 pipe_bpc = temp & PIPE_BPC_MASK;
1793
1794 /* XXX: When our outputs are all unaware of DPMS modes other than off
1795 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1796 */
1797 switch (mode) {
1798 case DRM_MODE_DPMS_ON:
1799 case DRM_MODE_DPMS_STANDBY:
1800 case DRM_MODE_DPMS_SUSPEND:
1801 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1802
1803 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1804 temp = I915_READ(PCH_LVDS);
1805 if ((temp & LVDS_PORT_EN) == 0) {
1806 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1807 POSTING_READ(PCH_LVDS);
1808 }
1809 }
1810
1811 if (HAS_eDP) {
1812 /* enable eDP PLL */
1813 ironlake_enable_pll_edp(crtc);
1814 } else {
1815
1816 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1817 temp = I915_READ(fdi_rx_reg);
1818 /*
1819 * make the BPC in FDI Rx be consistent with that in
1820 * pipeconf reg.
1821 */
1822 temp &= ~(0x7 << 16);
1823 temp |= (pipe_bpc << 11);
1824 temp &= ~(7 << 19);
1825 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1826 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1827 I915_READ(fdi_rx_reg);
1828 udelay(200);
1829
1830 /* Switch from Rawclk to PCDclk */
1831 temp = I915_READ(fdi_rx_reg);
1832 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1833 I915_READ(fdi_rx_reg);
1834 udelay(200);
1835
1836 /* Enable CPU FDI TX PLL, always on for Ironlake */
1837 temp = I915_READ(fdi_tx_reg);
1838 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1839 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1840 I915_READ(fdi_tx_reg);
1841 udelay(100);
1842 }
1843 }
1844
1845 /* Enable panel fitting for LVDS */
1846 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1847 temp = I915_READ(pf_ctl_reg);
1848 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1849
1850 /* currently full aspect */
1851 I915_WRITE(pf_win_pos, 0);
1852
1853 I915_WRITE(pf_win_size,
1854 (dev_priv->panel_fixed_mode->hdisplay << 16) |
1855 (dev_priv->panel_fixed_mode->vdisplay));
1856 }
1857
1858 /* Enable CPU pipe */
1859 temp = I915_READ(pipeconf_reg);
1860 if ((temp & PIPEACONF_ENABLE) == 0) {
1861 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1862 I915_READ(pipeconf_reg);
1863 udelay(100);
1864 }
1865
1866 /* configure and enable CPU plane */
1867 temp = I915_READ(dspcntr_reg);
1868 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1869 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1870 /* Flush the plane changes */
1871 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1872 }
1873
1874 if (!HAS_eDP) {
1875 /* For PCH output, training FDI link */
1876 if (IS_GEN6(dev))
1877 gen6_fdi_link_train(crtc);
1878 else
1879 ironlake_fdi_link_train(crtc);
1880
1881 /* enable PCH DPLL */
1882 temp = I915_READ(pch_dpll_reg);
1883 if ((temp & DPLL_VCO_ENABLE) == 0) {
1884 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1885 I915_READ(pch_dpll_reg);
1886 }
1887 udelay(200);
1888
1889 if (HAS_PCH_CPT(dev)) {
1890 /* Be sure PCH DPLL SEL is set */
1891 temp = I915_READ(PCH_DPLL_SEL);
1892 if (trans_dpll_sel == 0 &&
1893 (temp & TRANSA_DPLL_ENABLE) == 0)
1894 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1895 else if (trans_dpll_sel == 1 &&
1896 (temp & TRANSB_DPLL_ENABLE) == 0)
1897 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1898 I915_WRITE(PCH_DPLL_SEL, temp);
1899 I915_READ(PCH_DPLL_SEL);
1900 }
1901
1902 /* set transcoder timing */
1903 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1904 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1905 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1906
1907 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1908 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1909 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1910
1911 /* enable normal train */
1912 temp = I915_READ(fdi_tx_reg);
1913 temp &= ~FDI_LINK_TRAIN_NONE;
1914 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1915 FDI_TX_ENHANCE_FRAME_ENABLE);
1916 I915_READ(fdi_tx_reg);
1917
1918 temp = I915_READ(fdi_rx_reg);
1919 if (HAS_PCH_CPT(dev)) {
1920 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1921 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1922 } else {
1923 temp &= ~FDI_LINK_TRAIN_NONE;
1924 temp |= FDI_LINK_TRAIN_NONE;
1925 }
1926 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1927 I915_READ(fdi_rx_reg);
1928
1929 /* wait one idle pattern time */
1930 udelay(100);
1931
1932 /* For PCH DP, enable TRANS_DP_CTL */
1933 if (HAS_PCH_CPT(dev) &&
1934 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
1935 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
1936 int reg;
1937
1938 reg = I915_READ(trans_dp_ctl);
1939 reg &= ~TRANS_DP_PORT_SEL_MASK;
1940 reg = TRANS_DP_OUTPUT_ENABLE |
1941 TRANS_DP_ENH_FRAMING |
1942 TRANS_DP_VSYNC_ACTIVE_HIGH |
1943 TRANS_DP_HSYNC_ACTIVE_HIGH;
1944
1945 switch (intel_trans_dp_port_sel(crtc)) {
1946 case PCH_DP_B:
1947 reg |= TRANS_DP_PORT_SEL_B;
1948 break;
1949 case PCH_DP_C:
1950 reg |= TRANS_DP_PORT_SEL_C;
1951 break;
1952 case PCH_DP_D:
1953 reg |= TRANS_DP_PORT_SEL_D;
1954 break;
1955 default:
1956 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
1957 reg |= TRANS_DP_PORT_SEL_B;
1958 break;
1959 }
1960
1961 I915_WRITE(trans_dp_ctl, reg);
1962 POSTING_READ(trans_dp_ctl);
1963 }
1964
1965 /* enable PCH transcoder */
1966 temp = I915_READ(transconf_reg);
1967 /*
1968 * make the BPC in transcoder be consistent with
1969 * that in pipeconf reg.
1970 */
1971 temp &= ~PIPE_BPC_MASK;
1972 temp |= pipe_bpc;
1973 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1974 I915_READ(transconf_reg);
1975
1976 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1977 ;
1978
1979 }
1980
1981 intel_crtc_load_lut(crtc);
1982
1983 break;
1984 case DRM_MODE_DPMS_OFF:
1985 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1986
1987 drm_vblank_off(dev, pipe);
1988 /* Disable display plane */
1989 temp = I915_READ(dspcntr_reg);
1990 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1991 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1992 /* Flush the plane changes */
1993 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1994 I915_READ(dspbase_reg);
1995 }
1996
1997 i915_disable_vga(dev);
1998
1999 /* disable cpu pipe, disable after all planes disabled */
2000 temp = I915_READ(pipeconf_reg);
2001 if ((temp & PIPEACONF_ENABLE) != 0) {
2002 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2003 I915_READ(pipeconf_reg);
2004 n = 0;
2005 /* wait for cpu pipe off, pipe state */
2006 while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
2007 n++;
2008 if (n < 60) {
2009 udelay(500);
2010 continue;
2011 } else {
2012 DRM_DEBUG_KMS("pipe %d off delay\n",
2013 pipe);
2014 break;
2015 }
2016 }
2017 } else
2018 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2019
2020 udelay(100);
2021
2022 /* Disable PF */
2023 temp = I915_READ(pf_ctl_reg);
2024 if ((temp & PF_ENABLE) != 0) {
2025 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2026 I915_READ(pf_ctl_reg);
2027 }
2028 I915_WRITE(pf_win_size, 0);
2029 POSTING_READ(pf_win_size);
2030
2031
2032 /* disable CPU FDI tx and PCH FDI rx */
2033 temp = I915_READ(fdi_tx_reg);
2034 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2035 I915_READ(fdi_tx_reg);
2036
2037 temp = I915_READ(fdi_rx_reg);
2038 /* BPC in FDI rx is consistent with that in pipeconf */
2039 temp &= ~(0x07 << 16);
2040 temp |= (pipe_bpc << 11);
2041 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2042 I915_READ(fdi_rx_reg);
2043
2044 udelay(100);
2045
2046 /* still set train pattern 1 */
2047 temp = I915_READ(fdi_tx_reg);
2048 temp &= ~FDI_LINK_TRAIN_NONE;
2049 temp |= FDI_LINK_TRAIN_PATTERN_1;
2050 I915_WRITE(fdi_tx_reg, temp);
2051 POSTING_READ(fdi_tx_reg);
2052
2053 temp = I915_READ(fdi_rx_reg);
2054 if (HAS_PCH_CPT(dev)) {
2055 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2056 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2057 } else {
2058 temp &= ~FDI_LINK_TRAIN_NONE;
2059 temp |= FDI_LINK_TRAIN_PATTERN_1;
2060 }
2061 I915_WRITE(fdi_rx_reg, temp);
2062 POSTING_READ(fdi_rx_reg);
2063
2064 udelay(100);
2065
2066 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2067 temp = I915_READ(PCH_LVDS);
2068 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2069 I915_READ(PCH_LVDS);
2070 udelay(100);
2071 }
2072
2073 /* disable PCH transcoder */
2074 temp = I915_READ(transconf_reg);
2075 if ((temp & TRANS_ENABLE) != 0) {
2076 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2077 I915_READ(transconf_reg);
2078 n = 0;
2079 /* wait for PCH transcoder off, transcoder state */
2080 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
2081 n++;
2082 if (n < 60) {
2083 udelay(500);
2084 continue;
2085 } else {
2086 DRM_DEBUG_KMS("transcoder %d off "
2087 "delay\n", pipe);
2088 break;
2089 }
2090 }
2091 }
2092
2093 temp = I915_READ(transconf_reg);
2094 /* BPC in transcoder is consistent with that in pipeconf */
2095 temp &= ~PIPE_BPC_MASK;
2096 temp |= pipe_bpc;
2097 I915_WRITE(transconf_reg, temp);
2098 I915_READ(transconf_reg);
2099 udelay(100);
2100
2101 if (HAS_PCH_CPT(dev)) {
2102 /* disable TRANS_DP_CTL */
2103 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2104 int reg;
2105
2106 reg = I915_READ(trans_dp_ctl);
2107 reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2108 I915_WRITE(trans_dp_ctl, reg);
2109 POSTING_READ(trans_dp_ctl);
2110
2111 /* disable DPLL_SEL */
2112 temp = I915_READ(PCH_DPLL_SEL);
2113 if (trans_dpll_sel == 0)
2114 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2115 else
2116 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2117 I915_WRITE(PCH_DPLL_SEL, temp);
2118 I915_READ(PCH_DPLL_SEL);
2119
2120 }
2121
2122 /* disable PCH DPLL */
2123 temp = I915_READ(pch_dpll_reg);
2124 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2125 I915_READ(pch_dpll_reg);
2126
2127 if (HAS_eDP) {
2128 ironlake_disable_pll_edp(crtc);
2129 }
2130
2131 /* Switch from PCDclk to Rawclk */
2132 temp = I915_READ(fdi_rx_reg);
2133 temp &= ~FDI_SEL_PCDCLK;
2134 I915_WRITE(fdi_rx_reg, temp);
2135 I915_READ(fdi_rx_reg);
2136
2137 /* Disable CPU FDI TX PLL */
2138 temp = I915_READ(fdi_tx_reg);
2139 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2140 I915_READ(fdi_tx_reg);
2141 udelay(100);
2142
2143 temp = I915_READ(fdi_rx_reg);
2144 temp &= ~FDI_RX_PLL_ENABLE;
2145 I915_WRITE(fdi_rx_reg, temp);
2146 I915_READ(fdi_rx_reg);
2147
2148 /* Wait for the clocks to turn off. */
2149 udelay(100);
2150 break;
2151 }
2152 }
2153
2154 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2155 {
2156 struct intel_overlay *overlay;
2157 int ret;
2158
2159 if (!enable && intel_crtc->overlay) {
2160 overlay = intel_crtc->overlay;
2161 mutex_lock(&overlay->dev->struct_mutex);
2162 for (;;) {
2163 ret = intel_overlay_switch_off(overlay);
2164 if (ret == 0)
2165 break;
2166
2167 ret = intel_overlay_recover_from_interrupt(overlay, 0);
2168 if (ret != 0) {
2169 /* overlay doesn't react anymore. Usually
2170 * results in a black screen and an unkillable
2171 * X server. */
2172 BUG();
2173 overlay->hw_wedged = HW_WEDGED;
2174 break;
2175 }
2176 }
2177 mutex_unlock(&overlay->dev->struct_mutex);
2178 }
2179 /* Let userspace switch the overlay on again. In most cases userspace
2180 * has to recompute where to put it anyway. */
2181
2182 return;
2183 }
2184
2185 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2186 {
2187 struct drm_device *dev = crtc->dev;
2188 struct drm_i915_private *dev_priv = dev->dev_private;
2189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2190 int pipe = intel_crtc->pipe;
2191 int plane = intel_crtc->plane;
2192 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2193 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2194 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2195 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2196 u32 temp;
2197
2198 /* XXX: When our outputs are all unaware of DPMS modes other than off
2199 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2200 */
2201 switch (mode) {
2202 case DRM_MODE_DPMS_ON:
2203 case DRM_MODE_DPMS_STANDBY:
2204 case DRM_MODE_DPMS_SUSPEND:
2205 intel_update_watermarks(dev);
2206
2207 /* Enable the DPLL */
2208 temp = I915_READ(dpll_reg);
2209 if ((temp & DPLL_VCO_ENABLE) == 0) {
2210 I915_WRITE(dpll_reg, temp);
2211 I915_READ(dpll_reg);
2212 /* Wait for the clocks to stabilize. */
2213 udelay(150);
2214 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2215 I915_READ(dpll_reg);
2216 /* Wait for the clocks to stabilize. */
2217 udelay(150);
2218 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2219 I915_READ(dpll_reg);
2220 /* Wait for the clocks to stabilize. */
2221 udelay(150);
2222 }
2223
2224 /* Enable the pipe */
2225 temp = I915_READ(pipeconf_reg);
2226 if ((temp & PIPEACONF_ENABLE) == 0)
2227 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2228
2229 /* Enable the plane */
2230 temp = I915_READ(dspcntr_reg);
2231 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2232 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2233 /* Flush the plane changes */
2234 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2235 }
2236
2237 intel_crtc_load_lut(crtc);
2238
2239 if ((IS_I965G(dev) || plane == 0))
2240 intel_update_fbc(crtc, &crtc->mode);
2241
2242 /* Give the overlay scaler a chance to enable if it's on this pipe */
2243 intel_crtc_dpms_overlay(intel_crtc, true);
2244 break;
2245 case DRM_MODE_DPMS_OFF:
2246 intel_update_watermarks(dev);
2247
2248 /* Give the overlay scaler a chance to disable if it's on this pipe */
2249 intel_crtc_dpms_overlay(intel_crtc, false);
2250 drm_vblank_off(dev, pipe);
2251
2252 if (dev_priv->cfb_plane == plane &&
2253 dev_priv->display.disable_fbc)
2254 dev_priv->display.disable_fbc(dev);
2255
2256 /* Disable the VGA plane that we never use */
2257 i915_disable_vga(dev);
2258
2259 /* Disable display plane */
2260 temp = I915_READ(dspcntr_reg);
2261 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2262 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2263 /* Flush the plane changes */
2264 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2265 I915_READ(dspbase_reg);
2266 }
2267
2268 if (!IS_I9XX(dev)) {
2269 /* Wait for vblank for the disable to take effect */
2270 intel_wait_for_vblank(dev);
2271 }
2272
2273 /* Next, disable display pipes */
2274 temp = I915_READ(pipeconf_reg);
2275 if ((temp & PIPEACONF_ENABLE) != 0) {
2276 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2277 I915_READ(pipeconf_reg);
2278 }
2279
2280 /* Wait for vblank for the disable to take effect. */
2281 intel_wait_for_vblank(dev);
2282
2283 temp = I915_READ(dpll_reg);
2284 if ((temp & DPLL_VCO_ENABLE) != 0) {
2285 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2286 I915_READ(dpll_reg);
2287 }
2288
2289 /* Wait for the clocks to turn off. */
2290 udelay(150);
2291 break;
2292 }
2293 }
2294
2295 /**
2296 * Sets the power management mode of the pipe and plane.
2297 *
2298 * This code should probably grow support for turning the cursor off and back
2299 * on appropriately at the same time as we're turning the pipe off/on.
2300 */
2301 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2302 {
2303 struct drm_device *dev = crtc->dev;
2304 struct drm_i915_private *dev_priv = dev->dev_private;
2305 struct drm_i915_master_private *master_priv;
2306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2307 int pipe = intel_crtc->pipe;
2308 bool enabled;
2309
2310 dev_priv->display.dpms(crtc, mode);
2311
2312 intel_crtc->dpms_mode = mode;
2313
2314 if (!dev->primary->master)
2315 return;
2316
2317 master_priv = dev->primary->master->driver_priv;
2318 if (!master_priv->sarea_priv)
2319 return;
2320
2321 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2322
2323 switch (pipe) {
2324 case 0:
2325 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2326 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2327 break;
2328 case 1:
2329 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2330 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2331 break;
2332 default:
2333 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2334 break;
2335 }
2336 }
2337
2338 static void intel_crtc_prepare (struct drm_crtc *crtc)
2339 {
2340 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2341 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2342 }
2343
2344 static void intel_crtc_commit (struct drm_crtc *crtc)
2345 {
2346 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2347 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2348 }
2349
2350 void intel_encoder_prepare (struct drm_encoder *encoder)
2351 {
2352 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2353 /* lvds has its own version of prepare see intel_lvds_prepare */
2354 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2355 }
2356
2357 void intel_encoder_commit (struct drm_encoder *encoder)
2358 {
2359 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2360 /* lvds has its own version of commit see intel_lvds_commit */
2361 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2362 }
2363
2364 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2365 struct drm_display_mode *mode,
2366 struct drm_display_mode *adjusted_mode)
2367 {
2368 struct drm_device *dev = crtc->dev;
2369 if (HAS_PCH_SPLIT(dev)) {
2370 /* FDI link clock is fixed at 2.7G */
2371 if (mode->clock * 3 > 27000 * 4)
2372 return MODE_CLOCK_HIGH;
2373 }
2374
2375 drm_mode_set_crtcinfo(adjusted_mode, 0);
2376 return true;
2377 }
2378
2379 static int i945_get_display_clock_speed(struct drm_device *dev)
2380 {
2381 return 400000;
2382 }
2383
2384 static int i915_get_display_clock_speed(struct drm_device *dev)
2385 {
2386 return 333000;
2387 }
2388
2389 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2390 {
2391 return 200000;
2392 }
2393
2394 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2395 {
2396 u16 gcfgc = 0;
2397
2398 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2399
2400 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2401 return 133000;
2402 else {
2403 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2404 case GC_DISPLAY_CLOCK_333_MHZ:
2405 return 333000;
2406 default:
2407 case GC_DISPLAY_CLOCK_190_200_MHZ:
2408 return 190000;
2409 }
2410 }
2411 }
2412
2413 static int i865_get_display_clock_speed(struct drm_device *dev)
2414 {
2415 return 266000;
2416 }
2417
2418 static int i855_get_display_clock_speed(struct drm_device *dev)
2419 {
2420 u16 hpllcc = 0;
2421 /* Assume that the hardware is in the high speed state. This
2422 * should be the default.
2423 */
2424 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2425 case GC_CLOCK_133_200:
2426 case GC_CLOCK_100_200:
2427 return 200000;
2428 case GC_CLOCK_166_250:
2429 return 250000;
2430 case GC_CLOCK_100_133:
2431 return 133000;
2432 }
2433
2434 /* Shouldn't happen */
2435 return 0;
2436 }
2437
2438 static int i830_get_display_clock_speed(struct drm_device *dev)
2439 {
2440 return 133000;
2441 }
2442
2443 /**
2444 * Return the pipe currently connected to the panel fitter,
2445 * or -1 if the panel fitter is not present or not in use
2446 */
2447 int intel_panel_fitter_pipe (struct drm_device *dev)
2448 {
2449 struct drm_i915_private *dev_priv = dev->dev_private;
2450 u32 pfit_control;
2451
2452 /* i830 doesn't have a panel fitter */
2453 if (IS_I830(dev))
2454 return -1;
2455
2456 pfit_control = I915_READ(PFIT_CONTROL);
2457
2458 /* See if the panel fitter is in use */
2459 if ((pfit_control & PFIT_ENABLE) == 0)
2460 return -1;
2461
2462 /* 965 can place panel fitter on either pipe */
2463 if (IS_I965G(dev))
2464 return (pfit_control >> 29) & 0x3;
2465
2466 /* older chips can only use pipe 1 */
2467 return 1;
2468 }
2469
2470 struct fdi_m_n {
2471 u32 tu;
2472 u32 gmch_m;
2473 u32 gmch_n;
2474 u32 link_m;
2475 u32 link_n;
2476 };
2477
2478 static void
2479 fdi_reduce_ratio(u32 *num, u32 *den)
2480 {
2481 while (*num > 0xffffff || *den > 0xffffff) {
2482 *num >>= 1;
2483 *den >>= 1;
2484 }
2485 }
2486
2487 #define DATA_N 0x800000
2488 #define LINK_N 0x80000
2489
2490 static void
2491 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2492 int link_clock, struct fdi_m_n *m_n)
2493 {
2494 u64 temp;
2495
2496 m_n->tu = 64; /* default size */
2497
2498 temp = (u64) DATA_N * pixel_clock;
2499 temp = div_u64(temp, link_clock);
2500 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2501 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2502 m_n->gmch_n = DATA_N;
2503 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2504
2505 temp = (u64) LINK_N * pixel_clock;
2506 m_n->link_m = div_u64(temp, link_clock);
2507 m_n->link_n = LINK_N;
2508 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2509 }
2510
2511
2512 struct intel_watermark_params {
2513 unsigned long fifo_size;
2514 unsigned long max_wm;
2515 unsigned long default_wm;
2516 unsigned long guard_size;
2517 unsigned long cacheline_size;
2518 };
2519
2520 /* Pineview has different values for various configs */
2521 static struct intel_watermark_params pineview_display_wm = {
2522 PINEVIEW_DISPLAY_FIFO,
2523 PINEVIEW_MAX_WM,
2524 PINEVIEW_DFT_WM,
2525 PINEVIEW_GUARD_WM,
2526 PINEVIEW_FIFO_LINE_SIZE
2527 };
2528 static struct intel_watermark_params pineview_display_hplloff_wm = {
2529 PINEVIEW_DISPLAY_FIFO,
2530 PINEVIEW_MAX_WM,
2531 PINEVIEW_DFT_HPLLOFF_WM,
2532 PINEVIEW_GUARD_WM,
2533 PINEVIEW_FIFO_LINE_SIZE
2534 };
2535 static struct intel_watermark_params pineview_cursor_wm = {
2536 PINEVIEW_CURSOR_FIFO,
2537 PINEVIEW_CURSOR_MAX_WM,
2538 PINEVIEW_CURSOR_DFT_WM,
2539 PINEVIEW_CURSOR_GUARD_WM,
2540 PINEVIEW_FIFO_LINE_SIZE,
2541 };
2542 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2543 PINEVIEW_CURSOR_FIFO,
2544 PINEVIEW_CURSOR_MAX_WM,
2545 PINEVIEW_CURSOR_DFT_WM,
2546 PINEVIEW_CURSOR_GUARD_WM,
2547 PINEVIEW_FIFO_LINE_SIZE
2548 };
2549 static struct intel_watermark_params g4x_wm_info = {
2550 G4X_FIFO_SIZE,
2551 G4X_MAX_WM,
2552 G4X_MAX_WM,
2553 2,
2554 G4X_FIFO_LINE_SIZE,
2555 };
2556 static struct intel_watermark_params i945_wm_info = {
2557 I945_FIFO_SIZE,
2558 I915_MAX_WM,
2559 1,
2560 2,
2561 I915_FIFO_LINE_SIZE
2562 };
2563 static struct intel_watermark_params i915_wm_info = {
2564 I915_FIFO_SIZE,
2565 I915_MAX_WM,
2566 1,
2567 2,
2568 I915_FIFO_LINE_SIZE
2569 };
2570 static struct intel_watermark_params i855_wm_info = {
2571 I855GM_FIFO_SIZE,
2572 I915_MAX_WM,
2573 1,
2574 2,
2575 I830_FIFO_LINE_SIZE
2576 };
2577 static struct intel_watermark_params i830_wm_info = {
2578 I830_FIFO_SIZE,
2579 I915_MAX_WM,
2580 1,
2581 2,
2582 I830_FIFO_LINE_SIZE
2583 };
2584
2585 static struct intel_watermark_params ironlake_display_wm_info = {
2586 ILK_DISPLAY_FIFO,
2587 ILK_DISPLAY_MAXWM,
2588 ILK_DISPLAY_DFTWM,
2589 2,
2590 ILK_FIFO_LINE_SIZE
2591 };
2592
2593 static struct intel_watermark_params ironlake_display_srwm_info = {
2594 ILK_DISPLAY_SR_FIFO,
2595 ILK_DISPLAY_MAX_SRWM,
2596 ILK_DISPLAY_DFT_SRWM,
2597 2,
2598 ILK_FIFO_LINE_SIZE
2599 };
2600
2601 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2602 ILK_CURSOR_SR_FIFO,
2603 ILK_CURSOR_MAX_SRWM,
2604 ILK_CURSOR_DFT_SRWM,
2605 2,
2606 ILK_FIFO_LINE_SIZE
2607 };
2608
2609 /**
2610 * intel_calculate_wm - calculate watermark level
2611 * @clock_in_khz: pixel clock
2612 * @wm: chip FIFO params
2613 * @pixel_size: display pixel size
2614 * @latency_ns: memory latency for the platform
2615 *
2616 * Calculate the watermark level (the level at which the display plane will
2617 * start fetching from memory again). Each chip has a different display
2618 * FIFO size and allocation, so the caller needs to figure that out and pass
2619 * in the correct intel_watermark_params structure.
2620 *
2621 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2622 * on the pixel size. When it reaches the watermark level, it'll start
2623 * fetching FIFO line sized based chunks from memory until the FIFO fills
2624 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2625 * will occur, and a display engine hang could result.
2626 */
2627 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2628 struct intel_watermark_params *wm,
2629 int pixel_size,
2630 unsigned long latency_ns)
2631 {
2632 long entries_required, wm_size;
2633
2634 /*
2635 * Note: we need to make sure we don't overflow for various clock &
2636 * latency values.
2637 * clocks go from a few thousand to several hundred thousand.
2638 * latency is usually a few thousand
2639 */
2640 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2641 1000;
2642 entries_required /= wm->cacheline_size;
2643
2644 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2645
2646 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2647
2648 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2649
2650 /* Don't promote wm_size to unsigned... */
2651 if (wm_size > (long)wm->max_wm)
2652 wm_size = wm->max_wm;
2653 if (wm_size <= 0)
2654 wm_size = wm->default_wm;
2655 return wm_size;
2656 }
2657
2658 struct cxsr_latency {
2659 int is_desktop;
2660 int is_ddr3;
2661 unsigned long fsb_freq;
2662 unsigned long mem_freq;
2663 unsigned long display_sr;
2664 unsigned long display_hpll_disable;
2665 unsigned long cursor_sr;
2666 unsigned long cursor_hpll_disable;
2667 };
2668
2669 static struct cxsr_latency cxsr_latency_table[] = {
2670 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2671 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2672 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2673 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2674 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2675
2676 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2677 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2678 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2679 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2680 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2681
2682 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2683 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2684 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2685 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2686 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2687
2688 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2689 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2690 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2691 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2692 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2693
2694 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2695 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2696 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2697 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2698 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2699
2700 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2701 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2702 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2703 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2704 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2705 };
2706
2707 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3,
2708 int fsb, int mem)
2709 {
2710 int i;
2711 struct cxsr_latency *latency;
2712
2713 if (fsb == 0 || mem == 0)
2714 return NULL;
2715
2716 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2717 latency = &cxsr_latency_table[i];
2718 if (is_desktop == latency->is_desktop &&
2719 is_ddr3 == latency->is_ddr3 &&
2720 fsb == latency->fsb_freq && mem == latency->mem_freq)
2721 return latency;
2722 }
2723
2724 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2725
2726 return NULL;
2727 }
2728
2729 static void pineview_disable_cxsr(struct drm_device *dev)
2730 {
2731 struct drm_i915_private *dev_priv = dev->dev_private;
2732 u32 reg;
2733
2734 /* deactivate cxsr */
2735 reg = I915_READ(DSPFW3);
2736 reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2737 I915_WRITE(DSPFW3, reg);
2738 DRM_INFO("Big FIFO is disabled\n");
2739 }
2740
2741 /*
2742 * Latency for FIFO fetches is dependent on several factors:
2743 * - memory configuration (speed, channels)
2744 * - chipset
2745 * - current MCH state
2746 * It can be fairly high in some situations, so here we assume a fairly
2747 * pessimal value. It's a tradeoff between extra memory fetches (if we
2748 * set this value too high, the FIFO will fetch frequently to stay full)
2749 * and power consumption (set it too low to save power and we might see
2750 * FIFO underruns and display "flicker").
2751 *
2752 * A value of 5us seems to be a good balance; safe for very low end
2753 * platforms but not overly aggressive on lower latency configs.
2754 */
2755 static const int latency_ns = 5000;
2756
2757 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2758 {
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 uint32_t dsparb = I915_READ(DSPARB);
2761 int size;
2762
2763 if (plane == 0)
2764 size = dsparb & 0x7f;
2765 else
2766 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2767 (dsparb & 0x7f);
2768
2769 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2770 plane ? "B" : "A", size);
2771
2772 return size;
2773 }
2774
2775 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2776 {
2777 struct drm_i915_private *dev_priv = dev->dev_private;
2778 uint32_t dsparb = I915_READ(DSPARB);
2779 int size;
2780
2781 if (plane == 0)
2782 size = dsparb & 0x1ff;
2783 else
2784 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2785 (dsparb & 0x1ff);
2786 size >>= 1; /* Convert to cachelines */
2787
2788 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2789 plane ? "B" : "A", size);
2790
2791 return size;
2792 }
2793
2794 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2795 {
2796 struct drm_i915_private *dev_priv = dev->dev_private;
2797 uint32_t dsparb = I915_READ(DSPARB);
2798 int size;
2799
2800 size = dsparb & 0x7f;
2801 size >>= 2; /* Convert to cachelines */
2802
2803 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2804 plane ? "B" : "A",
2805 size);
2806
2807 return size;
2808 }
2809
2810 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2811 {
2812 struct drm_i915_private *dev_priv = dev->dev_private;
2813 uint32_t dsparb = I915_READ(DSPARB);
2814 int size;
2815
2816 size = dsparb & 0x7f;
2817 size >>= 1; /* Convert to cachelines */
2818
2819 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2820 plane ? "B" : "A", size);
2821
2822 return size;
2823 }
2824
2825 static void pineview_update_wm(struct drm_device *dev, int planea_clock,
2826 int planeb_clock, int sr_hdisplay, int pixel_size)
2827 {
2828 struct drm_i915_private *dev_priv = dev->dev_private;
2829 u32 reg;
2830 unsigned long wm;
2831 struct cxsr_latency *latency;
2832 int sr_clock;
2833
2834 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
2835 dev_priv->fsb_freq, dev_priv->mem_freq);
2836 if (!latency) {
2837 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2838 pineview_disable_cxsr(dev);
2839 return;
2840 }
2841
2842 if (!planea_clock || !planeb_clock) {
2843 sr_clock = planea_clock ? planea_clock : planeb_clock;
2844
2845 /* Display SR */
2846 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2847 pixel_size, latency->display_sr);
2848 reg = I915_READ(DSPFW1);
2849 reg &= ~DSPFW_SR_MASK;
2850 reg |= wm << DSPFW_SR_SHIFT;
2851 I915_WRITE(DSPFW1, reg);
2852 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2853
2854 /* cursor SR */
2855 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2856 pixel_size, latency->cursor_sr);
2857 reg = I915_READ(DSPFW3);
2858 reg &= ~DSPFW_CURSOR_SR_MASK;
2859 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2860 I915_WRITE(DSPFW3, reg);
2861
2862 /* Display HPLL off SR */
2863 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2864 pixel_size, latency->display_hpll_disable);
2865 reg = I915_READ(DSPFW3);
2866 reg &= ~DSPFW_HPLL_SR_MASK;
2867 reg |= wm & DSPFW_HPLL_SR_MASK;
2868 I915_WRITE(DSPFW3, reg);
2869
2870 /* cursor HPLL off SR */
2871 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2872 pixel_size, latency->cursor_hpll_disable);
2873 reg = I915_READ(DSPFW3);
2874 reg &= ~DSPFW_HPLL_CURSOR_MASK;
2875 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
2876 I915_WRITE(DSPFW3, reg);
2877 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2878
2879 /* activate cxsr */
2880 reg = I915_READ(DSPFW3);
2881 reg |= PINEVIEW_SELF_REFRESH_EN;
2882 I915_WRITE(DSPFW3, reg);
2883 DRM_DEBUG_KMS("Self-refresh is enabled\n");
2884 } else {
2885 pineview_disable_cxsr(dev);
2886 DRM_DEBUG_KMS("Self-refresh is disabled\n");
2887 }
2888 }
2889
2890 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
2891 int planeb_clock, int sr_hdisplay, int pixel_size)
2892 {
2893 struct drm_i915_private *dev_priv = dev->dev_private;
2894 int total_size, cacheline_size;
2895 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2896 struct intel_watermark_params planea_params, planeb_params;
2897 unsigned long line_time_us;
2898 int sr_clock, sr_entries = 0, entries_required;
2899
2900 /* Create copies of the base settings for each pipe */
2901 planea_params = planeb_params = g4x_wm_info;
2902
2903 /* Grab a couple of global values before we overwrite them */
2904 total_size = planea_params.fifo_size;
2905 cacheline_size = planea_params.cacheline_size;
2906
2907 /*
2908 * Note: we need to make sure we don't overflow for various clock &
2909 * latency values.
2910 * clocks go from a few thousand to several hundred thousand.
2911 * latency is usually a few thousand
2912 */
2913 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2914 1000;
2915 entries_required /= G4X_FIFO_LINE_SIZE;
2916 planea_wm = entries_required + planea_params.guard_size;
2917
2918 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2919 1000;
2920 entries_required /= G4X_FIFO_LINE_SIZE;
2921 planeb_wm = entries_required + planeb_params.guard_size;
2922
2923 cursora_wm = cursorb_wm = 16;
2924 cursor_sr = 32;
2925
2926 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2927
2928 /* Calc sr entries for one plane configs */
2929 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2930 /* self-refresh has much higher latency */
2931 static const int sr_latency_ns = 12000;
2932
2933 sr_clock = planea_clock ? planea_clock : planeb_clock;
2934 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2935
2936 /* Use ns/us then divide to preserve precision */
2937 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2938 pixel_size * sr_hdisplay) / 1000;
2939 sr_entries = roundup(sr_entries / cacheline_size, 1);
2940 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2941 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2942 } else {
2943 /* Turn off self refresh if both pipes are enabled */
2944 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2945 & ~FW_BLC_SELF_EN);
2946 }
2947
2948 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2949 planea_wm, planeb_wm, sr_entries);
2950
2951 planea_wm &= 0x3f;
2952 planeb_wm &= 0x3f;
2953
2954 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2955 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2956 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2957 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2958 (cursora_wm << DSPFW_CURSORA_SHIFT));
2959 /* HPLL off in SR has some issues on G4x... disable it */
2960 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2961 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2962 }
2963
2964 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2965 int planeb_clock, int sr_hdisplay, int pixel_size)
2966 {
2967 struct drm_i915_private *dev_priv = dev->dev_private;
2968 unsigned long line_time_us;
2969 int sr_clock, sr_entries, srwm = 1;
2970
2971 /* Calc sr entries for one plane configs */
2972 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2973 /* self-refresh has much higher latency */
2974 static const int sr_latency_ns = 12000;
2975
2976 sr_clock = planea_clock ? planea_clock : planeb_clock;
2977 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2978
2979 /* Use ns/us then divide to preserve precision */
2980 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2981 pixel_size * sr_hdisplay) / 1000;
2982 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2983 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2984 srwm = I945_FIFO_SIZE - sr_entries;
2985 if (srwm < 0)
2986 srwm = 1;
2987 srwm &= 0x3f;
2988 if (IS_I965GM(dev))
2989 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2990 } else {
2991 /* Turn off self refresh if both pipes are enabled */
2992 if (IS_I965GM(dev))
2993 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2994 & ~FW_BLC_SELF_EN);
2995 }
2996
2997 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2998 srwm);
2999
3000 /* 965 has limitations... */
3001 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3002 (8 << 0));
3003 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3004 }
3005
3006 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3007 int planeb_clock, int sr_hdisplay, int pixel_size)
3008 {
3009 struct drm_i915_private *dev_priv = dev->dev_private;
3010 uint32_t fwater_lo;
3011 uint32_t fwater_hi;
3012 int total_size, cacheline_size, cwm, srwm = 1;
3013 int planea_wm, planeb_wm;
3014 struct intel_watermark_params planea_params, planeb_params;
3015 unsigned long line_time_us;
3016 int sr_clock, sr_entries = 0;
3017
3018 /* Create copies of the base settings for each pipe */
3019 if (IS_I965GM(dev) || IS_I945GM(dev))
3020 planea_params = planeb_params = i945_wm_info;
3021 else if (IS_I9XX(dev))
3022 planea_params = planeb_params = i915_wm_info;
3023 else
3024 planea_params = planeb_params = i855_wm_info;
3025
3026 /* Grab a couple of global values before we overwrite them */
3027 total_size = planea_params.fifo_size;
3028 cacheline_size = planea_params.cacheline_size;
3029
3030 /* Update per-plane FIFO sizes */
3031 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3032 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3033
3034 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3035 pixel_size, latency_ns);
3036 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3037 pixel_size, latency_ns);
3038 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3039
3040 /*
3041 * Overlay gets an aggressive default since video jitter is bad.
3042 */
3043 cwm = 2;
3044
3045 /* Calc sr entries for one plane configs */
3046 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3047 (!planea_clock || !planeb_clock)) {
3048 /* self-refresh has much higher latency */
3049 static const int sr_latency_ns = 6000;
3050
3051 sr_clock = planea_clock ? planea_clock : planeb_clock;
3052 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3053
3054 /* Use ns/us then divide to preserve precision */
3055 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
3056 pixel_size * sr_hdisplay) / 1000;
3057 sr_entries = roundup(sr_entries / cacheline_size, 1);
3058 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3059 srwm = total_size - sr_entries;
3060 if (srwm < 0)
3061 srwm = 1;
3062
3063 if (IS_I945G(dev) || IS_I945GM(dev))
3064 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3065 else if (IS_I915GM(dev)) {
3066 /* 915M has a smaller SRWM field */
3067 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3068 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3069 }
3070 } else {
3071 /* Turn off self refresh if both pipes are enabled */
3072 if (IS_I945G(dev) || IS_I945GM(dev)) {
3073 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3074 & ~FW_BLC_SELF_EN);
3075 } else if (IS_I915GM(dev)) {
3076 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3077 }
3078 }
3079
3080 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3081 planea_wm, planeb_wm, cwm, srwm);
3082
3083 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3084 fwater_hi = (cwm & 0x1f);
3085
3086 /* Set request length to 8 cachelines per fetch */
3087 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3088 fwater_hi = fwater_hi | (1 << 8);
3089
3090 I915_WRITE(FW_BLC, fwater_lo);
3091 I915_WRITE(FW_BLC2, fwater_hi);
3092 }
3093
3094 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3095 int unused2, int pixel_size)
3096 {
3097 struct drm_i915_private *dev_priv = dev->dev_private;
3098 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3099 int planea_wm;
3100
3101 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3102
3103 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3104 pixel_size, latency_ns);
3105 fwater_lo |= (3<<8) | planea_wm;
3106
3107 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3108
3109 I915_WRITE(FW_BLC, fwater_lo);
3110 }
3111
3112 #define ILK_LP0_PLANE_LATENCY 700
3113
3114 static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
3115 int planeb_clock, int sr_hdisplay, int pixel_size)
3116 {
3117 struct drm_i915_private *dev_priv = dev->dev_private;
3118 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3119 int sr_wm, cursor_wm;
3120 unsigned long line_time_us;
3121 int sr_clock, entries_required;
3122 u32 reg_value;
3123
3124 /* Calculate and update the watermark for plane A */
3125 if (planea_clock) {
3126 entries_required = ((planea_clock / 1000) * pixel_size *
3127 ILK_LP0_PLANE_LATENCY) / 1000;
3128 entries_required = DIV_ROUND_UP(entries_required,
3129 ironlake_display_wm_info.cacheline_size);
3130 planea_wm = entries_required +
3131 ironlake_display_wm_info.guard_size;
3132
3133 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3134 planea_wm = ironlake_display_wm_info.max_wm;
3135
3136 cursora_wm = 16;
3137 reg_value = I915_READ(WM0_PIPEA_ILK);
3138 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3139 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3140 (cursora_wm & WM0_PIPE_CURSOR_MASK);
3141 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3142 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3143 "cursor: %d\n", planea_wm, cursora_wm);
3144 }
3145 /* Calculate and update the watermark for plane B */
3146 if (planeb_clock) {
3147 entries_required = ((planeb_clock / 1000) * pixel_size *
3148 ILK_LP0_PLANE_LATENCY) / 1000;
3149 entries_required = DIV_ROUND_UP(entries_required,
3150 ironlake_display_wm_info.cacheline_size);
3151 planeb_wm = entries_required +
3152 ironlake_display_wm_info.guard_size;
3153
3154 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3155 planeb_wm = ironlake_display_wm_info.max_wm;
3156
3157 cursorb_wm = 16;
3158 reg_value = I915_READ(WM0_PIPEB_ILK);
3159 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3160 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3161 (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3162 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3163 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3164 "cursor: %d\n", planeb_wm, cursorb_wm);
3165 }
3166
3167 /*
3168 * Calculate and update the self-refresh watermark only when one
3169 * display plane is used.
3170 */
3171 if (!planea_clock || !planeb_clock) {
3172 int line_count;
3173 /* Read the self-refresh latency. The unit is 0.5us */
3174 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3175
3176 sr_clock = planea_clock ? planea_clock : planeb_clock;
3177 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3178
3179 /* Use ns/us then divide to preserve precision */
3180 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3181 / 1000;
3182
3183 /* calculate the self-refresh watermark for display plane */
3184 entries_required = line_count * sr_hdisplay * pixel_size;
3185 entries_required = DIV_ROUND_UP(entries_required,
3186 ironlake_display_srwm_info.cacheline_size);
3187 sr_wm = entries_required +
3188 ironlake_display_srwm_info.guard_size;
3189
3190 /* calculate the self-refresh watermark for display cursor */
3191 entries_required = line_count * pixel_size * 64;
3192 entries_required = DIV_ROUND_UP(entries_required,
3193 ironlake_cursor_srwm_info.cacheline_size);
3194 cursor_wm = entries_required +
3195 ironlake_cursor_srwm_info.guard_size;
3196
3197 /* configure watermark and enable self-refresh */
3198 reg_value = I915_READ(WM1_LP_ILK);
3199 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3200 WM1_LP_CURSOR_MASK);
3201 reg_value |= WM1_LP_SR_EN |
3202 (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3203 (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3204
3205 I915_WRITE(WM1_LP_ILK, reg_value);
3206 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3207 "cursor %d\n", sr_wm, cursor_wm);
3208
3209 } else {
3210 /* Turn off self refresh if both pipes are enabled */
3211 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3212 }
3213 }
3214 /**
3215 * intel_update_watermarks - update FIFO watermark values based on current modes
3216 *
3217 * Calculate watermark values for the various WM regs based on current mode
3218 * and plane configuration.
3219 *
3220 * There are several cases to deal with here:
3221 * - normal (i.e. non-self-refresh)
3222 * - self-refresh (SR) mode
3223 * - lines are large relative to FIFO size (buffer can hold up to 2)
3224 * - lines are small relative to FIFO size (buffer can hold more than 2
3225 * lines), so need to account for TLB latency
3226 *
3227 * The normal calculation is:
3228 * watermark = dotclock * bytes per pixel * latency
3229 * where latency is platform & configuration dependent (we assume pessimal
3230 * values here).
3231 *
3232 * The SR calculation is:
3233 * watermark = (trunc(latency/line time)+1) * surface width *
3234 * bytes per pixel
3235 * where
3236 * line time = htotal / dotclock
3237 * and latency is assumed to be high, as above.
3238 *
3239 * The final value programmed to the register should always be rounded up,
3240 * and include an extra 2 entries to account for clock crossings.
3241 *
3242 * We don't use the sprite, so we can ignore that. And on Crestline we have
3243 * to set the non-SR watermarks to 8.
3244 */
3245 static void intel_update_watermarks(struct drm_device *dev)
3246 {
3247 struct drm_i915_private *dev_priv = dev->dev_private;
3248 struct drm_crtc *crtc;
3249 struct intel_crtc *intel_crtc;
3250 int sr_hdisplay = 0;
3251 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3252 int enabled = 0, pixel_size = 0;
3253
3254 if (!dev_priv->display.update_wm)
3255 return;
3256
3257 /* Get the clock config from both planes */
3258 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3259 intel_crtc = to_intel_crtc(crtc);
3260 if (crtc->enabled) {
3261 enabled++;
3262 if (intel_crtc->plane == 0) {
3263 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3264 intel_crtc->pipe, crtc->mode.clock);
3265 planea_clock = crtc->mode.clock;
3266 } else {
3267 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3268 intel_crtc->pipe, crtc->mode.clock);
3269 planeb_clock = crtc->mode.clock;
3270 }
3271 sr_hdisplay = crtc->mode.hdisplay;
3272 sr_clock = crtc->mode.clock;
3273 if (crtc->fb)
3274 pixel_size = crtc->fb->bits_per_pixel / 8;
3275 else
3276 pixel_size = 4; /* by default */
3277 }
3278 }
3279
3280 if (enabled <= 0)
3281 return;
3282
3283 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3284 sr_hdisplay, pixel_size);
3285 }
3286
3287 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3288 struct drm_display_mode *mode,
3289 struct drm_display_mode *adjusted_mode,
3290 int x, int y,
3291 struct drm_framebuffer *old_fb)
3292 {
3293 struct drm_device *dev = crtc->dev;
3294 struct drm_i915_private *dev_priv = dev->dev_private;
3295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3296 int pipe = intel_crtc->pipe;
3297 int plane = intel_crtc->plane;
3298 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3299 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3300 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3301 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3302 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3303 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3304 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3305 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3306 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3307 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3308 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3309 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3310 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3311 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3312 int refclk, num_connectors = 0;
3313 intel_clock_t clock, reduced_clock;
3314 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3315 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3316 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3317 bool is_edp = false;
3318 struct drm_mode_config *mode_config = &dev->mode_config;
3319 struct drm_encoder *encoder;
3320 struct intel_encoder *intel_encoder = NULL;
3321 const intel_limit_t *limit;
3322 int ret;
3323 struct fdi_m_n m_n = {0};
3324 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3325 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3326 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3327 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3328 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3329 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3330 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3331 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3332 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3333 int lvds_reg = LVDS;
3334 u32 temp;
3335 int sdvo_pixel_multiply;
3336 int target_clock;
3337
3338 drm_vblank_pre_modeset(dev, pipe);
3339
3340 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3341
3342 if (!encoder || encoder->crtc != crtc)
3343 continue;
3344
3345 intel_encoder = enc_to_intel_encoder(encoder);
3346
3347 switch (intel_encoder->type) {
3348 case INTEL_OUTPUT_LVDS:
3349 is_lvds = true;
3350 break;
3351 case INTEL_OUTPUT_SDVO:
3352 case INTEL_OUTPUT_HDMI:
3353 is_sdvo = true;
3354 if (intel_encoder->needs_tv_clock)
3355 is_tv = true;
3356 break;
3357 case INTEL_OUTPUT_DVO:
3358 is_dvo = true;
3359 break;
3360 case INTEL_OUTPUT_TVOUT:
3361 is_tv = true;
3362 break;
3363 case INTEL_OUTPUT_ANALOG:
3364 is_crt = true;
3365 break;
3366 case INTEL_OUTPUT_DISPLAYPORT:
3367 is_dp = true;
3368 break;
3369 case INTEL_OUTPUT_EDP:
3370 is_edp = true;
3371 break;
3372 }
3373
3374 num_connectors++;
3375 }
3376
3377 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3378 refclk = dev_priv->lvds_ssc_freq * 1000;
3379 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3380 refclk / 1000);
3381 } else if (IS_I9XX(dev)) {
3382 refclk = 96000;
3383 if (HAS_PCH_SPLIT(dev))
3384 refclk = 120000; /* 120Mhz refclk */
3385 } else {
3386 refclk = 48000;
3387 }
3388
3389
3390 /*
3391 * Returns a set of divisors for the desired target clock with the given
3392 * refclk, or FALSE. The returned values represent the clock equation:
3393 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3394 */
3395 limit = intel_limit(crtc);
3396 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3397 if (!ok) {
3398 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3399 drm_vblank_post_modeset(dev, pipe);
3400 return -EINVAL;
3401 }
3402
3403 if (is_lvds && dev_priv->lvds_downclock_avail) {
3404 has_reduced_clock = limit->find_pll(limit, crtc,
3405 dev_priv->lvds_downclock,
3406 refclk,
3407 &reduced_clock);
3408 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3409 /*
3410 * If the different P is found, it means that we can't
3411 * switch the display clock by using the FP0/FP1.
3412 * In such case we will disable the LVDS downclock
3413 * feature.
3414 */
3415 DRM_DEBUG_KMS("Different P is found for "
3416 "LVDS clock/downclock\n");
3417 has_reduced_clock = 0;
3418 }
3419 }
3420 /* SDVO TV has fixed PLL values depend on its clock range,
3421 this mirrors vbios setting. */
3422 if (is_sdvo && is_tv) {
3423 if (adjusted_mode->clock >= 100000
3424 && adjusted_mode->clock < 140500) {
3425 clock.p1 = 2;
3426 clock.p2 = 10;
3427 clock.n = 3;
3428 clock.m1 = 16;
3429 clock.m2 = 8;
3430 } else if (adjusted_mode->clock >= 140500
3431 && adjusted_mode->clock <= 200000) {
3432 clock.p1 = 1;
3433 clock.p2 = 10;
3434 clock.n = 6;
3435 clock.m1 = 12;
3436 clock.m2 = 8;
3437 }
3438 }
3439
3440 /* FDI link */
3441 if (HAS_PCH_SPLIT(dev)) {
3442 int lane = 0, link_bw, bpp;
3443 /* eDP doesn't require FDI link, so just set DP M/N
3444 according to current link config */
3445 if (is_edp) {
3446 target_clock = mode->clock;
3447 intel_edp_link_config(intel_encoder,
3448 &lane, &link_bw);
3449 } else {
3450 /* DP over FDI requires target mode clock
3451 instead of link clock */
3452 if (is_dp)
3453 target_clock = mode->clock;
3454 else
3455 target_clock = adjusted_mode->clock;
3456 link_bw = 270000;
3457 }
3458
3459 /* determine panel color depth */
3460 temp = I915_READ(pipeconf_reg);
3461 temp &= ~PIPE_BPC_MASK;
3462 if (is_lvds) {
3463 int lvds_reg = I915_READ(PCH_LVDS);
3464 /* the BPC will be 6 if it is 18-bit LVDS panel */
3465 if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3466 temp |= PIPE_8BPC;
3467 else
3468 temp |= PIPE_6BPC;
3469 } else if (is_edp) {
3470 switch (dev_priv->edp_bpp/3) {
3471 case 8:
3472 temp |= PIPE_8BPC;
3473 break;
3474 case 10:
3475 temp |= PIPE_10BPC;
3476 break;
3477 case 6:
3478 temp |= PIPE_6BPC;
3479 break;
3480 case 12:
3481 temp |= PIPE_12BPC;
3482 break;
3483 }
3484 } else
3485 temp |= PIPE_8BPC;
3486 I915_WRITE(pipeconf_reg, temp);
3487 I915_READ(pipeconf_reg);
3488
3489 switch (temp & PIPE_BPC_MASK) {
3490 case PIPE_8BPC:
3491 bpp = 24;
3492 break;
3493 case PIPE_10BPC:
3494 bpp = 30;
3495 break;
3496 case PIPE_6BPC:
3497 bpp = 18;
3498 break;
3499 case PIPE_12BPC:
3500 bpp = 36;
3501 break;
3502 default:
3503 DRM_ERROR("unknown pipe bpc value\n");
3504 bpp = 24;
3505 }
3506
3507 if (!lane) {
3508 /*
3509 * Account for spread spectrum to avoid
3510 * oversubscribing the link. Max center spread
3511 * is 2.5%; use 5% for safety's sake.
3512 */
3513 u32 bps = target_clock * bpp * 21 / 20;
3514 lane = bps / (link_bw * 8) + 1;
3515 }
3516
3517 intel_crtc->fdi_lanes = lane;
3518
3519 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3520 }
3521
3522 /* Ironlake: try to setup display ref clock before DPLL
3523 * enabling. This is only under driver's control after
3524 * PCH B stepping, previous chipset stepping should be
3525 * ignoring this setting.
3526 */
3527 if (HAS_PCH_SPLIT(dev)) {
3528 temp = I915_READ(PCH_DREF_CONTROL);
3529 /* Always enable nonspread source */
3530 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3531 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3532 I915_WRITE(PCH_DREF_CONTROL, temp);
3533 POSTING_READ(PCH_DREF_CONTROL);
3534
3535 temp &= ~DREF_SSC_SOURCE_MASK;
3536 temp |= DREF_SSC_SOURCE_ENABLE;
3537 I915_WRITE(PCH_DREF_CONTROL, temp);
3538 POSTING_READ(PCH_DREF_CONTROL);
3539
3540 udelay(200);
3541
3542 if (is_edp) {
3543 if (dev_priv->lvds_use_ssc) {
3544 temp |= DREF_SSC1_ENABLE;
3545 I915_WRITE(PCH_DREF_CONTROL, temp);
3546 POSTING_READ(PCH_DREF_CONTROL);
3547
3548 udelay(200);
3549
3550 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3551 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3552 I915_WRITE(PCH_DREF_CONTROL, temp);
3553 POSTING_READ(PCH_DREF_CONTROL);
3554 } else {
3555 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3556 I915_WRITE(PCH_DREF_CONTROL, temp);
3557 POSTING_READ(PCH_DREF_CONTROL);
3558 }
3559 }
3560 }
3561
3562 if (IS_PINEVIEW(dev)) {
3563 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3564 if (has_reduced_clock)
3565 fp2 = (1 << reduced_clock.n) << 16 |
3566 reduced_clock.m1 << 8 | reduced_clock.m2;
3567 } else {
3568 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3569 if (has_reduced_clock)
3570 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3571 reduced_clock.m2;
3572 }
3573
3574 if (!HAS_PCH_SPLIT(dev))
3575 dpll = DPLL_VGA_MODE_DIS;
3576
3577 if (IS_I9XX(dev)) {
3578 if (is_lvds)
3579 dpll |= DPLLB_MODE_LVDS;
3580 else
3581 dpll |= DPLLB_MODE_DAC_SERIAL;
3582 if (is_sdvo) {
3583 dpll |= DPLL_DVO_HIGH_SPEED;
3584 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3585 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3586 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3587 else if (HAS_PCH_SPLIT(dev))
3588 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3589 }
3590 if (is_dp)
3591 dpll |= DPLL_DVO_HIGH_SPEED;
3592
3593 /* compute bitmask from p1 value */
3594 if (IS_PINEVIEW(dev))
3595 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3596 else {
3597 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3598 /* also FPA1 */
3599 if (HAS_PCH_SPLIT(dev))
3600 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3601 if (IS_G4X(dev) && has_reduced_clock)
3602 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3603 }
3604 switch (clock.p2) {
3605 case 5:
3606 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3607 break;
3608 case 7:
3609 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3610 break;
3611 case 10:
3612 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3613 break;
3614 case 14:
3615 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3616 break;
3617 }
3618 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3619 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3620 } else {
3621 if (is_lvds) {
3622 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3623 } else {
3624 if (clock.p1 == 2)
3625 dpll |= PLL_P1_DIVIDE_BY_TWO;
3626 else
3627 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3628 if (clock.p2 == 4)
3629 dpll |= PLL_P2_DIVIDE_BY_4;
3630 }
3631 }
3632
3633 if (is_sdvo && is_tv)
3634 dpll |= PLL_REF_INPUT_TVCLKINBC;
3635 else if (is_tv)
3636 /* XXX: just matching BIOS for now */
3637 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3638 dpll |= 3;
3639 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3640 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3641 else
3642 dpll |= PLL_REF_INPUT_DREFCLK;
3643
3644 /* setup pipeconf */
3645 pipeconf = I915_READ(pipeconf_reg);
3646
3647 /* Set up the display plane register */
3648 dspcntr = DISPPLANE_GAMMA_ENABLE;
3649
3650 /* Ironlake's plane is forced to pipe, bit 24 is to
3651 enable color space conversion */
3652 if (!HAS_PCH_SPLIT(dev)) {
3653 if (pipe == 0)
3654 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3655 else
3656 dspcntr |= DISPPLANE_SEL_PIPE_B;
3657 }
3658
3659 if (pipe == 0 && !IS_I965G(dev)) {
3660 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3661 * core speed.
3662 *
3663 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3664 * pipe == 0 check?
3665 */
3666 if (mode->clock >
3667 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3668 pipeconf |= PIPEACONF_DOUBLE_WIDE;
3669 else
3670 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3671 }
3672
3673 dspcntr |= DISPLAY_PLANE_ENABLE;
3674 pipeconf |= PIPEACONF_ENABLE;
3675 dpll |= DPLL_VCO_ENABLE;
3676
3677
3678 /* Disable the panel fitter if it was on our pipe */
3679 if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3680 I915_WRITE(PFIT_CONTROL, 0);
3681
3682 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3683 drm_mode_debug_printmodeline(mode);
3684
3685 /* assign to Ironlake registers */
3686 if (HAS_PCH_SPLIT(dev)) {
3687 fp_reg = pch_fp_reg;
3688 dpll_reg = pch_dpll_reg;
3689 }
3690
3691 if (is_edp) {
3692 ironlake_disable_pll_edp(crtc);
3693 } else if ((dpll & DPLL_VCO_ENABLE)) {
3694 I915_WRITE(fp_reg, fp);
3695 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3696 I915_READ(dpll_reg);
3697 udelay(150);
3698 }
3699
3700 /* enable transcoder DPLL */
3701 if (HAS_PCH_CPT(dev)) {
3702 temp = I915_READ(PCH_DPLL_SEL);
3703 if (trans_dpll_sel == 0)
3704 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3705 else
3706 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3707 I915_WRITE(PCH_DPLL_SEL, temp);
3708 I915_READ(PCH_DPLL_SEL);
3709 udelay(150);
3710 }
3711
3712 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3713 * This is an exception to the general rule that mode_set doesn't turn
3714 * things on.
3715 */
3716 if (is_lvds) {
3717 u32 lvds;
3718
3719 if (HAS_PCH_SPLIT(dev))
3720 lvds_reg = PCH_LVDS;
3721
3722 lvds = I915_READ(lvds_reg);
3723 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3724 if (pipe == 1) {
3725 if (HAS_PCH_CPT(dev))
3726 lvds |= PORT_TRANS_B_SEL_CPT;
3727 else
3728 lvds |= LVDS_PIPEB_SELECT;
3729 } else {
3730 if (HAS_PCH_CPT(dev))
3731 lvds &= ~PORT_TRANS_SEL_MASK;
3732 else
3733 lvds &= ~LVDS_PIPEB_SELECT;
3734 }
3735 /* set the corresponsding LVDS_BORDER bit */
3736 lvds |= dev_priv->lvds_border_bits;
3737 /* Set the B0-B3 data pairs corresponding to whether we're going to
3738 * set the DPLLs for dual-channel mode or not.
3739 */
3740 if (clock.p2 == 7)
3741 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3742 else
3743 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3744
3745 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3746 * appropriately here, but we need to look more thoroughly into how
3747 * panels behave in the two modes.
3748 */
3749 /* set the dithering flag */
3750 if (IS_I965G(dev)) {
3751 if (dev_priv->lvds_dither) {
3752 if (HAS_PCH_SPLIT(dev)) {
3753 pipeconf |= PIPE_ENABLE_DITHER;
3754 pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3755 pipeconf |= PIPE_DITHER_TYPE_ST01;
3756 } else
3757 lvds |= LVDS_ENABLE_DITHER;
3758 } else {
3759 if (HAS_PCH_SPLIT(dev)) {
3760 pipeconf &= ~PIPE_ENABLE_DITHER;
3761 pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3762 } else
3763 lvds &= ~LVDS_ENABLE_DITHER;
3764 }
3765 }
3766 I915_WRITE(lvds_reg, lvds);
3767 I915_READ(lvds_reg);
3768 }
3769 if (is_dp)
3770 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3771 else if (HAS_PCH_SPLIT(dev)) {
3772 /* For non-DP output, clear any trans DP clock recovery setting.*/
3773 if (pipe == 0) {
3774 I915_WRITE(TRANSA_DATA_M1, 0);
3775 I915_WRITE(TRANSA_DATA_N1, 0);
3776 I915_WRITE(TRANSA_DP_LINK_M1, 0);
3777 I915_WRITE(TRANSA_DP_LINK_N1, 0);
3778 } else {
3779 I915_WRITE(TRANSB_DATA_M1, 0);
3780 I915_WRITE(TRANSB_DATA_N1, 0);
3781 I915_WRITE(TRANSB_DP_LINK_M1, 0);
3782 I915_WRITE(TRANSB_DP_LINK_N1, 0);
3783 }
3784 }
3785
3786 if (!is_edp) {
3787 I915_WRITE(fp_reg, fp);
3788 I915_WRITE(dpll_reg, dpll);
3789 I915_READ(dpll_reg);
3790 /* Wait for the clocks to stabilize. */
3791 udelay(150);
3792
3793 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3794 if (is_sdvo) {
3795 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3796 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3797 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3798 } else
3799 I915_WRITE(dpll_md_reg, 0);
3800 } else {
3801 /* write it again -- the BIOS does, after all */
3802 I915_WRITE(dpll_reg, dpll);
3803 }
3804 I915_READ(dpll_reg);
3805 /* Wait for the clocks to stabilize. */
3806 udelay(150);
3807 }
3808
3809 if (is_lvds && has_reduced_clock && i915_powersave) {
3810 I915_WRITE(fp_reg + 4, fp2);
3811 intel_crtc->lowfreq_avail = true;
3812 if (HAS_PIPE_CXSR(dev)) {
3813 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3814 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3815 }
3816 } else {
3817 I915_WRITE(fp_reg + 4, fp);
3818 intel_crtc->lowfreq_avail = false;
3819 if (HAS_PIPE_CXSR(dev)) {
3820 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3821 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3822 }
3823 }
3824
3825 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
3826 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3827 /* the chip adds 2 halflines automatically */
3828 adjusted_mode->crtc_vdisplay -= 1;
3829 adjusted_mode->crtc_vtotal -= 1;
3830 adjusted_mode->crtc_vblank_start -= 1;
3831 adjusted_mode->crtc_vblank_end -= 1;
3832 adjusted_mode->crtc_vsync_end -= 1;
3833 adjusted_mode->crtc_vsync_start -= 1;
3834 } else
3835 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
3836
3837 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3838 ((adjusted_mode->crtc_htotal - 1) << 16));
3839 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3840 ((adjusted_mode->crtc_hblank_end - 1) << 16));
3841 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3842 ((adjusted_mode->crtc_hsync_end - 1) << 16));
3843 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3844 ((adjusted_mode->crtc_vtotal - 1) << 16));
3845 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3846 ((adjusted_mode->crtc_vblank_end - 1) << 16));
3847 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3848 ((adjusted_mode->crtc_vsync_end - 1) << 16));
3849 /* pipesrc and dspsize control the size that is scaled from, which should
3850 * always be the user's requested size.
3851 */
3852 if (!HAS_PCH_SPLIT(dev)) {
3853 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3854 (mode->hdisplay - 1));
3855 I915_WRITE(dsppos_reg, 0);
3856 }
3857 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3858
3859 if (HAS_PCH_SPLIT(dev)) {
3860 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3861 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3862 I915_WRITE(link_m1_reg, m_n.link_m);
3863 I915_WRITE(link_n1_reg, m_n.link_n);
3864
3865 if (is_edp) {
3866 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
3867 } else {
3868 /* enable FDI RX PLL too */
3869 temp = I915_READ(fdi_rx_reg);
3870 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3871 I915_READ(fdi_rx_reg);
3872 udelay(200);
3873
3874 /* enable FDI TX PLL too */
3875 temp = I915_READ(fdi_tx_reg);
3876 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
3877 I915_READ(fdi_tx_reg);
3878
3879 /* enable FDI RX PCDCLK */
3880 temp = I915_READ(fdi_rx_reg);
3881 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
3882 I915_READ(fdi_rx_reg);
3883 udelay(200);
3884 }
3885 }
3886
3887 I915_WRITE(pipeconf_reg, pipeconf);
3888 I915_READ(pipeconf_reg);
3889
3890 intel_wait_for_vblank(dev);
3891
3892 if (IS_IRONLAKE(dev)) {
3893 /* enable address swizzle for tiling buffer */
3894 temp = I915_READ(DISP_ARB_CTL);
3895 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3896 }
3897
3898 I915_WRITE(dspcntr_reg, dspcntr);
3899
3900 /* Flush the plane changes */
3901 ret = intel_pipe_set_base(crtc, x, y, old_fb);
3902
3903 if ((IS_I965G(dev) || plane == 0))
3904 intel_update_fbc(crtc, &crtc->mode);
3905
3906 intel_update_watermarks(dev);
3907
3908 drm_vblank_post_modeset(dev, pipe);
3909
3910 return ret;
3911 }
3912
3913 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3914 void intel_crtc_load_lut(struct drm_crtc *crtc)
3915 {
3916 struct drm_device *dev = crtc->dev;
3917 struct drm_i915_private *dev_priv = dev->dev_private;
3918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3919 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3920 int i;
3921
3922 /* The clocks have to be on to load the palette. */
3923 if (!crtc->enabled)
3924 return;
3925
3926 /* use legacy palette for Ironlake */
3927 if (HAS_PCH_SPLIT(dev))
3928 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3929 LGC_PALETTE_B;
3930
3931 for (i = 0; i < 256; i++) {
3932 I915_WRITE(palreg + 4 * i,
3933 (intel_crtc->lut_r[i] << 16) |
3934 (intel_crtc->lut_g[i] << 8) |
3935 intel_crtc->lut_b[i]);
3936 }
3937 }
3938
3939 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3940 struct drm_file *file_priv,
3941 uint32_t handle,
3942 uint32_t width, uint32_t height)
3943 {
3944 struct drm_device *dev = crtc->dev;
3945 struct drm_i915_private *dev_priv = dev->dev_private;
3946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3947 struct drm_gem_object *bo;
3948 struct drm_i915_gem_object *obj_priv;
3949 int pipe = intel_crtc->pipe;
3950 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3951 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3952 uint32_t temp = I915_READ(control);
3953 size_t addr;
3954 int ret;
3955
3956 DRM_DEBUG_KMS("\n");
3957
3958 /* if we want to turn off the cursor ignore width and height */
3959 if (!handle) {
3960 DRM_DEBUG_KMS("cursor off\n");
3961 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3962 temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3963 temp |= CURSOR_MODE_DISABLE;
3964 } else {
3965 temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3966 }
3967 addr = 0;
3968 bo = NULL;
3969 mutex_lock(&dev->struct_mutex);
3970 goto finish;
3971 }
3972
3973 /* Currently we only support 64x64 cursors */
3974 if (width != 64 || height != 64) {
3975 DRM_ERROR("we currently only support 64x64 cursors\n");
3976 return -EINVAL;
3977 }
3978
3979 bo = drm_gem_object_lookup(dev, file_priv, handle);
3980 if (!bo)
3981 return -ENOENT;
3982
3983 obj_priv = to_intel_bo(bo);
3984
3985 if (bo->size < width * height * 4) {
3986 DRM_ERROR("buffer is to small\n");
3987 ret = -ENOMEM;
3988 goto fail;
3989 }
3990
3991 /* we only need to pin inside GTT if cursor is non-phy */
3992 mutex_lock(&dev->struct_mutex);
3993 if (!dev_priv->info->cursor_needs_physical) {
3994 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3995 if (ret) {
3996 DRM_ERROR("failed to pin cursor bo\n");
3997 goto fail_locked;
3998 }
3999
4000 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4001 if (ret) {
4002 DRM_ERROR("failed to move cursor bo into the GTT\n");
4003 goto fail_unpin;
4004 }
4005
4006 addr = obj_priv->gtt_offset;
4007 } else {
4008 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
4009 if (ret) {
4010 DRM_ERROR("failed to attach phys object\n");
4011 goto fail_locked;
4012 }
4013 addr = obj_priv->phys_obj->handle->busaddr;
4014 }
4015
4016 if (!IS_I9XX(dev))
4017 I915_WRITE(CURSIZE, (height << 12) | width);
4018
4019 /* Hooray for CUR*CNTR differences */
4020 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4021 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4022 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4023 temp |= (pipe << 28); /* Connect to correct pipe */
4024 } else {
4025 temp &= ~(CURSOR_FORMAT_MASK);
4026 temp |= CURSOR_ENABLE;
4027 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
4028 }
4029
4030 finish:
4031 I915_WRITE(control, temp);
4032 I915_WRITE(base, addr);
4033
4034 if (intel_crtc->cursor_bo) {
4035 if (dev_priv->info->cursor_needs_physical) {
4036 if (intel_crtc->cursor_bo != bo)
4037 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4038 } else
4039 i915_gem_object_unpin(intel_crtc->cursor_bo);
4040 drm_gem_object_unreference(intel_crtc->cursor_bo);
4041 }
4042
4043 mutex_unlock(&dev->struct_mutex);
4044
4045 intel_crtc->cursor_addr = addr;
4046 intel_crtc->cursor_bo = bo;
4047
4048 return 0;
4049 fail_unpin:
4050 i915_gem_object_unpin(bo);
4051 fail_locked:
4052 mutex_unlock(&dev->struct_mutex);
4053 fail:
4054 drm_gem_object_unreference_unlocked(bo);
4055 return ret;
4056 }
4057
4058 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4059 {
4060 struct drm_device *dev = crtc->dev;
4061 struct drm_i915_private *dev_priv = dev->dev_private;
4062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4063 struct intel_framebuffer *intel_fb;
4064 int pipe = intel_crtc->pipe;
4065 uint32_t temp = 0;
4066 uint32_t adder;
4067
4068 if (crtc->fb) {
4069 intel_fb = to_intel_framebuffer(crtc->fb);
4070 intel_mark_busy(dev, intel_fb->obj);
4071 }
4072
4073 if (x < 0) {
4074 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4075 x = -x;
4076 }
4077 if (y < 0) {
4078 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4079 y = -y;
4080 }
4081
4082 temp |= x << CURSOR_X_SHIFT;
4083 temp |= y << CURSOR_Y_SHIFT;
4084
4085 adder = intel_crtc->cursor_addr;
4086 I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
4087 I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
4088
4089 return 0;
4090 }
4091
4092 /** Sets the color ramps on behalf of RandR */
4093 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4094 u16 blue, int regno)
4095 {
4096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4097
4098 intel_crtc->lut_r[regno] = red >> 8;
4099 intel_crtc->lut_g[regno] = green >> 8;
4100 intel_crtc->lut_b[regno] = blue >> 8;
4101 }
4102
4103 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4104 u16 *blue, int regno)
4105 {
4106 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4107
4108 *red = intel_crtc->lut_r[regno] << 8;
4109 *green = intel_crtc->lut_g[regno] << 8;
4110 *blue = intel_crtc->lut_b[regno] << 8;
4111 }
4112
4113 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4114 u16 *blue, uint32_t size)
4115 {
4116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4117 int i;
4118
4119 if (size != 256)
4120 return;
4121
4122 for (i = 0; i < 256; i++) {
4123 intel_crtc->lut_r[i] = red[i] >> 8;
4124 intel_crtc->lut_g[i] = green[i] >> 8;
4125 intel_crtc->lut_b[i] = blue[i] >> 8;
4126 }
4127
4128 intel_crtc_load_lut(crtc);
4129 }
4130
4131 /**
4132 * Get a pipe with a simple mode set on it for doing load-based monitor
4133 * detection.
4134 *
4135 * It will be up to the load-detect code to adjust the pipe as appropriate for
4136 * its requirements. The pipe will be connected to no other encoders.
4137 *
4138 * Currently this code will only succeed if there is a pipe with no encoders
4139 * configured for it. In the future, it could choose to temporarily disable
4140 * some outputs to free up a pipe for its use.
4141 *
4142 * \return crtc, or NULL if no pipes are available.
4143 */
4144
4145 /* VESA 640x480x72Hz mode to set on the pipe */
4146 static struct drm_display_mode load_detect_mode = {
4147 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4148 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4149 };
4150
4151 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4152 struct drm_connector *connector,
4153 struct drm_display_mode *mode,
4154 int *dpms_mode)
4155 {
4156 struct intel_crtc *intel_crtc;
4157 struct drm_crtc *possible_crtc;
4158 struct drm_crtc *supported_crtc =NULL;
4159 struct drm_encoder *encoder = &intel_encoder->enc;
4160 struct drm_crtc *crtc = NULL;
4161 struct drm_device *dev = encoder->dev;
4162 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4163 struct drm_crtc_helper_funcs *crtc_funcs;
4164 int i = -1;
4165
4166 /*
4167 * Algorithm gets a little messy:
4168 * - if the connector already has an assigned crtc, use it (but make
4169 * sure it's on first)
4170 * - try to find the first unused crtc that can drive this connector,
4171 * and use that if we find one
4172 * - if there are no unused crtcs available, try to use the first
4173 * one we found that supports the connector
4174 */
4175
4176 /* See if we already have a CRTC for this connector */
4177 if (encoder->crtc) {
4178 crtc = encoder->crtc;
4179 /* Make sure the crtc and connector are running */
4180 intel_crtc = to_intel_crtc(crtc);
4181 *dpms_mode = intel_crtc->dpms_mode;
4182 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4183 crtc_funcs = crtc->helper_private;
4184 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4185 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4186 }
4187 return crtc;
4188 }
4189
4190 /* Find an unused one (if possible) */
4191 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4192 i++;
4193 if (!(encoder->possible_crtcs & (1 << i)))
4194 continue;
4195 if (!possible_crtc->enabled) {
4196 crtc = possible_crtc;
4197 break;
4198 }
4199 if (!supported_crtc)
4200 supported_crtc = possible_crtc;
4201 }
4202
4203 /*
4204 * If we didn't find an unused CRTC, don't use any.
4205 */
4206 if (!crtc) {
4207 return NULL;
4208 }
4209
4210 encoder->crtc = crtc;
4211 connector->encoder = encoder;
4212 intel_encoder->load_detect_temp = true;
4213
4214 intel_crtc = to_intel_crtc(crtc);
4215 *dpms_mode = intel_crtc->dpms_mode;
4216
4217 if (!crtc->enabled) {
4218 if (!mode)
4219 mode = &load_detect_mode;
4220 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4221 } else {
4222 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4223 crtc_funcs = crtc->helper_private;
4224 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4225 }
4226
4227 /* Add this connector to the crtc */
4228 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4229 encoder_funcs->commit(encoder);
4230 }
4231 /* let the connector get through one full cycle before testing */
4232 intel_wait_for_vblank(dev);
4233
4234 return crtc;
4235 }
4236
4237 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4238 struct drm_connector *connector, int dpms_mode)
4239 {
4240 struct drm_encoder *encoder = &intel_encoder->enc;
4241 struct drm_device *dev = encoder->dev;
4242 struct drm_crtc *crtc = encoder->crtc;
4243 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4244 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4245
4246 if (intel_encoder->load_detect_temp) {
4247 encoder->crtc = NULL;
4248 connector->encoder = NULL;
4249 intel_encoder->load_detect_temp = false;
4250 crtc->enabled = drm_helper_crtc_in_use(crtc);
4251 drm_helper_disable_unused_functions(dev);
4252 }
4253
4254 /* Switch crtc and encoder back off if necessary */
4255 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4256 if (encoder->crtc == crtc)
4257 encoder_funcs->dpms(encoder, dpms_mode);
4258 crtc_funcs->dpms(crtc, dpms_mode);
4259 }
4260 }
4261
4262 /* Returns the clock of the currently programmed mode of the given pipe. */
4263 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4264 {
4265 struct drm_i915_private *dev_priv = dev->dev_private;
4266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4267 int pipe = intel_crtc->pipe;
4268 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4269 u32 fp;
4270 intel_clock_t clock;
4271
4272 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4273 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4274 else
4275 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4276
4277 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4278 if (IS_PINEVIEW(dev)) {
4279 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4280 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4281 } else {
4282 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4283 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4284 }
4285
4286 if (IS_I9XX(dev)) {
4287 if (IS_PINEVIEW(dev))
4288 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4289 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4290 else
4291 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4292 DPLL_FPA01_P1_POST_DIV_SHIFT);
4293
4294 switch (dpll & DPLL_MODE_MASK) {
4295 case DPLLB_MODE_DAC_SERIAL:
4296 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4297 5 : 10;
4298 break;
4299 case DPLLB_MODE_LVDS:
4300 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4301 7 : 14;
4302 break;
4303 default:
4304 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4305 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4306 return 0;
4307 }
4308
4309 /* XXX: Handle the 100Mhz refclk */
4310 intel_clock(dev, 96000, &clock);
4311 } else {
4312 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4313
4314 if (is_lvds) {
4315 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4316 DPLL_FPA01_P1_POST_DIV_SHIFT);
4317 clock.p2 = 14;
4318
4319 if ((dpll & PLL_REF_INPUT_MASK) ==
4320 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4321 /* XXX: might not be 66MHz */
4322 intel_clock(dev, 66000, &clock);
4323 } else
4324 intel_clock(dev, 48000, &clock);
4325 } else {
4326 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4327 clock.p1 = 2;
4328 else {
4329 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4330 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4331 }
4332 if (dpll & PLL_P2_DIVIDE_BY_4)
4333 clock.p2 = 4;
4334 else
4335 clock.p2 = 2;
4336
4337 intel_clock(dev, 48000, &clock);
4338 }
4339 }
4340
4341 /* XXX: It would be nice to validate the clocks, but we can't reuse
4342 * i830PllIsValid() because it relies on the xf86_config connector
4343 * configuration being accurate, which it isn't necessarily.
4344 */
4345
4346 return clock.dot;
4347 }
4348
4349 /** Returns the currently programmed mode of the given pipe. */
4350 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4351 struct drm_crtc *crtc)
4352 {
4353 struct drm_i915_private *dev_priv = dev->dev_private;
4354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4355 int pipe = intel_crtc->pipe;
4356 struct drm_display_mode *mode;
4357 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4358 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4359 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4360 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4361
4362 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4363 if (!mode)
4364 return NULL;
4365
4366 mode->clock = intel_crtc_clock_get(dev, crtc);
4367 mode->hdisplay = (htot & 0xffff) + 1;
4368 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4369 mode->hsync_start = (hsync & 0xffff) + 1;
4370 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4371 mode->vdisplay = (vtot & 0xffff) + 1;
4372 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4373 mode->vsync_start = (vsync & 0xffff) + 1;
4374 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4375
4376 drm_mode_set_name(mode);
4377 drm_mode_set_crtcinfo(mode, 0);
4378
4379 return mode;
4380 }
4381
4382 #define GPU_IDLE_TIMEOUT 500 /* ms */
4383
4384 /* When this timer fires, we've been idle for awhile */
4385 static void intel_gpu_idle_timer(unsigned long arg)
4386 {
4387 struct drm_device *dev = (struct drm_device *)arg;
4388 drm_i915_private_t *dev_priv = dev->dev_private;
4389
4390 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4391
4392 dev_priv->busy = false;
4393
4394 queue_work(dev_priv->wq, &dev_priv->idle_work);
4395 }
4396
4397 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4398
4399 static void intel_crtc_idle_timer(unsigned long arg)
4400 {
4401 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4402 struct drm_crtc *crtc = &intel_crtc->base;
4403 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4404
4405 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4406
4407 intel_crtc->busy = false;
4408
4409 queue_work(dev_priv->wq, &dev_priv->idle_work);
4410 }
4411
4412 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4413 {
4414 struct drm_device *dev = crtc->dev;
4415 drm_i915_private_t *dev_priv = dev->dev_private;
4416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4417 int pipe = intel_crtc->pipe;
4418 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4419 int dpll = I915_READ(dpll_reg);
4420
4421 if (HAS_PCH_SPLIT(dev))
4422 return;
4423
4424 if (!dev_priv->lvds_downclock_avail)
4425 return;
4426
4427 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4428 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4429
4430 /* Unlock panel regs */
4431 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4432 PANEL_UNLOCK_REGS);
4433
4434 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4435 I915_WRITE(dpll_reg, dpll);
4436 dpll = I915_READ(dpll_reg);
4437 intel_wait_for_vblank(dev);
4438 dpll = I915_READ(dpll_reg);
4439 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4440 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4441
4442 /* ...and lock them again */
4443 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4444 }
4445
4446 /* Schedule downclock */
4447 if (schedule)
4448 mod_timer(&intel_crtc->idle_timer, jiffies +
4449 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4450 }
4451
4452 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4453 {
4454 struct drm_device *dev = crtc->dev;
4455 drm_i915_private_t *dev_priv = dev->dev_private;
4456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4457 int pipe = intel_crtc->pipe;
4458 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4459 int dpll = I915_READ(dpll_reg);
4460
4461 if (HAS_PCH_SPLIT(dev))
4462 return;
4463
4464 if (!dev_priv->lvds_downclock_avail)
4465 return;
4466
4467 /*
4468 * Since this is called by a timer, we should never get here in
4469 * the manual case.
4470 */
4471 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4472 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4473
4474 /* Unlock panel regs */
4475 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4476 PANEL_UNLOCK_REGS);
4477
4478 dpll |= DISPLAY_RATE_SELECT_FPA1;
4479 I915_WRITE(dpll_reg, dpll);
4480 dpll = I915_READ(dpll_reg);
4481 intel_wait_for_vblank(dev);
4482 dpll = I915_READ(dpll_reg);
4483 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4484 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4485
4486 /* ...and lock them again */
4487 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4488 }
4489
4490 }
4491
4492 /**
4493 * intel_idle_update - adjust clocks for idleness
4494 * @work: work struct
4495 *
4496 * Either the GPU or display (or both) went idle. Check the busy status
4497 * here and adjust the CRTC and GPU clocks as necessary.
4498 */
4499 static void intel_idle_update(struct work_struct *work)
4500 {
4501 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4502 idle_work);
4503 struct drm_device *dev = dev_priv->dev;
4504 struct drm_crtc *crtc;
4505 struct intel_crtc *intel_crtc;
4506 int enabled = 0;
4507
4508 if (!i915_powersave)
4509 return;
4510
4511 mutex_lock(&dev->struct_mutex);
4512
4513 i915_update_gfx_val(dev_priv);
4514
4515 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4516 /* Skip inactive CRTCs */
4517 if (!crtc->fb)
4518 continue;
4519
4520 enabled++;
4521 intel_crtc = to_intel_crtc(crtc);
4522 if (!intel_crtc->busy)
4523 intel_decrease_pllclock(crtc);
4524 }
4525
4526 if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4527 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4528 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4529 }
4530
4531 mutex_unlock(&dev->struct_mutex);
4532 }
4533
4534 /**
4535 * intel_mark_busy - mark the GPU and possibly the display busy
4536 * @dev: drm device
4537 * @obj: object we're operating on
4538 *
4539 * Callers can use this function to indicate that the GPU is busy processing
4540 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4541 * buffer), we'll also mark the display as busy, so we know to increase its
4542 * clock frequency.
4543 */
4544 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4545 {
4546 drm_i915_private_t *dev_priv = dev->dev_private;
4547 struct drm_crtc *crtc = NULL;
4548 struct intel_framebuffer *intel_fb;
4549 struct intel_crtc *intel_crtc;
4550
4551 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4552 return;
4553
4554 if (!dev_priv->busy) {
4555 if (IS_I945G(dev) || IS_I945GM(dev)) {
4556 u32 fw_blc_self;
4557
4558 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4559 fw_blc_self = I915_READ(FW_BLC_SELF);
4560 fw_blc_self &= ~FW_BLC_SELF_EN;
4561 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4562 }
4563 dev_priv->busy = true;
4564 } else
4565 mod_timer(&dev_priv->idle_timer, jiffies +
4566 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4567
4568 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4569 if (!crtc->fb)
4570 continue;
4571
4572 intel_crtc = to_intel_crtc(crtc);
4573 intel_fb = to_intel_framebuffer(crtc->fb);
4574 if (intel_fb->obj == obj) {
4575 if (!intel_crtc->busy) {
4576 if (IS_I945G(dev) || IS_I945GM(dev)) {
4577 u32 fw_blc_self;
4578
4579 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4580 fw_blc_self = I915_READ(FW_BLC_SELF);
4581 fw_blc_self &= ~FW_BLC_SELF_EN;
4582 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4583 }
4584 /* Non-busy -> busy, upclock */
4585 intel_increase_pllclock(crtc, true);
4586 intel_crtc->busy = true;
4587 } else {
4588 /* Busy -> busy, put off timer */
4589 mod_timer(&intel_crtc->idle_timer, jiffies +
4590 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4591 }
4592 }
4593 }
4594 }
4595
4596 static void intel_crtc_destroy(struct drm_crtc *crtc)
4597 {
4598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4599
4600 drm_crtc_cleanup(crtc);
4601 kfree(intel_crtc);
4602 }
4603
4604 struct intel_unpin_work {
4605 struct work_struct work;
4606 struct drm_device *dev;
4607 struct drm_gem_object *old_fb_obj;
4608 struct drm_gem_object *pending_flip_obj;
4609 struct drm_pending_vblank_event *event;
4610 int pending;
4611 };
4612
4613 static void intel_unpin_work_fn(struct work_struct *__work)
4614 {
4615 struct intel_unpin_work *work =
4616 container_of(__work, struct intel_unpin_work, work);
4617
4618 mutex_lock(&work->dev->struct_mutex);
4619 i915_gem_object_unpin(work->old_fb_obj);
4620 drm_gem_object_unreference(work->pending_flip_obj);
4621 drm_gem_object_unreference(work->old_fb_obj);
4622 mutex_unlock(&work->dev->struct_mutex);
4623 kfree(work);
4624 }
4625
4626 static void do_intel_finish_page_flip(struct drm_device *dev,
4627 struct drm_crtc *crtc)
4628 {
4629 drm_i915_private_t *dev_priv = dev->dev_private;
4630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4631 struct intel_unpin_work *work;
4632 struct drm_i915_gem_object *obj_priv;
4633 struct drm_pending_vblank_event *e;
4634 struct timeval now;
4635 unsigned long flags;
4636
4637 /* Ignore early vblank irqs */
4638 if (intel_crtc == NULL)
4639 return;
4640
4641 spin_lock_irqsave(&dev->event_lock, flags);
4642 work = intel_crtc->unpin_work;
4643 if (work == NULL || !work->pending) {
4644 spin_unlock_irqrestore(&dev->event_lock, flags);
4645 return;
4646 }
4647
4648 intel_crtc->unpin_work = NULL;
4649 drm_vblank_put(dev, intel_crtc->pipe);
4650
4651 if (work->event) {
4652 e = work->event;
4653 do_gettimeofday(&now);
4654 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4655 e->event.tv_sec = now.tv_sec;
4656 e->event.tv_usec = now.tv_usec;
4657 list_add_tail(&e->base.link,
4658 &e->base.file_priv->event_list);
4659 wake_up_interruptible(&e->base.file_priv->event_wait);
4660 }
4661
4662 spin_unlock_irqrestore(&dev->event_lock, flags);
4663
4664 obj_priv = to_intel_bo(work->pending_flip_obj);
4665
4666 /* Initial scanout buffer will have a 0 pending flip count */
4667 if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4668 atomic_dec_and_test(&obj_priv->pending_flip))
4669 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4670 schedule_work(&work->work);
4671 }
4672
4673 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4674 {
4675 drm_i915_private_t *dev_priv = dev->dev_private;
4676 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4677
4678 do_intel_finish_page_flip(dev, crtc);
4679 }
4680
4681 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
4682 {
4683 drm_i915_private_t *dev_priv = dev->dev_private;
4684 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
4685
4686 do_intel_finish_page_flip(dev, crtc);
4687 }
4688
4689 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4690 {
4691 drm_i915_private_t *dev_priv = dev->dev_private;
4692 struct intel_crtc *intel_crtc =
4693 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4694 unsigned long flags;
4695
4696 spin_lock_irqsave(&dev->event_lock, flags);
4697 if (intel_crtc->unpin_work) {
4698 intel_crtc->unpin_work->pending = 1;
4699 } else {
4700 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4701 }
4702 spin_unlock_irqrestore(&dev->event_lock, flags);
4703 }
4704
4705 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4706 struct drm_framebuffer *fb,
4707 struct drm_pending_vblank_event *event)
4708 {
4709 struct drm_device *dev = crtc->dev;
4710 struct drm_i915_private *dev_priv = dev->dev_private;
4711 struct intel_framebuffer *intel_fb;
4712 struct drm_i915_gem_object *obj_priv;
4713 struct drm_gem_object *obj;
4714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4715 struct intel_unpin_work *work;
4716 unsigned long flags, offset;
4717 int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
4718 int ret, pipesrc;
4719 u32 flip_mask;
4720
4721 work = kzalloc(sizeof *work, GFP_KERNEL);
4722 if (work == NULL)
4723 return -ENOMEM;
4724
4725 work->event = event;
4726 work->dev = crtc->dev;
4727 intel_fb = to_intel_framebuffer(crtc->fb);
4728 work->old_fb_obj = intel_fb->obj;
4729 INIT_WORK(&work->work, intel_unpin_work_fn);
4730
4731 /* We borrow the event spin lock for protecting unpin_work */
4732 spin_lock_irqsave(&dev->event_lock, flags);
4733 if (intel_crtc->unpin_work) {
4734 spin_unlock_irqrestore(&dev->event_lock, flags);
4735 kfree(work);
4736
4737 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4738 return -EBUSY;
4739 }
4740 intel_crtc->unpin_work = work;
4741 spin_unlock_irqrestore(&dev->event_lock, flags);
4742
4743 intel_fb = to_intel_framebuffer(fb);
4744 obj = intel_fb->obj;
4745
4746 mutex_lock(&dev->struct_mutex);
4747 ret = intel_pin_and_fence_fb_obj(dev, obj);
4748 if (ret != 0) {
4749 mutex_unlock(&dev->struct_mutex);
4750
4751 spin_lock_irqsave(&dev->event_lock, flags);
4752 intel_crtc->unpin_work = NULL;
4753 spin_unlock_irqrestore(&dev->event_lock, flags);
4754
4755 kfree(work);
4756
4757 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4758 to_intel_bo(obj));
4759 return ret;
4760 }
4761
4762 /* Reference the objects for the scheduled work. */
4763 drm_gem_object_reference(work->old_fb_obj);
4764 drm_gem_object_reference(obj);
4765
4766 crtc->fb = fb;
4767 i915_gem_object_flush_write_domain(obj);
4768 drm_vblank_get(dev, intel_crtc->pipe);
4769 obj_priv = to_intel_bo(obj);
4770 atomic_inc(&obj_priv->pending_flip);
4771 work->pending_flip_obj = obj;
4772
4773 if (intel_crtc->plane)
4774 flip_mask = I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4775 else
4776 flip_mask = I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
4777
4778 /* Wait for any previous flip to finish */
4779 if (IS_GEN3(dev))
4780 while (I915_READ(ISR) & flip_mask)
4781 ;
4782
4783 /* Offset into the new buffer for cases of shared fbs between CRTCs */
4784 offset = obj_priv->gtt_offset;
4785 offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
4786
4787 BEGIN_LP_RING(4);
4788 if (IS_I965G(dev)) {
4789 OUT_RING(MI_DISPLAY_FLIP |
4790 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4791 OUT_RING(fb->pitch);
4792 OUT_RING(offset | obj_priv->tiling_mode);
4793 pipesrc = I915_READ(pipesrc_reg);
4794 OUT_RING(pipesrc & 0x0fff0fff);
4795 } else {
4796 OUT_RING(MI_DISPLAY_FLIP_I915 |
4797 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4798 OUT_RING(fb->pitch);
4799 OUT_RING(offset);
4800 OUT_RING(MI_NOOP);
4801 }
4802 ADVANCE_LP_RING();
4803
4804 mutex_unlock(&dev->struct_mutex);
4805
4806 return 0;
4807 }
4808
4809 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4810 .dpms = intel_crtc_dpms,
4811 .mode_fixup = intel_crtc_mode_fixup,
4812 .mode_set = intel_crtc_mode_set,
4813 .mode_set_base = intel_pipe_set_base,
4814 .prepare = intel_crtc_prepare,
4815 .commit = intel_crtc_commit,
4816 .load_lut = intel_crtc_load_lut,
4817 };
4818
4819 static const struct drm_crtc_funcs intel_crtc_funcs = {
4820 .cursor_set = intel_crtc_cursor_set,
4821 .cursor_move = intel_crtc_cursor_move,
4822 .gamma_set = intel_crtc_gamma_set,
4823 .set_config = drm_crtc_helper_set_config,
4824 .destroy = intel_crtc_destroy,
4825 .page_flip = intel_crtc_page_flip,
4826 };
4827
4828
4829 static void intel_crtc_init(struct drm_device *dev, int pipe)
4830 {
4831 drm_i915_private_t *dev_priv = dev->dev_private;
4832 struct intel_crtc *intel_crtc;
4833 int i;
4834
4835 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4836 if (intel_crtc == NULL)
4837 return;
4838
4839 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4840
4841 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4842 intel_crtc->pipe = pipe;
4843 intel_crtc->plane = pipe;
4844 for (i = 0; i < 256; i++) {
4845 intel_crtc->lut_r[i] = i;
4846 intel_crtc->lut_g[i] = i;
4847 intel_crtc->lut_b[i] = i;
4848 }
4849
4850 /* Swap pipes & planes for FBC on pre-965 */
4851 intel_crtc->pipe = pipe;
4852 intel_crtc->plane = pipe;
4853 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4854 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4855 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4856 }
4857
4858 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
4859 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
4860 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
4861 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
4862
4863 intel_crtc->cursor_addr = 0;
4864 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4865 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4866
4867 intel_crtc->busy = false;
4868
4869 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4870 (unsigned long)intel_crtc);
4871 }
4872
4873 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4874 struct drm_file *file_priv)
4875 {
4876 drm_i915_private_t *dev_priv = dev->dev_private;
4877 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4878 struct drm_mode_object *drmmode_obj;
4879 struct intel_crtc *crtc;
4880
4881 if (!dev_priv) {
4882 DRM_ERROR("called with no initialization\n");
4883 return -EINVAL;
4884 }
4885
4886 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4887 DRM_MODE_OBJECT_CRTC);
4888
4889 if (!drmmode_obj) {
4890 DRM_ERROR("no such CRTC id\n");
4891 return -EINVAL;
4892 }
4893
4894 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4895 pipe_from_crtc_id->pipe = crtc->pipe;
4896
4897 return 0;
4898 }
4899
4900 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4901 {
4902 struct drm_crtc *crtc = NULL;
4903
4904 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4906 if (intel_crtc->pipe == pipe)
4907 break;
4908 }
4909 return crtc;
4910 }
4911
4912 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
4913 {
4914 int index_mask = 0;
4915 struct drm_encoder *encoder;
4916 int entry = 0;
4917
4918 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4919 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
4920 if (type_mask & intel_encoder->clone_mask)
4921 index_mask |= (1 << entry);
4922 entry++;
4923 }
4924 return index_mask;
4925 }
4926
4927
4928 static void intel_setup_outputs(struct drm_device *dev)
4929 {
4930 struct drm_i915_private *dev_priv = dev->dev_private;
4931 struct drm_encoder *encoder;
4932
4933 intel_crt_init(dev);
4934
4935 /* Set up integrated LVDS */
4936 if (IS_MOBILE(dev) && !IS_I830(dev))
4937 intel_lvds_init(dev);
4938
4939 if (HAS_PCH_SPLIT(dev)) {
4940 int found;
4941
4942 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4943 intel_dp_init(dev, DP_A);
4944
4945 if (I915_READ(HDMIB) & PORT_DETECTED) {
4946 /* PCH SDVOB multiplex with HDMIB */
4947 found = intel_sdvo_init(dev, PCH_SDVOB);
4948 if (!found)
4949 intel_hdmi_init(dev, HDMIB);
4950 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4951 intel_dp_init(dev, PCH_DP_B);
4952 }
4953
4954 if (I915_READ(HDMIC) & PORT_DETECTED)
4955 intel_hdmi_init(dev, HDMIC);
4956
4957 if (I915_READ(HDMID) & PORT_DETECTED)
4958 intel_hdmi_init(dev, HDMID);
4959
4960 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4961 intel_dp_init(dev, PCH_DP_C);
4962
4963 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4964 intel_dp_init(dev, PCH_DP_D);
4965
4966 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
4967 bool found = false;
4968
4969 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4970 DRM_DEBUG_KMS("probing SDVOB\n");
4971 found = intel_sdvo_init(dev, SDVOB);
4972 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
4973 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4974 intel_hdmi_init(dev, SDVOB);
4975 }
4976
4977 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
4978 DRM_DEBUG_KMS("probing DP_B\n");
4979 intel_dp_init(dev, DP_B);
4980 }
4981 }
4982
4983 /* Before G4X SDVOC doesn't have its own detect register */
4984
4985 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4986 DRM_DEBUG_KMS("probing SDVOC\n");
4987 found = intel_sdvo_init(dev, SDVOC);
4988 }
4989
4990 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4991
4992 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
4993 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4994 intel_hdmi_init(dev, SDVOC);
4995 }
4996 if (SUPPORTS_INTEGRATED_DP(dev)) {
4997 DRM_DEBUG_KMS("probing DP_C\n");
4998 intel_dp_init(dev, DP_C);
4999 }
5000 }
5001
5002 if (SUPPORTS_INTEGRATED_DP(dev) &&
5003 (I915_READ(DP_D) & DP_DETECTED)) {
5004 DRM_DEBUG_KMS("probing DP_D\n");
5005 intel_dp_init(dev, DP_D);
5006 }
5007 } else if (IS_GEN2(dev))
5008 intel_dvo_init(dev);
5009
5010 if (SUPPORTS_TV(dev))
5011 intel_tv_init(dev);
5012
5013 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5014 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5015
5016 encoder->possible_crtcs = intel_encoder->crtc_mask;
5017 encoder->possible_clones = intel_encoder_clones(dev,
5018 intel_encoder->clone_mask);
5019 }
5020 }
5021
5022 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5023 {
5024 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5025
5026 drm_framebuffer_cleanup(fb);
5027 drm_gem_object_unreference_unlocked(intel_fb->obj);
5028
5029 kfree(intel_fb);
5030 }
5031
5032 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5033 struct drm_file *file_priv,
5034 unsigned int *handle)
5035 {
5036 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5037 struct drm_gem_object *object = intel_fb->obj;
5038
5039 return drm_gem_handle_create(file_priv, object, handle);
5040 }
5041
5042 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5043 .destroy = intel_user_framebuffer_destroy,
5044 .create_handle = intel_user_framebuffer_create_handle,
5045 };
5046
5047 int intel_framebuffer_init(struct drm_device *dev,
5048 struct intel_framebuffer *intel_fb,
5049 struct drm_mode_fb_cmd *mode_cmd,
5050 struct drm_gem_object *obj)
5051 {
5052 int ret;
5053
5054 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5055 if (ret) {
5056 DRM_ERROR("framebuffer init failed %d\n", ret);
5057 return ret;
5058 }
5059
5060 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5061 intel_fb->obj = obj;
5062 return 0;
5063 }
5064
5065 static struct drm_framebuffer *
5066 intel_user_framebuffer_create(struct drm_device *dev,
5067 struct drm_file *filp,
5068 struct drm_mode_fb_cmd *mode_cmd)
5069 {
5070 struct drm_gem_object *obj;
5071 struct intel_framebuffer *intel_fb;
5072 int ret;
5073
5074 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5075 if (!obj)
5076 return NULL;
5077
5078 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5079 if (!intel_fb)
5080 return NULL;
5081
5082 ret = intel_framebuffer_init(dev, intel_fb,
5083 mode_cmd, obj);
5084 if (ret) {
5085 drm_gem_object_unreference_unlocked(obj);
5086 kfree(intel_fb);
5087 return NULL;
5088 }
5089
5090 return &intel_fb->base;
5091 }
5092
5093 static const struct drm_mode_config_funcs intel_mode_funcs = {
5094 .fb_create = intel_user_framebuffer_create,
5095 .output_poll_changed = intel_fb_output_poll_changed,
5096 };
5097
5098 static struct drm_gem_object *
5099 intel_alloc_power_context(struct drm_device *dev)
5100 {
5101 struct drm_gem_object *pwrctx;
5102 int ret;
5103
5104 pwrctx = i915_gem_alloc_object(dev, 4096);
5105 if (!pwrctx) {
5106 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5107 return NULL;
5108 }
5109
5110 mutex_lock(&dev->struct_mutex);
5111 ret = i915_gem_object_pin(pwrctx, 4096);
5112 if (ret) {
5113 DRM_ERROR("failed to pin power context: %d\n", ret);
5114 goto err_unref;
5115 }
5116
5117 ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
5118 if (ret) {
5119 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5120 goto err_unpin;
5121 }
5122 mutex_unlock(&dev->struct_mutex);
5123
5124 return pwrctx;
5125
5126 err_unpin:
5127 i915_gem_object_unpin(pwrctx);
5128 err_unref:
5129 drm_gem_object_unreference(pwrctx);
5130 mutex_unlock(&dev->struct_mutex);
5131 return NULL;
5132 }
5133
5134 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5135 {
5136 struct drm_i915_private *dev_priv = dev->dev_private;
5137 u16 rgvswctl;
5138
5139 rgvswctl = I915_READ16(MEMSWCTL);
5140 if (rgvswctl & MEMCTL_CMD_STS) {
5141 DRM_DEBUG("gpu busy, RCS change rejected\n");
5142 return false; /* still busy with another command */
5143 }
5144
5145 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5146 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5147 I915_WRITE16(MEMSWCTL, rgvswctl);
5148 POSTING_READ16(MEMSWCTL);
5149
5150 rgvswctl |= MEMCTL_CMD_STS;
5151 I915_WRITE16(MEMSWCTL, rgvswctl);
5152
5153 return true;
5154 }
5155
5156 void ironlake_enable_drps(struct drm_device *dev)
5157 {
5158 struct drm_i915_private *dev_priv = dev->dev_private;
5159 u32 rgvmodectl = I915_READ(MEMMODECTL);
5160 u8 fmax, fmin, fstart, vstart;
5161 int i = 0;
5162
5163 /* 100ms RC evaluation intervals */
5164 I915_WRITE(RCUPEI, 100000);
5165 I915_WRITE(RCDNEI, 100000);
5166
5167 /* Set max/min thresholds to 90ms and 80ms respectively */
5168 I915_WRITE(RCBMAXAVG, 90000);
5169 I915_WRITE(RCBMINAVG, 80000);
5170
5171 I915_WRITE(MEMIHYST, 1);
5172
5173 /* Set up min, max, and cur for interrupt handling */
5174 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5175 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5176 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5177 MEMMODE_FSTART_SHIFT;
5178 fstart = fmax;
5179
5180 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5181 PXVFREQ_PX_SHIFT;
5182
5183 dev_priv->fmax = fstart; /* IPS callback will increase this */
5184 dev_priv->fstart = fstart;
5185
5186 dev_priv->max_delay = fmax;
5187 dev_priv->min_delay = fmin;
5188 dev_priv->cur_delay = fstart;
5189
5190 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5191 fstart);
5192
5193 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5194
5195 /*
5196 * Interrupts will be enabled in ironlake_irq_postinstall
5197 */
5198
5199 I915_WRITE(VIDSTART, vstart);
5200 POSTING_READ(VIDSTART);
5201
5202 rgvmodectl |= MEMMODE_SWMODE_EN;
5203 I915_WRITE(MEMMODECTL, rgvmodectl);
5204
5205 while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
5206 if (i++ > 100) {
5207 DRM_ERROR("stuck trying to change perf mode\n");
5208 break;
5209 }
5210 msleep(1);
5211 }
5212 msleep(1);
5213
5214 ironlake_set_drps(dev, fstart);
5215
5216 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5217 I915_READ(0x112e0);
5218 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5219 dev_priv->last_count2 = I915_READ(0x112f4);
5220 getrawmonotonic(&dev_priv->last_time2);
5221 }
5222
5223 void ironlake_disable_drps(struct drm_device *dev)
5224 {
5225 struct drm_i915_private *dev_priv = dev->dev_private;
5226 u16 rgvswctl = I915_READ16(MEMSWCTL);
5227
5228 /* Ack interrupts, disable EFC interrupt */
5229 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5230 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5231 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5232 I915_WRITE(DEIIR, DE_PCU_EVENT);
5233 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5234
5235 /* Go back to the starting frequency */
5236 ironlake_set_drps(dev, dev_priv->fstart);
5237 msleep(1);
5238 rgvswctl |= MEMCTL_CMD_STS;
5239 I915_WRITE(MEMSWCTL, rgvswctl);
5240 msleep(1);
5241
5242 }
5243
5244 static unsigned long intel_pxfreq(u32 vidfreq)
5245 {
5246 unsigned long freq;
5247 int div = (vidfreq & 0x3f0000) >> 16;
5248 int post = (vidfreq & 0x3000) >> 12;
5249 int pre = (vidfreq & 0x7);
5250
5251 if (!pre)
5252 return 0;
5253
5254 freq = ((div * 133333) / ((1<<post) * pre));
5255
5256 return freq;
5257 }
5258
5259 void intel_init_emon(struct drm_device *dev)
5260 {
5261 struct drm_i915_private *dev_priv = dev->dev_private;
5262 u32 lcfuse;
5263 u8 pxw[16];
5264 int i;
5265
5266 /* Disable to program */
5267 I915_WRITE(ECR, 0);
5268 POSTING_READ(ECR);
5269
5270 /* Program energy weights for various events */
5271 I915_WRITE(SDEW, 0x15040d00);
5272 I915_WRITE(CSIEW0, 0x007f0000);
5273 I915_WRITE(CSIEW1, 0x1e220004);
5274 I915_WRITE(CSIEW2, 0x04000004);
5275
5276 for (i = 0; i < 5; i++)
5277 I915_WRITE(PEW + (i * 4), 0);
5278 for (i = 0; i < 3; i++)
5279 I915_WRITE(DEW + (i * 4), 0);
5280
5281 /* Program P-state weights to account for frequency power adjustment */
5282 for (i = 0; i < 16; i++) {
5283 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5284 unsigned long freq = intel_pxfreq(pxvidfreq);
5285 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5286 PXVFREQ_PX_SHIFT;
5287 unsigned long val;
5288
5289 val = vid * vid;
5290 val *= (freq / 1000);
5291 val *= 255;
5292 val /= (127*127*900);
5293 if (val > 0xff)
5294 DRM_ERROR("bad pxval: %ld\n", val);
5295 pxw[i] = val;
5296 }
5297 /* Render standby states get 0 weight */
5298 pxw[14] = 0;
5299 pxw[15] = 0;
5300
5301 for (i = 0; i < 4; i++) {
5302 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5303 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5304 I915_WRITE(PXW + (i * 4), val);
5305 }
5306
5307 /* Adjust magic regs to magic values (more experimental results) */
5308 I915_WRITE(OGW0, 0);
5309 I915_WRITE(OGW1, 0);
5310 I915_WRITE(EG0, 0x00007f00);
5311 I915_WRITE(EG1, 0x0000000e);
5312 I915_WRITE(EG2, 0x000e0000);
5313 I915_WRITE(EG3, 0x68000300);
5314 I915_WRITE(EG4, 0x42000000);
5315 I915_WRITE(EG5, 0x00140031);
5316 I915_WRITE(EG6, 0);
5317 I915_WRITE(EG7, 0);
5318
5319 for (i = 0; i < 8; i++)
5320 I915_WRITE(PXWL + (i * 4), 0);
5321
5322 /* Enable PMON + select events */
5323 I915_WRITE(ECR, 0x80000019);
5324
5325 lcfuse = I915_READ(LCFUSE02);
5326
5327 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5328 }
5329
5330 void intel_init_clock_gating(struct drm_device *dev)
5331 {
5332 struct drm_i915_private *dev_priv = dev->dev_private;
5333
5334 /*
5335 * Disable clock gating reported to work incorrectly according to the
5336 * specs, but enable as much else as we can.
5337 */
5338 if (HAS_PCH_SPLIT(dev)) {
5339 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5340
5341 if (IS_IRONLAKE(dev)) {
5342 /* Required for FBC */
5343 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5344 /* Required for CxSR */
5345 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5346
5347 I915_WRITE(PCH_3DCGDIS0,
5348 MARIUNIT_CLOCK_GATE_DISABLE |
5349 SVSMUNIT_CLOCK_GATE_DISABLE);
5350 }
5351
5352 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5353
5354 /*
5355 * According to the spec the following bits should be set in
5356 * order to enable memory self-refresh
5357 * The bit 22/21 of 0x42004
5358 * The bit 5 of 0x42020
5359 * The bit 15 of 0x45000
5360 */
5361 if (IS_IRONLAKE(dev)) {
5362 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5363 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5364 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5365 I915_WRITE(ILK_DSPCLK_GATE,
5366 (I915_READ(ILK_DSPCLK_GATE) |
5367 ILK_DPARB_CLK_GATE));
5368 I915_WRITE(DISP_ARB_CTL,
5369 (I915_READ(DISP_ARB_CTL) |
5370 DISP_FBC_WM_DIS));
5371 }
5372 return;
5373 } else if (IS_G4X(dev)) {
5374 uint32_t dspclk_gate;
5375 I915_WRITE(RENCLK_GATE_D1, 0);
5376 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5377 GS_UNIT_CLOCK_GATE_DISABLE |
5378 CL_UNIT_CLOCK_GATE_DISABLE);
5379 I915_WRITE(RAMCLK_GATE_D, 0);
5380 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5381 OVRUNIT_CLOCK_GATE_DISABLE |
5382 OVCUNIT_CLOCK_GATE_DISABLE;
5383 if (IS_GM45(dev))
5384 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5385 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5386 } else if (IS_I965GM(dev)) {
5387 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5388 I915_WRITE(RENCLK_GATE_D2, 0);
5389 I915_WRITE(DSPCLK_GATE_D, 0);
5390 I915_WRITE(RAMCLK_GATE_D, 0);
5391 I915_WRITE16(DEUC, 0);
5392 } else if (IS_I965G(dev)) {
5393 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5394 I965_RCC_CLOCK_GATE_DISABLE |
5395 I965_RCPB_CLOCK_GATE_DISABLE |
5396 I965_ISC_CLOCK_GATE_DISABLE |
5397 I965_FBC_CLOCK_GATE_DISABLE);
5398 I915_WRITE(RENCLK_GATE_D2, 0);
5399 } else if (IS_I9XX(dev)) {
5400 u32 dstate = I915_READ(D_STATE);
5401
5402 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5403 DSTATE_DOT_CLOCK_GATING;
5404 I915_WRITE(D_STATE, dstate);
5405 } else if (IS_I85X(dev) || IS_I865G(dev)) {
5406 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5407 } else if (IS_I830(dev)) {
5408 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5409 }
5410
5411 /*
5412 * GPU can automatically power down the render unit if given a page
5413 * to save state.
5414 */
5415 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5416 struct drm_i915_gem_object *obj_priv = NULL;
5417
5418 if (dev_priv->pwrctx) {
5419 obj_priv = to_intel_bo(dev_priv->pwrctx);
5420 } else {
5421 struct drm_gem_object *pwrctx;
5422
5423 pwrctx = intel_alloc_power_context(dev);
5424 if (pwrctx) {
5425 dev_priv->pwrctx = pwrctx;
5426 obj_priv = to_intel_bo(pwrctx);
5427 }
5428 }
5429
5430 if (obj_priv) {
5431 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5432 I915_WRITE(MCHBAR_RENDER_STANDBY,
5433 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5434 }
5435 }
5436 }
5437
5438 /* Set up chip specific display functions */
5439 static void intel_init_display(struct drm_device *dev)
5440 {
5441 struct drm_i915_private *dev_priv = dev->dev_private;
5442
5443 /* We always want a DPMS function */
5444 if (HAS_PCH_SPLIT(dev))
5445 dev_priv->display.dpms = ironlake_crtc_dpms;
5446 else
5447 dev_priv->display.dpms = i9xx_crtc_dpms;
5448
5449 if (I915_HAS_FBC(dev)) {
5450 if (IS_GM45(dev)) {
5451 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5452 dev_priv->display.enable_fbc = g4x_enable_fbc;
5453 dev_priv->display.disable_fbc = g4x_disable_fbc;
5454 } else if (IS_I965GM(dev)) {
5455 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5456 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5457 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5458 }
5459 /* 855GM needs testing */
5460 }
5461
5462 /* Returns the core display clock speed */
5463 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5464 dev_priv->display.get_display_clock_speed =
5465 i945_get_display_clock_speed;
5466 else if (IS_I915G(dev))
5467 dev_priv->display.get_display_clock_speed =
5468 i915_get_display_clock_speed;
5469 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5470 dev_priv->display.get_display_clock_speed =
5471 i9xx_misc_get_display_clock_speed;
5472 else if (IS_I915GM(dev))
5473 dev_priv->display.get_display_clock_speed =
5474 i915gm_get_display_clock_speed;
5475 else if (IS_I865G(dev))
5476 dev_priv->display.get_display_clock_speed =
5477 i865_get_display_clock_speed;
5478 else if (IS_I85X(dev))
5479 dev_priv->display.get_display_clock_speed =
5480 i855_get_display_clock_speed;
5481 else /* 852, 830 */
5482 dev_priv->display.get_display_clock_speed =
5483 i830_get_display_clock_speed;
5484
5485 /* For FIFO watermark updates */
5486 if (HAS_PCH_SPLIT(dev)) {
5487 if (IS_IRONLAKE(dev)) {
5488 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5489 dev_priv->display.update_wm = ironlake_update_wm;
5490 else {
5491 DRM_DEBUG_KMS("Failed to get proper latency. "
5492 "Disable CxSR\n");
5493 dev_priv->display.update_wm = NULL;
5494 }
5495 } else
5496 dev_priv->display.update_wm = NULL;
5497 } else if (IS_PINEVIEW(dev)) {
5498 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5499 dev_priv->is_ddr3,
5500 dev_priv->fsb_freq,
5501 dev_priv->mem_freq)) {
5502 DRM_INFO("failed to find known CxSR latency "
5503 "(found ddr%s fsb freq %d, mem freq %d), "
5504 "disabling CxSR\n",
5505 (dev_priv->is_ddr3 == 1) ? "3": "2",
5506 dev_priv->fsb_freq, dev_priv->mem_freq);
5507 /* Disable CxSR and never update its watermark again */
5508 pineview_disable_cxsr(dev);
5509 dev_priv->display.update_wm = NULL;
5510 } else
5511 dev_priv->display.update_wm = pineview_update_wm;
5512 } else if (IS_G4X(dev))
5513 dev_priv->display.update_wm = g4x_update_wm;
5514 else if (IS_I965G(dev))
5515 dev_priv->display.update_wm = i965_update_wm;
5516 else if (IS_I9XX(dev)) {
5517 dev_priv->display.update_wm = i9xx_update_wm;
5518 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5519 } else if (IS_I85X(dev)) {
5520 dev_priv->display.update_wm = i9xx_update_wm;
5521 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5522 } else {
5523 dev_priv->display.update_wm = i830_update_wm;
5524 if (IS_845G(dev))
5525 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5526 else
5527 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5528 }
5529 }
5530
5531 void intel_modeset_init(struct drm_device *dev)
5532 {
5533 struct drm_i915_private *dev_priv = dev->dev_private;
5534 int i;
5535
5536 drm_mode_config_init(dev);
5537
5538 dev->mode_config.min_width = 0;
5539 dev->mode_config.min_height = 0;
5540
5541 dev->mode_config.funcs = (void *)&intel_mode_funcs;
5542
5543 intel_init_display(dev);
5544
5545 if (IS_I965G(dev)) {
5546 dev->mode_config.max_width = 8192;
5547 dev->mode_config.max_height = 8192;
5548 } else if (IS_I9XX(dev)) {
5549 dev->mode_config.max_width = 4096;
5550 dev->mode_config.max_height = 4096;
5551 } else {
5552 dev->mode_config.max_width = 2048;
5553 dev->mode_config.max_height = 2048;
5554 }
5555
5556 /* set memory base */
5557 if (IS_I9XX(dev))
5558 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
5559 else
5560 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
5561
5562 if (IS_MOBILE(dev) || IS_I9XX(dev))
5563 dev_priv->num_pipe = 2;
5564 else
5565 dev_priv->num_pipe = 1;
5566 DRM_DEBUG_KMS("%d display pipe%s available.\n",
5567 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
5568
5569 for (i = 0; i < dev_priv->num_pipe; i++) {
5570 intel_crtc_init(dev, i);
5571 }
5572
5573 intel_setup_outputs(dev);
5574
5575 intel_init_clock_gating(dev);
5576
5577 if (IS_IRONLAKE_M(dev)) {
5578 ironlake_enable_drps(dev);
5579 intel_init_emon(dev);
5580 }
5581
5582 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
5583 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
5584 (unsigned long)dev);
5585
5586 intel_setup_overlay(dev);
5587 }
5588
5589 void intel_modeset_cleanup(struct drm_device *dev)
5590 {
5591 struct drm_i915_private *dev_priv = dev->dev_private;
5592 struct drm_crtc *crtc;
5593 struct intel_crtc *intel_crtc;
5594
5595 mutex_lock(&dev->struct_mutex);
5596
5597 drm_kms_helper_poll_fini(dev);
5598 intel_fbdev_fini(dev);
5599
5600 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5601 /* Skip inactive CRTCs */
5602 if (!crtc->fb)
5603 continue;
5604
5605 intel_crtc = to_intel_crtc(crtc);
5606 intel_increase_pllclock(crtc, false);
5607 del_timer_sync(&intel_crtc->idle_timer);
5608 }
5609
5610 del_timer_sync(&dev_priv->idle_timer);
5611
5612 if (dev_priv->display.disable_fbc)
5613 dev_priv->display.disable_fbc(dev);
5614
5615 if (dev_priv->pwrctx) {
5616 struct drm_i915_gem_object *obj_priv;
5617
5618 obj_priv = to_intel_bo(dev_priv->pwrctx);
5619 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
5620 I915_READ(PWRCTXA);
5621 i915_gem_object_unpin(dev_priv->pwrctx);
5622 drm_gem_object_unreference(dev_priv->pwrctx);
5623 }
5624
5625 if (IS_IRONLAKE_M(dev))
5626 ironlake_disable_drps(dev);
5627
5628 mutex_unlock(&dev->struct_mutex);
5629
5630 drm_mode_config_cleanup(dev);
5631 }
5632
5633
5634 /*
5635 * Return which encoder is currently attached for connector.
5636 */
5637 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
5638 {
5639 struct drm_mode_object *obj;
5640 struct drm_encoder *encoder;
5641 int i;
5642
5643 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
5644 if (connector->encoder_ids[i] == 0)
5645 break;
5646
5647 obj = drm_mode_object_find(connector->dev,
5648 connector->encoder_ids[i],
5649 DRM_MODE_OBJECT_ENCODER);
5650 if (!obj)
5651 continue;
5652
5653 encoder = obj_to_encoder(obj);
5654 return encoder;
5655 }
5656 return NULL;
5657 }
5658
5659 /*
5660 * set vga decode state - true == enable VGA decode
5661 */
5662 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
5663 {
5664 struct drm_i915_private *dev_priv = dev->dev_private;
5665 u16 gmch_ctrl;
5666
5667 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
5668 if (state)
5669 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
5670 else
5671 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
5672 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
5673 return 0;
5674 }
Linux kernel - Deliverables
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